dp_tx.c 86 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /* invalid peer id for reinject*/
  51. #define DP_INVALID_PEER 0XFFFE
  52. /*mapping between hal encrypt type and cdp_sec_type*/
  53. #define MAX_CDP_SEC_TYPE 12
  54. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  55. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  56. HAL_TX_ENCRYPT_TYPE_WEP_128,
  57. HAL_TX_ENCRYPT_TYPE_WEP_104,
  58. HAL_TX_ENCRYPT_TYPE_WEP_40,
  59. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  61. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_WAPI,
  63. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  64. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  66. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  67. /**
  68. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  69. * @vdev: DP Virtual device handle
  70. * @nbuf: Buffer pointer
  71. * @queue: queue ids container for nbuf
  72. *
  73. * TX packet queue has 2 instances, software descriptors id and dma ring id
  74. * Based on tx feature and hardware configuration queue id combination could be
  75. * different.
  76. * For example -
  77. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  78. * With no XPS,lock based resource protection, Descriptor pool ids are different
  79. * for each vdev, dma ring id will be same as single pdev id
  80. *
  81. * Return: None
  82. */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. qdf_atomic_dec(&pdev->num_tx_outstanding);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  168. qdf_atomic_dec(&pdev->num_tx_exception);
  169. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  170. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  171. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  172. else
  173. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  175. "Tx Completion Release desc %d status %d outstanding %d",
  176. tx_desc->id, comp_status,
  177. qdf_atomic_read(&pdev->num_tx_outstanding));
  178. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  179. return;
  180. }
  181. /**
  182. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  183. * @vdev: DP vdev Handle
  184. * @nbuf: skb
  185. *
  186. * Prepares and fills HTT metadata in the frame pre-header for special frames
  187. * that should be transmitted using varying transmit parameters.
  188. * There are 2 VDEV modes that currently needs this special metadata -
  189. * 1) Mesh Mode
  190. * 2) DSRC Mode
  191. *
  192. * Return: HTT metadata size
  193. *
  194. */
  195. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  196. uint32_t *meta_data)
  197. {
  198. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  199. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  200. uint8_t htt_desc_size;
  201. /* Size rounded of multiple of 8 bytes */
  202. uint8_t htt_desc_size_aligned;
  203. uint8_t *hdr = NULL;
  204. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  205. /*
  206. * Metadata - HTT MSDU Extension header
  207. */
  208. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  209. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  210. if (vdev->mesh_vdev) {
  211. /* Fill and add HTT metaheader */
  212. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  213. if (hdr == NULL) {
  214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  215. "Error in filling HTT metadata\n");
  216. return 0;
  217. }
  218. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  219. } else if (vdev->opmode == wlan_op_mode_ocb) {
  220. /* Todo - Add support for DSRC */
  221. }
  222. return htt_desc_size_aligned;
  223. }
  224. /**
  225. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  226. * @tso_seg: TSO segment to process
  227. * @ext_desc: Pointer to MSDU extension descriptor
  228. *
  229. * Return: void
  230. */
  231. #if defined(FEATURE_TSO)
  232. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  233. void *ext_desc)
  234. {
  235. uint8_t num_frag;
  236. uint32_t tso_flags;
  237. /*
  238. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  239. * tcp_flag_mask
  240. *
  241. * Checksum enable flags are set in TCL descriptor and not in Extension
  242. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  243. */
  244. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  245. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  246. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  247. tso_seg->tso_flags.ip_len);
  248. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  249. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  250. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  251. uint32_t lo = 0;
  252. uint32_t hi = 0;
  253. qdf_dmaaddr_to_32s(
  254. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  255. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  256. tso_seg->tso_frags[num_frag].length);
  257. }
  258. return;
  259. }
  260. #else
  261. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  262. void *ext_desc)
  263. {
  264. return;
  265. }
  266. #endif
  267. #if defined(FEATURE_TSO)
  268. /**
  269. * dp_tx_free_tso_seg() - Loop through the tso segments
  270. * allocated and free them
  271. *
  272. * @soc: soc handle
  273. * @free_seg: list of tso segments
  274. * @msdu_info: msdu descriptor
  275. *
  276. * Return - void
  277. */
  278. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  279. struct qdf_tso_seg_elem_t *free_seg,
  280. struct dp_tx_msdu_info_s *msdu_info)
  281. {
  282. struct qdf_tso_seg_elem_t *next_seg;
  283. while (free_seg) {
  284. next_seg = free_seg->next;
  285. dp_tx_tso_desc_free(soc,
  286. msdu_info->tx_queue.desc_pool_id,
  287. free_seg);
  288. free_seg = next_seg;
  289. }
  290. }
  291. /**
  292. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  293. * allocated and free them
  294. *
  295. * @soc: soc handle
  296. * @free_seg: list of tso segments
  297. * @msdu_info: msdu descriptor
  298. * Return - void
  299. */
  300. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  301. struct qdf_tso_num_seg_elem_t *free_seg,
  302. struct dp_tx_msdu_info_s *msdu_info)
  303. {
  304. struct qdf_tso_num_seg_elem_t *next_seg;
  305. while (free_seg) {
  306. next_seg = free_seg->next;
  307. dp_tso_num_seg_free(soc,
  308. msdu_info->tx_queue.desc_pool_id,
  309. free_seg);
  310. free_seg = next_seg;
  311. }
  312. }
  313. /**
  314. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  315. * @vdev: virtual device handle
  316. * @msdu: network buffer
  317. * @msdu_info: meta data associated with the msdu
  318. *
  319. * Return: QDF_STATUS_SUCCESS success
  320. */
  321. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  322. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *tso_seg;
  325. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  326. struct dp_soc *soc = vdev->pdev->soc;
  327. struct qdf_tso_info_t *tso_info;
  328. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  329. tso_info = &msdu_info->u.tso_info;
  330. tso_info->curr_seg = NULL;
  331. tso_info->tso_seg_list = NULL;
  332. tso_info->num_segs = num_seg;
  333. msdu_info->frm_type = dp_tx_frm_tso;
  334. tso_info->tso_num_seg_list = NULL;
  335. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  336. while (num_seg) {
  337. tso_seg = dp_tx_tso_desc_alloc(
  338. soc, msdu_info->tx_queue.desc_pool_id);
  339. if (tso_seg) {
  340. tso_seg->next = tso_info->tso_seg_list;
  341. tso_info->tso_seg_list = tso_seg;
  342. num_seg--;
  343. } else {
  344. struct qdf_tso_seg_elem_t *free_seg =
  345. tso_info->tso_seg_list;
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. }
  350. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  351. tso_num_seg = dp_tso_num_seg_alloc(soc,
  352. msdu_info->tx_queue.desc_pool_id);
  353. if (tso_num_seg) {
  354. tso_num_seg->next = tso_info->tso_num_seg_list;
  355. tso_info->tso_num_seg_list = tso_num_seg;
  356. } else {
  357. /* Bug: free tso_num_seg and tso_seg */
  358. /* Free the already allocated num of segments */
  359. struct qdf_tso_seg_elem_t *free_seg =
  360. tso_info->tso_seg_list;
  361. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  362. __func__);
  363. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  364. return QDF_STATUS_E_NOMEM;
  365. }
  366. msdu_info->num_seg =
  367. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  368. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  369. msdu_info->num_seg);
  370. if (!(msdu_info->num_seg)) {
  371. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  372. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  373. msdu_info);
  374. return QDF_STATUS_E_INVAL;
  375. }
  376. tso_info->curr_seg = tso_info->tso_seg_list;
  377. return QDF_STATUS_SUCCESS;
  378. }
  379. #else
  380. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  381. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  382. {
  383. return QDF_STATUS_E_NOMEM;
  384. }
  385. #endif
  386. /**
  387. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  388. * @vdev: DP Vdev handle
  389. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  390. * @desc_pool_id: Descriptor Pool ID
  391. *
  392. * Return:
  393. */
  394. static
  395. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  396. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  397. {
  398. uint8_t i;
  399. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  400. struct dp_tx_seg_info_s *seg_info;
  401. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  402. struct dp_soc *soc = vdev->pdev->soc;
  403. /* Allocate an extension descriptor */
  404. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  405. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  406. if (!msdu_ext_desc) {
  407. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  408. return NULL;
  409. }
  410. if (msdu_info->exception_fw &&
  411. qdf_unlikely(vdev->mesh_vdev)) {
  412. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  413. &msdu_info->meta_data[0],
  414. sizeof(struct htt_tx_msdu_desc_ext2_t));
  415. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  416. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  417. }
  418. switch (msdu_info->frm_type) {
  419. case dp_tx_frm_sg:
  420. case dp_tx_frm_me:
  421. case dp_tx_frm_raw:
  422. seg_info = msdu_info->u.sg_info.curr_seg;
  423. /* Update the buffer pointers in MSDU Extension Descriptor */
  424. for (i = 0; i < seg_info->frag_cnt; i++) {
  425. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  426. seg_info->frags[i].paddr_lo,
  427. seg_info->frags[i].paddr_hi,
  428. seg_info->frags[i].len);
  429. }
  430. break;
  431. case dp_tx_frm_tso:
  432. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  433. &cached_ext_desc[0]);
  434. break;
  435. default:
  436. break;
  437. }
  438. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  439. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  440. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  441. msdu_ext_desc->vaddr);
  442. return msdu_ext_desc;
  443. }
  444. /**
  445. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  446. * @vdev: DP vdev handle
  447. * @nbuf: skb
  448. * @desc_pool_id: Descriptor pool ID
  449. * Allocate and prepare Tx descriptor with msdu information.
  450. *
  451. * Return: Pointer to Tx Descriptor on success,
  452. * NULL on failure
  453. */
  454. static
  455. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  456. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  457. struct dp_tx_msdu_info_s *msdu_info)
  458. {
  459. uint8_t align_pad;
  460. uint8_t is_exception = 0;
  461. uint8_t htt_hdr_size;
  462. struct ether_header *eh;
  463. struct dp_tx_desc_s *tx_desc;
  464. struct dp_pdev *pdev = vdev->pdev;
  465. struct dp_soc *soc = pdev->soc;
  466. /* Allocate software Tx descriptor */
  467. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  468. if (qdf_unlikely(!tx_desc)) {
  469. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  470. return NULL;
  471. }
  472. /* Flow control/Congestion Control counters */
  473. qdf_atomic_inc(&pdev->num_tx_outstanding);
  474. /* Initialize the SW tx descriptor */
  475. tx_desc->nbuf = nbuf;
  476. tx_desc->frm_type = dp_tx_frm_std;
  477. tx_desc->tx_encap_type = vdev->tx_encap_type;
  478. tx_desc->vdev = vdev;
  479. tx_desc->pdev = pdev;
  480. tx_desc->msdu_ext_desc = NULL;
  481. tx_desc->pkt_offset = 0;
  482. /*
  483. * For special modes (vdev_type == ocb or mesh), data frames should be
  484. * transmitted using varying transmit parameters (tx spec) which include
  485. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  486. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  487. * These frames are sent as exception packets to firmware.
  488. *
  489. * HW requirement is that metadata should always point to a
  490. * 8-byte aligned address. So we add alignment pad to start of buffer.
  491. * HTT Metadata should be ensured to be multiple of 8-bytes,
  492. * to get 8-byte aligned start address along with align_pad added
  493. *
  494. * |-----------------------------|
  495. * | |
  496. * |-----------------------------| <-----Buffer Pointer Address given
  497. * | | ^ in HW descriptor (aligned)
  498. * | HTT Metadata | |
  499. * | | |
  500. * | | | Packet Offset given in descriptor
  501. * | | |
  502. * |-----------------------------| |
  503. * | Alignment Pad | v
  504. * |-----------------------------| <----- Actual buffer start address
  505. * | SKB Data | (Unaligned)
  506. * | |
  507. * | |
  508. * | |
  509. * | |
  510. * | |
  511. * |-----------------------------|
  512. */
  513. if (qdf_unlikely((msdu_info->exception_fw)) ||
  514. (vdev->opmode == wlan_op_mode_ocb)) {
  515. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  516. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  517. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  518. "qdf_nbuf_push_head failed\n");
  519. goto failure;
  520. }
  521. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  522. msdu_info->meta_data);
  523. if (htt_hdr_size == 0)
  524. goto failure;
  525. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  526. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  527. is_exception = 1;
  528. }
  529. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  530. qdf_nbuf_map(soc->osdev, nbuf,
  531. QDF_DMA_TO_DEVICE))) {
  532. /* Handle failure */
  533. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  534. "qdf_nbuf_map failed\n");
  535. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  536. goto failure;
  537. }
  538. if (qdf_unlikely(vdev->nawds_enabled)) {
  539. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  540. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  541. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  542. is_exception = 1;
  543. }
  544. }
  545. #if !TQM_BYPASS_WAR
  546. if (is_exception)
  547. #endif
  548. {
  549. /* Temporary WAR due to TQM VP issues */
  550. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  551. qdf_atomic_inc(&pdev->num_tx_exception);
  552. }
  553. return tx_desc;
  554. failure:
  555. dp_tx_desc_release(tx_desc, desc_pool_id);
  556. return NULL;
  557. }
  558. /**
  559. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  560. * @vdev: DP vdev handle
  561. * @nbuf: skb
  562. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  563. * @desc_pool_id : Descriptor Pool ID
  564. *
  565. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  566. * information. For frames wth fragments, allocate and prepare
  567. * an MSDU extension descriptor
  568. *
  569. * Return: Pointer to Tx Descriptor on success,
  570. * NULL on failure
  571. */
  572. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  573. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  574. uint8_t desc_pool_id)
  575. {
  576. struct dp_tx_desc_s *tx_desc;
  577. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  578. struct dp_pdev *pdev = vdev->pdev;
  579. struct dp_soc *soc = pdev->soc;
  580. /* Allocate software Tx descriptor */
  581. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  582. if (!tx_desc) {
  583. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  584. return NULL;
  585. }
  586. /* Flow control/Congestion Control counters */
  587. qdf_atomic_inc(&pdev->num_tx_outstanding);
  588. /* Initialize the SW tx descriptor */
  589. tx_desc->nbuf = nbuf;
  590. tx_desc->frm_type = msdu_info->frm_type;
  591. tx_desc->tx_encap_type = vdev->tx_encap_type;
  592. tx_desc->vdev = vdev;
  593. tx_desc->pdev = pdev;
  594. tx_desc->pkt_offset = 0;
  595. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  596. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  597. /* Handle scattered frames - TSO/SG/ME */
  598. /* Allocate and prepare an extension descriptor for scattered frames */
  599. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  600. if (!msdu_ext_desc) {
  601. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  602. "%s Tx Extension Descriptor Alloc Fail\n",
  603. __func__);
  604. goto failure;
  605. }
  606. #if TQM_BYPASS_WAR
  607. /* Temporary WAR due to TQM VP issues */
  608. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  609. qdf_atomic_inc(&pdev->num_tx_exception);
  610. #endif
  611. if (qdf_unlikely(msdu_info->exception_fw))
  612. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  613. tx_desc->msdu_ext_desc = msdu_ext_desc;
  614. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  615. return tx_desc;
  616. failure:
  617. dp_tx_desc_release(tx_desc, desc_pool_id);
  618. return NULL;
  619. }
  620. /**
  621. * dp_tx_prepare_raw() - Prepare RAW packet TX
  622. * @vdev: DP vdev handle
  623. * @nbuf: buffer pointer
  624. * @seg_info: Pointer to Segment info Descriptor to be prepared
  625. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  626. * descriptor
  627. *
  628. * Return:
  629. */
  630. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  631. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  632. {
  633. qdf_nbuf_t curr_nbuf = NULL;
  634. uint16_t total_len = 0;
  635. qdf_dma_addr_t paddr;
  636. int32_t i;
  637. int32_t mapped_buf_num = 0;
  638. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  639. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  640. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  641. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  642. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  643. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  644. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  645. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  646. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  647. QDF_DMA_TO_DEVICE)) {
  648. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  649. "%s dma map error \n", __func__);
  650. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  651. mapped_buf_num = i;
  652. goto error;
  653. }
  654. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  655. seg_info->frags[i].paddr_lo = paddr;
  656. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  657. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  658. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  659. total_len += qdf_nbuf_len(curr_nbuf);
  660. }
  661. seg_info->frag_cnt = i;
  662. seg_info->total_len = total_len;
  663. seg_info->next = NULL;
  664. sg_info->curr_seg = seg_info;
  665. msdu_info->frm_type = dp_tx_frm_raw;
  666. msdu_info->num_seg = 1;
  667. return nbuf;
  668. error:
  669. i = 0;
  670. while (nbuf) {
  671. curr_nbuf = nbuf;
  672. if (i < mapped_buf_num) {
  673. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  674. i++;
  675. }
  676. nbuf = qdf_nbuf_next(nbuf);
  677. qdf_nbuf_free(curr_nbuf);
  678. }
  679. return NULL;
  680. }
  681. /**
  682. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  683. * @soc: DP Soc Handle
  684. * @vdev: DP vdev handle
  685. * @tx_desc: Tx Descriptor Handle
  686. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  687. * @fw_metadata: Metadata to send to Target Firmware along with frame
  688. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  689. *
  690. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  691. * from software Tx descriptor
  692. *
  693. * Return:
  694. */
  695. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  696. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  697. uint16_t fw_metadata, uint8_t ring_id)
  698. {
  699. uint8_t type;
  700. uint16_t length;
  701. void *hal_tx_desc, *hal_tx_desc_cached;
  702. qdf_dma_addr_t dma_addr;
  703. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  704. /* Return Buffer Manager ID */
  705. uint8_t bm_id = ring_id;
  706. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  707. hal_tx_desc_cached = (void *) cached_desc;
  708. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  709. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  710. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  711. type = HAL_TX_BUF_TYPE_EXT_DESC;
  712. dma_addr = tx_desc->msdu_ext_desc->paddr;
  713. } else {
  714. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  715. type = HAL_TX_BUF_TYPE_BUFFER;
  716. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  717. }
  718. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  719. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  720. dma_addr , bm_id, tx_desc->id, type);
  721. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  722. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  723. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  724. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  725. vdev->dscp_tid_map_id);
  726. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  727. sec_type_map[vdev->sec_type]);
  728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  729. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  730. __func__, length, type, (uint64_t)dma_addr,
  731. tx_desc->pkt_offset, tx_desc->id);
  732. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  733. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  734. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  735. vdev->hal_desc_addr_search_flags);
  736. /* verify checksum offload configuration*/
  737. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  738. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  739. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  740. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  741. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  742. }
  743. if (tid != HTT_TX_EXT_TID_INVALID)
  744. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  745. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  746. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  747. /* Sync cached descriptor with HW */
  748. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  749. if (!hal_tx_desc) {
  750. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  751. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  752. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  753. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  754. return QDF_STATUS_E_RESOURCES;
  755. }
  756. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  757. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  758. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  759. /*
  760. * If one packet is enqueued in HW, PM usage count needs to be
  761. * incremented by one to prevent future runtime suspend. This
  762. * should be tied with the success of enqueuing. It will be
  763. * decremented after the packet has been sent.
  764. */
  765. hif_pm_runtime_get_noresume(soc->hif_handle);
  766. return QDF_STATUS_SUCCESS;
  767. }
  768. /**
  769. * dp_cce_classify() - Classify the frame based on CCE rules
  770. * @vdev: DP vdev handle
  771. * @nbuf: skb
  772. *
  773. * Classify frames based on CCE rules
  774. * Return: bool( true if classified,
  775. * else false)
  776. */
  777. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  778. {
  779. struct ether_header *eh = NULL;
  780. uint16_t ether_type;
  781. qdf_llc_t *llcHdr;
  782. qdf_nbuf_t nbuf_clone = NULL;
  783. qdf_dot3_qosframe_t *qos_wh = NULL;
  784. /* for mesh packets don't do any classification */
  785. if (qdf_unlikely(vdev->mesh_vdev))
  786. return false;
  787. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  788. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  789. ether_type = eh->ether_type;
  790. llcHdr = (qdf_llc_t *)(nbuf->data +
  791. sizeof(struct ether_header));
  792. } else {
  793. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  794. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  795. if (qdf_unlikely(
  796. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  797. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  798. ether_type = *(uint16_t *)(nbuf->data
  799. + QDF_IEEE80211_4ADDR_HDR_LEN
  800. + sizeof(qdf_llc_t)
  801. - sizeof(ether_type));
  802. llcHdr = (qdf_llc_t *)(nbuf->data +
  803. QDF_IEEE80211_4ADDR_HDR_LEN);
  804. } else {
  805. ether_type = *(uint16_t *)(nbuf->data
  806. + QDF_IEEE80211_3ADDR_HDR_LEN
  807. + sizeof(qdf_llc_t)
  808. - sizeof(ether_type));
  809. llcHdr = (qdf_llc_t *)(nbuf->data +
  810. QDF_IEEE80211_3ADDR_HDR_LEN);
  811. }
  812. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  813. && (ether_type ==
  814. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  815. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  816. return true;
  817. }
  818. }
  819. return false;
  820. }
  821. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  822. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  823. sizeof(*llcHdr));
  824. nbuf_clone = qdf_nbuf_clone(nbuf);
  825. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  826. if (ether_type == htons(ETHERTYPE_8021Q)) {
  827. qdf_nbuf_pull_head(nbuf_clone,
  828. sizeof(qdf_net_vlanhdr_t));
  829. }
  830. } else {
  831. if (ether_type == htons(ETHERTYPE_8021Q)) {
  832. nbuf_clone = qdf_nbuf_clone(nbuf);
  833. qdf_nbuf_pull_head(nbuf_clone,
  834. sizeof(qdf_net_vlanhdr_t));
  835. }
  836. }
  837. if (qdf_unlikely(nbuf_clone))
  838. nbuf = nbuf_clone;
  839. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  840. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  841. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  842. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  843. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  844. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  845. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  846. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  847. if (qdf_unlikely(nbuf_clone != NULL))
  848. qdf_nbuf_free(nbuf_clone);
  849. return true;
  850. }
  851. if (qdf_unlikely(nbuf_clone != NULL))
  852. qdf_nbuf_free(nbuf_clone);
  853. return false;
  854. }
  855. /**
  856. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  857. * @vdev: DP vdev handle
  858. * @nbuf: skb
  859. *
  860. * Extract the DSCP or PCP information from frame and map into TID value.
  861. * Software based TID classification is required when more than 2 DSCP-TID
  862. * mapping tables are needed.
  863. * Hardware supports 2 DSCP-TID mapping tables
  864. *
  865. * Return: void
  866. */
  867. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  868. struct dp_tx_msdu_info_s *msdu_info)
  869. {
  870. uint8_t tos = 0, dscp_tid_override = 0;
  871. uint8_t *hdr_ptr, *L3datap;
  872. uint8_t is_mcast = 0;
  873. struct ether_header *eh = NULL;
  874. qdf_ethervlan_header_t *evh = NULL;
  875. uint16_t ether_type;
  876. qdf_llc_t *llcHdr;
  877. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  878. /* for mesh packets don't do any classification */
  879. if (qdf_unlikely(vdev->mesh_vdev))
  880. return;
  881. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  882. eh = (struct ether_header *) nbuf->data;
  883. hdr_ptr = eh->ether_dhost;
  884. L3datap = hdr_ptr + sizeof(struct ether_header);
  885. } else {
  886. qdf_dot3_qosframe_t *qos_wh =
  887. (qdf_dot3_qosframe_t *) nbuf->data;
  888. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  889. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  890. return;
  891. }
  892. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  893. ether_type = eh->ether_type;
  894. /*
  895. * Check if packet is dot3 or eth2 type.
  896. */
  897. if (IS_LLC_PRESENT(ether_type)) {
  898. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  899. sizeof(*llcHdr));
  900. if (ether_type == htons(ETHERTYPE_8021Q)) {
  901. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  902. sizeof(*llcHdr);
  903. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  904. + sizeof(*llcHdr) +
  905. sizeof(qdf_net_vlanhdr_t));
  906. } else {
  907. L3datap = hdr_ptr + sizeof(struct ether_header) +
  908. sizeof(*llcHdr);
  909. }
  910. } else {
  911. if (ether_type == htons(ETHERTYPE_8021Q)) {
  912. evh = (qdf_ethervlan_header_t *) eh;
  913. ether_type = evh->ether_type;
  914. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  915. }
  916. }
  917. /*
  918. * Find priority from IP TOS DSCP field
  919. */
  920. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  921. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  922. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  923. /* Only for unicast frames */
  924. if (!is_mcast) {
  925. /* send it on VO queue */
  926. msdu_info->tid = DP_VO_TID;
  927. }
  928. } else {
  929. /*
  930. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  931. * from TOS byte.
  932. */
  933. tos = ip->ip_tos;
  934. dscp_tid_override = 1;
  935. }
  936. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  937. /* TODO
  938. * use flowlabel
  939. *igmpmld cases to be handled in phase 2
  940. */
  941. unsigned long ver_pri_flowlabel;
  942. unsigned long pri;
  943. ver_pri_flowlabel = *(unsigned long *) L3datap;
  944. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  945. DP_IPV6_PRIORITY_SHIFT;
  946. tos = pri;
  947. dscp_tid_override = 1;
  948. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  949. msdu_info->tid = DP_VO_TID;
  950. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  951. /* Only for unicast frames */
  952. if (!is_mcast) {
  953. /* send ucast arp on VO queue */
  954. msdu_info->tid = DP_VO_TID;
  955. }
  956. }
  957. /*
  958. * Assign all MCAST packets to BE
  959. */
  960. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  961. if (is_mcast) {
  962. tos = 0;
  963. dscp_tid_override = 1;
  964. }
  965. }
  966. if (dscp_tid_override == 1) {
  967. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  968. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  969. }
  970. return;
  971. }
  972. #ifdef CONVERGED_TDLS_ENABLE
  973. /**
  974. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  975. * @tx_desc: TX descriptor
  976. *
  977. * Return: None
  978. */
  979. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  980. {
  981. if (tx_desc->vdev) {
  982. if (tx_desc->vdev->is_tdls_frame)
  983. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  984. tx_desc->vdev->is_tdls_frame = false;
  985. }
  986. }
  987. /**
  988. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  989. * @tx_desc: TX descriptor
  990. * @vdev: datapath vdev handle
  991. *
  992. * Return: None
  993. */
  994. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  995. struct dp_vdev *vdev)
  996. {
  997. struct hal_tx_completion_status ts = {0};
  998. qdf_nbuf_t nbuf = tx_desc->nbuf;
  999. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1000. if (vdev->tx_non_std_data_callback.func) {
  1001. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1002. vdev->tx_non_std_data_callback.func(
  1003. vdev->tx_non_std_data_callback.ctxt,
  1004. nbuf, ts.status);
  1005. return;
  1006. }
  1007. }
  1008. #endif
  1009. /**
  1010. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1011. * @vdev: DP vdev handle
  1012. * @nbuf: skb
  1013. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1014. * @tx_q: Tx queue to be used for this Tx frame
  1015. * @peer_id: peer_id of the peer in case of NAWDS frames
  1016. *
  1017. * Return: NULL on success,
  1018. * nbuf when it fails to send
  1019. */
  1020. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1021. struct dp_tx_msdu_info_s *msdu_info,
  1022. uint16_t peer_id)
  1023. {
  1024. struct dp_pdev *pdev = vdev->pdev;
  1025. struct dp_soc *soc = pdev->soc;
  1026. struct dp_tx_desc_s *tx_desc;
  1027. QDF_STATUS status;
  1028. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1029. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1030. uint16_t htt_tcl_metadata = 0;
  1031. uint8_t tid = msdu_info->tid;
  1032. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  1033. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1034. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, msdu_info);
  1035. if (!tx_desc) {
  1036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1037. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1038. __func__, vdev, tx_q->desc_pool_id);
  1039. return nbuf;
  1040. }
  1041. if (qdf_unlikely(soc->cce_disable)) {
  1042. if (dp_cce_classify(vdev, nbuf) == true) {
  1043. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1044. tid = DP_VO_TID;
  1045. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1046. }
  1047. }
  1048. dp_tx_update_tdls_flags(tx_desc);
  1049. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1050. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1051. "%s %d : HAL RING Access Failed -- %pK\n",
  1052. __func__, __LINE__, hal_srng);
  1053. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1054. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1055. goto fail_return;
  1056. }
  1057. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1058. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1059. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1060. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1061. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1062. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1063. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1064. peer_id);
  1065. } else
  1066. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1067. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1068. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1069. htt_tcl_metadata, tx_q->ring_id);
  1070. if (status != QDF_STATUS_SUCCESS) {
  1071. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1072. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1073. __func__, tx_desc, tx_q->ring_id);
  1074. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1075. goto fail_return;
  1076. }
  1077. nbuf = NULL;
  1078. fail_return:
  1079. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1080. hal_srng_access_end(soc->hal_soc, hal_srng);
  1081. hif_pm_runtime_put(soc->hif_handle);
  1082. } else {
  1083. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1084. }
  1085. return nbuf;
  1086. }
  1087. /**
  1088. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1089. * @vdev: DP vdev handle
  1090. * @nbuf: skb
  1091. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1092. *
  1093. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1094. *
  1095. * Return: NULL on success,
  1096. * nbuf when it fails to send
  1097. */
  1098. #if QDF_LOCK_STATS
  1099. static noinline
  1100. #else
  1101. static
  1102. #endif
  1103. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1104. struct dp_tx_msdu_info_s *msdu_info)
  1105. {
  1106. uint8_t i;
  1107. struct dp_pdev *pdev = vdev->pdev;
  1108. struct dp_soc *soc = pdev->soc;
  1109. struct dp_tx_desc_s *tx_desc;
  1110. bool is_cce_classified = false;
  1111. QDF_STATUS status;
  1112. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1113. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1114. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1115. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1116. "%s %d : HAL RING Access Failed -- %pK\n",
  1117. __func__, __LINE__, hal_srng);
  1118. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1119. return nbuf;
  1120. }
  1121. if (qdf_unlikely(soc->cce_disable)) {
  1122. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1123. if (is_cce_classified) {
  1124. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1125. msdu_info->tid = DP_VO_TID;
  1126. }
  1127. }
  1128. if (msdu_info->frm_type == dp_tx_frm_me)
  1129. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1130. i = 0;
  1131. /* Print statement to track i and num_seg */
  1132. /*
  1133. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1134. * descriptors using information in msdu_info
  1135. */
  1136. while (i < msdu_info->num_seg) {
  1137. /*
  1138. * Setup Tx descriptor for an MSDU, and MSDU extension
  1139. * descriptor
  1140. */
  1141. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1142. tx_q->desc_pool_id);
  1143. if (!tx_desc) {
  1144. if (msdu_info->frm_type == dp_tx_frm_me) {
  1145. dp_tx_me_free_buf(pdev,
  1146. (void *)(msdu_info->u.sg_info
  1147. .curr_seg->frags[0].vaddr));
  1148. }
  1149. goto done;
  1150. }
  1151. if (msdu_info->frm_type == dp_tx_frm_me) {
  1152. tx_desc->me_buffer =
  1153. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1154. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1155. }
  1156. if (is_cce_classified)
  1157. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1158. /*
  1159. * Enqueue the Tx MSDU descriptor to HW for transmit
  1160. */
  1161. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1162. vdev->htt_tcl_metadata, tx_q->ring_id);
  1163. if (status != QDF_STATUS_SUCCESS) {
  1164. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1165. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1166. __func__, tx_desc, tx_q->ring_id);
  1167. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1168. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1169. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1170. goto done;
  1171. }
  1172. /*
  1173. * TODO
  1174. * if tso_info structure can be modified to have curr_seg
  1175. * as first element, following 2 blocks of code (for TSO and SG)
  1176. * can be combined into 1
  1177. */
  1178. /*
  1179. * For frames with multiple segments (TSO, ME), jump to next
  1180. * segment.
  1181. */
  1182. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1183. if (msdu_info->u.tso_info.curr_seg->next) {
  1184. msdu_info->u.tso_info.curr_seg =
  1185. msdu_info->u.tso_info.curr_seg->next;
  1186. /*
  1187. * If this is a jumbo nbuf, then increment the number of
  1188. * nbuf users for each additional segment of the msdu.
  1189. * This will ensure that the skb is freed only after
  1190. * receiving tx completion for all segments of an nbuf
  1191. */
  1192. qdf_nbuf_inc_users(nbuf);
  1193. /* Check with MCL if this is needed */
  1194. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1195. }
  1196. }
  1197. /*
  1198. * For Multicast-Unicast converted packets,
  1199. * each converted frame (for a client) is represented as
  1200. * 1 segment
  1201. */
  1202. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1203. (msdu_info->frm_type == dp_tx_frm_me)) {
  1204. if (msdu_info->u.sg_info.curr_seg->next) {
  1205. msdu_info->u.sg_info.curr_seg =
  1206. msdu_info->u.sg_info.curr_seg->next;
  1207. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1208. }
  1209. }
  1210. i++;
  1211. }
  1212. nbuf = NULL;
  1213. done:
  1214. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1215. hal_srng_access_end(soc->hal_soc, hal_srng);
  1216. hif_pm_runtime_put(soc->hif_handle);
  1217. } else {
  1218. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1219. }
  1220. return nbuf;
  1221. }
  1222. /**
  1223. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1224. * for SG frames
  1225. * @vdev: DP vdev handle
  1226. * @nbuf: skb
  1227. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1228. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1229. *
  1230. * Return: NULL on success,
  1231. * nbuf when it fails to send
  1232. */
  1233. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1234. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1235. {
  1236. uint32_t cur_frag, nr_frags;
  1237. qdf_dma_addr_t paddr;
  1238. struct dp_tx_sg_info_s *sg_info;
  1239. sg_info = &msdu_info->u.sg_info;
  1240. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1241. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1242. QDF_DMA_TO_DEVICE)) {
  1243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1244. "dma map error\n");
  1245. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1246. qdf_nbuf_free(nbuf);
  1247. return NULL;
  1248. }
  1249. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1250. seg_info->frags[0].paddr_lo = paddr;
  1251. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1252. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1253. seg_info->frags[0].vaddr = (void *) nbuf;
  1254. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1255. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1256. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1257. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1258. "frag dma map error\n");
  1259. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1260. qdf_nbuf_free(nbuf);
  1261. return NULL;
  1262. }
  1263. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1264. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1265. seg_info->frags[cur_frag + 1].paddr_hi =
  1266. ((uint64_t) paddr) >> 32;
  1267. seg_info->frags[cur_frag + 1].len =
  1268. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1269. }
  1270. seg_info->frag_cnt = (cur_frag + 1);
  1271. seg_info->total_len = qdf_nbuf_len(nbuf);
  1272. seg_info->next = NULL;
  1273. sg_info->curr_seg = seg_info;
  1274. msdu_info->frm_type = dp_tx_frm_sg;
  1275. msdu_info->num_seg = 1;
  1276. return nbuf;
  1277. }
  1278. #ifdef MESH_MODE_SUPPORT
  1279. /**
  1280. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1281. and prepare msdu_info for mesh frames.
  1282. * @vdev: DP vdev handle
  1283. * @nbuf: skb
  1284. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1285. *
  1286. * Return: NULL on failure,
  1287. * nbuf when extracted successfully
  1288. */
  1289. static
  1290. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1291. struct dp_tx_msdu_info_s *msdu_info)
  1292. {
  1293. struct meta_hdr_s *mhdr;
  1294. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1295. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1296. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1297. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1298. msdu_info->exception_fw = 0;
  1299. goto remove_meta_hdr;
  1300. }
  1301. msdu_info->exception_fw = 1;
  1302. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1303. meta_data->host_tx_desc_pool = 1;
  1304. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1305. meta_data->power = mhdr->power;
  1306. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1307. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1308. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1309. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1310. meta_data->dyn_bw = 1;
  1311. meta_data->valid_pwr = 1;
  1312. meta_data->valid_mcs_mask = 1;
  1313. meta_data->valid_nss_mask = 1;
  1314. meta_data->valid_preamble_type = 1;
  1315. meta_data->valid_retries = 1;
  1316. meta_data->valid_bw_info = 1;
  1317. }
  1318. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1319. meta_data->encrypt_type = 0;
  1320. meta_data->valid_encrypt_type = 1;
  1321. }
  1322. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1323. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1324. else
  1325. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1326. meta_data->valid_key_flags = 1;
  1327. meta_data->key_flags = (mhdr->keyix & 0x3);
  1328. remove_meta_hdr:
  1329. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1330. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1331. "qdf_nbuf_pull_head failed\n");
  1332. qdf_nbuf_free(nbuf);
  1333. return NULL;
  1334. }
  1335. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1336. "%s , Meta hdr %0x %0x %0x %0x %0x to_fw %d\n",
  1337. __func__, msdu_info->meta_data[0],
  1338. msdu_info->meta_data[1],
  1339. msdu_info->meta_data[2],
  1340. msdu_info->meta_data[3],
  1341. msdu_info->meta_data[4], msdu_info->exception_fw);
  1342. return nbuf;
  1343. }
  1344. #else
  1345. static
  1346. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1347. struct dp_tx_msdu_info_s *msdu_info)
  1348. {
  1349. return nbuf;
  1350. }
  1351. #endif
  1352. #ifdef DP_FEATURE_NAWDS_TX
  1353. /**
  1354. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1355. * @vdev: dp_vdev handle
  1356. * @nbuf: skb
  1357. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1358. * @tx_q: Tx queue to be used for this Tx frame
  1359. * @meta_data: Meta date for mesh
  1360. * @peer_id: peer_id of the peer in case of NAWDS frames
  1361. *
  1362. * return: NULL on success nbuf on failure
  1363. */
  1364. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1365. struct dp_tx_msdu_info_s *msdu_info)
  1366. {
  1367. struct dp_peer *peer = NULL;
  1368. struct dp_soc *soc = vdev->pdev->soc;
  1369. struct dp_ast_entry *ast_entry = NULL;
  1370. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1371. uint16_t peer_id = HTT_INVALID_PEER;
  1372. struct dp_peer *sa_peer = NULL;
  1373. qdf_nbuf_t nbuf_copy;
  1374. qdf_spin_lock_bh(&(soc->ast_lock));
  1375. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1376. if (ast_entry)
  1377. sa_peer = ast_entry->peer;
  1378. qdf_spin_unlock_bh(&(soc->ast_lock));
  1379. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1380. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1381. (peer->nawds_enabled)) {
  1382. if (sa_peer == peer) {
  1383. QDF_TRACE(QDF_MODULE_ID_DP,
  1384. QDF_TRACE_LEVEL_DEBUG,
  1385. " %s: broadcast multicast packet",
  1386. __func__);
  1387. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1388. continue;
  1389. }
  1390. nbuf_copy = qdf_nbuf_copy(nbuf);
  1391. if (!nbuf_copy) {
  1392. QDF_TRACE(QDF_MODULE_ID_DP,
  1393. QDF_TRACE_LEVEL_ERROR,
  1394. "nbuf copy failed");
  1395. }
  1396. peer_id = peer->peer_ids[0];
  1397. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1398. msdu_info, peer_id);
  1399. if (nbuf_copy != NULL) {
  1400. qdf_nbuf_free(nbuf_copy);
  1401. continue;
  1402. }
  1403. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1404. 1, qdf_nbuf_len(nbuf));
  1405. }
  1406. }
  1407. if (peer_id == HTT_INVALID_PEER)
  1408. return nbuf;
  1409. return NULL;
  1410. }
  1411. #endif
  1412. /**
  1413. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1414. * @vap_dev: DP vdev handle
  1415. * @nbuf: skb
  1416. *
  1417. * Entry point for Core Tx layer (DP_TX) invoked from
  1418. * hard_start_xmit in OSIF/HDD
  1419. *
  1420. * Return: NULL on success,
  1421. * nbuf when it fails to send
  1422. */
  1423. #ifdef MESH_MODE_SUPPORT
  1424. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1425. {
  1426. struct meta_hdr_s *mhdr;
  1427. qdf_nbuf_t nbuf_mesh = NULL;
  1428. qdf_nbuf_t nbuf_clone = NULL;
  1429. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1430. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1431. if (nbuf_mesh == NULL) {
  1432. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1433. "qdf_nbuf_unshare failed\n");
  1434. return nbuf;
  1435. }
  1436. nbuf = nbuf_mesh;
  1437. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1438. if (mhdr->flags & METAHDR_FLAG_INFO_UPDATED) {
  1439. nbuf_clone = qdf_nbuf_clone(nbuf);
  1440. if (nbuf_clone == NULL) {
  1441. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1442. "qdf_nbuf_clone failed\n");
  1443. return nbuf;
  1444. }
  1445. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1446. }
  1447. if (nbuf_clone) {
  1448. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1449. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1450. } else
  1451. qdf_nbuf_free(nbuf_clone);
  1452. }
  1453. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1454. return dp_tx_send(vap_dev, nbuf);
  1455. }
  1456. #else
  1457. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1458. {
  1459. return dp_tx_send(vap_dev, nbuf);
  1460. }
  1461. #endif
  1462. /**
  1463. * dp_tx_send() - Transmit a frame on a given VAP
  1464. * @vap_dev: DP vdev handle
  1465. * @nbuf: skb
  1466. *
  1467. * Entry point for Core Tx layer (DP_TX) invoked from
  1468. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1469. * cases
  1470. *
  1471. * Return: NULL on success,
  1472. * nbuf when it fails to send
  1473. */
  1474. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1475. {
  1476. struct ether_header *eh = NULL;
  1477. struct dp_tx_msdu_info_s msdu_info;
  1478. struct dp_tx_seg_info_s seg_info;
  1479. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1480. uint16_t peer_id = HTT_INVALID_PEER;
  1481. qdf_nbuf_t nbuf_mesh = NULL;
  1482. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1483. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1484. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1486. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1487. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1488. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1489. /*
  1490. * Set Default Host TID value to invalid TID
  1491. * (TID override disabled)
  1492. */
  1493. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1494. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1495. if (qdf_unlikely(vdev->mesh_vdev)) {
  1496. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1497. &msdu_info);
  1498. if (nbuf_mesh == NULL) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1500. "Extracting mesh metadata failed\n");
  1501. return nbuf;
  1502. }
  1503. nbuf = nbuf_mesh;
  1504. }
  1505. /*
  1506. * Get HW Queue to use for this frame.
  1507. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1508. * dedicated for data and 1 for command.
  1509. * "queue_id" maps to one hardware ring.
  1510. * With each ring, we also associate a unique Tx descriptor pool
  1511. * to minimize lock contention for these resources.
  1512. */
  1513. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1514. /*
  1515. * TCL H/W supports 2 DSCP-TID mapping tables.
  1516. * Table 1 - Default DSCP-TID mapping table
  1517. * Table 2 - 1 DSCP-TID override table
  1518. *
  1519. * If we need a different DSCP-TID mapping for this vap,
  1520. * call tid_classify to extract DSCP/ToS from frame and
  1521. * map to a TID and store in msdu_info. This is later used
  1522. * to fill in TCL Input descriptor (per-packet TID override).
  1523. */
  1524. if (vdev->dscp_tid_map_id > 1)
  1525. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1526. /* Reset the control block */
  1527. qdf_nbuf_reset_ctxt(nbuf);
  1528. /*
  1529. * Classify the frame and call corresponding
  1530. * "prepare" function which extracts the segment (TSO)
  1531. * and fragmentation information (for TSO , SG, ME, or Raw)
  1532. * into MSDU_INFO structure which is later used to fill
  1533. * SW and HW descriptors.
  1534. */
  1535. if (qdf_nbuf_is_tso(nbuf)) {
  1536. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1537. "%s TSO frame %pK\n", __func__, vdev);
  1538. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1539. qdf_nbuf_len(nbuf));
  1540. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1541. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1542. return nbuf;
  1543. }
  1544. goto send_multiple;
  1545. }
  1546. /* SG */
  1547. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1548. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1549. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1550. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1551. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1552. qdf_nbuf_len(nbuf));
  1553. goto send_multiple;
  1554. }
  1555. #ifdef ATH_SUPPORT_IQUE
  1556. /* Mcast to Ucast Conversion*/
  1557. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1558. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1559. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1561. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1562. DP_STATS_INC_PKT(vdev,
  1563. tx_i.mcast_en.mcast_pkt, 1,
  1564. qdf_nbuf_len(nbuf));
  1565. if (dp_tx_prepare_send_me(vdev, nbuf) > 0) {
  1566. qdf_nbuf_free(nbuf);
  1567. return NULL;
  1568. }
  1569. }
  1570. }
  1571. #endif
  1572. /* RAW */
  1573. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1574. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1575. if (nbuf == NULL)
  1576. return NULL;
  1577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1578. "%s Raw frame %pK\n", __func__, vdev);
  1579. goto send_multiple;
  1580. }
  1581. /* Single linear frame */
  1582. /*
  1583. * If nbuf is a simple linear frame, use send_single function to
  1584. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1585. * SRNG. There is no need to setup a MSDU extension descriptor.
  1586. */
  1587. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id);
  1588. return nbuf;
  1589. send_multiple:
  1590. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1591. return nbuf;
  1592. }
  1593. /**
  1594. * dp_tx_reinject_handler() - Tx Reinject Handler
  1595. * @tx_desc: software descriptor head pointer
  1596. * @status : Tx completion status from HTT descriptor
  1597. *
  1598. * This function reinjects frames back to Target.
  1599. * Todo - Host queue needs to be added
  1600. *
  1601. * Return: none
  1602. */
  1603. static
  1604. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1605. {
  1606. struct dp_vdev *vdev;
  1607. struct dp_peer *peer = NULL;
  1608. uint32_t peer_id = HTT_INVALID_PEER;
  1609. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1610. qdf_nbuf_t nbuf_copy = NULL;
  1611. struct dp_tx_msdu_info_s msdu_info;
  1612. struct dp_peer *sa_peer = NULL;
  1613. struct dp_ast_entry *ast_entry = NULL;
  1614. struct dp_soc *soc = NULL;
  1615. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1616. #ifdef WDS_VENDOR_EXTENSION
  1617. int is_mcast = 0, is_ucast = 0;
  1618. int num_peers_3addr = 0;
  1619. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1620. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1621. #endif
  1622. vdev = tx_desc->vdev;
  1623. soc = vdev->pdev->soc;
  1624. qdf_assert(vdev);
  1625. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1626. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1627. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1628. "%s Tx reinject path\n", __func__);
  1629. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1630. qdf_nbuf_len(tx_desc->nbuf));
  1631. qdf_spin_lock_bh(&(soc->ast_lock));
  1632. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost), 0);
  1633. if (ast_entry)
  1634. sa_peer = ast_entry->peer;
  1635. qdf_spin_unlock_bh(&(soc->ast_lock));
  1636. #ifdef WDS_VENDOR_EXTENSION
  1637. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1638. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1639. } else {
  1640. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1641. }
  1642. is_ucast = !is_mcast;
  1643. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1644. if (peer->bss_peer)
  1645. continue;
  1646. /* Detect wds peers that use 3-addr framing for mcast.
  1647. * if there are any, the bss_peer is used to send the
  1648. * the mcast frame using 3-addr format. all wds enabled
  1649. * peers that use 4-addr framing for mcast frames will
  1650. * be duplicated and sent as 4-addr frames below.
  1651. */
  1652. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1653. num_peers_3addr = 1;
  1654. break;
  1655. }
  1656. }
  1657. #endif
  1658. if (qdf_unlikely(vdev->mesh_vdev)) {
  1659. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1660. } else {
  1661. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1662. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1663. #ifdef WDS_VENDOR_EXTENSION
  1664. /*
  1665. * . if 3-addr STA, then send on BSS Peer
  1666. * . if Peer WDS enabled and accept 4-addr mcast,
  1667. * send mcast on that peer only
  1668. * . if Peer WDS enabled and accept 4-addr ucast,
  1669. * send ucast on that peer only
  1670. */
  1671. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1672. (peer->wds_enabled &&
  1673. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1674. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1675. #else
  1676. ((peer->bss_peer &&
  1677. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1678. peer->nawds_enabled)) {
  1679. #endif
  1680. peer_id = DP_INVALID_PEER;
  1681. if (peer->nawds_enabled) {
  1682. peer_id = peer->peer_ids[0];
  1683. if (sa_peer == peer) {
  1684. QDF_TRACE(
  1685. QDF_MODULE_ID_DP,
  1686. QDF_TRACE_LEVEL_DEBUG,
  1687. " %s: multicast packet",
  1688. __func__);
  1689. DP_STATS_INC(peer,
  1690. tx.nawds_mcast_drop, 1);
  1691. continue;
  1692. }
  1693. }
  1694. nbuf_copy = qdf_nbuf_copy(nbuf);
  1695. if (!nbuf_copy) {
  1696. QDF_TRACE(QDF_MODULE_ID_DP,
  1697. QDF_TRACE_LEVEL_DEBUG,
  1698. FL("nbuf copy failed"));
  1699. break;
  1700. }
  1701. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1702. nbuf_copy,
  1703. &msdu_info,
  1704. peer_id);
  1705. if (nbuf_copy) {
  1706. QDF_TRACE(QDF_MODULE_ID_DP,
  1707. QDF_TRACE_LEVEL_DEBUG,
  1708. FL("pkt send failed"));
  1709. qdf_nbuf_free(nbuf_copy);
  1710. } else {
  1711. if (peer_id != DP_INVALID_PEER)
  1712. DP_STATS_INC_PKT(peer,
  1713. tx.nawds_mcast,
  1714. 1, qdf_nbuf_len(nbuf));
  1715. }
  1716. }
  1717. }
  1718. }
  1719. if (vdev->nawds_enabled) {
  1720. peer_id = DP_INVALID_PEER;
  1721. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1722. 1, qdf_nbuf_len(nbuf));
  1723. nbuf = dp_tx_send_msdu_single(vdev,
  1724. nbuf, &msdu_info, peer_id);
  1725. if (nbuf) {
  1726. QDF_TRACE(QDF_MODULE_ID_DP,
  1727. QDF_TRACE_LEVEL_DEBUG,
  1728. FL("pkt send failed"));
  1729. qdf_nbuf_free(nbuf);
  1730. }
  1731. } else
  1732. qdf_nbuf_free(nbuf);
  1733. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1734. }
  1735. /**
  1736. * dp_tx_inspect_handler() - Tx Inspect Handler
  1737. * @tx_desc: software descriptor head pointer
  1738. * @status : Tx completion status from HTT descriptor
  1739. *
  1740. * Handles Tx frames sent back to Host for inspection
  1741. * (ProxyARP)
  1742. *
  1743. * Return: none
  1744. */
  1745. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1746. {
  1747. struct dp_soc *soc;
  1748. struct dp_pdev *pdev = tx_desc->pdev;
  1749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1750. "%s Tx inspect path\n",
  1751. __func__);
  1752. qdf_assert(pdev);
  1753. soc = pdev->soc;
  1754. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1755. qdf_nbuf_len(tx_desc->nbuf));
  1756. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1757. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1758. }
  1759. #ifdef FEATURE_PERPKT_INFO
  1760. QDF_STATUS
  1761. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1762. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1763. {
  1764. struct tx_capture_hdr *ppdu_hdr;
  1765. struct dp_peer *peer = NULL;
  1766. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1767. return QDF_STATUS_E_NOSUPPORT;
  1768. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1769. dp_peer_find_by_id(soc, peer_id);
  1770. if (!peer) {
  1771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1772. FL("Peer Invalid"));
  1773. return QDF_STATUS_E_INVAL;
  1774. }
  1775. if (pdev->mcopy_mode) {
  1776. if ((pdev->am_copy_id.tx_ppdu_id == ppdu_id) &&
  1777. (pdev->am_copy_id.tx_peer_id == peer_id)) {
  1778. return QDF_STATUS_E_INVAL;
  1779. }
  1780. pdev->am_copy_id.tx_ppdu_id = ppdu_id;
  1781. pdev->am_copy_id.tx_peer_id = peer_id;
  1782. }
  1783. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1784. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1785. FL("No headroom"));
  1786. return QDF_STATUS_E_NOMEM;
  1787. }
  1788. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1789. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1790. IEEE80211_ADDR_LEN);
  1791. ppdu_hdr->ppdu_id = ppdu_id;
  1792. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1793. IEEE80211_ADDR_LEN);
  1794. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1795. netbuf, peer_id,
  1796. WDI_NO_VAL, pdev->pdev_id);
  1797. return QDF_STATUS_SUCCESS;
  1798. }
  1799. #else
  1800. static QDF_STATUS
  1801. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1802. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1803. {
  1804. return QDF_STATUS_E_NOSUPPORT;
  1805. }
  1806. #endif
  1807. /**
  1808. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1809. * @soc: Soc handle
  1810. * @desc: software Tx descriptor to be processed
  1811. *
  1812. * Return: none
  1813. */
  1814. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1815. struct dp_tx_desc_s *desc)
  1816. {
  1817. struct dp_vdev *vdev = desc->vdev;
  1818. qdf_nbuf_t nbuf = desc->nbuf;
  1819. struct hal_tx_completion_status ts = {0};
  1820. if (desc)
  1821. hal_tx_comp_get_status(&desc->comp, &ts);
  1822. /* If it is TDLS mgmt, don't unmap or free the frame */
  1823. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1824. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1825. /* 0 : MSDU buffer, 1 : MLE */
  1826. if (desc->msdu_ext_desc) {
  1827. /* TSO free */
  1828. if (hal_tx_ext_desc_get_tso_enable(
  1829. desc->msdu_ext_desc->vaddr)) {
  1830. /* If remaining number of segment is 0
  1831. * actual TSO may unmap and free */
  1832. if (!DP_DESC_NUM_FRAG(desc)) {
  1833. qdf_nbuf_unmap(soc->osdev, nbuf,
  1834. QDF_DMA_TO_DEVICE);
  1835. qdf_nbuf_free(nbuf);
  1836. return;
  1837. }
  1838. }
  1839. }
  1840. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1841. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1842. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1843. if (dp_send_compl_to_stack(soc, desc->pdev, ts.peer_id,
  1844. ts.ppdu_id, nbuf) == QDF_STATUS_SUCCESS)
  1845. return;
  1846. if (qdf_likely(!vdev->mesh_vdev))
  1847. qdf_nbuf_free(nbuf);
  1848. else {
  1849. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1850. qdf_nbuf_free(nbuf);
  1851. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1852. } else
  1853. vdev->osif_tx_free_ext((nbuf));
  1854. }
  1855. }
  1856. /**
  1857. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1858. * @vdev: pointer to dp dev handler
  1859. * @status : Tx completion status from HTT descriptor
  1860. *
  1861. * Handles MEC notify event sent from fw to Host
  1862. *
  1863. * Return: none
  1864. */
  1865. #ifdef FEATURE_WDS
  1866. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1867. {
  1868. struct dp_soc *soc;
  1869. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1870. struct dp_peer *peer;
  1871. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1872. soc = vdev->pdev->soc;
  1873. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1874. peer = TAILQ_FIRST(&vdev->peer_list);
  1875. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1876. if (!peer) {
  1877. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1878. FL("peer is NULL"));
  1879. return;
  1880. }
  1881. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1882. "%s Tx MEC Handler\n",
  1883. __func__);
  1884. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1885. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1886. status[(DP_MAC_ADDR_LEN - 2) + i];
  1887. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN) &&
  1888. !dp_peer_add_ast(soc, peer, mac_addr, dp_ast_type_mec)) {
  1889. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1890. vdev->osif_vdev,
  1891. mac_addr,
  1892. vdev->mac_addr.raw,
  1893. flags);
  1894. }
  1895. }
  1896. #else
  1897. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1898. {
  1899. }
  1900. #endif
  1901. /**
  1902. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1903. * @tx_desc: software descriptor head pointer
  1904. * @status : Tx completion status from HTT descriptor
  1905. *
  1906. * This function will process HTT Tx indication messages from Target
  1907. *
  1908. * Return: none
  1909. */
  1910. static
  1911. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1912. {
  1913. uint8_t tx_status;
  1914. struct dp_pdev *pdev;
  1915. struct dp_vdev *vdev;
  1916. struct dp_soc *soc;
  1917. uint32_t *htt_status_word = (uint32_t *) status;
  1918. qdf_assert(tx_desc->pdev);
  1919. pdev = tx_desc->pdev;
  1920. vdev = tx_desc->vdev;
  1921. soc = pdev->soc;
  1922. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1923. switch (tx_status) {
  1924. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1925. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1926. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1927. {
  1928. dp_tx_comp_free_buf(soc, tx_desc);
  1929. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1930. break;
  1931. }
  1932. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1933. {
  1934. dp_tx_reinject_handler(tx_desc, status);
  1935. break;
  1936. }
  1937. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1938. {
  1939. dp_tx_inspect_handler(tx_desc, status);
  1940. break;
  1941. }
  1942. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1943. {
  1944. dp_tx_mec_handler(vdev, status);
  1945. break;
  1946. }
  1947. default:
  1948. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1949. "%s Invalid HTT tx_status %d\n",
  1950. __func__, tx_status);
  1951. break;
  1952. }
  1953. }
  1954. #ifdef MESH_MODE_SUPPORT
  1955. /**
  1956. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1957. * in mesh meta header
  1958. * @tx_desc: software descriptor head pointer
  1959. * @ts: pointer to tx completion stats
  1960. * Return: none
  1961. */
  1962. static
  1963. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1964. struct hal_tx_completion_status *ts)
  1965. {
  1966. struct meta_hdr_s *mhdr;
  1967. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1968. if (!tx_desc->msdu_ext_desc) {
  1969. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  1970. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1971. "netbuf %pK offset %d\n",
  1972. netbuf, tx_desc->pkt_offset);
  1973. return;
  1974. }
  1975. }
  1976. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1977. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1978. "netbuf %pK offset %d\n", netbuf,
  1979. sizeof(struct meta_hdr_s));
  1980. return;
  1981. }
  1982. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1983. mhdr->rssi = ts->ack_frame_rssi;
  1984. mhdr->channel = tx_desc->pdev->operating_channel;
  1985. }
  1986. #else
  1987. static
  1988. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1989. struct hal_tx_completion_status *ts)
  1990. {
  1991. }
  1992. #endif
  1993. /**
  1994. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1995. * @peer: Handle to DP peer
  1996. * @ts: pointer to HAL Tx completion stats
  1997. * @length: MSDU length
  1998. *
  1999. * Return: None
  2000. */
  2001. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2002. struct hal_tx_completion_status *ts, uint32_t length)
  2003. {
  2004. struct dp_pdev *pdev = peer->vdev->pdev;
  2005. struct dp_soc *soc = pdev->soc;
  2006. uint8_t mcs, pkt_type;
  2007. mcs = ts->mcs;
  2008. pkt_type = ts->pkt_type;
  2009. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2010. return;
  2011. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2012. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2013. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2014. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2015. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2016. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2017. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2018. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2019. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2020. return;
  2021. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2022. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2023. if (!(soc->process_tx_status))
  2024. return;
  2025. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  2026. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2027. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2028. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2029. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  2030. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2031. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2032. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2033. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  2034. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2035. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2036. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2037. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  2038. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2039. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2040. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2041. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS], 1,
  2042. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2043. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2044. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2045. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2046. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2047. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2048. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2049. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2050. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2051. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2052. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2053. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2054. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2055. &peer->stats, ts->peer_id,
  2056. UPDATE_PEER_STATS);
  2057. }
  2058. }
  2059. /**
  2060. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2061. * @tx_desc: software descriptor head pointer
  2062. * @length: packet length
  2063. *
  2064. * Return: none
  2065. */
  2066. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2067. uint32_t length)
  2068. {
  2069. struct hal_tx_completion_status ts;
  2070. struct dp_soc *soc = NULL;
  2071. struct dp_vdev *vdev = tx_desc->vdev;
  2072. struct dp_peer *peer = NULL;
  2073. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2074. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2075. "-------------------- \n"
  2076. "Tx Completion Stats: \n"
  2077. "-------------------- \n"
  2078. "ack_frame_rssi = %d \n"
  2079. "first_msdu = %d \n"
  2080. "last_msdu = %d \n"
  2081. "msdu_part_of_amsdu = %d \n"
  2082. "rate_stats valid = %d \n"
  2083. "bw = %d \n"
  2084. "pkt_type = %d \n"
  2085. "stbc = %d \n"
  2086. "ldpc = %d \n"
  2087. "sgi = %d \n"
  2088. "mcs = %d \n"
  2089. "ofdma = %d \n"
  2090. "tones_in_ru = %d \n"
  2091. "tsf = %d \n"
  2092. "ppdu_id = %d \n"
  2093. "transmit_cnt = %d \n"
  2094. "tid = %d \n"
  2095. "peer_id = %d \n",
  2096. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2097. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2098. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2099. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2100. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2101. ts.peer_id);
  2102. if (!vdev) {
  2103. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2104. "invalid vdev");
  2105. goto out;
  2106. }
  2107. soc = vdev->pdev->soc;
  2108. /* Update SoC level stats */
  2109. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2110. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2111. /* Update per-packet stats */
  2112. if (qdf_unlikely(vdev->mesh_vdev) &&
  2113. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2114. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2115. /* Update peer level stats */
  2116. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2117. if (!peer) {
  2118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2119. "invalid peer");
  2120. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2121. goto out;
  2122. }
  2123. dp_tx_update_peer_stats(peer, &ts, length);
  2124. out:
  2125. return;
  2126. }
  2127. /**
  2128. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2129. * @soc: core txrx main context
  2130. * @comp_head: software descriptor head pointer
  2131. *
  2132. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2133. * and release the software descriptors after processing is complete
  2134. *
  2135. * Return: none
  2136. */
  2137. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2138. struct dp_tx_desc_s *comp_head)
  2139. {
  2140. struct dp_tx_desc_s *desc;
  2141. struct dp_tx_desc_s *next;
  2142. struct hal_tx_completion_status ts = {0};
  2143. uint32_t length;
  2144. struct dp_peer *peer;
  2145. DP_HIST_INIT();
  2146. desc = comp_head;
  2147. while (desc) {
  2148. hal_tx_comp_get_status(&desc->comp, &ts);
  2149. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2150. length = qdf_nbuf_len(desc->nbuf);
  2151. dp_tx_comp_process_tx_status(desc, length);
  2152. dp_tx_comp_free_buf(soc, desc);
  2153. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2154. next = desc->next;
  2155. dp_tx_desc_release(desc, desc->pool_id);
  2156. desc = next;
  2157. }
  2158. DP_TX_HIST_STATS_PER_PDEV();
  2159. }
  2160. /**
  2161. * dp_tx_comp_handler() - Tx completion handler
  2162. * @soc: core txrx main context
  2163. * @ring_id: completion ring id
  2164. * @quota: No. of packets/descriptors that can be serviced in one loop
  2165. *
  2166. * This function will collect hardware release ring element contents and
  2167. * handle descriptor contents. Based on contents, free packet or handle error
  2168. * conditions
  2169. *
  2170. * Return: none
  2171. */
  2172. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2173. {
  2174. void *tx_comp_hal_desc;
  2175. uint8_t buffer_src;
  2176. uint8_t pool_id;
  2177. uint32_t tx_desc_id;
  2178. struct dp_tx_desc_s *tx_desc = NULL;
  2179. struct dp_tx_desc_s *head_desc = NULL;
  2180. struct dp_tx_desc_s *tail_desc = NULL;
  2181. uint32_t num_processed;
  2182. uint32_t count;
  2183. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2184. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2185. "%s %d : HAL RING Access Failed -- %pK\n",
  2186. __func__, __LINE__, hal_srng);
  2187. return 0;
  2188. }
  2189. num_processed = 0;
  2190. count = 0;
  2191. /* Find head descriptor from completion ring */
  2192. while (qdf_likely(tx_comp_hal_desc =
  2193. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2194. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2195. /* If this buffer was not released by TQM or FW, then it is not
  2196. * Tx completion indication, assert */
  2197. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2198. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2199. QDF_TRACE(QDF_MODULE_ID_DP,
  2200. QDF_TRACE_LEVEL_FATAL,
  2201. "Tx comp release_src != TQM | FW");
  2202. qdf_assert_always(0);
  2203. }
  2204. /* Get descriptor id */
  2205. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2206. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2207. DP_TX_DESC_ID_POOL_OS;
  2208. /* Pool ID is out of limit. Error */
  2209. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2210. soc->wlan_cfg_ctx)) {
  2211. QDF_TRACE(QDF_MODULE_ID_DP,
  2212. QDF_TRACE_LEVEL_FATAL,
  2213. "Tx Comp pool id %d not valid",
  2214. pool_id);
  2215. qdf_assert_always(0);
  2216. }
  2217. /* Find Tx descriptor */
  2218. tx_desc = dp_tx_desc_find(soc, pool_id,
  2219. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2220. DP_TX_DESC_ID_PAGE_OS,
  2221. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2222. DP_TX_DESC_ID_OFFSET_OS);
  2223. /* Pool id is not matching. Error */
  2224. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  2225. QDF_TRACE(QDF_MODULE_ID_DP,
  2226. QDF_TRACE_LEVEL_FATAL,
  2227. "Tx Comp pool id %d not matched %d",
  2228. pool_id, tx_desc->pool_id);
  2229. qdf_assert_always(0);
  2230. }
  2231. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2232. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2233. QDF_TRACE(QDF_MODULE_ID_DP,
  2234. QDF_TRACE_LEVEL_FATAL,
  2235. "Txdesc invalid, flgs = %x,id = %d",
  2236. tx_desc->flags, tx_desc_id);
  2237. qdf_assert_always(0);
  2238. }
  2239. /*
  2240. * If the release source is FW, process the HTT status
  2241. */
  2242. if (qdf_unlikely(buffer_src ==
  2243. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2244. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2245. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2246. htt_tx_status);
  2247. dp_tx_process_htt_completion(tx_desc,
  2248. htt_tx_status);
  2249. } else {
  2250. /* First ring descriptor on the cycle */
  2251. if (!head_desc) {
  2252. head_desc = tx_desc;
  2253. tail_desc = tx_desc;
  2254. }
  2255. tail_desc->next = tx_desc;
  2256. tx_desc->next = NULL;
  2257. tail_desc = tx_desc;
  2258. /* Collect hw completion contents */
  2259. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2260. &tx_desc->comp, 1);
  2261. }
  2262. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2263. /* Decrement PM usage count if the packet has been sent.*/
  2264. hif_pm_runtime_put(soc->hif_handle);
  2265. /*
  2266. * Processed packet count is more than given quota
  2267. * stop to processing
  2268. */
  2269. if ((num_processed >= quota))
  2270. break;
  2271. count++;
  2272. }
  2273. hal_srng_access_end(soc->hal_soc, hal_srng);
  2274. /* Process the reaped descriptors */
  2275. if (head_desc)
  2276. dp_tx_comp_process_desc(soc, head_desc);
  2277. return num_processed;
  2278. }
  2279. #ifdef CONVERGED_TDLS_ENABLE
  2280. /**
  2281. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2282. *
  2283. * @data_vdev - which vdev should transmit the tx data frames
  2284. * @tx_spec - what non-standard handling to apply to the tx data frames
  2285. * @msdu_list - NULL-terminated list of tx MSDUs
  2286. *
  2287. * Return: NULL on success,
  2288. * nbuf when it fails to send
  2289. */
  2290. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2291. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2292. {
  2293. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2294. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2295. vdev->is_tdls_frame = true;
  2296. return dp_tx_send(vdev_handle, msdu_list);
  2297. }
  2298. #endif
  2299. /**
  2300. * dp_tx_vdev_attach() - attach vdev to dp tx
  2301. * @vdev: virtual device instance
  2302. *
  2303. * Return: QDF_STATUS_SUCCESS: success
  2304. * QDF_STATUS_E_RESOURCES: Error return
  2305. */
  2306. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2307. {
  2308. /*
  2309. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2310. */
  2311. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2312. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2313. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2314. vdev->vdev_id);
  2315. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2316. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2317. /*
  2318. * Set HTT Extension Valid bit to 0 by default
  2319. */
  2320. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2321. dp_tx_vdev_update_search_flags(vdev);
  2322. return QDF_STATUS_SUCCESS;
  2323. }
  2324. /**
  2325. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2326. * @vdev: virtual device instance
  2327. *
  2328. * Return: void
  2329. *
  2330. */
  2331. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2332. {
  2333. /*
  2334. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2335. * for TDLS link
  2336. *
  2337. * Enable AddrY (SA based search) only for non-WDS STA and
  2338. * ProxySTA VAP modes.
  2339. *
  2340. * In all other VAP modes, only DA based search should be
  2341. * enabled
  2342. */
  2343. if (vdev->opmode == wlan_op_mode_sta &&
  2344. vdev->tdls_link_connected)
  2345. vdev->hal_desc_addr_search_flags =
  2346. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2347. else if ((vdev->opmode == wlan_op_mode_sta &&
  2348. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2349. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2350. else
  2351. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2352. }
  2353. /**
  2354. * dp_tx_vdev_detach() - detach vdev from dp tx
  2355. * @vdev: virtual device instance
  2356. *
  2357. * Return: QDF_STATUS_SUCCESS: success
  2358. * QDF_STATUS_E_RESOURCES: Error return
  2359. */
  2360. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2361. {
  2362. return QDF_STATUS_SUCCESS;
  2363. }
  2364. /**
  2365. * dp_tx_pdev_attach() - attach pdev to dp tx
  2366. * @pdev: physical device instance
  2367. *
  2368. * Return: QDF_STATUS_SUCCESS: success
  2369. * QDF_STATUS_E_RESOURCES: Error return
  2370. */
  2371. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2372. {
  2373. struct dp_soc *soc = pdev->soc;
  2374. /* Initialize Flow control counters */
  2375. qdf_atomic_init(&pdev->num_tx_exception);
  2376. qdf_atomic_init(&pdev->num_tx_outstanding);
  2377. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2378. /* Initialize descriptors in TCL Ring */
  2379. hal_tx_init_data_ring(soc->hal_soc,
  2380. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2381. }
  2382. return QDF_STATUS_SUCCESS;
  2383. }
  2384. /**
  2385. * dp_tx_pdev_detach() - detach pdev from dp tx
  2386. * @pdev: physical device instance
  2387. *
  2388. * Return: QDF_STATUS_SUCCESS: success
  2389. * QDF_STATUS_E_RESOURCES: Error return
  2390. */
  2391. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2392. {
  2393. dp_tx_me_exit(pdev);
  2394. return QDF_STATUS_SUCCESS;
  2395. }
  2396. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2397. /* Pools will be allocated dynamically */
  2398. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2399. int num_desc)
  2400. {
  2401. uint8_t i;
  2402. for (i = 0; i < num_pool; i++) {
  2403. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2404. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2405. }
  2406. return 0;
  2407. }
  2408. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2409. {
  2410. uint8_t i;
  2411. for (i = 0; i < num_pool; i++)
  2412. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2413. }
  2414. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2415. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2416. int num_desc)
  2417. {
  2418. uint8_t i;
  2419. /* Allocate software Tx descriptor pools */
  2420. for (i = 0; i < num_pool; i++) {
  2421. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2422. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2423. "%s Tx Desc Pool alloc %d failed %pK\n",
  2424. __func__, i, soc);
  2425. return ENOMEM;
  2426. }
  2427. }
  2428. return 0;
  2429. }
  2430. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2431. {
  2432. uint8_t i;
  2433. for (i = 0; i < num_pool; i++) {
  2434. if (dp_tx_desc_pool_free(soc, i)) {
  2435. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2436. "%s Tx Desc Pool Free failed\n", __func__);
  2437. }
  2438. }
  2439. }
  2440. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2441. /**
  2442. * dp_tx_soc_detach() - detach soc from dp tx
  2443. * @soc: core txrx main context
  2444. *
  2445. * This function will detach dp tx into main device context
  2446. * will free dp tx resource and initialize resources
  2447. *
  2448. * Return: QDF_STATUS_SUCCESS: success
  2449. * QDF_STATUS_E_RESOURCES: Error return
  2450. */
  2451. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2452. {
  2453. uint8_t num_pool;
  2454. uint16_t num_desc;
  2455. uint16_t num_ext_desc;
  2456. uint8_t i;
  2457. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2458. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2459. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2460. dp_tx_flow_control_deinit(soc);
  2461. dp_tx_delete_static_pools(soc, num_pool);
  2462. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2463. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2464. __func__, num_pool, num_desc);
  2465. for (i = 0; i < num_pool; i++) {
  2466. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2467. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2468. "%s Tx Ext Desc Pool Free failed\n",
  2469. __func__);
  2470. return QDF_STATUS_E_RESOURCES;
  2471. }
  2472. }
  2473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2474. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2475. __func__, num_pool, num_ext_desc);
  2476. for (i = 0; i < num_pool; i++) {
  2477. dp_tx_tso_desc_pool_free(soc, i);
  2478. }
  2479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2480. "%s TSO Desc Pool %d Free descs = %d\n",
  2481. __func__, num_pool, num_desc);
  2482. for (i = 0; i < num_pool; i++)
  2483. dp_tx_tso_num_seg_pool_free(soc, i);
  2484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2485. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2486. __func__, num_pool, num_desc);
  2487. return QDF_STATUS_SUCCESS;
  2488. }
  2489. /**
  2490. * dp_tx_soc_attach() - attach soc to dp tx
  2491. * @soc: core txrx main context
  2492. *
  2493. * This function will attach dp tx into main device context
  2494. * will allocate dp tx resource and initialize resources
  2495. *
  2496. * Return: QDF_STATUS_SUCCESS: success
  2497. * QDF_STATUS_E_RESOURCES: Error return
  2498. */
  2499. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2500. {
  2501. uint8_t i;
  2502. uint8_t num_pool;
  2503. uint32_t num_desc;
  2504. uint32_t num_ext_desc;
  2505. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2506. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2507. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2508. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2509. goto fail;
  2510. dp_tx_flow_control_init(soc);
  2511. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2512. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2513. __func__, num_pool, num_desc);
  2514. /* Allocate extension tx descriptor pools */
  2515. for (i = 0; i < num_pool; i++) {
  2516. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2517. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2518. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2519. i, soc);
  2520. goto fail;
  2521. }
  2522. }
  2523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2524. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2525. __func__, num_pool, num_ext_desc);
  2526. for (i = 0; i < num_pool; i++) {
  2527. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2528. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2529. "TSO Desc Pool alloc %d failed %pK\n",
  2530. i, soc);
  2531. goto fail;
  2532. }
  2533. }
  2534. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2535. "%s TSO Desc Alloc %d, descs = %d\n",
  2536. __func__, num_pool, num_desc);
  2537. for (i = 0; i < num_pool; i++) {
  2538. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2540. "TSO Num of seg Pool alloc %d failed %pK\n",
  2541. i, soc);
  2542. goto fail;
  2543. }
  2544. }
  2545. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2546. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2547. __func__, num_pool, num_desc);
  2548. /* Initialize descriptors in TCL Rings */
  2549. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2550. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2551. hal_tx_init_data_ring(soc->hal_soc,
  2552. soc->tcl_data_ring[i].hal_srng);
  2553. }
  2554. }
  2555. /*
  2556. * todo - Add a runtime config option to enable this.
  2557. */
  2558. /*
  2559. * Due to multiple issues on NPR EMU, enable it selectively
  2560. * only for NPR EMU, should be removed, once NPR platforms
  2561. * are stable.
  2562. */
  2563. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2564. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2565. "%s HAL Tx init Success\n", __func__);
  2566. return QDF_STATUS_SUCCESS;
  2567. fail:
  2568. /* Detach will take care of freeing only allocated resources */
  2569. dp_tx_soc_detach(soc);
  2570. return QDF_STATUS_E_RESOURCES;
  2571. }
  2572. /*
  2573. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2574. * pdev: pointer to DP PDEV structure
  2575. * seg_info_head: Pointer to the head of list
  2576. *
  2577. * return: void
  2578. */
  2579. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2580. struct dp_tx_seg_info_s *seg_info_head)
  2581. {
  2582. struct dp_tx_me_buf_t *mc_uc_buf;
  2583. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2584. qdf_nbuf_t nbuf = NULL;
  2585. uint64_t phy_addr;
  2586. while (seg_info_head) {
  2587. nbuf = seg_info_head->nbuf;
  2588. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2589. seg_info_head->frags[0].vaddr;
  2590. phy_addr = seg_info_head->frags[0].paddr_hi;
  2591. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2592. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2593. phy_addr,
  2594. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2595. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2596. qdf_nbuf_free(nbuf);
  2597. seg_info_new = seg_info_head;
  2598. seg_info_head = seg_info_head->next;
  2599. qdf_mem_free(seg_info_new);
  2600. }
  2601. }
  2602. /**
  2603. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2604. * @vdev: DP VDEV handle
  2605. * @nbuf: Multicast nbuf
  2606. * @newmac: Table of the clients to which packets have to be sent
  2607. * @new_mac_cnt: No of clients
  2608. *
  2609. * return: no of converted packets
  2610. */
  2611. uint16_t
  2612. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2613. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2614. {
  2615. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2616. struct dp_pdev *pdev = vdev->pdev;
  2617. struct ether_header *eh;
  2618. uint8_t *data;
  2619. uint16_t len;
  2620. /* reference to frame dst addr */
  2621. uint8_t *dstmac;
  2622. /* copy of original frame src addr */
  2623. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2624. /* local index into newmac */
  2625. uint8_t new_mac_idx = 0;
  2626. struct dp_tx_me_buf_t *mc_uc_buf;
  2627. qdf_nbuf_t nbuf_clone;
  2628. struct dp_tx_msdu_info_s msdu_info;
  2629. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2630. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2631. struct dp_tx_seg_info_s *seg_info_new;
  2632. struct dp_tx_frag_info_s data_frag;
  2633. qdf_dma_addr_t paddr_data;
  2634. qdf_dma_addr_t paddr_mcbuf = 0;
  2635. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2636. QDF_STATUS status;
  2637. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2638. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2639. eh = (struct ether_header *) nbuf;
  2640. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2641. len = qdf_nbuf_len(nbuf);
  2642. data = qdf_nbuf_data(nbuf);
  2643. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2644. QDF_DMA_TO_DEVICE);
  2645. if (status) {
  2646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2647. "Mapping failure Error:%d", status);
  2648. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2649. return 0;
  2650. }
  2651. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2652. /*preparing data fragment*/
  2653. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2654. data_frag.paddr_lo = (uint32_t)paddr_data;
  2655. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2656. data_frag.len = len - DP_MAC_ADDR_LEN;
  2657. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2658. dstmac = newmac[new_mac_idx];
  2659. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2660. "added mac addr (%pM)", dstmac);
  2661. /* Check for NULL Mac Address */
  2662. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2663. continue;
  2664. /* frame to self mac. skip */
  2665. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2666. continue;
  2667. /*
  2668. * TODO: optimize to avoid malloc in per-packet path
  2669. * For eg. seg_pool can be made part of vdev structure
  2670. */
  2671. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2672. if (!seg_info_new) {
  2673. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2674. "alloc failed");
  2675. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2676. goto fail_seg_alloc;
  2677. }
  2678. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2679. if (mc_uc_buf == NULL)
  2680. goto fail_buf_alloc;
  2681. /*
  2682. * TODO: Check if we need to clone the nbuf
  2683. * Or can we just use the reference for all cases
  2684. */
  2685. if (new_mac_idx < (new_mac_cnt - 1)) {
  2686. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2687. if (nbuf_clone == NULL) {
  2688. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2689. goto fail_clone;
  2690. }
  2691. } else {
  2692. /*
  2693. * Update the ref
  2694. * to account for frame sent without cloning
  2695. */
  2696. qdf_nbuf_ref(nbuf);
  2697. nbuf_clone = nbuf;
  2698. }
  2699. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2700. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2701. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2702. &paddr_mcbuf);
  2703. if (status) {
  2704. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2705. "Mapping failure Error:%d", status);
  2706. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2707. goto fail_map;
  2708. }
  2709. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2710. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2711. seg_info_new->frags[0].paddr_hi =
  2712. ((uint64_t) paddr_mcbuf >> 32);
  2713. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2714. seg_info_new->frags[1] = data_frag;
  2715. seg_info_new->nbuf = nbuf_clone;
  2716. seg_info_new->frag_cnt = 2;
  2717. seg_info_new->total_len = len;
  2718. seg_info_new->next = NULL;
  2719. if (seg_info_head == NULL)
  2720. seg_info_head = seg_info_new;
  2721. else
  2722. seg_info_tail->next = seg_info_new;
  2723. seg_info_tail = seg_info_new;
  2724. }
  2725. if (!seg_info_head)
  2726. return 0;
  2727. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2728. msdu_info.num_seg = new_mac_cnt;
  2729. msdu_info.frm_type = dp_tx_frm_me;
  2730. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2731. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2732. while (seg_info_head->next) {
  2733. seg_info_new = seg_info_head;
  2734. seg_info_head = seg_info_head->next;
  2735. qdf_mem_free(seg_info_new);
  2736. }
  2737. qdf_mem_free(seg_info_head);
  2738. return new_mac_cnt;
  2739. fail_map:
  2740. qdf_nbuf_free(nbuf_clone);
  2741. fail_clone:
  2742. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2743. fail_buf_alloc:
  2744. qdf_mem_free(seg_info_new);
  2745. fail_seg_alloc:
  2746. dp_tx_me_mem_free(pdev, seg_info_head);
  2747. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2748. return 0;
  2749. }