msm_cvp_internal.h 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _MSM_CVP_INTERNAL_H_
  6. #define _MSM_CVP_INTERNAL_H_
  7. #include <linux/atomic.h>
  8. #include <linux/list.h>
  9. #include <linux/time.h>
  10. #include <linux/types.h>
  11. #include <linux/completion.h>
  12. #include <linux/wait.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interconnect.h>
  15. #include <linux/kref.h>
  16. #include <linux/cdev.h>
  17. #include <linux/slab.h>
  18. #include <linux/kthread.h>
  19. #include <linux/dma-mapping.h>
  20. #include "msm_cvp_core.h"
  21. #include <media/msm_media_info.h>
  22. #include <media/msm_eva_private.h>
  23. #include "cvp_hfi_api.h"
  24. #include "cvp_hfi_helper.h"
  25. #include <synx_api.h>
  26. #define MAX_SUPPORTED_INSTANCES 16
  27. #define MAX_NAME_LENGTH 64
  28. #define MAX_DEBUGFS_NAME 50
  29. #define MAX_DSP_INIT_ATTEMPTS 16
  30. #define FENCE_WAIT_SIGNAL_TIMEOUT 100
  31. #define FENCE_WAIT_SIGNAL_RETRY_TIMES 20
  32. #define FENCE_BIT (1ULL << 63)
  33. #define FENCE_DMM_ICA_ENABLED_IDX 0
  34. #define FENCE_DMM_DS_IDX 1
  35. #define FENCE_DMM_OUTPUT_IDX 7
  36. #define SYS_MSG_START HAL_SYS_INIT_DONE
  37. #define SYS_MSG_END HAL_SYS_ERROR
  38. #define SESSION_MSG_START HAL_SESSION_EVENT_CHANGE
  39. #define SESSION_MSG_END HAL_SESSION_ERROR
  40. #define SYS_MSG_INDEX(__msg) (__msg - SYS_MSG_START)
  41. #define SESSION_MSG_INDEX(__msg) (__msg - SESSION_MSG_START)
  42. #define ARP_BUF_SIZE 0x300000
  43. #define CVP_RT_PRIO_THRESHOLD 1
  44. struct msm_cvp_inst;
  45. enum cvp_core_state {
  46. CVP_CORE_UNINIT = 0,
  47. CVP_CORE_INIT,
  48. CVP_CORE_INIT_DONE,
  49. };
  50. /*
  51. * Do not change the enum values unless
  52. * you know what you are doing
  53. */
  54. enum instance_state {
  55. MSM_CVP_CORE_UNINIT_DONE = 0x0001,
  56. MSM_CVP_CORE_INIT,
  57. MSM_CVP_CORE_INIT_DONE,
  58. MSM_CVP_OPEN,
  59. MSM_CVP_OPEN_DONE,
  60. MSM_CVP_CLOSE,
  61. MSM_CVP_CLOSE_DONE,
  62. MSM_CVP_CORE_UNINIT,
  63. MSM_CVP_CORE_INVALID
  64. };
  65. enum dsp_state {
  66. DSP_INVALID,
  67. DSP_UNINIT,
  68. DSP_PROBED,
  69. DSP_READY,
  70. DSP_SUSPEND,
  71. DSP_INACTIVE,
  72. };
  73. struct msm_cvp_common_data {
  74. char key[128];
  75. int value;
  76. };
  77. enum sku_version {
  78. SKU_VERSION_0 = 0,
  79. SKU_VERSION_1,
  80. SKU_VERSION_2,
  81. };
  82. enum vpu_version {
  83. VPU_VERSION_4 = 1,
  84. VPU_VERSION_5,
  85. };
  86. struct msm_cvp_ubwc_config_data {
  87. struct {
  88. u32 max_channel_override : 1;
  89. u32 mal_length_override : 1;
  90. u32 hb_override : 1;
  91. u32 bank_swzl_level_override : 1;
  92. u32 bank_spreading_override : 1;
  93. u32 reserved : 27;
  94. } override_bit_info;
  95. u32 max_channels;
  96. u32 mal_length;
  97. u32 highest_bank_bit;
  98. u32 bank_swzl_level;
  99. u32 bank_spreading;
  100. };
  101. struct msm_cvp_platform_data {
  102. struct msm_cvp_common_data *common_data;
  103. unsigned int common_data_length;
  104. unsigned int sku_version;
  105. uint32_t vpu_ver;
  106. struct msm_cvp_ubwc_config_data *ubwc_config;
  107. };
  108. struct msm_cvp_drv {
  109. struct mutex lock;
  110. struct list_head cores;
  111. int num_cores;
  112. struct dentry *debugfs_root;
  113. int thermal_level;
  114. u32 sku_version;
  115. struct kmem_cache *msg_cache;
  116. struct kmem_cache *frame_cache;
  117. struct kmem_cache *buf_cache;
  118. struct kmem_cache *smem_cache;
  119. char fw_version[CVP_VERSION_LENGTH];
  120. };
  121. enum profiling_points {
  122. SYS_INIT = 0,
  123. SESSION_INIT,
  124. LOAD_RESOURCES,
  125. FRAME_PROCESSING,
  126. FW_IDLE,
  127. MAX_PROFILING_POINTS,
  128. };
  129. struct cvp_clock_data {
  130. int buffer_counter;
  131. int load;
  132. int load_low;
  133. int load_norm;
  134. int load_high;
  135. int min_threshold;
  136. int max_threshold;
  137. unsigned long bitrate;
  138. unsigned long min_freq;
  139. unsigned long curr_freq;
  140. u32 ddr_bw;
  141. u32 sys_cache_bw;
  142. u32 operating_rate;
  143. u32 core_id;
  144. bool low_latency_mode;
  145. bool turbo_mode;
  146. };
  147. struct cvp_profile_data {
  148. int start;
  149. int stop;
  150. int cumulative;
  151. char name[64];
  152. int sampling;
  153. int average;
  154. };
  155. struct msm_cvp_debug {
  156. struct cvp_profile_data pdata[MAX_PROFILING_POINTS];
  157. int profile;
  158. int samples;
  159. };
  160. enum msm_cvp_modes {
  161. CVP_SECURE = BIT(0),
  162. CVP_TURBO = BIT(1),
  163. CVP_THUMBNAIL = BIT(2),
  164. CVP_LOW_POWER = BIT(3),
  165. CVP_REALTIME = BIT(4),
  166. };
  167. #define MAX_NUM_MSGS_PER_SESSION 128
  168. #define CVP_MAX_WAIT_TIME 2000
  169. struct cvp_session_msg {
  170. struct list_head node;
  171. struct cvp_hfi_msg_session_hdr_ext pkt;
  172. };
  173. struct cvp_session_queue {
  174. spinlock_t lock;
  175. enum queue_state state;
  176. unsigned int msg_count;
  177. struct list_head msgs;
  178. wait_queue_head_t wq;
  179. };
  180. #define CVP_CYCLE_STAT_SIZE 8
  181. struct cvp_cycle_stat {
  182. u32 busy[CVP_CYCLE_STAT_SIZE];
  183. u32 total;
  184. u32 idx;
  185. u32 size;
  186. };
  187. struct cvp_cycle_info {
  188. u32 sum_fps[HFI_MAX_HW_THREADS];
  189. u32 hi_ctrl_lim[HFI_MAX_HW_THREADS];
  190. u32 lo_ctrl_lim[HFI_MAX_HW_THREADS];
  191. struct cvp_cycle_stat cycle[HFI_MAX_HW_THREADS];
  192. unsigned long conf_freq;
  193. };
  194. struct cvp_session_prop {
  195. u32 type;
  196. u32 kernel_mask;
  197. u32 priority;
  198. u32 is_secure;
  199. u32 dsp_mask;
  200. u32 fthread_nr;
  201. u32 fdu_cycles;
  202. u32 od_cycles;
  203. u32 mpu_cycles;
  204. u32 ica_cycles;
  205. u32 fw_cycles;
  206. u32 fdu_op_cycles;
  207. u32 od_op_cycles;
  208. u32 mpu_op_cycles;
  209. u32 ica_op_cycles;
  210. u32 fw_op_cycles;
  211. u32 ddr_bw;
  212. u32 ddr_op_bw;
  213. u32 ddr_cache;
  214. u32 ddr_op_cache;
  215. u32 fps[HFI_MAX_HW_THREADS];
  216. };
  217. enum cvp_event_t {
  218. CVP_NO_EVENT,
  219. CVP_SSR_EVENT = 1,
  220. CVP_SYS_ERROR_EVENT,
  221. CVP_MAX_CLIENTS_EVENT,
  222. CVP_HW_UNSUPPORTED_EVENT,
  223. CVP_INVALID_EVENT,
  224. };
  225. struct cvp_session_event {
  226. spinlock_t lock;
  227. enum cvp_event_t event;
  228. wait_queue_head_t wq;
  229. };
  230. struct msm_cvp_core {
  231. struct list_head list;
  232. struct mutex lock;
  233. struct mutex clk_lock;
  234. int id;
  235. dev_t dev_num;
  236. struct cdev cdev;
  237. struct class *class;
  238. struct device *dev;
  239. struct cvp_hfi_device *device;
  240. struct msm_cvp_platform_data *platform_data;
  241. struct list_head instances;
  242. struct dentry *debugfs_root;
  243. enum cvp_core_state state;
  244. struct completion completions[SYS_MSG_END - SYS_MSG_START + 1];
  245. enum msm_cvp_hfi_type hfi_type;
  246. struct msm_cvp_platform_resources resources;
  247. struct msm_cvp_capability *capabilities;
  248. struct delayed_work fw_unload_work;
  249. struct work_struct ssr_work;
  250. enum hal_ssr_trigger_type ssr_type;
  251. bool smmu_fault_handled;
  252. u32 last_fault_addr;
  253. bool trigger_ssr;
  254. unsigned long curr_freq;
  255. struct cvp_cycle_info dyn_clk;
  256. atomic64_t kernel_trans_id;
  257. };
  258. struct msm_cvp_inst {
  259. struct list_head list;
  260. struct list_head dsp_list;
  261. struct mutex sync_lock, lock;
  262. struct msm_cvp_core *core;
  263. enum session_type session_type;
  264. u32 process_id;
  265. struct task_struct *task;
  266. struct cvp_session_queue session_queue;
  267. struct cvp_session_queue session_queue_fence;
  268. struct cvp_session_event event_handler;
  269. void *session;
  270. enum instance_state state;
  271. struct msm_cvp_list freqs;
  272. struct msm_cvp_list persistbufs;
  273. struct cvp_dmamap_cache dma_cache;
  274. struct msm_cvp_list cvpdspbufs;
  275. struct msm_cvp_list frames;
  276. struct completion completions[SESSION_MSG_END - SESSION_MSG_START + 1];
  277. struct dentry *debugfs_root;
  278. struct msm_cvp_debug debug;
  279. struct cvp_clock_data clk_data;
  280. enum msm_cvp_modes flags;
  281. struct msm_cvp_capability capability;
  282. struct kref kref;
  283. struct cvp_session_prop prop;
  284. u32 cur_cmd_type;
  285. struct synx_session synx_session_id;
  286. struct cvp_fence_queue fence_cmd_queue;
  287. };
  288. extern struct msm_cvp_drv *cvp_driver;
  289. void cvp_handle_cmd_response(enum hal_command_response cmd, void *data);
  290. int msm_cvp_trigger_ssr(struct msm_cvp_core *core,
  291. enum hal_ssr_trigger_type type);
  292. int msm_cvp_noc_error_info(struct msm_cvp_core *core);
  293. void msm_cvp_comm_handle_thermal_event(void);
  294. void msm_cvp_fw_unload_handler(struct work_struct *work);
  295. void msm_cvp_ssr_handler(struct work_struct *work);
  296. /*
  297. * XXX: normally should be in msm_cvp_core.h, but that's meant for public APIs,
  298. * whereas this is private
  299. */
  300. int msm_cvp_destroy(struct msm_cvp_inst *inst);
  301. void *cvp_get_drv_data(struct device *dev);
  302. #endif