qcs405.c 250 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include <asoc/msm-cdc-pinctrl.h>
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. SEN_AUX_PCM,
  104. AUX_PCM_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_RX_0 = 0,
  108. WSA_CDC_DMA_RX_1,
  109. CDC_DMA_RX_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_TX_0 = 0,
  113. WSA_CDC_DMA_TX_1,
  114. WSA_CDC_DMA_TX_2,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. PRIM_SPDIF_RX = 0,
  121. SEC_SPDIF_RX,
  122. SPDIF_RX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_TX = 0,
  126. SEC_SPDIF_TX,
  127. SPDIF_TX_MAX,
  128. };
  129. struct mi2s_conf {
  130. struct mutex lock;
  131. u32 ref_cnt;
  132. u32 msm_is_mi2s_master;
  133. };
  134. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  135. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  136. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  161. struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */
  162. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  163. int dmic_01_gpio_cnt;
  164. int dmic_23_gpio_cnt;
  165. int dmic_45_gpio_cnt;
  166. int dmic_67_gpio_cnt;
  167. struct regulator *tdm_micb_supply;
  168. u32 tdm_micb_voltage;
  169. u32 tdm_micb_current;
  170. bool codec_is_csra;
  171. };
  172. struct msm_asoc_wcd93xx_codec {
  173. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  174. enum afe_config_type config_type);
  175. };
  176. static const char *const pin_states[] = {"sleep", "i2s-active",
  177. "tdm-active"};
  178. enum {
  179. TDM_0 = 0,
  180. TDM_1,
  181. TDM_2,
  182. TDM_3,
  183. TDM_4,
  184. TDM_5,
  185. TDM_6,
  186. TDM_7,
  187. TDM_PORT_MAX,
  188. };
  189. enum {
  190. TDM_PRI = 0,
  191. TDM_SEC,
  192. TDM_TERT,
  193. TDM_QUAT,
  194. TDM_QUIN,
  195. TDM_INTERFACE_MAX,
  196. };
  197. struct tdm_port {
  198. u32 mode;
  199. u32 channel;
  200. };
  201. /* TDM default config */
  202. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  203. { /* PRI TDM */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  212. },
  213. { /* SEC TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* TERT TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* QUAT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUIN TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. }
  253. };
  254. /* TDM default config */
  255. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  256. { /* PRI TDM */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  265. },
  266. { /* SEC TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* TERT TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* QUAT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUIN TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. }
  306. };
  307. /* Default configuration of slimbus channels */
  308. static struct dev_config slim_rx_cfg[] = {
  309. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. };
  318. static struct dev_config slim_tx_cfg[] = {
  319. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. };
  330. /* Default configuration of Codec DMA Interface Tx */
  331. static struct dev_config cdc_dma_rx_cfg[] = {
  332. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. };
  335. /* Default configuration of Codec DMA Interface Rx */
  336. static struct dev_config cdc_dma_tx_cfg[] = {
  337. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  342. };
  343. static struct dev_config usb_rx_cfg = {
  344. .sample_rate = SAMPLING_RATE_48KHZ,
  345. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  346. .channels = 2,
  347. };
  348. static struct dev_config usb_tx_cfg = {
  349. .sample_rate = SAMPLING_RATE_48KHZ,
  350. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  351. .channels = 1,
  352. };
  353. static struct dev_config proxy_rx_cfg = {
  354. .sample_rate = SAMPLING_RATE_48KHZ,
  355. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  356. .channels = 2,
  357. };
  358. /* Default configuration of MI2S channels */
  359. static struct dev_config mi2s_rx_cfg[] = {
  360. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  366. };
  367. /* Default configuration of SPDIF channels */
  368. static struct dev_config spdif_rx_cfg[] = {
  369. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. };
  372. static struct dev_config spdif_tx_cfg[] = {
  373. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  375. };
  376. static struct dev_config mi2s_tx_cfg[] = {
  377. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  383. };
  384. static struct dev_config aux_pcm_rx_cfg[] = {
  385. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. };
  392. static struct dev_config aux_pcm_tx_cfg[] = {
  393. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. };
  400. static struct dev_config afe_lb_tx_cfg = {
  401. .sample_rate = SAMPLING_RATE_48KHZ,
  402. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  403. .channels = 2,
  404. };
  405. static int msm_vi_feed_tx_ch = 2;
  406. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  407. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  408. "Five", "Six", "Seven",
  409. "Eight"};
  410. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  411. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  412. "S32_LE"};
  413. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  414. "KHZ_32", "KHZ_44P1", "KHZ_48",
  415. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  416. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  417. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  418. "KHZ_44P1", "KHZ_48",
  419. "KHZ_88P2", "KHZ_96"};
  420. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  421. "Five", "Six", "Seven",
  422. "Eight"};
  423. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  424. "Six", "Seven", "Eight"};
  425. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  426. "KHZ_16", "KHZ_22P05",
  427. "KHZ_32", "KHZ_44P1", "KHZ_48",
  428. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  429. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  430. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  431. "Five", "Six", "Seven", "Eight"};
  432. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  433. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  434. "KHZ_48", "KHZ_176P4",
  435. "KHZ_352P8"};
  436. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  437. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  438. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  439. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  440. static const char *const mi2s_ch_text[] = {
  441. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  442. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  443. "Fourteen", "Fifteen", "Sixteen"
  444. };
  445. static const char *const qos_text[] = {"Disable", "Enable"};
  446. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  447. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  448. "Five", "Six", "Seven",
  449. "Eight"};
  450. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  451. "KHZ_16", "KHZ_22P05",
  452. "KHZ_32", "KHZ_44P1", "KHZ_48",
  453. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  454. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  455. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  456. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  457. "KHZ_192"};
  458. static const char *spdif_ch_text[] = {"One", "Two"};
  459. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  545. cdc_dma_sample_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  547. cdc_dma_sample_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  549. cdc_dma_sample_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  551. cdc_dma_sample_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  553. cdc_dma_sample_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  555. cdc_dma_sample_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  557. cdc_dma_sample_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_chs, cdc_dma_tx_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_format, bit_format_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_sample_rate,
  567. cdc_dma_sample_rate_text);
  568. static struct platform_device *spdev;
  569. static bool is_initial_boot;
  570. static bool codec_reg_done;
  571. static struct snd_soc_aux_dev *msm_aux_dev;
  572. static struct snd_soc_codec_conf *msm_codec_conf;
  573. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  574. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  575. int enable, bool dapm);
  576. static int msm_wsa881x_init(struct snd_soc_component *component);
  577. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  578. struct snd_ctl_elem_value *ucontrol);
  579. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  580. {"MIC BIAS1", NULL, "MCLK TX"},
  581. {"MIC BIAS2", NULL, "MCLK TX"},
  582. {"MIC BIAS3", NULL, "MCLK TX"},
  583. {"MIC BIAS4", NULL, "MCLK TX"},
  584. };
  585. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  586. {
  587. AFE_API_VERSION_I2S_CONFIG,
  588. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  589. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  590. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  591. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  592. 0,
  593. },
  594. {
  595. AFE_API_VERSION_I2S_CONFIG,
  596. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  597. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  598. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  599. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  600. 0,
  601. },
  602. {
  603. AFE_API_VERSION_I2S_CONFIG,
  604. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  605. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  606. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  607. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  608. 0,
  609. },
  610. {
  611. AFE_API_VERSION_I2S_CONFIG,
  612. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  613. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  614. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  615. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  616. 0,
  617. },
  618. {
  619. AFE_API_VERSION_I2S_CONFIG,
  620. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  621. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  622. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  623. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  624. 0,
  625. },
  626. {
  627. AFE_API_VERSION_I2S_CONFIG,
  628. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  629. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  630. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  631. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  632. 0,
  633. }
  634. };
  635. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  636. static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  637. {
  638. *port_id = 0xFFFF;
  639. switch (be_id) {
  640. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  641. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  642. break;
  643. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  644. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  645. break;
  646. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  647. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  648. break;
  649. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  650. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  651. break;
  652. default:
  653. return -EINVAL;
  654. }
  655. return 0;
  656. }
  657. static int qcs405_send_island_vad_config(int32_t be_id)
  658. {
  659. int rc = 0;
  660. int port_id = 0xFFFF;
  661. rc = msm_island_vad_get_portid_from_beid(be_id, &port_id);
  662. if (rc) {
  663. pr_debug("%s: Invalid island interface\n", __func__);
  664. } else {
  665. /*
  666. * send island mode config
  667. * This should be the first configuration
  668. */
  669. rc = afe_send_port_island_mode(port_id);
  670. if (rc) {
  671. pr_err("%s: afe send island mode failed %d\n",
  672. __func__, rc);
  673. return rc;
  674. }
  675. rc = afe_send_port_vad_cfg_params(port_id);
  676. if (rc) {
  677. pr_err("%s: afe send vad config failed %d\n",
  678. __func__, rc);
  679. return rc;
  680. }
  681. }
  682. return 0;
  683. }
  684. static int slim_get_sample_rate_val(int sample_rate)
  685. {
  686. int sample_rate_val = 0;
  687. switch (sample_rate) {
  688. case SAMPLING_RATE_8KHZ:
  689. sample_rate_val = 0;
  690. break;
  691. case SAMPLING_RATE_16KHZ:
  692. sample_rate_val = 1;
  693. break;
  694. case SAMPLING_RATE_32KHZ:
  695. sample_rate_val = 2;
  696. break;
  697. case SAMPLING_RATE_44P1KHZ:
  698. sample_rate_val = 3;
  699. break;
  700. case SAMPLING_RATE_48KHZ:
  701. sample_rate_val = 4;
  702. break;
  703. case SAMPLING_RATE_88P2KHZ:
  704. sample_rate_val = 5;
  705. break;
  706. case SAMPLING_RATE_96KHZ:
  707. sample_rate_val = 6;
  708. break;
  709. case SAMPLING_RATE_176P4KHZ:
  710. sample_rate_val = 7;
  711. break;
  712. case SAMPLING_RATE_192KHZ:
  713. sample_rate_val = 8;
  714. break;
  715. case SAMPLING_RATE_352P8KHZ:
  716. sample_rate_val = 9;
  717. break;
  718. case SAMPLING_RATE_384KHZ:
  719. sample_rate_val = 10;
  720. break;
  721. default:
  722. sample_rate_val = 4;
  723. break;
  724. }
  725. return sample_rate_val;
  726. }
  727. static int slim_get_sample_rate(int value)
  728. {
  729. int sample_rate = 0;
  730. switch (value) {
  731. case 0:
  732. sample_rate = SAMPLING_RATE_8KHZ;
  733. break;
  734. case 1:
  735. sample_rate = SAMPLING_RATE_16KHZ;
  736. break;
  737. case 2:
  738. sample_rate = SAMPLING_RATE_32KHZ;
  739. break;
  740. case 3:
  741. sample_rate = SAMPLING_RATE_44P1KHZ;
  742. break;
  743. case 4:
  744. sample_rate = SAMPLING_RATE_48KHZ;
  745. break;
  746. case 5:
  747. sample_rate = SAMPLING_RATE_88P2KHZ;
  748. break;
  749. case 6:
  750. sample_rate = SAMPLING_RATE_96KHZ;
  751. break;
  752. case 7:
  753. sample_rate = SAMPLING_RATE_176P4KHZ;
  754. break;
  755. case 8:
  756. sample_rate = SAMPLING_RATE_192KHZ;
  757. break;
  758. case 9:
  759. sample_rate = SAMPLING_RATE_352P8KHZ;
  760. break;
  761. case 10:
  762. sample_rate = SAMPLING_RATE_384KHZ;
  763. break;
  764. default:
  765. sample_rate = SAMPLING_RATE_48KHZ;
  766. break;
  767. }
  768. return sample_rate;
  769. }
  770. static int slim_get_bit_format_val(int bit_format)
  771. {
  772. int val = 0;
  773. switch (bit_format) {
  774. case SNDRV_PCM_FORMAT_S32_LE:
  775. val = 3;
  776. break;
  777. case SNDRV_PCM_FORMAT_S24_3LE:
  778. val = 2;
  779. break;
  780. case SNDRV_PCM_FORMAT_S24_LE:
  781. val = 1;
  782. break;
  783. case SNDRV_PCM_FORMAT_S16_LE:
  784. default:
  785. val = 0;
  786. break;
  787. }
  788. return val;
  789. }
  790. static int slim_get_bit_format(int val)
  791. {
  792. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  793. switch (val) {
  794. case 0:
  795. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  796. break;
  797. case 1:
  798. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  799. break;
  800. case 2:
  801. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  802. break;
  803. case 3:
  804. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  805. break;
  806. default:
  807. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  808. break;
  809. }
  810. return bit_fmt;
  811. }
  812. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  813. {
  814. int port_id = 0;
  815. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  816. port_id = SLIM_RX_0;
  817. } else if (strnstr(kcontrol->id.name,
  818. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  819. port_id = SLIM_RX_2;
  820. } else if (strnstr(kcontrol->id.name,
  821. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  822. port_id = SLIM_RX_5;
  823. } else if (strnstr(kcontrol->id.name,
  824. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  825. port_id = SLIM_RX_6;
  826. } else if (strnstr(kcontrol->id.name,
  827. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  828. port_id = SLIM_TX_0;
  829. } else if (strnstr(kcontrol->id.name,
  830. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  831. port_id = SLIM_TX_1;
  832. } else {
  833. pr_err("%s: unsupported channel: %s",
  834. __func__, kcontrol->id.name);
  835. return -EINVAL;
  836. }
  837. return port_id;
  838. }
  839. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  840. struct snd_ctl_elem_value *ucontrol)
  841. {
  842. int ch_num = slim_get_port_idx(kcontrol);
  843. if (ch_num < 0)
  844. return ch_num;
  845. ucontrol->value.enumerated.item[0] =
  846. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  847. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  848. ch_num, slim_rx_cfg[ch_num].sample_rate,
  849. ucontrol->value.enumerated.item[0]);
  850. return 0;
  851. }
  852. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. int ch_num = slim_get_port_idx(kcontrol);
  856. if (ch_num < 0)
  857. return ch_num;
  858. slim_rx_cfg[ch_num].sample_rate =
  859. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  860. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  861. ch_num, slim_rx_cfg[ch_num].sample_rate,
  862. ucontrol->value.enumerated.item[0]);
  863. return 0;
  864. }
  865. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. int ch_num = slim_get_port_idx(kcontrol);
  869. if (ch_num < 0)
  870. return ch_num;
  871. ucontrol->value.enumerated.item[0] =
  872. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  873. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  874. ch_num, slim_tx_cfg[ch_num].sample_rate,
  875. ucontrol->value.enumerated.item[0]);
  876. return 0;
  877. }
  878. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. int sample_rate = 0;
  882. int ch_num = slim_get_port_idx(kcontrol);
  883. if (ch_num < 0)
  884. return ch_num;
  885. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  886. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  887. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  888. __func__, sample_rate);
  889. return -EINVAL;
  890. }
  891. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  892. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  893. ch_num, slim_tx_cfg[ch_num].sample_rate,
  894. ucontrol->value.enumerated.item[0]);
  895. return 0;
  896. }
  897. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  898. struct snd_ctl_elem_value *ucontrol)
  899. {
  900. int ch_num = slim_get_port_idx(kcontrol);
  901. if (ch_num < 0)
  902. return ch_num;
  903. ucontrol->value.enumerated.item[0] =
  904. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  905. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  906. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  907. ucontrol->value.enumerated.item[0]);
  908. return 0;
  909. }
  910. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_value *ucontrol)
  912. {
  913. int ch_num = slim_get_port_idx(kcontrol);
  914. if (ch_num < 0)
  915. return ch_num;
  916. slim_rx_cfg[ch_num].bit_format =
  917. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  918. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  919. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  920. ucontrol->value.enumerated.item[0]);
  921. return 0;
  922. }
  923. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  924. struct snd_ctl_elem_value *ucontrol)
  925. {
  926. int ch_num = slim_get_port_idx(kcontrol);
  927. if (ch_num < 0)
  928. return ch_num;
  929. ucontrol->value.enumerated.item[0] =
  930. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  931. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  932. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  933. ucontrol->value.enumerated.item[0]);
  934. return 0;
  935. }
  936. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  937. struct snd_ctl_elem_value *ucontrol)
  938. {
  939. int ch_num = slim_get_port_idx(kcontrol);
  940. if (ch_num < 0)
  941. return ch_num;
  942. slim_tx_cfg[ch_num].bit_format =
  943. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  944. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  945. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  946. ucontrol->value.enumerated.item[0]);
  947. return 0;
  948. }
  949. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  950. struct snd_ctl_elem_value *ucontrol)
  951. {
  952. int ch_num = slim_get_port_idx(kcontrol);
  953. if (ch_num < 0)
  954. return ch_num;
  955. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  956. ch_num, slim_rx_cfg[ch_num].channels);
  957. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  958. return 0;
  959. }
  960. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  961. struct snd_ctl_elem_value *ucontrol)
  962. {
  963. int ch_num = slim_get_port_idx(kcontrol);
  964. if (ch_num < 0)
  965. return ch_num;
  966. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  967. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  968. ch_num, slim_rx_cfg[ch_num].channels);
  969. return 1;
  970. }
  971. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  972. struct snd_ctl_elem_value *ucontrol)
  973. {
  974. int ch_num = slim_get_port_idx(kcontrol);
  975. if (ch_num < 0)
  976. return ch_num;
  977. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  978. ch_num, slim_tx_cfg[ch_num].channels);
  979. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  980. return 0;
  981. }
  982. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  983. struct snd_ctl_elem_value *ucontrol)
  984. {
  985. int ch_num = slim_get_port_idx(kcontrol);
  986. if (ch_num < 0)
  987. return ch_num;
  988. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  989. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  990. ch_num, slim_tx_cfg[ch_num].channels);
  991. return 1;
  992. }
  993. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  994. struct snd_ctl_elem_value *ucontrol)
  995. {
  996. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  997. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  998. ucontrol->value.integer.value[0]);
  999. return 0;
  1000. }
  1001. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1002. struct snd_ctl_elem_value *ucontrol)
  1003. {
  1004. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1005. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1006. return 1;
  1007. }
  1008. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  1009. struct snd_ctl_elem_value *ucontrol)
  1010. {
  1011. /*
  1012. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  1013. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  1014. * value.
  1015. */
  1016. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  1017. case SAMPLING_RATE_96KHZ:
  1018. ucontrol->value.integer.value[0] = 5;
  1019. break;
  1020. case SAMPLING_RATE_88P2KHZ:
  1021. ucontrol->value.integer.value[0] = 4;
  1022. break;
  1023. case SAMPLING_RATE_48KHZ:
  1024. ucontrol->value.integer.value[0] = 3;
  1025. break;
  1026. case SAMPLING_RATE_44P1KHZ:
  1027. ucontrol->value.integer.value[0] = 2;
  1028. break;
  1029. case SAMPLING_RATE_16KHZ:
  1030. ucontrol->value.integer.value[0] = 1;
  1031. break;
  1032. case SAMPLING_RATE_8KHZ:
  1033. default:
  1034. ucontrol->value.integer.value[0] = 0;
  1035. break;
  1036. }
  1037. pr_debug("%s: sample rate = %d", __func__,
  1038. slim_rx_cfg[SLIM_RX_7].sample_rate);
  1039. return 0;
  1040. }
  1041. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  1042. struct snd_ctl_elem_value *ucontrol)
  1043. {
  1044. switch (ucontrol->value.integer.value[0]) {
  1045. case 1:
  1046. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1047. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1048. break;
  1049. case 2:
  1050. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1051. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1052. break;
  1053. case 3:
  1054. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1055. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1056. break;
  1057. case 4:
  1058. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1059. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1060. break;
  1061. case 5:
  1062. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1063. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1064. break;
  1065. case 0:
  1066. default:
  1067. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1068. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1069. break;
  1070. }
  1071. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1072. __func__,
  1073. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1074. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1075. ucontrol->value.enumerated.item[0]);
  1076. return 0;
  1077. }
  1078. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1079. struct snd_ctl_elem_value *ucontrol)
  1080. {
  1081. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1082. case SAMPLING_RATE_96KHZ:
  1083. ucontrol->value.integer.value[0] = 5;
  1084. break;
  1085. case SAMPLING_RATE_88P2KHZ:
  1086. ucontrol->value.integer.value[0] = 4;
  1087. break;
  1088. case SAMPLING_RATE_48KHZ:
  1089. ucontrol->value.integer.value[0] = 3;
  1090. break;
  1091. case SAMPLING_RATE_44P1KHZ:
  1092. ucontrol->value.integer.value[0] = 2;
  1093. break;
  1094. case SAMPLING_RATE_16KHZ:
  1095. ucontrol->value.integer.value[0] = 1;
  1096. break;
  1097. case SAMPLING_RATE_8KHZ:
  1098. default:
  1099. ucontrol->value.integer.value[0] = 0;
  1100. break;
  1101. }
  1102. pr_debug("%s: sample rate = %d", __func__,
  1103. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1104. return 0;
  1105. }
  1106. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1107. struct snd_ctl_elem_value *ucontrol)
  1108. {
  1109. switch (ucontrol->value.integer.value[0]) {
  1110. case 1:
  1111. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1112. break;
  1113. case 2:
  1114. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1115. break;
  1116. case 3:
  1117. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1118. break;
  1119. case 4:
  1120. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1121. break;
  1122. case 5:
  1123. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1124. break;
  1125. case 0:
  1126. default:
  1127. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1128. break;
  1129. }
  1130. pr_debug("%s: sample rate = %d, value = %d\n",
  1131. __func__,
  1132. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1133. ucontrol->value.enumerated.item[0]);
  1134. return 0;
  1135. }
  1136. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1137. {
  1138. int idx = 0;
  1139. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1140. sizeof("WSA_CDC_DMA_RX_0")))
  1141. idx = WSA_CDC_DMA_RX_0;
  1142. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1143. sizeof("WSA_CDC_DMA_RX_0")))
  1144. idx = WSA_CDC_DMA_RX_1;
  1145. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1146. sizeof("WSA_CDC_DMA_TX_0")))
  1147. idx = WSA_CDC_DMA_TX_0;
  1148. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1149. sizeof("WSA_CDC_DMA_TX_1")))
  1150. idx = WSA_CDC_DMA_TX_1;
  1151. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1152. sizeof("WSA_CDC_DMA_TX_2")))
  1153. idx = WSA_CDC_DMA_TX_2;
  1154. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1155. sizeof("VA_CDC_DMA_TX_0")))
  1156. idx = VA_CDC_DMA_TX_0;
  1157. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1158. sizeof("VA_CDC_DMA_TX_1")))
  1159. idx = VA_CDC_DMA_TX_1;
  1160. else {
  1161. pr_err("%s: unsupported port: %s\n",
  1162. __func__, kcontrol->id.name);
  1163. return -EINVAL;
  1164. }
  1165. return idx;
  1166. }
  1167. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1168. struct snd_ctl_elem_value *ucontrol)
  1169. {
  1170. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1171. if (ch_num < 0)
  1172. return ch_num;
  1173. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1174. cdc_dma_rx_cfg[ch_num].channels - 1);
  1175. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1176. return 0;
  1177. }
  1178. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1179. struct snd_ctl_elem_value *ucontrol)
  1180. {
  1181. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1182. if (ch_num < 0)
  1183. return ch_num;
  1184. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1185. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1186. cdc_dma_rx_cfg[ch_num].channels);
  1187. return 1;
  1188. }
  1189. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1190. struct snd_ctl_elem_value *ucontrol)
  1191. {
  1192. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1193. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1194. case SNDRV_PCM_FORMAT_S32_LE:
  1195. ucontrol->value.integer.value[0] = 3;
  1196. break;
  1197. case SNDRV_PCM_FORMAT_S24_3LE:
  1198. ucontrol->value.integer.value[0] = 2;
  1199. break;
  1200. case SNDRV_PCM_FORMAT_S24_LE:
  1201. ucontrol->value.integer.value[0] = 1;
  1202. break;
  1203. case SNDRV_PCM_FORMAT_S16_LE:
  1204. default:
  1205. ucontrol->value.integer.value[0] = 0;
  1206. break;
  1207. }
  1208. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1209. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1210. ucontrol->value.integer.value[0]);
  1211. return 0;
  1212. }
  1213. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1214. struct snd_ctl_elem_value *ucontrol)
  1215. {
  1216. int rc = 0;
  1217. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1218. switch (ucontrol->value.integer.value[0]) {
  1219. case 3:
  1220. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1221. break;
  1222. case 2:
  1223. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1224. break;
  1225. case 1:
  1226. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1227. break;
  1228. case 0:
  1229. default:
  1230. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1231. break;
  1232. }
  1233. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1234. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1235. ucontrol->value.integer.value[0]);
  1236. return rc;
  1237. }
  1238. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1239. {
  1240. int sample_rate_val = 0;
  1241. switch (sample_rate) {
  1242. case SAMPLING_RATE_8KHZ:
  1243. sample_rate_val = 0;
  1244. break;
  1245. case SAMPLING_RATE_11P025KHZ:
  1246. sample_rate_val = 1;
  1247. break;
  1248. case SAMPLING_RATE_16KHZ:
  1249. sample_rate_val = 2;
  1250. break;
  1251. case SAMPLING_RATE_22P05KHZ:
  1252. sample_rate_val = 3;
  1253. break;
  1254. case SAMPLING_RATE_32KHZ:
  1255. sample_rate_val = 4;
  1256. break;
  1257. case SAMPLING_RATE_44P1KHZ:
  1258. sample_rate_val = 5;
  1259. break;
  1260. case SAMPLING_RATE_48KHZ:
  1261. sample_rate_val = 6;
  1262. break;
  1263. case SAMPLING_RATE_88P2KHZ:
  1264. sample_rate_val = 7;
  1265. break;
  1266. case SAMPLING_RATE_96KHZ:
  1267. sample_rate_val = 8;
  1268. break;
  1269. case SAMPLING_RATE_176P4KHZ:
  1270. sample_rate_val = 9;
  1271. break;
  1272. case SAMPLING_RATE_192KHZ:
  1273. sample_rate_val = 10;
  1274. break;
  1275. case SAMPLING_RATE_352P8KHZ:
  1276. sample_rate_val = 11;
  1277. break;
  1278. case SAMPLING_RATE_384KHZ:
  1279. sample_rate_val = 12;
  1280. break;
  1281. default:
  1282. sample_rate_val = 6;
  1283. break;
  1284. }
  1285. return sample_rate_val;
  1286. }
  1287. static int cdc_dma_get_sample_rate(int value)
  1288. {
  1289. int sample_rate = 0;
  1290. switch (value) {
  1291. case 0:
  1292. sample_rate = SAMPLING_RATE_8KHZ;
  1293. break;
  1294. case 1:
  1295. sample_rate = SAMPLING_RATE_11P025KHZ;
  1296. break;
  1297. case 2:
  1298. sample_rate = SAMPLING_RATE_16KHZ;
  1299. break;
  1300. case 3:
  1301. sample_rate = SAMPLING_RATE_22P05KHZ;
  1302. break;
  1303. case 4:
  1304. sample_rate = SAMPLING_RATE_32KHZ;
  1305. break;
  1306. case 5:
  1307. sample_rate = SAMPLING_RATE_44P1KHZ;
  1308. break;
  1309. case 6:
  1310. sample_rate = SAMPLING_RATE_48KHZ;
  1311. break;
  1312. case 7:
  1313. sample_rate = SAMPLING_RATE_88P2KHZ;
  1314. break;
  1315. case 8:
  1316. sample_rate = SAMPLING_RATE_96KHZ;
  1317. break;
  1318. case 9:
  1319. sample_rate = SAMPLING_RATE_176P4KHZ;
  1320. break;
  1321. case 10:
  1322. sample_rate = SAMPLING_RATE_192KHZ;
  1323. break;
  1324. case 11:
  1325. sample_rate = SAMPLING_RATE_352P8KHZ;
  1326. break;
  1327. case 12:
  1328. sample_rate = SAMPLING_RATE_384KHZ;
  1329. break;
  1330. default:
  1331. sample_rate = SAMPLING_RATE_48KHZ;
  1332. break;
  1333. }
  1334. return sample_rate;
  1335. }
  1336. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1337. struct snd_ctl_elem_value *ucontrol)
  1338. {
  1339. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1340. if (ch_num < 0)
  1341. return ch_num;
  1342. ucontrol->value.enumerated.item[0] =
  1343. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1344. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1345. cdc_dma_rx_cfg[ch_num].sample_rate);
  1346. return 0;
  1347. }
  1348. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1349. struct snd_ctl_elem_value *ucontrol)
  1350. {
  1351. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1352. if (ch_num < 0)
  1353. return ch_num;
  1354. cdc_dma_rx_cfg[ch_num].sample_rate =
  1355. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1356. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1357. __func__, ucontrol->value.enumerated.item[0],
  1358. cdc_dma_rx_cfg[ch_num].sample_rate);
  1359. return 0;
  1360. }
  1361. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1362. struct snd_ctl_elem_value *ucontrol)
  1363. {
  1364. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1365. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1366. cdc_dma_tx_cfg[ch_num].channels);
  1367. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1368. return 0;
  1369. }
  1370. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1371. struct snd_ctl_elem_value *ucontrol)
  1372. {
  1373. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1374. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1375. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1376. cdc_dma_tx_cfg[ch_num].channels);
  1377. return 1;
  1378. }
  1379. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1380. struct snd_ctl_elem_value *ucontrol)
  1381. {
  1382. int sample_rate_val;
  1383. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1384. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1385. case SAMPLING_RATE_384KHZ:
  1386. sample_rate_val = 12;
  1387. break;
  1388. case SAMPLING_RATE_352P8KHZ:
  1389. sample_rate_val = 11;
  1390. break;
  1391. case SAMPLING_RATE_192KHZ:
  1392. sample_rate_val = 10;
  1393. break;
  1394. case SAMPLING_RATE_176P4KHZ:
  1395. sample_rate_val = 9;
  1396. break;
  1397. case SAMPLING_RATE_96KHZ:
  1398. sample_rate_val = 8;
  1399. break;
  1400. case SAMPLING_RATE_88P2KHZ:
  1401. sample_rate_val = 7;
  1402. break;
  1403. case SAMPLING_RATE_48KHZ:
  1404. sample_rate_val = 6;
  1405. break;
  1406. case SAMPLING_RATE_44P1KHZ:
  1407. sample_rate_val = 5;
  1408. break;
  1409. case SAMPLING_RATE_32KHZ:
  1410. sample_rate_val = 4;
  1411. break;
  1412. case SAMPLING_RATE_22P05KHZ:
  1413. sample_rate_val = 3;
  1414. break;
  1415. case SAMPLING_RATE_16KHZ:
  1416. sample_rate_val = 2;
  1417. break;
  1418. case SAMPLING_RATE_11P025KHZ:
  1419. sample_rate_val = 1;
  1420. break;
  1421. case SAMPLING_RATE_8KHZ:
  1422. sample_rate_val = 0;
  1423. break;
  1424. default:
  1425. sample_rate_val = 6;
  1426. break;
  1427. }
  1428. ucontrol->value.integer.value[0] = sample_rate_val;
  1429. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1430. cdc_dma_tx_cfg[ch_num].sample_rate);
  1431. return 0;
  1432. }
  1433. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1434. struct snd_ctl_elem_value *ucontrol)
  1435. {
  1436. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1437. switch (ucontrol->value.integer.value[0]) {
  1438. case 12:
  1439. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1440. break;
  1441. case 11:
  1442. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1443. break;
  1444. case 10:
  1445. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1446. break;
  1447. case 9:
  1448. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1449. break;
  1450. case 8:
  1451. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1452. break;
  1453. case 7:
  1454. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1455. break;
  1456. case 6:
  1457. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1458. break;
  1459. case 5:
  1460. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1461. break;
  1462. case 4:
  1463. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1464. break;
  1465. case 3:
  1466. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1467. break;
  1468. case 2:
  1469. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1470. break;
  1471. case 1:
  1472. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1473. break;
  1474. case 0:
  1475. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1476. break;
  1477. default:
  1478. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1479. break;
  1480. }
  1481. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1482. __func__, ucontrol->value.integer.value[0],
  1483. cdc_dma_tx_cfg[ch_num].sample_rate);
  1484. return 0;
  1485. }
  1486. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1490. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1491. case SNDRV_PCM_FORMAT_S32_LE:
  1492. ucontrol->value.integer.value[0] = 3;
  1493. break;
  1494. case SNDRV_PCM_FORMAT_S24_3LE:
  1495. ucontrol->value.integer.value[0] = 2;
  1496. break;
  1497. case SNDRV_PCM_FORMAT_S24_LE:
  1498. ucontrol->value.integer.value[0] = 1;
  1499. break;
  1500. case SNDRV_PCM_FORMAT_S16_LE:
  1501. default:
  1502. ucontrol->value.integer.value[0] = 0;
  1503. break;
  1504. }
  1505. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1506. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1507. ucontrol->value.integer.value[0]);
  1508. return 0;
  1509. }
  1510. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. int rc = 0;
  1514. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1515. switch (ucontrol->value.integer.value[0]) {
  1516. case 3:
  1517. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1518. break;
  1519. case 2:
  1520. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1521. break;
  1522. case 1:
  1523. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1524. break;
  1525. case 0:
  1526. default:
  1527. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1528. break;
  1529. }
  1530. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1531. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1532. ucontrol->value.integer.value[0]);
  1533. return rc;
  1534. }
  1535. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1536. struct snd_ctl_elem_value *ucontrol)
  1537. {
  1538. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1539. usb_rx_cfg.channels);
  1540. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1541. return 0;
  1542. }
  1543. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1547. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1548. return 1;
  1549. }
  1550. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1551. struct snd_ctl_elem_value *ucontrol)
  1552. {
  1553. int sample_rate_val;
  1554. switch (usb_rx_cfg.sample_rate) {
  1555. case SAMPLING_RATE_384KHZ:
  1556. sample_rate_val = 12;
  1557. break;
  1558. case SAMPLING_RATE_352P8KHZ:
  1559. sample_rate_val = 11;
  1560. break;
  1561. case SAMPLING_RATE_192KHZ:
  1562. sample_rate_val = 10;
  1563. break;
  1564. case SAMPLING_RATE_176P4KHZ:
  1565. sample_rate_val = 9;
  1566. break;
  1567. case SAMPLING_RATE_96KHZ:
  1568. sample_rate_val = 8;
  1569. break;
  1570. case SAMPLING_RATE_88P2KHZ:
  1571. sample_rate_val = 7;
  1572. break;
  1573. case SAMPLING_RATE_48KHZ:
  1574. sample_rate_val = 6;
  1575. break;
  1576. case SAMPLING_RATE_44P1KHZ:
  1577. sample_rate_val = 5;
  1578. break;
  1579. case SAMPLING_RATE_32KHZ:
  1580. sample_rate_val = 4;
  1581. break;
  1582. case SAMPLING_RATE_22P05KHZ:
  1583. sample_rate_val = 3;
  1584. break;
  1585. case SAMPLING_RATE_16KHZ:
  1586. sample_rate_val = 2;
  1587. break;
  1588. case SAMPLING_RATE_11P025KHZ:
  1589. sample_rate_val = 1;
  1590. break;
  1591. case SAMPLING_RATE_8KHZ:
  1592. default:
  1593. sample_rate_val = 0;
  1594. break;
  1595. }
  1596. ucontrol->value.integer.value[0] = sample_rate_val;
  1597. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1598. usb_rx_cfg.sample_rate);
  1599. return 0;
  1600. }
  1601. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1602. struct snd_ctl_elem_value *ucontrol)
  1603. {
  1604. switch (ucontrol->value.integer.value[0]) {
  1605. case 12:
  1606. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1607. break;
  1608. case 11:
  1609. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1610. break;
  1611. case 10:
  1612. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1613. break;
  1614. case 9:
  1615. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1616. break;
  1617. case 8:
  1618. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1619. break;
  1620. case 7:
  1621. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1622. break;
  1623. case 6:
  1624. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1625. break;
  1626. case 5:
  1627. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1628. break;
  1629. case 4:
  1630. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1631. break;
  1632. case 3:
  1633. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1634. break;
  1635. case 2:
  1636. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1637. break;
  1638. case 1:
  1639. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1640. break;
  1641. case 0:
  1642. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1643. break;
  1644. default:
  1645. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1646. break;
  1647. }
  1648. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1649. __func__, ucontrol->value.integer.value[0],
  1650. usb_rx_cfg.sample_rate);
  1651. return 0;
  1652. }
  1653. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1654. struct snd_ctl_elem_value *ucontrol)
  1655. {
  1656. switch (usb_rx_cfg.bit_format) {
  1657. case SNDRV_PCM_FORMAT_S32_LE:
  1658. ucontrol->value.integer.value[0] = 3;
  1659. break;
  1660. case SNDRV_PCM_FORMAT_S24_3LE:
  1661. ucontrol->value.integer.value[0] = 2;
  1662. break;
  1663. case SNDRV_PCM_FORMAT_S24_LE:
  1664. ucontrol->value.integer.value[0] = 1;
  1665. break;
  1666. case SNDRV_PCM_FORMAT_S16_LE:
  1667. default:
  1668. ucontrol->value.integer.value[0] = 0;
  1669. break;
  1670. }
  1671. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1672. __func__, usb_rx_cfg.bit_format,
  1673. ucontrol->value.integer.value[0]);
  1674. return 0;
  1675. }
  1676. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1677. struct snd_ctl_elem_value *ucontrol)
  1678. {
  1679. int rc = 0;
  1680. switch (ucontrol->value.integer.value[0]) {
  1681. case 3:
  1682. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1683. break;
  1684. case 2:
  1685. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1686. break;
  1687. case 1:
  1688. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1689. break;
  1690. case 0:
  1691. default:
  1692. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1693. break;
  1694. }
  1695. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1696. __func__, usb_rx_cfg.bit_format,
  1697. ucontrol->value.integer.value[0]);
  1698. return rc;
  1699. }
  1700. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1701. struct snd_ctl_elem_value *ucontrol)
  1702. {
  1703. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1704. usb_tx_cfg.channels);
  1705. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1706. return 0;
  1707. }
  1708. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1709. struct snd_ctl_elem_value *ucontrol)
  1710. {
  1711. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1712. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1713. return 1;
  1714. }
  1715. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1716. struct snd_ctl_elem_value *ucontrol)
  1717. {
  1718. int sample_rate_val;
  1719. switch (usb_tx_cfg.sample_rate) {
  1720. case SAMPLING_RATE_384KHZ:
  1721. sample_rate_val = 12;
  1722. break;
  1723. case SAMPLING_RATE_352P8KHZ:
  1724. sample_rate_val = 11;
  1725. break;
  1726. case SAMPLING_RATE_192KHZ:
  1727. sample_rate_val = 10;
  1728. break;
  1729. case SAMPLING_RATE_176P4KHZ:
  1730. sample_rate_val = 9;
  1731. break;
  1732. case SAMPLING_RATE_96KHZ:
  1733. sample_rate_val = 8;
  1734. break;
  1735. case SAMPLING_RATE_88P2KHZ:
  1736. sample_rate_val = 7;
  1737. break;
  1738. case SAMPLING_RATE_48KHZ:
  1739. sample_rate_val = 6;
  1740. break;
  1741. case SAMPLING_RATE_44P1KHZ:
  1742. sample_rate_val = 5;
  1743. break;
  1744. case SAMPLING_RATE_32KHZ:
  1745. sample_rate_val = 4;
  1746. break;
  1747. case SAMPLING_RATE_22P05KHZ:
  1748. sample_rate_val = 3;
  1749. break;
  1750. case SAMPLING_RATE_16KHZ:
  1751. sample_rate_val = 2;
  1752. break;
  1753. case SAMPLING_RATE_11P025KHZ:
  1754. sample_rate_val = 1;
  1755. break;
  1756. case SAMPLING_RATE_8KHZ:
  1757. sample_rate_val = 0;
  1758. break;
  1759. default:
  1760. sample_rate_val = 6;
  1761. break;
  1762. }
  1763. ucontrol->value.integer.value[0] = sample_rate_val;
  1764. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1765. usb_tx_cfg.sample_rate);
  1766. return 0;
  1767. }
  1768. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1769. struct snd_ctl_elem_value *ucontrol)
  1770. {
  1771. switch (ucontrol->value.integer.value[0]) {
  1772. case 12:
  1773. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1774. break;
  1775. case 11:
  1776. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1777. break;
  1778. case 10:
  1779. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1780. break;
  1781. case 9:
  1782. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1783. break;
  1784. case 8:
  1785. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1786. break;
  1787. case 7:
  1788. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1789. break;
  1790. case 6:
  1791. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1792. break;
  1793. case 5:
  1794. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1795. break;
  1796. case 4:
  1797. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1798. break;
  1799. case 3:
  1800. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1801. break;
  1802. case 2:
  1803. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1804. break;
  1805. case 1:
  1806. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1807. break;
  1808. case 0:
  1809. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1810. break;
  1811. default:
  1812. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1813. break;
  1814. }
  1815. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1816. __func__, ucontrol->value.integer.value[0],
  1817. usb_tx_cfg.sample_rate);
  1818. return 0;
  1819. }
  1820. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1821. struct snd_ctl_elem_value *ucontrol)
  1822. {
  1823. switch (usb_tx_cfg.bit_format) {
  1824. case SNDRV_PCM_FORMAT_S32_LE:
  1825. ucontrol->value.integer.value[0] = 3;
  1826. break;
  1827. case SNDRV_PCM_FORMAT_S24_3LE:
  1828. ucontrol->value.integer.value[0] = 2;
  1829. break;
  1830. case SNDRV_PCM_FORMAT_S24_LE:
  1831. ucontrol->value.integer.value[0] = 1;
  1832. break;
  1833. case SNDRV_PCM_FORMAT_S16_LE:
  1834. default:
  1835. ucontrol->value.integer.value[0] = 0;
  1836. break;
  1837. }
  1838. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1839. __func__, usb_tx_cfg.bit_format,
  1840. ucontrol->value.integer.value[0]);
  1841. return 0;
  1842. }
  1843. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1844. struct snd_ctl_elem_value *ucontrol)
  1845. {
  1846. int rc = 0;
  1847. switch (ucontrol->value.integer.value[0]) {
  1848. case 3:
  1849. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1850. break;
  1851. case 2:
  1852. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1853. break;
  1854. case 1:
  1855. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1856. break;
  1857. case 0:
  1858. default:
  1859. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1860. break;
  1861. }
  1862. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1863. __func__, usb_tx_cfg.bit_format,
  1864. ucontrol->value.integer.value[0]);
  1865. return rc;
  1866. }
  1867. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1868. struct snd_ctl_elem_value *ucontrol)
  1869. {
  1870. pr_debug("%s: proxy_rx channels = %d\n",
  1871. __func__, proxy_rx_cfg.channels);
  1872. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1873. return 0;
  1874. }
  1875. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1876. struct snd_ctl_elem_value *ucontrol)
  1877. {
  1878. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1879. pr_debug("%s: proxy_rx channels = %d\n",
  1880. __func__, proxy_rx_cfg.channels);
  1881. return 1;
  1882. }
  1883. static int tdm_get_sample_rate(int value)
  1884. {
  1885. int sample_rate = 0;
  1886. switch (value) {
  1887. case 0:
  1888. sample_rate = SAMPLING_RATE_8KHZ;
  1889. break;
  1890. case 1:
  1891. sample_rate = SAMPLING_RATE_16KHZ;
  1892. break;
  1893. case 2:
  1894. sample_rate = SAMPLING_RATE_32KHZ;
  1895. break;
  1896. case 3:
  1897. sample_rate = SAMPLING_RATE_48KHZ;
  1898. break;
  1899. case 4:
  1900. sample_rate = SAMPLING_RATE_176P4KHZ;
  1901. break;
  1902. case 5:
  1903. sample_rate = SAMPLING_RATE_352P8KHZ;
  1904. break;
  1905. default:
  1906. sample_rate = SAMPLING_RATE_48KHZ;
  1907. break;
  1908. }
  1909. return sample_rate;
  1910. }
  1911. static int aux_pcm_get_sample_rate(int value)
  1912. {
  1913. int sample_rate;
  1914. switch (value) {
  1915. case 1:
  1916. sample_rate = SAMPLING_RATE_16KHZ;
  1917. break;
  1918. case 0:
  1919. default:
  1920. sample_rate = SAMPLING_RATE_8KHZ;
  1921. break;
  1922. }
  1923. return sample_rate;
  1924. }
  1925. static int tdm_get_sample_rate_val(int sample_rate)
  1926. {
  1927. int sample_rate_val = 0;
  1928. switch (sample_rate) {
  1929. case SAMPLING_RATE_8KHZ:
  1930. sample_rate_val = 0;
  1931. break;
  1932. case SAMPLING_RATE_16KHZ:
  1933. sample_rate_val = 1;
  1934. break;
  1935. case SAMPLING_RATE_32KHZ:
  1936. sample_rate_val = 2;
  1937. break;
  1938. case SAMPLING_RATE_48KHZ:
  1939. sample_rate_val = 3;
  1940. break;
  1941. case SAMPLING_RATE_176P4KHZ:
  1942. sample_rate_val = 4;
  1943. break;
  1944. case SAMPLING_RATE_352P8KHZ:
  1945. sample_rate_val = 5;
  1946. break;
  1947. default:
  1948. sample_rate_val = 3;
  1949. break;
  1950. }
  1951. return sample_rate_val;
  1952. }
  1953. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1954. {
  1955. int sample_rate_val;
  1956. switch (sample_rate) {
  1957. case SAMPLING_RATE_16KHZ:
  1958. sample_rate_val = 1;
  1959. break;
  1960. case SAMPLING_RATE_8KHZ:
  1961. default:
  1962. sample_rate_val = 0;
  1963. break;
  1964. }
  1965. return sample_rate_val;
  1966. }
  1967. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1968. struct tdm_port *port)
  1969. {
  1970. if (port) {
  1971. if (strnstr(kcontrol->id.name, "PRI",
  1972. sizeof(kcontrol->id.name))) {
  1973. port->mode = TDM_PRI;
  1974. } else if (strnstr(kcontrol->id.name, "SEC",
  1975. sizeof(kcontrol->id.name))) {
  1976. port->mode = TDM_SEC;
  1977. } else if (strnstr(kcontrol->id.name, "TERT",
  1978. sizeof(kcontrol->id.name))) {
  1979. port->mode = TDM_TERT;
  1980. } else if (strnstr(kcontrol->id.name, "QUAT",
  1981. sizeof(kcontrol->id.name))) {
  1982. port->mode = TDM_QUAT;
  1983. } else if (strnstr(kcontrol->id.name, "QUIN",
  1984. sizeof(kcontrol->id.name))) {
  1985. port->mode = TDM_QUIN;
  1986. } else {
  1987. pr_err("%s: unsupported mode in: %s",
  1988. __func__, kcontrol->id.name);
  1989. return -EINVAL;
  1990. }
  1991. if (strnstr(kcontrol->id.name, "RX_0",
  1992. sizeof(kcontrol->id.name)) ||
  1993. strnstr(kcontrol->id.name, "TX_0",
  1994. sizeof(kcontrol->id.name))) {
  1995. port->channel = TDM_0;
  1996. } else if (strnstr(kcontrol->id.name, "RX_1",
  1997. sizeof(kcontrol->id.name)) ||
  1998. strnstr(kcontrol->id.name, "TX_1",
  1999. sizeof(kcontrol->id.name))) {
  2000. port->channel = TDM_1;
  2001. } else if (strnstr(kcontrol->id.name, "RX_2",
  2002. sizeof(kcontrol->id.name)) ||
  2003. strnstr(kcontrol->id.name, "TX_2",
  2004. sizeof(kcontrol->id.name))) {
  2005. port->channel = TDM_2;
  2006. } else if (strnstr(kcontrol->id.name, "RX_3",
  2007. sizeof(kcontrol->id.name)) ||
  2008. strnstr(kcontrol->id.name, "TX_3",
  2009. sizeof(kcontrol->id.name))) {
  2010. port->channel = TDM_3;
  2011. } else if (strnstr(kcontrol->id.name, "RX_4",
  2012. sizeof(kcontrol->id.name)) ||
  2013. strnstr(kcontrol->id.name, "TX_4",
  2014. sizeof(kcontrol->id.name))) {
  2015. port->channel = TDM_4;
  2016. } else if (strnstr(kcontrol->id.name, "RX_5",
  2017. sizeof(kcontrol->id.name)) ||
  2018. strnstr(kcontrol->id.name, "TX_5",
  2019. sizeof(kcontrol->id.name))) {
  2020. port->channel = TDM_5;
  2021. } else if (strnstr(kcontrol->id.name, "RX_6",
  2022. sizeof(kcontrol->id.name)) ||
  2023. strnstr(kcontrol->id.name, "TX_6",
  2024. sizeof(kcontrol->id.name))) {
  2025. port->channel = TDM_6;
  2026. } else if (strnstr(kcontrol->id.name, "RX_7",
  2027. sizeof(kcontrol->id.name)) ||
  2028. strnstr(kcontrol->id.name, "TX_7",
  2029. sizeof(kcontrol->id.name))) {
  2030. port->channel = TDM_7;
  2031. } else {
  2032. pr_err("%s: unsupported channel in: %s",
  2033. __func__, kcontrol->id.name);
  2034. return -EINVAL;
  2035. }
  2036. } else
  2037. return -EINVAL;
  2038. return 0;
  2039. }
  2040. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2041. struct snd_ctl_elem_value *ucontrol)
  2042. {
  2043. struct tdm_port port;
  2044. int ret = tdm_get_port_idx(kcontrol, &port);
  2045. if (ret) {
  2046. pr_err("%s: unsupported control: %s",
  2047. __func__, kcontrol->id.name);
  2048. } else {
  2049. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2050. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  2051. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2052. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2053. ucontrol->value.enumerated.item[0]);
  2054. }
  2055. return ret;
  2056. }
  2057. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2058. struct snd_ctl_elem_value *ucontrol)
  2059. {
  2060. struct tdm_port port;
  2061. int ret = tdm_get_port_idx(kcontrol, &port);
  2062. if (ret) {
  2063. pr_err("%s: unsupported control: %s",
  2064. __func__, kcontrol->id.name);
  2065. } else {
  2066. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2067. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2068. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2069. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2070. ucontrol->value.enumerated.item[0]);
  2071. }
  2072. return ret;
  2073. }
  2074. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2075. struct snd_ctl_elem_value *ucontrol)
  2076. {
  2077. struct tdm_port port;
  2078. int ret = tdm_get_port_idx(kcontrol, &port);
  2079. if (ret) {
  2080. pr_err("%s: unsupported control: %s",
  2081. __func__, kcontrol->id.name);
  2082. } else {
  2083. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2084. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2085. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2086. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2087. ucontrol->value.enumerated.item[0]);
  2088. }
  2089. return ret;
  2090. }
  2091. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2092. struct snd_ctl_elem_value *ucontrol)
  2093. {
  2094. struct tdm_port port;
  2095. int ret = tdm_get_port_idx(kcontrol, &port);
  2096. if (ret) {
  2097. pr_err("%s: unsupported control: %s",
  2098. __func__, kcontrol->id.name);
  2099. } else {
  2100. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2101. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2102. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2103. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2104. ucontrol->value.enumerated.item[0]);
  2105. }
  2106. return ret;
  2107. }
  2108. static int tdm_get_format(int value)
  2109. {
  2110. int format = 0;
  2111. switch (value) {
  2112. case 0:
  2113. format = SNDRV_PCM_FORMAT_S16_LE;
  2114. break;
  2115. case 1:
  2116. format = SNDRV_PCM_FORMAT_S24_LE;
  2117. break;
  2118. case 2:
  2119. format = SNDRV_PCM_FORMAT_S32_LE;
  2120. break;
  2121. default:
  2122. format = SNDRV_PCM_FORMAT_S16_LE;
  2123. break;
  2124. }
  2125. return format;
  2126. }
  2127. static int tdm_get_format_val(int format)
  2128. {
  2129. int value = 0;
  2130. switch (format) {
  2131. case SNDRV_PCM_FORMAT_S16_LE:
  2132. value = 0;
  2133. break;
  2134. case SNDRV_PCM_FORMAT_S24_LE:
  2135. value = 1;
  2136. break;
  2137. case SNDRV_PCM_FORMAT_S32_LE:
  2138. value = 2;
  2139. break;
  2140. default:
  2141. value = 0;
  2142. break;
  2143. }
  2144. return value;
  2145. }
  2146. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2147. struct snd_ctl_elem_value *ucontrol)
  2148. {
  2149. struct tdm_port port;
  2150. int ret = tdm_get_port_idx(kcontrol, &port);
  2151. if (ret) {
  2152. pr_err("%s: unsupported control: %s",
  2153. __func__, kcontrol->id.name);
  2154. } else {
  2155. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2156. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2157. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2158. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2159. ucontrol->value.enumerated.item[0]);
  2160. }
  2161. return ret;
  2162. }
  2163. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2164. struct snd_ctl_elem_value *ucontrol)
  2165. {
  2166. struct tdm_port port;
  2167. int ret = tdm_get_port_idx(kcontrol, &port);
  2168. if (ret) {
  2169. pr_err("%s: unsupported control: %s",
  2170. __func__, kcontrol->id.name);
  2171. } else {
  2172. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2173. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2174. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2175. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2176. ucontrol->value.enumerated.item[0]);
  2177. }
  2178. return ret;
  2179. }
  2180. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2181. struct snd_ctl_elem_value *ucontrol)
  2182. {
  2183. struct tdm_port port;
  2184. int ret = tdm_get_port_idx(kcontrol, &port);
  2185. if (ret) {
  2186. pr_err("%s: unsupported control: %s",
  2187. __func__, kcontrol->id.name);
  2188. } else {
  2189. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2190. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2191. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2192. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2193. ucontrol->value.enumerated.item[0]);
  2194. }
  2195. return ret;
  2196. }
  2197. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2198. struct snd_ctl_elem_value *ucontrol)
  2199. {
  2200. struct tdm_port port;
  2201. int ret = tdm_get_port_idx(kcontrol, &port);
  2202. if (ret) {
  2203. pr_err("%s: unsupported control: %s",
  2204. __func__, kcontrol->id.name);
  2205. } else {
  2206. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2207. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2208. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2209. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2210. ucontrol->value.enumerated.item[0]);
  2211. }
  2212. return ret;
  2213. }
  2214. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2215. struct snd_ctl_elem_value *ucontrol)
  2216. {
  2217. struct tdm_port port;
  2218. int ret = tdm_get_port_idx(kcontrol, &port);
  2219. if (ret) {
  2220. pr_err("%s: unsupported control: %s",
  2221. __func__, kcontrol->id.name);
  2222. } else {
  2223. ucontrol->value.enumerated.item[0] =
  2224. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2225. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2226. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2227. ucontrol->value.enumerated.item[0]);
  2228. }
  2229. return ret;
  2230. }
  2231. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2232. struct snd_ctl_elem_value *ucontrol)
  2233. {
  2234. struct tdm_port port;
  2235. int ret = tdm_get_port_idx(kcontrol, &port);
  2236. if (ret) {
  2237. pr_err("%s: unsupported control: %s",
  2238. __func__, kcontrol->id.name);
  2239. } else {
  2240. tdm_rx_cfg[port.mode][port.channel].channels =
  2241. ucontrol->value.enumerated.item[0] + 1;
  2242. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2243. tdm_rx_cfg[port.mode][port.channel].channels,
  2244. ucontrol->value.enumerated.item[0] + 1);
  2245. }
  2246. return ret;
  2247. }
  2248. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2249. struct snd_ctl_elem_value *ucontrol)
  2250. {
  2251. struct tdm_port port;
  2252. int ret = tdm_get_port_idx(kcontrol, &port);
  2253. if (ret) {
  2254. pr_err("%s: unsupported control: %s",
  2255. __func__, kcontrol->id.name);
  2256. } else {
  2257. ucontrol->value.enumerated.item[0] =
  2258. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2259. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2260. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2261. ucontrol->value.enumerated.item[0]);
  2262. }
  2263. return ret;
  2264. }
  2265. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2266. struct snd_ctl_elem_value *ucontrol)
  2267. {
  2268. struct tdm_port port;
  2269. int ret = tdm_get_port_idx(kcontrol, &port);
  2270. if (ret) {
  2271. pr_err("%s: unsupported control: %s",
  2272. __func__, kcontrol->id.name);
  2273. } else {
  2274. tdm_tx_cfg[port.mode][port.channel].channels =
  2275. ucontrol->value.enumerated.item[0] + 1;
  2276. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2277. tdm_tx_cfg[port.mode][port.channel].channels,
  2278. ucontrol->value.enumerated.item[0] + 1);
  2279. }
  2280. return ret;
  2281. }
  2282. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2283. {
  2284. int idx;
  2285. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2286. sizeof("PRIM_AUX_PCM")))
  2287. idx = PRIM_AUX_PCM;
  2288. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2289. sizeof("SEC_AUX_PCM")))
  2290. idx = SEC_AUX_PCM;
  2291. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2292. sizeof("TERT_AUX_PCM")))
  2293. idx = TERT_AUX_PCM;
  2294. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2295. sizeof("QUAT_AUX_PCM")))
  2296. idx = QUAT_AUX_PCM;
  2297. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2298. sizeof("QUIN_AUX_PCM")))
  2299. idx = QUIN_AUX_PCM;
  2300. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2301. sizeof("SENN_AUX_PCM")))
  2302. idx = SEN_AUX_PCM;
  2303. else {
  2304. pr_err("%s: unsupported port: %s",
  2305. __func__, kcontrol->id.name);
  2306. idx = -EINVAL;
  2307. }
  2308. return idx;
  2309. }
  2310. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2311. struct snd_ctl_elem_value *ucontrol)
  2312. {
  2313. int idx = aux_pcm_get_port_idx(kcontrol);
  2314. if (idx < 0)
  2315. return idx;
  2316. aux_pcm_rx_cfg[idx].sample_rate =
  2317. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2318. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2319. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2320. ucontrol->value.enumerated.item[0]);
  2321. return 0;
  2322. }
  2323. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2324. struct snd_ctl_elem_value *ucontrol)
  2325. {
  2326. int idx = aux_pcm_get_port_idx(kcontrol);
  2327. if (idx < 0)
  2328. return idx;
  2329. ucontrol->value.enumerated.item[0] =
  2330. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2331. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2332. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2333. ucontrol->value.enumerated.item[0]);
  2334. return 0;
  2335. }
  2336. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2337. struct snd_ctl_elem_value *ucontrol)
  2338. {
  2339. int idx = aux_pcm_get_port_idx(kcontrol);
  2340. if (idx < 0)
  2341. return idx;
  2342. aux_pcm_tx_cfg[idx].sample_rate =
  2343. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2344. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2345. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2346. ucontrol->value.enumerated.item[0]);
  2347. return 0;
  2348. }
  2349. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2350. struct snd_ctl_elem_value *ucontrol)
  2351. {
  2352. int idx = aux_pcm_get_port_idx(kcontrol);
  2353. if (idx < 0)
  2354. return idx;
  2355. ucontrol->value.enumerated.item[0] =
  2356. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2357. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2358. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2359. ucontrol->value.enumerated.item[0]);
  2360. return 0;
  2361. }
  2362. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2363. {
  2364. int idx;
  2365. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2366. sizeof("PRIM_MI2S_RX")))
  2367. idx = PRIM_MI2S;
  2368. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2369. sizeof("SEC_MI2S_RX")))
  2370. idx = SEC_MI2S;
  2371. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2372. sizeof("TERT_MI2S_RX")))
  2373. idx = TERT_MI2S;
  2374. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2375. sizeof("QUAT_MI2S_RX")))
  2376. idx = QUAT_MI2S;
  2377. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2378. sizeof("QUIN_MI2S_RX")))
  2379. idx = QUIN_MI2S;
  2380. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2381. sizeof("SEN_MI2S_RX")))
  2382. idx = SEN_MI2S;
  2383. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2384. sizeof("PRIM_MI2S_TX")))
  2385. idx = PRIM_MI2S;
  2386. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2387. sizeof("SEC_MI2S_TX")))
  2388. idx = SEC_MI2S;
  2389. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2390. sizeof("TERT_MI2S_TX")))
  2391. idx = TERT_MI2S;
  2392. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2393. sizeof("QUAT_MI2S_TX")))
  2394. idx = QUAT_MI2S;
  2395. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2396. sizeof("QUIN_MI2S_TX")))
  2397. idx = QUIN_MI2S;
  2398. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2399. sizeof("SEN_MI2S_TX")))
  2400. idx = SEN_MI2S;
  2401. else {
  2402. pr_err("%s: unsupported channel: %s",
  2403. __func__, kcontrol->id.name);
  2404. idx = -EINVAL;
  2405. }
  2406. return idx;
  2407. }
  2408. static int mi2s_get_sample_rate_val(int sample_rate)
  2409. {
  2410. int sample_rate_val;
  2411. switch (sample_rate) {
  2412. case SAMPLING_RATE_8KHZ:
  2413. sample_rate_val = 0;
  2414. break;
  2415. case SAMPLING_RATE_11P025KHZ:
  2416. sample_rate_val = 1;
  2417. break;
  2418. case SAMPLING_RATE_16KHZ:
  2419. sample_rate_val = 2;
  2420. break;
  2421. case SAMPLING_RATE_22P05KHZ:
  2422. sample_rate_val = 3;
  2423. break;
  2424. case SAMPLING_RATE_32KHZ:
  2425. sample_rate_val = 4;
  2426. break;
  2427. case SAMPLING_RATE_44P1KHZ:
  2428. sample_rate_val = 5;
  2429. break;
  2430. case SAMPLING_RATE_48KHZ:
  2431. sample_rate_val = 6;
  2432. break;
  2433. case SAMPLING_RATE_96KHZ:
  2434. sample_rate_val = 7;
  2435. break;
  2436. case SAMPLING_RATE_192KHZ:
  2437. sample_rate_val = 8;
  2438. break;
  2439. case SAMPLING_RATE_384KHZ:
  2440. sample_rate_val = 9;
  2441. break;
  2442. default:
  2443. sample_rate_val = 6;
  2444. break;
  2445. }
  2446. return sample_rate_val;
  2447. }
  2448. static int mi2s_get_sample_rate(int value)
  2449. {
  2450. int sample_rate;
  2451. switch (value) {
  2452. case 0:
  2453. sample_rate = SAMPLING_RATE_8KHZ;
  2454. break;
  2455. case 1:
  2456. sample_rate = SAMPLING_RATE_11P025KHZ;
  2457. break;
  2458. case 2:
  2459. sample_rate = SAMPLING_RATE_16KHZ;
  2460. break;
  2461. case 3:
  2462. sample_rate = SAMPLING_RATE_22P05KHZ;
  2463. break;
  2464. case 4:
  2465. sample_rate = SAMPLING_RATE_32KHZ;
  2466. break;
  2467. case 5:
  2468. sample_rate = SAMPLING_RATE_44P1KHZ;
  2469. break;
  2470. case 6:
  2471. sample_rate = SAMPLING_RATE_48KHZ;
  2472. break;
  2473. case 7:
  2474. sample_rate = SAMPLING_RATE_96KHZ;
  2475. break;
  2476. case 8:
  2477. sample_rate = SAMPLING_RATE_192KHZ;
  2478. break;
  2479. case 9:
  2480. sample_rate = SAMPLING_RATE_384KHZ;
  2481. break;
  2482. default:
  2483. sample_rate = SAMPLING_RATE_48KHZ;
  2484. break;
  2485. }
  2486. return sample_rate;
  2487. }
  2488. static int mi2s_auxpcm_get_format(int value)
  2489. {
  2490. int format;
  2491. switch (value) {
  2492. case 0:
  2493. format = SNDRV_PCM_FORMAT_S16_LE;
  2494. break;
  2495. case 1:
  2496. format = SNDRV_PCM_FORMAT_S24_LE;
  2497. break;
  2498. case 2:
  2499. format = SNDRV_PCM_FORMAT_S24_3LE;
  2500. break;
  2501. case 3:
  2502. format = SNDRV_PCM_FORMAT_S32_LE;
  2503. break;
  2504. default:
  2505. format = SNDRV_PCM_FORMAT_S16_LE;
  2506. break;
  2507. }
  2508. return format;
  2509. }
  2510. static int mi2s_auxpcm_get_format_value(int format)
  2511. {
  2512. int value;
  2513. switch (format) {
  2514. case SNDRV_PCM_FORMAT_S16_LE:
  2515. value = 0;
  2516. break;
  2517. case SNDRV_PCM_FORMAT_S24_LE:
  2518. value = 1;
  2519. break;
  2520. case SNDRV_PCM_FORMAT_S24_3LE:
  2521. value = 2;
  2522. break;
  2523. case SNDRV_PCM_FORMAT_S32_LE:
  2524. value = 3;
  2525. break;
  2526. default:
  2527. value = 0;
  2528. break;
  2529. }
  2530. return value;
  2531. }
  2532. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2533. struct snd_ctl_elem_value *ucontrol)
  2534. {
  2535. int idx = mi2s_get_port_idx(kcontrol);
  2536. if (idx < 0)
  2537. return idx;
  2538. mi2s_rx_cfg[idx].sample_rate =
  2539. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2540. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2541. idx, mi2s_rx_cfg[idx].sample_rate,
  2542. ucontrol->value.enumerated.item[0]);
  2543. return 0;
  2544. }
  2545. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2546. struct snd_ctl_elem_value *ucontrol)
  2547. {
  2548. int idx = mi2s_get_port_idx(kcontrol);
  2549. if (idx < 0)
  2550. return idx;
  2551. ucontrol->value.enumerated.item[0] =
  2552. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2553. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2554. idx, mi2s_rx_cfg[idx].sample_rate,
  2555. ucontrol->value.enumerated.item[0]);
  2556. return 0;
  2557. }
  2558. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2559. struct snd_ctl_elem_value *ucontrol)
  2560. {
  2561. int idx = mi2s_get_port_idx(kcontrol);
  2562. if (idx < 0)
  2563. return idx;
  2564. mi2s_tx_cfg[idx].sample_rate =
  2565. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2566. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2567. idx, mi2s_tx_cfg[idx].sample_rate,
  2568. ucontrol->value.enumerated.item[0]);
  2569. return 0;
  2570. }
  2571. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2572. struct snd_ctl_elem_value *ucontrol)
  2573. {
  2574. int idx = mi2s_get_port_idx(kcontrol);
  2575. if (idx < 0)
  2576. return idx;
  2577. ucontrol->value.enumerated.item[0] =
  2578. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2579. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2580. idx, mi2s_tx_cfg[idx].sample_rate,
  2581. ucontrol->value.enumerated.item[0]);
  2582. return 0;
  2583. }
  2584. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2585. struct snd_ctl_elem_value *ucontrol)
  2586. {
  2587. int idx = mi2s_get_port_idx(kcontrol);
  2588. if (idx < 0)
  2589. return idx;
  2590. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2591. idx, mi2s_rx_cfg[idx].channels);
  2592. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2593. return 0;
  2594. }
  2595. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2596. struct snd_ctl_elem_value *ucontrol)
  2597. {
  2598. int idx = mi2s_get_port_idx(kcontrol);
  2599. if (idx < 0)
  2600. return idx;
  2601. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2602. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2603. idx, mi2s_rx_cfg[idx].channels);
  2604. return 1;
  2605. }
  2606. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2607. struct snd_ctl_elem_value *ucontrol)
  2608. {
  2609. int idx = mi2s_get_port_idx(kcontrol);
  2610. if (idx < 0)
  2611. return idx;
  2612. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2613. idx, mi2s_tx_cfg[idx].channels);
  2614. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2615. return 0;
  2616. }
  2617. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2618. struct snd_ctl_elem_value *ucontrol)
  2619. {
  2620. int idx = mi2s_get_port_idx(kcontrol);
  2621. if (idx < 0)
  2622. return idx;
  2623. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2624. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2625. idx, mi2s_tx_cfg[idx].channels);
  2626. return 1;
  2627. }
  2628. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2629. struct snd_ctl_elem_value *ucontrol)
  2630. {
  2631. int idx = mi2s_get_port_idx(kcontrol);
  2632. if (idx < 0)
  2633. return idx;
  2634. ucontrol->value.enumerated.item[0] =
  2635. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2636. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2637. idx, mi2s_rx_cfg[idx].bit_format,
  2638. ucontrol->value.enumerated.item[0]);
  2639. return 0;
  2640. }
  2641. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2642. struct snd_ctl_elem_value *ucontrol)
  2643. {
  2644. struct msm_asoc_mach_data *pdata = NULL;
  2645. struct snd_soc_component *component = NULL;
  2646. struct snd_soc_card *card = NULL;
  2647. int idx = mi2s_get_port_idx(kcontrol);
  2648. component = snd_soc_kcontrol_component(kcontrol);
  2649. card = kcontrol->private_data;
  2650. pdata = snd_soc_card_get_drvdata(card);
  2651. if (idx < 0)
  2652. return idx;
  2653. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2654. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2655. {
  2656. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2657. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2658. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2659. ucontrol->value.enumerated.item[0]);
  2660. } else {
  2661. mi2s_rx_cfg[idx].bit_format =
  2662. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2663. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2664. idx, mi2s_rx_cfg[idx].bit_format,
  2665. ucontrol->value.enumerated.item[0]);
  2666. }
  2667. return 0;
  2668. }
  2669. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2670. struct snd_ctl_elem_value *ucontrol)
  2671. {
  2672. int idx = mi2s_get_port_idx(kcontrol);
  2673. if (idx < 0)
  2674. return idx;
  2675. ucontrol->value.enumerated.item[0] =
  2676. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2677. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2678. idx, mi2s_tx_cfg[idx].bit_format,
  2679. ucontrol->value.enumerated.item[0]);
  2680. return 0;
  2681. }
  2682. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2683. struct snd_ctl_elem_value *ucontrol)
  2684. {
  2685. int idx = mi2s_get_port_idx(kcontrol);
  2686. if (idx < 0)
  2687. return idx;
  2688. mi2s_tx_cfg[idx].bit_format =
  2689. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2690. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2691. idx, mi2s_tx_cfg[idx].bit_format,
  2692. ucontrol->value.enumerated.item[0]);
  2693. return 0;
  2694. }
  2695. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2696. struct snd_ctl_elem_value *ucontrol)
  2697. {
  2698. int idx = aux_pcm_get_port_idx(kcontrol);
  2699. if (idx < 0)
  2700. return idx;
  2701. ucontrol->value.enumerated.item[0] =
  2702. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2703. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2704. idx, aux_pcm_rx_cfg[idx].bit_format,
  2705. ucontrol->value.enumerated.item[0]);
  2706. return 0;
  2707. }
  2708. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2709. struct snd_ctl_elem_value *ucontrol)
  2710. {
  2711. int idx = aux_pcm_get_port_idx(kcontrol);
  2712. if (idx < 0)
  2713. return idx;
  2714. aux_pcm_rx_cfg[idx].bit_format =
  2715. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2716. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2717. idx, aux_pcm_rx_cfg[idx].bit_format,
  2718. ucontrol->value.enumerated.item[0]);
  2719. return 0;
  2720. }
  2721. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2722. struct snd_ctl_elem_value *ucontrol)
  2723. {
  2724. int idx = aux_pcm_get_port_idx(kcontrol);
  2725. if (idx < 0)
  2726. return idx;
  2727. ucontrol->value.enumerated.item[0] =
  2728. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2729. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2730. idx, aux_pcm_tx_cfg[idx].bit_format,
  2731. ucontrol->value.enumerated.item[0]);
  2732. return 0;
  2733. }
  2734. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2735. struct snd_ctl_elem_value *ucontrol)
  2736. {
  2737. int idx = aux_pcm_get_port_idx(kcontrol);
  2738. if (idx < 0)
  2739. return idx;
  2740. aux_pcm_tx_cfg[idx].bit_format =
  2741. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2742. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2743. idx, aux_pcm_tx_cfg[idx].bit_format,
  2744. ucontrol->value.enumerated.item[0]);
  2745. return 0;
  2746. }
  2747. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2748. {
  2749. int idx;
  2750. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2751. sizeof("PRIM_SPDIF_RX")))
  2752. idx = PRIM_SPDIF_RX;
  2753. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2754. sizeof("SEC_SPDIF_RX")))
  2755. idx = SEC_SPDIF_RX;
  2756. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2757. sizeof("PRIM_SPDIF_TX")))
  2758. idx = PRIM_SPDIF_TX;
  2759. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2760. sizeof("SEC_SPDIF_TX")))
  2761. idx = SEC_SPDIF_TX;
  2762. else {
  2763. pr_err("%s: unsupported channel: %s",
  2764. __func__, kcontrol->id.name);
  2765. idx = -EINVAL;
  2766. }
  2767. return idx;
  2768. }
  2769. static int spdif_get_sample_rate_val(int sample_rate)
  2770. {
  2771. int sample_rate_val;
  2772. switch (sample_rate) {
  2773. case SAMPLING_RATE_32KHZ:
  2774. sample_rate_val = 0;
  2775. break;
  2776. case SAMPLING_RATE_44P1KHZ:
  2777. sample_rate_val = 1;
  2778. break;
  2779. case SAMPLING_RATE_48KHZ:
  2780. sample_rate_val = 2;
  2781. break;
  2782. case SAMPLING_RATE_88P2KHZ:
  2783. sample_rate_val = 3;
  2784. break;
  2785. case SAMPLING_RATE_96KHZ:
  2786. sample_rate_val = 4;
  2787. break;
  2788. case SAMPLING_RATE_176P4KHZ:
  2789. sample_rate_val = 5;
  2790. break;
  2791. case SAMPLING_RATE_192KHZ:
  2792. sample_rate_val = 6;
  2793. break;
  2794. default:
  2795. sample_rate_val = 2;
  2796. break;
  2797. }
  2798. return sample_rate_val;
  2799. }
  2800. static int spdif_get_sample_rate(int value)
  2801. {
  2802. int sample_rate;
  2803. switch (value) {
  2804. case 0:
  2805. sample_rate = SAMPLING_RATE_32KHZ;
  2806. break;
  2807. case 1:
  2808. sample_rate = SAMPLING_RATE_44P1KHZ;
  2809. break;
  2810. case 2:
  2811. sample_rate = SAMPLING_RATE_48KHZ;
  2812. break;
  2813. case 3:
  2814. sample_rate = SAMPLING_RATE_88P2KHZ;
  2815. break;
  2816. case 4:
  2817. sample_rate = SAMPLING_RATE_96KHZ;
  2818. break;
  2819. case 5:
  2820. sample_rate = SAMPLING_RATE_176P4KHZ;
  2821. break;
  2822. case 6:
  2823. sample_rate = SAMPLING_RATE_192KHZ;
  2824. break;
  2825. default:
  2826. sample_rate = SAMPLING_RATE_48KHZ;
  2827. break;
  2828. }
  2829. return sample_rate;
  2830. }
  2831. static int spdif_get_format(int value)
  2832. {
  2833. int format;
  2834. switch (value) {
  2835. case 0:
  2836. format = SNDRV_PCM_FORMAT_S16_LE;
  2837. break;
  2838. case 1:
  2839. format = SNDRV_PCM_FORMAT_S24_LE;
  2840. break;
  2841. default:
  2842. format = SNDRV_PCM_FORMAT_S16_LE;
  2843. break;
  2844. }
  2845. return format;
  2846. }
  2847. static int spdif_get_format_value(int format)
  2848. {
  2849. int value;
  2850. switch (format) {
  2851. case SNDRV_PCM_FORMAT_S16_LE:
  2852. value = 0;
  2853. break;
  2854. case SNDRV_PCM_FORMAT_S24_LE:
  2855. value = 1;
  2856. break;
  2857. default:
  2858. value = 0;
  2859. break;
  2860. }
  2861. return value;
  2862. }
  2863. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2864. struct snd_ctl_elem_value *ucontrol)
  2865. {
  2866. int idx = spdif_get_port_idx(kcontrol);
  2867. if (idx < 0)
  2868. return idx;
  2869. spdif_rx_cfg[idx].sample_rate =
  2870. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2871. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2872. idx, spdif_rx_cfg[idx].sample_rate,
  2873. ucontrol->value.enumerated.item[0]);
  2874. return 0;
  2875. }
  2876. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2877. struct snd_ctl_elem_value *ucontrol)
  2878. {
  2879. int idx = spdif_get_port_idx(kcontrol);
  2880. if (idx < 0)
  2881. return idx;
  2882. ucontrol->value.enumerated.item[0] =
  2883. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2884. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2885. idx, spdif_rx_cfg[idx].sample_rate,
  2886. ucontrol->value.enumerated.item[0]);
  2887. return 0;
  2888. }
  2889. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2890. struct snd_ctl_elem_value *ucontrol)
  2891. {
  2892. int idx = spdif_get_port_idx(kcontrol);
  2893. if (idx < 0)
  2894. return idx;
  2895. spdif_tx_cfg[idx].sample_rate =
  2896. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2897. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2898. idx, spdif_tx_cfg[idx].sample_rate,
  2899. ucontrol->value.enumerated.item[0]);
  2900. return 0;
  2901. }
  2902. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2903. struct snd_ctl_elem_value *ucontrol)
  2904. {
  2905. int idx = spdif_get_port_idx(kcontrol);
  2906. if (idx < 0)
  2907. return idx;
  2908. ucontrol->value.enumerated.item[0] =
  2909. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2910. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2911. idx, spdif_tx_cfg[idx].sample_rate,
  2912. ucontrol->value.enumerated.item[0]);
  2913. return 0;
  2914. }
  2915. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2916. struct snd_ctl_elem_value *ucontrol)
  2917. {
  2918. int idx = spdif_get_port_idx(kcontrol);
  2919. if (idx < 0)
  2920. return idx;
  2921. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2922. idx, spdif_rx_cfg[idx].channels);
  2923. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2924. return 0;
  2925. }
  2926. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2927. struct snd_ctl_elem_value *ucontrol)
  2928. {
  2929. int idx = spdif_get_port_idx(kcontrol);
  2930. if (idx < 0)
  2931. return idx;
  2932. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2933. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2934. idx, spdif_rx_cfg[idx].channels);
  2935. return 1;
  2936. }
  2937. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2938. struct snd_ctl_elem_value *ucontrol)
  2939. {
  2940. int idx = spdif_get_port_idx(kcontrol);
  2941. if (idx < 0)
  2942. return idx;
  2943. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2944. idx, spdif_tx_cfg[idx].channels);
  2945. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2946. return 0;
  2947. }
  2948. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2949. struct snd_ctl_elem_value *ucontrol)
  2950. {
  2951. int idx = spdif_get_port_idx(kcontrol);
  2952. if (idx < 0)
  2953. return idx;
  2954. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2955. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2956. idx, spdif_tx_cfg[idx].channels);
  2957. return 1;
  2958. }
  2959. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2960. struct snd_ctl_elem_value *ucontrol)
  2961. {
  2962. int idx = spdif_get_port_idx(kcontrol);
  2963. if (idx < 0)
  2964. return idx;
  2965. ucontrol->value.enumerated.item[0] =
  2966. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2967. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2968. idx, spdif_rx_cfg[idx].bit_format,
  2969. ucontrol->value.enumerated.item[0]);
  2970. return 0;
  2971. }
  2972. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2973. struct snd_ctl_elem_value *ucontrol)
  2974. {
  2975. int idx = spdif_get_port_idx(kcontrol);
  2976. if (idx < 0)
  2977. return idx;
  2978. spdif_rx_cfg[idx].bit_format =
  2979. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2980. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2981. idx, spdif_rx_cfg[idx].bit_format,
  2982. ucontrol->value.enumerated.item[0]);
  2983. return 0;
  2984. }
  2985. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2986. struct snd_ctl_elem_value *ucontrol)
  2987. {
  2988. int idx = spdif_get_port_idx(kcontrol);
  2989. if (idx < 0)
  2990. return idx;
  2991. ucontrol->value.enumerated.item[0] =
  2992. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2993. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2994. idx, spdif_tx_cfg[idx].bit_format,
  2995. ucontrol->value.enumerated.item[0]);
  2996. return 0;
  2997. }
  2998. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2999. struct snd_ctl_elem_value *ucontrol)
  3000. {
  3001. int idx = spdif_get_port_idx(kcontrol);
  3002. if (idx < 0)
  3003. return idx;
  3004. spdif_tx_cfg[idx].bit_format =
  3005. spdif_get_format(ucontrol->value.enumerated.item[0]);
  3006. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3007. idx, spdif_tx_cfg[idx].bit_format,
  3008. ucontrol->value.enumerated.item[0]);
  3009. return 0;
  3010. }
  3011. static int afe_lb_tx_ch_get(struct snd_kcontrol *kcontrol,
  3012. struct snd_ctl_elem_value *ucontrol)
  3013. {
  3014. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__,
  3015. afe_lb_tx_cfg.channels);
  3016. ucontrol->value.integer.value[0] = afe_lb_tx_cfg.channels - 1;
  3017. return 0;
  3018. }
  3019. static int afe_lb_tx_ch_put(struct snd_kcontrol *kcontrol,
  3020. struct snd_ctl_elem_value *ucontrol)
  3021. {
  3022. afe_lb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  3023. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__, afe_lb_tx_cfg.channels);
  3024. return 0;
  3025. }
  3026. static int afe_lb_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3027. struct snd_ctl_elem_value *ucontrol)
  3028. {
  3029. int sample_rate_val;
  3030. switch (afe_lb_tx_cfg.sample_rate) {
  3031. case SAMPLING_RATE_384KHZ:
  3032. sample_rate_val = 12;
  3033. break;
  3034. case SAMPLING_RATE_352P8KHZ:
  3035. sample_rate_val = 11;
  3036. break;
  3037. case SAMPLING_RATE_192KHZ:
  3038. sample_rate_val = 10;
  3039. break;
  3040. case SAMPLING_RATE_176P4KHZ:
  3041. sample_rate_val = 9;
  3042. break;
  3043. case SAMPLING_RATE_96KHZ:
  3044. sample_rate_val = 8;
  3045. break;
  3046. case SAMPLING_RATE_88P2KHZ:
  3047. sample_rate_val = 7;
  3048. break;
  3049. case SAMPLING_RATE_48KHZ:
  3050. sample_rate_val = 6;
  3051. break;
  3052. case SAMPLING_RATE_44P1KHZ:
  3053. sample_rate_val = 5;
  3054. break;
  3055. case SAMPLING_RATE_32KHZ:
  3056. sample_rate_val = 4;
  3057. break;
  3058. case SAMPLING_RATE_22P05KHZ:
  3059. sample_rate_val = 3;
  3060. break;
  3061. case SAMPLING_RATE_16KHZ:
  3062. sample_rate_val = 2;
  3063. break;
  3064. case SAMPLING_RATE_11P025KHZ:
  3065. sample_rate_val = 1;
  3066. break;
  3067. case SAMPLING_RATE_8KHZ:
  3068. sample_rate_val = 0;
  3069. break;
  3070. default:
  3071. sample_rate_val = 6;
  3072. break;
  3073. }
  3074. ucontrol->value.integer.value[0] = sample_rate_val;
  3075. pr_debug("%s: afe_lb_tx_sample_rate = %d\n", __func__,
  3076. afe_lb_tx_cfg.sample_rate);
  3077. return 0;
  3078. }
  3079. static int afe_lb_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3080. struct snd_ctl_elem_value *ucontrol)
  3081. {
  3082. switch (ucontrol->value.integer.value[0]) {
  3083. case 12:
  3084. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  3085. break;
  3086. case 11:
  3087. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  3088. break;
  3089. case 10:
  3090. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  3091. break;
  3092. case 9:
  3093. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  3094. break;
  3095. case 8:
  3096. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  3097. break;
  3098. case 7:
  3099. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  3100. break;
  3101. case 6:
  3102. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3103. break;
  3104. case 5:
  3105. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  3106. break;
  3107. case 4:
  3108. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  3109. break;
  3110. case 3:
  3111. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  3112. break;
  3113. case 2:
  3114. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  3115. break;
  3116. case 1:
  3117. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  3118. break;
  3119. case 0:
  3120. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  3121. break;
  3122. default:
  3123. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3124. break;
  3125. }
  3126. pr_debug("%s: control value = %ld, afe_lb_tx_sample_rate = %d\n",
  3127. __func__, ucontrol->value.integer.value[0],
  3128. afe_lb_tx_cfg.sample_rate);
  3129. return 0;
  3130. }
  3131. static int afe_lb_tx_format_get(struct snd_kcontrol *kcontrol,
  3132. struct snd_ctl_elem_value *ucontrol)
  3133. {
  3134. switch (afe_lb_tx_cfg.bit_format) {
  3135. case SNDRV_PCM_FORMAT_S32_LE:
  3136. ucontrol->value.integer.value[0] = 3;
  3137. break;
  3138. case SNDRV_PCM_FORMAT_S24_3LE:
  3139. ucontrol->value.integer.value[0] = 2;
  3140. break;
  3141. case SNDRV_PCM_FORMAT_S24_LE:
  3142. ucontrol->value.integer.value[0] = 1;
  3143. break;
  3144. case SNDRV_PCM_FORMAT_S16_LE:
  3145. default:
  3146. ucontrol->value.integer.value[0] = 0;
  3147. break;
  3148. }
  3149. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3150. __func__, afe_lb_tx_cfg.bit_format,
  3151. ucontrol->value.integer.value[0]);
  3152. return 0;
  3153. }
  3154. static int afe_lb_tx_format_put(struct snd_kcontrol *kcontrol,
  3155. struct snd_ctl_elem_value *ucontrol)
  3156. {
  3157. switch (ucontrol->value.integer.value[0]) {
  3158. case 3:
  3159. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  3160. break;
  3161. case 2:
  3162. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  3163. break;
  3164. case 1:
  3165. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  3166. break;
  3167. case 0:
  3168. default:
  3169. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  3170. break;
  3171. }
  3172. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3173. __func__, afe_lb_tx_cfg.bit_format,
  3174. ucontrol->value.integer.value[0]);
  3175. return 0;
  3176. }
  3177. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  3178. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  3179. slim_rx_ch_get, slim_rx_ch_put),
  3180. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  3181. slim_rx_ch_get, slim_rx_ch_put),
  3182. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  3183. slim_tx_ch_get, slim_tx_ch_put),
  3184. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  3185. slim_tx_ch_get, slim_tx_ch_put),
  3186. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  3187. slim_rx_ch_get, slim_rx_ch_put),
  3188. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  3189. slim_rx_ch_get, slim_rx_ch_put),
  3190. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  3191. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3192. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  3193. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3194. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  3195. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3196. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  3197. slim_tx_bit_format_get, slim_tx_bit_format_put),
  3198. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  3199. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3200. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  3201. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3202. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  3203. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  3204. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  3205. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3206. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  3207. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3208. };
  3209. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  3210. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3211. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3212. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3213. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3214. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3215. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3216. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3217. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3218. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3219. va_cdc_dma_tx_0_sample_rate,
  3220. cdc_dma_tx_sample_rate_get,
  3221. cdc_dma_tx_sample_rate_put),
  3222. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3223. va_cdc_dma_tx_1_sample_rate,
  3224. cdc_dma_tx_sample_rate_get,
  3225. cdc_dma_tx_sample_rate_put),
  3226. };
  3227. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3228. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3229. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3230. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3231. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3232. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3233. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3234. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3235. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3236. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3237. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3238. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3239. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3240. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3241. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3242. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3243. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3244. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3245. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3246. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3247. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3248. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3249. wsa_cdc_dma_rx_0_sample_rate,
  3250. cdc_dma_rx_sample_rate_get,
  3251. cdc_dma_rx_sample_rate_put),
  3252. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3253. wsa_cdc_dma_rx_1_sample_rate,
  3254. cdc_dma_rx_sample_rate_get,
  3255. cdc_dma_rx_sample_rate_put),
  3256. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3257. wsa_cdc_dma_tx_0_sample_rate,
  3258. cdc_dma_tx_sample_rate_get,
  3259. cdc_dma_tx_sample_rate_put),
  3260. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3261. wsa_cdc_dma_tx_1_sample_rate,
  3262. cdc_dma_tx_sample_rate_get,
  3263. cdc_dma_tx_sample_rate_put),
  3264. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3265. wsa_cdc_dma_tx_2_sample_rate,
  3266. cdc_dma_tx_sample_rate_get,
  3267. cdc_dma_tx_sample_rate_put),
  3268. };
  3269. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3270. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3271. msm_bt_sample_rate_sink_get,
  3272. msm_bt_sample_rate_sink_put),
  3273. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3274. msm_bt_sample_rate_get,
  3275. msm_bt_sample_rate_put),
  3276. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3277. msm_bt_sample_rate_get,
  3278. msm_bt_sample_rate_put),
  3279. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3280. proxy_rx_ch_get, proxy_rx_ch_put),
  3281. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3282. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3283. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3284. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3285. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3286. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3287. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3288. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3289. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3290. usb_audio_rx_sample_rate_get,
  3291. usb_audio_rx_sample_rate_put),
  3292. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3293. usb_audio_tx_sample_rate_get,
  3294. usb_audio_tx_sample_rate_put),
  3295. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3296. tdm_rx_sample_rate_get,
  3297. tdm_rx_sample_rate_put),
  3298. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3299. tdm_tx_sample_rate_get,
  3300. tdm_tx_sample_rate_put),
  3301. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3302. tdm_rx_format_get,
  3303. tdm_rx_format_put),
  3304. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3305. tdm_tx_format_get,
  3306. tdm_tx_format_put),
  3307. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3308. tdm_rx_ch_get,
  3309. tdm_rx_ch_put),
  3310. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3311. tdm_tx_ch_get,
  3312. tdm_tx_ch_put),
  3313. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3314. tdm_rx_sample_rate_get,
  3315. tdm_rx_sample_rate_put),
  3316. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3317. tdm_tx_sample_rate_get,
  3318. tdm_tx_sample_rate_put),
  3319. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3320. tdm_rx_format_get,
  3321. tdm_rx_format_put),
  3322. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3323. tdm_tx_format_get,
  3324. tdm_tx_format_put),
  3325. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3326. tdm_rx_ch_get,
  3327. tdm_rx_ch_put),
  3328. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3329. tdm_tx_ch_get,
  3330. tdm_tx_ch_put),
  3331. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3332. tdm_rx_sample_rate_get,
  3333. tdm_rx_sample_rate_put),
  3334. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3335. tdm_tx_sample_rate_get,
  3336. tdm_tx_sample_rate_put),
  3337. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3338. tdm_rx_format_get,
  3339. tdm_rx_format_put),
  3340. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3341. tdm_tx_format_get,
  3342. tdm_tx_format_put),
  3343. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3344. tdm_rx_ch_get,
  3345. tdm_rx_ch_put),
  3346. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3347. tdm_tx_ch_get,
  3348. tdm_tx_ch_put),
  3349. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3350. tdm_rx_sample_rate_get,
  3351. tdm_rx_sample_rate_put),
  3352. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3353. tdm_tx_sample_rate_get,
  3354. tdm_tx_sample_rate_put),
  3355. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3356. tdm_rx_format_get,
  3357. tdm_rx_format_put),
  3358. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3359. tdm_tx_format_get,
  3360. tdm_tx_format_put),
  3361. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3362. tdm_rx_ch_get,
  3363. tdm_rx_ch_put),
  3364. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3365. tdm_tx_ch_get,
  3366. tdm_tx_ch_put),
  3367. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3368. tdm_rx_sample_rate_get,
  3369. tdm_rx_sample_rate_put),
  3370. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3371. tdm_tx_sample_rate_get,
  3372. tdm_tx_sample_rate_put),
  3373. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3374. tdm_rx_format_get,
  3375. tdm_rx_format_put),
  3376. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3377. tdm_tx_format_get,
  3378. tdm_tx_format_put),
  3379. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3380. tdm_rx_ch_get,
  3381. tdm_rx_ch_put),
  3382. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3383. tdm_tx_ch_get,
  3384. tdm_tx_ch_put),
  3385. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3386. aux_pcm_rx_sample_rate_get,
  3387. aux_pcm_rx_sample_rate_put),
  3388. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3389. aux_pcm_rx_sample_rate_get,
  3390. aux_pcm_rx_sample_rate_put),
  3391. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3392. aux_pcm_rx_sample_rate_get,
  3393. aux_pcm_rx_sample_rate_put),
  3394. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3395. aux_pcm_rx_sample_rate_get,
  3396. aux_pcm_rx_sample_rate_put),
  3397. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3398. aux_pcm_rx_sample_rate_get,
  3399. aux_pcm_rx_sample_rate_put),
  3400. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3401. aux_pcm_tx_sample_rate_get,
  3402. aux_pcm_tx_sample_rate_put),
  3403. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3404. aux_pcm_tx_sample_rate_get,
  3405. aux_pcm_tx_sample_rate_put),
  3406. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3407. aux_pcm_tx_sample_rate_get,
  3408. aux_pcm_tx_sample_rate_put),
  3409. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3410. aux_pcm_tx_sample_rate_get,
  3411. aux_pcm_tx_sample_rate_put),
  3412. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3413. aux_pcm_tx_sample_rate_get,
  3414. aux_pcm_tx_sample_rate_put),
  3415. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3416. aux_pcm_tx_sample_rate_get,
  3417. aux_pcm_tx_sample_rate_put),
  3418. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3419. mi2s_rx_sample_rate_get,
  3420. mi2s_rx_sample_rate_put),
  3421. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3422. mi2s_rx_sample_rate_get,
  3423. mi2s_rx_sample_rate_put),
  3424. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3425. mi2s_rx_sample_rate_get,
  3426. mi2s_rx_sample_rate_put),
  3427. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3428. mi2s_rx_sample_rate_get,
  3429. mi2s_rx_sample_rate_put),
  3430. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3431. mi2s_rx_sample_rate_get,
  3432. mi2s_rx_sample_rate_put),
  3433. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3434. mi2s_rx_sample_rate_get,
  3435. mi2s_rx_sample_rate_put),
  3436. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3437. mi2s_tx_sample_rate_get,
  3438. mi2s_tx_sample_rate_put),
  3439. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3440. mi2s_tx_sample_rate_get,
  3441. mi2s_tx_sample_rate_put),
  3442. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3443. mi2s_tx_sample_rate_get,
  3444. mi2s_tx_sample_rate_put),
  3445. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3446. mi2s_tx_sample_rate_get,
  3447. mi2s_tx_sample_rate_put),
  3448. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3449. mi2s_tx_sample_rate_get,
  3450. mi2s_tx_sample_rate_put),
  3451. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3452. mi2s_tx_sample_rate_get,
  3453. mi2s_tx_sample_rate_put),
  3454. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3455. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3456. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3457. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3458. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3459. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3460. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3461. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3462. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3463. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3464. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3465. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3466. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3467. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3468. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3469. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3470. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3471. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3472. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3473. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3474. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3475. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3476. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3477. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3478. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3479. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3480. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3481. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3482. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3483. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3484. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3485. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3486. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3487. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3488. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3489. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3490. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3491. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3492. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3493. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3494. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3495. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3496. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3497. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3498. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3499. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3500. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3501. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3502. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3503. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3504. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3505. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3506. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3507. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3508. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3509. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3510. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3511. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3512. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3513. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3514. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3515. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3516. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3517. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3518. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3519. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3520. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3521. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3522. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3523. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3524. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3525. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3526. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3527. msm_snd_vad_cfg_put),
  3528. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3529. msm_spdif_rx_sample_rate_get,
  3530. msm_spdif_rx_sample_rate_put),
  3531. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3532. msm_spdif_tx_sample_rate_get,
  3533. msm_spdif_tx_sample_rate_put),
  3534. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3535. msm_spdif_rx_sample_rate_get,
  3536. msm_spdif_rx_sample_rate_put),
  3537. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3538. msm_spdif_tx_sample_rate_get,
  3539. msm_spdif_tx_sample_rate_put),
  3540. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3541. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3542. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3543. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3544. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3545. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3546. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3547. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3548. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3549. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3550. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3551. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3552. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3553. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3554. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3555. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3556. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_lb_tx_chs,
  3557. afe_lb_tx_ch_get, afe_lb_tx_ch_put),
  3558. SOC_ENUM_EXT("AFE_LOOPBACK_TX Format", afe_lb_tx_format,
  3559. afe_lb_tx_format_get, afe_lb_tx_format_put),
  3560. SOC_ENUM_EXT("AFE_LOOPBACK_TX SampleRate", afe_lb_tx_sample_rate,
  3561. afe_lb_tx_sample_rate_get,
  3562. afe_lb_tx_sample_rate_put),
  3563. };
  3564. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3565. int enable, bool dapm)
  3566. {
  3567. int ret = 0;
  3568. if (!strcmp(component.name, "tasha_codec")) {
  3569. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3570. } else {
  3571. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3572. __func__);
  3573. ret = -EINVAL;
  3574. }
  3575. return ret;
  3576. }
  3577. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  3578. int enable, bool dapm)
  3579. {
  3580. int ret = 0;
  3581. if (!strcmp(component.name, "tasha_codec")) {
  3582. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  3583. } else {
  3584. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  3585. __func__);
  3586. ret = -EINVAL;
  3587. }
  3588. return ret;
  3589. }
  3590. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3591. struct snd_kcontrol *kcontrol, int event)
  3592. {
  3593. struct snd_soc_component *component =
  3594. snd_soc_dapm_to_component(w->dapm);
  3595. pr_debug("%s: event = %d\n", __func__, event);
  3596. switch (event) {
  3597. case SND_SOC_DAPM_PRE_PMU:
  3598. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  3599. case SND_SOC_DAPM_POST_PMD:
  3600. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  3601. }
  3602. return 0;
  3603. }
  3604. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3605. struct snd_kcontrol *kcontrol, int event)
  3606. {
  3607. struct snd_soc_component *component =
  3608. snd_soc_dapm_to_component(w->dapm);
  3609. pr_debug("%s: event = %d\n", __func__, event);
  3610. switch (event) {
  3611. case SND_SOC_DAPM_PRE_PMU:
  3612. return msm_snd_enable_codec_ext_clk(component, 1, true);
  3613. case SND_SOC_DAPM_POST_PMD:
  3614. return msm_snd_enable_codec_ext_clk(component, 0, true);
  3615. }
  3616. return 0;
  3617. }
  3618. static int msm_lineout_booster_ctrl_event(struct snd_soc_dapm_widget *w,
  3619. struct snd_kcontrol *k, int event)
  3620. {
  3621. struct snd_soc_component *component =
  3622. snd_soc_dapm_to_component(w->dapm);
  3623. struct snd_soc_card *card = component->card;
  3624. struct msm_asoc_mach_data *pdata =
  3625. snd_soc_card_get_drvdata(card);
  3626. pr_debug("%s: event = %d\n", __func__, event);
  3627. switch (event) {
  3628. case SND_SOC_DAPM_POST_PMU:
  3629. msm_cdc_pinctrl_select_active_state(
  3630. pdata->lineout_booster_gpio_p);
  3631. break;
  3632. case SND_SOC_DAPM_PRE_PMD:
  3633. msm_cdc_pinctrl_select_sleep_state(
  3634. pdata->lineout_booster_gpio_p);
  3635. break;
  3636. }
  3637. return 0;
  3638. }
  3639. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3640. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3641. msm_mclk_event,
  3642. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3643. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3644. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3645. SND_SOC_DAPM_SPK("lineout booster", msm_lineout_booster_ctrl_event),
  3646. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3647. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3648. };
  3649. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3650. struct snd_kcontrol *kcontrol, int event)
  3651. {
  3652. struct msm_asoc_mach_data *pdata = NULL;
  3653. struct snd_soc_component *component =
  3654. snd_soc_dapm_to_component(w->dapm);
  3655. int ret = 0;
  3656. uint32_t dmic_idx;
  3657. int *dmic_gpio_cnt;
  3658. struct device_node *dmic_gpio;
  3659. char *wname;
  3660. wname = strpbrk(w->name, "01234567");
  3661. if (!wname) {
  3662. dev_err(component->dev, "%s: widget not found\n", __func__);
  3663. return -EINVAL;
  3664. }
  3665. ret = kstrtouint(wname, 10, &dmic_idx);
  3666. if (ret < 0) {
  3667. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3668. __func__);
  3669. return -EINVAL;
  3670. }
  3671. pdata = snd_soc_card_get_drvdata(component->card);
  3672. switch (dmic_idx) {
  3673. case 0:
  3674. case 1:
  3675. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3676. dmic_gpio = pdata->dmic_01_gpio_p;
  3677. break;
  3678. case 2:
  3679. case 3:
  3680. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3681. dmic_gpio = pdata->dmic_23_gpio_p;
  3682. break;
  3683. case 4:
  3684. case 5:
  3685. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3686. dmic_gpio = pdata->dmic_45_gpio_p;
  3687. break;
  3688. case 6:
  3689. case 7:
  3690. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3691. dmic_gpio = pdata->dmic_67_gpio_p;
  3692. break;
  3693. default:
  3694. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3695. __func__);
  3696. return -EINVAL;
  3697. }
  3698. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3699. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3700. switch (event) {
  3701. case SND_SOC_DAPM_PRE_PMU:
  3702. (*dmic_gpio_cnt)++;
  3703. if (*dmic_gpio_cnt == 1) {
  3704. ret = msm_cdc_pinctrl_select_active_state(
  3705. dmic_gpio);
  3706. if (ret < 0) {
  3707. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  3708. __func__, "dmic_gpio");
  3709. return ret;
  3710. }
  3711. }
  3712. break;
  3713. case SND_SOC_DAPM_POST_PMD:
  3714. (*dmic_gpio_cnt)--;
  3715. if (*dmic_gpio_cnt == 0) {
  3716. ret = msm_cdc_pinctrl_select_sleep_state(
  3717. dmic_gpio);
  3718. if (ret < 0) {
  3719. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  3720. __func__, "dmic_gpio");
  3721. return ret;
  3722. }
  3723. }
  3724. break;
  3725. default:
  3726. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  3727. __func__, event);
  3728. return -EINVAL;
  3729. }
  3730. return 0;
  3731. }
  3732. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3733. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3734. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3735. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3736. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3737. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3738. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3739. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3740. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3741. };
  3742. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3743. };
  3744. static inline int param_is_mask(int p)
  3745. {
  3746. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3747. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3748. }
  3749. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3750. int n)
  3751. {
  3752. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3753. }
  3754. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3755. unsigned int bit)
  3756. {
  3757. if (bit >= SNDRV_MASK_MAX)
  3758. return;
  3759. if (param_is_mask(n)) {
  3760. struct snd_mask *m = param_to_mask(p, n);
  3761. m->bits[0] = 0;
  3762. m->bits[1] = 0;
  3763. m->bits[bit >> 5] |= (1 << (bit & 31));
  3764. }
  3765. }
  3766. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3767. {
  3768. int ch_id = 0;
  3769. switch (be_id) {
  3770. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3771. ch_id = SLIM_RX_0;
  3772. break;
  3773. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3774. ch_id = SLIM_RX_1;
  3775. break;
  3776. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3777. ch_id = SLIM_RX_2;
  3778. break;
  3779. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3780. ch_id = SLIM_RX_3;
  3781. break;
  3782. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3783. ch_id = SLIM_RX_4;
  3784. break;
  3785. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3786. ch_id = SLIM_RX_6;
  3787. break;
  3788. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3789. ch_id = SLIM_TX_0;
  3790. break;
  3791. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3792. ch_id = SLIM_TX_3;
  3793. break;
  3794. default:
  3795. ch_id = SLIM_RX_0;
  3796. break;
  3797. }
  3798. return ch_id;
  3799. }
  3800. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3801. {
  3802. int idx = 0;
  3803. switch (be_id) {
  3804. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3805. idx = WSA_CDC_DMA_RX_0;
  3806. break;
  3807. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3808. idx = WSA_CDC_DMA_TX_0;
  3809. break;
  3810. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3811. idx = WSA_CDC_DMA_RX_1;
  3812. break;
  3813. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3814. idx = WSA_CDC_DMA_TX_1;
  3815. break;
  3816. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3817. idx = WSA_CDC_DMA_TX_2;
  3818. break;
  3819. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3820. idx = VA_CDC_DMA_TX_0;
  3821. break;
  3822. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3823. idx = VA_CDC_DMA_TX_1;
  3824. break;
  3825. default:
  3826. idx = VA_CDC_DMA_TX_0;
  3827. break;
  3828. }
  3829. return idx;
  3830. }
  3831. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3832. struct snd_pcm_hw_params *params)
  3833. {
  3834. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3835. struct snd_interval *rate = hw_param_interval(params,
  3836. SNDRV_PCM_HW_PARAM_RATE);
  3837. struct snd_interval *channels = hw_param_interval(params,
  3838. SNDRV_PCM_HW_PARAM_CHANNELS);
  3839. int rc = 0;
  3840. int idx;
  3841. void *config = NULL;
  3842. struct snd_soc_component *component = NULL;
  3843. pr_debug("%s: format = %d, rate = %d\n",
  3844. __func__, params_format(params), params_rate(params));
  3845. switch (dai_link->id) {
  3846. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3847. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3848. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3849. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3850. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3851. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3852. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3853. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3854. slim_rx_cfg[idx].bit_format);
  3855. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3856. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3857. break;
  3858. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3859. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3860. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3861. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3862. slim_tx_cfg[idx].bit_format);
  3863. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3864. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3865. break;
  3866. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3867. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3868. slim_tx_cfg[1].bit_format);
  3869. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3870. channels->min = channels->max = slim_tx_cfg[1].channels;
  3871. break;
  3872. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3873. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3874. SNDRV_PCM_FORMAT_S32_LE);
  3875. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3876. channels->min = channels->max = msm_vi_feed_tx_ch;
  3877. break;
  3878. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3879. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3880. slim_rx_cfg[5].bit_format);
  3881. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3882. channels->min = channels->max = slim_rx_cfg[5].channels;
  3883. break;
  3884. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3885. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  3886. if (!component) {
  3887. pr_err("%s: component is NULL\n", __func__);
  3888. return -EINVAL;
  3889. }
  3890. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3891. channels->min = channels->max = 1;
  3892. config = msm_codec_fn.get_afe_config_fn(component,
  3893. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3894. if (config) {
  3895. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3896. config, SLIMBUS_5_TX);
  3897. if (rc)
  3898. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3899. __func__, rc);
  3900. }
  3901. break;
  3902. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3903. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3904. slim_rx_cfg[SLIM_RX_7].bit_format);
  3905. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3906. channels->min = channels->max =
  3907. slim_rx_cfg[SLIM_RX_7].channels;
  3908. break;
  3909. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3910. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3911. channels->min = channels->max =
  3912. slim_tx_cfg[SLIM_TX_7].channels;
  3913. break;
  3914. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3915. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3916. channels->min = channels->max =
  3917. slim_tx_cfg[SLIM_TX_8].channels;
  3918. break;
  3919. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3920. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3921. slim_tx_cfg[SLIM_TX_9].bit_format);
  3922. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3923. channels->min = channels->max =
  3924. slim_tx_cfg[SLIM_TX_9].channels;
  3925. break;
  3926. case MSM_BACKEND_DAI_USB_RX:
  3927. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3928. usb_rx_cfg.bit_format);
  3929. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3930. channels->min = channels->max = usb_rx_cfg.channels;
  3931. break;
  3932. case MSM_BACKEND_DAI_USB_TX:
  3933. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3934. usb_tx_cfg.bit_format);
  3935. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3936. channels->min = channels->max = usb_tx_cfg.channels;
  3937. break;
  3938. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3939. channels->min = channels->max = proxy_rx_cfg.channels;
  3940. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3941. break;
  3942. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3943. channels->min = channels->max =
  3944. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3945. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3946. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3947. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3948. break;
  3949. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3950. channels->min = channels->max =
  3951. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3952. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3953. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3954. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3955. break;
  3956. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3957. channels->min = channels->max =
  3958. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3959. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3960. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3961. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3962. break;
  3963. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3964. channels->min = channels->max =
  3965. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3966. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3967. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3968. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3969. break;
  3970. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3971. channels->min = channels->max =
  3972. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3973. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3974. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3975. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3976. break;
  3977. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3978. channels->min = channels->max =
  3979. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3980. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3981. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3982. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3983. break;
  3984. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3985. channels->min = channels->max =
  3986. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3987. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3988. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3989. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3990. break;
  3991. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3992. channels->min = channels->max =
  3993. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3994. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3995. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3996. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3997. break;
  3998. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3999. channels->min = channels->max =
  4000. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4001. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4002. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4003. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4004. break;
  4005. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  4006. channels->min = channels->max =
  4007. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4008. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4009. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  4010. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4011. break;
  4012. case MSM_BACKEND_DAI_AUXPCM_RX:
  4013. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4014. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  4015. rate->min = rate->max =
  4016. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  4017. channels->min = channels->max =
  4018. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  4019. break;
  4020. case MSM_BACKEND_DAI_AUXPCM_TX:
  4021. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4022. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  4023. rate->min = rate->max =
  4024. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  4025. channels->min = channels->max =
  4026. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  4027. break;
  4028. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  4029. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4030. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  4031. rate->min = rate->max =
  4032. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  4033. channels->min = channels->max =
  4034. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  4035. break;
  4036. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  4037. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4038. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  4039. rate->min = rate->max =
  4040. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  4041. channels->min = channels->max =
  4042. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  4043. break;
  4044. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  4045. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4046. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  4047. rate->min = rate->max =
  4048. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  4049. channels->min = channels->max =
  4050. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  4051. break;
  4052. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  4053. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4054. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  4055. rate->min = rate->max =
  4056. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  4057. channels->min = channels->max =
  4058. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  4059. break;
  4060. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  4061. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4062. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  4063. rate->min = rate->max =
  4064. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  4065. channels->min = channels->max =
  4066. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  4067. break;
  4068. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  4069. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4070. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  4071. rate->min = rate->max =
  4072. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  4073. channels->min = channels->max =
  4074. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  4075. break;
  4076. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  4077. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4078. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  4079. rate->min = rate->max =
  4080. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  4081. channels->min = channels->max =
  4082. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  4083. break;
  4084. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  4085. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4086. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  4087. rate->min = rate->max =
  4088. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  4089. channels->min = channels->max =
  4090. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  4091. break;
  4092. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  4093. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4094. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  4095. rate->min = rate->max =
  4096. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  4097. channels->min = channels->max =
  4098. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  4099. break;
  4100. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  4101. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4102. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  4103. rate->min = rate->max =
  4104. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  4105. channels->min = channels->max =
  4106. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  4107. break;
  4108. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4109. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4110. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  4111. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  4112. channels->min = channels->max =
  4113. mi2s_rx_cfg[PRIM_MI2S].channels;
  4114. break;
  4115. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4116. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4117. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  4118. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  4119. channels->min = channels->max =
  4120. mi2s_tx_cfg[PRIM_MI2S].channels;
  4121. break;
  4122. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4123. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4124. mi2s_rx_cfg[SEC_MI2S].bit_format);
  4125. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  4126. channels->min = channels->max =
  4127. mi2s_rx_cfg[SEC_MI2S].channels;
  4128. break;
  4129. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4130. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4131. mi2s_tx_cfg[SEC_MI2S].bit_format);
  4132. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  4133. channels->min = channels->max =
  4134. mi2s_tx_cfg[SEC_MI2S].channels;
  4135. break;
  4136. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4137. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4138. mi2s_rx_cfg[TERT_MI2S].bit_format);
  4139. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  4140. channels->min = channels->max =
  4141. mi2s_rx_cfg[TERT_MI2S].channels;
  4142. break;
  4143. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4144. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4145. mi2s_tx_cfg[TERT_MI2S].bit_format);
  4146. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  4147. channels->min = channels->max =
  4148. mi2s_tx_cfg[TERT_MI2S].channels;
  4149. break;
  4150. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4151. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4152. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  4153. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  4154. channels->min = channels->max =
  4155. mi2s_rx_cfg[QUAT_MI2S].channels;
  4156. break;
  4157. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4158. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4159. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  4160. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  4161. channels->min = channels->max =
  4162. mi2s_tx_cfg[QUAT_MI2S].channels;
  4163. break;
  4164. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4165. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4166. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  4167. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  4168. channels->min = channels->max =
  4169. mi2s_rx_cfg[QUIN_MI2S].channels;
  4170. break;
  4171. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4172. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4173. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  4174. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  4175. channels->min = channels->max =
  4176. mi2s_tx_cfg[QUIN_MI2S].channels;
  4177. break;
  4178. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4179. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4180. mi2s_rx_cfg[SEN_MI2S].bit_format);
  4181. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  4182. channels->min = channels->max =
  4183. mi2s_rx_cfg[SEN_MI2S].channels;
  4184. break;
  4185. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4186. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4187. mi2s_tx_cfg[SEN_MI2S].bit_format);
  4188. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  4189. channels->min = channels->max =
  4190. mi2s_tx_cfg[SEN_MI2S].channels;
  4191. break;
  4192. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4193. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4194. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4195. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4196. cdc_dma_rx_cfg[idx].bit_format);
  4197. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  4198. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  4199. break;
  4200. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4201. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4202. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4203. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4204. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4205. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4206. cdc_dma_tx_cfg[idx].bit_format);
  4207. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  4208. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  4209. break;
  4210. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4211. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4212. SNDRV_PCM_FORMAT_S32_LE);
  4213. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4214. channels->min = channels->max = msm_vi_feed_tx_ch;
  4215. break;
  4216. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  4217. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4218. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  4219. rate->min = rate->max =
  4220. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  4221. channels->min = channels->max =
  4222. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  4223. break;
  4224. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  4225. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4226. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  4227. rate->min = rate->max =
  4228. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  4229. channels->min = channels->max =
  4230. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4231. break;
  4232. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4233. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4234. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4235. rate->min = rate->max =
  4236. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4237. channels->min = channels->max =
  4238. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4239. break;
  4240. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4241. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4242. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4243. rate->min = rate->max =
  4244. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4245. channels->min = channels->max =
  4246. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4247. break;
  4248. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  4249. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4250. afe_lb_tx_cfg.bit_format);
  4251. rate->min = rate->max = afe_lb_tx_cfg.sample_rate;
  4252. channels->min = channels->max = afe_lb_tx_cfg.channels;
  4253. break;
  4254. default:
  4255. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4256. break;
  4257. }
  4258. return rc;
  4259. }
  4260. static int msm_afe_set_config(struct snd_soc_component *component)
  4261. {
  4262. int ret = 0;
  4263. void *config_data = NULL;
  4264. if (!msm_codec_fn.get_afe_config_fn) {
  4265. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4266. __func__);
  4267. return -EINVAL;
  4268. }
  4269. config_data = msm_codec_fn.get_afe_config_fn(component,
  4270. AFE_CDC_REGISTERS_CONFIG);
  4271. if (config_data) {
  4272. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4273. if (ret) {
  4274. dev_err(component->dev,
  4275. "%s: Failed to set codec registers config %d\n",
  4276. __func__, ret);
  4277. return ret;
  4278. }
  4279. }
  4280. config_data = msm_codec_fn.get_afe_config_fn(component,
  4281. AFE_CDC_REGISTER_PAGE_CONFIG);
  4282. if (config_data) {
  4283. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4284. 0);
  4285. if (ret)
  4286. dev_err(component->dev,
  4287. "%s: Failed to set cdc register page config\n",
  4288. __func__);
  4289. }
  4290. config_data = msm_codec_fn.get_afe_config_fn(component,
  4291. AFE_SLIMBUS_SLAVE_CONFIG);
  4292. if (config_data) {
  4293. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4294. if (ret) {
  4295. dev_err(component->dev,
  4296. "%s: Failed to set slimbus slave config %d\n",
  4297. __func__, ret);
  4298. return ret;
  4299. }
  4300. }
  4301. return 0;
  4302. }
  4303. static void msm_afe_clear_config(void)
  4304. {
  4305. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4306. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4307. }
  4308. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4309. struct snd_card *card)
  4310. {
  4311. int ret = 0;
  4312. unsigned long timeout;
  4313. int adsp_ready = 0;
  4314. bool snd_card_online = 0;
  4315. timeout = jiffies +
  4316. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4317. do {
  4318. if (!snd_card_online) {
  4319. snd_card_online = snd_card_is_online_state(card);
  4320. pr_debug("%s: Sound card is %s\n", __func__,
  4321. snd_card_online ? "Online" : "Offline");
  4322. }
  4323. if (!adsp_ready) {
  4324. adsp_ready = q6core_is_adsp_ready();
  4325. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4326. adsp_ready ? "ready" : "not ready");
  4327. }
  4328. if (snd_card_online && adsp_ready)
  4329. break;
  4330. /*
  4331. * Sound card/ADSP will be coming up after subsystem restart and
  4332. * it might not be fully up when the control reaches
  4333. * here. So, wait for 50msec before checking ADSP state
  4334. */
  4335. msleep(50);
  4336. } while (time_after(timeout, jiffies));
  4337. if (!snd_card_online || !adsp_ready) {
  4338. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4339. __func__,
  4340. snd_card_online ? "Online" : "Offline",
  4341. adsp_ready ? "ready" : "not ready");
  4342. ret = -ETIMEDOUT;
  4343. goto err;
  4344. }
  4345. ret = msm_afe_set_config(component);
  4346. if (ret)
  4347. pr_err("%s: Failed to set AFE config. err %d\n",
  4348. __func__, ret);
  4349. return 0;
  4350. err:
  4351. return ret;
  4352. }
  4353. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4354. unsigned long opcode, void *ptr)
  4355. {
  4356. int ret;
  4357. struct snd_soc_card *card = NULL;
  4358. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4359. struct snd_soc_pcm_runtime *rtd;
  4360. struct snd_soc_dai *codec_dai;
  4361. struct snd_soc_component *component;
  4362. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4363. switch (opcode) {
  4364. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4365. /*
  4366. * Use flag to ignore initial boot notifications
  4367. * On initial boot msm_adsp_power_up_config is
  4368. * called on init. There is no need to clear
  4369. * and set the config again on initial boot.
  4370. */
  4371. if (is_initial_boot)
  4372. break;
  4373. msm_afe_clear_config();
  4374. break;
  4375. case AUDIO_NOTIFIER_SERVICE_UP:
  4376. if (is_initial_boot) {
  4377. is_initial_boot = false;
  4378. break;
  4379. }
  4380. if (!spdev)
  4381. return -EINVAL;
  4382. card = platform_get_drvdata(spdev);
  4383. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4384. if (!rtd) {
  4385. dev_err(card->dev,
  4386. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4387. __func__, be_dl_name);
  4388. ret = -EINVAL;
  4389. goto err;
  4390. }
  4391. codec_dai = rtd->codec_dai;
  4392. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4393. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4394. ret = msm_adsp_power_up_config(component, card->snd_card);
  4395. if (ret < 0) {
  4396. dev_err(card->dev,
  4397. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4398. __func__, ret);
  4399. goto err;
  4400. }
  4401. break;
  4402. default:
  4403. break;
  4404. }
  4405. err:
  4406. return NOTIFY_OK;
  4407. }
  4408. static struct notifier_block service_nb = {
  4409. .notifier_call = qcs405_notifier_service_cb,
  4410. .priority = -INT_MAX,
  4411. };
  4412. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4413. {
  4414. int ret = 0;
  4415. void *config_data;
  4416. struct snd_soc_component *component;
  4417. struct snd_soc_dapm_context *dapm;
  4418. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4419. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4420. struct snd_card *card;
  4421. struct msm_asoc_mach_data *pdata =
  4422. snd_soc_card_get_drvdata(rtd->card);
  4423. /*
  4424. * Codec SLIMBUS configuration
  4425. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4426. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4427. * TX14, TX15, TX16
  4428. */
  4429. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4430. 151, 152, 153, 154, 155, 156};
  4431. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4432. 134, 135, 136, 137, 138, 139,
  4433. 140, 141, 142, 143};
  4434. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4435. rtd->pmdown_time = 0;
  4436. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4437. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4438. dapm = snd_soc_component_get_dapm(component);
  4439. }
  4440. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4441. ARRAY_SIZE(msm_snd_sb_controls));
  4442. if (ret < 0) {
  4443. pr_err("%s: add_codec_controls failed, err %d\n",
  4444. __func__, ret);
  4445. return ret;
  4446. }
  4447. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4448. ARRAY_SIZE(msm_dapm_widgets));
  4449. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4450. ARRAY_SIZE(wcd_audio_paths));
  4451. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4452. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4453. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4454. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4455. snd_soc_dapm_sync(dapm);
  4456. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4457. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4458. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4459. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4460. if (ret) {
  4461. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4462. __func__, ret);
  4463. goto err;
  4464. }
  4465. config_data = msm_codec_fn.get_afe_config_fn(component,
  4466. AFE_AANC_VERSION);
  4467. if (config_data) {
  4468. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4469. if (ret) {
  4470. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4471. __func__, ret);
  4472. goto err;
  4473. }
  4474. }
  4475. card = rtd->card->snd_card;
  4476. if (!pdata->codec_root)
  4477. pdata->codec_root = snd_info_create_subdir(card->module,
  4478. "codecs", card->proc_root);
  4479. if (!pdata->codec_root) {
  4480. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4481. __func__);
  4482. ret = 0;
  4483. goto err;
  4484. }
  4485. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4486. codec_reg_done = true;
  4487. return 0;
  4488. err:
  4489. return ret;
  4490. }
  4491. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4492. {
  4493. int ret = 0;
  4494. struct snd_soc_component *component;
  4495. struct snd_soc_dapm_context *dapm;
  4496. struct snd_card *card;
  4497. struct msm_asoc_mach_data *pdata =
  4498. snd_soc_card_get_drvdata(rtd->card);
  4499. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4500. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4501. if (!component) {
  4502. pr_err("%s: component is NULL\n", __func__);
  4503. return -EINVAL;
  4504. }
  4505. dapm = snd_soc_component_get_dapm(component);
  4506. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4507. ARRAY_SIZE(msm_snd_va_controls));
  4508. if (ret < 0) {
  4509. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4510. __func__, ret);
  4511. return ret;
  4512. }
  4513. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4514. ARRAY_SIZE(msm_va_dapm_widgets));
  4515. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4516. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4517. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4518. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4519. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4520. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4521. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4522. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4523. snd_soc_dapm_sync(dapm);
  4524. card = rtd->card->snd_card;
  4525. if (!pdata->codec_root)
  4526. pdata->codec_root = snd_info_create_subdir(card->module,
  4527. "codecs", card->proc_root);
  4528. if (!pdata->codec_root) {
  4529. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4530. __func__);
  4531. ret = 0;
  4532. goto done;
  4533. }
  4534. bolero_info_create_codec_entry(pdata->codec_root, component);
  4535. done:
  4536. return ret;
  4537. }
  4538. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4539. {
  4540. int ret = 0;
  4541. struct snd_soc_component *component = NULL;
  4542. struct snd_soc_dapm_context *dapm = NULL;
  4543. struct snd_soc_component *aux_comp = NULL;
  4544. struct snd_card *card = NULL;
  4545. struct msm_asoc_mach_data *pdata =
  4546. snd_soc_card_get_drvdata(rtd->card);
  4547. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4548. if (!component) {
  4549. pr_err("%s: component is NULL\n", __func__);
  4550. return -EINVAL;
  4551. }
  4552. dapm = snd_soc_component_get_dapm(component);
  4553. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  4554. ARRAY_SIZE(msm_snd_wsa_controls));
  4555. if (ret < 0) {
  4556. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4557. __func__, ret);
  4558. return ret;
  4559. }
  4560. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4561. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4562. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4563. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4564. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4565. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4566. snd_soc_dapm_sync(dapm);
  4567. /*
  4568. * Send speaker configuration only for WSA8810.
  4569. * Default configuration is for WSA8815.
  4570. */
  4571. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4572. __func__, rtd->card->num_aux_devs);
  4573. if (rtd->card->num_aux_devs &&
  4574. !list_empty(&rtd->card->component_dev_list)) {
  4575. aux_comp = list_first_entry(
  4576. &rtd->card->component_dev_list,
  4577. struct snd_soc_component,
  4578. card_aux_list);
  4579. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4580. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4581. wsa_macro_set_spkr_mode(component,
  4582. WSA_MACRO_SPKR_MODE_1);
  4583. wsa_macro_set_spkr_gain_offset(component,
  4584. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4585. }
  4586. }
  4587. card = rtd->card->snd_card;
  4588. if (!pdata->codec_root)
  4589. pdata->codec_root = snd_info_create_subdir(card->module,
  4590. "codecs", card->proc_root);
  4591. if (!pdata->codec_root) {
  4592. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  4593. __func__);
  4594. ret = 0;
  4595. goto done;
  4596. }
  4597. bolero_info_create_codec_entry(pdata->codec_root, component);
  4598. done:
  4599. return ret;
  4600. }
  4601. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4602. {
  4603. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4604. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4605. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4606. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4607. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4608. }
  4609. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4610. struct snd_pcm_hw_params *params)
  4611. {
  4612. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4613. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4614. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4615. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4616. int ret = 0;
  4617. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4618. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4619. u32 user_set_tx_ch = 0;
  4620. u32 rx_ch_count;
  4621. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4622. ret = snd_soc_dai_get_channel_map(codec_dai,
  4623. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4624. if (ret < 0) {
  4625. pr_err("%s: failed to get codec chan map, err:%d\n",
  4626. __func__, ret);
  4627. goto err;
  4628. }
  4629. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4630. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4631. slim_rx_cfg[5].channels);
  4632. rx_ch_count = slim_rx_cfg[5].channels;
  4633. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4634. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4635. slim_rx_cfg[2].channels);
  4636. rx_ch_count = slim_rx_cfg[2].channels;
  4637. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4638. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4639. slim_rx_cfg[6].channels);
  4640. rx_ch_count = slim_rx_cfg[6].channels;
  4641. } else {
  4642. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4643. slim_rx_cfg[0].channels);
  4644. rx_ch_count = slim_rx_cfg[0].channels;
  4645. }
  4646. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4647. rx_ch_count, rx_ch);
  4648. if (ret < 0) {
  4649. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4650. __func__, ret);
  4651. goto err;
  4652. }
  4653. } else {
  4654. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4655. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4656. ret = snd_soc_dai_get_channel_map(codec_dai,
  4657. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4658. if (ret < 0) {
  4659. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4660. __func__, ret);
  4661. goto err;
  4662. }
  4663. /* For <codec>_tx1 case */
  4664. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4665. user_set_tx_ch = slim_tx_cfg[0].channels;
  4666. /* For <codec>_tx3 case */
  4667. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4668. user_set_tx_ch = slim_tx_cfg[1].channels;
  4669. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4670. user_set_tx_ch = msm_vi_feed_tx_ch;
  4671. else
  4672. user_set_tx_ch = tx_ch_cnt;
  4673. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4674. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4675. tx_ch_cnt, dai_link->id);
  4676. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4677. user_set_tx_ch, tx_ch, 0, 0);
  4678. if (ret < 0)
  4679. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4680. __func__, ret);
  4681. }
  4682. err:
  4683. return ret;
  4684. }
  4685. static int msm_snd_auxpcm_startup(struct snd_pcm_substream *substream)
  4686. {
  4687. int ret = 0;
  4688. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4689. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4690. ret = qcs405_send_island_vad_config(dai_link->id);
  4691. if (ret) {
  4692. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4693. __func__, ret);
  4694. }
  4695. return ret;
  4696. }
  4697. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4698. {
  4699. int ret = 0;
  4700. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4701. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4702. ret = qcs405_send_island_vad_config(dai_link->id);
  4703. if (ret) {
  4704. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4705. __func__, ret);
  4706. }
  4707. return ret;
  4708. }
  4709. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4710. struct snd_pcm_hw_params *params)
  4711. {
  4712. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4713. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4714. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4715. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4716. int ret = 0;
  4717. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4718. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4719. u32 user_set_tx_ch = 0;
  4720. u32 user_set_rx_ch = 0;
  4721. u32 ch_id;
  4722. ret = snd_soc_dai_get_channel_map(codec_dai,
  4723. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4724. &rx_ch_cdc_dma);
  4725. if (ret < 0) {
  4726. pr_err("%s: failed to get codec chan map, err:%d\n",
  4727. __func__, ret);
  4728. goto err;
  4729. }
  4730. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4731. switch (dai_link->id) {
  4732. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4733. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4734. {
  4735. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4736. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4737. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4738. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4739. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4740. user_set_rx_ch, &rx_ch_cdc_dma);
  4741. if (ret < 0) {
  4742. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4743. __func__, ret);
  4744. goto err;
  4745. }
  4746. }
  4747. break;
  4748. }
  4749. } else {
  4750. switch (dai_link->id) {
  4751. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4752. {
  4753. user_set_tx_ch = msm_vi_feed_tx_ch;
  4754. }
  4755. break;
  4756. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4757. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4758. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4759. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4760. {
  4761. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4762. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4763. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4764. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4765. }
  4766. break;
  4767. }
  4768. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4769. &tx_ch_cdc_dma, 0, 0);
  4770. if (ret < 0) {
  4771. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4772. __func__, ret);
  4773. goto err;
  4774. }
  4775. }
  4776. err:
  4777. return ret;
  4778. }
  4779. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4780. struct snd_pcm_hw_params *params)
  4781. {
  4782. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4783. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4784. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4785. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4786. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4787. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4788. int ret;
  4789. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4790. codec_dai->name, codec_dai->id);
  4791. ret = snd_soc_dai_get_channel_map(codec_dai,
  4792. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4793. if (ret) {
  4794. dev_err(rtd->dev,
  4795. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4796. __func__, ret);
  4797. goto err;
  4798. }
  4799. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4800. __func__, tx_ch_cnt, dai_link->id);
  4801. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4802. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4803. if (ret)
  4804. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4805. __func__, ret);
  4806. err:
  4807. return ret;
  4808. }
  4809. static int msm_get_port_id(int be_id)
  4810. {
  4811. int afe_port_id;
  4812. switch (be_id) {
  4813. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4814. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4815. break;
  4816. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4817. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4818. break;
  4819. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4820. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4821. break;
  4822. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4823. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4824. break;
  4825. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4826. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4827. break;
  4828. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4829. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4830. break;
  4831. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4832. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4833. break;
  4834. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4835. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4836. break;
  4837. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4838. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4839. break;
  4840. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4841. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4842. break;
  4843. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4844. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4845. break;
  4846. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4847. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4848. break;
  4849. default:
  4850. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4851. afe_port_id = -EINVAL;
  4852. }
  4853. return afe_port_id;
  4854. }
  4855. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4856. {
  4857. u32 bit_per_sample;
  4858. switch (bit_format) {
  4859. case SNDRV_PCM_FORMAT_S32_LE:
  4860. case SNDRV_PCM_FORMAT_S24_3LE:
  4861. case SNDRV_PCM_FORMAT_S24_LE:
  4862. bit_per_sample = 32;
  4863. break;
  4864. case SNDRV_PCM_FORMAT_S16_LE:
  4865. default:
  4866. bit_per_sample = 16;
  4867. break;
  4868. }
  4869. return bit_per_sample;
  4870. }
  4871. static void update_mi2s_clk_val(int dai_id, int stream)
  4872. {
  4873. u32 bit_per_sample;
  4874. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4875. bit_per_sample =
  4876. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4877. mi2s_clk[dai_id].clk_freq_in_hz =
  4878. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4879. } else {
  4880. bit_per_sample =
  4881. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4882. mi2s_clk[dai_id].clk_freq_in_hz =
  4883. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4884. }
  4885. }
  4886. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4887. {
  4888. int ret = 0;
  4889. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4890. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4891. int port_id = 0;
  4892. int index = cpu_dai->id;
  4893. port_id = msm_get_port_id(rtd->dai_link->id);
  4894. if (port_id < 0) {
  4895. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4896. ret = port_id;
  4897. goto err;
  4898. }
  4899. if (enable) {
  4900. update_mi2s_clk_val(index, substream->stream);
  4901. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4902. mi2s_clk[index].clk_freq_in_hz);
  4903. }
  4904. mi2s_clk[index].enable = enable;
  4905. ret = afe_set_lpass_clock_v2(port_id,
  4906. &mi2s_clk[index]);
  4907. if (ret < 0) {
  4908. dev_err(rtd->card->dev,
  4909. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4910. __func__, port_id, ret);
  4911. goto err;
  4912. }
  4913. err:
  4914. return ret;
  4915. }
  4916. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4917. struct snd_pcm_hw_params *params)
  4918. {
  4919. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4920. struct snd_interval *rate = hw_param_interval(params,
  4921. SNDRV_PCM_HW_PARAM_RATE);
  4922. struct snd_interval *channels = hw_param_interval(params,
  4923. SNDRV_PCM_HW_PARAM_CHANNELS);
  4924. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4925. channels->min = channels->max =
  4926. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4927. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4928. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4929. rate->min = rate->max =
  4930. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4931. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4932. channels->min = channels->max =
  4933. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4934. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4935. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4936. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4937. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4938. channels->min = channels->max =
  4939. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4940. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4941. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4942. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4943. } else {
  4944. pr_err("%s: dai id 0x%x not supported\n",
  4945. __func__, cpu_dai->id);
  4946. return -EINVAL;
  4947. }
  4948. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4949. __func__, cpu_dai->id, channels->max, rate->max,
  4950. params_format(params));
  4951. return 0;
  4952. }
  4953. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4954. struct snd_pcm_hw_params *params)
  4955. {
  4956. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4957. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4958. int ret = 0;
  4959. int slot_width = 32;
  4960. int channels, slots = 8;
  4961. unsigned int slot_mask, rate, clk_freq;
  4962. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4963. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4964. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4965. switch (cpu_dai->id) {
  4966. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4967. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4968. break;
  4969. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4970. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4971. break;
  4972. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4973. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4974. break;
  4975. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4976. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4977. break;
  4978. case AFE_PORT_ID_QUINARY_TDM_RX:
  4979. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4980. break;
  4981. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4982. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4983. break;
  4984. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4985. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4986. break;
  4987. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4988. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4989. break;
  4990. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4991. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4992. break;
  4993. case AFE_PORT_ID_QUINARY_TDM_TX:
  4994. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4995. break;
  4996. default:
  4997. pr_err("%s: dai id 0x%x not supported\n",
  4998. __func__, cpu_dai->id);
  4999. return -EINVAL;
  5000. }
  5001. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5002. /*2 slot config - bits 0 and 1 set for the first two slots */
  5003. slot_mask = 0x0000FFFF >> (16-channels);
  5004. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  5005. __func__, slot_width, slots);
  5006. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  5007. slots, slot_width);
  5008. if (ret < 0) {
  5009. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  5010. __func__, ret);
  5011. goto end;
  5012. }
  5013. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5014. 0, NULL, channels, slot_offset);
  5015. if (ret < 0) {
  5016. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  5017. __func__, ret);
  5018. goto end;
  5019. }
  5020. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  5021. /*2 slot config - bits 0 and 1 set for the first two slots */
  5022. slot_mask = 0x0000FFFF >> (16-channels);
  5023. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  5024. __func__, slot_width, slots);
  5025. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  5026. slots, slot_width);
  5027. if (ret < 0) {
  5028. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  5029. __func__, ret);
  5030. goto end;
  5031. }
  5032. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5033. channels, slot_offset, 0, NULL);
  5034. if (ret < 0) {
  5035. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  5036. __func__, ret);
  5037. goto end;
  5038. }
  5039. } else {
  5040. ret = -EINVAL;
  5041. pr_err("%s: invalid use case, err:%d\n",
  5042. __func__, ret);
  5043. goto end;
  5044. }
  5045. rate = params_rate(params);
  5046. clk_freq = rate * slot_width * slots;
  5047. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  5048. if (ret < 0)
  5049. pr_err("%s: failed to set tdm clk, err:%d\n",
  5050. __func__, ret);
  5051. end:
  5052. return ret;
  5053. }
  5054. static int msm_get_tdm_mode(u32 port_id)
  5055. {
  5056. u32 tdm_mode;
  5057. switch (port_id) {
  5058. case AFE_PORT_ID_PRIMARY_TDM_RX:
  5059. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5060. tdm_mode = TDM_PRI;
  5061. break;
  5062. case AFE_PORT_ID_SECONDARY_TDM_RX:
  5063. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5064. tdm_mode = TDM_SEC;
  5065. break;
  5066. case AFE_PORT_ID_TERTIARY_TDM_RX:
  5067. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5068. tdm_mode = TDM_TERT;
  5069. break;
  5070. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  5071. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5072. tdm_mode = TDM_QUAT;
  5073. break;
  5074. case AFE_PORT_ID_QUINARY_TDM_RX:
  5075. case AFE_PORT_ID_QUINARY_TDM_TX:
  5076. tdm_mode = TDM_QUIN;
  5077. break;
  5078. default:
  5079. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  5080. tdm_mode = -EINVAL;
  5081. }
  5082. return tdm_mode;
  5083. }
  5084. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  5085. {
  5086. int ret = 0;
  5087. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5088. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5089. struct snd_soc_card *card = rtd->card;
  5090. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5091. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5092. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5093. if (tdm_mode >= TDM_INTERFACE_MAX) {
  5094. ret = -EINVAL;
  5095. pr_err("%s: Invalid TDM interface %d\n",
  5096. __func__, ret);
  5097. return ret;
  5098. }
  5099. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5100. ret = msm_cdc_pinctrl_select_active_state(
  5101. pdata->mi2s_gpio_p[tdm_mode]);
  5102. if (ret)
  5103. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  5104. __func__, ret);
  5105. }
  5106. /* Enable Mic bias for TDM Mics */
  5107. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5108. if (pdata->tdm_micb_supply) {
  5109. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  5110. pdata->tdm_micb_voltage,
  5111. pdata->tdm_micb_voltage);
  5112. if (ret) {
  5113. pr_err("%s: Setting voltage failed, err = %d\n",
  5114. __func__, ret);
  5115. return ret;
  5116. }
  5117. ret = regulator_set_load(pdata->tdm_micb_supply,
  5118. pdata->tdm_micb_current);
  5119. if (ret) {
  5120. pr_err("%s: Setting current failed, err = %d\n",
  5121. __func__, ret);
  5122. return ret;
  5123. }
  5124. ret = regulator_enable(pdata->tdm_micb_supply);
  5125. if (ret) {
  5126. pr_err("%s: regulator enable failed, err = %d\n",
  5127. __func__, ret);
  5128. return ret;
  5129. }
  5130. }
  5131. }
  5132. ret = qcs405_send_island_vad_config(dai_link->id);
  5133. if (ret) {
  5134. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5135. __func__, ret);
  5136. return ret;
  5137. }
  5138. return ret;
  5139. }
  5140. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  5141. {
  5142. int ret = 0;
  5143. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5144. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5145. struct snd_soc_card *card = rtd->card;
  5146. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5147. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5148. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5149. if (pdata->tdm_micb_supply) {
  5150. ret = regulator_disable(pdata->tdm_micb_supply);
  5151. if (ret)
  5152. pr_err("%s: regulator disable failed, err = %d\n",
  5153. __func__, ret);
  5154. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  5155. pdata->tdm_micb_voltage);
  5156. regulator_set_load(pdata->tdm_micb_supply, 0);
  5157. }
  5158. }
  5159. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5160. ret = msm_cdc_pinctrl_select_sleep_state(
  5161. pdata->mi2s_gpio_p[tdm_mode]);
  5162. if (ret)
  5163. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  5164. __func__, ret);
  5165. }
  5166. }
  5167. static struct snd_soc_ops qcs405_tdm_be_ops = {
  5168. .hw_params = qcs405_tdm_snd_hw_params,
  5169. .startup = qcs405_tdm_snd_startup,
  5170. .shutdown = qcs405_tdm_snd_shutdown
  5171. };
  5172. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  5173. {
  5174. cpumask_t mask;
  5175. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  5176. pm_qos_remove_request(&substream->latency_pm_qos_req);
  5177. cpumask_clear(&mask);
  5178. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  5179. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  5180. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  5181. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  5182. pm_qos_add_request(&substream->latency_pm_qos_req,
  5183. PM_QOS_CPU_DMA_LATENCY,
  5184. MSM_LL_QOS_VALUE);
  5185. return 0;
  5186. }
  5187. static struct snd_soc_ops msm_fe_qos_ops = {
  5188. .prepare = msm_fe_qos_prepare,
  5189. };
  5190. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5191. {
  5192. int ret = 0;
  5193. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5194. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5195. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5196. int index = cpu_dai->id;
  5197. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5198. struct snd_soc_card *card = rtd->card;
  5199. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5200. dev_dbg(rtd->card->dev,
  5201. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5202. __func__, substream->name, substream->stream,
  5203. cpu_dai->name, cpu_dai->id);
  5204. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5205. ret = -EINVAL;
  5206. dev_err(rtd->card->dev,
  5207. "%s: CPU DAI id (%d) out of range\n",
  5208. __func__, cpu_dai->id);
  5209. goto err;
  5210. }
  5211. /*
  5212. * Mutex protection in case the same MI2S
  5213. * interface using for both TX and RX so
  5214. * that the same clock won't be enable twice.
  5215. */
  5216. mutex_lock(&mi2s_intf_conf[index].lock);
  5217. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  5218. /* Check if msm needs to provide the clock to the interface */
  5219. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  5220. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  5221. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5222. }
  5223. ret = msm_mi2s_set_sclk(substream, true);
  5224. if (ret < 0) {
  5225. dev_err(rtd->card->dev,
  5226. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5227. __func__, ret);
  5228. goto clean_up;
  5229. }
  5230. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5231. if (ret < 0) {
  5232. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  5233. __func__, index, ret);
  5234. goto clk_off;
  5235. }
  5236. if (pdata->mi2s_gpio_p[index])
  5237. msm_cdc_pinctrl_select_active_state(
  5238. pdata->mi2s_gpio_p[index]);
  5239. }
  5240. ret = qcs405_send_island_vad_config(dai_link->id);
  5241. if (ret) {
  5242. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5243. __func__, ret);
  5244. return ret;
  5245. }
  5246. clk_off:
  5247. if (ret < 0)
  5248. msm_mi2s_set_sclk(substream, false);
  5249. clean_up:
  5250. if (ret < 0)
  5251. mi2s_intf_conf[index].ref_cnt--;
  5252. mutex_unlock(&mi2s_intf_conf[index].lock);
  5253. err:
  5254. return ret;
  5255. }
  5256. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5257. {
  5258. int ret;
  5259. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5260. int index = rtd->cpu_dai->id;
  5261. struct snd_soc_card *card = rtd->card;
  5262. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5263. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5264. substream->name, substream->stream);
  5265. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5266. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5267. return;
  5268. }
  5269. mutex_lock(&mi2s_intf_conf[index].lock);
  5270. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  5271. if (pdata->mi2s_gpio_p[index])
  5272. msm_cdc_pinctrl_select_sleep_state(
  5273. pdata->mi2s_gpio_p[index]);
  5274. ret = msm_mi2s_set_sclk(substream, false);
  5275. if (ret < 0)
  5276. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5277. __func__, index, ret);
  5278. }
  5279. mutex_unlock(&mi2s_intf_conf[index].lock);
  5280. }
  5281. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5282. {
  5283. int ret = 0;
  5284. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5285. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5286. int port_id = cpu_dai->id;
  5287. struct afe_clk_set clk_cfg;
  5288. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5289. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5290. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5291. clk_cfg.enable = enable;
  5292. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5293. switch (port_id) {
  5294. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5295. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5296. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5297. clk_cfg.clk_freq_in_hz =
  5298. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5299. break;
  5300. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5301. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5302. clk_cfg.clk_freq_in_hz =
  5303. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5304. break;
  5305. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5306. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5307. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5308. break;
  5309. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5310. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5311. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5312. break;
  5313. }
  5314. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5315. if (ret < 0) {
  5316. dev_err(rtd->card->dev,
  5317. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5318. __func__, port_id, ret);
  5319. goto err;
  5320. }
  5321. /* Set NPL clock for RX in addition */
  5322. switch (port_id) {
  5323. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5324. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5325. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5326. if (ret < 0) {
  5327. dev_err(rtd->card->dev,
  5328. "%s: afe NPL failed port 0x%x, err:%d\n",
  5329. __func__, port_id, ret);
  5330. goto err;
  5331. }
  5332. break;
  5333. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5334. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5335. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5336. if (ret < 0) {
  5337. dev_err(rtd->card->dev,
  5338. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5339. __func__, port_id, ret);
  5340. goto err;
  5341. }
  5342. break;
  5343. }
  5344. if (enable) {
  5345. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5346. clk_cfg.clk_freq_in_hz);
  5347. }
  5348. err:
  5349. return ret;
  5350. }
  5351. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5352. {
  5353. int ret = 0;
  5354. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5355. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5356. int port_id = cpu_dai->id;
  5357. dev_dbg(rtd->card->dev,
  5358. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5359. __func__, substream->name, substream->stream,
  5360. cpu_dai->name, cpu_dai->id);
  5361. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5362. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5363. ret = -EINVAL;
  5364. dev_err(rtd->card->dev,
  5365. "%s: CPU DAI id (%d) out of range\n",
  5366. __func__, cpu_dai->id);
  5367. goto err;
  5368. }
  5369. ret = msm_spdif_set_clk(substream, true);
  5370. if (ret < 0) {
  5371. dev_err(rtd->card->dev,
  5372. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5373. __func__, port_id, ret);
  5374. }
  5375. err:
  5376. return ret;
  5377. }
  5378. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5379. {
  5380. int ret;
  5381. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5382. int port_id = rtd->cpu_dai->id;
  5383. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5384. substream->name, substream->stream);
  5385. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5386. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5387. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5388. return;
  5389. }
  5390. ret = msm_spdif_set_clk(substream, false);
  5391. if (ret < 0)
  5392. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5393. __func__, port_id, ret);
  5394. }
  5395. static struct snd_soc_ops msm_mi2s_be_ops = {
  5396. .startup = msm_mi2s_snd_startup,
  5397. .shutdown = msm_mi2s_snd_shutdown,
  5398. };
  5399. static struct snd_soc_ops msm_auxpcm_be_ops = {
  5400. .startup = msm_snd_auxpcm_startup,
  5401. };
  5402. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5403. .startup = msm_snd_cdc_dma_startup,
  5404. .hw_params = msm_snd_cdc_dma_hw_params,
  5405. };
  5406. static struct snd_soc_ops msm_be_ops = {
  5407. .hw_params = msm_snd_hw_params,
  5408. };
  5409. static struct snd_soc_ops msm_wcn_ops = {
  5410. .hw_params = msm_wcn_hw_params,
  5411. };
  5412. static struct snd_soc_ops msm_spdif_be_ops = {
  5413. .startup = msm_spdif_snd_startup,
  5414. .shutdown = msm_spdif_snd_shutdown,
  5415. };
  5416. /* Digital audio interface glue - connects codec <---> CPU */
  5417. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5418. /* FrontEnd DAI Links */
  5419. {
  5420. .name = MSM_DAILINK_NAME(Media1),
  5421. .stream_name = "MultiMedia1",
  5422. .cpu_dai_name = "MultiMedia1",
  5423. .platform_name = "msm-pcm-dsp.0",
  5424. .dynamic = 1,
  5425. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5426. .dpcm_playback = 1,
  5427. .dpcm_capture = 1,
  5428. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5429. SND_SOC_DPCM_TRIGGER_POST},
  5430. .codec_dai_name = "snd-soc-dummy-dai",
  5431. .codec_name = "snd-soc-dummy",
  5432. .ignore_suspend = 1,
  5433. /* this dainlink has playback support */
  5434. .ignore_pmdown_time = 1,
  5435. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5436. },
  5437. {
  5438. .name = MSM_DAILINK_NAME(Media2),
  5439. .stream_name = "MultiMedia2",
  5440. .cpu_dai_name = "MultiMedia2",
  5441. .platform_name = "msm-pcm-dsp.0",
  5442. .dynamic = 1,
  5443. .dpcm_playback = 1,
  5444. .dpcm_capture = 1,
  5445. .codec_dai_name = "snd-soc-dummy-dai",
  5446. .codec_name = "snd-soc-dummy",
  5447. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5448. SND_SOC_DPCM_TRIGGER_POST},
  5449. .ignore_suspend = 1,
  5450. /* this dainlink has playback support */
  5451. .ignore_pmdown_time = 1,
  5452. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5453. },
  5454. {
  5455. .name = "VoiceMMode1",
  5456. .stream_name = "VoiceMMode1",
  5457. .cpu_dai_name = "VoiceMMode1",
  5458. .platform_name = "msm-pcm-voice",
  5459. .dynamic = 1,
  5460. .dpcm_playback = 1,
  5461. .dpcm_capture = 1,
  5462. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5463. SND_SOC_DPCM_TRIGGER_POST},
  5464. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5465. .ignore_suspend = 1,
  5466. .ignore_pmdown_time = 1,
  5467. .codec_dai_name = "snd-soc-dummy-dai",
  5468. .codec_name = "snd-soc-dummy",
  5469. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5470. },
  5471. {
  5472. .name = "MSM VoIP",
  5473. .stream_name = "VoIP",
  5474. .cpu_dai_name = "VoIP",
  5475. .platform_name = "msm-voip-dsp",
  5476. .dynamic = 1,
  5477. .dpcm_playback = 1,
  5478. .dpcm_capture = 1,
  5479. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5480. SND_SOC_DPCM_TRIGGER_POST},
  5481. .codec_dai_name = "snd-soc-dummy-dai",
  5482. .codec_name = "snd-soc-dummy",
  5483. .ignore_suspend = 1,
  5484. /* this dainlink has playback support */
  5485. .ignore_pmdown_time = 1,
  5486. .id = MSM_FRONTEND_DAI_VOIP,
  5487. },
  5488. {
  5489. .name = MSM_DAILINK_NAME(ULL),
  5490. .stream_name = "MultiMedia3",
  5491. .cpu_dai_name = "MultiMedia3",
  5492. .platform_name = "msm-pcm-dsp.2",
  5493. .dynamic = 1,
  5494. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5495. .dpcm_playback = 1,
  5496. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5497. SND_SOC_DPCM_TRIGGER_POST},
  5498. .codec_dai_name = "snd-soc-dummy-dai",
  5499. .codec_name = "snd-soc-dummy",
  5500. .ignore_suspend = 1,
  5501. /* this dainlink has playback support */
  5502. .ignore_pmdown_time = 1,
  5503. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5504. },
  5505. /* Hostless PCM purpose */
  5506. {
  5507. .name = "SLIMBUS_0 Hostless",
  5508. .stream_name = "SLIMBUS_0 Hostless",
  5509. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5510. .platform_name = "msm-pcm-hostless",
  5511. .dynamic = 1,
  5512. .dpcm_playback = 1,
  5513. .dpcm_capture = 1,
  5514. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5515. SND_SOC_DPCM_TRIGGER_POST},
  5516. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5517. .ignore_suspend = 1,
  5518. /* this dailink has playback support */
  5519. .ignore_pmdown_time = 1,
  5520. .codec_dai_name = "snd-soc-dummy-dai",
  5521. .codec_name = "snd-soc-dummy",
  5522. },
  5523. {
  5524. .name = "MSM AFE-PCM RX",
  5525. .stream_name = "AFE-PROXY RX",
  5526. .cpu_dai_name = "msm-dai-q6-dev.241",
  5527. .codec_name = "msm-stub-codec.1",
  5528. .codec_dai_name = "msm-stub-rx",
  5529. .platform_name = "msm-pcm-afe",
  5530. .dpcm_playback = 1,
  5531. .ignore_suspend = 1,
  5532. /* this dainlink has playback support */
  5533. .ignore_pmdown_time = 1,
  5534. },
  5535. {
  5536. .name = "MSM AFE-PCM TX",
  5537. .stream_name = "AFE-PROXY TX",
  5538. .cpu_dai_name = "msm-dai-q6-dev.240",
  5539. .codec_name = "msm-stub-codec.1",
  5540. .codec_dai_name = "msm-stub-tx",
  5541. .platform_name = "msm-pcm-afe",
  5542. .dpcm_capture = 1,
  5543. .ignore_suspend = 1,
  5544. },
  5545. {
  5546. .name = MSM_DAILINK_NAME(Compress1),
  5547. .stream_name = "Compress1",
  5548. .cpu_dai_name = "MultiMedia4",
  5549. .platform_name = "msm-compress-dsp",
  5550. .dynamic = 1,
  5551. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5552. .dpcm_playback = 1,
  5553. .dpcm_capture = 1,
  5554. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5555. SND_SOC_DPCM_TRIGGER_POST},
  5556. .codec_dai_name = "snd-soc-dummy-dai",
  5557. .codec_name = "snd-soc-dummy",
  5558. .ignore_suspend = 1,
  5559. .ignore_pmdown_time = 1,
  5560. /* this dainlink has playback support */
  5561. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5562. },
  5563. {
  5564. .name = "AUXPCM Hostless",
  5565. .stream_name = "AUXPCM Hostless",
  5566. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5567. .platform_name = "msm-pcm-hostless",
  5568. .dynamic = 1,
  5569. .dpcm_playback = 1,
  5570. .dpcm_capture = 1,
  5571. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5572. SND_SOC_DPCM_TRIGGER_POST},
  5573. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5574. .ignore_suspend = 1,
  5575. /* this dainlink has playback support */
  5576. .ignore_pmdown_time = 1,
  5577. .codec_dai_name = "snd-soc-dummy-dai",
  5578. .codec_name = "snd-soc-dummy",
  5579. },
  5580. {
  5581. .name = "SLIMBUS_1 Hostless",
  5582. .stream_name = "SLIMBUS_1 Hostless",
  5583. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5584. .platform_name = "msm-pcm-hostless",
  5585. .dynamic = 1,
  5586. .dpcm_playback = 1,
  5587. .dpcm_capture = 1,
  5588. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5589. SND_SOC_DPCM_TRIGGER_POST},
  5590. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5591. .ignore_suspend = 1,
  5592. /* this dailink has playback support */
  5593. .ignore_pmdown_time = 1,
  5594. .codec_dai_name = "snd-soc-dummy-dai",
  5595. .codec_name = "snd-soc-dummy",
  5596. },
  5597. {
  5598. .name = "SLIMBUS_3 Hostless",
  5599. .stream_name = "SLIMBUS_3 Hostless",
  5600. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5601. .platform_name = "msm-pcm-hostless",
  5602. .dynamic = 1,
  5603. .dpcm_playback = 1,
  5604. .dpcm_capture = 1,
  5605. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5606. SND_SOC_DPCM_TRIGGER_POST},
  5607. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5608. .ignore_suspend = 1,
  5609. /* this dailink has playback support */
  5610. .ignore_pmdown_time = 1,
  5611. .codec_dai_name = "snd-soc-dummy-dai",
  5612. .codec_name = "snd-soc-dummy",
  5613. },
  5614. {
  5615. .name = "SLIMBUS_4 Hostless",
  5616. .stream_name = "SLIMBUS_4 Hostless",
  5617. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5618. .platform_name = "msm-pcm-hostless",
  5619. .dynamic = 1,
  5620. .dpcm_playback = 1,
  5621. .dpcm_capture = 1,
  5622. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5623. SND_SOC_DPCM_TRIGGER_POST},
  5624. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5625. .ignore_suspend = 1,
  5626. /* this dailink has playback support */
  5627. .ignore_pmdown_time = 1,
  5628. .codec_dai_name = "snd-soc-dummy-dai",
  5629. .codec_name = "snd-soc-dummy",
  5630. },
  5631. {
  5632. .name = MSM_DAILINK_NAME(LowLatency),
  5633. .stream_name = "MultiMedia5",
  5634. .cpu_dai_name = "MultiMedia5",
  5635. .platform_name = "msm-pcm-dsp.1",
  5636. .dynamic = 1,
  5637. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5638. .dpcm_playback = 1,
  5639. .dpcm_capture = 1,
  5640. .codec_dai_name = "snd-soc-dummy-dai",
  5641. .codec_name = "snd-soc-dummy",
  5642. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5643. SND_SOC_DPCM_TRIGGER_POST},
  5644. .ignore_suspend = 1,
  5645. /* this dainlink has playback support */
  5646. .ignore_pmdown_time = 1,
  5647. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5648. .ops = &msm_fe_qos_ops,
  5649. },
  5650. {
  5651. .name = "Listen 1 Audio Service",
  5652. .stream_name = "Listen 1 Audio Service",
  5653. .cpu_dai_name = "LSM1",
  5654. .platform_name = "msm-lsm-client",
  5655. .dynamic = 1,
  5656. .dpcm_capture = 1,
  5657. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5658. SND_SOC_DPCM_TRIGGER_POST },
  5659. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5660. .ignore_suspend = 1,
  5661. .codec_dai_name = "snd-soc-dummy-dai",
  5662. .codec_name = "snd-soc-dummy",
  5663. .id = MSM_FRONTEND_DAI_LSM1,
  5664. },
  5665. /* Multiple Tunnel instances */
  5666. {
  5667. .name = MSM_DAILINK_NAME(Compress2),
  5668. .stream_name = "Compress2",
  5669. .cpu_dai_name = "MultiMedia7",
  5670. .platform_name = "msm-compress-dsp",
  5671. .dynamic = 1,
  5672. .dpcm_playback = 1,
  5673. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5674. SND_SOC_DPCM_TRIGGER_POST},
  5675. .codec_dai_name = "snd-soc-dummy-dai",
  5676. .codec_name = "snd-soc-dummy",
  5677. .ignore_suspend = 1,
  5678. .ignore_pmdown_time = 1,
  5679. /* this dainlink has playback support */
  5680. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5681. },
  5682. {
  5683. .name = MSM_DAILINK_NAME(MultiMedia10),
  5684. .stream_name = "MultiMedia10",
  5685. .cpu_dai_name = "MultiMedia10",
  5686. .platform_name = "msm-pcm-dsp.1",
  5687. .dynamic = 1,
  5688. .dpcm_playback = 1,
  5689. .dpcm_capture = 1,
  5690. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5691. SND_SOC_DPCM_TRIGGER_POST},
  5692. .codec_dai_name = "snd-soc-dummy-dai",
  5693. .codec_name = "snd-soc-dummy",
  5694. .ignore_suspend = 1,
  5695. .ignore_pmdown_time = 1,
  5696. /* this dainlink has playback support */
  5697. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5698. },
  5699. {
  5700. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5701. .stream_name = "MM_NOIRQ",
  5702. .cpu_dai_name = "MultiMedia8",
  5703. .platform_name = "msm-pcm-dsp-noirq",
  5704. .dynamic = 1,
  5705. .dpcm_playback = 1,
  5706. .dpcm_capture = 1,
  5707. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5708. SND_SOC_DPCM_TRIGGER_POST},
  5709. .codec_dai_name = "snd-soc-dummy-dai",
  5710. .codec_name = "snd-soc-dummy",
  5711. .ignore_suspend = 1,
  5712. .ignore_pmdown_time = 1,
  5713. /* this dainlink has playback support */
  5714. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5715. .ops = &msm_fe_qos_ops,
  5716. },
  5717. /* HDMI Hostless */
  5718. {
  5719. .name = "HDMI_RX_HOSTLESS",
  5720. .stream_name = "HDMI_RX_HOSTLESS",
  5721. .cpu_dai_name = "HDMI_HOSTLESS",
  5722. .platform_name = "msm-pcm-hostless",
  5723. .dynamic = 1,
  5724. .dpcm_playback = 1,
  5725. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5726. SND_SOC_DPCM_TRIGGER_POST},
  5727. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5728. .ignore_suspend = 1,
  5729. .ignore_pmdown_time = 1,
  5730. .codec_dai_name = "snd-soc-dummy-dai",
  5731. .codec_name = "snd-soc-dummy",
  5732. },
  5733. {
  5734. .name = "VoiceMMode2",
  5735. .stream_name = "VoiceMMode2",
  5736. .cpu_dai_name = "VoiceMMode2",
  5737. .platform_name = "msm-pcm-voice",
  5738. .dynamic = 1,
  5739. .dpcm_playback = 1,
  5740. .dpcm_capture = 1,
  5741. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5742. SND_SOC_DPCM_TRIGGER_POST},
  5743. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5744. .ignore_suspend = 1,
  5745. .ignore_pmdown_time = 1,
  5746. .codec_dai_name = "snd-soc-dummy-dai",
  5747. .codec_name = "snd-soc-dummy",
  5748. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5749. },
  5750. /* LSM FE */
  5751. {
  5752. .name = "Listen 2 Audio Service",
  5753. .stream_name = "Listen 2 Audio Service",
  5754. .cpu_dai_name = "LSM2",
  5755. .platform_name = "msm-lsm-client",
  5756. .dynamic = 1,
  5757. .dpcm_capture = 1,
  5758. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5759. SND_SOC_DPCM_TRIGGER_POST },
  5760. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5761. .ignore_suspend = 1,
  5762. .codec_dai_name = "snd-soc-dummy-dai",
  5763. .codec_name = "snd-soc-dummy",
  5764. .id = MSM_FRONTEND_DAI_LSM2,
  5765. },
  5766. {
  5767. .name = "Listen 3 Audio Service",
  5768. .stream_name = "Listen 3 Audio Service",
  5769. .cpu_dai_name = "LSM3",
  5770. .platform_name = "msm-lsm-client",
  5771. .dynamic = 1,
  5772. .dpcm_capture = 1,
  5773. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5774. SND_SOC_DPCM_TRIGGER_POST },
  5775. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5776. .ignore_suspend = 1,
  5777. .codec_dai_name = "snd-soc-dummy-dai",
  5778. .codec_name = "snd-soc-dummy",
  5779. .id = MSM_FRONTEND_DAI_LSM3,
  5780. },
  5781. {
  5782. .name = "Listen 4 Audio Service",
  5783. .stream_name = "Listen 4 Audio Service",
  5784. .cpu_dai_name = "LSM4",
  5785. .platform_name = "msm-lsm-client",
  5786. .dynamic = 1,
  5787. .dpcm_capture = 1,
  5788. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5789. SND_SOC_DPCM_TRIGGER_POST },
  5790. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5791. .ignore_suspend = 1,
  5792. .codec_dai_name = "snd-soc-dummy-dai",
  5793. .codec_name = "snd-soc-dummy",
  5794. .id = MSM_FRONTEND_DAI_LSM4,
  5795. },
  5796. {
  5797. .name = "Listen 5 Audio Service",
  5798. .stream_name = "Listen 5 Audio Service",
  5799. .cpu_dai_name = "LSM5",
  5800. .platform_name = "msm-lsm-client",
  5801. .dynamic = 1,
  5802. .dpcm_capture = 1,
  5803. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5804. SND_SOC_DPCM_TRIGGER_POST },
  5805. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5806. .ignore_suspend = 1,
  5807. .codec_dai_name = "snd-soc-dummy-dai",
  5808. .codec_name = "snd-soc-dummy",
  5809. .id = MSM_FRONTEND_DAI_LSM5,
  5810. },
  5811. {
  5812. .name = "Listen 6 Audio Service",
  5813. .stream_name = "Listen 6 Audio Service",
  5814. .cpu_dai_name = "LSM6",
  5815. .platform_name = "msm-lsm-client",
  5816. .dynamic = 1,
  5817. .dpcm_capture = 1,
  5818. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5819. SND_SOC_DPCM_TRIGGER_POST },
  5820. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5821. .ignore_suspend = 1,
  5822. .codec_dai_name = "snd-soc-dummy-dai",
  5823. .codec_name = "snd-soc-dummy",
  5824. .id = MSM_FRONTEND_DAI_LSM6,
  5825. },
  5826. {
  5827. .name = "Listen 7 Audio Service",
  5828. .stream_name = "Listen 7 Audio Service",
  5829. .cpu_dai_name = "LSM7",
  5830. .platform_name = "msm-lsm-client",
  5831. .dynamic = 1,
  5832. .dpcm_capture = 1,
  5833. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5834. SND_SOC_DPCM_TRIGGER_POST },
  5835. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5836. .ignore_suspend = 1,
  5837. .codec_dai_name = "snd-soc-dummy-dai",
  5838. .codec_name = "snd-soc-dummy",
  5839. .id = MSM_FRONTEND_DAI_LSM7,
  5840. },
  5841. {
  5842. .name = "Listen 8 Audio Service",
  5843. .stream_name = "Listen 8 Audio Service",
  5844. .cpu_dai_name = "LSM8",
  5845. .platform_name = "msm-lsm-client",
  5846. .dynamic = 1,
  5847. .dpcm_capture = 1,
  5848. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5849. SND_SOC_DPCM_TRIGGER_POST },
  5850. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5851. .ignore_suspend = 1,
  5852. .codec_dai_name = "snd-soc-dummy-dai",
  5853. .codec_name = "snd-soc-dummy",
  5854. .id = MSM_FRONTEND_DAI_LSM8,
  5855. },
  5856. {
  5857. .name = MSM_DAILINK_NAME(Media9),
  5858. .stream_name = "MultiMedia9",
  5859. .cpu_dai_name = "MultiMedia9",
  5860. .platform_name = "msm-pcm-dsp.0",
  5861. .dynamic = 1,
  5862. .dpcm_playback = 1,
  5863. .dpcm_capture = 1,
  5864. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5865. SND_SOC_DPCM_TRIGGER_POST},
  5866. .codec_dai_name = "snd-soc-dummy-dai",
  5867. .codec_name = "snd-soc-dummy",
  5868. .ignore_suspend = 1,
  5869. /* this dainlink has playback support */
  5870. .ignore_pmdown_time = 1,
  5871. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5872. },
  5873. {
  5874. .name = MSM_DAILINK_NAME(Compress4),
  5875. .stream_name = "Compress4",
  5876. .cpu_dai_name = "MultiMedia11",
  5877. .platform_name = "msm-compress-dsp",
  5878. .dynamic = 1,
  5879. .dpcm_playback = 1,
  5880. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5881. SND_SOC_DPCM_TRIGGER_POST},
  5882. .codec_dai_name = "snd-soc-dummy-dai",
  5883. .codec_name = "snd-soc-dummy",
  5884. .ignore_suspend = 1,
  5885. .ignore_pmdown_time = 1,
  5886. /* this dainlink has playback support */
  5887. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5888. },
  5889. {
  5890. .name = MSM_DAILINK_NAME(Compress5),
  5891. .stream_name = "Compress5",
  5892. .cpu_dai_name = "MultiMedia12",
  5893. .platform_name = "msm-compress-dsp",
  5894. .dynamic = 1,
  5895. .dpcm_playback = 1,
  5896. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5897. SND_SOC_DPCM_TRIGGER_POST},
  5898. .codec_dai_name = "snd-soc-dummy-dai",
  5899. .codec_name = "snd-soc-dummy",
  5900. .ignore_suspend = 1,
  5901. .ignore_pmdown_time = 1,
  5902. /* this dainlink has playback support */
  5903. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5904. },
  5905. {
  5906. .name = MSM_DAILINK_NAME(Compress6),
  5907. .stream_name = "Compress6",
  5908. .cpu_dai_name = "MultiMedia13",
  5909. .platform_name = "msm-compress-dsp",
  5910. .dynamic = 1,
  5911. .dpcm_playback = 1,
  5912. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5913. SND_SOC_DPCM_TRIGGER_POST},
  5914. .codec_dai_name = "snd-soc-dummy-dai",
  5915. .codec_name = "snd-soc-dummy",
  5916. .ignore_suspend = 1,
  5917. .ignore_pmdown_time = 1,
  5918. /* this dainlink has playback support */
  5919. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5920. },
  5921. {
  5922. .name = MSM_DAILINK_NAME(Compress7),
  5923. .stream_name = "Compress7",
  5924. .cpu_dai_name = "MultiMedia14",
  5925. .platform_name = "msm-compress-dsp",
  5926. .dynamic = 1,
  5927. .dpcm_playback = 1,
  5928. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5929. SND_SOC_DPCM_TRIGGER_POST},
  5930. .codec_dai_name = "snd-soc-dummy-dai",
  5931. .codec_name = "snd-soc-dummy",
  5932. .ignore_suspend = 1,
  5933. .ignore_pmdown_time = 1,
  5934. /* this dainlink has playback support */
  5935. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5936. },
  5937. {
  5938. .name = MSM_DAILINK_NAME(Compress8),
  5939. .stream_name = "Compress8",
  5940. .cpu_dai_name = "MultiMedia15",
  5941. .platform_name = "msm-compress-dsp",
  5942. .dynamic = 1,
  5943. .dpcm_playback = 1,
  5944. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5945. SND_SOC_DPCM_TRIGGER_POST},
  5946. .codec_dai_name = "snd-soc-dummy-dai",
  5947. .codec_name = "snd-soc-dummy",
  5948. .ignore_suspend = 1,
  5949. .ignore_pmdown_time = 1,
  5950. /* this dainlink has playback support */
  5951. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5952. },
  5953. {
  5954. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5955. .stream_name = "MM_NOIRQ_2",
  5956. .cpu_dai_name = "MultiMedia16",
  5957. .platform_name = "msm-pcm-dsp-noirq",
  5958. .dynamic = 1,
  5959. .dpcm_playback = 1,
  5960. .dpcm_capture = 1,
  5961. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5962. SND_SOC_DPCM_TRIGGER_POST},
  5963. .codec_dai_name = "snd-soc-dummy-dai",
  5964. .codec_name = "snd-soc-dummy",
  5965. .ignore_suspend = 1,
  5966. .ignore_pmdown_time = 1,
  5967. /* this dainlink has playback support */
  5968. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5969. },
  5970. {
  5971. .name = "SLIMBUS_8 Hostless",
  5972. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5973. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5974. .platform_name = "msm-pcm-hostless",
  5975. .dynamic = 1,
  5976. .dpcm_capture = 1,
  5977. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5978. SND_SOC_DPCM_TRIGGER_POST},
  5979. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5980. .ignore_suspend = 1,
  5981. .codec_dai_name = "snd-soc-dummy-dai",
  5982. .codec_name = "snd-soc-dummy",
  5983. },
  5984. /* Hostless PCM purpose */
  5985. {
  5986. .name = "CDC_DMA Hostless",
  5987. .stream_name = "CDC_DMA Hostless",
  5988. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5989. .platform_name = "msm-pcm-hostless",
  5990. .dynamic = 1,
  5991. .dpcm_playback = 1,
  5992. .dpcm_capture = 1,
  5993. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5994. SND_SOC_DPCM_TRIGGER_POST},
  5995. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5996. .ignore_suspend = 1,
  5997. /* this dailink has playback support */
  5998. .ignore_pmdown_time = 1,
  5999. .codec_dai_name = "snd-soc-dummy-dai",
  6000. .codec_name = "snd-soc-dummy",
  6001. },
  6002. };
  6003. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  6004. {
  6005. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  6006. .stream_name = "WSA CDC DMA0 Capture",
  6007. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  6008. .platform_name = "msm-pcm-hostless",
  6009. .codec_name = "bolero_codec",
  6010. .codec_dai_name = "wsa_macro_vifeedback",
  6011. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  6012. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6013. .ignore_suspend = 1,
  6014. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6015. .ops = &msm_cdc_dma_be_ops,
  6016. },
  6017. };
  6018. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  6019. {
  6020. .name = MSM_DAILINK_NAME(ASM Loopback),
  6021. .stream_name = "MultiMedia6",
  6022. .cpu_dai_name = "MultiMedia6",
  6023. .platform_name = "msm-pcm-loopback",
  6024. .dynamic = 1,
  6025. .dpcm_playback = 1,
  6026. .dpcm_capture = 1,
  6027. .codec_dai_name = "snd-soc-dummy-dai",
  6028. .codec_name = "snd-soc-dummy",
  6029. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6030. SND_SOC_DPCM_TRIGGER_POST},
  6031. .ignore_suspend = 1,
  6032. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6033. .ignore_pmdown_time = 1,
  6034. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  6035. },
  6036. {
  6037. .name = "USB Audio Hostless",
  6038. .stream_name = "USB Audio Hostless",
  6039. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  6040. .platform_name = "msm-pcm-hostless",
  6041. .dynamic = 1,
  6042. .dpcm_playback = 1,
  6043. .dpcm_capture = 1,
  6044. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6045. SND_SOC_DPCM_TRIGGER_POST},
  6046. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6047. .ignore_suspend = 1,
  6048. .ignore_pmdown_time = 1,
  6049. .codec_dai_name = "snd-soc-dummy-dai",
  6050. .codec_name = "snd-soc-dummy",
  6051. },
  6052. {
  6053. .name = "SLIMBUS_7 Hostless",
  6054. .stream_name = "SLIMBUS_7 Hostless",
  6055. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  6056. .platform_name = "msm-pcm-hostless",
  6057. .dynamic = 1,
  6058. .dpcm_capture = 1,
  6059. .dpcm_playback = 1,
  6060. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6061. SND_SOC_DPCM_TRIGGER_POST},
  6062. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6063. .ignore_suspend = 1,
  6064. .ignore_pmdown_time = 1,
  6065. .codec_dai_name = "snd-soc-dummy-dai",
  6066. .codec_name = "snd-soc-dummy",
  6067. },
  6068. {
  6069. .name = MSM_DAILINK_NAME(Compr Capture2),
  6070. .stream_name = "Compr Capture2",
  6071. .cpu_dai_name = "MultiMedia18",
  6072. .platform_name = "msm-compress-dsp",
  6073. .dynamic = 1,
  6074. .dpcm_capture = 1,
  6075. .codec_dai_name = "snd-soc-dummy-dai",
  6076. .codec_name = "snd-soc-dummy",
  6077. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6078. SND_SOC_DPCM_TRIGGER_POST},
  6079. .ignore_pmdown_time = 1,
  6080. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  6081. },
  6082. {
  6083. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  6084. .stream_name = "Transcode Loopback Playback",
  6085. .cpu_dai_name = "MultiMedia26",
  6086. .platform_name = "msm-transcode-loopback",
  6087. .dynamic = 1,
  6088. .dpcm_playback = 1,
  6089. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6090. SND_SOC_DPCM_TRIGGER_POST},
  6091. .codec_dai_name = "snd-soc-dummy-dai",
  6092. .codec_name = "snd-soc-dummy",
  6093. .ignore_suspend = 1,
  6094. .ignore_pmdown_time = 1,
  6095. /* this dailink has playback support */
  6096. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  6097. },
  6098. {
  6099. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  6100. .stream_name = "Transcode Loopback Capture",
  6101. .cpu_dai_name = "MultiMedia27",
  6102. .platform_name = "msm-transcode-loopback",
  6103. .dynamic = 1,
  6104. .dpcm_capture = 1,
  6105. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6106. SND_SOC_DPCM_TRIGGER_POST},
  6107. .codec_dai_name = "snd-soc-dummy-dai",
  6108. .codec_name = "snd-soc-dummy",
  6109. .ignore_suspend = 1,
  6110. .ignore_pmdown_time = 1,
  6111. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  6112. },
  6113. {
  6114. .name = MSM_DAILINK_NAME(Compr Capture3),
  6115. .stream_name = "Compr Capture3",
  6116. .cpu_dai_name = "MultiMedia19",
  6117. .platform_name = "msm-compress-dsp",
  6118. .dynamic = 1,
  6119. .dpcm_capture = 1,
  6120. .codec_dai_name = "snd-soc-dummy-dai",
  6121. .codec_name = "snd-soc-dummy",
  6122. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6123. SND_SOC_DPCM_TRIGGER_POST},
  6124. .ignore_pmdown_time = 1,
  6125. .id = MSM_FRONTEND_DAI_MULTIMEDIA19,
  6126. },
  6127. {
  6128. .name = MSM_DAILINK_NAME(Compr Capture4),
  6129. .stream_name = "Compr Capture4",
  6130. .cpu_dai_name = "MultiMedia28",
  6131. .platform_name = "msm-compress-dsp",
  6132. .dynamic = 1,
  6133. .dpcm_capture = 1,
  6134. .codec_dai_name = "snd-soc-dummy-dai",
  6135. .codec_name = "snd-soc-dummy",
  6136. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6137. SND_SOC_DPCM_TRIGGER_POST},
  6138. .ignore_pmdown_time = 1,
  6139. .id = MSM_FRONTEND_DAI_MULTIMEDIA28,
  6140. },
  6141. {
  6142. .name = MSM_DAILINK_NAME(Compr Capture5),
  6143. .stream_name = "Compr Capture5",
  6144. .cpu_dai_name = "MultiMedia29",
  6145. .platform_name = "msm-compress-dsp",
  6146. .dynamic = 1,
  6147. .dpcm_capture = 1,
  6148. .codec_dai_name = "snd-soc-dummy-dai",
  6149. .codec_name = "snd-soc-dummy",
  6150. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6151. SND_SOC_DPCM_TRIGGER_POST},
  6152. .ignore_pmdown_time = 1,
  6153. .id = MSM_FRONTEND_DAI_MULTIMEDIA29,
  6154. },
  6155. };
  6156. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  6157. /* Backend AFE DAI Links */
  6158. {
  6159. .name = LPASS_BE_AFE_PCM_RX,
  6160. .stream_name = "AFE Playback",
  6161. .cpu_dai_name = "msm-dai-q6-dev.224",
  6162. .platform_name = "msm-pcm-routing",
  6163. .codec_name = "msm-stub-codec.1",
  6164. .codec_dai_name = "msm-stub-rx",
  6165. .no_pcm = 1,
  6166. .dpcm_playback = 1,
  6167. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  6168. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6169. /* this dainlink has playback support */
  6170. .ignore_pmdown_time = 1,
  6171. .ignore_suspend = 1,
  6172. },
  6173. {
  6174. .name = LPASS_BE_AFE_PCM_TX,
  6175. .stream_name = "AFE Capture",
  6176. .cpu_dai_name = "msm-dai-q6-dev.225",
  6177. .platform_name = "msm-pcm-routing",
  6178. .codec_name = "msm-stub-codec.1",
  6179. .codec_dai_name = "msm-stub-tx",
  6180. .no_pcm = 1,
  6181. .dpcm_capture = 1,
  6182. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  6183. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6184. .ignore_suspend = 1,
  6185. },
  6186. /* Incall Record Uplink BACK END DAI Link */
  6187. {
  6188. .name = LPASS_BE_INCALL_RECORD_TX,
  6189. .stream_name = "Voice Uplink Capture",
  6190. .cpu_dai_name = "msm-dai-q6-dev.32772",
  6191. .platform_name = "msm-pcm-routing",
  6192. .codec_name = "msm-stub-codec.1",
  6193. .codec_dai_name = "msm-stub-tx",
  6194. .no_pcm = 1,
  6195. .dpcm_capture = 1,
  6196. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  6197. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6198. .ignore_suspend = 1,
  6199. },
  6200. /* Incall Record Downlink BACK END DAI Link */
  6201. {
  6202. .name = LPASS_BE_INCALL_RECORD_RX,
  6203. .stream_name = "Voice Downlink Capture",
  6204. .cpu_dai_name = "msm-dai-q6-dev.32771",
  6205. .platform_name = "msm-pcm-routing",
  6206. .codec_name = "msm-stub-codec.1",
  6207. .codec_dai_name = "msm-stub-tx",
  6208. .no_pcm = 1,
  6209. .dpcm_capture = 1,
  6210. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  6211. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6212. .ignore_suspend = 1,
  6213. },
  6214. /* Incall Music BACK END DAI Link */
  6215. {
  6216. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  6217. .stream_name = "Voice Farend Playback",
  6218. .cpu_dai_name = "msm-dai-q6-dev.32773",
  6219. .platform_name = "msm-pcm-routing",
  6220. .codec_name = "msm-stub-codec.1",
  6221. .codec_dai_name = "msm-stub-rx",
  6222. .no_pcm = 1,
  6223. .dpcm_playback = 1,
  6224. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  6225. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6226. .ignore_suspend = 1,
  6227. .ignore_pmdown_time = 1,
  6228. },
  6229. /* Incall Music 2 BACK END DAI Link */
  6230. {
  6231. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  6232. .stream_name = "Voice2 Farend Playback",
  6233. .cpu_dai_name = "msm-dai-q6-dev.32770",
  6234. .platform_name = "msm-pcm-routing",
  6235. .codec_name = "msm-stub-codec.1",
  6236. .codec_dai_name = "msm-stub-rx",
  6237. .no_pcm = 1,
  6238. .dpcm_playback = 1,
  6239. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  6240. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6241. .ignore_suspend = 1,
  6242. .ignore_pmdown_time = 1,
  6243. },
  6244. {
  6245. .name = LPASS_BE_USB_AUDIO_RX,
  6246. .stream_name = "USB Audio Playback",
  6247. .cpu_dai_name = "msm-dai-q6-dev.28672",
  6248. .platform_name = "msm-pcm-routing",
  6249. .codec_name = "msm-stub-codec.1",
  6250. .codec_dai_name = "msm-stub-rx",
  6251. .no_pcm = 1,
  6252. .dpcm_playback = 1,
  6253. .id = MSM_BACKEND_DAI_USB_RX,
  6254. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6255. .ignore_pmdown_time = 1,
  6256. .ignore_suspend = 1,
  6257. },
  6258. {
  6259. .name = LPASS_BE_USB_AUDIO_TX,
  6260. .stream_name = "USB Audio Capture",
  6261. .cpu_dai_name = "msm-dai-q6-dev.28673",
  6262. .platform_name = "msm-pcm-routing",
  6263. .codec_name = "msm-stub-codec.1",
  6264. .codec_dai_name = "msm-stub-tx",
  6265. .no_pcm = 1,
  6266. .dpcm_capture = 1,
  6267. .id = MSM_BACKEND_DAI_USB_TX,
  6268. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6269. .ignore_suspend = 1,
  6270. },
  6271. {
  6272. .name = LPASS_BE_PRI_TDM_RX_0,
  6273. .stream_name = "Primary TDM0 Playback",
  6274. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  6275. .platform_name = "msm-pcm-routing",
  6276. .codec_name = "msm-stub-codec.1",
  6277. .codec_dai_name = "msm-stub-rx",
  6278. .no_pcm = 1,
  6279. .dpcm_playback = 1,
  6280. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  6281. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6282. .ops = &qcs405_tdm_be_ops,
  6283. .ignore_suspend = 1,
  6284. .ignore_pmdown_time = 1,
  6285. },
  6286. {
  6287. .name = LPASS_BE_PRI_TDM_TX_0,
  6288. .stream_name = "Primary TDM0 Capture",
  6289. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  6290. .platform_name = "msm-pcm-routing",
  6291. .codec_name = "msm-stub-codec.1",
  6292. .codec_dai_name = "msm-stub-tx",
  6293. .no_pcm = 1,
  6294. .dpcm_capture = 1,
  6295. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  6296. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6297. .ops = &qcs405_tdm_be_ops,
  6298. .ignore_suspend = 1,
  6299. },
  6300. {
  6301. .name = LPASS_BE_SEC_TDM_RX_0,
  6302. .stream_name = "Secondary TDM0 Playback",
  6303. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  6304. .platform_name = "msm-pcm-routing",
  6305. .codec_name = "msm-stub-codec.1",
  6306. .codec_dai_name = "msm-stub-rx",
  6307. .no_pcm = 1,
  6308. .dpcm_playback = 1,
  6309. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  6310. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6311. .ops = &qcs405_tdm_be_ops,
  6312. .ignore_suspend = 1,
  6313. .ignore_pmdown_time = 1,
  6314. },
  6315. {
  6316. .name = LPASS_BE_SEC_TDM_TX_0,
  6317. .stream_name = "Secondary TDM0 Capture",
  6318. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  6319. .platform_name = "msm-pcm-routing",
  6320. .codec_name = "msm-stub-codec.1",
  6321. .codec_dai_name = "msm-stub-tx",
  6322. .no_pcm = 1,
  6323. .dpcm_capture = 1,
  6324. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  6325. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6326. .ops = &qcs405_tdm_be_ops,
  6327. .ignore_suspend = 1,
  6328. },
  6329. {
  6330. .name = LPASS_BE_TERT_TDM_RX_0,
  6331. .stream_name = "Tertiary TDM0 Playback",
  6332. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  6333. .platform_name = "msm-pcm-routing",
  6334. .codec_name = "msm-stub-codec.1",
  6335. .codec_dai_name = "msm-stub-rx",
  6336. .no_pcm = 1,
  6337. .dpcm_playback = 1,
  6338. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  6339. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6340. .ops = &qcs405_tdm_be_ops,
  6341. .ignore_suspend = 1,
  6342. .ignore_pmdown_time = 1,
  6343. },
  6344. {
  6345. .name = LPASS_BE_TERT_TDM_TX_0,
  6346. .stream_name = "Tertiary TDM0 Capture",
  6347. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6348. .platform_name = "msm-pcm-routing",
  6349. .codec_name = "msm-stub-codec.1",
  6350. .codec_dai_name = "msm-stub-tx",
  6351. .no_pcm = 1,
  6352. .dpcm_capture = 1,
  6353. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6354. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6355. .ops = &qcs405_tdm_be_ops,
  6356. .ignore_suspend = 1,
  6357. },
  6358. {
  6359. .name = LPASS_BE_QUAT_TDM_RX_0,
  6360. .stream_name = "Quaternary TDM0 Playback",
  6361. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6362. .platform_name = "msm-pcm-routing",
  6363. .codec_name = "msm-stub-codec.1",
  6364. .codec_dai_name = "msm-stub-rx",
  6365. .no_pcm = 1,
  6366. .dpcm_playback = 1,
  6367. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6368. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6369. .ops = &qcs405_tdm_be_ops,
  6370. .ignore_suspend = 1,
  6371. .ignore_pmdown_time = 1,
  6372. },
  6373. {
  6374. .name = LPASS_BE_QUAT_TDM_TX_0,
  6375. .stream_name = "Quaternary TDM0 Capture",
  6376. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6377. .platform_name = "msm-pcm-routing",
  6378. .codec_name = "msm-stub-codec.1",
  6379. .codec_dai_name = "msm-stub-tx",
  6380. .no_pcm = 1,
  6381. .dpcm_capture = 1,
  6382. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6383. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6384. .ops = &qcs405_tdm_be_ops,
  6385. .ignore_suspend = 1,
  6386. },
  6387. {
  6388. .name = LPASS_BE_QUIN_TDM_RX_0,
  6389. .stream_name = "Quinary TDM0 Playback",
  6390. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6391. .platform_name = "msm-pcm-routing",
  6392. .codec_name = "msm-stub-codec.1",
  6393. .codec_dai_name = "msm-stub-rx",
  6394. .no_pcm = 1,
  6395. .dpcm_playback = 1,
  6396. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6397. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6398. .ops = &qcs405_tdm_be_ops,
  6399. .ignore_suspend = 1,
  6400. .ignore_pmdown_time = 1,
  6401. },
  6402. {
  6403. .name = LPASS_BE_QUIN_TDM_TX_0,
  6404. .stream_name = "Quinary TDM0 Capture",
  6405. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6406. .platform_name = "msm-pcm-routing",
  6407. .codec_name = "msm-stub-codec.1",
  6408. .codec_dai_name = "msm-stub-tx",
  6409. .no_pcm = 1,
  6410. .dpcm_capture = 1,
  6411. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6412. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6413. .ops = &qcs405_tdm_be_ops,
  6414. .ignore_suspend = 1,
  6415. },
  6416. };
  6417. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6418. {
  6419. .name = LPASS_BE_SLIMBUS_0_RX,
  6420. .stream_name = "Slimbus Playback",
  6421. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6422. .platform_name = "msm-pcm-routing",
  6423. .codec_name = "tasha_codec",
  6424. .codec_dai_name = "tasha_mix_rx1",
  6425. .no_pcm = 1,
  6426. .dpcm_playback = 1,
  6427. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6428. .init = &msm_audrx_init,
  6429. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6430. /* this dainlink has playback support */
  6431. .ignore_pmdown_time = 1,
  6432. .ignore_suspend = 1,
  6433. .ops = &msm_be_ops,
  6434. },
  6435. {
  6436. .name = LPASS_BE_SLIMBUS_0_TX,
  6437. .stream_name = "Slimbus Capture",
  6438. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6439. .platform_name = "msm-pcm-routing",
  6440. .codec_name = "tasha_codec",
  6441. .codec_dai_name = "tasha_tx1",
  6442. .no_pcm = 1,
  6443. .dpcm_capture = 1,
  6444. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6445. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6446. .ignore_suspend = 1,
  6447. .ops = &msm_be_ops,
  6448. },
  6449. {
  6450. .name = LPASS_BE_SLIMBUS_1_RX,
  6451. .stream_name = "Slimbus1 Playback",
  6452. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6453. .platform_name = "msm-pcm-routing",
  6454. .codec_name = "tasha_codec",
  6455. .codec_dai_name = "tasha_mix_rx1",
  6456. .no_pcm = 1,
  6457. .dpcm_playback = 1,
  6458. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6459. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6460. .ops = &msm_be_ops,
  6461. /* dai link has playback support */
  6462. .ignore_pmdown_time = 1,
  6463. .ignore_suspend = 1,
  6464. },
  6465. {
  6466. .name = LPASS_BE_SLIMBUS_1_TX,
  6467. .stream_name = "Slimbus1 Capture",
  6468. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6469. .platform_name = "msm-pcm-routing",
  6470. .codec_name = "tasha_codec",
  6471. .codec_dai_name = "tasha_tx3",
  6472. .no_pcm = 1,
  6473. .dpcm_capture = 1,
  6474. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6475. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6476. .ops = &msm_be_ops,
  6477. .ignore_suspend = 1,
  6478. },
  6479. {
  6480. .name = LPASS_BE_SLIMBUS_2_RX,
  6481. .stream_name = "Slimbus2 Playback",
  6482. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6483. .platform_name = "msm-pcm-routing",
  6484. .codec_name = "tasha_codec",
  6485. .codec_dai_name = "tasha_rx2",
  6486. .no_pcm = 1,
  6487. .dpcm_playback = 1,
  6488. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6489. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6490. .ops = &msm_be_ops,
  6491. .ignore_pmdown_time = 1,
  6492. .ignore_suspend = 1,
  6493. },
  6494. {
  6495. .name = LPASS_BE_SLIMBUS_3_RX,
  6496. .stream_name = "Slimbus3 Playback",
  6497. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6498. .platform_name = "msm-pcm-routing",
  6499. .codec_name = "tasha_codec",
  6500. .codec_dai_name = "tasha_mix_rx1",
  6501. .no_pcm = 1,
  6502. .dpcm_playback = 1,
  6503. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6504. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6505. .ops = &msm_be_ops,
  6506. /* dai link has playback support */
  6507. .ignore_pmdown_time = 1,
  6508. .ignore_suspend = 1,
  6509. },
  6510. {
  6511. .name = LPASS_BE_SLIMBUS_3_TX,
  6512. .stream_name = "Slimbus3 Capture",
  6513. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6514. .platform_name = "msm-pcm-routing",
  6515. .codec_name = "tasha_codec",
  6516. .codec_dai_name = "tasha_tx1",
  6517. .no_pcm = 1,
  6518. .dpcm_capture = 1,
  6519. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6520. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6521. .ops = &msm_be_ops,
  6522. .ignore_suspend = 1,
  6523. },
  6524. {
  6525. .name = LPASS_BE_SLIMBUS_4_RX,
  6526. .stream_name = "Slimbus4 Playback",
  6527. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6528. .platform_name = "msm-pcm-routing",
  6529. .codec_name = "tasha_codec",
  6530. .codec_dai_name = "tasha_mix_rx1",
  6531. .no_pcm = 1,
  6532. .dpcm_playback = 1,
  6533. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6534. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6535. .ops = &msm_be_ops,
  6536. /* dai link has playback support */
  6537. .ignore_pmdown_time = 1,
  6538. .ignore_suspend = 1,
  6539. },
  6540. {
  6541. .name = LPASS_BE_SLIMBUS_5_RX,
  6542. .stream_name = "Slimbus5 Playback",
  6543. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6544. .platform_name = "msm-pcm-routing",
  6545. .codec_name = "tasha_codec",
  6546. .codec_dai_name = "tasha_rx3",
  6547. .no_pcm = 1,
  6548. .dpcm_playback = 1,
  6549. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6550. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6551. .ops = &msm_be_ops,
  6552. /* dai link has playback support */
  6553. .ignore_pmdown_time = 1,
  6554. .ignore_suspend = 1,
  6555. },
  6556. {
  6557. .name = LPASS_BE_SLIMBUS_6_RX,
  6558. .stream_name = "Slimbus6 Playback",
  6559. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6560. .platform_name = "msm-pcm-routing",
  6561. .codec_name = "tasha_codec",
  6562. .codec_dai_name = "tasha_rx4",
  6563. .no_pcm = 1,
  6564. .dpcm_playback = 1,
  6565. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6566. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6567. .ops = &msm_be_ops,
  6568. /* dai link has playback support */
  6569. .ignore_pmdown_time = 1,
  6570. .ignore_suspend = 1,
  6571. },
  6572. /* Slimbus VI Recording */
  6573. {
  6574. .name = LPASS_BE_SLIMBUS_TX_VI,
  6575. .stream_name = "Slimbus4 Capture",
  6576. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6577. .platform_name = "msm-pcm-routing",
  6578. .codec_name = "tasha_codec",
  6579. .codec_dai_name = "tasha_vifeedback",
  6580. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6581. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6582. .ops = &msm_be_ops,
  6583. .ignore_suspend = 1,
  6584. .no_pcm = 1,
  6585. .dpcm_capture = 1,
  6586. .ignore_pmdown_time = 1,
  6587. },
  6588. };
  6589. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6590. {
  6591. .name = LPASS_BE_SLIMBUS_7_RX,
  6592. .stream_name = "Slimbus7 Playback",
  6593. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6594. .platform_name = "msm-pcm-routing",
  6595. .codec_name = "btfmslim_slave",
  6596. /* BT codec driver determines capabilities based on
  6597. * dai name, bt codecdai name should always contains
  6598. * supported usecase information
  6599. */
  6600. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6601. .no_pcm = 1,
  6602. .dpcm_playback = 1,
  6603. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6604. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6605. .ops = &msm_wcn_ops,
  6606. /* dai link has playback support */
  6607. .ignore_pmdown_time = 1,
  6608. .ignore_suspend = 1,
  6609. },
  6610. {
  6611. .name = LPASS_BE_SLIMBUS_7_TX,
  6612. .stream_name = "Slimbus7 Capture",
  6613. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6614. .platform_name = "msm-pcm-routing",
  6615. .codec_name = "btfmslim_slave",
  6616. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6617. .no_pcm = 1,
  6618. .dpcm_capture = 1,
  6619. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6620. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6621. .ops = &msm_wcn_ops,
  6622. .ignore_suspend = 1,
  6623. },
  6624. {
  6625. .name = LPASS_BE_SLIMBUS_8_TX,
  6626. .stream_name = "Slimbus8 Capture",
  6627. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6628. .platform_name = "msm-pcm-routing",
  6629. .codec_name = "btfmslim_slave",
  6630. .codec_dai_name = "btfm_fm_slim_tx",
  6631. .no_pcm = 1,
  6632. .dpcm_capture = 1,
  6633. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6634. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6635. .init = &msm_wcn_init,
  6636. .ops = &msm_wcn_ops,
  6637. .ignore_suspend = 1,
  6638. },
  6639. {
  6640. .name = LPASS_BE_SLIMBUS_9_TX,
  6641. .stream_name = "Slimbus9 Capture",
  6642. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6643. .platform_name = "msm-pcm-routing",
  6644. .codec_name = "btfmslim_slave",
  6645. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6646. .no_pcm = 1,
  6647. .dpcm_capture = 1,
  6648. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6649. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6650. .ops = &msm_wcn_ops,
  6651. .ignore_suspend = 1,
  6652. },
  6653. };
  6654. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6655. {
  6656. .name = LPASS_BE_PRI_MI2S_RX,
  6657. .stream_name = "Primary MI2S Playback",
  6658. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6659. .platform_name = "msm-pcm-routing",
  6660. .codec_name = "msm-stub-codec.1",
  6661. .codec_dai_name = "msm-stub-rx",
  6662. .no_pcm = 1,
  6663. .dpcm_playback = 1,
  6664. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6665. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6666. .ops = &msm_mi2s_be_ops,
  6667. .ignore_suspend = 1,
  6668. .ignore_pmdown_time = 1,
  6669. },
  6670. {
  6671. .name = LPASS_BE_PRI_MI2S_TX,
  6672. .stream_name = "Primary MI2S Capture",
  6673. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6674. .platform_name = "msm-pcm-routing",
  6675. .codec_name = "msm-stub-codec.1",
  6676. .codec_dai_name = "msm-stub-tx",
  6677. .no_pcm = 1,
  6678. .dpcm_capture = 1,
  6679. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6680. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6681. .ops = &msm_mi2s_be_ops,
  6682. .ignore_suspend = 1,
  6683. },
  6684. {
  6685. .name = LPASS_BE_SEC_MI2S_RX,
  6686. .stream_name = "Secondary MI2S Playback",
  6687. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6688. .platform_name = "msm-pcm-routing",
  6689. .codec_name = "msm-stub-codec.1",
  6690. .codec_dai_name = "msm-stub-rx",
  6691. .no_pcm = 1,
  6692. .dpcm_playback = 1,
  6693. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6694. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6695. .ops = &msm_mi2s_be_ops,
  6696. .ignore_suspend = 1,
  6697. .ignore_pmdown_time = 1,
  6698. },
  6699. {
  6700. .name = LPASS_BE_SEC_MI2S_TX,
  6701. .stream_name = "Secondary MI2S Capture",
  6702. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6703. .platform_name = "msm-pcm-routing",
  6704. .codec_name = "msm-stub-codec.1",
  6705. .codec_dai_name = "msm-stub-tx",
  6706. .no_pcm = 1,
  6707. .dpcm_capture = 1,
  6708. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6709. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6710. .ops = &msm_mi2s_be_ops,
  6711. .ignore_suspend = 1,
  6712. },
  6713. {
  6714. .name = LPASS_BE_TERT_MI2S_RX,
  6715. .stream_name = "Tertiary MI2S Playback",
  6716. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6717. .platform_name = "msm-pcm-routing",
  6718. .codec_name = "msm-stub-codec.1",
  6719. .codec_dai_name = "msm-stub-rx",
  6720. .no_pcm = 1,
  6721. .dpcm_playback = 1,
  6722. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6723. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6724. .ops = &msm_mi2s_be_ops,
  6725. .ignore_suspend = 1,
  6726. .ignore_pmdown_time = 1,
  6727. },
  6728. {
  6729. .name = LPASS_BE_TERT_MI2S_TX,
  6730. .stream_name = "Tertiary MI2S Capture",
  6731. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6732. .platform_name = "msm-pcm-routing",
  6733. .codec_name = "msm-stub-codec.1",
  6734. .codec_dai_name = "msm-stub-tx",
  6735. .no_pcm = 1,
  6736. .dpcm_capture = 1,
  6737. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6738. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6739. .ops = &msm_mi2s_be_ops,
  6740. .ignore_suspend = 1,
  6741. },
  6742. {
  6743. .name = LPASS_BE_QUAT_MI2S_RX,
  6744. .stream_name = "Quaternary MI2S Playback",
  6745. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6746. .platform_name = "msm-pcm-routing",
  6747. .codec_name = "msm-stub-codec.1",
  6748. .codec_dai_name = "msm-stub-rx",
  6749. .no_pcm = 1,
  6750. .dpcm_playback = 1,
  6751. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6752. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6753. .ops = &msm_mi2s_be_ops,
  6754. .ignore_suspend = 1,
  6755. .ignore_pmdown_time = 1,
  6756. },
  6757. {
  6758. .name = LPASS_BE_QUAT_MI2S_TX,
  6759. .stream_name = "Quaternary MI2S Capture",
  6760. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6761. .platform_name = "msm-pcm-routing",
  6762. .codec_name = "msm-stub-codec.1",
  6763. .codec_dai_name = "msm-stub-tx",
  6764. .no_pcm = 1,
  6765. .dpcm_capture = 1,
  6766. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6767. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6768. .ops = &msm_mi2s_be_ops,
  6769. .ignore_suspend = 1,
  6770. },
  6771. {
  6772. .name = LPASS_BE_QUIN_MI2S_RX,
  6773. .stream_name = "Quinary MI2S Playback",
  6774. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6775. .platform_name = "msm-pcm-routing",
  6776. .codec_name = "msm-stub-codec.1",
  6777. .codec_dai_name = "msm-stub-rx",
  6778. .no_pcm = 1,
  6779. .dpcm_playback = 1,
  6780. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6782. .ops = &msm_mi2s_be_ops,
  6783. .ignore_suspend = 1,
  6784. .ignore_pmdown_time = 1,
  6785. },
  6786. {
  6787. .name = LPASS_BE_QUIN_MI2S_TX,
  6788. .stream_name = "Quinary MI2S Capture",
  6789. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6790. .platform_name = "msm-pcm-routing",
  6791. .codec_name = "msm-stub-codec.1",
  6792. .codec_dai_name = "msm-stub-tx",
  6793. .no_pcm = 1,
  6794. .dpcm_capture = 1,
  6795. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6796. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6797. .ops = &msm_mi2s_be_ops,
  6798. .ignore_suspend = 1,
  6799. },
  6800. };
  6801. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6802. /* Primary AUX PCM Backend DAI Links */
  6803. {
  6804. .name = LPASS_BE_AUXPCM_RX,
  6805. .stream_name = "AUX PCM Playback",
  6806. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6807. .platform_name = "msm-pcm-routing",
  6808. .codec_name = "msm-stub-codec.1",
  6809. .codec_dai_name = "msm-stub-rx",
  6810. .no_pcm = 1,
  6811. .dpcm_playback = 1,
  6812. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6813. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6814. .ops = &msm_auxpcm_be_ops,
  6815. .ignore_pmdown_time = 1,
  6816. .ignore_suspend = 1,
  6817. },
  6818. {
  6819. .name = LPASS_BE_AUXPCM_TX,
  6820. .stream_name = "AUX PCM Capture",
  6821. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6822. .platform_name = "msm-pcm-routing",
  6823. .codec_name = "msm-stub-codec.1",
  6824. .codec_dai_name = "msm-stub-tx",
  6825. .no_pcm = 1,
  6826. .dpcm_capture = 1,
  6827. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6828. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6829. .ops = &msm_auxpcm_be_ops,
  6830. .ignore_suspend = 1,
  6831. },
  6832. /* Secondary AUX PCM Backend DAI Links */
  6833. {
  6834. .name = LPASS_BE_SEC_AUXPCM_RX,
  6835. .stream_name = "Sec AUX PCM Playback",
  6836. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6837. .platform_name = "msm-pcm-routing",
  6838. .codec_name = "msm-stub-codec.1",
  6839. .codec_dai_name = "msm-stub-rx",
  6840. .no_pcm = 1,
  6841. .dpcm_playback = 1,
  6842. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6843. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6844. .ops = &msm_auxpcm_be_ops,
  6845. .ignore_pmdown_time = 1,
  6846. .ignore_suspend = 1,
  6847. },
  6848. {
  6849. .name = LPASS_BE_SEC_AUXPCM_TX,
  6850. .stream_name = "Sec AUX PCM Capture",
  6851. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6852. .platform_name = "msm-pcm-routing",
  6853. .codec_name = "msm-stub-codec.1",
  6854. .codec_dai_name = "msm-stub-tx",
  6855. .no_pcm = 1,
  6856. .dpcm_capture = 1,
  6857. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6858. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6859. .ops = &msm_auxpcm_be_ops,
  6860. .ignore_suspend = 1,
  6861. },
  6862. /* Tertiary AUX PCM Backend DAI Links */
  6863. {
  6864. .name = LPASS_BE_TERT_AUXPCM_RX,
  6865. .stream_name = "Tert AUX PCM Playback",
  6866. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6867. .platform_name = "msm-pcm-routing",
  6868. .codec_name = "msm-stub-codec.1",
  6869. .codec_dai_name = "msm-stub-rx",
  6870. .no_pcm = 1,
  6871. .dpcm_playback = 1,
  6872. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6873. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6874. .ops = &msm_auxpcm_be_ops,
  6875. .ignore_suspend = 1,
  6876. },
  6877. {
  6878. .name = LPASS_BE_TERT_AUXPCM_TX,
  6879. .stream_name = "Tert AUX PCM Capture",
  6880. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6881. .platform_name = "msm-pcm-routing",
  6882. .codec_name = "msm-stub-codec.1",
  6883. .codec_dai_name = "msm-stub-tx",
  6884. .no_pcm = 1,
  6885. .dpcm_capture = 1,
  6886. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6887. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6888. .ops = &msm_auxpcm_be_ops,
  6889. .ignore_suspend = 1,
  6890. },
  6891. /* Quaternary AUX PCM Backend DAI Links */
  6892. {
  6893. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6894. .stream_name = "Quat AUX PCM Playback",
  6895. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6896. .platform_name = "msm-pcm-routing",
  6897. .codec_name = "msm-stub-codec.1",
  6898. .codec_dai_name = "msm-stub-rx",
  6899. .no_pcm = 1,
  6900. .dpcm_playback = 1,
  6901. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6902. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6903. .ops = &msm_auxpcm_be_ops,
  6904. .ignore_pmdown_time = 1,
  6905. .ignore_suspend = 1,
  6906. },
  6907. {
  6908. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6909. .stream_name = "Quat AUX PCM Capture",
  6910. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6911. .platform_name = "msm-pcm-routing",
  6912. .codec_name = "msm-stub-codec.1",
  6913. .codec_dai_name = "msm-stub-tx",
  6914. .no_pcm = 1,
  6915. .dpcm_capture = 1,
  6916. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6917. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6918. .ops = &msm_auxpcm_be_ops,
  6919. .ignore_suspend = 1,
  6920. },
  6921. /* Quinary AUX PCM Backend DAI Links */
  6922. {
  6923. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6924. .stream_name = "Quin AUX PCM Playback",
  6925. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6926. .platform_name = "msm-pcm-routing",
  6927. .codec_name = "msm-stub-codec.1",
  6928. .codec_dai_name = "msm-stub-rx",
  6929. .no_pcm = 1,
  6930. .dpcm_playback = 1,
  6931. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6932. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6933. .ops = &msm_auxpcm_be_ops,
  6934. .ignore_pmdown_time = 1,
  6935. .ignore_suspend = 1,
  6936. },
  6937. {
  6938. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6939. .stream_name = "Quin AUX PCM Capture",
  6940. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6941. .platform_name = "msm-pcm-routing",
  6942. .codec_name = "msm-stub-codec.1",
  6943. .codec_dai_name = "msm-stub-tx",
  6944. .no_pcm = 1,
  6945. .dpcm_capture = 1,
  6946. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6947. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6948. .ops = &msm_auxpcm_be_ops,
  6949. .ignore_suspend = 1,
  6950. },
  6951. };
  6952. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6953. /* WSA CDC DMA Backend DAI Links */
  6954. {
  6955. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6956. .stream_name = "WSA CDC DMA0 Playback",
  6957. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6958. .platform_name = "msm-pcm-routing",
  6959. .codec_name = "bolero_codec",
  6960. .codec_dai_name = "wsa_macro_rx1",
  6961. .no_pcm = 1,
  6962. .dpcm_playback = 1,
  6963. .init = &msm_wsa_cdc_dma_init,
  6964. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6965. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6966. .ignore_pmdown_time = 1,
  6967. .ignore_suspend = 1,
  6968. .ops = &msm_cdc_dma_be_ops,
  6969. },
  6970. {
  6971. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6972. .stream_name = "WSA CDC DMA1 Playback",
  6973. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6974. .platform_name = "msm-pcm-routing",
  6975. .codec_name = "bolero_codec",
  6976. .codec_dai_name = "wsa_macro_rx_mix",
  6977. .no_pcm = 1,
  6978. .dpcm_playback = 1,
  6979. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6980. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6981. .ignore_pmdown_time = 1,
  6982. .ignore_suspend = 1,
  6983. .ops = &msm_cdc_dma_be_ops,
  6984. },
  6985. {
  6986. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6987. .stream_name = "WSA CDC DMA1 Capture",
  6988. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6989. .platform_name = "msm-pcm-routing",
  6990. .codec_name = "bolero_codec",
  6991. .codec_dai_name = "wsa_macro_echo",
  6992. .no_pcm = 1,
  6993. .dpcm_capture = 1,
  6994. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6995. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6996. .ignore_suspend = 1,
  6997. .ops = &msm_cdc_dma_be_ops,
  6998. },
  6999. };
  7000. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  7001. {
  7002. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7003. .stream_name = "VA CDC DMA0 Capture",
  7004. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7005. .platform_name = "msm-pcm-routing",
  7006. .codec_name = "bolero_codec",
  7007. .codec_dai_name = "va_macro_tx1",
  7008. .no_pcm = 1,
  7009. .dpcm_capture = 1,
  7010. .init = &msm_va_cdc_dma_init,
  7011. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7012. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7013. .ignore_suspend = 1,
  7014. .ops = &msm_cdc_dma_be_ops,
  7015. },
  7016. {
  7017. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7018. .stream_name = "VA CDC DMA1 Capture",
  7019. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7020. .platform_name = "msm-pcm-routing",
  7021. .codec_name = "bolero_codec",
  7022. .codec_dai_name = "va_macro_tx2",
  7023. .no_pcm = 1,
  7024. .dpcm_capture = 1,
  7025. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7026. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7027. .ignore_suspend = 1,
  7028. .ops = &msm_cdc_dma_be_ops,
  7029. },
  7030. };
  7031. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  7032. {
  7033. .name = LPASS_BE_PRI_SPDIF_RX,
  7034. .stream_name = "Primary SPDIF Playback",
  7035. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  7036. .platform_name = "msm-pcm-routing",
  7037. .codec_name = "msm-stub-codec.1",
  7038. .codec_dai_name = "msm-stub-rx",
  7039. .no_pcm = 1,
  7040. .dpcm_playback = 1,
  7041. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  7042. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7043. .ops = &msm_spdif_be_ops,
  7044. .ignore_suspend = 1,
  7045. .ignore_pmdown_time = 1,
  7046. },
  7047. {
  7048. .name = LPASS_BE_PRI_SPDIF_TX,
  7049. .stream_name = "Primary SPDIF Capture",
  7050. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  7051. .platform_name = "msm-pcm-routing",
  7052. .codec_name = "msm-stub-codec.1",
  7053. .codec_dai_name = "msm-stub-tx",
  7054. .no_pcm = 1,
  7055. .dpcm_capture = 1,
  7056. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  7057. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7058. .ops = &msm_spdif_be_ops,
  7059. .ignore_suspend = 1,
  7060. },
  7061. {
  7062. .name = LPASS_BE_SEC_SPDIF_RX,
  7063. .stream_name = "Secondary SPDIF Playback",
  7064. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  7065. .platform_name = "msm-pcm-routing",
  7066. .codec_name = "msm-stub-codec.1",
  7067. .codec_dai_name = "msm-stub-rx",
  7068. .no_pcm = 1,
  7069. .dpcm_playback = 1,
  7070. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  7071. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7072. .ops = &msm_spdif_be_ops,
  7073. .ignore_suspend = 1,
  7074. .ignore_pmdown_time = 1,
  7075. },
  7076. {
  7077. .name = LPASS_BE_SEC_SPDIF_TX,
  7078. .stream_name = "Secondary SPDIF Capture",
  7079. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  7080. .platform_name = "msm-pcm-routing",
  7081. .codec_name = "msm-stub-codec.1",
  7082. .codec_dai_name = "msm-stub-tx",
  7083. .no_pcm = 1,
  7084. .dpcm_capture = 1,
  7085. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  7086. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7087. .ops = &msm_spdif_be_ops,
  7088. .ignore_suspend = 1,
  7089. },
  7090. };
  7091. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  7092. {
  7093. .name = LPASS_BE_AFE_LOOPBACK_TX,
  7094. .stream_name = "AFE Loopback Capture",
  7095. .cpu_dai_name = "msm-dai-q6-dev.24577",
  7096. .platform_name = "msm-pcm-routing",
  7097. .codec_name = "msm-stub-codec.1",
  7098. .codec_dai_name = "msm-stub-tx",
  7099. .no_pcm = 1,
  7100. .dpcm_capture = 1,
  7101. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  7102. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7103. .ignore_pmdown_time = 1,
  7104. .ignore_suspend = 1,
  7105. },
  7106. };
  7107. static struct snd_soc_dai_link msm_qcs405_dai_links[
  7108. ARRAY_SIZE(msm_common_dai_links) +
  7109. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  7110. ARRAY_SIZE(msm_common_be_dai_links) +
  7111. ARRAY_SIZE(msm_tasha_be_dai_links) +
  7112. ARRAY_SIZE(msm_wcn_be_dai_links) +
  7113. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  7114. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  7115. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  7116. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  7117. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  7118. ARRAY_SIZE(msm_spdif_be_dai_links) +
  7119. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link)];
  7120. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  7121. {
  7122. int ret = 0;
  7123. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  7124. &service_nb);
  7125. if (ret < 0)
  7126. pr_err("%s: Audio notifier register failed ret = %d\n",
  7127. __func__, ret);
  7128. return ret;
  7129. }
  7130. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  7131. struct snd_ctl_elem_value *ucontrol)
  7132. {
  7133. int ret = 0;
  7134. int port_id;
  7135. uint32_t vad_enable = ucontrol->value.integer.value[0];
  7136. uint32_t preroll_config = ucontrol->value.integer.value[1];
  7137. uint32_t vad_intf = ucontrol->value.integer.value[2];
  7138. if ((preroll_config < 0) || (preroll_config > 1000) ||
  7139. (vad_enable < 0) || (vad_enable > 1) ||
  7140. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  7141. pr_err("%s: Invalid arguments\n", __func__);
  7142. ret = -EINVAL;
  7143. goto done;
  7144. }
  7145. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  7146. vad_enable, preroll_config, vad_intf);
  7147. ret = msm_island_vad_get_portid_from_beid(vad_intf, &port_id);
  7148. if (ret) {
  7149. pr_err("%s: Invalid vad interface\n", __func__);
  7150. goto done;
  7151. }
  7152. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  7153. done:
  7154. return ret;
  7155. }
  7156. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  7157. {
  7158. int ret = 0;
  7159. uint32_t tasha_codec = 0;
  7160. ret = afe_cal_init_hwdep(card);
  7161. if (ret) {
  7162. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  7163. ret = 0;
  7164. }
  7165. /* tasha late probe when it is present */
  7166. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  7167. &tasha_codec);
  7168. if (ret) {
  7169. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  7170. ret = 0;
  7171. } else {
  7172. if (tasha_codec) {
  7173. ret = msm_snd_card_tasha_late_probe(card);
  7174. if (ret)
  7175. dev_err(card->dev, "%s: tasha late probe err\n",
  7176. __func__);
  7177. }
  7178. }
  7179. return ret;
  7180. }
  7181. struct snd_soc_card snd_soc_card_qcs405_msm = {
  7182. .name = "qcs405-snd-card",
  7183. .controls = msm_snd_controls,
  7184. .num_controls = ARRAY_SIZE(msm_snd_controls),
  7185. .late_probe = msm_snd_card_codec_late_probe,
  7186. };
  7187. static int msm_populate_dai_link_component_of_node(
  7188. struct snd_soc_card *card)
  7189. {
  7190. int i, index, ret = 0;
  7191. struct device *cdev = card->dev;
  7192. struct snd_soc_dai_link *dai_link = card->dai_link;
  7193. struct device_node *np;
  7194. if (!cdev) {
  7195. pr_err("%s: Sound card device memory NULL\n", __func__);
  7196. return -ENODEV;
  7197. }
  7198. for (i = 0; i < card->num_links; i++) {
  7199. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  7200. continue;
  7201. /* populate platform_of_node for snd card dai links */
  7202. if (dai_link[i].platform_name &&
  7203. !dai_link[i].platform_of_node) {
  7204. index = of_property_match_string(cdev->of_node,
  7205. "asoc-platform-names",
  7206. dai_link[i].platform_name);
  7207. if (index < 0) {
  7208. pr_err("%s: No match found for platform name: %s\n",
  7209. __func__, dai_link[i].platform_name);
  7210. ret = index;
  7211. goto err;
  7212. }
  7213. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  7214. index);
  7215. if (!np) {
  7216. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  7217. __func__, dai_link[i].platform_name,
  7218. index);
  7219. ret = -ENODEV;
  7220. goto err;
  7221. }
  7222. dai_link[i].platform_of_node = np;
  7223. dai_link[i].platform_name = NULL;
  7224. }
  7225. /* populate cpu_of_node for snd card dai links */
  7226. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  7227. index = of_property_match_string(cdev->of_node,
  7228. "asoc-cpu-names",
  7229. dai_link[i].cpu_dai_name);
  7230. if (index >= 0) {
  7231. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  7232. index);
  7233. if (!np) {
  7234. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  7235. __func__,
  7236. dai_link[i].cpu_dai_name);
  7237. ret = -ENODEV;
  7238. goto err;
  7239. }
  7240. dai_link[i].cpu_of_node = np;
  7241. dai_link[i].cpu_dai_name = NULL;
  7242. }
  7243. }
  7244. /* populate codec_of_node for snd card dai links */
  7245. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  7246. index = of_property_match_string(cdev->of_node,
  7247. "asoc-codec-names",
  7248. dai_link[i].codec_name);
  7249. if (index < 0)
  7250. continue;
  7251. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  7252. index);
  7253. if (!np) {
  7254. pr_err("%s: retrieving phandle for codec %s failed\n",
  7255. __func__, dai_link[i].codec_name);
  7256. ret = -ENODEV;
  7257. goto err;
  7258. }
  7259. dai_link[i].codec_of_node = np;
  7260. dai_link[i].codec_name = NULL;
  7261. }
  7262. }
  7263. err:
  7264. return ret;
  7265. }
  7266. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  7267. /* FrontEnd DAI Links */
  7268. {
  7269. .name = "MSMSTUB Media1",
  7270. .stream_name = "MultiMedia1",
  7271. .cpu_dai_name = "MultiMedia1",
  7272. .platform_name = "msm-pcm-dsp.0",
  7273. .dynamic = 1,
  7274. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  7275. .dpcm_playback = 1,
  7276. .dpcm_capture = 1,
  7277. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  7278. SND_SOC_DPCM_TRIGGER_POST},
  7279. .codec_dai_name = "snd-soc-dummy-dai",
  7280. .codec_name = "snd-soc-dummy",
  7281. .ignore_suspend = 1,
  7282. /* this dainlink has playback support */
  7283. .ignore_pmdown_time = 1,
  7284. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  7285. },
  7286. };
  7287. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  7288. /* Backend DAI Links */
  7289. {
  7290. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7291. .stream_name = "VA CDC DMA0 Capture",
  7292. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7293. .platform_name = "msm-pcm-routing",
  7294. .codec_name = "bolero_codec",
  7295. .codec_dai_name = "va_macro_tx1",
  7296. .no_pcm = 1,
  7297. .dpcm_capture = 1,
  7298. .init = &msm_va_cdc_dma_init,
  7299. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7300. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7301. .ignore_suspend = 1,
  7302. .ops = &msm_cdc_dma_be_ops,
  7303. },
  7304. {
  7305. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7306. .stream_name = "VA CDC DMA1 Capture",
  7307. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7308. .platform_name = "msm-pcm-routing",
  7309. .codec_name = "bolero_codec",
  7310. .codec_dai_name = "va_macro_tx2",
  7311. .no_pcm = 1,
  7312. .dpcm_capture = 1,
  7313. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7314. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7315. .ignore_suspend = 1,
  7316. .ops = &msm_cdc_dma_be_ops,
  7317. },
  7318. };
  7319. static struct snd_soc_dai_link msm_stub_dai_links[
  7320. ARRAY_SIZE(msm_stub_fe_dai_links) +
  7321. ARRAY_SIZE(msm_stub_be_dai_links)];
  7322. struct snd_soc_card snd_soc_card_stub_msm = {
  7323. .name = "qcs405-stub-snd-card",
  7324. };
  7325. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  7326. { .compatible = "qcom,qcs405-asoc-snd",
  7327. .data = "codec"},
  7328. { .compatible = "qcom,qcs405-asoc-snd-stub",
  7329. .data = "stub_codec"},
  7330. {},
  7331. };
  7332. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  7333. {
  7334. struct snd_soc_card *card = NULL;
  7335. struct snd_soc_dai_link *dailink;
  7336. int total_links = 0;
  7337. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  7338. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  7339. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  7340. uint32_t afe_loopback_intf = 0;
  7341. const struct of_device_id *match;
  7342. char __iomem *spdif_cfg, *spdif_pin_ctl;
  7343. int rc = 0;
  7344. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  7345. if (!match) {
  7346. dev_err(dev, "%s: No DT match found for sound card\n",
  7347. __func__);
  7348. return NULL;
  7349. }
  7350. if (!strcmp(match->data, "codec")) {
  7351. card = &snd_soc_card_qcs405_msm;
  7352. memcpy(msm_qcs405_dai_links + total_links,
  7353. msm_common_dai_links,
  7354. sizeof(msm_common_dai_links));
  7355. total_links += ARRAY_SIZE(msm_common_dai_links);
  7356. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  7357. &wsa_bolero_codec);
  7358. if (rc) {
  7359. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  7360. __func__);
  7361. } else {
  7362. if (wsa_bolero_codec) {
  7363. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  7364. __func__);
  7365. memcpy(msm_qcs405_dai_links + total_links,
  7366. msm_bolero_fe_dai_links,
  7367. sizeof(msm_bolero_fe_dai_links));
  7368. total_links +=
  7369. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7370. }
  7371. }
  7372. memcpy(msm_qcs405_dai_links + total_links,
  7373. msm_common_misc_fe_dai_links,
  7374. sizeof(msm_common_misc_fe_dai_links));
  7375. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7376. memcpy(msm_qcs405_dai_links + total_links,
  7377. msm_common_be_dai_links,
  7378. sizeof(msm_common_be_dai_links));
  7379. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7380. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7381. &tasha_codec);
  7382. if (rc) {
  7383. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7384. __func__);
  7385. } else {
  7386. if (tasha_codec) {
  7387. memcpy(msm_qcs405_dai_links + total_links,
  7388. msm_tasha_be_dai_links,
  7389. sizeof(msm_tasha_be_dai_links));
  7390. total_links +=
  7391. ARRAY_SIZE(msm_tasha_be_dai_links);
  7392. }
  7393. }
  7394. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7395. &va_bolero_codec);
  7396. if (rc) {
  7397. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7398. __func__);
  7399. } else {
  7400. if (va_bolero_codec) {
  7401. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7402. __func__);
  7403. memcpy(msm_qcs405_dai_links + total_links,
  7404. msm_va_cdc_dma_be_dai_links,
  7405. sizeof(msm_va_cdc_dma_be_dai_links));
  7406. total_links +=
  7407. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7408. }
  7409. }
  7410. if (wsa_bolero_codec) {
  7411. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7412. __func__);
  7413. memcpy(msm_qcs405_dai_links + total_links,
  7414. msm_wsa_cdc_dma_be_dai_links,
  7415. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7416. total_links +=
  7417. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7418. }
  7419. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7420. &mi2s_audio_intf);
  7421. if (rc) {
  7422. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7423. __func__);
  7424. } else {
  7425. if (mi2s_audio_intf) {
  7426. memcpy(msm_qcs405_dai_links + total_links,
  7427. msm_mi2s_be_dai_links,
  7428. sizeof(msm_mi2s_be_dai_links));
  7429. total_links +=
  7430. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7431. }
  7432. }
  7433. rc = of_property_read_u32(dev->of_node,
  7434. "qcom,auxpcm-audio-intf",
  7435. &auxpcm_audio_intf);
  7436. if (rc) {
  7437. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7438. __func__);
  7439. } else {
  7440. if (auxpcm_audio_intf) {
  7441. memcpy(msm_qcs405_dai_links + total_links,
  7442. msm_auxpcm_be_dai_links,
  7443. sizeof(msm_auxpcm_be_dai_links));
  7444. total_links +=
  7445. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7446. }
  7447. }
  7448. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7449. &spdif_audio_intf);
  7450. if (rc) {
  7451. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7452. __func__);
  7453. } else {
  7454. if (spdif_audio_intf) {
  7455. memcpy(msm_qcs405_dai_links + total_links,
  7456. msm_spdif_be_dai_links,
  7457. sizeof(msm_spdif_be_dai_links));
  7458. total_links +=
  7459. ARRAY_SIZE(msm_spdif_be_dai_links);
  7460. /* enable spdif coax pins */
  7461. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7462. spdif_pin_ctl =
  7463. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7464. iowrite32(0xc0, spdif_cfg);
  7465. iowrite32(0x2220, spdif_pin_ctl);
  7466. }
  7467. }
  7468. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7469. &wcn_audio_intf);
  7470. if (rc) {
  7471. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7472. __func__);
  7473. } else {
  7474. if (wcn_audio_intf) {
  7475. memcpy(msm_qcs405_dai_links + total_links,
  7476. msm_wcn_be_dai_links,
  7477. sizeof(msm_wcn_be_dai_links));
  7478. total_links +=
  7479. ARRAY_SIZE(msm_wcn_be_dai_links);
  7480. }
  7481. }
  7482. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  7483. &afe_loopback_intf);
  7484. if (rc) {
  7485. dev_dbg(dev, "%s: No DT match AFE loopback audio interface\n",
  7486. __func__);
  7487. } else {
  7488. if (afe_loopback_intf) {
  7489. memcpy(msm_qcs405_dai_links + total_links,
  7490. msm_afe_rxtx_lb_be_dai_link,
  7491. sizeof(msm_afe_rxtx_lb_be_dai_link));
  7492. total_links +=
  7493. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  7494. }
  7495. }
  7496. dailink = msm_qcs405_dai_links;
  7497. } else if (!strcmp(match->data, "stub_codec")) {
  7498. card = &snd_soc_card_stub_msm;
  7499. memcpy(msm_stub_dai_links + total_links,
  7500. msm_stub_fe_dai_links,
  7501. sizeof(msm_stub_fe_dai_links));
  7502. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7503. memcpy(msm_stub_dai_links + total_links,
  7504. msm_stub_be_dai_links,
  7505. sizeof(msm_stub_be_dai_links));
  7506. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7507. dailink = msm_stub_dai_links;
  7508. }
  7509. if (card) {
  7510. card->dai_link = dailink;
  7511. card->num_links = total_links;
  7512. }
  7513. return card;
  7514. }
  7515. static int msm_wsa881x_init(struct snd_soc_component *component)
  7516. {
  7517. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7518. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7519. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7520. SPKR_L_BOOST, SPKR_L_VI};
  7521. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7522. SPKR_R_BOOST, SPKR_R_VI};
  7523. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7524. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7525. struct msm_asoc_mach_data *pdata;
  7526. struct snd_soc_dapm_context *dapm;
  7527. int ret = 0;
  7528. if (!component) {
  7529. pr_err("%s component is NULL\n", __func__);
  7530. return -EINVAL;
  7531. }
  7532. dapm = snd_soc_component_get_dapm(component);
  7533. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7534. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  7535. __func__, component->name);
  7536. wsa881x_set_channel_map(component, &spkleft_ports[0],
  7537. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7538. &ch_rate[0], &spkleft_port_types[0]);
  7539. if (dapm->component) {
  7540. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7541. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7542. }
  7543. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7544. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  7545. __func__, component->name);
  7546. wsa881x_set_channel_map(component, &spkright_ports[0],
  7547. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7548. &ch_rate[0], &spkright_port_types[0]);
  7549. if (dapm->component) {
  7550. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7551. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7552. }
  7553. } else {
  7554. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  7555. component->name);
  7556. ret = -EINVAL;
  7557. goto err;
  7558. }
  7559. pdata = snd_soc_card_get_drvdata(component->card);
  7560. if (pdata && pdata->codec_root)
  7561. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7562. component);
  7563. err:
  7564. return ret;
  7565. }
  7566. static int msm_init_wsa_dev(struct platform_device *pdev,
  7567. struct snd_soc_card *card)
  7568. {
  7569. struct device_node *wsa_of_node;
  7570. u32 wsa_max_devs;
  7571. u32 wsa_dev_cnt;
  7572. int i;
  7573. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7574. const char *wsa_auxdev_name_prefix[1];
  7575. char *dev_name_str = NULL;
  7576. int found = 0;
  7577. int ret = 0;
  7578. /* Get maximum WSA device count for this platform */
  7579. ret = of_property_read_u32(pdev->dev.of_node,
  7580. "qcom,wsa-max-devs", &wsa_max_devs);
  7581. if (ret) {
  7582. dev_info(&pdev->dev,
  7583. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7584. __func__, pdev->dev.of_node->full_name, ret);
  7585. card->num_aux_devs = 0;
  7586. return 0;
  7587. }
  7588. if (wsa_max_devs == 0) {
  7589. dev_warn(&pdev->dev,
  7590. "%s: Max WSA devices is 0 for this target?\n",
  7591. __func__);
  7592. card->num_aux_devs = 0;
  7593. return 0;
  7594. }
  7595. /* Get count of WSA device phandles for this platform */
  7596. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7597. "qcom,wsa-devs", NULL);
  7598. if (wsa_dev_cnt == -ENOENT) {
  7599. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7600. __func__);
  7601. goto err;
  7602. } else if (wsa_dev_cnt <= 0) {
  7603. dev_err(&pdev->dev,
  7604. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7605. __func__, wsa_dev_cnt);
  7606. ret = -EINVAL;
  7607. goto err;
  7608. }
  7609. /*
  7610. * Expect total phandles count to be NOT less than maximum possible
  7611. * WSA count. However, if it is less, then assign same value to
  7612. * max count as well.
  7613. */
  7614. if (wsa_dev_cnt < wsa_max_devs) {
  7615. dev_dbg(&pdev->dev,
  7616. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7617. __func__, wsa_max_devs, wsa_dev_cnt);
  7618. wsa_max_devs = wsa_dev_cnt;
  7619. }
  7620. /* Make sure prefix string passed for each WSA device */
  7621. ret = of_property_count_strings(pdev->dev.of_node,
  7622. "qcom,wsa-aux-dev-prefix");
  7623. if (ret != wsa_dev_cnt) {
  7624. dev_err(&pdev->dev,
  7625. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7626. __func__, wsa_dev_cnt, ret);
  7627. ret = -EINVAL;
  7628. goto err;
  7629. }
  7630. /*
  7631. * Alloc mem to store phandle and index info of WSA device, if already
  7632. * registered with ALSA core
  7633. */
  7634. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7635. sizeof(struct msm_wsa881x_dev_info),
  7636. GFP_KERNEL);
  7637. if (!wsa881x_dev_info) {
  7638. ret = -ENOMEM;
  7639. goto err;
  7640. }
  7641. /*
  7642. * search and check whether all WSA devices are already
  7643. * registered with ALSA core or not. If found a node, store
  7644. * the node and the index in a local array of struct for later
  7645. * use.
  7646. */
  7647. for (i = 0; i < wsa_dev_cnt; i++) {
  7648. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7649. "qcom,wsa-devs", i);
  7650. if (unlikely(!wsa_of_node)) {
  7651. /* we should not be here */
  7652. dev_err(&pdev->dev,
  7653. "%s: wsa dev node is not present\n",
  7654. __func__);
  7655. ret = -EINVAL;
  7656. goto err_free_dev_info;
  7657. }
  7658. if (soc_find_component(wsa_of_node, NULL)) {
  7659. /* WSA device registered with ALSA core */
  7660. wsa881x_dev_info[found].of_node = wsa_of_node;
  7661. wsa881x_dev_info[found].index = i;
  7662. found++;
  7663. if (found == wsa_max_devs)
  7664. break;
  7665. }
  7666. }
  7667. if (found < wsa_max_devs) {
  7668. dev_err(&pdev->dev,
  7669. "%s: failed to find %d components. Found only %d\n",
  7670. __func__, wsa_max_devs, found);
  7671. return -EPROBE_DEFER;
  7672. }
  7673. dev_info(&pdev->dev,
  7674. "%s: found %d wsa881x devices registered with ALSA core\n",
  7675. __func__, found);
  7676. card->num_aux_devs = wsa_max_devs;
  7677. card->num_configs = wsa_max_devs;
  7678. /* Alloc array of AUX devs struct */
  7679. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7680. sizeof(struct snd_soc_aux_dev),
  7681. GFP_KERNEL);
  7682. if (!msm_aux_dev) {
  7683. ret = -ENOMEM;
  7684. goto err_free_dev_info;
  7685. }
  7686. /* Alloc array of codec conf struct */
  7687. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7688. sizeof(struct snd_soc_codec_conf),
  7689. GFP_KERNEL);
  7690. if (!msm_codec_conf) {
  7691. ret = -ENOMEM;
  7692. goto err_free_aux_dev;
  7693. }
  7694. for (i = 0; i < card->num_aux_devs; i++) {
  7695. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7696. GFP_KERNEL);
  7697. if (!dev_name_str) {
  7698. ret = -ENOMEM;
  7699. goto err_free_cdc_conf;
  7700. }
  7701. ret = of_property_read_string_index(pdev->dev.of_node,
  7702. "qcom,wsa-aux-dev-prefix",
  7703. wsa881x_dev_info[i].index,
  7704. wsa_auxdev_name_prefix);
  7705. if (ret) {
  7706. dev_err(&pdev->dev,
  7707. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7708. __func__, ret);
  7709. ret = -EINVAL;
  7710. goto err_free_dev_name_str;
  7711. }
  7712. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7713. msm_aux_dev[i].name = dev_name_str;
  7714. msm_aux_dev[i].codec_name = NULL;
  7715. msm_aux_dev[i].codec_of_node =
  7716. wsa881x_dev_info[i].of_node;
  7717. msm_aux_dev[i].init = msm_wsa881x_init;
  7718. msm_codec_conf[i].dev_name = NULL;
  7719. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7720. msm_codec_conf[i].of_node =
  7721. wsa881x_dev_info[i].of_node;
  7722. }
  7723. card->codec_conf = msm_codec_conf;
  7724. card->aux_dev = msm_aux_dev;
  7725. return 0;
  7726. err_free_dev_name_str:
  7727. devm_kfree(&pdev->dev, dev_name_str);
  7728. err_free_cdc_conf:
  7729. devm_kfree(&pdev->dev, msm_codec_conf);
  7730. err_free_aux_dev:
  7731. devm_kfree(&pdev->dev, msm_aux_dev);
  7732. err_free_dev_info:
  7733. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7734. err:
  7735. return ret;
  7736. }
  7737. static int msm_csra66x0_init(struct snd_soc_component *component)
  7738. {
  7739. if (!component) {
  7740. pr_err("%s component is NULL\n", __func__);
  7741. return -EINVAL;
  7742. }
  7743. return 0;
  7744. }
  7745. static int msm_init_csra_dev(struct platform_device *pdev,
  7746. struct snd_soc_card *card)
  7747. {
  7748. struct device_node *csra_of_node;
  7749. u32 csra_max_devs;
  7750. u32 csra_dev_cnt;
  7751. char *dev_name_str = NULL;
  7752. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7753. const char *csra_auxdev_name_prefix[1];
  7754. int i;
  7755. int found = 0;
  7756. int ret = 0;
  7757. /* Get maximum CSRA device count for this platform */
  7758. ret = of_property_read_u32(pdev->dev.of_node,
  7759. "qcom,csra-max-devs", &csra_max_devs);
  7760. if (ret) {
  7761. dev_info(&pdev->dev,
  7762. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7763. __func__, pdev->dev.of_node->full_name, ret);
  7764. card->num_aux_devs = 0;
  7765. return 0;
  7766. }
  7767. if (csra_max_devs == 0) {
  7768. dev_warn(&pdev->dev,
  7769. "%s: Max CSRA devices is 0 for this target?\n",
  7770. __func__);
  7771. return 0;
  7772. }
  7773. /* Get count of CSRA device phandles for this platform */
  7774. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7775. "qcom,csra-devs", NULL);
  7776. if (csra_dev_cnt == -ENOENT) {
  7777. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7778. __func__);
  7779. goto err;
  7780. } else if (csra_dev_cnt <= 0) {
  7781. dev_err(&pdev->dev,
  7782. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7783. __func__, csra_dev_cnt);
  7784. ret = -EINVAL;
  7785. goto err;
  7786. }
  7787. /*
  7788. * Expect total phandles count to be NOT less than maximum possible
  7789. * CSRA count. However, if it is less, then assign same value to
  7790. * max count as well.
  7791. */
  7792. if (csra_dev_cnt < csra_max_devs) {
  7793. dev_dbg(&pdev->dev,
  7794. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7795. __func__, csra_max_devs, csra_dev_cnt);
  7796. csra_max_devs = csra_dev_cnt;
  7797. }
  7798. /* Make sure prefix string passed for each CSRA device */
  7799. ret = of_property_count_strings(pdev->dev.of_node,
  7800. "qcom,csra-aux-dev-prefix");
  7801. if (ret != csra_dev_cnt) {
  7802. dev_err(&pdev->dev,
  7803. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7804. __func__, csra_dev_cnt, ret);
  7805. ret = -EINVAL;
  7806. goto err;
  7807. }
  7808. /*
  7809. * Alloc mem to store phandle and index info of CSRA device, if already
  7810. * registered with ALSA core
  7811. */
  7812. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7813. sizeof(struct msm_csra66x0_dev_info),
  7814. GFP_KERNEL);
  7815. if (!csra66x0_dev_info) {
  7816. ret = -ENOMEM;
  7817. goto err;
  7818. }
  7819. /*
  7820. * search and check whether all CSRA devices are already
  7821. * registered with ALSA core or not. If found a node, store
  7822. * the node and the index in a local array of struct for later
  7823. * use.
  7824. */
  7825. for (i = 0; i < csra_dev_cnt; i++) {
  7826. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7827. "qcom,csra-devs", i);
  7828. if (unlikely(!csra_of_node)) {
  7829. /* we should not be here */
  7830. dev_err(&pdev->dev,
  7831. "%s: csra dev node is not present\n",
  7832. __func__);
  7833. ret = -EINVAL;
  7834. goto err_free_dev_info;
  7835. }
  7836. if (soc_find_component(csra_of_node, NULL)) {
  7837. /* CSRA device registered with ALSA core */
  7838. csra66x0_dev_info[found].of_node = csra_of_node;
  7839. csra66x0_dev_info[found].index = i;
  7840. found++;
  7841. if (found == csra_max_devs)
  7842. break;
  7843. }
  7844. }
  7845. if (found < csra_max_devs) {
  7846. dev_dbg(&pdev->dev,
  7847. "%s: failed to find %d components. Found only %d\n",
  7848. __func__, csra_max_devs, found);
  7849. return -EPROBE_DEFER;
  7850. }
  7851. dev_info(&pdev->dev,
  7852. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7853. __func__, found);
  7854. card->num_aux_devs = csra_max_devs;
  7855. card->num_configs = csra_max_devs;
  7856. /* Alloc array of AUX devs struct */
  7857. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7858. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7859. if (!msm_aux_dev) {
  7860. ret = -ENOMEM;
  7861. goto err_free_dev_info;
  7862. }
  7863. /* Alloc array of codec conf struct */
  7864. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7865. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7866. if (!msm_codec_conf) {
  7867. ret = -ENOMEM;
  7868. goto err_free_aux_dev;
  7869. }
  7870. for (i = 0; i < card->num_aux_devs; i++) {
  7871. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7872. GFP_KERNEL);
  7873. if (!dev_name_str) {
  7874. ret = -ENOMEM;
  7875. goto err_free_cdc_conf;
  7876. }
  7877. ret = of_property_read_string_index(pdev->dev.of_node,
  7878. "qcom,csra-aux-dev-prefix",
  7879. csra66x0_dev_info[i].index,
  7880. csra_auxdev_name_prefix);
  7881. if (ret) {
  7882. dev_err(&pdev->dev,
  7883. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7884. __func__, ret);
  7885. ret = -EINVAL;
  7886. goto err_free_dev_name_str;
  7887. }
  7888. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7889. msm_aux_dev[i].name = dev_name_str;
  7890. msm_aux_dev[i].codec_name = NULL;
  7891. msm_aux_dev[i].codec_of_node =
  7892. csra66x0_dev_info[i].of_node;
  7893. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7894. msm_codec_conf[i].dev_name = NULL;
  7895. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7896. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7897. }
  7898. card->codec_conf = msm_codec_conf;
  7899. card->aux_dev = msm_aux_dev;
  7900. return 0;
  7901. err_free_dev_name_str:
  7902. devm_kfree(&pdev->dev, dev_name_str);
  7903. err_free_cdc_conf:
  7904. devm_kfree(&pdev->dev, msm_codec_conf);
  7905. err_free_aux_dev:
  7906. devm_kfree(&pdev->dev, msm_aux_dev);
  7907. err_free_dev_info:
  7908. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7909. err:
  7910. return ret;
  7911. }
  7912. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7913. {
  7914. int count;
  7915. u32 mi2s_master_slave[MI2S_MAX];
  7916. int ret;
  7917. for (count = 0; count < MI2S_MAX; count++) {
  7918. mutex_init(&mi2s_intf_conf[count].lock);
  7919. mi2s_intf_conf[count].ref_cnt = 0;
  7920. }
  7921. ret = of_property_read_u32_array(pdev->dev.of_node,
  7922. "qcom,msm-mi2s-master",
  7923. mi2s_master_slave, MI2S_MAX);
  7924. if (ret) {
  7925. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7926. __func__);
  7927. } else {
  7928. for (count = 0; count < MI2S_MAX; count++) {
  7929. mi2s_intf_conf[count].msm_is_mi2s_master =
  7930. mi2s_master_slave[count];
  7931. }
  7932. }
  7933. }
  7934. static void msm_i2s_auxpcm_deinit(void)
  7935. {
  7936. int count;
  7937. for (count = 0; count < MI2S_MAX; count++) {
  7938. mutex_destroy(&mi2s_intf_conf[count].lock);
  7939. mi2s_intf_conf[count].ref_cnt = 0;
  7940. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7941. }
  7942. }
  7943. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7944. uint32_t busnum, uint32_t addr)
  7945. {
  7946. struct i2c_adapter *adap;
  7947. u8 rbuf;
  7948. struct i2c_msg msg;
  7949. int status = 0;
  7950. adap = i2c_get_adapter(busnum);
  7951. if (!adap) {
  7952. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7953. __func__, busnum);
  7954. return -EBUSY;
  7955. }
  7956. /* to test presence, read one byte from device */
  7957. msg.addr = addr;
  7958. msg.flags = I2C_M_RD;
  7959. msg.len = 1;
  7960. msg.buf = &rbuf;
  7961. status = i2c_transfer(adap, &msg, 1);
  7962. i2c_put_adapter(adap);
  7963. if (status != 1) {
  7964. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7965. __func__, addr);
  7966. return -ENODEV;
  7967. }
  7968. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7969. __func__, addr);
  7970. return 0;
  7971. }
  7972. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7973. struct snd_soc_card *card)
  7974. {
  7975. int i;
  7976. uint32_t ep92_busnum = 0;
  7977. uint32_t ep92_reg = 0;
  7978. const char *ep92_name = NULL;
  7979. struct snd_soc_dai_link *dai;
  7980. int rc = 0;
  7981. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7982. &ep92_busnum);
  7983. if (rc) {
  7984. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7985. return 0;
  7986. }
  7987. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7988. &ep92_reg);
  7989. if (rc) {
  7990. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7991. return 0;
  7992. }
  7993. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7994. &ep92_name);
  7995. if (rc) {
  7996. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7997. return 0;
  7998. }
  7999. /* check I2C bus for connected ep92 chip */
  8000. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8001. /* check a second time after a short delay */
  8002. msleep(20);
  8003. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8004. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  8005. __func__);
  8006. /* continue with snd_card registration without ep92 */
  8007. return 0;
  8008. }
  8009. }
  8010. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  8011. /* update codec info in MI2S dai link */
  8012. dai = &msm_mi2s_be_dai_links[0];
  8013. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  8014. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  8015. dev_dbg(&pdev->dev,
  8016. "%s: Set Sec MI2S dai to ep92 codec\n",
  8017. __func__);
  8018. dai->codec_name = ep92_name;
  8019. dai->codec_dai_name = "ep92-hdmi";
  8020. break;
  8021. }
  8022. dai++;
  8023. }
  8024. /* update codec info in SPDIF dai link */
  8025. dai = &msm_spdif_be_dai_links[0];
  8026. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  8027. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  8028. dev_dbg(&pdev->dev,
  8029. "%s: Set Sec SPDIF dai to ep92 codec\n",
  8030. __func__);
  8031. dai->codec_name = ep92_name;
  8032. dai->codec_dai_name = "ep92-arc";
  8033. break;
  8034. }
  8035. dai++;
  8036. }
  8037. return 0;
  8038. }
  8039. static int msm_asoc_machine_probe(struct platform_device *pdev)
  8040. {
  8041. struct snd_soc_card *card;
  8042. struct msm_asoc_mach_data *pdata;
  8043. int ret;
  8044. u32 val;
  8045. const char *micb_supply_str = "tdm-vdd-micb-supply";
  8046. const char *micb_supply_str1 = "tdm-vdd-micb";
  8047. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  8048. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  8049. if (!pdev->dev.of_node) {
  8050. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  8051. return -EINVAL;
  8052. }
  8053. pdata = devm_kzalloc(&pdev->dev,
  8054. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  8055. if (!pdata)
  8056. return -ENOMEM;
  8057. /* test for ep92 HDMI bridge and update dai links accordingly */
  8058. ret = msm_detect_ep92_dev(pdev, card);
  8059. if (ret)
  8060. goto err;
  8061. card = populate_snd_card_dailinks(&pdev->dev);
  8062. if (!card) {
  8063. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  8064. ret = -EINVAL;
  8065. goto err;
  8066. }
  8067. card->dev = &pdev->dev;
  8068. platform_set_drvdata(pdev, card);
  8069. snd_soc_card_set_drvdata(card, pdata);
  8070. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  8071. if (ret) {
  8072. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  8073. ret);
  8074. goto err;
  8075. }
  8076. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  8077. if (ret) {
  8078. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  8079. ret);
  8080. goto err;
  8081. }
  8082. ret = msm_populate_dai_link_component_of_node(card);
  8083. if (ret) {
  8084. ret = -EPROBE_DEFER;
  8085. goto err;
  8086. }
  8087. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  8088. if (ret) {
  8089. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  8090. val = 0;
  8091. }
  8092. if (val) {
  8093. pdata->codec_is_csra = true;
  8094. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  8095. ret = msm_init_csra_dev(pdev, card);
  8096. if (ret)
  8097. goto err;
  8098. } else {
  8099. pdata->codec_is_csra = false;
  8100. ret = msm_init_wsa_dev(pdev, card);
  8101. if (ret)
  8102. goto err;
  8103. }
  8104. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8105. "qcom,cdc-dmic01-gpios", 0);
  8106. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8107. "qcom,cdc-dmic23-gpios", 0);
  8108. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8109. "qcom,cdc-dmic45-gpios", 0);
  8110. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8111. "qcom,cdc-dmic67-gpios", 0);
  8112. pdata->lineout_booster_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8113. "qcom,lineout-booster-gpio", 0);
  8114. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8115. "qcom,pri-mi2s-gpios", 0);
  8116. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8117. "qcom,sec-mi2s-gpios", 0);
  8118. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8119. "qcom,tert-mi2s-gpios", 0);
  8120. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8121. "qcom,quat-mi2s-gpios", 0);
  8122. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8123. "qcom,quin-mi2s-gpios", 0);
  8124. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  8125. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  8126. micb_supply_str1);
  8127. if (IS_ERR(pdata->tdm_micb_supply)) {
  8128. ret = PTR_ERR(pdata->tdm_micb_supply);
  8129. dev_err(&pdev->dev,
  8130. "%s:Failed to get micbias supply for TDM Mic %d\n",
  8131. __func__, ret);
  8132. }
  8133. ret = of_property_read_u32(pdev->dev.of_node,
  8134. micb_voltage_str,
  8135. &pdata->tdm_micb_voltage);
  8136. if (ret) {
  8137. dev_err(&pdev->dev,
  8138. "%s:Looking up %s property in node %s failed\n",
  8139. __func__, micb_voltage_str,
  8140. pdev->dev.of_node->full_name);
  8141. }
  8142. ret = of_property_read_u32(pdev->dev.of_node,
  8143. micb_current_str,
  8144. &pdata->tdm_micb_current);
  8145. if (ret) {
  8146. dev_err(&pdev->dev,
  8147. "%s:Looking up %s property in node %s failed\n",
  8148. __func__, micb_current_str,
  8149. pdev->dev.of_node->full_name);
  8150. }
  8151. }
  8152. ret = devm_snd_soc_register_card(&pdev->dev, card);
  8153. if (ret == -EPROBE_DEFER) {
  8154. if (codec_reg_done)
  8155. ret = -EINVAL;
  8156. goto err;
  8157. } else if (ret) {
  8158. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  8159. ret);
  8160. goto err;
  8161. }
  8162. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  8163. spdev = pdev;
  8164. ret = msm_mdf_mem_init();
  8165. if (ret)
  8166. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  8167. ret);
  8168. msm_i2s_auxpcm_init(pdev);
  8169. is_initial_boot = true;
  8170. return 0;
  8171. err:
  8172. return ret;
  8173. }
  8174. static int msm_asoc_machine_remove(struct platform_device *pdev)
  8175. {
  8176. audio_notifier_deregister("qcs405");
  8177. msm_i2s_auxpcm_deinit();
  8178. msm_mdf_mem_deinit();
  8179. return 0;
  8180. }
  8181. static struct platform_driver qcs405_asoc_machine_driver = {
  8182. .driver = {
  8183. .name = DRV_NAME,
  8184. .owner = THIS_MODULE,
  8185. .pm = &snd_soc_pm_ops,
  8186. .of_match_table = qcs405_asoc_machine_of_match,
  8187. },
  8188. .probe = msm_asoc_machine_probe,
  8189. .remove = msm_asoc_machine_remove,
  8190. };
  8191. module_platform_driver(qcs405_asoc_machine_driver);
  8192. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  8193. MODULE_LICENSE("GPL v2");
  8194. MODULE_ALIAS("platform:" DRV_NAME);
  8195. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);