dp_tx.c 109 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #if defined(FEATURE_TSO)
  63. /**
  64. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  65. *
  66. * @soc - core txrx main context
  67. * @seg_desc - tso segment descriptor
  68. * @num_seg_desc - tso number segment descriptor
  69. */
  70. static void dp_tx_tso_unmap_segment(
  71. struct dp_soc *soc,
  72. struct qdf_tso_seg_elem_t *seg_desc,
  73. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  74. {
  75. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  76. if (qdf_unlikely(!seg_desc)) {
  77. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  78. __func__, __LINE__);
  79. qdf_assert(0);
  80. } else if (qdf_unlikely(!num_seg_desc)) {
  81. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  82. __func__, __LINE__);
  83. qdf_assert(0);
  84. } else {
  85. bool is_last_seg;
  86. /* no tso segment left to do dma unmap */
  87. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  88. return;
  89. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  90. true : false;
  91. qdf_nbuf_unmap_tso_segment(soc->osdev,
  92. seg_desc, is_last_seg);
  93. num_seg_desc->num_seg.tso_cmn_num_seg--;
  94. }
  95. }
  96. /**
  97. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  98. * back to the freelist
  99. *
  100. * @soc - soc device handle
  101. * @tx_desc - Tx software descriptor
  102. */
  103. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  104. struct dp_tx_desc_s *tx_desc)
  105. {
  106. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  107. if (qdf_unlikely(!tx_desc->tso_desc)) {
  108. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  109. "%s %d TSO desc is NULL!",
  110. __func__, __LINE__);
  111. qdf_assert(0);
  112. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  113. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  114. "%s %d TSO num desc is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. /* Add the tso num segment into the free list */
  121. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  122. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  123. tx_desc->tso_num_desc);
  124. tx_desc->tso_num_desc = NULL;
  125. }
  126. /* Add the tso segment into the free list*/
  127. dp_tx_tso_desc_free(soc,
  128. tx_desc->pool_id, tx_desc->tso_desc);
  129. tx_desc->tso_desc = NULL;
  130. }
  131. }
  132. #else
  133. static void dp_tx_tso_unmap_segment(
  134. struct dp_soc *soc,
  135. struct qdf_tso_seg_elem_t *seg_desc,
  136. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  137. {
  138. }
  139. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  140. struct dp_tx_desc_s *tx_desc)
  141. {
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  167. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  170. qdf_atomic_dec(&pdev->num_tx_exception);
  171. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  172. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  173. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  174. soc->hal_soc);
  175. else
  176. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  178. "Tx Completion Release desc %d status %d outstanding %d",
  179. tx_desc->id, comp_status,
  180. qdf_atomic_read(&pdev->num_tx_outstanding));
  181. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  182. return;
  183. }
  184. /**
  185. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  186. * @vdev: DP vdev Handle
  187. * @nbuf: skb
  188. * @msdu_info: msdu_info required to create HTT metadata
  189. *
  190. * Prepares and fills HTT metadata in the frame pre-header for special frames
  191. * that should be transmitted using varying transmit parameters.
  192. * There are 2 VDEV modes that currently needs this special metadata -
  193. * 1) Mesh Mode
  194. * 2) DSRC Mode
  195. *
  196. * Return: HTT metadata size
  197. *
  198. */
  199. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  200. struct dp_tx_msdu_info_s *msdu_info)
  201. {
  202. uint32_t *meta_data = msdu_info->meta_data;
  203. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  204. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  205. uint8_t htt_desc_size;
  206. /* Size rounded of multiple of 8 bytes */
  207. uint8_t htt_desc_size_aligned;
  208. uint8_t *hdr = NULL;
  209. /*
  210. * Metadata - HTT MSDU Extension header
  211. */
  212. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  213. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  214. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer) {
  215. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  216. htt_desc_size_aligned)) {
  217. DP_STATS_INC(vdev,
  218. tx_i.dropped.headroom_insufficient, 1);
  219. return 0;
  220. }
  221. /* Fill and add HTT metaheader */
  222. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  223. if (!hdr) {
  224. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  225. "Error in filling HTT metadata");
  226. return 0;
  227. }
  228. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  229. } else if (vdev->opmode == wlan_op_mode_ocb) {
  230. /* Todo - Add support for DSRC */
  231. }
  232. return htt_desc_size_aligned;
  233. }
  234. /**
  235. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  236. * @tso_seg: TSO segment to process
  237. * @ext_desc: Pointer to MSDU extension descriptor
  238. *
  239. * Return: void
  240. */
  241. #if defined(FEATURE_TSO)
  242. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  243. void *ext_desc)
  244. {
  245. uint8_t num_frag;
  246. uint32_t tso_flags;
  247. /*
  248. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  249. * tcp_flag_mask
  250. *
  251. * Checksum enable flags are set in TCL descriptor and not in Extension
  252. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  253. */
  254. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  255. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  256. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  257. tso_seg->tso_flags.ip_len);
  258. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  259. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  260. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  261. uint32_t lo = 0;
  262. uint32_t hi = 0;
  263. qdf_dmaaddr_to_32s(
  264. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  265. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  266. tso_seg->tso_frags[num_frag].length);
  267. }
  268. return;
  269. }
  270. #else
  271. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  272. void *ext_desc)
  273. {
  274. return;
  275. }
  276. #endif
  277. #if defined(FEATURE_TSO)
  278. /**
  279. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  280. * allocated and free them
  281. *
  282. * @soc: soc handle
  283. * @free_seg: list of tso segments
  284. * @msdu_info: msdu descriptor
  285. *
  286. * Return - void
  287. */
  288. static void dp_tx_free_tso_seg_list(
  289. struct dp_soc *soc,
  290. struct qdf_tso_seg_elem_t *free_seg,
  291. struct dp_tx_msdu_info_s *msdu_info)
  292. {
  293. struct qdf_tso_seg_elem_t *next_seg;
  294. while (free_seg) {
  295. next_seg = free_seg->next;
  296. dp_tx_tso_desc_free(soc,
  297. msdu_info->tx_queue.desc_pool_id,
  298. free_seg);
  299. free_seg = next_seg;
  300. }
  301. }
  302. /**
  303. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  304. * allocated and free them
  305. *
  306. * @soc: soc handle
  307. * @free_num_seg: list of tso number segments
  308. * @msdu_info: msdu descriptor
  309. * Return - void
  310. */
  311. static void dp_tx_free_tso_num_seg_list(
  312. struct dp_soc *soc,
  313. struct qdf_tso_num_seg_elem_t *free_num_seg,
  314. struct dp_tx_msdu_info_s *msdu_info)
  315. {
  316. struct qdf_tso_num_seg_elem_t *next_num_seg;
  317. while (free_num_seg) {
  318. next_num_seg = free_num_seg->next;
  319. dp_tso_num_seg_free(soc,
  320. msdu_info->tx_queue.desc_pool_id,
  321. free_num_seg);
  322. free_num_seg = next_num_seg;
  323. }
  324. }
  325. /**
  326. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  327. * do dma unmap for each segment
  328. *
  329. * @soc: soc handle
  330. * @free_seg: list of tso segments
  331. * @num_seg_desc: tso number segment descriptor
  332. *
  333. * Return - void
  334. */
  335. static void dp_tx_unmap_tso_seg_list(
  336. struct dp_soc *soc,
  337. struct qdf_tso_seg_elem_t *free_seg,
  338. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  339. {
  340. struct qdf_tso_seg_elem_t *next_seg;
  341. if (qdf_unlikely(!num_seg_desc)) {
  342. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  343. return;
  344. }
  345. while (free_seg) {
  346. next_seg = free_seg->next;
  347. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  348. free_seg = next_seg;
  349. }
  350. }
  351. /**
  352. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  353. * free the tso segments descriptor and
  354. * tso num segments descriptor
  355. *
  356. * @soc: soc handle
  357. * @msdu_info: msdu descriptor
  358. * @tso_seg_unmap: flag to show if dma unmap is necessary
  359. *
  360. * Return - void
  361. */
  362. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  363. struct dp_tx_msdu_info_s *msdu_info,
  364. bool tso_seg_unmap)
  365. {
  366. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  367. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  368. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  369. tso_info->tso_num_seg_list;
  370. /* do dma unmap for each segment */
  371. if (tso_seg_unmap)
  372. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  373. /* free all tso number segment descriptor though looks only have 1 */
  374. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  375. /* free all tso segment descriptor */
  376. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  377. }
  378. /**
  379. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  380. * @vdev: virtual device handle
  381. * @msdu: network buffer
  382. * @msdu_info: meta data associated with the msdu
  383. *
  384. * Return: QDF_STATUS_SUCCESS success
  385. */
  386. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  387. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  388. {
  389. struct qdf_tso_seg_elem_t *tso_seg;
  390. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  391. struct dp_soc *soc = vdev->pdev->soc;
  392. struct qdf_tso_info_t *tso_info;
  393. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  394. tso_info = &msdu_info->u.tso_info;
  395. tso_info->curr_seg = NULL;
  396. tso_info->tso_seg_list = NULL;
  397. tso_info->num_segs = num_seg;
  398. msdu_info->frm_type = dp_tx_frm_tso;
  399. tso_info->tso_num_seg_list = NULL;
  400. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  401. while (num_seg) {
  402. tso_seg = dp_tx_tso_desc_alloc(
  403. soc, msdu_info->tx_queue.desc_pool_id);
  404. if (tso_seg) {
  405. tso_seg->next = tso_info->tso_seg_list;
  406. tso_info->tso_seg_list = tso_seg;
  407. num_seg--;
  408. } else {
  409. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  410. __func__);
  411. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  412. return QDF_STATUS_E_NOMEM;
  413. }
  414. }
  415. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  416. tso_num_seg = dp_tso_num_seg_alloc(soc,
  417. msdu_info->tx_queue.desc_pool_id);
  418. if (tso_num_seg) {
  419. tso_num_seg->next = tso_info->tso_num_seg_list;
  420. tso_info->tso_num_seg_list = tso_num_seg;
  421. } else {
  422. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  423. __func__);
  424. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  425. return QDF_STATUS_E_NOMEM;
  426. }
  427. msdu_info->num_seg =
  428. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  429. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  430. msdu_info->num_seg);
  431. if (!(msdu_info->num_seg)) {
  432. /*
  433. * Free allocated TSO seg desc and number seg desc,
  434. * do unmap for segments if dma map has done.
  435. */
  436. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  437. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  438. return QDF_STATUS_E_INVAL;
  439. }
  440. tso_info->curr_seg = tso_info->tso_seg_list;
  441. return QDF_STATUS_SUCCESS;
  442. }
  443. #else
  444. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  445. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  446. {
  447. return QDF_STATUS_E_NOMEM;
  448. }
  449. #endif
  450. /**
  451. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  452. * @vdev: DP Vdev handle
  453. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  454. * @desc_pool_id: Descriptor Pool ID
  455. *
  456. * Return:
  457. */
  458. static
  459. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  460. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  461. {
  462. uint8_t i;
  463. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  464. struct dp_tx_seg_info_s *seg_info;
  465. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  466. struct dp_soc *soc = vdev->pdev->soc;
  467. /* Allocate an extension descriptor */
  468. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  469. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  470. if (!msdu_ext_desc) {
  471. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  472. return NULL;
  473. }
  474. if (msdu_info->exception_fw &&
  475. qdf_unlikely(vdev->mesh_vdev)) {
  476. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  477. &msdu_info->meta_data[0],
  478. sizeof(struct htt_tx_msdu_desc_ext2_t));
  479. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  480. }
  481. switch (msdu_info->frm_type) {
  482. case dp_tx_frm_sg:
  483. case dp_tx_frm_me:
  484. case dp_tx_frm_raw:
  485. seg_info = msdu_info->u.sg_info.curr_seg;
  486. /* Update the buffer pointers in MSDU Extension Descriptor */
  487. for (i = 0; i < seg_info->frag_cnt; i++) {
  488. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  489. seg_info->frags[i].paddr_lo,
  490. seg_info->frags[i].paddr_hi,
  491. seg_info->frags[i].len);
  492. }
  493. break;
  494. case dp_tx_frm_tso:
  495. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  496. &cached_ext_desc[0]);
  497. break;
  498. default:
  499. break;
  500. }
  501. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  502. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  503. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  504. msdu_ext_desc->vaddr);
  505. return msdu_ext_desc;
  506. }
  507. /**
  508. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  509. *
  510. * @skb: skb to be traced
  511. * @msdu_id: msdu_id of the packet
  512. * @vdev_id: vdev_id of the packet
  513. *
  514. * Return: None
  515. */
  516. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  517. uint8_t vdev_id)
  518. {
  519. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  520. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  521. DPTRACE(qdf_dp_trace_ptr(skb,
  522. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  523. QDF_TRACE_DEFAULT_PDEV_ID,
  524. qdf_nbuf_data_addr(skb),
  525. sizeof(qdf_nbuf_data(skb)),
  526. msdu_id, vdev_id));
  527. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  528. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  529. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  530. msdu_id, QDF_TX));
  531. }
  532. #ifdef QCA_512M_CONFIG
  533. /**
  534. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  535. * tx descriptor configured value
  536. * @vdev: DP vdev handle
  537. *
  538. * Return: true if allocated tx descriptors reached max configured value, else
  539. * false.
  540. */
  541. static inline bool
  542. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  543. {
  544. struct dp_pdev *pdev = vdev->pdev;
  545. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  546. pdev->num_tx_allowed) {
  547. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  548. "%s: queued packets are more than max tx, drop the frame",
  549. __func__);
  550. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  551. return true;
  552. }
  553. return false;
  554. }
  555. #else
  556. static inline bool
  557. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  558. {
  559. return false;
  560. }
  561. #endif
  562. /**
  563. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  564. * @vdev: DP vdev handle
  565. * @nbuf: skb
  566. * @desc_pool_id: Descriptor pool ID
  567. * @meta_data: Metadata to the fw
  568. * @tx_exc_metadata: Handle that holds exception path metadata
  569. * Allocate and prepare Tx descriptor with msdu information.
  570. *
  571. * Return: Pointer to Tx Descriptor on success,
  572. * NULL on failure
  573. */
  574. static
  575. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  576. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  577. struct dp_tx_msdu_info_s *msdu_info,
  578. struct cdp_tx_exception_metadata *tx_exc_metadata)
  579. {
  580. uint8_t align_pad;
  581. uint8_t is_exception = 0;
  582. uint8_t htt_hdr_size;
  583. qdf_ether_header_t *eh;
  584. struct dp_tx_desc_s *tx_desc;
  585. struct dp_pdev *pdev = vdev->pdev;
  586. struct dp_soc *soc = pdev->soc;
  587. if (dp_tx_pdev_pflow_control(vdev))
  588. return NULL;
  589. /* Allocate software Tx descriptor */
  590. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  591. if (qdf_unlikely(!tx_desc)) {
  592. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  593. return NULL;
  594. }
  595. /* Flow control/Congestion Control counters */
  596. qdf_atomic_inc(&pdev->num_tx_outstanding);
  597. /* Initialize the SW tx descriptor */
  598. tx_desc->nbuf = nbuf;
  599. tx_desc->frm_type = dp_tx_frm_std;
  600. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  601. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  602. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  603. tx_desc->vdev = vdev;
  604. tx_desc->pdev = pdev;
  605. tx_desc->msdu_ext_desc = NULL;
  606. tx_desc->pkt_offset = 0;
  607. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  608. /*
  609. * For special modes (vdev_type == ocb or mesh), data frames should be
  610. * transmitted using varying transmit parameters (tx spec) which include
  611. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  612. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  613. * These frames are sent as exception packets to firmware.
  614. *
  615. * HW requirement is that metadata should always point to a
  616. * 8-byte aligned address. So we add alignment pad to start of buffer.
  617. * HTT Metadata should be ensured to be multiple of 8-bytes,
  618. * to get 8-byte aligned start address along with align_pad added
  619. *
  620. * |-----------------------------|
  621. * | |
  622. * |-----------------------------| <-----Buffer Pointer Address given
  623. * | | ^ in HW descriptor (aligned)
  624. * | HTT Metadata | |
  625. * | | |
  626. * | | | Packet Offset given in descriptor
  627. * | | |
  628. * |-----------------------------| |
  629. * | Alignment Pad | v
  630. * |-----------------------------| <----- Actual buffer start address
  631. * | SKB Data | (Unaligned)
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * | |
  637. * |-----------------------------|
  638. */
  639. if (qdf_unlikely((msdu_info->exception_fw)) ||
  640. (vdev->opmode == wlan_op_mode_ocb) ||
  641. (tx_exc_metadata &&
  642. tx_exc_metadata->is_tx_sniffer)) {
  643. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  644. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  645. DP_STATS_INC(vdev,
  646. tx_i.dropped.headroom_insufficient, 1);
  647. goto failure;
  648. }
  649. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  651. "qdf_nbuf_push_head failed");
  652. goto failure;
  653. }
  654. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  655. msdu_info);
  656. if (htt_hdr_size == 0)
  657. goto failure;
  658. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  659. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  660. is_exception = 1;
  661. }
  662. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  663. qdf_nbuf_map(soc->osdev, nbuf,
  664. QDF_DMA_TO_DEVICE))) {
  665. /* Handle failure */
  666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  667. "qdf_nbuf_map failed");
  668. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  669. goto failure;
  670. }
  671. if (qdf_unlikely(vdev->nawds_enabled)) {
  672. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  673. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  674. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  675. is_exception = 1;
  676. }
  677. }
  678. #if !TQM_BYPASS_WAR
  679. if (is_exception || tx_exc_metadata)
  680. #endif
  681. {
  682. /* Temporary WAR due to TQM VP issues */
  683. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  684. qdf_atomic_inc(&pdev->num_tx_exception);
  685. }
  686. return tx_desc;
  687. failure:
  688. dp_tx_desc_release(tx_desc, desc_pool_id);
  689. return NULL;
  690. }
  691. /**
  692. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  693. * @vdev: DP vdev handle
  694. * @nbuf: skb
  695. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  696. * @desc_pool_id : Descriptor Pool ID
  697. *
  698. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  699. * information. For frames wth fragments, allocate and prepare
  700. * an MSDU extension descriptor
  701. *
  702. * Return: Pointer to Tx Descriptor on success,
  703. * NULL on failure
  704. */
  705. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  706. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  707. uint8_t desc_pool_id)
  708. {
  709. struct dp_tx_desc_s *tx_desc;
  710. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  711. struct dp_pdev *pdev = vdev->pdev;
  712. struct dp_soc *soc = pdev->soc;
  713. if (dp_tx_pdev_pflow_control(vdev))
  714. return NULL;
  715. /* Allocate software Tx descriptor */
  716. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  717. if (!tx_desc) {
  718. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  719. return NULL;
  720. }
  721. /* Flow control/Congestion Control counters */
  722. qdf_atomic_inc(&pdev->num_tx_outstanding);
  723. /* Initialize the SW tx descriptor */
  724. tx_desc->nbuf = nbuf;
  725. tx_desc->frm_type = msdu_info->frm_type;
  726. tx_desc->tx_encap_type = vdev->tx_encap_type;
  727. tx_desc->vdev = vdev;
  728. tx_desc->pdev = pdev;
  729. tx_desc->pkt_offset = 0;
  730. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  731. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  732. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  733. /* Handle scattered frames - TSO/SG/ME */
  734. /* Allocate and prepare an extension descriptor for scattered frames */
  735. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  736. if (!msdu_ext_desc) {
  737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  738. "%s Tx Extension Descriptor Alloc Fail",
  739. __func__);
  740. goto failure;
  741. }
  742. #if TQM_BYPASS_WAR
  743. /* Temporary WAR due to TQM VP issues */
  744. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  745. qdf_atomic_inc(&pdev->num_tx_exception);
  746. #endif
  747. if (qdf_unlikely(msdu_info->exception_fw))
  748. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  749. tx_desc->msdu_ext_desc = msdu_ext_desc;
  750. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  751. return tx_desc;
  752. failure:
  753. dp_tx_desc_release(tx_desc, desc_pool_id);
  754. return NULL;
  755. }
  756. /**
  757. * dp_tx_prepare_raw() - Prepare RAW packet TX
  758. * @vdev: DP vdev handle
  759. * @nbuf: buffer pointer
  760. * @seg_info: Pointer to Segment info Descriptor to be prepared
  761. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  762. * descriptor
  763. *
  764. * Return:
  765. */
  766. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  767. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  768. {
  769. qdf_nbuf_t curr_nbuf = NULL;
  770. uint16_t total_len = 0;
  771. qdf_dma_addr_t paddr;
  772. int32_t i;
  773. int32_t mapped_buf_num = 0;
  774. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  775. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  776. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  777. /* Continue only if frames are of DATA type */
  778. if (!DP_FRAME_IS_DATA(qos_wh)) {
  779. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  780. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  781. "Pkt. recd is of not data type");
  782. goto error;
  783. }
  784. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  785. if (vdev->raw_mode_war &&
  786. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  787. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  788. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  789. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  790. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  791. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  792. QDF_DMA_TO_DEVICE)) {
  793. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  794. "%s dma map error ", __func__);
  795. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  796. mapped_buf_num = i;
  797. goto error;
  798. }
  799. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  800. seg_info->frags[i].paddr_lo = paddr;
  801. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  802. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  803. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  804. total_len += qdf_nbuf_len(curr_nbuf);
  805. }
  806. seg_info->frag_cnt = i;
  807. seg_info->total_len = total_len;
  808. seg_info->next = NULL;
  809. sg_info->curr_seg = seg_info;
  810. msdu_info->frm_type = dp_tx_frm_raw;
  811. msdu_info->num_seg = 1;
  812. return nbuf;
  813. error:
  814. i = 0;
  815. while (nbuf) {
  816. curr_nbuf = nbuf;
  817. if (i < mapped_buf_num) {
  818. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  819. i++;
  820. }
  821. nbuf = qdf_nbuf_next(nbuf);
  822. qdf_nbuf_free(curr_nbuf);
  823. }
  824. return NULL;
  825. }
  826. /**
  827. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  828. * @soc: DP soc handle
  829. * @nbuf: Buffer pointer
  830. *
  831. * unmap the chain of nbufs that belong to this RAW frame.
  832. *
  833. * Return: None
  834. */
  835. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  836. qdf_nbuf_t nbuf)
  837. {
  838. qdf_nbuf_t cur_nbuf = nbuf;
  839. do {
  840. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  841. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  842. } while (cur_nbuf);
  843. }
  844. /**
  845. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  846. * @soc: DP Soc Handle
  847. * @vdev: DP vdev handle
  848. * @tx_desc: Tx Descriptor Handle
  849. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  850. * @fw_metadata: Metadata to send to Target Firmware along with frame
  851. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  852. * @tx_exc_metadata: Handle that holds exception path meta data
  853. *
  854. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  855. * from software Tx descriptor
  856. *
  857. * Return:
  858. */
  859. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  860. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  861. uint16_t fw_metadata, uint8_t ring_id,
  862. struct cdp_tx_exception_metadata
  863. *tx_exc_metadata)
  864. {
  865. uint8_t type;
  866. uint16_t length;
  867. void *hal_tx_desc, *hal_tx_desc_cached;
  868. qdf_dma_addr_t dma_addr;
  869. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  870. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  871. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  872. tx_exc_metadata->sec_type : vdev->sec_type);
  873. /* Return Buffer Manager ID */
  874. uint8_t bm_id = ring_id;
  875. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  876. hal_tx_desc_cached = (void *) cached_desc;
  877. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  878. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  879. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  880. type = HAL_TX_BUF_TYPE_EXT_DESC;
  881. dma_addr = tx_desc->msdu_ext_desc->paddr;
  882. } else {
  883. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  884. type = HAL_TX_BUF_TYPE_BUFFER;
  885. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  886. }
  887. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  888. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  889. dma_addr, bm_id, tx_desc->id,
  890. type, soc->hal_soc);
  891. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  892. return QDF_STATUS_E_RESOURCES;
  893. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  894. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  895. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  896. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  897. vdev->pdev->lmac_id);
  898. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  899. vdev->search_type);
  900. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  901. vdev->bss_ast_hash);
  902. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  903. vdev->dscp_tid_map_id);
  904. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  905. sec_type_map[sec_type]);
  906. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  907. length, type, (uint64_t)dma_addr,
  908. tx_desc->pkt_offset, tx_desc->id);
  909. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  910. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  911. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  912. vdev->hal_desc_addr_search_flags);
  913. /* verify checksum offload configuration*/
  914. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  915. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  916. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  917. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  918. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  919. }
  920. if (tid != HTT_TX_EXT_TID_INVALID)
  921. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  922. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  923. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  924. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  925. /* Sync cached descriptor with HW */
  926. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  927. if (!hal_tx_desc) {
  928. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  929. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  930. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  931. return QDF_STATUS_E_RESOURCES;
  932. }
  933. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  934. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  935. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  936. return QDF_STATUS_SUCCESS;
  937. }
  938. /**
  939. * dp_cce_classify() - Classify the frame based on CCE rules
  940. * @vdev: DP vdev handle
  941. * @nbuf: skb
  942. *
  943. * Classify frames based on CCE rules
  944. * Return: bool( true if classified,
  945. * else false)
  946. */
  947. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  948. {
  949. qdf_ether_header_t *eh = NULL;
  950. uint16_t ether_type;
  951. qdf_llc_t *llcHdr;
  952. qdf_nbuf_t nbuf_clone = NULL;
  953. qdf_dot3_qosframe_t *qos_wh = NULL;
  954. /* for mesh packets don't do any classification */
  955. if (qdf_unlikely(vdev->mesh_vdev))
  956. return false;
  957. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  958. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  959. ether_type = eh->ether_type;
  960. llcHdr = (qdf_llc_t *)(nbuf->data +
  961. sizeof(qdf_ether_header_t));
  962. } else {
  963. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  964. /* For encrypted packets don't do any classification */
  965. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  966. return false;
  967. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  968. if (qdf_unlikely(
  969. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  970. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  971. ether_type = *(uint16_t *)(nbuf->data
  972. + QDF_IEEE80211_4ADDR_HDR_LEN
  973. + sizeof(qdf_llc_t)
  974. - sizeof(ether_type));
  975. llcHdr = (qdf_llc_t *)(nbuf->data +
  976. QDF_IEEE80211_4ADDR_HDR_LEN);
  977. } else {
  978. ether_type = *(uint16_t *)(nbuf->data
  979. + QDF_IEEE80211_3ADDR_HDR_LEN
  980. + sizeof(qdf_llc_t)
  981. - sizeof(ether_type));
  982. llcHdr = (qdf_llc_t *)(nbuf->data +
  983. QDF_IEEE80211_3ADDR_HDR_LEN);
  984. }
  985. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  986. && (ether_type ==
  987. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  988. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  989. return true;
  990. }
  991. }
  992. return false;
  993. }
  994. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  995. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  996. sizeof(*llcHdr));
  997. nbuf_clone = qdf_nbuf_clone(nbuf);
  998. if (qdf_unlikely(nbuf_clone)) {
  999. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1000. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1001. qdf_nbuf_pull_head(nbuf_clone,
  1002. sizeof(qdf_net_vlanhdr_t));
  1003. }
  1004. }
  1005. } else {
  1006. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1007. nbuf_clone = qdf_nbuf_clone(nbuf);
  1008. if (qdf_unlikely(nbuf_clone)) {
  1009. qdf_nbuf_pull_head(nbuf_clone,
  1010. sizeof(qdf_net_vlanhdr_t));
  1011. }
  1012. }
  1013. }
  1014. if (qdf_unlikely(nbuf_clone))
  1015. nbuf = nbuf_clone;
  1016. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1017. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1018. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1019. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1020. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1021. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1022. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1023. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1024. if (qdf_unlikely(nbuf_clone))
  1025. qdf_nbuf_free(nbuf_clone);
  1026. return true;
  1027. }
  1028. if (qdf_unlikely(nbuf_clone))
  1029. qdf_nbuf_free(nbuf_clone);
  1030. return false;
  1031. }
  1032. /**
  1033. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1034. * @vdev: DP vdev handle
  1035. * @nbuf: skb
  1036. *
  1037. * Extract the DSCP or PCP information from frame and map into TID value.
  1038. *
  1039. * Return: void
  1040. */
  1041. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1042. struct dp_tx_msdu_info_s *msdu_info)
  1043. {
  1044. uint8_t tos = 0, dscp_tid_override = 0;
  1045. uint8_t *hdr_ptr, *L3datap;
  1046. uint8_t is_mcast = 0;
  1047. qdf_ether_header_t *eh = NULL;
  1048. qdf_ethervlan_header_t *evh = NULL;
  1049. uint16_t ether_type;
  1050. qdf_llc_t *llcHdr;
  1051. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1052. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1053. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1054. eh = (qdf_ether_header_t *)nbuf->data;
  1055. hdr_ptr = eh->ether_dhost;
  1056. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1057. } else {
  1058. qdf_dot3_qosframe_t *qos_wh =
  1059. (qdf_dot3_qosframe_t *) nbuf->data;
  1060. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1061. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1062. return;
  1063. }
  1064. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1065. ether_type = eh->ether_type;
  1066. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1067. /*
  1068. * Check if packet is dot3 or eth2 type.
  1069. */
  1070. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1071. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1072. sizeof(*llcHdr));
  1073. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1074. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1075. sizeof(*llcHdr);
  1076. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1077. + sizeof(*llcHdr) +
  1078. sizeof(qdf_net_vlanhdr_t));
  1079. } else {
  1080. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1081. sizeof(*llcHdr);
  1082. }
  1083. } else {
  1084. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1085. evh = (qdf_ethervlan_header_t *) eh;
  1086. ether_type = evh->ether_type;
  1087. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1088. }
  1089. }
  1090. /*
  1091. * Find priority from IP TOS DSCP field
  1092. */
  1093. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1094. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1095. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1096. /* Only for unicast frames */
  1097. if (!is_mcast) {
  1098. /* send it on VO queue */
  1099. msdu_info->tid = DP_VO_TID;
  1100. }
  1101. } else {
  1102. /*
  1103. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1104. * from TOS byte.
  1105. */
  1106. tos = ip->ip_tos;
  1107. dscp_tid_override = 1;
  1108. }
  1109. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1110. /* TODO
  1111. * use flowlabel
  1112. *igmpmld cases to be handled in phase 2
  1113. */
  1114. unsigned long ver_pri_flowlabel;
  1115. unsigned long pri;
  1116. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1117. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1118. DP_IPV6_PRIORITY_SHIFT;
  1119. tos = pri;
  1120. dscp_tid_override = 1;
  1121. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1122. msdu_info->tid = DP_VO_TID;
  1123. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1124. /* Only for unicast frames */
  1125. if (!is_mcast) {
  1126. /* send ucast arp on VO queue */
  1127. msdu_info->tid = DP_VO_TID;
  1128. }
  1129. }
  1130. /*
  1131. * Assign all MCAST packets to BE
  1132. */
  1133. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1134. if (is_mcast) {
  1135. tos = 0;
  1136. dscp_tid_override = 1;
  1137. }
  1138. }
  1139. if (dscp_tid_override == 1) {
  1140. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1141. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1142. }
  1143. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1144. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1145. return;
  1146. }
  1147. /**
  1148. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1149. * @vdev: DP vdev handle
  1150. * @nbuf: skb
  1151. *
  1152. * Software based TID classification is required when more than 2 DSCP-TID
  1153. * mapping tables are needed.
  1154. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1155. *
  1156. * Return: void
  1157. */
  1158. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1159. struct dp_tx_msdu_info_s *msdu_info)
  1160. {
  1161. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1162. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1163. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1164. return;
  1165. /* for mesh packets don't do any classification */
  1166. if (qdf_unlikely(vdev->mesh_vdev))
  1167. return;
  1168. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1169. }
  1170. #ifdef FEATURE_WLAN_TDLS
  1171. /**
  1172. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1173. * @tx_desc: TX descriptor
  1174. *
  1175. * Return: None
  1176. */
  1177. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1178. {
  1179. if (tx_desc->vdev) {
  1180. if (tx_desc->vdev->is_tdls_frame) {
  1181. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1182. tx_desc->vdev->is_tdls_frame = false;
  1183. }
  1184. }
  1185. }
  1186. /**
  1187. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1188. * @tx_desc: TX descriptor
  1189. * @vdev: datapath vdev handle
  1190. *
  1191. * Return: None
  1192. */
  1193. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1194. struct dp_vdev *vdev)
  1195. {
  1196. struct hal_tx_completion_status ts = {0};
  1197. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1198. if (qdf_unlikely(!vdev)) {
  1199. dp_err("vdev is null!");
  1200. return;
  1201. }
  1202. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1203. if (vdev->tx_non_std_data_callback.func) {
  1204. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1205. vdev->tx_non_std_data_callback.func(
  1206. vdev->tx_non_std_data_callback.ctxt,
  1207. nbuf, ts.status);
  1208. return;
  1209. }
  1210. }
  1211. #else
  1212. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1213. {
  1214. }
  1215. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1216. struct dp_vdev *vdev)
  1217. {
  1218. }
  1219. #endif
  1220. /**
  1221. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1222. * @vdev: DP vdev handle
  1223. * @nbuf: skb
  1224. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1225. * @meta_data: Metadata to the fw
  1226. * @tx_q: Tx queue to be used for this Tx frame
  1227. * @peer_id: peer_id of the peer in case of NAWDS frames
  1228. * @tx_exc_metadata: Handle that holds exception path metadata
  1229. *
  1230. * Return: NULL on success,
  1231. * nbuf when it fails to send
  1232. */
  1233. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1234. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1235. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1236. {
  1237. struct dp_pdev *pdev = vdev->pdev;
  1238. struct dp_soc *soc = pdev->soc;
  1239. struct dp_tx_desc_s *tx_desc;
  1240. QDF_STATUS status;
  1241. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1242. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1243. uint16_t htt_tcl_metadata = 0;
  1244. uint8_t tid = msdu_info->tid;
  1245. struct cdp_tid_tx_stats *tid_stats = NULL;
  1246. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1247. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1248. msdu_info, tx_exc_metadata);
  1249. if (!tx_desc) {
  1250. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1251. vdev, tx_q->desc_pool_id);
  1252. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1253. tid_stats = &pdev->stats.tid_stats.
  1254. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1255. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1256. return nbuf;
  1257. }
  1258. if (qdf_unlikely(soc->cce_disable)) {
  1259. if (dp_cce_classify(vdev, nbuf) == true) {
  1260. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1261. tid = DP_VO_TID;
  1262. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1263. }
  1264. }
  1265. dp_tx_update_tdls_flags(tx_desc);
  1266. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1267. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1268. "%s %d : HAL RING Access Failed -- %pK",
  1269. __func__, __LINE__, hal_srng);
  1270. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1271. tid_stats = &pdev->stats.tid_stats.
  1272. tid_tx_stats[tx_q->ring_id][tid];
  1273. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1274. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1275. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1276. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1277. goto fail_return;
  1278. }
  1279. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1280. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1281. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1282. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1283. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1284. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1285. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1286. peer_id);
  1287. } else
  1288. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1289. if (msdu_info->exception_fw) {
  1290. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1291. }
  1292. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1293. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1294. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1295. if (status != QDF_STATUS_SUCCESS) {
  1296. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1297. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1298. __func__, tx_desc, tx_q->ring_id);
  1299. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1300. tid_stats = &pdev->stats.tid_stats.
  1301. tid_tx_stats[tx_q->ring_id][tid];
  1302. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1303. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1304. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1305. goto fail_return;
  1306. }
  1307. nbuf = NULL;
  1308. fail_return:
  1309. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1310. hal_srng_access_end(soc->hal_soc, hal_srng);
  1311. hif_pm_runtime_put(soc->hif_handle);
  1312. } else {
  1313. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1314. }
  1315. return nbuf;
  1316. }
  1317. /**
  1318. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1319. * @vdev: DP vdev handle
  1320. * @nbuf: skb
  1321. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1322. *
  1323. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1324. *
  1325. * Return: NULL on success,
  1326. * nbuf when it fails to send
  1327. */
  1328. #if QDF_LOCK_STATS
  1329. noinline
  1330. #else
  1331. #endif
  1332. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1333. struct dp_tx_msdu_info_s *msdu_info)
  1334. {
  1335. uint8_t i;
  1336. struct dp_pdev *pdev = vdev->pdev;
  1337. struct dp_soc *soc = pdev->soc;
  1338. struct dp_tx_desc_s *tx_desc;
  1339. bool is_cce_classified = false;
  1340. QDF_STATUS status;
  1341. uint16_t htt_tcl_metadata = 0;
  1342. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1343. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1344. struct cdp_tid_tx_stats *tid_stats = NULL;
  1345. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1346. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1347. "%s %d : HAL RING Access Failed -- %pK",
  1348. __func__, __LINE__, hal_srng);
  1349. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1350. tid_stats = &pdev->stats.tid_stats.
  1351. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1352. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1353. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1354. return nbuf;
  1355. }
  1356. if (qdf_unlikely(soc->cce_disable)) {
  1357. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1358. if (is_cce_classified) {
  1359. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1360. msdu_info->tid = DP_VO_TID;
  1361. }
  1362. }
  1363. if (msdu_info->frm_type == dp_tx_frm_me)
  1364. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1365. i = 0;
  1366. /* Print statement to track i and num_seg */
  1367. /*
  1368. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1369. * descriptors using information in msdu_info
  1370. */
  1371. while (i < msdu_info->num_seg) {
  1372. /*
  1373. * Setup Tx descriptor for an MSDU, and MSDU extension
  1374. * descriptor
  1375. */
  1376. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1377. tx_q->desc_pool_id);
  1378. if (!tx_desc) {
  1379. if (msdu_info->frm_type == dp_tx_frm_me) {
  1380. dp_tx_me_free_buf(pdev,
  1381. (void *)(msdu_info->u.sg_info
  1382. .curr_seg->frags[0].vaddr));
  1383. }
  1384. goto done;
  1385. }
  1386. if (msdu_info->frm_type == dp_tx_frm_me) {
  1387. tx_desc->me_buffer =
  1388. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1389. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1390. }
  1391. if (is_cce_classified)
  1392. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1393. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1394. if (msdu_info->exception_fw) {
  1395. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1396. }
  1397. /*
  1398. * Enqueue the Tx MSDU descriptor to HW for transmit
  1399. */
  1400. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1401. htt_tcl_metadata, tx_q->ring_id, NULL);
  1402. if (status != QDF_STATUS_SUCCESS) {
  1403. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1404. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1405. __func__, tx_desc, tx_q->ring_id);
  1406. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1407. tid_stats = &pdev->stats.tid_stats.
  1408. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1409. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1410. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1411. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1412. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1413. goto done;
  1414. }
  1415. /*
  1416. * TODO
  1417. * if tso_info structure can be modified to have curr_seg
  1418. * as first element, following 2 blocks of code (for TSO and SG)
  1419. * can be combined into 1
  1420. */
  1421. /*
  1422. * For frames with multiple segments (TSO, ME), jump to next
  1423. * segment.
  1424. */
  1425. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1426. if (msdu_info->u.tso_info.curr_seg->next) {
  1427. msdu_info->u.tso_info.curr_seg =
  1428. msdu_info->u.tso_info.curr_seg->next;
  1429. /*
  1430. * If this is a jumbo nbuf, then increment the number of
  1431. * nbuf users for each additional segment of the msdu.
  1432. * This will ensure that the skb is freed only after
  1433. * receiving tx completion for all segments of an nbuf
  1434. */
  1435. qdf_nbuf_inc_users(nbuf);
  1436. /* Check with MCL if this is needed */
  1437. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1438. }
  1439. }
  1440. /*
  1441. * For Multicast-Unicast converted packets,
  1442. * each converted frame (for a client) is represented as
  1443. * 1 segment
  1444. */
  1445. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1446. (msdu_info->frm_type == dp_tx_frm_me)) {
  1447. if (msdu_info->u.sg_info.curr_seg->next) {
  1448. msdu_info->u.sg_info.curr_seg =
  1449. msdu_info->u.sg_info.curr_seg->next;
  1450. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1451. }
  1452. }
  1453. i++;
  1454. }
  1455. nbuf = NULL;
  1456. done:
  1457. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1458. hal_srng_access_end(soc->hal_soc, hal_srng);
  1459. hif_pm_runtime_put(soc->hif_handle);
  1460. } else {
  1461. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1462. }
  1463. return nbuf;
  1464. }
  1465. /**
  1466. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1467. * for SG frames
  1468. * @vdev: DP vdev handle
  1469. * @nbuf: skb
  1470. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1471. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1472. *
  1473. * Return: NULL on success,
  1474. * nbuf when it fails to send
  1475. */
  1476. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1477. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1478. {
  1479. uint32_t cur_frag, nr_frags;
  1480. qdf_dma_addr_t paddr;
  1481. struct dp_tx_sg_info_s *sg_info;
  1482. sg_info = &msdu_info->u.sg_info;
  1483. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1484. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1485. QDF_DMA_TO_DEVICE)) {
  1486. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1487. "dma map error");
  1488. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1489. qdf_nbuf_free(nbuf);
  1490. return NULL;
  1491. }
  1492. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1493. seg_info->frags[0].paddr_lo = paddr;
  1494. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1495. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1496. seg_info->frags[0].vaddr = (void *) nbuf;
  1497. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1498. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1499. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1500. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1501. "frag dma map error");
  1502. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1503. qdf_nbuf_free(nbuf);
  1504. return NULL;
  1505. }
  1506. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1507. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1508. seg_info->frags[cur_frag + 1].paddr_hi =
  1509. ((uint64_t) paddr) >> 32;
  1510. seg_info->frags[cur_frag + 1].len =
  1511. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1512. }
  1513. seg_info->frag_cnt = (cur_frag + 1);
  1514. seg_info->total_len = qdf_nbuf_len(nbuf);
  1515. seg_info->next = NULL;
  1516. sg_info->curr_seg = seg_info;
  1517. msdu_info->frm_type = dp_tx_frm_sg;
  1518. msdu_info->num_seg = 1;
  1519. return nbuf;
  1520. }
  1521. /**
  1522. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1523. * @vdev: DP vdev handle
  1524. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1525. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1526. *
  1527. * Return: NULL on failure,
  1528. * nbuf when extracted successfully
  1529. */
  1530. static
  1531. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1532. struct dp_tx_msdu_info_s *msdu_info,
  1533. uint16_t ppdu_cookie)
  1534. {
  1535. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1536. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1537. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1538. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1539. (msdu_info->meta_data[5], 1);
  1540. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1541. (msdu_info->meta_data[5], 1);
  1542. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1543. (msdu_info->meta_data[6], ppdu_cookie);
  1544. msdu_info->exception_fw = 1;
  1545. msdu_info->is_tx_sniffer = 1;
  1546. }
  1547. #ifdef MESH_MODE_SUPPORT
  1548. /**
  1549. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1550. and prepare msdu_info for mesh frames.
  1551. * @vdev: DP vdev handle
  1552. * @nbuf: skb
  1553. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1554. *
  1555. * Return: NULL on failure,
  1556. * nbuf when extracted successfully
  1557. */
  1558. static
  1559. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1560. struct dp_tx_msdu_info_s *msdu_info)
  1561. {
  1562. struct meta_hdr_s *mhdr;
  1563. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1564. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1565. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1566. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1567. msdu_info->exception_fw = 0;
  1568. goto remove_meta_hdr;
  1569. }
  1570. msdu_info->exception_fw = 1;
  1571. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1572. meta_data->host_tx_desc_pool = 1;
  1573. meta_data->update_peer_cache = 1;
  1574. meta_data->learning_frame = 1;
  1575. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1576. meta_data->power = mhdr->power;
  1577. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1578. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1579. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1580. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1581. meta_data->dyn_bw = 1;
  1582. meta_data->valid_pwr = 1;
  1583. meta_data->valid_mcs_mask = 1;
  1584. meta_data->valid_nss_mask = 1;
  1585. meta_data->valid_preamble_type = 1;
  1586. meta_data->valid_retries = 1;
  1587. meta_data->valid_bw_info = 1;
  1588. }
  1589. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1590. meta_data->encrypt_type = 0;
  1591. meta_data->valid_encrypt_type = 1;
  1592. meta_data->learning_frame = 0;
  1593. }
  1594. meta_data->valid_key_flags = 1;
  1595. meta_data->key_flags = (mhdr->keyix & 0x3);
  1596. remove_meta_hdr:
  1597. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1599. "qdf_nbuf_pull_head failed");
  1600. qdf_nbuf_free(nbuf);
  1601. return NULL;
  1602. }
  1603. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1604. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1605. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1606. " tid %d to_fw %d",
  1607. __func__, msdu_info->meta_data[0],
  1608. msdu_info->meta_data[1],
  1609. msdu_info->meta_data[2],
  1610. msdu_info->meta_data[3],
  1611. msdu_info->meta_data[4],
  1612. msdu_info->meta_data[5],
  1613. msdu_info->tid, msdu_info->exception_fw);
  1614. return nbuf;
  1615. }
  1616. #else
  1617. static
  1618. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1619. struct dp_tx_msdu_info_s *msdu_info)
  1620. {
  1621. return nbuf;
  1622. }
  1623. #endif
  1624. /**
  1625. * dp_check_exc_metadata() - Checks if parameters are valid
  1626. * @tx_exc - holds all exception path parameters
  1627. *
  1628. * Returns true when all the parameters are valid else false
  1629. *
  1630. */
  1631. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1632. {
  1633. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1634. HTT_INVALID_TID);
  1635. bool invalid_encap_type =
  1636. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1637. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1638. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1639. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1640. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1641. tx_exc->ppdu_cookie == 0);
  1642. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1643. invalid_cookie) {
  1644. return false;
  1645. }
  1646. return true;
  1647. }
  1648. /**
  1649. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1650. * @vap_dev: DP vdev handle
  1651. * @nbuf: skb
  1652. * @tx_exc_metadata: Handle that holds exception path meta data
  1653. *
  1654. * Entry point for Core Tx layer (DP_TX) invoked from
  1655. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1656. *
  1657. * Return: NULL on success,
  1658. * nbuf when it fails to send
  1659. */
  1660. qdf_nbuf_t
  1661. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1662. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1663. {
  1664. qdf_ether_header_t *eh = NULL;
  1665. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1666. struct dp_tx_msdu_info_s msdu_info;
  1667. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1668. if (!tx_exc_metadata)
  1669. goto fail;
  1670. msdu_info.tid = tx_exc_metadata->tid;
  1671. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1672. dp_verbose_debug("skb %pM", nbuf->data);
  1673. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1674. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1675. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1676. "Invalid parameters in exception path");
  1677. goto fail;
  1678. }
  1679. /* Basic sanity checks for unsupported packets */
  1680. /* MESH mode */
  1681. if (qdf_unlikely(vdev->mesh_vdev)) {
  1682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1683. "Mesh mode is not supported in exception path");
  1684. goto fail;
  1685. }
  1686. /* TSO or SG */
  1687. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1688. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1690. "TSO and SG are not supported in exception path");
  1691. goto fail;
  1692. }
  1693. /* RAW */
  1694. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1695. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1696. "Raw frame is not supported in exception path");
  1697. goto fail;
  1698. }
  1699. /* Mcast enhancement*/
  1700. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1701. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1702. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1704. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1705. }
  1706. }
  1707. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1708. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1709. qdf_nbuf_len(nbuf));
  1710. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1711. tx_exc_metadata->ppdu_cookie);
  1712. }
  1713. /*
  1714. * Get HW Queue to use for this frame.
  1715. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1716. * dedicated for data and 1 for command.
  1717. * "queue_id" maps to one hardware ring.
  1718. * With each ring, we also associate a unique Tx descriptor pool
  1719. * to minimize lock contention for these resources.
  1720. */
  1721. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1722. /* Single linear frame */
  1723. /*
  1724. * If nbuf is a simple linear frame, use send_single function to
  1725. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1726. * SRNG. There is no need to setup a MSDU extension descriptor.
  1727. */
  1728. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1729. tx_exc_metadata->peer_id, tx_exc_metadata);
  1730. return nbuf;
  1731. fail:
  1732. dp_verbose_debug("pkt send failed");
  1733. return nbuf;
  1734. }
  1735. /**
  1736. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1737. * @vap_dev: DP vdev handle
  1738. * @nbuf: skb
  1739. *
  1740. * Entry point for Core Tx layer (DP_TX) invoked from
  1741. * hard_start_xmit in OSIF/HDD
  1742. *
  1743. * Return: NULL on success,
  1744. * nbuf when it fails to send
  1745. */
  1746. #ifdef MESH_MODE_SUPPORT
  1747. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1748. {
  1749. struct meta_hdr_s *mhdr;
  1750. qdf_nbuf_t nbuf_mesh = NULL;
  1751. qdf_nbuf_t nbuf_clone = NULL;
  1752. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1753. uint8_t no_enc_frame = 0;
  1754. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1755. if (!nbuf_mesh) {
  1756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1757. "qdf_nbuf_unshare failed");
  1758. return nbuf;
  1759. }
  1760. nbuf = nbuf_mesh;
  1761. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1762. if ((vdev->sec_type != cdp_sec_type_none) &&
  1763. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1764. no_enc_frame = 1;
  1765. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1766. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1767. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1768. !no_enc_frame) {
  1769. nbuf_clone = qdf_nbuf_clone(nbuf);
  1770. if (!nbuf_clone) {
  1771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1772. "qdf_nbuf_clone failed");
  1773. return nbuf;
  1774. }
  1775. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1776. }
  1777. if (nbuf_clone) {
  1778. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1779. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1780. } else {
  1781. qdf_nbuf_free(nbuf_clone);
  1782. }
  1783. }
  1784. if (no_enc_frame)
  1785. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1786. else
  1787. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1788. nbuf = dp_tx_send(vap_dev, nbuf);
  1789. if ((!nbuf) && no_enc_frame) {
  1790. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1791. }
  1792. return nbuf;
  1793. }
  1794. #else
  1795. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1796. {
  1797. return dp_tx_send(vap_dev, nbuf);
  1798. }
  1799. #endif
  1800. /**
  1801. * dp_tx_send() - Transmit a frame on a given VAP
  1802. * @vap_dev: DP vdev handle
  1803. * @nbuf: skb
  1804. *
  1805. * Entry point for Core Tx layer (DP_TX) invoked from
  1806. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1807. * cases
  1808. *
  1809. * Return: NULL on success,
  1810. * nbuf when it fails to send
  1811. */
  1812. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1813. {
  1814. qdf_ether_header_t *eh = NULL;
  1815. struct dp_tx_msdu_info_s msdu_info;
  1816. struct dp_tx_seg_info_s seg_info;
  1817. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1818. uint16_t peer_id = HTT_INVALID_PEER;
  1819. qdf_nbuf_t nbuf_mesh = NULL;
  1820. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1821. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1822. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1823. dp_verbose_debug("skb %pM", nbuf->data);
  1824. /*
  1825. * Set Default Host TID value to invalid TID
  1826. * (TID override disabled)
  1827. */
  1828. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1829. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1830. if (qdf_unlikely(vdev->mesh_vdev)) {
  1831. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1832. &msdu_info);
  1833. if (!nbuf_mesh) {
  1834. dp_verbose_debug("Extracting mesh metadata failed");
  1835. return nbuf;
  1836. }
  1837. nbuf = nbuf_mesh;
  1838. }
  1839. /*
  1840. * Get HW Queue to use for this frame.
  1841. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1842. * dedicated for data and 1 for command.
  1843. * "queue_id" maps to one hardware ring.
  1844. * With each ring, we also associate a unique Tx descriptor pool
  1845. * to minimize lock contention for these resources.
  1846. */
  1847. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1848. /*
  1849. * TCL H/W supports 2 DSCP-TID mapping tables.
  1850. * Table 1 - Default DSCP-TID mapping table
  1851. * Table 2 - 1 DSCP-TID override table
  1852. *
  1853. * If we need a different DSCP-TID mapping for this vap,
  1854. * call tid_classify to extract DSCP/ToS from frame and
  1855. * map to a TID and store in msdu_info. This is later used
  1856. * to fill in TCL Input descriptor (per-packet TID override).
  1857. */
  1858. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1859. /*
  1860. * Classify the frame and call corresponding
  1861. * "prepare" function which extracts the segment (TSO)
  1862. * and fragmentation information (for TSO , SG, ME, or Raw)
  1863. * into MSDU_INFO structure which is later used to fill
  1864. * SW and HW descriptors.
  1865. */
  1866. if (qdf_nbuf_is_tso(nbuf)) {
  1867. dp_verbose_debug("TSO frame %pK", vdev);
  1868. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1869. qdf_nbuf_len(nbuf));
  1870. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1871. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1872. qdf_nbuf_len(nbuf));
  1873. return nbuf;
  1874. }
  1875. goto send_multiple;
  1876. }
  1877. /* SG */
  1878. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1879. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1880. if (!nbuf)
  1881. return NULL;
  1882. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1883. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1884. qdf_nbuf_len(nbuf));
  1885. goto send_multiple;
  1886. }
  1887. #ifdef ATH_SUPPORT_IQUE
  1888. /* Mcast to Ucast Conversion*/
  1889. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1890. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1891. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1892. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1893. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1894. DP_STATS_INC_PKT(vdev,
  1895. tx_i.mcast_en.mcast_pkt, 1,
  1896. qdf_nbuf_len(nbuf));
  1897. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1898. QDF_STATUS_SUCCESS) {
  1899. return NULL;
  1900. }
  1901. }
  1902. }
  1903. #endif
  1904. /* RAW */
  1905. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1906. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1907. if (!nbuf)
  1908. return NULL;
  1909. dp_verbose_debug("Raw frame %pK", vdev);
  1910. goto send_multiple;
  1911. }
  1912. /* Single linear frame */
  1913. /*
  1914. * If nbuf is a simple linear frame, use send_single function to
  1915. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1916. * SRNG. There is no need to setup a MSDU extension descriptor.
  1917. */
  1918. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1919. return nbuf;
  1920. send_multiple:
  1921. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1922. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1923. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1924. return nbuf;
  1925. }
  1926. /**
  1927. * dp_tx_reinject_handler() - Tx Reinject Handler
  1928. * @tx_desc: software descriptor head pointer
  1929. * @status : Tx completion status from HTT descriptor
  1930. *
  1931. * This function reinjects frames back to Target.
  1932. * Todo - Host queue needs to be added
  1933. *
  1934. * Return: none
  1935. */
  1936. static
  1937. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1938. {
  1939. struct dp_vdev *vdev;
  1940. struct dp_peer *peer = NULL;
  1941. uint32_t peer_id = HTT_INVALID_PEER;
  1942. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1943. qdf_nbuf_t nbuf_copy = NULL;
  1944. struct dp_tx_msdu_info_s msdu_info;
  1945. struct dp_peer *sa_peer = NULL;
  1946. struct dp_ast_entry *ast_entry = NULL;
  1947. struct dp_soc *soc = NULL;
  1948. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1949. #ifdef WDS_VENDOR_EXTENSION
  1950. int is_mcast = 0, is_ucast = 0;
  1951. int num_peers_3addr = 0;
  1952. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1953. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1954. #endif
  1955. vdev = tx_desc->vdev;
  1956. soc = vdev->pdev->soc;
  1957. qdf_assert(vdev);
  1958. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1959. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1961. "%s Tx reinject path", __func__);
  1962. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1963. qdf_nbuf_len(tx_desc->nbuf));
  1964. qdf_spin_lock_bh(&(soc->ast_lock));
  1965. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1966. (soc,
  1967. (uint8_t *)(eh->ether_shost),
  1968. vdev->pdev->pdev_id);
  1969. if (ast_entry)
  1970. sa_peer = ast_entry->peer;
  1971. qdf_spin_unlock_bh(&(soc->ast_lock));
  1972. #ifdef WDS_VENDOR_EXTENSION
  1973. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1974. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1975. } else {
  1976. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1977. }
  1978. is_ucast = !is_mcast;
  1979. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1980. if (peer->bss_peer)
  1981. continue;
  1982. /* Detect wds peers that use 3-addr framing for mcast.
  1983. * if there are any, the bss_peer is used to send the
  1984. * the mcast frame using 3-addr format. all wds enabled
  1985. * peers that use 4-addr framing for mcast frames will
  1986. * be duplicated and sent as 4-addr frames below.
  1987. */
  1988. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1989. num_peers_3addr = 1;
  1990. break;
  1991. }
  1992. }
  1993. #endif
  1994. if (qdf_unlikely(vdev->mesh_vdev)) {
  1995. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1996. } else {
  1997. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1998. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1999. #ifdef WDS_VENDOR_EXTENSION
  2000. /*
  2001. * . if 3-addr STA, then send on BSS Peer
  2002. * . if Peer WDS enabled and accept 4-addr mcast,
  2003. * send mcast on that peer only
  2004. * . if Peer WDS enabled and accept 4-addr ucast,
  2005. * send ucast on that peer only
  2006. */
  2007. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2008. (peer->wds_enabled &&
  2009. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2010. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2011. #else
  2012. ((peer->bss_peer &&
  2013. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2014. peer->nawds_enabled)) {
  2015. #endif
  2016. peer_id = DP_INVALID_PEER;
  2017. if (peer->nawds_enabled) {
  2018. peer_id = peer->peer_ids[0];
  2019. if (sa_peer == peer) {
  2020. QDF_TRACE(
  2021. QDF_MODULE_ID_DP,
  2022. QDF_TRACE_LEVEL_DEBUG,
  2023. " %s: multicast packet",
  2024. __func__);
  2025. DP_STATS_INC(peer,
  2026. tx.nawds_mcast_drop, 1);
  2027. continue;
  2028. }
  2029. }
  2030. nbuf_copy = qdf_nbuf_copy(nbuf);
  2031. if (!nbuf_copy) {
  2032. QDF_TRACE(QDF_MODULE_ID_DP,
  2033. QDF_TRACE_LEVEL_DEBUG,
  2034. FL("nbuf copy failed"));
  2035. break;
  2036. }
  2037. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2038. nbuf_copy,
  2039. &msdu_info,
  2040. peer_id,
  2041. NULL);
  2042. if (nbuf_copy) {
  2043. QDF_TRACE(QDF_MODULE_ID_DP,
  2044. QDF_TRACE_LEVEL_DEBUG,
  2045. FL("pkt send failed"));
  2046. qdf_nbuf_free(nbuf_copy);
  2047. } else {
  2048. if (peer_id != DP_INVALID_PEER)
  2049. DP_STATS_INC_PKT(peer,
  2050. tx.nawds_mcast,
  2051. 1, qdf_nbuf_len(nbuf));
  2052. }
  2053. }
  2054. }
  2055. }
  2056. if (vdev->nawds_enabled) {
  2057. peer_id = DP_INVALID_PEER;
  2058. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2059. 1, qdf_nbuf_len(nbuf));
  2060. nbuf = dp_tx_send_msdu_single(vdev,
  2061. nbuf,
  2062. &msdu_info,
  2063. peer_id, NULL);
  2064. if (nbuf) {
  2065. QDF_TRACE(QDF_MODULE_ID_DP,
  2066. QDF_TRACE_LEVEL_DEBUG,
  2067. FL("pkt send failed"));
  2068. qdf_nbuf_free(nbuf);
  2069. }
  2070. } else
  2071. qdf_nbuf_free(nbuf);
  2072. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2073. }
  2074. /**
  2075. * dp_tx_inspect_handler() - Tx Inspect Handler
  2076. * @tx_desc: software descriptor head pointer
  2077. * @status : Tx completion status from HTT descriptor
  2078. *
  2079. * Handles Tx frames sent back to Host for inspection
  2080. * (ProxyARP)
  2081. *
  2082. * Return: none
  2083. */
  2084. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2085. {
  2086. struct dp_soc *soc;
  2087. struct dp_pdev *pdev = tx_desc->pdev;
  2088. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2089. "%s Tx inspect path",
  2090. __func__);
  2091. qdf_assert(pdev);
  2092. soc = pdev->soc;
  2093. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2094. qdf_nbuf_len(tx_desc->nbuf));
  2095. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2096. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2097. }
  2098. #ifdef FEATURE_PERPKT_INFO
  2099. /**
  2100. * dp_get_completion_indication_for_stack() - send completion to stack
  2101. * @soc : dp_soc handle
  2102. * @pdev: dp_pdev handle
  2103. * @peer: dp peer handle
  2104. * @ts: transmit completion status structure
  2105. * @netbuf: Buffer pointer for free
  2106. *
  2107. * This function is used for indication whether buffer needs to be
  2108. * sent to stack for freeing or not
  2109. */
  2110. QDF_STATUS
  2111. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2112. struct dp_pdev *pdev,
  2113. struct dp_peer *peer,
  2114. struct hal_tx_completion_status *ts,
  2115. qdf_nbuf_t netbuf,
  2116. uint64_t time_latency)
  2117. {
  2118. struct tx_capture_hdr *ppdu_hdr;
  2119. uint16_t peer_id = ts->peer_id;
  2120. uint32_t ppdu_id = ts->ppdu_id;
  2121. uint8_t first_msdu = ts->first_msdu;
  2122. uint8_t last_msdu = ts->last_msdu;
  2123. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2124. !pdev->latency_capture_enable))
  2125. return QDF_STATUS_E_NOSUPPORT;
  2126. if (!peer) {
  2127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2128. FL("Peer Invalid"));
  2129. return QDF_STATUS_E_INVAL;
  2130. }
  2131. if (pdev->mcopy_mode) {
  2132. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2133. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2134. return QDF_STATUS_E_INVAL;
  2135. }
  2136. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2137. pdev->m_copy_id.tx_peer_id = peer_id;
  2138. }
  2139. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2140. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2141. FL("No headroom"));
  2142. return QDF_STATUS_E_NOMEM;
  2143. }
  2144. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2145. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2146. QDF_MAC_ADDR_SIZE);
  2147. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2148. QDF_MAC_ADDR_SIZE);
  2149. ppdu_hdr->ppdu_id = ppdu_id;
  2150. ppdu_hdr->peer_id = peer_id;
  2151. ppdu_hdr->first_msdu = first_msdu;
  2152. ppdu_hdr->last_msdu = last_msdu;
  2153. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2154. ppdu_hdr->tsf = ts->tsf;
  2155. ppdu_hdr->time_latency = time_latency;
  2156. }
  2157. return QDF_STATUS_SUCCESS;
  2158. }
  2159. /**
  2160. * dp_send_completion_to_stack() - send completion to stack
  2161. * @soc : dp_soc handle
  2162. * @pdev: dp_pdev handle
  2163. * @peer_id: peer_id of the peer for which completion came
  2164. * @ppdu_id: ppdu_id
  2165. * @netbuf: Buffer pointer for free
  2166. *
  2167. * This function is used to send completion to stack
  2168. * to free buffer
  2169. */
  2170. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2171. uint16_t peer_id, uint32_t ppdu_id,
  2172. qdf_nbuf_t netbuf)
  2173. {
  2174. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2175. netbuf, peer_id,
  2176. WDI_NO_VAL, pdev->pdev_id);
  2177. }
  2178. #else
  2179. static QDF_STATUS
  2180. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2181. struct dp_pdev *pdev,
  2182. struct dp_peer *peer,
  2183. struct hal_tx_completion_status *ts,
  2184. qdf_nbuf_t netbuf,
  2185. uint64_t time_latency)
  2186. {
  2187. return QDF_STATUS_E_NOSUPPORT;
  2188. }
  2189. static void
  2190. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2191. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2192. {
  2193. }
  2194. #endif
  2195. /**
  2196. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2197. * @soc: Soc handle
  2198. * @desc: software Tx descriptor to be processed
  2199. *
  2200. * Return: none
  2201. */
  2202. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2203. struct dp_tx_desc_s *desc)
  2204. {
  2205. struct dp_vdev *vdev = desc->vdev;
  2206. qdf_nbuf_t nbuf = desc->nbuf;
  2207. /* nbuf already freed in vdev detach path */
  2208. if (!nbuf)
  2209. return;
  2210. /* If it is TDLS mgmt, don't unmap or free the frame */
  2211. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2212. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2213. /* 0 : MSDU buffer, 1 : MLE */
  2214. if (desc->msdu_ext_desc) {
  2215. /* TSO free */
  2216. if (hal_tx_ext_desc_get_tso_enable(
  2217. desc->msdu_ext_desc->vaddr)) {
  2218. /* unmap eash TSO seg before free the nbuf */
  2219. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2220. desc->tso_num_desc);
  2221. qdf_nbuf_free(nbuf);
  2222. return;
  2223. }
  2224. }
  2225. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2226. if (qdf_unlikely(!vdev)) {
  2227. qdf_nbuf_free(nbuf);
  2228. return;
  2229. }
  2230. if (qdf_likely(!vdev->mesh_vdev))
  2231. qdf_nbuf_free(nbuf);
  2232. else {
  2233. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2234. qdf_nbuf_free(nbuf);
  2235. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2236. } else
  2237. vdev->osif_tx_free_ext((nbuf));
  2238. }
  2239. }
  2240. #ifdef MESH_MODE_SUPPORT
  2241. /**
  2242. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2243. * in mesh meta header
  2244. * @tx_desc: software descriptor head pointer
  2245. * @ts: pointer to tx completion stats
  2246. * Return: none
  2247. */
  2248. static
  2249. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2250. struct hal_tx_completion_status *ts)
  2251. {
  2252. struct meta_hdr_s *mhdr;
  2253. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2254. if (!tx_desc->msdu_ext_desc) {
  2255. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2257. "netbuf %pK offset %d",
  2258. netbuf, tx_desc->pkt_offset);
  2259. return;
  2260. }
  2261. }
  2262. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2263. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2264. "netbuf %pK offset %lu", netbuf,
  2265. sizeof(struct meta_hdr_s));
  2266. return;
  2267. }
  2268. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2269. mhdr->rssi = ts->ack_frame_rssi;
  2270. mhdr->channel = tx_desc->pdev->operating_channel;
  2271. }
  2272. #else
  2273. static
  2274. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2275. struct hal_tx_completion_status *ts)
  2276. {
  2277. }
  2278. #endif
  2279. /**
  2280. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2281. * to pass in correct fields
  2282. *
  2283. * @vdev: pdev handle
  2284. * @tx_desc: tx descriptor
  2285. * @tid: tid value
  2286. * @ring_id: TCL or WBM ring number for transmit path
  2287. * Return: none
  2288. */
  2289. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2290. struct dp_tx_desc_s *tx_desc,
  2291. uint8_t tid, uint8_t ring_id)
  2292. {
  2293. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2294. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2295. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2296. return;
  2297. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2298. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2299. timestamp_hw_enqueue = tx_desc->timestamp;
  2300. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2301. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2302. timestamp_hw_enqueue);
  2303. interframe_delay = (uint32_t)(timestamp_ingress -
  2304. vdev->prev_tx_enq_tstamp);
  2305. /*
  2306. * Delay in software enqueue
  2307. */
  2308. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2309. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2310. /*
  2311. * Delay between packet enqueued to HW and Tx completion
  2312. */
  2313. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2314. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2315. /*
  2316. * Update interframe delay stats calculated at hardstart receive point.
  2317. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2318. * interframe delay will not be calculate correctly for 1st frame.
  2319. * On the other side, this will help in avoiding extra per packet check
  2320. * of !vdev->prev_tx_enq_tstamp.
  2321. */
  2322. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2323. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2324. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2325. }
  2326. /**
  2327. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2328. * per wbm ring
  2329. *
  2330. * @tx_desc: software descriptor head pointer
  2331. * @ts: Tx completion status
  2332. * @peer: peer handle
  2333. * @ring_id: ring number
  2334. *
  2335. * Return: None
  2336. */
  2337. static inline void
  2338. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2339. struct hal_tx_completion_status *ts,
  2340. struct dp_peer *peer, uint8_t ring_id)
  2341. {
  2342. struct dp_pdev *pdev = peer->vdev->pdev;
  2343. struct dp_soc *soc = NULL;
  2344. uint8_t mcs, pkt_type;
  2345. uint8_t tid = ts->tid;
  2346. uint32_t length;
  2347. struct cdp_tid_tx_stats *tid_stats;
  2348. if (!pdev)
  2349. return;
  2350. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2351. tid = CDP_MAX_DATA_TIDS - 1;
  2352. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2353. soc = pdev->soc;
  2354. mcs = ts->mcs;
  2355. pkt_type = ts->pkt_type;
  2356. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2357. dp_err("Release source is not from TQM");
  2358. return;
  2359. }
  2360. length = qdf_nbuf_len(tx_desc->nbuf);
  2361. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2362. if (qdf_unlikely(pdev->delay_stats_flag))
  2363. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2364. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2365. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2366. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2367. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2368. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2369. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2370. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2371. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2372. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2373. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2374. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2375. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2376. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2377. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2378. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2379. tid_stats->comp_fail_cnt++;
  2380. return;
  2381. }
  2382. tid_stats->success_cnt++;
  2383. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2384. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2385. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2386. /*
  2387. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2388. * Return from here if HTT PPDU events are enabled.
  2389. */
  2390. if (!(soc->process_tx_status))
  2391. return;
  2392. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2393. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2394. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2395. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2396. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2397. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2398. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2399. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2400. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2401. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2402. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2403. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2404. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2405. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2406. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2407. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2408. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2409. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2410. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2411. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2412. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2413. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2414. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2415. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2416. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2417. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2418. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2419. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2420. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2421. &peer->stats, ts->peer_id,
  2422. UPDATE_PEER_STATS, pdev->pdev_id);
  2423. #endif
  2424. }
  2425. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2426. /**
  2427. * dp_tx_flow_pool_lock() - take flow pool lock
  2428. * @soc: core txrx main context
  2429. * @tx_desc: tx desc
  2430. *
  2431. * Return: None
  2432. */
  2433. static inline
  2434. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2435. struct dp_tx_desc_s *tx_desc)
  2436. {
  2437. struct dp_tx_desc_pool_s *pool;
  2438. uint8_t desc_pool_id;
  2439. desc_pool_id = tx_desc->pool_id;
  2440. pool = &soc->tx_desc[desc_pool_id];
  2441. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2442. }
  2443. /**
  2444. * dp_tx_flow_pool_unlock() - release flow pool lock
  2445. * @soc: core txrx main context
  2446. * @tx_desc: tx desc
  2447. *
  2448. * Return: None
  2449. */
  2450. static inline
  2451. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2452. struct dp_tx_desc_s *tx_desc)
  2453. {
  2454. struct dp_tx_desc_pool_s *pool;
  2455. uint8_t desc_pool_id;
  2456. desc_pool_id = tx_desc->pool_id;
  2457. pool = &soc->tx_desc[desc_pool_id];
  2458. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2459. }
  2460. #else
  2461. static inline
  2462. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2463. {
  2464. }
  2465. static inline
  2466. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2467. {
  2468. }
  2469. #endif
  2470. /**
  2471. * dp_tx_notify_completion() - Notify tx completion for this desc
  2472. * @soc: core txrx main context
  2473. * @tx_desc: tx desc
  2474. * @netbuf: buffer
  2475. *
  2476. * Return: none
  2477. */
  2478. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2479. struct dp_tx_desc_s *tx_desc,
  2480. qdf_nbuf_t netbuf)
  2481. {
  2482. void *osif_dev;
  2483. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2484. qdf_assert(tx_desc);
  2485. dp_tx_flow_pool_lock(soc, tx_desc);
  2486. if (!tx_desc->vdev ||
  2487. !tx_desc->vdev->osif_vdev) {
  2488. dp_tx_flow_pool_unlock(soc, tx_desc);
  2489. return;
  2490. }
  2491. osif_dev = tx_desc->vdev->osif_vdev;
  2492. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2493. dp_tx_flow_pool_unlock(soc, tx_desc);
  2494. if (tx_compl_cbk)
  2495. tx_compl_cbk(netbuf, osif_dev);
  2496. }
  2497. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2498. * @pdev: pdev handle
  2499. * @tid: tid value
  2500. * @txdesc_ts: timestamp from txdesc
  2501. * @ppdu_id: ppdu id
  2502. *
  2503. * Return: none
  2504. */
  2505. #ifdef FEATURE_PERPKT_INFO
  2506. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2507. struct dp_peer *peer,
  2508. uint8_t tid,
  2509. uint64_t txdesc_ts,
  2510. uint32_t ppdu_id)
  2511. {
  2512. uint64_t delta_ms;
  2513. struct cdp_tx_sojourn_stats *sojourn_stats;
  2514. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2515. return;
  2516. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2517. tid >= CDP_DATA_TID_MAX))
  2518. return;
  2519. if (qdf_unlikely(!pdev->sojourn_buf))
  2520. return;
  2521. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2522. qdf_nbuf_data(pdev->sojourn_buf);
  2523. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2524. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2525. txdesc_ts;
  2526. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2527. delta_ms);
  2528. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2529. sojourn_stats->num_msdus[tid] = 1;
  2530. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2531. peer->avg_sojourn_msdu[tid].internal;
  2532. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2533. pdev->sojourn_buf, HTT_INVALID_PEER,
  2534. WDI_NO_VAL, pdev->pdev_id);
  2535. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2536. sojourn_stats->num_msdus[tid] = 0;
  2537. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2538. }
  2539. #else
  2540. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2541. uint8_t tid,
  2542. uint64_t txdesc_ts,
  2543. uint32_t ppdu_id)
  2544. {
  2545. }
  2546. #endif
  2547. /**
  2548. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2549. * @soc: DP Soc handle
  2550. * @tx_desc: software Tx descriptor
  2551. * @ts : Tx completion status from HAL/HTT descriptor
  2552. *
  2553. * Return: none
  2554. */
  2555. static inline void
  2556. dp_tx_comp_process_desc(struct dp_soc *soc,
  2557. struct dp_tx_desc_s *desc,
  2558. struct hal_tx_completion_status *ts,
  2559. struct dp_peer *peer)
  2560. {
  2561. uint64_t time_latency = 0;
  2562. /*
  2563. * m_copy/tx_capture modes are not supported for
  2564. * scatter gather packets
  2565. */
  2566. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2567. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2568. desc->timestamp);
  2569. }
  2570. if (!(desc->msdu_ext_desc)) {
  2571. if (QDF_STATUS_SUCCESS ==
  2572. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2573. return;
  2574. }
  2575. if (QDF_STATUS_SUCCESS ==
  2576. dp_get_completion_indication_for_stack(soc,
  2577. desc->pdev,
  2578. peer, ts,
  2579. desc->nbuf,
  2580. time_latency)) {
  2581. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2582. QDF_DMA_TO_DEVICE);
  2583. dp_send_completion_to_stack(soc,
  2584. desc->pdev,
  2585. ts->peer_id,
  2586. ts->ppdu_id,
  2587. desc->nbuf);
  2588. return;
  2589. }
  2590. }
  2591. dp_tx_comp_free_buf(soc, desc);
  2592. }
  2593. /**
  2594. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2595. * @tx_desc: software descriptor head pointer
  2596. * @ts: Tx completion status
  2597. * @peer: peer handle
  2598. * @ring_id: ring number
  2599. *
  2600. * Return: none
  2601. */
  2602. static inline
  2603. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2604. struct hal_tx_completion_status *ts,
  2605. struct dp_peer *peer, uint8_t ring_id)
  2606. {
  2607. uint32_t length;
  2608. qdf_ether_header_t *eh;
  2609. struct dp_soc *soc = NULL;
  2610. struct dp_vdev *vdev = tx_desc->vdev;
  2611. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2612. if (!vdev || !nbuf) {
  2613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2614. "invalid tx descriptor. vdev or nbuf NULL");
  2615. goto out;
  2616. }
  2617. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2618. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2619. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2620. QDF_TRACE_DEFAULT_PDEV_ID,
  2621. qdf_nbuf_data_addr(nbuf),
  2622. sizeof(qdf_nbuf_data(nbuf)),
  2623. tx_desc->id,
  2624. ts->status));
  2625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2626. "-------------------- \n"
  2627. "Tx Completion Stats: \n"
  2628. "-------------------- \n"
  2629. "ack_frame_rssi = %d \n"
  2630. "first_msdu = %d \n"
  2631. "last_msdu = %d \n"
  2632. "msdu_part_of_amsdu = %d \n"
  2633. "rate_stats valid = %d \n"
  2634. "bw = %d \n"
  2635. "pkt_type = %d \n"
  2636. "stbc = %d \n"
  2637. "ldpc = %d \n"
  2638. "sgi = %d \n"
  2639. "mcs = %d \n"
  2640. "ofdma = %d \n"
  2641. "tones_in_ru = %d \n"
  2642. "tsf = %d \n"
  2643. "ppdu_id = %d \n"
  2644. "transmit_cnt = %d \n"
  2645. "tid = %d \n"
  2646. "peer_id = %d\n",
  2647. ts->ack_frame_rssi, ts->first_msdu,
  2648. ts->last_msdu, ts->msdu_part_of_amsdu,
  2649. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2650. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2651. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2652. ts->transmit_cnt, ts->tid, ts->peer_id);
  2653. soc = vdev->pdev->soc;
  2654. /* Update SoC level stats */
  2655. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2656. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2657. /* Update per-packet stats for mesh mode */
  2658. if (qdf_unlikely(vdev->mesh_vdev) &&
  2659. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2660. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2661. length = qdf_nbuf_len(nbuf);
  2662. /* Update peer level stats */
  2663. if (!peer) {
  2664. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2665. "peer is null or deletion in progress");
  2666. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2667. goto out;
  2668. }
  2669. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2670. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2671. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2672. if ((peer->vdev->tx_encap_type ==
  2673. htt_cmn_pkt_type_ethernet) &&
  2674. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2675. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2676. }
  2677. }
  2678. } else {
  2679. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2680. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2681. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2682. }
  2683. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2684. #ifdef QCA_SUPPORT_RDK_STATS
  2685. if (soc->wlanstats_enabled)
  2686. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2687. tx_desc->timestamp,
  2688. ts->ppdu_id);
  2689. #endif
  2690. out:
  2691. return;
  2692. }
  2693. /**
  2694. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2695. * @soc: core txrx main context
  2696. * @comp_head: software descriptor head pointer
  2697. * @ring_id: ring number
  2698. *
  2699. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2700. * and release the software descriptors after processing is complete
  2701. *
  2702. * Return: none
  2703. */
  2704. static void
  2705. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2706. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2707. {
  2708. struct dp_tx_desc_s *desc;
  2709. struct dp_tx_desc_s *next;
  2710. struct hal_tx_completion_status ts = {0};
  2711. struct dp_peer *peer;
  2712. qdf_nbuf_t netbuf;
  2713. desc = comp_head;
  2714. while (desc) {
  2715. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2716. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2717. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2718. netbuf = desc->nbuf;
  2719. /* check tx complete notification */
  2720. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2721. dp_tx_notify_completion(soc, desc, netbuf);
  2722. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2723. if (peer)
  2724. dp_peer_unref_del_find_by_id(peer);
  2725. next = desc->next;
  2726. dp_tx_desc_release(desc, desc->pool_id);
  2727. desc = next;
  2728. }
  2729. }
  2730. /**
  2731. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2732. * @tx_desc: software descriptor head pointer
  2733. * @status : Tx completion status from HTT descriptor
  2734. * @ring_id: ring number
  2735. *
  2736. * This function will process HTT Tx indication messages from Target
  2737. *
  2738. * Return: none
  2739. */
  2740. static
  2741. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2742. uint8_t ring_id)
  2743. {
  2744. uint8_t tx_status;
  2745. struct dp_pdev *pdev;
  2746. struct dp_vdev *vdev;
  2747. struct dp_soc *soc;
  2748. struct hal_tx_completion_status ts = {0};
  2749. uint32_t *htt_desc = (uint32_t *)status;
  2750. struct dp_peer *peer;
  2751. struct cdp_tid_tx_stats *tid_stats = NULL;
  2752. struct htt_soc *htt_handle;
  2753. qdf_assert(tx_desc->pdev);
  2754. pdev = tx_desc->pdev;
  2755. vdev = tx_desc->vdev;
  2756. soc = pdev->soc;
  2757. if (!vdev)
  2758. return;
  2759. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2760. htt_handle = (struct htt_soc *)soc->htt_handle;
  2761. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2762. switch (tx_status) {
  2763. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2764. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2765. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2766. {
  2767. uint8_t tid;
  2768. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2769. ts.peer_id =
  2770. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2771. htt_desc[2]);
  2772. ts.tid =
  2773. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2774. htt_desc[2]);
  2775. } else {
  2776. ts.peer_id = HTT_INVALID_PEER;
  2777. ts.tid = HTT_INVALID_TID;
  2778. }
  2779. ts.ppdu_id =
  2780. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2781. htt_desc[1]);
  2782. ts.ack_frame_rssi =
  2783. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2784. htt_desc[1]);
  2785. ts.first_msdu = 1;
  2786. ts.last_msdu = 1;
  2787. tid = ts.tid;
  2788. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2789. tid = CDP_MAX_DATA_TIDS - 1;
  2790. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2791. if (qdf_unlikely(pdev->delay_stats_flag))
  2792. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2793. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2794. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2795. tid_stats->comp_fail_cnt++;
  2796. } else {
  2797. tid_stats->success_cnt++;
  2798. }
  2799. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2800. if (qdf_likely(peer))
  2801. dp_peer_unref_del_find_by_id(peer);
  2802. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2803. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2804. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2805. break;
  2806. }
  2807. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2808. {
  2809. dp_tx_reinject_handler(tx_desc, status);
  2810. break;
  2811. }
  2812. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2813. {
  2814. dp_tx_inspect_handler(tx_desc, status);
  2815. break;
  2816. }
  2817. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2818. {
  2819. dp_tx_mec_handler(vdev, status);
  2820. break;
  2821. }
  2822. default:
  2823. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2824. "%s Invalid HTT tx_status %d\n",
  2825. __func__, tx_status);
  2826. break;
  2827. }
  2828. }
  2829. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2830. static inline
  2831. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2832. {
  2833. bool limit_hit = false;
  2834. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2835. limit_hit =
  2836. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2837. if (limit_hit)
  2838. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2839. return limit_hit;
  2840. }
  2841. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2842. {
  2843. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2844. }
  2845. #else
  2846. static inline
  2847. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2848. {
  2849. return false;
  2850. }
  2851. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2852. {
  2853. return false;
  2854. }
  2855. #endif
  2856. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2857. void *hal_srng, uint8_t ring_id, uint32_t quota)
  2858. {
  2859. void *tx_comp_hal_desc;
  2860. uint8_t buffer_src;
  2861. uint8_t pool_id;
  2862. uint32_t tx_desc_id;
  2863. struct dp_tx_desc_s *tx_desc = NULL;
  2864. struct dp_tx_desc_s *head_desc = NULL;
  2865. struct dp_tx_desc_s *tail_desc = NULL;
  2866. uint32_t num_processed = 0;
  2867. uint32_t count = 0;
  2868. bool force_break = false;
  2869. DP_HIST_INIT();
  2870. more_data:
  2871. /* Re-initialize local variables to be re-used */
  2872. head_desc = NULL;
  2873. tail_desc = NULL;
  2874. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_srng))) {
  2875. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2876. "%s %d : HAL RING Access Failed -- %pK",
  2877. __func__, __LINE__, hal_srng);
  2878. return 0;
  2879. }
  2880. /* Find head descriptor from completion ring */
  2881. while (qdf_likely(tx_comp_hal_desc =
  2882. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2883. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2884. /* If this buffer was not released by TQM or FW, then it is not
  2885. * Tx completion indication, assert */
  2886. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2887. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2888. QDF_TRACE(QDF_MODULE_ID_DP,
  2889. QDF_TRACE_LEVEL_FATAL,
  2890. "Tx comp release_src != TQM | FW but from %d",
  2891. buffer_src);
  2892. hal_dump_comp_desc(tx_comp_hal_desc);
  2893. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2894. qdf_assert_always(0);
  2895. }
  2896. /* Get descriptor id */
  2897. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2898. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2899. DP_TX_DESC_ID_POOL_OS;
  2900. /* Find Tx descriptor */
  2901. tx_desc = dp_tx_desc_find(soc, pool_id,
  2902. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2903. DP_TX_DESC_ID_PAGE_OS,
  2904. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2905. DP_TX_DESC_ID_OFFSET_OS);
  2906. /*
  2907. * If the descriptor is already freed in vdev_detach,
  2908. * continue to next descriptor
  2909. */
  2910. if (!tx_desc->vdev && !tx_desc->flags) {
  2911. QDF_TRACE(QDF_MODULE_ID_DP,
  2912. QDF_TRACE_LEVEL_INFO,
  2913. "Descriptor freed in vdev_detach %d",
  2914. tx_desc_id);
  2915. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2916. count++;
  2917. continue;
  2918. }
  2919. /*
  2920. * If the release source is FW, process the HTT status
  2921. */
  2922. if (qdf_unlikely(buffer_src ==
  2923. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2924. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2925. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2926. htt_tx_status);
  2927. dp_tx_process_htt_completion(tx_desc,
  2928. htt_tx_status, ring_id);
  2929. } else {
  2930. /* Pool id is not matching. Error */
  2931. if (tx_desc->pool_id != pool_id) {
  2932. QDF_TRACE(QDF_MODULE_ID_DP,
  2933. QDF_TRACE_LEVEL_FATAL,
  2934. "Tx Comp pool id %d not matched %d",
  2935. pool_id, tx_desc->pool_id);
  2936. qdf_assert_always(0);
  2937. }
  2938. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2939. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2940. QDF_TRACE(QDF_MODULE_ID_DP,
  2941. QDF_TRACE_LEVEL_FATAL,
  2942. "Txdesc invalid, flgs = %x,id = %d",
  2943. tx_desc->flags, tx_desc_id);
  2944. qdf_assert_always(0);
  2945. }
  2946. /* First ring descriptor on the cycle */
  2947. if (!head_desc) {
  2948. head_desc = tx_desc;
  2949. tail_desc = tx_desc;
  2950. }
  2951. tail_desc->next = tx_desc;
  2952. tx_desc->next = NULL;
  2953. tail_desc = tx_desc;
  2954. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2955. /* Collect hw completion contents */
  2956. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2957. &tx_desc->comp, 1);
  2958. }
  2959. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2960. /*
  2961. * Processed packet count is more than given quota
  2962. * stop to processing
  2963. */
  2964. if (num_processed >= quota) {
  2965. force_break = true;
  2966. break;
  2967. }
  2968. count++;
  2969. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2970. break;
  2971. }
  2972. dp_srng_access_end(int_ctx, soc, hal_srng);
  2973. /* Process the reaped descriptors */
  2974. if (head_desc)
  2975. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  2976. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2977. if (!force_break &&
  2978. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2979. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2980. if (!hif_exec_should_yield(soc->hif_handle,
  2981. int_ctx->dp_intr_id))
  2982. goto more_data;
  2983. }
  2984. }
  2985. DP_TX_HIST_STATS_PER_PDEV();
  2986. return num_processed;
  2987. }
  2988. #ifdef FEATURE_WLAN_TDLS
  2989. /**
  2990. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2991. *
  2992. * @data_vdev - which vdev should transmit the tx data frames
  2993. * @tx_spec - what non-standard handling to apply to the tx data frames
  2994. * @msdu_list - NULL-terminated list of tx MSDUs
  2995. *
  2996. * Return: NULL on success,
  2997. * nbuf when it fails to send
  2998. */
  2999. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3000. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3001. {
  3002. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3003. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3004. vdev->is_tdls_frame = true;
  3005. return dp_tx_send(vdev_handle, msdu_list);
  3006. }
  3007. #endif
  3008. /**
  3009. * dp_tx_vdev_attach() - attach vdev to dp tx
  3010. * @vdev: virtual device instance
  3011. *
  3012. * Return: QDF_STATUS_SUCCESS: success
  3013. * QDF_STATUS_E_RESOURCES: Error return
  3014. */
  3015. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3016. {
  3017. /*
  3018. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3019. */
  3020. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3021. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3022. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3023. vdev->vdev_id);
  3024. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3025. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3026. /*
  3027. * Set HTT Extension Valid bit to 0 by default
  3028. */
  3029. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3030. dp_tx_vdev_update_search_flags(vdev);
  3031. return QDF_STATUS_SUCCESS;
  3032. }
  3033. #ifndef FEATURE_WDS
  3034. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3035. {
  3036. return false;
  3037. }
  3038. #endif
  3039. /**
  3040. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3041. * @vdev: virtual device instance
  3042. *
  3043. * Return: void
  3044. *
  3045. */
  3046. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3047. {
  3048. struct dp_soc *soc = vdev->pdev->soc;
  3049. /*
  3050. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3051. * for TDLS link
  3052. *
  3053. * Enable AddrY (SA based search) only for non-WDS STA and
  3054. * ProxySTA VAP (in HKv1) modes.
  3055. *
  3056. * In all other VAP modes, only DA based search should be
  3057. * enabled
  3058. */
  3059. if (vdev->opmode == wlan_op_mode_sta &&
  3060. vdev->tdls_link_connected)
  3061. vdev->hal_desc_addr_search_flags =
  3062. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3063. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3064. !dp_tx_da_search_override(vdev))
  3065. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3066. else
  3067. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3068. /* Set search type only when peer map v2 messaging is enabled
  3069. * as we will have the search index (AST hash) only when v2 is
  3070. * enabled
  3071. */
  3072. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3073. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3074. else
  3075. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3076. }
  3077. static inline bool
  3078. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3079. struct dp_vdev *vdev,
  3080. struct dp_tx_desc_s *tx_desc)
  3081. {
  3082. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3083. return false;
  3084. /*
  3085. * if vdev is given, then only check whether desc
  3086. * vdev match. if vdev is NULL, then check whether
  3087. * desc pdev match.
  3088. */
  3089. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3090. }
  3091. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3092. /**
  3093. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3094. *
  3095. * @soc: Handle to DP SoC structure
  3096. * @tx_desc: pointer of one TX desc
  3097. * @desc_pool_id: TX Desc pool id
  3098. */
  3099. static inline void
  3100. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3101. uint8_t desc_pool_id)
  3102. {
  3103. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3104. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3105. tx_desc->vdev = NULL;
  3106. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3107. }
  3108. /**
  3109. * dp_tx_desc_flush() - release resources associated
  3110. * to TX Desc
  3111. *
  3112. * @dp_pdev: Handle to DP pdev structure
  3113. * @vdev: virtual device instance
  3114. * NULL: no specific Vdev is required and check all allcated TX desc
  3115. * on this pdev.
  3116. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3117. *
  3118. * @force_free:
  3119. * true: flush the TX desc.
  3120. * false: only reset the Vdev in each allocated TX desc
  3121. * that associated to current Vdev.
  3122. *
  3123. * This function will go through the TX desc pool to flush
  3124. * the outstanding TX data or reset Vdev to NULL in associated TX
  3125. * Desc.
  3126. */
  3127. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3128. struct dp_vdev *vdev,
  3129. bool force_free)
  3130. {
  3131. uint8_t i;
  3132. uint32_t j;
  3133. uint32_t num_desc, page_id, offset;
  3134. uint16_t num_desc_per_page;
  3135. struct dp_soc *soc = pdev->soc;
  3136. struct dp_tx_desc_s *tx_desc = NULL;
  3137. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3138. if (!vdev && !force_free) {
  3139. dp_err("Reset TX desc vdev, Vdev param is required!");
  3140. return;
  3141. }
  3142. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3143. tx_desc_pool = &soc->tx_desc[i];
  3144. if (!(tx_desc_pool->pool_size) ||
  3145. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3146. !(tx_desc_pool->desc_pages.cacheable_pages))
  3147. continue;
  3148. num_desc = tx_desc_pool->pool_size;
  3149. num_desc_per_page =
  3150. tx_desc_pool->desc_pages.num_element_per_page;
  3151. for (j = 0; j < num_desc; j++) {
  3152. page_id = j / num_desc_per_page;
  3153. offset = j % num_desc_per_page;
  3154. if (qdf_unlikely(!(tx_desc_pool->
  3155. desc_pages.cacheable_pages)))
  3156. break;
  3157. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3158. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3159. /*
  3160. * Free TX desc if force free is
  3161. * required, otherwise only reset vdev
  3162. * in this TX desc.
  3163. */
  3164. if (force_free) {
  3165. dp_tx_comp_free_buf(soc, tx_desc);
  3166. dp_tx_desc_release(tx_desc, i);
  3167. } else {
  3168. dp_tx_desc_reset_vdev(soc, tx_desc,
  3169. i);
  3170. }
  3171. }
  3172. }
  3173. }
  3174. }
  3175. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3176. static inline void
  3177. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3178. uint8_t desc_pool_id)
  3179. {
  3180. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3181. tx_desc->vdev = NULL;
  3182. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3183. }
  3184. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3185. struct dp_vdev *vdev,
  3186. bool force_free)
  3187. {
  3188. uint8_t i, num_pool;
  3189. uint32_t j;
  3190. uint32_t num_desc, page_id, offset;
  3191. uint16_t num_desc_per_page;
  3192. struct dp_soc *soc = pdev->soc;
  3193. struct dp_tx_desc_s *tx_desc = NULL;
  3194. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3195. if (!vdev && !force_free) {
  3196. dp_err("Reset TX desc vdev, Vdev param is required!");
  3197. return;
  3198. }
  3199. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3200. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3201. for (i = 0; i < num_pool; i++) {
  3202. tx_desc_pool = &soc->tx_desc[i];
  3203. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3204. continue;
  3205. num_desc_per_page =
  3206. tx_desc_pool->desc_pages.num_element_per_page;
  3207. for (j = 0; j < num_desc; j++) {
  3208. page_id = j / num_desc_per_page;
  3209. offset = j % num_desc_per_page;
  3210. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3211. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3212. if (force_free) {
  3213. dp_tx_comp_free_buf(soc, tx_desc);
  3214. dp_tx_desc_release(tx_desc, i);
  3215. } else {
  3216. dp_tx_desc_reset_vdev(soc, tx_desc,
  3217. i);
  3218. }
  3219. }
  3220. }
  3221. }
  3222. }
  3223. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3224. /**
  3225. * dp_tx_vdev_detach() - detach vdev from dp tx
  3226. * @vdev: virtual device instance
  3227. *
  3228. * Return: QDF_STATUS_SUCCESS: success
  3229. * QDF_STATUS_E_RESOURCES: Error return
  3230. */
  3231. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3232. {
  3233. struct dp_pdev *pdev = vdev->pdev;
  3234. /* Reset TX desc associated to this Vdev as NULL */
  3235. dp_tx_desc_flush(pdev, vdev, false);
  3236. return QDF_STATUS_SUCCESS;
  3237. }
  3238. /**
  3239. * dp_tx_pdev_attach() - attach pdev to dp tx
  3240. * @pdev: physical device instance
  3241. *
  3242. * Return: QDF_STATUS_SUCCESS: success
  3243. * QDF_STATUS_E_RESOURCES: Error return
  3244. */
  3245. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3246. {
  3247. struct dp_soc *soc = pdev->soc;
  3248. /* Initialize Flow control counters */
  3249. qdf_atomic_init(&pdev->num_tx_exception);
  3250. qdf_atomic_init(&pdev->num_tx_outstanding);
  3251. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3252. /* Initialize descriptors in TCL Ring */
  3253. hal_tx_init_data_ring(soc->hal_soc,
  3254. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3255. }
  3256. return QDF_STATUS_SUCCESS;
  3257. }
  3258. /**
  3259. * dp_tx_pdev_detach() - detach pdev from dp tx
  3260. * @pdev: physical device instance
  3261. *
  3262. * Return: QDF_STATUS_SUCCESS: success
  3263. * QDF_STATUS_E_RESOURCES: Error return
  3264. */
  3265. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3266. {
  3267. /* flush TX outstanding data per pdev */
  3268. dp_tx_desc_flush(pdev, NULL, true);
  3269. dp_tx_me_exit(pdev);
  3270. return QDF_STATUS_SUCCESS;
  3271. }
  3272. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3273. /* Pools will be allocated dynamically */
  3274. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3275. int num_desc)
  3276. {
  3277. uint8_t i;
  3278. for (i = 0; i < num_pool; i++) {
  3279. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3280. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3281. }
  3282. return 0;
  3283. }
  3284. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3285. {
  3286. uint8_t i;
  3287. for (i = 0; i < num_pool; i++)
  3288. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3289. }
  3290. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3291. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3292. int num_desc)
  3293. {
  3294. uint8_t i;
  3295. /* Allocate software Tx descriptor pools */
  3296. for (i = 0; i < num_pool; i++) {
  3297. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3298. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3299. "%s Tx Desc Pool alloc %d failed %pK",
  3300. __func__, i, soc);
  3301. return ENOMEM;
  3302. }
  3303. }
  3304. return 0;
  3305. }
  3306. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3307. {
  3308. uint8_t i;
  3309. for (i = 0; i < num_pool; i++) {
  3310. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3311. if (dp_tx_desc_pool_free(soc, i)) {
  3312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3313. "%s Tx Desc Pool Free failed", __func__);
  3314. }
  3315. }
  3316. }
  3317. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3318. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3319. /**
  3320. * dp_tso_attach_wifi3() - TSO attach handler
  3321. * @txrx_soc: Opaque Dp handle
  3322. *
  3323. * Reserve TSO descriptor buffers
  3324. *
  3325. * Return: QDF_STATUS_E_FAILURE on failure or
  3326. * QDF_STATUS_SUCCESS on success
  3327. */
  3328. static
  3329. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3330. {
  3331. return dp_tso_soc_attach(txrx_soc);
  3332. }
  3333. /**
  3334. * dp_tso_detach_wifi3() - TSO Detach handler
  3335. * @txrx_soc: Opaque Dp handle
  3336. *
  3337. * Deallocate TSO descriptor buffers
  3338. *
  3339. * Return: QDF_STATUS_E_FAILURE on failure or
  3340. * QDF_STATUS_SUCCESS on success
  3341. */
  3342. static
  3343. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3344. {
  3345. return dp_tso_soc_detach(txrx_soc);
  3346. }
  3347. #else
  3348. static
  3349. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3350. {
  3351. return QDF_STATUS_SUCCESS;
  3352. }
  3353. static
  3354. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3355. {
  3356. return QDF_STATUS_SUCCESS;
  3357. }
  3358. #endif
  3359. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3360. {
  3361. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3362. uint8_t i;
  3363. uint8_t num_pool;
  3364. uint32_t num_desc;
  3365. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3366. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3367. for (i = 0; i < num_pool; i++)
  3368. dp_tx_tso_desc_pool_free(soc, i);
  3369. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3370. __func__, num_pool, num_desc);
  3371. for (i = 0; i < num_pool; i++)
  3372. dp_tx_tso_num_seg_pool_free(soc, i);
  3373. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3374. __func__, num_pool, num_desc);
  3375. return QDF_STATUS_SUCCESS;
  3376. }
  3377. /**
  3378. * dp_tso_attach() - TSO attach handler
  3379. * @txrx_soc: Opaque Dp handle
  3380. *
  3381. * Reserve TSO descriptor buffers
  3382. *
  3383. * Return: QDF_STATUS_E_FAILURE on failure or
  3384. * QDF_STATUS_SUCCESS on success
  3385. */
  3386. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3387. {
  3388. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3389. uint8_t i;
  3390. uint8_t num_pool;
  3391. uint32_t num_desc;
  3392. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3393. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3394. for (i = 0; i < num_pool; i++) {
  3395. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3396. dp_err("TSO Desc Pool alloc %d failed %pK",
  3397. i, soc);
  3398. return QDF_STATUS_E_FAILURE;
  3399. }
  3400. }
  3401. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3402. __func__, num_pool, num_desc);
  3403. for (i = 0; i < num_pool; i++) {
  3404. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3405. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3406. i, soc);
  3407. return QDF_STATUS_E_FAILURE;
  3408. }
  3409. }
  3410. return QDF_STATUS_SUCCESS;
  3411. }
  3412. /**
  3413. * dp_tx_soc_detach() - detach soc from dp tx
  3414. * @soc: core txrx main context
  3415. *
  3416. * This function will detach dp tx into main device context
  3417. * will free dp tx resource and initialize resources
  3418. *
  3419. * Return: QDF_STATUS_SUCCESS: success
  3420. * QDF_STATUS_E_RESOURCES: Error return
  3421. */
  3422. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3423. {
  3424. uint8_t num_pool;
  3425. uint16_t num_desc;
  3426. uint16_t num_ext_desc;
  3427. uint8_t i;
  3428. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3429. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3430. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3431. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3432. dp_tx_flow_control_deinit(soc);
  3433. dp_tx_delete_static_pools(soc, num_pool);
  3434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3435. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3436. __func__, num_pool, num_desc);
  3437. for (i = 0; i < num_pool; i++) {
  3438. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3439. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3440. "%s Tx Ext Desc Pool Free failed",
  3441. __func__);
  3442. return QDF_STATUS_E_RESOURCES;
  3443. }
  3444. }
  3445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3446. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3447. __func__, num_pool, num_ext_desc);
  3448. status = dp_tso_detach_wifi3(soc);
  3449. if (status != QDF_STATUS_SUCCESS)
  3450. return status;
  3451. return QDF_STATUS_SUCCESS;
  3452. }
  3453. /**
  3454. * dp_tx_soc_attach() - attach soc to dp tx
  3455. * @soc: core txrx main context
  3456. *
  3457. * This function will attach dp tx into main device context
  3458. * will allocate dp tx resource and initialize resources
  3459. *
  3460. * Return: QDF_STATUS_SUCCESS: success
  3461. * QDF_STATUS_E_RESOURCES: Error return
  3462. */
  3463. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3464. {
  3465. uint8_t i;
  3466. uint8_t num_pool;
  3467. uint32_t num_desc;
  3468. uint32_t num_ext_desc;
  3469. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3470. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3471. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3472. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3473. if (num_pool > MAX_TXDESC_POOLS)
  3474. goto fail;
  3475. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3476. goto fail;
  3477. dp_tx_flow_control_init(soc);
  3478. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3479. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3480. __func__, num_pool, num_desc);
  3481. /* Allocate extension tx descriptor pools */
  3482. for (i = 0; i < num_pool; i++) {
  3483. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3485. "MSDU Ext Desc Pool alloc %d failed %pK",
  3486. i, soc);
  3487. goto fail;
  3488. }
  3489. }
  3490. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3491. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3492. __func__, num_pool, num_ext_desc);
  3493. status = dp_tso_attach_wifi3((void *)soc);
  3494. if (status != QDF_STATUS_SUCCESS)
  3495. goto fail;
  3496. /* Initialize descriptors in TCL Rings */
  3497. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3498. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3499. hal_tx_init_data_ring(soc->hal_soc,
  3500. soc->tcl_data_ring[i].hal_srng);
  3501. }
  3502. }
  3503. /*
  3504. * todo - Add a runtime config option to enable this.
  3505. */
  3506. /*
  3507. * Due to multiple issues on NPR EMU, enable it selectively
  3508. * only for NPR EMU, should be removed, once NPR platforms
  3509. * are stable.
  3510. */
  3511. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3512. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3513. "%s HAL Tx init Success", __func__);
  3514. return QDF_STATUS_SUCCESS;
  3515. fail:
  3516. /* Detach will take care of freeing only allocated resources */
  3517. dp_tx_soc_detach(soc);
  3518. return QDF_STATUS_E_RESOURCES;
  3519. }