dp_main.c 129 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <hal_api.h>
  23. #include <hif.h>
  24. #include <htt.h>
  25. #include <wdi_event.h>
  26. #include <queue.h>
  27. #include "dp_htt.h"
  28. #include "dp_types.h"
  29. #include "dp_internal.h"
  30. #include "dp_tx.h"
  31. #include "dp_tx_desc.h"
  32. #include "dp_rx.h"
  33. #include <cdp_txrx_handle.h>
  34. #include <wlan_cfg.h>
  35. #include "cdp_txrx_cmn_struct.h"
  36. #include <qdf_util.h>
  37. #include "dp_peer.h"
  38. #include "dp_rx_mon.h"
  39. #include "htt_stats.h"
  40. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  41. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  42. #include "cdp_txrx_flow_ctrl_v2.h"
  43. #else
  44. static inline void
  45. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  46. {
  47. return;
  48. }
  49. #endif
  50. #define DP_INTR_POLL_TIMER_MS 10
  51. #define DP_WDS_AGING_TIMER_DEFAULT_MS 6000
  52. #define DP_MCS_LENGTH (6*MAX_MCS)
  53. #define DP_NSS_LENGTH (6*SS_COUNT)
  54. #define DP_RXDMA_ERR_LENGTH (6*MAX_RXDMA_ERRORS)
  55. #define DP_REO_ERR_LENGTH (6*REO_ERROR_TYPE_MAX)
  56. #define DP_CURR_FW_STATS_AVAIL 19
  57. #define DP_HTT_DBG_EXT_STATS_MAX 256
  58. /**
  59. * default_dscp_tid_map - Default DSCP-TID mapping
  60. *
  61. * DSCP TID AC
  62. * 000000 0 WME_AC_BE
  63. * 001000 1 WME_AC_BK
  64. * 010000 1 WME_AC_BK
  65. * 011000 0 WME_AC_BE
  66. * 100000 5 WME_AC_VI
  67. * 101000 5 WME_AC_VI
  68. * 110000 6 WME_AC_VO
  69. * 111000 6 WME_AC_VO
  70. */
  71. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  72. 0, 0, 0, 0, 0, 0, 0, 0,
  73. 1, 1, 1, 1, 1, 1, 1, 1,
  74. 1, 1, 1, 1, 1, 1, 1, 1,
  75. 0, 0, 0, 0, 0, 0, 0, 0,
  76. 5, 5, 5, 5, 5, 5, 5, 5,
  77. 5, 5, 5, 5, 5, 5, 5, 5,
  78. 6, 6, 6, 6, 6, 6, 6, 6,
  79. 6, 6, 6, 6, 6, 6, 6, 6,
  80. };
  81. /**
  82. * @brief Cpu ring map types
  83. */
  84. enum dp_cpu_ring_map_types {
  85. DP_DEFAULT_MAP,
  86. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  87. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  88. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  89. DP_CPU_RING_MAP_MAX
  90. };
  91. /**
  92. * @brief Cpu to tx ring map
  93. */
  94. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  95. {0x0, 0x1, 0x2, 0x0},
  96. {0x1, 0x2, 0x1, 0x2},
  97. {0x0, 0x2, 0x0, 0x2},
  98. {0x2, 0x2, 0x2, 0x2}
  99. };
  100. /**
  101. * @brief Select the type of statistics
  102. */
  103. enum dp_stats_type {
  104. STATS_FW = 0,
  105. STATS_HOST = 1,
  106. STATS_TYPE_MAX = 2,
  107. };
  108. /**
  109. * @brief General Firmware statistics options
  110. *
  111. */
  112. enum dp_fw_stats {
  113. TXRX_FW_STATS_INVALID = -1,
  114. };
  115. /**
  116. * @brief Firmware and Host statistics
  117. * currently supported
  118. */
  119. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  120. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  121. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  122. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  123. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  124. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  125. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  126. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  127. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  128. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  129. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  130. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  131. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  132. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  133. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  134. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  135. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  136. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  137. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  138. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  139. /* Last ENUM for HTT FW STATS */
  140. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  141. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  142. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  143. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  144. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  145. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  146. };
  147. /*
  148. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  149. */
  150. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  151. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  152. {
  153. void *hal_soc = soc->hal_soc;
  154. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  155. /* TODO: See if we should get align size from hal */
  156. uint32_t ring_base_align = 8;
  157. struct hal_srng_params ring_params;
  158. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  159. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  160. srng->hal_srng = NULL;
  161. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  162. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  163. soc->osdev, soc->osdev->dev, srng->alloc_size,
  164. &(srng->base_paddr_unaligned));
  165. if (!srng->base_vaddr_unaligned) {
  166. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  167. FL("alloc failed - ring_type: %d, ring_num %d"),
  168. ring_type, ring_num);
  169. return QDF_STATUS_E_NOMEM;
  170. }
  171. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  172. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  173. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  174. ((unsigned long)(ring_params.ring_base_vaddr) -
  175. (unsigned long)srng->base_vaddr_unaligned);
  176. ring_params.num_entries = num_entries;
  177. /* TODO: Check MSI support and get MSI settings from HIF layer */
  178. ring_params.msi_data = 0;
  179. ring_params.msi_addr = 0;
  180. /*
  181. * Setup interrupt timer and batch counter thresholds for
  182. * interrupt mitigation based on ring type
  183. */
  184. if (ring_type == REO_DST) {
  185. ring_params.intr_timer_thres_us =
  186. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  187. ring_params.intr_batch_cntr_thres_entries =
  188. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  189. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  190. ring_params.intr_timer_thres_us =
  191. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  192. ring_params.intr_batch_cntr_thres_entries =
  193. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  194. } else {
  195. ring_params.intr_timer_thres_us =
  196. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  197. ring_params.intr_batch_cntr_thres_entries =
  198. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  199. }
  200. /* TODO: Currently hal layer takes care of endianness related settings.
  201. * See if these settings need to passed from DP layer
  202. */
  203. ring_params.flags = 0;
  204. /* Enable low threshold interrupts for rx buffer rings (regular and
  205. * monitor buffer rings.
  206. * TODO: See if this is required for any other ring
  207. */
  208. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  209. /* TODO: Setting low threshold to 1/8th of ring size
  210. * see if this needs to be configurable
  211. */
  212. ring_params.low_threshold = num_entries >> 3;
  213. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  214. }
  215. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  216. mac_id, &ring_params);
  217. return 0;
  218. }
  219. /**
  220. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  221. * Any buffers allocated and attached to ring entries are expected to be freed
  222. * before calling this function.
  223. */
  224. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  225. int ring_type, int ring_num)
  226. {
  227. if (!srng->hal_srng) {
  228. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  229. FL("Ring type: %d, num:%d not setup"),
  230. ring_type, ring_num);
  231. return;
  232. }
  233. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  234. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  235. srng->alloc_size,
  236. srng->base_vaddr_unaligned,
  237. srng->base_paddr_unaligned, 0);
  238. }
  239. /* TODO: Need this interface from HIF */
  240. void *hif_get_hal_handle(void *hif_handle);
  241. /*
  242. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  243. * @dp_ctx: DP SOC handle
  244. * @budget: Number of frames/descriptors that can be processed in one shot
  245. *
  246. * Return: remaining budget/quota for the soc device
  247. */
  248. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  249. {
  250. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  251. struct dp_soc *soc = int_ctx->soc;
  252. int ring = 0;
  253. uint32_t work_done = 0;
  254. uint32_t budget = dp_budget;
  255. uint8_t tx_mask = int_ctx->tx_ring_mask;
  256. uint8_t rx_mask = int_ctx->rx_ring_mask;
  257. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  258. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  259. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  260. /* Process Tx completion interrupts first to return back buffers */
  261. if (tx_mask) {
  262. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  263. if (tx_mask & (1 << ring)) {
  264. work_done =
  265. dp_tx_comp_handler(soc, ring, budget);
  266. budget -= work_done;
  267. if (work_done)
  268. QDF_TRACE(QDF_MODULE_ID_DP,
  269. QDF_TRACE_LEVEL_INFO,
  270. "tx mask 0x%x ring %d,"
  271. "budget %d",
  272. tx_mask, ring, budget);
  273. if (budget <= 0)
  274. goto budget_done;
  275. }
  276. }
  277. }
  278. /* Process REO Exception ring interrupt */
  279. if (rx_err_mask) {
  280. work_done = dp_rx_err_process(soc,
  281. soc->reo_exception_ring.hal_srng, budget);
  282. budget -= work_done;
  283. if (work_done)
  284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  285. "REO Exception Ring: work_done %d budget %d",
  286. work_done, budget);
  287. if (budget <= 0) {
  288. goto budget_done;
  289. }
  290. }
  291. /* Process Rx WBM release ring interrupt */
  292. if (rx_wbm_rel_mask) {
  293. work_done = dp_rx_wbm_err_process(soc,
  294. soc->rx_rel_ring.hal_srng, budget);
  295. budget -= work_done;
  296. if (work_done)
  297. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  298. "WBM Release Ring: work_done %d budget %d",
  299. work_done, budget);
  300. if (budget <= 0) {
  301. goto budget_done;
  302. }
  303. }
  304. /* Process Rx interrupts */
  305. if (rx_mask) {
  306. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  307. if (rx_mask & (1 << ring)) {
  308. work_done =
  309. dp_rx_process(int_ctx,
  310. soc->reo_dest_ring[ring].hal_srng,
  311. budget);
  312. budget -= work_done;
  313. if (work_done)
  314. QDF_TRACE(QDF_MODULE_ID_DP,
  315. QDF_TRACE_LEVEL_INFO,
  316. "rx mask 0x%x ring %d,"
  317. "budget %d",
  318. tx_mask, ring, budget);
  319. if (budget <= 0)
  320. goto budget_done;
  321. }
  322. }
  323. }
  324. if (reo_status_mask)
  325. dp_reo_status_ring_handler(soc);
  326. /* Process LMAC interrupts */
  327. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  328. if (soc->pdev_list[ring] == NULL)
  329. continue;
  330. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  331. work_done =
  332. dp_mon_process(soc, ring, budget);
  333. budget -= work_done;
  334. }
  335. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  336. work_done =
  337. dp_rxdma_err_process(soc, ring, budget);
  338. budget -= work_done;
  339. }
  340. }
  341. qdf_lro_flush(int_ctx->lro_ctx);
  342. budget_done:
  343. return dp_budget - budget;
  344. }
  345. /* dp_interrupt_timer()- timer poll for interrupts
  346. *
  347. * @arg: SoC Handle
  348. *
  349. * Return:
  350. *
  351. */
  352. #ifdef DP_INTR_POLL_BASED
  353. static void dp_interrupt_timer(void *arg)
  354. {
  355. struct dp_soc *soc = (struct dp_soc *) arg;
  356. int i;
  357. if (qdf_atomic_read(&soc->cmn_init_done)) {
  358. for (i = 0;
  359. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  360. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  361. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  362. }
  363. }
  364. /*
  365. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  366. * @txrx_soc: DP SOC handle
  367. *
  368. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  369. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  370. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  371. *
  372. * Return: 0 for success. nonzero for failure.
  373. */
  374. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  375. {
  376. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  377. int i;
  378. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  379. soc->intr_ctx[i].tx_ring_mask = 0xF;
  380. soc->intr_ctx[i].rx_ring_mask = 0xF;
  381. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  382. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  383. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  384. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  385. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  386. soc->intr_ctx[i].soc = soc;
  387. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  388. }
  389. qdf_timer_init(soc->osdev, &soc->int_timer,
  390. dp_interrupt_timer, (void *)soc,
  391. QDF_TIMER_TYPE_WAKE_APPS);
  392. return QDF_STATUS_SUCCESS;
  393. }
  394. /*
  395. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  396. * @txrx_soc: DP SOC handle
  397. *
  398. * Return: void
  399. */
  400. static void dp_soc_interrupt_detach(void *txrx_soc)
  401. {
  402. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  403. int i;
  404. qdf_timer_stop(&soc->int_timer);
  405. qdf_timer_free(&soc->int_timer);
  406. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  407. soc->intr_ctx[i].tx_ring_mask = 0;
  408. soc->intr_ctx[i].rx_ring_mask = 0;
  409. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  410. soc->intr_ctx[i].rx_err_ring_mask = 0;
  411. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  412. soc->intr_ctx[i].reo_status_ring_mask = 0;
  413. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  414. }
  415. }
  416. #else
  417. /*
  418. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  419. * @txrx_soc: DP SOC handle
  420. *
  421. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  422. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  423. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  424. *
  425. * Return: 0 for success. nonzero for failure.
  426. */
  427. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  428. {
  429. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  430. int i = 0;
  431. int num_irq = 0;
  432. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  433. int j = 0;
  434. int ret = 0;
  435. /* Map of IRQ ids registered with one interrupt context */
  436. int irq_id_map[HIF_MAX_GRP_IRQ];
  437. int tx_mask =
  438. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  439. int rx_mask =
  440. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  441. int rx_mon_mask =
  442. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  443. int rx_err_ring_mask =
  444. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  445. int rx_wbm_rel_ring_mask =
  446. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  447. int reo_status_ring_mask =
  448. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  449. int rxdma2host_ring_mask =
  450. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  451. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  452. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  453. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  454. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  455. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  456. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  457. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  458. soc->intr_ctx[i].soc = soc;
  459. num_irq = 0;
  460. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  461. if (tx_mask & (1 << j)) {
  462. irq_id_map[num_irq++] =
  463. (wbm2host_tx_completions_ring1 - j);
  464. }
  465. if (rx_mask & (1 << j)) {
  466. irq_id_map[num_irq++] =
  467. (reo2host_destination_ring1 - j);
  468. }
  469. if (rxdma2host_ring_mask & (1 << j)) {
  470. irq_id_map[num_irq++] =
  471. rxdma2host_destination_ring_mac1 -
  472. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  473. }
  474. if (rx_mon_mask & (1 << j)) {
  475. irq_id_map[num_irq++] =
  476. ppdu_end_interrupts_mac1 -
  477. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  478. }
  479. if (rx_wbm_rel_ring_mask & (1 << j))
  480. irq_id_map[num_irq++] = wbm2host_rx_release;
  481. if (rx_err_ring_mask & (1 << j))
  482. irq_id_map[num_irq++] = reo2host_exception;
  483. if (reo_status_ring_mask & (1 << j))
  484. irq_id_map[num_irq++] = reo2host_status;
  485. }
  486. ret = hif_register_ext_group(soc->hif_handle,
  487. num_irq, irq_id_map, dp_service_srngs,
  488. &soc->intr_ctx[i], "dp_intr",
  489. HIF_EXEC_NAPI_TYPE);
  490. if (ret) {
  491. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  492. FL("failed, ret = %d"), ret);
  493. return QDF_STATUS_E_FAILURE;
  494. }
  495. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  496. }
  497. hif_configure_ext_group_interrupts(soc->hif_handle);
  498. return QDF_STATUS_SUCCESS;
  499. }
  500. /*
  501. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  502. * @txrx_soc: DP SOC handle
  503. *
  504. * Return: void
  505. */
  506. static void dp_soc_interrupt_detach(void *txrx_soc)
  507. {
  508. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  509. int i;
  510. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  511. soc->intr_ctx[i].tx_ring_mask = 0;
  512. soc->intr_ctx[i].rx_ring_mask = 0;
  513. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  514. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  515. }
  516. }
  517. #endif
  518. #define AVG_MAX_MPDUS_PER_TID 128
  519. #define AVG_TIDS_PER_CLIENT 2
  520. #define AVG_FLOWS_PER_TID 2
  521. #define AVG_MSDUS_PER_FLOW 128
  522. #define AVG_MSDUS_PER_MPDU 4
  523. /*
  524. * Allocate and setup link descriptor pool that will be used by HW for
  525. * various link and queue descriptors and managed by WBM
  526. */
  527. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  528. {
  529. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  530. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  531. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  532. uint32_t num_mpdus_per_link_desc =
  533. hal_num_mpdus_per_link_desc(soc->hal_soc);
  534. uint32_t num_msdus_per_link_desc =
  535. hal_num_msdus_per_link_desc(soc->hal_soc);
  536. uint32_t num_mpdu_links_per_queue_desc =
  537. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  538. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  539. uint32_t total_link_descs, total_mem_size;
  540. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  541. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  542. uint32_t num_link_desc_banks;
  543. uint32_t last_bank_size = 0;
  544. uint32_t entry_size, num_entries;
  545. int i;
  546. /* Only Tx queue descriptors are allocated from common link descriptor
  547. * pool Rx queue descriptors are not included in this because (REO queue
  548. * extension descriptors) they are expected to be allocated contiguously
  549. * with REO queue descriptors
  550. */
  551. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  552. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  553. num_mpdu_queue_descs = num_mpdu_link_descs /
  554. num_mpdu_links_per_queue_desc;
  555. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  556. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  557. num_msdus_per_link_desc;
  558. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  559. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  560. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  561. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  562. /* Round up to power of 2 */
  563. total_link_descs = 1;
  564. while (total_link_descs < num_entries)
  565. total_link_descs <<= 1;
  566. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  567. FL("total_link_descs: %u, link_desc_size: %d"),
  568. total_link_descs, link_desc_size);
  569. total_mem_size = total_link_descs * link_desc_size;
  570. total_mem_size += link_desc_align;
  571. if (total_mem_size <= max_alloc_size) {
  572. num_link_desc_banks = 0;
  573. last_bank_size = total_mem_size;
  574. } else {
  575. num_link_desc_banks = (total_mem_size) /
  576. (max_alloc_size - link_desc_align);
  577. last_bank_size = total_mem_size %
  578. (max_alloc_size - link_desc_align);
  579. }
  580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  581. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  582. total_mem_size, num_link_desc_banks);
  583. for (i = 0; i < num_link_desc_banks; i++) {
  584. soc->link_desc_banks[i].base_vaddr_unaligned =
  585. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  586. max_alloc_size,
  587. &(soc->link_desc_banks[i].base_paddr_unaligned));
  588. soc->link_desc_banks[i].size = max_alloc_size;
  589. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  590. soc->link_desc_banks[i].base_vaddr_unaligned) +
  591. ((unsigned long)(
  592. soc->link_desc_banks[i].base_vaddr_unaligned) %
  593. link_desc_align));
  594. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  595. soc->link_desc_banks[i].base_paddr_unaligned) +
  596. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  597. (unsigned long)(
  598. soc->link_desc_banks[i].base_vaddr_unaligned));
  599. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  600. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  601. FL("Link descriptor memory alloc failed"));
  602. goto fail;
  603. }
  604. }
  605. if (last_bank_size) {
  606. /* Allocate last bank in case total memory required is not exact
  607. * multiple of max_alloc_size
  608. */
  609. soc->link_desc_banks[i].base_vaddr_unaligned =
  610. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  611. last_bank_size,
  612. &(soc->link_desc_banks[i].base_paddr_unaligned));
  613. soc->link_desc_banks[i].size = last_bank_size;
  614. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  615. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  616. ((unsigned long)(
  617. soc->link_desc_banks[i].base_vaddr_unaligned) %
  618. link_desc_align));
  619. soc->link_desc_banks[i].base_paddr =
  620. (unsigned long)(
  621. soc->link_desc_banks[i].base_paddr_unaligned) +
  622. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  623. (unsigned long)(
  624. soc->link_desc_banks[i].base_vaddr_unaligned));
  625. }
  626. /* Allocate and setup link descriptor idle list for HW internal use */
  627. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  628. total_mem_size = entry_size * total_link_descs;
  629. if (total_mem_size <= max_alloc_size) {
  630. void *desc;
  631. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  632. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  634. FL("Link desc idle ring setup failed"));
  635. goto fail;
  636. }
  637. hal_srng_access_start_unlocked(soc->hal_soc,
  638. soc->wbm_idle_link_ring.hal_srng);
  639. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  640. soc->link_desc_banks[i].base_paddr; i++) {
  641. uint32_t num_entries = (soc->link_desc_banks[i].size -
  642. ((unsigned long)(
  643. soc->link_desc_banks[i].base_vaddr) -
  644. (unsigned long)(
  645. soc->link_desc_banks[i].base_vaddr_unaligned)))
  646. / link_desc_size;
  647. unsigned long paddr = (unsigned long)(
  648. soc->link_desc_banks[i].base_paddr);
  649. while (num_entries && (desc = hal_srng_src_get_next(
  650. soc->hal_soc,
  651. soc->wbm_idle_link_ring.hal_srng))) {
  652. hal_set_link_desc_addr(desc, i, paddr);
  653. num_entries--;
  654. paddr += link_desc_size;
  655. }
  656. }
  657. hal_srng_access_end_unlocked(soc->hal_soc,
  658. soc->wbm_idle_link_ring.hal_srng);
  659. } else {
  660. uint32_t num_scatter_bufs;
  661. uint32_t num_entries_per_buf;
  662. uint32_t rem_entries;
  663. uint8_t *scatter_buf_ptr;
  664. uint16_t scatter_buf_num;
  665. soc->wbm_idle_scatter_buf_size =
  666. hal_idle_list_scatter_buf_size(soc->hal_soc);
  667. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  668. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  669. num_scatter_bufs = (total_mem_size /
  670. soc->wbm_idle_scatter_buf_size) + (total_mem_size %
  671. soc->wbm_idle_scatter_buf_size) ? 1 : 0;
  672. for (i = 0; i < num_scatter_bufs; i++) {
  673. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  674. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  675. soc->wbm_idle_scatter_buf_size,
  676. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  677. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  678. QDF_TRACE(QDF_MODULE_ID_DP,
  679. QDF_TRACE_LEVEL_ERROR,
  680. FL("Scatter list memory alloc failed"));
  681. goto fail;
  682. }
  683. }
  684. /* Populate idle list scatter buffers with link descriptor
  685. * pointers
  686. */
  687. scatter_buf_num = 0;
  688. scatter_buf_ptr = (uint8_t *)(
  689. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  690. rem_entries = num_entries_per_buf;
  691. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  692. soc->link_desc_banks[i].base_paddr; i++) {
  693. uint32_t num_link_descs =
  694. (soc->link_desc_banks[i].size -
  695. ((unsigned long)(
  696. soc->link_desc_banks[i].base_vaddr) -
  697. (unsigned long)(
  698. soc->link_desc_banks[i].base_vaddr_unaligned)))
  699. / link_desc_size;
  700. unsigned long paddr = (unsigned long)(
  701. soc->link_desc_banks[i].base_paddr);
  702. void *desc = NULL;
  703. while (num_link_descs && (desc =
  704. hal_srng_src_get_next(soc->hal_soc,
  705. soc->wbm_idle_link_ring.hal_srng))) {
  706. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  707. i, paddr);
  708. num_link_descs--;
  709. paddr += link_desc_size;
  710. if (rem_entries) {
  711. rem_entries--;
  712. scatter_buf_ptr += link_desc_size;
  713. } else {
  714. rem_entries = num_entries_per_buf;
  715. scatter_buf_num++;
  716. scatter_buf_ptr = (uint8_t *)(
  717. soc->wbm_idle_scatter_buf_base_vaddr[
  718. scatter_buf_num]);
  719. }
  720. }
  721. }
  722. /* Setup link descriptor idle list in HW */
  723. hal_setup_link_idle_list(soc->hal_soc,
  724. soc->wbm_idle_scatter_buf_base_paddr,
  725. soc->wbm_idle_scatter_buf_base_vaddr,
  726. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  727. (uint32_t)(scatter_buf_ptr -
  728. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  729. scatter_buf_num])));
  730. }
  731. return 0;
  732. fail:
  733. if (soc->wbm_idle_link_ring.hal_srng) {
  734. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  735. WBM_IDLE_LINK, 0);
  736. }
  737. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  738. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  739. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  740. soc->wbm_idle_scatter_buf_size,
  741. soc->wbm_idle_scatter_buf_base_vaddr[i],
  742. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  743. }
  744. }
  745. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  746. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  747. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  748. soc->link_desc_banks[i].size,
  749. soc->link_desc_banks[i].base_vaddr_unaligned,
  750. soc->link_desc_banks[i].base_paddr_unaligned,
  751. 0);
  752. }
  753. }
  754. return QDF_STATUS_E_FAILURE;
  755. }
  756. #ifdef notused
  757. /*
  758. * Free link descriptor pool that was setup HW
  759. */
  760. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  761. {
  762. int i;
  763. if (soc->wbm_idle_link_ring.hal_srng) {
  764. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  765. WBM_IDLE_LINK, 0);
  766. }
  767. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  768. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  769. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  770. soc->wbm_idle_scatter_buf_size,
  771. soc->wbm_idle_scatter_buf_base_vaddr[i],
  772. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  773. }
  774. }
  775. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  776. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  777. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  778. soc->link_desc_banks[i].size,
  779. soc->link_desc_banks[i].base_vaddr_unaligned,
  780. soc->link_desc_banks[i].base_paddr_unaligned,
  781. 0);
  782. }
  783. }
  784. }
  785. #endif /* notused */
  786. /* TODO: Following should be configurable */
  787. #define WBM_RELEASE_RING_SIZE 64
  788. #define TCL_CMD_RING_SIZE 32
  789. #define TCL_STATUS_RING_SIZE 32
  790. #define REO_DST_RING_SIZE 2048
  791. #define REO_REINJECT_RING_SIZE 32
  792. #define RX_RELEASE_RING_SIZE 1024
  793. #define REO_EXCEPTION_RING_SIZE 128
  794. #define REO_CMD_RING_SIZE 32
  795. #define REO_STATUS_RING_SIZE 32
  796. #define RXDMA_BUF_RING_SIZE 1024
  797. #define RXDMA_REFILL_RING_SIZE 2048
  798. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  799. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  800. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  801. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  802. #define RXDMA_ERR_DST_RING_SIZE 1024
  803. /*
  804. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  805. * @soc: Datapath SOC handle
  806. *
  807. * This is a timer function used to age out stale WDS nodes from
  808. * AST table
  809. */
  810. #ifdef FEATURE_WDS
  811. static void dp_wds_aging_timer_fn(void *soc_hdl)
  812. {
  813. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  814. struct dp_pdev *pdev;
  815. struct dp_vdev *vdev;
  816. struct dp_peer *peer;
  817. struct dp_ast_entry *ase;
  818. int i;
  819. qdf_spin_lock_bh(&soc->ast_lock);
  820. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  821. pdev = soc->pdev_list[i];
  822. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  823. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  824. DP_PEER_ITERATE_ASE_LIST(peer, ase) {
  825. /*
  826. * Do not expire static ast entries
  827. */
  828. if (ase->is_static)
  829. continue;
  830. if (ase->is_active) {
  831. ase->is_active = FALSE;
  832. continue;
  833. }
  834. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  835. pdev->osif_pdev,
  836. ase->mac_addr.raw);
  837. dp_peer_del_ast(soc, ase);
  838. }
  839. }
  840. }
  841. }
  842. qdf_spin_unlock_bh(&soc->ast_lock);
  843. if (qdf_atomic_read(&soc->cmn_init_done))
  844. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  845. }
  846. /*
  847. * dp_soc_wds_attach() - Setup WDS timer and AST table
  848. * @soc: Datapath SOC handle
  849. *
  850. * Return: None
  851. */
  852. static void dp_soc_wds_attach(struct dp_soc *soc)
  853. {
  854. qdf_spinlock_create(&soc->ast_lock);
  855. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  856. dp_wds_aging_timer_fn, (void *)soc,
  857. QDF_TIMER_TYPE_WAKE_APPS);
  858. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  859. }
  860. /*
  861. * dp_soc_wds_detach() - Detach WDS data structures and timers
  862. * @txrx_soc: DP SOC handle
  863. *
  864. * Return: None
  865. */
  866. static void dp_soc_wds_detach(struct dp_soc *soc)
  867. {
  868. qdf_timer_stop(&soc->wds_aging_timer);
  869. qdf_timer_free(&soc->wds_aging_timer);
  870. qdf_spinlock_destroy(&soc->ast_lock);
  871. }
  872. #else
  873. static void dp_soc_wds_attach(struct dp_soc *soc)
  874. {
  875. }
  876. static void dp_soc_wds_detach(struct dp_soc *soc)
  877. {
  878. }
  879. #endif
  880. /*
  881. * dp_soc_reset_ring_map() - Reset cpu ring map
  882. * @soc: Datapath soc handler
  883. *
  884. * This api resets the default cpu ring map
  885. */
  886. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  887. {
  888. uint8_t i;
  889. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  890. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  891. if (nss_config == 1) {
  892. /*
  893. * Setting Tx ring map for one nss offloaded radio
  894. */
  895. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  896. } else if (nss_config == 2) {
  897. /*
  898. * Setting Tx ring for two nss offloaded radios
  899. */
  900. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  901. } else {
  902. /*
  903. * Setting Tx ring map for all nss offloaded radios
  904. */
  905. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  906. }
  907. }
  908. }
  909. /*
  910. * dp_soc_cmn_setup() - Common SoC level initializion
  911. * @soc: Datapath SOC handle
  912. *
  913. * This is an internal function used to setup common SOC data structures,
  914. * to be called from PDEV attach after receiving HW mode capabilities from FW
  915. */
  916. static int dp_soc_cmn_setup(struct dp_soc *soc)
  917. {
  918. int i;
  919. struct hal_reo_params reo_params;
  920. int tx_ring_size;
  921. int tx_comp_ring_size;
  922. if (qdf_atomic_read(&soc->cmn_init_done))
  923. return 0;
  924. if (dp_peer_find_attach(soc))
  925. goto fail0;
  926. if (dp_hw_link_desc_pool_setup(soc))
  927. goto fail1;
  928. /* Setup SRNG rings */
  929. /* Common rings */
  930. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  931. WBM_RELEASE_RING_SIZE)) {
  932. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  933. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  934. goto fail1;
  935. }
  936. soc->num_tcl_data_rings = 0;
  937. /* Tx data rings */
  938. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  939. soc->num_tcl_data_rings =
  940. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  941. tx_comp_ring_size =
  942. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  943. tx_ring_size =
  944. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  945. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  946. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  947. TCL_DATA, i, 0, tx_ring_size)) {
  948. QDF_TRACE(QDF_MODULE_ID_DP,
  949. QDF_TRACE_LEVEL_ERROR,
  950. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  951. goto fail1;
  952. }
  953. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  954. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  955. QDF_TRACE(QDF_MODULE_ID_DP,
  956. QDF_TRACE_LEVEL_ERROR,
  957. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  958. goto fail1;
  959. }
  960. }
  961. } else {
  962. /* This will be incremented during per pdev ring setup */
  963. soc->num_tcl_data_rings = 0;
  964. }
  965. if (dp_tx_soc_attach(soc)) {
  966. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  967. FL("dp_tx_soc_attach failed"));
  968. goto fail1;
  969. }
  970. /* TCL command and status rings */
  971. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  972. TCL_CMD_RING_SIZE)) {
  973. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  974. FL("dp_srng_setup failed for tcl_cmd_ring"));
  975. goto fail1;
  976. }
  977. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  978. TCL_STATUS_RING_SIZE)) {
  979. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  980. FL("dp_srng_setup failed for tcl_status_ring"));
  981. goto fail1;
  982. }
  983. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  984. * descriptors
  985. */
  986. /* Rx data rings */
  987. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  988. soc->num_reo_dest_rings =
  989. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  990. QDF_TRACE(QDF_MODULE_ID_DP,
  991. QDF_TRACE_LEVEL_ERROR,
  992. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  993. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  994. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  995. i, 0, REO_DST_RING_SIZE)) {
  996. QDF_TRACE(QDF_MODULE_ID_DP,
  997. QDF_TRACE_LEVEL_ERROR,
  998. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  999. goto fail1;
  1000. }
  1001. }
  1002. } else {
  1003. /* This will be incremented during per pdev ring setup */
  1004. soc->num_reo_dest_rings = 0;
  1005. }
  1006. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1007. /* REO reinjection ring */
  1008. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1009. REO_REINJECT_RING_SIZE)) {
  1010. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1011. FL("dp_srng_setup failed for reo_reinject_ring"));
  1012. goto fail1;
  1013. }
  1014. /* Rx release ring */
  1015. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1016. RX_RELEASE_RING_SIZE)) {
  1017. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1018. FL("dp_srng_setup failed for rx_rel_ring"));
  1019. goto fail1;
  1020. }
  1021. /* Rx exception ring */
  1022. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1023. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1024. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1025. FL("dp_srng_setup failed for reo_exception_ring"));
  1026. goto fail1;
  1027. }
  1028. /* REO command and status rings */
  1029. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1030. REO_CMD_RING_SIZE)) {
  1031. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1032. FL("dp_srng_setup failed for reo_cmd_ring"));
  1033. goto fail1;
  1034. }
  1035. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1036. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1037. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1038. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1039. REO_STATUS_RING_SIZE)) {
  1040. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1041. FL("dp_srng_setup failed for reo_status_ring"));
  1042. goto fail1;
  1043. }
  1044. dp_soc_wds_attach(soc);
  1045. /* Reset the cpu ring map if radio is NSS offloaded */
  1046. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1047. dp_soc_reset_cpu_ring_map(soc);
  1048. }
  1049. /* Setup HW REO */
  1050. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1051. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx))
  1052. reo_params.rx_hash_enabled = true;
  1053. hal_reo_setup(soc->hal_soc, &reo_params);
  1054. qdf_atomic_set(&soc->cmn_init_done, 1);
  1055. qdf_nbuf_queue_init(&soc->htt_stats_msg);
  1056. return 0;
  1057. fail1:
  1058. /*
  1059. * Cleanup will be done as part of soc_detach, which will
  1060. * be called on pdev attach failure
  1061. */
  1062. fail0:
  1063. return QDF_STATUS_E_FAILURE;
  1064. }
  1065. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1066. static void dp_lro_hash_setup(struct dp_soc *soc)
  1067. {
  1068. struct cdp_lro_hash_config lro_hash;
  1069. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1070. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1071. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1072. FL("LRO disabled RX hash disabled"));
  1073. return;
  1074. }
  1075. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1076. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1077. lro_hash.lro_enable = 1;
  1078. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1079. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1080. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1081. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1082. }
  1083. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1084. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1085. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1086. LRO_IPV4_SEED_ARR_SZ));
  1087. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1088. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1089. LRO_IPV6_SEED_ARR_SZ));
  1090. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1091. "lro_hash: lro_enable: 0x%x"
  1092. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1093. lro_hash.lro_enable, lro_hash.tcp_flag,
  1094. lro_hash.tcp_flag_mask);
  1095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1096. FL("lro_hash: toeplitz_hash_ipv4:"));
  1097. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1098. QDF_TRACE_LEVEL_ERROR,
  1099. (void *)lro_hash.toeplitz_hash_ipv4,
  1100. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1101. LRO_IPV4_SEED_ARR_SZ));
  1102. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1103. FL("lro_hash: toeplitz_hash_ipv6:"));
  1104. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1105. QDF_TRACE_LEVEL_ERROR,
  1106. (void *)lro_hash.toeplitz_hash_ipv6,
  1107. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1108. LRO_IPV6_SEED_ARR_SZ));
  1109. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1110. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1111. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1112. (soc->osif_soc, &lro_hash);
  1113. }
  1114. /*
  1115. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1116. * @soc: data path SoC handle
  1117. * @pdev: Physical device handle
  1118. *
  1119. * Return: 0 - success, > 0 - failure
  1120. */
  1121. #ifdef QCA_HOST2FW_RXBUF_RING
  1122. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1123. struct dp_pdev *pdev)
  1124. {
  1125. int max_mac_rings =
  1126. wlan_cfg_get_num_mac_rings
  1127. (pdev->wlan_cfg_ctx);
  1128. int i;
  1129. for (i = 0; i < max_mac_rings; i++) {
  1130. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1131. "%s: pdev_id %d mac_id %d\n",
  1132. __func__, pdev->pdev_id, i);
  1133. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1134. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1135. QDF_TRACE(QDF_MODULE_ID_DP,
  1136. QDF_TRACE_LEVEL_ERROR,
  1137. FL("failed rx mac ring setup"));
  1138. return QDF_STATUS_E_FAILURE;
  1139. }
  1140. }
  1141. return QDF_STATUS_SUCCESS;
  1142. }
  1143. #else
  1144. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1145. struct dp_pdev *pdev)
  1146. {
  1147. return QDF_STATUS_SUCCESS;
  1148. }
  1149. #endif
  1150. /**
  1151. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1152. * @pdev - DP_PDEV handle
  1153. *
  1154. * Return: void
  1155. */
  1156. static inline void
  1157. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1158. {
  1159. uint8_t map_id;
  1160. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1161. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1162. sizeof(default_dscp_tid_map));
  1163. }
  1164. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1165. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1166. pdev->dscp_tid_map[map_id],
  1167. map_id);
  1168. }
  1169. }
  1170. /*
  1171. * dp_reset_intr_mask() - reset interrupt mask
  1172. * @dp_soc - DP Soc handle
  1173. * @dp_pdev - DP pdev handle
  1174. *
  1175. * Return: Return void
  1176. */
  1177. static inline
  1178. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1179. {
  1180. /*
  1181. * We will set the interrupt mask to zero for NSS offloaded radio
  1182. */
  1183. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1184. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1185. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1186. }
  1187. /*
  1188. * dp_pdev_attach_wifi3() - attach txrx pdev
  1189. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1190. * @txrx_soc: Datapath SOC handle
  1191. * @htc_handle: HTC handle for host-target interface
  1192. * @qdf_osdev: QDF OS device
  1193. * @pdev_id: PDEV ID
  1194. *
  1195. * Return: DP PDEV handle on success, NULL on failure
  1196. */
  1197. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1198. struct cdp_cfg *ctrl_pdev,
  1199. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1200. {
  1201. int tx_ring_size;
  1202. int tx_comp_ring_size;
  1203. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1204. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1205. if (!pdev) {
  1206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1207. FL("DP PDEV memory allocation failed"));
  1208. goto fail0;
  1209. }
  1210. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1211. if (!pdev->wlan_cfg_ctx) {
  1212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1213. FL("pdev cfg_attach failed"));
  1214. qdf_mem_free(pdev);
  1215. goto fail0;
  1216. }
  1217. /*
  1218. * set nss pdev config based on soc config
  1219. */
  1220. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1221. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1222. pdev->soc = soc;
  1223. pdev->osif_pdev = ctrl_pdev;
  1224. pdev->pdev_id = pdev_id;
  1225. soc->pdev_list[pdev_id] = pdev;
  1226. soc->pdev_count++;
  1227. TAILQ_INIT(&pdev->vdev_list);
  1228. pdev->vdev_count = 0;
  1229. qdf_spinlock_create(&pdev->tx_mutex);
  1230. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1231. TAILQ_INIT(&pdev->neighbour_peers_list);
  1232. if (dp_soc_cmn_setup(soc)) {
  1233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1234. FL("dp_soc_cmn_setup failed"));
  1235. goto fail1;
  1236. }
  1237. /* Setup per PDEV TCL rings if configured */
  1238. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1239. tx_ring_size =
  1240. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1241. tx_comp_ring_size =
  1242. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1243. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1244. pdev_id, pdev_id, tx_ring_size)) {
  1245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1246. FL("dp_srng_setup failed for tcl_data_ring"));
  1247. goto fail1;
  1248. }
  1249. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1250. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1251. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1252. FL("dp_srng_setup failed for tx_comp_ring"));
  1253. goto fail1;
  1254. }
  1255. soc->num_tcl_data_rings++;
  1256. }
  1257. /* Tx specific init */
  1258. if (dp_tx_pdev_attach(pdev)) {
  1259. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1260. FL("dp_tx_pdev_attach failed"));
  1261. goto fail1;
  1262. }
  1263. /* Setup per PDEV REO rings if configured */
  1264. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1265. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1266. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1267. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1268. FL("dp_srng_setup failed for reo_dest_ringn"));
  1269. goto fail1;
  1270. }
  1271. soc->num_reo_dest_rings++;
  1272. }
  1273. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1274. RXDMA_REFILL_RING_SIZE)) {
  1275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1276. FL("dp_srng_setup failed rx refill ring"));
  1277. goto fail1;
  1278. }
  1279. if (dp_rxdma_ring_setup(soc, pdev)) {
  1280. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1281. FL("RXDMA ring config failed"));
  1282. goto fail1;
  1283. }
  1284. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1285. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1286. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1287. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1288. goto fail1;
  1289. }
  1290. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1291. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1293. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1294. goto fail1;
  1295. }
  1296. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1297. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1298. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1299. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1300. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1301. goto fail1;
  1302. }
  1303. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1304. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1305. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1306. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1307. goto fail1;
  1308. }
  1309. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  1310. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1312. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1313. goto fail1;
  1314. }
  1315. /* Rx specific init */
  1316. if (dp_rx_pdev_attach(pdev)) {
  1317. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1318. FL("dp_rx_pdev_attach failed "));
  1319. goto fail0;
  1320. }
  1321. DP_STATS_INIT(pdev);
  1322. #ifndef CONFIG_WIN
  1323. /* MCL */
  1324. dp_local_peer_id_pool_init(pdev);
  1325. #endif
  1326. dp_dscp_tid_map_setup(pdev);
  1327. /* Rx monitor mode specific init */
  1328. if (dp_rx_pdev_mon_attach(pdev)) {
  1329. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1330. "dp_rx_pdev_attach failed\n");
  1331. goto fail1;
  1332. }
  1333. if (dp_wdi_event_attach(pdev)) {
  1334. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1335. "dp_wdi_evet_attach failed\n");
  1336. goto fail1;
  1337. }
  1338. /* set the reo destination during initialization */
  1339. pdev->reo_dest = pdev->pdev_id + 1;
  1340. /*
  1341. * reset the interrupt mask for offloaded radio
  1342. */
  1343. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  1344. dp_soc_reset_intr_mask(soc, pdev);
  1345. }
  1346. return (struct cdp_pdev *)pdev;
  1347. fail1:
  1348. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1349. fail0:
  1350. return NULL;
  1351. }
  1352. /*
  1353. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1354. * @soc: data path SoC handle
  1355. * @pdev: Physical device handle
  1356. *
  1357. * Return: void
  1358. */
  1359. #ifdef QCA_HOST2FW_RXBUF_RING
  1360. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1361. struct dp_pdev *pdev)
  1362. {
  1363. int max_mac_rings =
  1364. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1365. int i;
  1366. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1367. max_mac_rings : MAX_RX_MAC_RINGS;
  1368. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  1369. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  1370. RXDMA_BUF, 1);
  1371. }
  1372. #else
  1373. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1374. struct dp_pdev *pdev)
  1375. {
  1376. }
  1377. #endif
  1378. /*
  1379. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  1380. * @pdev: device object
  1381. *
  1382. * Return: void
  1383. */
  1384. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  1385. {
  1386. struct dp_neighbour_peer *peer = NULL;
  1387. struct dp_neighbour_peer *temp_peer = NULL;
  1388. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  1389. neighbour_peer_list_elem, temp_peer) {
  1390. /* delete this peer from the list */
  1391. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  1392. peer, neighbour_peer_list_elem);
  1393. qdf_mem_free(peer);
  1394. }
  1395. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  1396. }
  1397. /*
  1398. * dp_pdev_detach_wifi3() - detach txrx pdev
  1399. * @txrx_pdev: Datapath PDEV handle
  1400. * @force: Force detach
  1401. *
  1402. */
  1403. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  1404. {
  1405. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1406. struct dp_soc *soc = pdev->soc;
  1407. dp_wdi_event_detach(pdev);
  1408. dp_tx_pdev_detach(pdev);
  1409. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1410. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  1411. TCL_DATA, pdev->pdev_id);
  1412. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  1413. WBM2SW_RELEASE, pdev->pdev_id);
  1414. }
  1415. dp_rx_pdev_detach(pdev);
  1416. dp_rx_pdev_mon_detach(pdev);
  1417. dp_neighbour_peers_detach(pdev);
  1418. qdf_spinlock_destroy(&pdev->tx_mutex);
  1419. /* Setup per PDEV REO rings if configured */
  1420. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1421. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  1422. REO_DST, pdev->pdev_id);
  1423. }
  1424. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  1425. dp_rxdma_ring_cleanup(soc, pdev);
  1426. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  1427. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  1428. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  1429. RXDMA_MONITOR_STATUS, 0);
  1430. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  1431. RXDMA_MONITOR_DESC, 0);
  1432. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  1433. soc->pdev_list[pdev->pdev_id] = NULL;
  1434. soc->pdev_count--;
  1435. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  1436. qdf_mem_free(pdev);
  1437. }
  1438. /*
  1439. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  1440. * @soc: DP SOC handle
  1441. */
  1442. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  1443. {
  1444. struct reo_desc_list_node *desc;
  1445. struct dp_rx_tid *rx_tid;
  1446. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  1447. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  1448. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  1449. rx_tid = &desc->rx_tid;
  1450. qdf_mem_unmap_nbytes_single(soc->osdev,
  1451. rx_tid->hw_qdesc_paddr,
  1452. QDF_DMA_BIDIRECTIONAL,
  1453. rx_tid->hw_qdesc_alloc_size);
  1454. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  1455. qdf_mem_free(desc);
  1456. }
  1457. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  1458. qdf_list_destroy(&soc->reo_desc_freelist);
  1459. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  1460. }
  1461. /*
  1462. * dp_soc_detach_wifi3() - Detach txrx SOC
  1463. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  1464. *
  1465. */
  1466. static void dp_soc_detach_wifi3(void *txrx_soc)
  1467. {
  1468. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1469. int i;
  1470. qdf_atomic_set(&soc->cmn_init_done, 0);
  1471. qdf_flush_work(0, &soc->htt_stats_work);
  1472. qdf_disable_work(0, &soc->htt_stats_work);
  1473. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1474. if (soc->pdev_list[i])
  1475. dp_pdev_detach_wifi3(
  1476. (struct cdp_pdev *)soc->pdev_list[i], 1);
  1477. }
  1478. dp_peer_find_detach(soc);
  1479. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  1480. * SW descriptors
  1481. */
  1482. /* Free the ring memories */
  1483. /* Common rings */
  1484. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  1485. dp_tx_soc_detach(soc);
  1486. /* Tx data rings */
  1487. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1488. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1489. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  1490. TCL_DATA, i);
  1491. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  1492. WBM2SW_RELEASE, i);
  1493. }
  1494. }
  1495. /* TCL command and status rings */
  1496. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  1497. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  1498. /* Rx data rings */
  1499. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1500. soc->num_reo_dest_rings =
  1501. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1502. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1503. /* TODO: Get number of rings and ring sizes
  1504. * from wlan_cfg
  1505. */
  1506. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  1507. REO_DST, i);
  1508. }
  1509. }
  1510. /* REO reinjection ring */
  1511. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  1512. /* Rx release ring */
  1513. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  1514. /* Rx exception ring */
  1515. /* TODO: Better to store ring_type and ring_num in
  1516. * dp_srng during setup
  1517. */
  1518. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  1519. /* REO command and status rings */
  1520. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  1521. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  1522. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  1523. htt_soc_detach(soc->htt_handle);
  1524. dp_reo_cmdlist_destroy(soc);
  1525. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  1526. dp_reo_desc_freelist_destroy(soc);
  1527. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  1528. dp_soc_wds_detach(soc);
  1529. qdf_mem_free(soc);
  1530. }
  1531. /*
  1532. * dp_rxdma_ring_config() - configure the RX DMA rings
  1533. *
  1534. * This function is used to configure the MAC rings.
  1535. * On MCL host provides buffers in Host2FW ring
  1536. * FW refills (copies) buffers to the ring and updates
  1537. * ring_idx in register
  1538. *
  1539. * @soc: data path SoC handle
  1540. * @pdev: Physical device handle
  1541. *
  1542. * Return: void
  1543. */
  1544. #ifdef QCA_HOST2FW_RXBUF_RING
  1545. static void dp_rxdma_ring_config(struct dp_soc *soc)
  1546. {
  1547. int i;
  1548. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1549. struct dp_pdev *pdev = soc->pdev_list[i];
  1550. if (pdev) {
  1551. int mac_id = 0;
  1552. int j;
  1553. bool dbs_enable = 0;
  1554. int max_mac_rings =
  1555. wlan_cfg_get_num_mac_rings
  1556. (pdev->wlan_cfg_ctx);
  1557. htt_srng_setup(soc->htt_handle, 0,
  1558. pdev->rx_refill_buf_ring.hal_srng,
  1559. RXDMA_BUF);
  1560. if (soc->cdp_soc.ol_ops->
  1561. is_hw_dbs_2x2_capable) {
  1562. dbs_enable = soc->cdp_soc.ol_ops->
  1563. is_hw_dbs_2x2_capable(soc->psoc);
  1564. }
  1565. if (dbs_enable) {
  1566. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1567. QDF_TRACE_LEVEL_ERROR,
  1568. FL("DBS enabled max_mac_rings %d\n"),
  1569. max_mac_rings);
  1570. } else {
  1571. max_mac_rings = 1;
  1572. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1573. QDF_TRACE_LEVEL_ERROR,
  1574. FL("DBS disabled, max_mac_rings %d\n"),
  1575. max_mac_rings);
  1576. }
  1577. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1578. FL("pdev_id %d max_mac_rings %d\n"),
  1579. pdev->pdev_id, max_mac_rings);
  1580. for (j = 0; j < max_mac_rings; j++) {
  1581. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1582. QDF_TRACE_LEVEL_ERROR,
  1583. FL("mac_id %d\n"), mac_id);
  1584. htt_srng_setup(soc->htt_handle, mac_id,
  1585. pdev->rx_mac_buf_ring[j]
  1586. .hal_srng,
  1587. RXDMA_BUF);
  1588. mac_id++;
  1589. }
  1590. /* Configure monitor mode rings */
  1591. htt_srng_setup(soc->htt_handle, i,
  1592. pdev->rxdma_mon_buf_ring.hal_srng,
  1593. RXDMA_MONITOR_BUF);
  1594. htt_srng_setup(soc->htt_handle, i,
  1595. pdev->rxdma_mon_dst_ring.hal_srng,
  1596. RXDMA_MONITOR_DST);
  1597. htt_srng_setup(soc->htt_handle, i,
  1598. pdev->rxdma_mon_status_ring.hal_srng,
  1599. RXDMA_MONITOR_STATUS);
  1600. htt_srng_setup(soc->htt_handle, i,
  1601. pdev->rxdma_mon_desc_ring.hal_srng,
  1602. RXDMA_MONITOR_DESC);
  1603. htt_srng_setup(soc->htt_handle, i,
  1604. pdev->rxdma_err_dst_ring.hal_srng,
  1605. RXDMA_DST);
  1606. }
  1607. }
  1608. }
  1609. #else
  1610. static void dp_rxdma_ring_config(struct dp_soc *soc)
  1611. {
  1612. int i;
  1613. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1614. struct dp_pdev *pdev = soc->pdev_list[i];
  1615. if (pdev) {
  1616. htt_srng_setup(soc->htt_handle, i,
  1617. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  1618. htt_srng_setup(soc->htt_handle, i,
  1619. pdev->rxdma_mon_buf_ring.hal_srng,
  1620. RXDMA_MONITOR_BUF);
  1621. htt_srng_setup(soc->htt_handle, i,
  1622. pdev->rxdma_mon_dst_ring.hal_srng,
  1623. RXDMA_MONITOR_DST);
  1624. htt_srng_setup(soc->htt_handle, i,
  1625. pdev->rxdma_mon_status_ring.hal_srng,
  1626. RXDMA_MONITOR_STATUS);
  1627. htt_srng_setup(soc->htt_handle, i,
  1628. pdev->rxdma_mon_desc_ring.hal_srng,
  1629. RXDMA_MONITOR_DESC);
  1630. htt_srng_setup(soc->htt_handle, i,
  1631. pdev->rxdma_err_dst_ring.hal_srng,
  1632. RXDMA_DST);
  1633. }
  1634. }
  1635. }
  1636. #endif
  1637. /*
  1638. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  1639. * @txrx_soc: Datapath SOC handle
  1640. */
  1641. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  1642. {
  1643. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  1644. htt_soc_attach_target(soc->htt_handle);
  1645. dp_rxdma_ring_config(soc);
  1646. DP_STATS_INIT(soc);
  1647. /* initialize work queue for stats processing */
  1648. qdf_create_work(0, &soc->htt_stats_work, htt_t2h_stats_handler, soc);
  1649. return 0;
  1650. }
  1651. /*
  1652. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  1653. * @txrx_soc: Datapath SOC handle
  1654. */
  1655. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  1656. {
  1657. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  1658. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  1659. }
  1660. /*
  1661. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  1662. * @txrx_soc: Datapath SOC handle
  1663. * @nss_cfg: nss config
  1664. */
  1665. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  1666. {
  1667. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  1668. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  1669. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1670. FL("nss-wifi<0> nss config is enabled"));
  1671. }
  1672. /*
  1673. * dp_vdev_attach_wifi3() - attach txrx vdev
  1674. * @txrx_pdev: Datapath PDEV handle
  1675. * @vdev_mac_addr: MAC address of the virtual interface
  1676. * @vdev_id: VDEV Id
  1677. * @wlan_op_mode: VDEV operating mode
  1678. *
  1679. * Return: DP VDEV handle on success, NULL on failure
  1680. */
  1681. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  1682. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  1683. {
  1684. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1685. struct dp_soc *soc = pdev->soc;
  1686. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  1687. int tx_ring_size;
  1688. if (!vdev) {
  1689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1690. FL("DP VDEV memory allocation failed"));
  1691. goto fail0;
  1692. }
  1693. vdev->pdev = pdev;
  1694. vdev->vdev_id = vdev_id;
  1695. vdev->opmode = op_mode;
  1696. vdev->osdev = soc->osdev;
  1697. vdev->osif_rx = NULL;
  1698. vdev->osif_rsim_rx_decap = NULL;
  1699. vdev->osif_rx_mon = NULL;
  1700. vdev->osif_tx_free_ext = NULL;
  1701. vdev->osif_vdev = NULL;
  1702. vdev->delete.pending = 0;
  1703. vdev->safemode = 0;
  1704. vdev->drop_unenc = 1;
  1705. #ifdef notyet
  1706. vdev->filters_num = 0;
  1707. #endif
  1708. qdf_mem_copy(
  1709. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  1710. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  1711. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  1712. vdev->dscp_tid_map_id = 0;
  1713. vdev->mcast_enhancement_en = 0;
  1714. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1715. /* TODO: Initialize default HTT meta data that will be used in
  1716. * TCL descriptors for packets transmitted from this VDEV
  1717. */
  1718. TAILQ_INIT(&vdev->peer_list);
  1719. /* add this vdev into the pdev's list */
  1720. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  1721. pdev->vdev_count++;
  1722. dp_tx_vdev_attach(vdev);
  1723. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  1724. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  1725. goto fail1;
  1726. #ifdef DP_INTR_POLL_BASED
  1727. if (wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  1728. if (pdev->vdev_count == 1)
  1729. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  1730. }
  1731. #endif
  1732. dp_lro_hash_setup(soc);
  1733. /* LRO */
  1734. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1735. wlan_op_mode_sta == vdev->opmode)
  1736. vdev->lro_enable = true;
  1737. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1738. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  1739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1740. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  1741. DP_STATS_INIT(vdev);
  1742. return (struct cdp_vdev *)vdev;
  1743. fail1:
  1744. dp_tx_vdev_detach(vdev);
  1745. qdf_mem_free(vdev);
  1746. fail0:
  1747. return NULL;
  1748. }
  1749. /**
  1750. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  1751. * @vdev: Datapath VDEV handle
  1752. * @osif_vdev: OSIF vdev handle
  1753. * @txrx_ops: Tx and Rx operations
  1754. *
  1755. * Return: DP VDEV handle on success, NULL on failure
  1756. */
  1757. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  1758. void *osif_vdev,
  1759. struct ol_txrx_ops *txrx_ops)
  1760. {
  1761. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1762. vdev->osif_vdev = osif_vdev;
  1763. vdev->osif_rx = txrx_ops->rx.rx;
  1764. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  1765. vdev->osif_rx_mon = txrx_ops->rx.mon;
  1766. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  1767. #ifdef notyet
  1768. #if ATH_SUPPORT_WAPI
  1769. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  1770. #endif
  1771. #endif
  1772. #ifdef UMAC_SUPPORT_PROXY_ARP
  1773. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  1774. #endif
  1775. vdev->me_convert = txrx_ops->me_convert;
  1776. /* TODO: Enable the following once Tx code is integrated */
  1777. txrx_ops->tx.tx = dp_tx_send;
  1778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1779. "DP Vdev Register success");
  1780. }
  1781. /*
  1782. * dp_vdev_detach_wifi3() - Detach txrx vdev
  1783. * @txrx_vdev: Datapath VDEV handle
  1784. * @callback: Callback OL_IF on completion of detach
  1785. * @cb_context: Callback context
  1786. *
  1787. */
  1788. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  1789. ol_txrx_vdev_delete_cb callback, void *cb_context)
  1790. {
  1791. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1792. struct dp_pdev *pdev = vdev->pdev;
  1793. struct dp_soc *soc = pdev->soc;
  1794. /* preconditions */
  1795. qdf_assert(vdev);
  1796. /* remove the vdev from its parent pdev's list */
  1797. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  1798. /*
  1799. * Use peer_ref_mutex while accessing peer_list, in case
  1800. * a peer is in the process of being removed from the list.
  1801. */
  1802. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1803. /* check that the vdev has no peers allocated */
  1804. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  1805. /* debug print - will be removed later */
  1806. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  1807. FL("not deleting vdev object %p (%pM)"
  1808. "until deletion finishes for all its peers"),
  1809. vdev, vdev->mac_addr.raw);
  1810. /* indicate that the vdev needs to be deleted */
  1811. vdev->delete.pending = 1;
  1812. vdev->delete.callback = callback;
  1813. vdev->delete.context = cb_context;
  1814. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1815. return;
  1816. }
  1817. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1818. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  1819. vdev->vdev_id);
  1820. dp_tx_vdev_detach(vdev);
  1821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1822. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  1823. qdf_mem_free(vdev);
  1824. if (callback)
  1825. callback(cb_context);
  1826. }
  1827. /*
  1828. * dp_peer_create_wifi3() - attach txrx peer
  1829. * @txrx_vdev: Datapath VDEV handle
  1830. * @peer_mac_addr: Peer MAC address
  1831. *
  1832. * Return: DP peeer handle on success, NULL on failure
  1833. */
  1834. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  1835. uint8_t *peer_mac_addr)
  1836. {
  1837. struct dp_peer *peer;
  1838. int i;
  1839. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1840. struct dp_pdev *pdev;
  1841. struct dp_soc *soc;
  1842. /* preconditions */
  1843. qdf_assert(vdev);
  1844. qdf_assert(peer_mac_addr);
  1845. pdev = vdev->pdev;
  1846. soc = pdev->soc;
  1847. #ifdef notyet
  1848. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  1849. soc->mempool_ol_ath_peer);
  1850. #else
  1851. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  1852. #endif
  1853. if (!peer)
  1854. return NULL; /* failure */
  1855. qdf_mem_zero(peer, sizeof(struct dp_peer));
  1856. TAILQ_INIT(&peer->ast_entry_list);
  1857. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  1858. qdf_spinlock_create(&peer->peer_info_lock);
  1859. /* store provided params */
  1860. peer->vdev = vdev;
  1861. qdf_mem_copy(
  1862. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  1863. /* TODO: See of rx_opt_proc is really required */
  1864. peer->rx_opt_proc = soc->rx_opt_proc;
  1865. /* initialize the peer_id */
  1866. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  1867. peer->peer_ids[i] = HTT_INVALID_PEER;
  1868. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1869. qdf_atomic_init(&peer->ref_cnt);
  1870. /* keep one reference for attach */
  1871. qdf_atomic_inc(&peer->ref_cnt);
  1872. /* add this peer into the vdev's list */
  1873. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  1874. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1875. /* TODO: See if hash based search is required */
  1876. dp_peer_find_hash_add(soc, peer);
  1877. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1878. "vdev %p created peer %p (%pM) ref_cnt: %d",
  1879. vdev, peer, peer->mac_addr.raw,
  1880. qdf_atomic_read(&peer->ref_cnt));
  1881. /*
  1882. * For every peer MAp message search and set if bss_peer
  1883. */
  1884. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  1885. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1886. "vdev bss_peer!!!!");
  1887. peer->bss_peer = 1;
  1888. vdev->vap_bss_peer = peer;
  1889. }
  1890. #ifndef CONFIG_WIN
  1891. dp_local_peer_id_alloc(pdev, peer);
  1892. #endif
  1893. DP_STATS_INIT(peer);
  1894. return (void *)peer;
  1895. }
  1896. /*
  1897. * dp_peer_setup_wifi3() - initialize the peer
  1898. * @vdev_hdl: virtual device object
  1899. * @peer: Peer object
  1900. *
  1901. * Return: void
  1902. */
  1903. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  1904. {
  1905. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  1906. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  1907. struct dp_pdev *pdev;
  1908. struct dp_soc *soc;
  1909. bool hash_based = 0;
  1910. enum cdp_host_reo_dest_ring reo_dest;
  1911. /* preconditions */
  1912. qdf_assert(vdev);
  1913. qdf_assert(peer);
  1914. pdev = vdev->pdev;
  1915. soc = pdev->soc;
  1916. dp_peer_rx_init(pdev, peer);
  1917. peer->last_assoc_rcvd = 0;
  1918. peer->last_disassoc_rcvd = 0;
  1919. peer->last_deauth_rcvd = 0;
  1920. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1922. FL("hash based steering %d\n"), hash_based);
  1923. if (!hash_based)
  1924. reo_dest = pdev->reo_dest;
  1925. else
  1926. reo_dest = 1;
  1927. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  1928. /* TODO: Check the destination ring number to be passed to FW */
  1929. soc->cdp_soc.ol_ops->peer_set_default_routing(
  1930. pdev->osif_pdev, peer->mac_addr.raw,
  1931. peer->vdev->vdev_id, hash_based, reo_dest);
  1932. }
  1933. return;
  1934. }
  1935. /*
  1936. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  1937. * @vdev_handle: virtual device object
  1938. * @htt_pkt_type: type of pkt
  1939. *
  1940. * Return: void
  1941. */
  1942. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  1943. enum htt_cmn_pkt_type val)
  1944. {
  1945. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1946. vdev->tx_encap_type = val;
  1947. }
  1948. /*
  1949. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  1950. * @vdev_handle: virtual device object
  1951. * @htt_pkt_type: type of pkt
  1952. *
  1953. * Return: void
  1954. */
  1955. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  1956. enum htt_cmn_pkt_type val)
  1957. {
  1958. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  1959. vdev->rx_decap_type = val;
  1960. }
  1961. /*
  1962. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  1963. * @pdev_handle: physical device object
  1964. * @val: reo destination ring index (1 - 4)
  1965. *
  1966. * Return: void
  1967. */
  1968. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  1969. enum cdp_host_reo_dest_ring val)
  1970. {
  1971. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  1972. if (pdev)
  1973. pdev->reo_dest = val;
  1974. }
  1975. /*
  1976. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  1977. * @pdev_handle: physical device object
  1978. *
  1979. * Return: reo destination ring index
  1980. */
  1981. static enum cdp_host_reo_dest_ring
  1982. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  1983. {
  1984. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  1985. if (pdev)
  1986. return pdev->reo_dest;
  1987. else
  1988. return cdp_host_reo_dest_ring_unknown;
  1989. }
  1990. #ifdef QCA_SUPPORT_SON
  1991. static void dp_son_peer_authorize(struct dp_peer *peer)
  1992. {
  1993. struct dp_soc *soc;
  1994. soc = peer->vdev->pdev->soc;
  1995. peer->peer_bs_inact_flag = 0;
  1996. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  1997. return;
  1998. }
  1999. #else
  2000. static void dp_son_peer_authorize(struct dp_peer *peer)
  2001. {
  2002. return;
  2003. }
  2004. #endif
  2005. /*
  2006. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2007. * @pdev_handle: device object
  2008. * @val: value to be set
  2009. *
  2010. * Return: void
  2011. */
  2012. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2013. uint32_t val)
  2014. {
  2015. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2016. /* Enable/Disable smart mesh filtering. This flag will be checked
  2017. * during rx processing to check if packets are from NAC clients.
  2018. */
  2019. pdev->filter_neighbour_peers = val;
  2020. return 0;
  2021. }
  2022. /*
  2023. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2024. * address for smart mesh filtering
  2025. * @pdev_handle: device object
  2026. * @cmd: Add/Del command
  2027. * @macaddr: nac client mac address
  2028. *
  2029. * Return: void
  2030. */
  2031. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2032. uint32_t cmd, uint8_t *macaddr)
  2033. {
  2034. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2035. struct dp_neighbour_peer *peer = NULL;
  2036. if (!macaddr)
  2037. goto fail0;
  2038. /* Store address of NAC (neighbour peer) which will be checked
  2039. * against TA of received packets.
  2040. */
  2041. if (cmd == DP_NAC_PARAM_ADD) {
  2042. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2043. sizeof(*peer));
  2044. if (!peer) {
  2045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2046. FL("DP neighbour peer node memory allocation failed"));
  2047. goto fail0;
  2048. }
  2049. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2050. macaddr, DP_MAC_ADDR_LEN);
  2051. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2052. /* add this neighbour peer into the list */
  2053. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2054. neighbour_peer_list_elem);
  2055. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2056. return 1;
  2057. } else if (cmd == DP_NAC_PARAM_DEL) {
  2058. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2059. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2060. neighbour_peer_list_elem) {
  2061. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2062. macaddr, DP_MAC_ADDR_LEN)) {
  2063. /* delete this peer from the list */
  2064. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2065. peer, neighbour_peer_list_elem);
  2066. qdf_mem_free(peer);
  2067. break;
  2068. }
  2069. }
  2070. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2071. return 1;
  2072. }
  2073. fail0:
  2074. return 0;
  2075. }
  2076. /*
  2077. * dp_peer_authorize() - authorize txrx peer
  2078. * @peer_handle: Datapath peer handle
  2079. * @authorize
  2080. *
  2081. */
  2082. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2083. {
  2084. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2085. struct dp_soc *soc;
  2086. if (peer != NULL) {
  2087. soc = peer->vdev->pdev->soc;
  2088. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2089. dp_son_peer_authorize(peer);
  2090. peer->authorize = authorize ? 1 : 0;
  2091. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2092. }
  2093. }
  2094. /*
  2095. * dp_peer_unref_delete() - unref and delete peer
  2096. * @peer_handle: Datapath peer handle
  2097. *
  2098. */
  2099. void dp_peer_unref_delete(void *peer_handle)
  2100. {
  2101. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2102. struct dp_vdev *vdev = peer->vdev;
  2103. struct dp_pdev *pdev = vdev->pdev;
  2104. struct dp_soc *soc = pdev->soc;
  2105. struct dp_peer *tmppeer;
  2106. int found = 0;
  2107. uint16_t peer_id;
  2108. /*
  2109. * Hold the lock all the way from checking if the peer ref count
  2110. * is zero until the peer references are removed from the hash
  2111. * table and vdev list (if the peer ref count is zero).
  2112. * This protects against a new HL tx operation starting to use the
  2113. * peer object just after this function concludes it's done being used.
  2114. * Furthermore, the lock needs to be held while checking whether the
  2115. * vdev's list of peers is empty, to make sure that list is not modified
  2116. * concurrently with the empty check.
  2117. */
  2118. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2119. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2120. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  2121. peer, qdf_atomic_read(&peer->ref_cnt));
  2122. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2123. peer_id = peer->peer_ids[0];
  2124. /*
  2125. * Make sure that the reference to the peer in
  2126. * peer object map is removed
  2127. */
  2128. if (peer_id != HTT_INVALID_PEER)
  2129. soc->peer_id_to_obj_map[peer_id] = NULL;
  2130. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2131. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  2132. /* remove the reference to the peer from the hash table */
  2133. dp_peer_find_hash_remove(soc, peer);
  2134. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2135. if (tmppeer == peer) {
  2136. found = 1;
  2137. break;
  2138. }
  2139. }
  2140. if (found) {
  2141. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2142. peer_list_elem);
  2143. } else {
  2144. /*Ignoring the remove operation as peer not found*/
  2145. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2146. "peer %p not found in vdev (%p)->peer_list:%p",
  2147. peer, vdev, &peer->vdev->peer_list);
  2148. }
  2149. /* cleanup the peer data */
  2150. dp_peer_cleanup(vdev, peer);
  2151. /* check whether the parent vdev has no peers left */
  2152. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2153. /*
  2154. * Now that there are no references to the peer, we can
  2155. * release the peer reference lock.
  2156. */
  2157. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2158. /*
  2159. * Check if the parent vdev was waiting for its peers
  2160. * to be deleted, in order for it to be deleted too.
  2161. */
  2162. if (vdev->delete.pending) {
  2163. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2164. vdev->delete.callback;
  2165. void *vdev_delete_context =
  2166. vdev->delete.context;
  2167. QDF_TRACE(QDF_MODULE_ID_DP,
  2168. QDF_TRACE_LEVEL_INFO_HIGH,
  2169. FL("deleting vdev object %p (%pM)"
  2170. " - its last peer is done"),
  2171. vdev, vdev->mac_addr.raw);
  2172. /* all peers are gone, go ahead and delete it */
  2173. qdf_mem_free(vdev);
  2174. if (vdev_delete_cb)
  2175. vdev_delete_cb(vdev_delete_context);
  2176. }
  2177. } else {
  2178. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2179. }
  2180. #ifdef notyet
  2181. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2182. #else
  2183. qdf_mem_free(peer);
  2184. #endif
  2185. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2186. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2187. vdev->vdev_id, peer->mac_addr.raw);
  2188. }
  2189. } else {
  2190. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2191. }
  2192. }
  2193. /*
  2194. * dp_peer_detach_wifi3() – Detach txrx peer
  2195. * @peer_handle: Datapath peer handle
  2196. *
  2197. */
  2198. static void dp_peer_delete_wifi3(void *peer_handle)
  2199. {
  2200. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2201. /* redirect the peer's rx delivery function to point to a
  2202. * discard func
  2203. */
  2204. peer->rx_opt_proc = dp_rx_discard;
  2205. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2206. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  2207. #ifndef CONFIG_WIN
  2208. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2209. #endif
  2210. qdf_spinlock_destroy(&peer->peer_info_lock);
  2211. /*
  2212. * Remove the reference added during peer_attach.
  2213. * The peer will still be left allocated until the
  2214. * PEER_UNMAP message arrives to remove the other
  2215. * reference, added by the PEER_MAP message.
  2216. */
  2217. dp_peer_unref_delete(peer_handle);
  2218. }
  2219. /*
  2220. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2221. * @peer_handle: Datapath peer handle
  2222. *
  2223. */
  2224. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2225. {
  2226. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2227. return vdev->mac_addr.raw;
  2228. }
  2229. /*
  2230. * dp_vdev_set_wds() - Enable per packet stats
  2231. * @vdev_handle: DP VDEV handle
  2232. * @val: value
  2233. *
  2234. * Return: none
  2235. */
  2236. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2237. {
  2238. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2239. vdev->wds_enabled = val;
  2240. return 0;
  2241. }
  2242. /*
  2243. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2244. * @peer_handle: Datapath peer handle
  2245. *
  2246. */
  2247. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2248. uint8_t vdev_id)
  2249. {
  2250. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2251. struct dp_vdev *vdev = NULL;
  2252. if (qdf_unlikely(!pdev))
  2253. return NULL;
  2254. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2255. if (vdev->vdev_id == vdev_id)
  2256. break;
  2257. }
  2258. return (struct cdp_vdev *)vdev;
  2259. }
  2260. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2261. {
  2262. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2263. return vdev->opmode;
  2264. }
  2265. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2266. {
  2267. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2268. struct dp_pdev *pdev = vdev->pdev;
  2269. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2270. }
  2271. /**
  2272. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2273. * @vdev_handle: Datapath VDEV handle
  2274. * @smart_monitor: Flag to denote if its smart monitor mode
  2275. *
  2276. * Return: 0 on success, not 0 on failure
  2277. */
  2278. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2279. uint8_t smart_monitor)
  2280. {
  2281. /* Many monitor VAPs can exists in a system but only one can be up at
  2282. * anytime
  2283. */
  2284. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2285. struct dp_pdev *pdev;
  2286. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2287. struct dp_soc *soc;
  2288. uint8_t pdev_id;
  2289. qdf_assert(vdev);
  2290. pdev = vdev->pdev;
  2291. pdev_id = pdev->pdev_id;
  2292. soc = pdev->soc;
  2293. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2294. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  2295. pdev, pdev_id, soc, vdev);
  2296. /*Check if current pdev's monitor_vdev exists */
  2297. if (pdev->monitor_vdev) {
  2298. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2299. "vdev=%p\n", vdev);
  2300. qdf_assert(vdev);
  2301. }
  2302. pdev->monitor_vdev = vdev;
  2303. /* If smart monitor mode, do not configure monitor ring */
  2304. if (smart_monitor)
  2305. return QDF_STATUS_SUCCESS;
  2306. htt_tlv_filter.mpdu_start = 1;
  2307. htt_tlv_filter.msdu_start = 1;
  2308. htt_tlv_filter.packet = 1;
  2309. htt_tlv_filter.msdu_end = 1;
  2310. htt_tlv_filter.mpdu_end = 1;
  2311. htt_tlv_filter.packet_header = 1;
  2312. htt_tlv_filter.attention = 1;
  2313. htt_tlv_filter.ppdu_start = 0;
  2314. htt_tlv_filter.ppdu_end = 0;
  2315. htt_tlv_filter.ppdu_end_user_stats = 0;
  2316. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  2317. htt_tlv_filter.ppdu_end_status_done = 0;
  2318. htt_tlv_filter.enable_fp = 1;
  2319. htt_tlv_filter.enable_md = 0;
  2320. htt_tlv_filter.enable_mo = 1;
  2321. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2322. pdev->rxdma_mon_buf_ring.hal_srng,
  2323. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2324. htt_tlv_filter.mpdu_start = 1;
  2325. htt_tlv_filter.msdu_start = 1;
  2326. htt_tlv_filter.packet = 0;
  2327. htt_tlv_filter.msdu_end = 1;
  2328. htt_tlv_filter.mpdu_end = 1;
  2329. htt_tlv_filter.packet_header = 1;
  2330. htt_tlv_filter.attention = 1;
  2331. htt_tlv_filter.ppdu_start = 1;
  2332. htt_tlv_filter.ppdu_end = 1;
  2333. htt_tlv_filter.ppdu_end_user_stats = 1;
  2334. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  2335. htt_tlv_filter.ppdu_end_status_done = 1;
  2336. htt_tlv_filter.enable_fp = 1;
  2337. htt_tlv_filter.enable_md = 0;
  2338. htt_tlv_filter.enable_mo = 1;
  2339. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2340. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2341. RX_BUFFER_SIZE, &htt_tlv_filter);
  2342. return QDF_STATUS_SUCCESS;
  2343. }
  2344. #ifdef MESH_MODE_SUPPORT
  2345. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  2346. {
  2347. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2349. FL("val %d"), val);
  2350. vdev->mesh_vdev = val;
  2351. }
  2352. /*
  2353. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  2354. * @vdev_hdl: virtual device object
  2355. * @val: value to be set
  2356. *
  2357. * Return: void
  2358. */
  2359. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  2360. {
  2361. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2363. FL("val %d"), val);
  2364. vdev->mesh_rx_filter = val;
  2365. }
  2366. #endif
  2367. /**
  2368. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  2369. * @vdev: DP VDEV handle
  2370. *
  2371. * return: void
  2372. */
  2373. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  2374. {
  2375. struct dp_peer *peer = NULL;
  2376. int i;
  2377. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  2378. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  2379. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2380. if (!peer)
  2381. return;
  2382. for (i = 0; i <= MAX_MCS; i++) {
  2383. DP_STATS_AGGR(vdev, peer, tx.pkt_type[0].mcs_count[i]);
  2384. DP_STATS_AGGR(vdev, peer, tx.pkt_type[1].mcs_count[i]);
  2385. DP_STATS_AGGR(vdev, peer, tx.pkt_type[2].mcs_count[i]);
  2386. DP_STATS_AGGR(vdev, peer, tx.pkt_type[3].mcs_count[i]);
  2387. DP_STATS_AGGR(vdev, peer, tx.pkt_type[4].mcs_count[i]);
  2388. DP_STATS_AGGR(vdev, peer, rx.pkt_type[0].mcs_count[i]);
  2389. DP_STATS_AGGR(vdev, peer, rx.pkt_type[1].mcs_count[i]);
  2390. DP_STATS_AGGR(vdev, peer, rx.pkt_type[2].mcs_count[i]);
  2391. DP_STATS_AGGR(vdev, peer, rx.pkt_type[3].mcs_count[i]);
  2392. DP_STATS_AGGR(vdev, peer, rx.pkt_type[4].mcs_count[i]);
  2393. }
  2394. for (i = 0; i < SUPPORTED_BW; i++) {
  2395. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  2396. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  2397. }
  2398. for (i = 0; i < SS_COUNT; i++)
  2399. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  2400. for (i = 0; i < WME_AC_MAX; i++) {
  2401. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  2402. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  2403. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  2404. }
  2405. for (i = 0; i < MAX_MCS + 1; i++) {
  2406. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  2407. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  2408. }
  2409. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  2410. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  2411. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  2412. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  2413. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  2414. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  2415. DP_STATS_AGGR(vdev, peer, tx.stbc);
  2416. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  2417. DP_STATS_AGGR(vdev, peer, tx.retries);
  2418. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  2419. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  2420. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard);
  2421. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_retired);
  2422. DP_STATS_AGGR(vdev, peer, tx.dropped.mpdu_age_out);
  2423. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason1);
  2424. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason2);
  2425. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason3);
  2426. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  2427. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  2428. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  2429. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  2430. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  2431. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  2432. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  2433. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  2434. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  2435. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  2436. peer->stats.rx.multicast.num;
  2437. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  2438. peer->stats.rx.multicast.bytes;
  2439. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  2440. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  2441. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  2442. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  2443. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  2444. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  2445. vdev->stats.tx.last_ack_rssi =
  2446. peer->stats.tx.last_ack_rssi;
  2447. }
  2448. }
  2449. /**
  2450. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  2451. * @pdev: DP PDEV handle
  2452. *
  2453. * return: void
  2454. */
  2455. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  2456. {
  2457. struct dp_vdev *vdev = NULL;
  2458. uint8_t i;
  2459. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  2460. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  2461. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  2462. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2463. if (!vdev)
  2464. return;
  2465. dp_aggregate_vdev_stats(vdev);
  2466. for (i = 0; i <= MAX_MCS; i++) {
  2467. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[0].mcs_count[i]);
  2468. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[1].mcs_count[i]);
  2469. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[2].mcs_count[i]);
  2470. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[3].mcs_count[i]);
  2471. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[4].mcs_count[i]);
  2472. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[0].mcs_count[i]);
  2473. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[1].mcs_count[i]);
  2474. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[2].mcs_count[i]);
  2475. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[3].mcs_count[i]);
  2476. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[4].mcs_count[i]);
  2477. }
  2478. for (i = 0; i < SUPPORTED_BW; i++) {
  2479. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  2480. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  2481. }
  2482. for (i = 0; i < SS_COUNT; i++)
  2483. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  2484. for (i = 0; i < WME_AC_MAX; i++) {
  2485. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  2486. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  2487. DP_STATS_AGGR(pdev, vdev,
  2488. tx.excess_retries_ac[i]);
  2489. }
  2490. for (i = 0; i < MAX_MCS + 1; i++) {
  2491. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  2492. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  2493. }
  2494. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  2495. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  2496. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  2497. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  2498. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  2499. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  2500. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  2501. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  2502. DP_STATS_AGGR(pdev, vdev, tx.retries);
  2503. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  2504. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  2505. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_discard);
  2506. DP_STATS_AGGR(pdev, vdev,
  2507. tx.dropped.fw_discard_retired);
  2508. DP_STATS_AGGR(pdev, vdev, tx.dropped.mpdu_age_out);
  2509. DP_STATS_AGGR(pdev, vdev,
  2510. tx.dropped.fw_discard_reason1);
  2511. DP_STATS_AGGR(pdev, vdev,
  2512. tx.dropped.fw_discard_reason2);
  2513. DP_STATS_AGGR(pdev, vdev,
  2514. tx.dropped.fw_discard_reason3);
  2515. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  2516. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  2517. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  2518. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  2519. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  2520. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  2521. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  2522. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  2523. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  2524. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  2525. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  2526. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  2527. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  2528. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  2529. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  2530. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  2531. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  2532. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  2533. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  2534. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  2535. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  2536. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  2537. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  2538. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  2539. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  2540. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  2541. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  2542. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  2543. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  2544. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  2545. DP_STATS_AGGR(pdev, vdev,
  2546. tx_i.mcast_en.dropped_map_error);
  2547. DP_STATS_AGGR(pdev, vdev,
  2548. tx_i.mcast_en.dropped_self_mac);
  2549. DP_STATS_AGGR(pdev, vdev,
  2550. tx_i.mcast_en.dropped_send_fail);
  2551. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  2552. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  2553. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  2554. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  2555. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  2556. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  2557. pdev->stats.tx_i.dropped.dropped_pkt.num =
  2558. pdev->stats.tx_i.dropped.dma_error +
  2559. pdev->stats.tx_i.dropped.ring_full +
  2560. pdev->stats.tx_i.dropped.enqueue_fail +
  2561. pdev->stats.tx_i.dropped.desc_na +
  2562. pdev->stats.tx_i.dropped.res_full;
  2563. pdev->stats.tx.last_ack_rssi =
  2564. vdev->stats.tx.last_ack_rssi;
  2565. pdev->stats.tx_i.tso.num_seg =
  2566. vdev->stats.tx_i.tso.num_seg;
  2567. }
  2568. }
  2569. /**
  2570. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  2571. * @pdev: DP_PDEV Handle
  2572. *
  2573. * Return:void
  2574. */
  2575. static inline void
  2576. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  2577. {
  2578. DP_TRACE_STATS(FATAL, "WLAN Tx Stats:\n");
  2579. DP_TRACE_STATS(FATAL, "Received From Stack:\n");
  2580. DP_TRACE_STATS(FATAL, "Packets = %d",
  2581. pdev->stats.tx_i.rcvd.num);
  2582. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2583. pdev->stats.tx_i.rcvd.bytes);
  2584. DP_TRACE_STATS(FATAL, "Processed:\n");
  2585. DP_TRACE_STATS(FATAL, "Packets = %d",
  2586. pdev->stats.tx_i.processed.num);
  2587. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2588. pdev->stats.tx_i.processed.bytes);
  2589. DP_TRACE_STATS(FATAL, "Completions:\n");
  2590. DP_TRACE_STATS(FATAL, "Packets = %d",
  2591. pdev->stats.tx.comp_pkt.num);
  2592. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2593. pdev->stats.tx.comp_pkt.bytes);
  2594. DP_TRACE_STATS(FATAL, "Dropped:\n");
  2595. DP_TRACE_STATS(FATAL, "Packets = %d",
  2596. pdev->stats.tx_i.dropped.dropped_pkt.num);
  2597. DP_TRACE_STATS(FATAL, "Dma_map_error = %d",
  2598. pdev->stats.tx_i.dropped.dma_error);
  2599. DP_TRACE_STATS(FATAL, "Ring Full = %d",
  2600. pdev->stats.tx_i.dropped.ring_full);
  2601. DP_TRACE_STATS(FATAL, "Descriptor Not available = %d",
  2602. pdev->stats.tx_i.dropped.desc_na);
  2603. DP_TRACE_STATS(FATAL, "HW enqueue failed= %d",
  2604. pdev->stats.tx_i.dropped.enqueue_fail);
  2605. DP_TRACE_STATS(FATAL, "Resources Full = %d",
  2606. pdev->stats.tx_i.dropped.res_full);
  2607. DP_TRACE_STATS(FATAL, "Fw Discard = %d",
  2608. pdev->stats.tx.dropped.fw_discard);
  2609. DP_TRACE_STATS(FATAL, "Fw Discard Retired = %d",
  2610. pdev->stats.tx.dropped.fw_discard_retired);
  2611. DP_TRACE_STATS(FATAL, "Firmware Discard Untransmitted = %d",
  2612. pdev->stats.tx.dropped.fw_discard_untransmitted);
  2613. DP_TRACE_STATS(FATAL, "Mpdu Age Out = %d",
  2614. pdev->stats.tx.dropped.mpdu_age_out);
  2615. DP_TRACE_STATS(FATAL, "Firmware Discard Reason1 = %d",
  2616. pdev->stats.tx.dropped.fw_discard_reason1);
  2617. DP_TRACE_STATS(FATAL, "Firmware Discard Reason2 = %d",
  2618. pdev->stats.tx.dropped.fw_discard_reason2);
  2619. DP_TRACE_STATS(FATAL, "Firmware Discard Reason3 = %d\n",
  2620. pdev->stats.tx.dropped.fw_discard_reason3);
  2621. DP_TRACE_STATS(FATAL, "Scatter Gather:\n");
  2622. DP_TRACE_STATS(FATAL, "Packets = %d",
  2623. pdev->stats.tx_i.sg.sg_pkt.num);
  2624. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2625. pdev->stats.tx_i.sg.sg_pkt.bytes);
  2626. DP_TRACE_STATS(FATAL, "Dropped By Host = %d",
  2627. pdev->stats.tx_i.sg.dropped_host);
  2628. DP_TRACE_STATS(FATAL, "Dropped By Target = %d\n",
  2629. pdev->stats.tx_i.sg.dropped_target);
  2630. DP_TRACE_STATS(FATAL, "Tso:\n");
  2631. DP_TRACE_STATS(FATAL, "Number of Segments = %d",
  2632. pdev->stats.tx_i.tso.num_seg);
  2633. DP_TRACE_STATS(FATAL, "Packets = %d",
  2634. pdev->stats.tx_i.tso.tso_pkt.num);
  2635. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2636. pdev->stats.tx_i.tso.tso_pkt.bytes);
  2637. DP_TRACE_STATS(FATAL, "Dropped By Host = %d\n",
  2638. pdev->stats.tx_i.tso.dropped_host);
  2639. DP_TRACE_STATS(FATAL, "Mcast Enhancement:\n");
  2640. DP_TRACE_STATS(FATAL, "Packets = %d",
  2641. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  2642. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2643. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  2644. DP_TRACE_STATS(FATAL, "Dropped: Map Errors = %d",
  2645. pdev->stats.tx_i.mcast_en.dropped_map_error);
  2646. DP_TRACE_STATS(FATAL, "Dropped: Self Mac = %d",
  2647. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  2648. DP_TRACE_STATS(FATAL, "Dropped: Send Fail = %d",
  2649. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  2650. DP_TRACE_STATS(FATAL, "Unicast sent = %d\n",
  2651. pdev->stats.tx_i.mcast_en.ucast);
  2652. DP_TRACE_STATS(FATAL, "Raw:\n");
  2653. DP_TRACE_STATS(FATAL, "Packets = %d",
  2654. pdev->stats.tx_i.raw.raw_pkt.num);
  2655. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2656. pdev->stats.tx_i.raw.raw_pkt.bytes);
  2657. DP_TRACE_STATS(FATAL, "DMA map error = %d\n",
  2658. pdev->stats.tx_i.raw.dma_map_error);
  2659. DP_TRACE_STATS(FATAL, "Reinjected:\n");
  2660. DP_TRACE_STATS(FATAL, "Packets = %d",
  2661. pdev->stats.tx_i.reinject_pkts.num);
  2662. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2663. pdev->stats.tx_i.reinject_pkts.bytes);
  2664. DP_TRACE_STATS(FATAL, "Inspected:\n");
  2665. DP_TRACE_STATS(FATAL, "Packets = %d",
  2666. pdev->stats.tx_i.inspect_pkts.num);
  2667. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2668. pdev->stats.tx_i.inspect_pkts.bytes);
  2669. }
  2670. /**
  2671. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  2672. * @pdev: DP_PDEV Handle
  2673. *
  2674. * Return: void
  2675. */
  2676. static inline void
  2677. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  2678. {
  2679. DP_TRACE_STATS(FATAL, "WLAN Rx Stats:\n");
  2680. DP_TRACE_STATS(FATAL, "Received From HW (Per Rx Ring):\n");
  2681. DP_TRACE_STATS(FATAL, "Packets = %d %d %d %d",
  2682. pdev->stats.rx.rcvd_reo[0].num,
  2683. pdev->stats.rx.rcvd_reo[1].num,
  2684. pdev->stats.rx.rcvd_reo[2].num,
  2685. pdev->stats.rx.rcvd_reo[3].num);
  2686. DP_TRACE_STATS(FATAL, "Bytes = %d %d %d %d\n",
  2687. pdev->stats.rx.rcvd_reo[0].bytes,
  2688. pdev->stats.rx.rcvd_reo[1].bytes,
  2689. pdev->stats.rx.rcvd_reo[2].bytes,
  2690. pdev->stats.rx.rcvd_reo[3].bytes);
  2691. DP_TRACE_STATS(FATAL, "Replenished:\n");
  2692. DP_TRACE_STATS(FATAL, "Packets = %d",
  2693. pdev->stats.replenish.pkts.num);
  2694. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2695. pdev->stats.replenish.pkts.bytes);
  2696. DP_TRACE_STATS(FATAL, "Buffers Added To Freelist = %d\n",
  2697. pdev->stats.buf_freelist);
  2698. DP_TRACE_STATS(FATAL, "Dropped:\n");
  2699. DP_TRACE_STATS(FATAL, "Total Packets With Msdu Not Done = %d\n",
  2700. pdev->stats.dropped.msdu_not_done);
  2701. DP_TRACE_STATS(FATAL, "Sent To Stack:\n");
  2702. DP_TRACE_STATS(FATAL, "Packets = %d",
  2703. pdev->stats.rx.to_stack.num);
  2704. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2705. pdev->stats.rx.to_stack.bytes);
  2706. DP_TRACE_STATS(FATAL, "Multicast/Broadcast:\n");
  2707. DP_TRACE_STATS(FATAL, "Packets = %d",
  2708. pdev->stats.rx.multicast.num);
  2709. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  2710. pdev->stats.rx.multicast.bytes);
  2711. DP_TRACE_STATS(FATAL, "Errors:\n");
  2712. DP_TRACE_STATS(FATAL, "Rxdma Ring Un-inititalized = %d",
  2713. pdev->stats.replenish.rxdma_err);
  2714. DP_TRACE_STATS(FATAL, "Desc Alloc Failed: = %d",
  2715. pdev->stats.err.desc_alloc_fail);
  2716. }
  2717. /**
  2718. * dp_print_soc_tx_stats(): Print SOC level stats
  2719. * @soc DP_SOC Handle
  2720. *
  2721. * Return: void
  2722. */
  2723. static inline void
  2724. dp_print_soc_tx_stats(struct dp_soc *soc)
  2725. {
  2726. DP_TRACE_STATS(FATAL, "SOC Tx Stats:\n");
  2727. DP_TRACE_STATS(FATAL, "Tx Descriptors In Use = %d",
  2728. soc->stats.tx.desc_in_use);
  2729. DP_TRACE_STATS(FATAL, "Invalid peer:\n");
  2730. DP_TRACE_STATS(FATAL, "Packets = %d",
  2731. soc->stats.tx.tx_invalid_peer.num);
  2732. DP_TRACE_STATS(FATAL, "Bytes = %d",
  2733. soc->stats.tx.tx_invalid_peer.bytes);
  2734. DP_TRACE_STATS(FATAL, "Packets dropped due to TCL ring full = %d %d %d",
  2735. soc->stats.tx.tcl_ring_full[0],
  2736. soc->stats.tx.tcl_ring_full[1],
  2737. soc->stats.tx.tcl_ring_full[2]);
  2738. }
  2739. /**
  2740. * dp_print_soc_rx_stats: Print SOC level Rx stats
  2741. * @soc: DP_SOC Handle
  2742. *
  2743. * Return:void
  2744. */
  2745. static inline void
  2746. dp_print_soc_rx_stats(struct dp_soc *soc)
  2747. {
  2748. uint32_t i;
  2749. char reo_error[DP_REO_ERR_LENGTH];
  2750. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  2751. uint8_t index = 0;
  2752. DP_TRACE_STATS(FATAL, "SOC Rx Stats:\n");
  2753. DP_TRACE_STATS(FATAL, "Errors:\n");
  2754. DP_TRACE_STATS(FATAL, "Rx Decrypt Errors = %d",
  2755. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  2756. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  2757. DP_TRACE_STATS(FATAL, "Invalid RBM = %d",
  2758. soc->stats.rx.err.invalid_rbm);
  2759. DP_TRACE_STATS(FATAL, "Invalid Vdev = %d",
  2760. soc->stats.rx.err.invalid_vdev);
  2761. DP_TRACE_STATS(FATAL, "Invalid Pdev = %d",
  2762. soc->stats.rx.err.invalid_pdev);
  2763. DP_TRACE_STATS(FATAL, "Invalid Peer = %d",
  2764. soc->stats.rx.err.rx_invalid_peer.num);
  2765. DP_TRACE_STATS(FATAL, "HAL Ring Access Fail = %d",
  2766. soc->stats.rx.err.hal_ring_access_fail);
  2767. for (i = 0; i < MAX_RXDMA_ERRORS; i++) {
  2768. index += qdf_snprint(&rxdma_error[index],
  2769. DP_RXDMA_ERR_LENGTH - index,
  2770. " %d", soc->stats.rx.err.rxdma_error[i]);
  2771. }
  2772. DP_TRACE_STATS(FATAL, "RXDMA Error (0-31):%s",
  2773. rxdma_error);
  2774. index = 0;
  2775. for (i = 0; i < REO_ERROR_TYPE_MAX; i++) {
  2776. index += qdf_snprint(&reo_error[index],
  2777. DP_REO_ERR_LENGTH - index,
  2778. " %d", soc->stats.rx.err.reo_error[i]);
  2779. }
  2780. DP_TRACE_STATS(FATAL, "REO Error(0-14):%s",
  2781. reo_error);
  2782. }
  2783. /**
  2784. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  2785. * @vdev: DP_VDEV handle
  2786. *
  2787. * Return:void
  2788. */
  2789. static inline void
  2790. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  2791. {
  2792. struct dp_peer *peer = NULL;
  2793. DP_STATS_CLR(vdev->pdev);
  2794. DP_STATS_CLR(vdev->pdev->soc);
  2795. DP_STATS_CLR(vdev);
  2796. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2797. if (!peer)
  2798. return;
  2799. DP_STATS_CLR(peer);
  2800. }
  2801. }
  2802. /**
  2803. * dp_print_rx_rates(): Print Rx rate stats
  2804. * @vdev: DP_VDEV handle
  2805. *
  2806. * Return:void
  2807. */
  2808. static inline void
  2809. dp_print_rx_rates(struct dp_vdev *vdev)
  2810. {
  2811. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  2812. uint8_t i, pkt_type;
  2813. uint8_t index = 0;
  2814. char rx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  2815. char nss[DP_NSS_LENGTH];
  2816. DP_TRACE_STATS(FATAL, "Rx Rate Info:\n");
  2817. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  2818. index = 0;
  2819. for (i = 0; i < MAX_MCS; i++) {
  2820. index += qdf_snprint(&rx_mcs[pkt_type][index],
  2821. DP_MCS_LENGTH - index,
  2822. " %d ",
  2823. pdev->stats.rx.pkt_type[pkt_type].
  2824. mcs_count[i]);
  2825. }
  2826. }
  2827. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  2828. rx_mcs[0]);
  2829. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  2830. pdev->stats.rx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  2831. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  2832. rx_mcs[1]);
  2833. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  2834. pdev->stats.rx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  2835. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  2836. rx_mcs[2]);
  2837. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  2838. pdev->stats.rx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  2839. DP_TRACE_STATS(FATAL, "Type 11AC MCS(0-9) = %s",
  2840. rx_mcs[3]);
  2841. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  2842. pdev->stats.rx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  2843. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  2844. rx_mcs[4]);
  2845. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  2846. pdev->stats.rx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  2847. index = 0;
  2848. for (i = 0; i < SS_COUNT; i++) {
  2849. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  2850. " %d", pdev->stats.rx.nss[i]);
  2851. }
  2852. DP_TRACE_STATS(FATAL, "NSS(0-7) = %s",
  2853. nss);
  2854. DP_TRACE_STATS(FATAL, "SGI ="
  2855. " 0.8us %d,"
  2856. " 0.4us %d,"
  2857. " 1.6us %d,"
  2858. " 3.2us %d,",
  2859. pdev->stats.rx.sgi_count[0],
  2860. pdev->stats.rx.sgi_count[1],
  2861. pdev->stats.rx.sgi_count[2],
  2862. pdev->stats.rx.sgi_count[3]);
  2863. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  2864. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  2865. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  2866. DP_TRACE_STATS(FATAL, "Reception Type ="
  2867. " SU: %d,"
  2868. " MU_MIMO:%d,"
  2869. " MU_OFDMA:%d,"
  2870. " MU_OFDMA_MIMO:%d\n",
  2871. pdev->stats.rx.reception_type[0],
  2872. pdev->stats.rx.reception_type[1],
  2873. pdev->stats.rx.reception_type[2],
  2874. pdev->stats.rx.reception_type[3]);
  2875. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  2876. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Ampdus = %d",
  2877. pdev->stats.rx.ampdu_cnt);
  2878. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Mpdu Level Aggregation : %d",
  2879. pdev->stats.rx.non_ampdu_cnt);
  2880. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu: %d",
  2881. pdev->stats.rx.amsdu_cnt);
  2882. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation: %d",
  2883. pdev->stats.rx.non_amsdu_cnt);
  2884. }
  2885. /**
  2886. * dp_print_tx_rates(): Print tx rates
  2887. * @vdev: DP_VDEV handle
  2888. *
  2889. * Return:void
  2890. */
  2891. static inline void
  2892. dp_print_tx_rates(struct dp_vdev *vdev)
  2893. {
  2894. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  2895. uint8_t i, pkt_type;
  2896. char mcs[DOT11_MAX][DP_MCS_LENGTH];
  2897. uint32_t index;
  2898. DP_TRACE_STATS(FATAL, "Tx Rate Info:\n");
  2899. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  2900. index = 0;
  2901. for (i = 0; i < MAX_MCS; i++) {
  2902. index += qdf_snprint(&mcs[pkt_type][index],
  2903. DP_MCS_LENGTH - index,
  2904. " %d ",
  2905. pdev->stats.tx.pkt_type[pkt_type].
  2906. mcs_count[i]);
  2907. }
  2908. }
  2909. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  2910. mcs[0]);
  2911. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  2912. pdev->stats.tx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  2913. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  2914. mcs[1]);
  2915. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  2916. pdev->stats.tx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  2917. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  2918. mcs[2]);
  2919. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  2920. pdev->stats.tx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  2921. DP_TRACE_STATS(FATAL, "Type 11AC MCS(0-9) = %s",
  2922. mcs[3]);
  2923. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  2924. pdev->stats.tx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  2925. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  2926. mcs[4]);
  2927. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  2928. pdev->stats.tx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  2929. DP_TRACE_STATS(FATAL, "SGI ="
  2930. " 0.8us %d"
  2931. " 0.4us %d"
  2932. " 1.6us %d"
  2933. " 3.2us %d",
  2934. pdev->stats.tx.sgi_count[0],
  2935. pdev->stats.tx.sgi_count[1],
  2936. pdev->stats.tx.sgi_count[2],
  2937. pdev->stats.tx.sgi_count[3]);
  2938. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  2939. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  2940. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  2941. DP_TRACE_STATS(FATAL, "OFDMA = %d", pdev->stats.tx.ofdma);
  2942. DP_TRACE_STATS(FATAL, "STBC = %d", pdev->stats.tx.stbc);
  2943. DP_TRACE_STATS(FATAL, "LDPC = %d", pdev->stats.tx.ldpc);
  2944. DP_TRACE_STATS(FATAL, "Retries = %d", pdev->stats.tx.retries);
  2945. DP_TRACE_STATS(FATAL, "Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  2946. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  2947. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  2948. pdev->stats.tx.amsdu_cnt);
  2949. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d",
  2950. pdev->stats.tx.non_amsdu_cnt);
  2951. }
  2952. /**
  2953. * dp_print_peer_stats():print peer stats
  2954. * @peer: DP_PEER handle
  2955. *
  2956. * return void
  2957. */
  2958. static inline void dp_print_peer_stats(struct dp_peer *peer)
  2959. {
  2960. uint8_t i, pkt_type;
  2961. char tx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  2962. char rx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  2963. uint32_t index;
  2964. char nss[DP_NSS_LENGTH];
  2965. DP_TRACE_STATS(FATAL, "Node Tx Stats:\n");
  2966. DP_TRACE_STATS(FATAL, "Total Packet Completions = %d",
  2967. peer->stats.tx.comp_pkt.num);
  2968. DP_TRACE_STATS(FATAL, "Total Bytes Completions = %d",
  2969. peer->stats.tx.comp_pkt.bytes);
  2970. DP_TRACE_STATS(FATAL, "Success Packets = %d",
  2971. peer->stats.tx.tx_success.num);
  2972. DP_TRACE_STATS(FATAL, "Success Bytes = %d",
  2973. peer->stats.tx.tx_success.bytes);
  2974. DP_TRACE_STATS(FATAL, "Packets Failed = %d",
  2975. peer->stats.tx.tx_failed);
  2976. DP_TRACE_STATS(FATAL, "Packets In OFDMA = %d",
  2977. peer->stats.tx.ofdma);
  2978. DP_TRACE_STATS(FATAL, "Packets In STBC = %d",
  2979. peer->stats.tx.stbc);
  2980. DP_TRACE_STATS(FATAL, "Packets In LDPC = %d",
  2981. peer->stats.tx.ldpc);
  2982. DP_TRACE_STATS(FATAL, "Packet Retries = %d",
  2983. peer->stats.tx.retries);
  2984. DP_TRACE_STATS(FATAL, "Msdu's Not Part of Ampdu = %d",
  2985. peer->stats.tx.non_amsdu_cnt);
  2986. DP_TRACE_STATS(FATAL, "Mpdu's Part of Ampdu = %d",
  2987. peer->stats.tx.amsdu_cnt);
  2988. DP_TRACE_STATS(FATAL, "Last Packet RSSI = %d",
  2989. peer->stats.tx.last_ack_rssi);
  2990. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard = %d",
  2991. peer->stats.tx.dropped.fw_discard);
  2992. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard Retired = %d",
  2993. peer->stats.tx.dropped.fw_discard_retired);
  2994. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard Untransmitted = %d",
  2995. peer->stats.tx.dropped.fw_discard_untransmitted);
  2996. DP_TRACE_STATS(FATAL, "Dropped : Mpdu Age Out = %d",
  2997. peer->stats.tx.dropped.mpdu_age_out);
  2998. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason1 = %d",
  2999. peer->stats.tx.dropped.fw_discard_reason1);
  3000. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason2 = %d",
  3001. peer->stats.tx.dropped.fw_discard_reason2);
  3002. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason3 = %d",
  3003. peer->stats.tx.dropped.fw_discard_reason3);
  3004. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3005. index = 0;
  3006. for (i = 0; i < MAX_MCS; i++) {
  3007. index += qdf_snprint(&tx_mcs[pkt_type][index],
  3008. DP_MCS_LENGTH - index,
  3009. " %d ",
  3010. peer->stats.tx.pkt_type[pkt_type].
  3011. mcs_count[i]);
  3012. }
  3013. }
  3014. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  3015. tx_mcs[0]);
  3016. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  3017. peer->stats.tx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  3018. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  3019. tx_mcs[1]);
  3020. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  3021. peer->stats.tx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  3022. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  3023. tx_mcs[2]);
  3024. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  3025. peer->stats.tx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  3026. DP_TRACE_STATS(FATAL, "11AC MCS(0-9) = %s",
  3027. tx_mcs[3]);
  3028. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  3029. peer->stats.tx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  3030. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  3031. tx_mcs[4]);
  3032. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  3033. peer->stats.tx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  3034. DP_TRACE_STATS(FATAL, "SGI = "
  3035. " 0.8us %d"
  3036. " 0.4us %d"
  3037. " 1.6us %d"
  3038. " 3.2us %d",
  3039. peer->stats.tx.sgi_count[0],
  3040. peer->stats.tx.sgi_count[1],
  3041. peer->stats.tx.sgi_count[2],
  3042. peer->stats.tx.sgi_count[3]);
  3043. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3044. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3045. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3046. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  3047. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  3048. peer->stats.tx.amsdu_cnt);
  3049. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3050. peer->stats.tx.non_amsdu_cnt);
  3051. DP_TRACE_STATS(FATAL, "Node Rx Stats:\n");
  3052. DP_TRACE_STATS(FATAL, "Packets Sent To Stack = %d",
  3053. peer->stats.rx.to_stack.num);
  3054. DP_TRACE_STATS(FATAL, "Bytes Sent To Stack = %d",
  3055. peer->stats.rx.to_stack.bytes);
  3056. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3057. DP_TRACE_STATS(FATAL, "Packets Received = %d",
  3058. peer->stats.rx.rcvd_reo[i].num);
  3059. DP_TRACE_STATS(FATAL, "Bytes Received = %d",
  3060. peer->stats.rx.rcvd_reo[i].bytes);
  3061. }
  3062. DP_TRACE_STATS(FATAL, "Multicast Packets Received = %d",
  3063. peer->stats.rx.multicast.num);
  3064. DP_TRACE_STATS(FATAL, "Multicast Bytes Received = %d",
  3065. peer->stats.rx.multicast.bytes);
  3066. DP_TRACE_STATS(FATAL, "WDS Packets Received = %d",
  3067. peer->stats.rx.wds.num);
  3068. DP_TRACE_STATS(FATAL, "WDS Bytes Received = %d",
  3069. peer->stats.rx.wds.bytes);
  3070. DP_TRACE_STATS(FATAL, "Intra BSS Packets Received = %d",
  3071. peer->stats.rx.intra_bss.pkts.num);
  3072. DP_TRACE_STATS(FATAL, "Intra BSS Bytes Received = %d",
  3073. peer->stats.rx.intra_bss.pkts.bytes);
  3074. DP_TRACE_STATS(FATAL, "Raw Packets Received = %d",
  3075. peer->stats.rx.raw.num);
  3076. DP_TRACE_STATS(FATAL, "Raw Bytes Received = %d",
  3077. peer->stats.rx.raw.bytes);
  3078. DP_TRACE_STATS(FATAL, "Errors: MIC Errors = %d",
  3079. peer->stats.rx.err.mic_err);
  3080. DP_TRACE_STATS(FATAL, "Erros: Decryption Errors = %d",
  3081. peer->stats.rx.err.decrypt_err);
  3082. DP_TRACE_STATS(FATAL, "Msdu's Received As Part of Ampdu = %d",
  3083. peer->stats.rx.non_ampdu_cnt);
  3084. DP_TRACE_STATS(FATAL, "Msdu's Recived As Ampdu = %d",
  3085. peer->stats.rx.ampdu_cnt);
  3086. DP_TRACE_STATS(FATAL, "Msdu's Received Not Part of Amsdu's = %d",
  3087. peer->stats.rx.non_amsdu_cnt);
  3088. DP_TRACE_STATS(FATAL, "MSDUs Received As Part of Amsdu = %d",
  3089. peer->stats.rx.amsdu_cnt);
  3090. DP_TRACE_STATS(FATAL, "SGI ="
  3091. " 0.8us %d"
  3092. " 0.4us %d"
  3093. " 1.6us %d"
  3094. " 3.2us %d",
  3095. peer->stats.rx.sgi_count[0],
  3096. peer->stats.rx.sgi_count[1],
  3097. peer->stats.rx.sgi_count[2],
  3098. peer->stats.rx.sgi_count[3]);
  3099. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3100. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3101. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3102. DP_TRACE_STATS(FATAL, "Reception Type ="
  3103. " SU %d,"
  3104. " MU_MIMO %d,"
  3105. " MU_OFDMA %d,"
  3106. " MU_OFDMA_MIMO %d",
  3107. peer->stats.rx.reception_type[0],
  3108. peer->stats.rx.reception_type[1],
  3109. peer->stats.rx.reception_type[2],
  3110. peer->stats.rx.reception_type[3]);
  3111. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3112. index = 0;
  3113. for (i = 0; i < MAX_MCS; i++) {
  3114. index += qdf_snprint(&rx_mcs[pkt_type][index],
  3115. DP_MCS_LENGTH - index,
  3116. " %d ",
  3117. peer->stats.rx.pkt_type[pkt_type].
  3118. mcs_count[i]);
  3119. }
  3120. }
  3121. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  3122. rx_mcs[0]);
  3123. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  3124. peer->stats.rx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  3125. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  3126. rx_mcs[1]);
  3127. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  3128. peer->stats.rx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  3129. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  3130. rx_mcs[2]);
  3131. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  3132. peer->stats.rx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  3133. DP_TRACE_STATS(FATAL, "11AC MCS(0-9) = %s",
  3134. rx_mcs[3]);
  3135. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  3136. peer->stats.rx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  3137. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  3138. rx_mcs[4]);
  3139. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  3140. peer->stats.rx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  3141. index = 0;
  3142. for (i = 0; i < SS_COUNT; i++) {
  3143. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3144. " %d", peer->stats.rx.nss[i]);
  3145. }
  3146. DP_TRACE_STATS(FATAL, "NSS(0-7) = %s\n",
  3147. nss);
  3148. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  3149. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Ampdu = %d",
  3150. peer->stats.rx.ampdu_cnt);
  3151. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Mpdu Level Aggregation = %d",
  3152. peer->stats.rx.non_ampdu_cnt);
  3153. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  3154. peer->stats.rx.amsdu_cnt);
  3155. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d",
  3156. peer->stats.rx.non_amsdu_cnt);
  3157. }
  3158. /**
  3159. * dp_print_host_stats()- Function to print the stats aggregated at host
  3160. * @vdev_handle: DP_VDEV handle
  3161. * @type: host stats type
  3162. *
  3163. * Available Stat types
  3164. * TXRX_CLEAR_STATS : Clear the stats
  3165. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3166. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3167. * TXRX_TX_HOST_STATS: Print Tx Stats
  3168. * TXRX_RX_HOST_STATS: Print Rx Stats
  3169. *
  3170. * Return: 0 on success, print error message in case of failure
  3171. */
  3172. static int
  3173. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3174. {
  3175. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3176. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3177. dp_aggregate_pdev_stats(pdev);
  3178. switch (type) {
  3179. case TXRX_CLEAR_STATS:
  3180. dp_txrx_host_stats_clr(vdev);
  3181. break;
  3182. case TXRX_RX_RATE_STATS:
  3183. dp_print_rx_rates(vdev);
  3184. break;
  3185. case TXRX_TX_RATE_STATS:
  3186. dp_print_tx_rates(vdev);
  3187. break;
  3188. case TXRX_TX_HOST_STATS:
  3189. dp_print_pdev_tx_stats(pdev);
  3190. dp_print_soc_tx_stats(pdev->soc);
  3191. break;
  3192. case TXRX_RX_HOST_STATS:
  3193. dp_print_pdev_rx_stats(pdev);
  3194. dp_print_soc_rx_stats(pdev->soc);
  3195. break;
  3196. default:
  3197. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3198. break;
  3199. }
  3200. return 0;
  3201. }
  3202. /*
  3203. * dp_get_host_peer_stats()- function to print peer stats
  3204. * @pdev_handle: DP_PDEV handle
  3205. * @mac_addr: mac address of the peer
  3206. *
  3207. * Return: void
  3208. */
  3209. static void
  3210. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3211. {
  3212. struct dp_peer *peer;
  3213. uint8_t local_id;
  3214. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3215. &local_id);
  3216. if (!peer) {
  3217. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3218. "%s: Invalid peer\n", __func__);
  3219. return;
  3220. }
  3221. dp_print_peer_stats(peer);
  3222. dp_peer_rxtid_stats(peer);
  3223. return;
  3224. }
  3225. /*
  3226. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3227. * @pdev_handle: DP_PDEV handle
  3228. *
  3229. * Return: void
  3230. */
  3231. static void
  3232. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3233. {
  3234. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3235. pdev->enhanced_stats_en = 1;
  3236. }
  3237. /*
  3238. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3239. * @pdev_handle: DP_PDEV handle
  3240. *
  3241. * Return: void
  3242. */
  3243. static void
  3244. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3245. {
  3246. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3247. pdev->enhanced_stats_en = 0;
  3248. }
  3249. /*
  3250. * dp_get_fw_peer_stats()- function to print peer stats
  3251. * @pdev_handle: DP_PDEV handle
  3252. * @mac_addr: mac address of the peer
  3253. * @cap: Type of htt stats requested
  3254. *
  3255. * Currently Supporting only MAC ID based requests Only
  3256. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3257. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3258. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3259. *
  3260. * Return: void
  3261. */
  3262. static void
  3263. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3264. uint32_t cap)
  3265. {
  3266. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3267. uint32_t config_param0 = 0;
  3268. uint32_t config_param1 = 0;
  3269. uint32_t config_param2 = 0;
  3270. uint32_t config_param3 = 0;
  3271. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3272. config_param0 |= (1 << (cap + 1));
  3273. config_param1 = 0x8f;
  3274. config_param2 |= (mac_addr[0] & 0x000000ff);
  3275. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3276. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3277. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3278. config_param3 |= (mac_addr[4] & 0x000000ff);
  3279. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3280. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3281. config_param0, config_param1, config_param2,
  3282. config_param3);
  3283. }
  3284. /*
  3285. * dp_set_vdev_param: function to set parameters in vdev
  3286. * @param: parameter type to be set
  3287. * @val: value of parameter to be set
  3288. *
  3289. * return: void
  3290. */
  3291. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3292. enum cdp_vdev_param_type param, uint32_t val)
  3293. {
  3294. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3295. switch (param) {
  3296. case CDP_ENABLE_WDS:
  3297. vdev->wds_enabled = val;
  3298. break;
  3299. case CDP_ENABLE_NAWDS:
  3300. vdev->nawds_enabled = val;
  3301. break;
  3302. case CDP_ENABLE_MCAST_EN:
  3303. vdev->mcast_enhancement_en = val;
  3304. break;
  3305. case CDP_ENABLE_PROXYSTA:
  3306. vdev->proxysta_vdev = val;
  3307. break;
  3308. case CDP_UPDATE_TDLS_FLAGS:
  3309. vdev->tdls_link_connected = val;
  3310. break;
  3311. case CDP_CFG_WDS_AGING_TIMER:
  3312. if (val == 0)
  3313. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  3314. else if (val != vdev->wds_aging_timer_val)
  3315. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  3316. vdev->wds_aging_timer_val = val;
  3317. break;
  3318. default:
  3319. break;
  3320. }
  3321. dp_tx_vdev_update_search_flags(vdev);
  3322. }
  3323. /**
  3324. * dp_peer_set_nawds: set nawds bit in peer
  3325. * @peer_handle: pointer to peer
  3326. * @value: enable/disable nawds
  3327. *
  3328. * return: void
  3329. */
  3330. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  3331. {
  3332. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3333. peer->nawds_enabled = value;
  3334. }
  3335. /*
  3336. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  3337. * @vdev_handle: DP_VDEV handle
  3338. * @map_id:ID of map that needs to be updated
  3339. *
  3340. * Return: void
  3341. */
  3342. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  3343. uint8_t map_id)
  3344. {
  3345. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3346. vdev->dscp_tid_map_id = map_id;
  3347. return;
  3348. }
  3349. /**
  3350. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  3351. * @pdev: DP_PDEV handle
  3352. * @map_id: ID of map that needs to be updated
  3353. * @tos: index value in map
  3354. * @tid: tid value passed by the user
  3355. *
  3356. * Return: void
  3357. */
  3358. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  3359. uint8_t map_id, uint8_t tos, uint8_t tid)
  3360. {
  3361. uint8_t dscp;
  3362. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  3363. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  3364. pdev->dscp_tid_map[map_id][dscp] = tid;
  3365. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  3366. map_id, dscp);
  3367. return;
  3368. }
  3369. /**
  3370. * dp_fw_stats_process(): Process TxRX FW stats request
  3371. * @vdev_handle: DP VDEV handle
  3372. * @val: value passed by user
  3373. *
  3374. * return: int
  3375. */
  3376. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  3377. {
  3378. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3379. struct dp_pdev *pdev = NULL;
  3380. if (!vdev) {
  3381. DP_TRACE(NONE, "VDEV not found");
  3382. return 1;
  3383. }
  3384. pdev = vdev->pdev;
  3385. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  3386. }
  3387. /*
  3388. * dp_txrx_stats() - function to map to firmware and host stats
  3389. * @vdev: virtual handle
  3390. * @stats: type of statistics requested
  3391. *
  3392. * Return: integer
  3393. */
  3394. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  3395. {
  3396. int host_stats;
  3397. int fw_stats;
  3398. if (stats >= CDP_TXRX_MAX_STATS)
  3399. return 0;
  3400. /*
  3401. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  3402. * has to be updated if new FW HTT stats added
  3403. */
  3404. if (stats > CDP_TXRX_STATS_HTT_MAX)
  3405. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  3406. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  3407. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  3408. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3409. "stats: %u fw_stats_type: %d host_stats_type: %d",
  3410. stats, fw_stats, host_stats);
  3411. if (fw_stats != TXRX_FW_STATS_INVALID)
  3412. return dp_fw_stats_process(vdev, fw_stats);
  3413. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  3414. (host_stats <= TXRX_HOST_STATS_MAX))
  3415. return dp_print_host_stats(vdev, host_stats);
  3416. else
  3417. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3418. "Wrong Input for TxRx Stats");
  3419. return 0;
  3420. }
  3421. /*
  3422. * dp_print_per_ring_stats(): Packet count per ring
  3423. * @soc - soc handle
  3424. */
  3425. static void dp_print_per_ring_stats(struct dp_soc *soc)
  3426. {
  3427. uint8_t core, ring;
  3428. uint64_t total_packets;
  3429. DP_TRACE(FATAL, "Reo packets per ring:");
  3430. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  3431. total_packets = 0;
  3432. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  3433. for (core = 0; core < NR_CPUS; core++) {
  3434. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  3435. core, soc->stats.rx.ring_packets[core][ring]);
  3436. total_packets += soc->stats.rx.ring_packets[core][ring];
  3437. }
  3438. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  3439. ring, total_packets);
  3440. }
  3441. }
  3442. /*
  3443. * dp_txrx_path_stats() - Function to display dump stats
  3444. * @soc - soc handle
  3445. *
  3446. * return: none
  3447. */
  3448. static void dp_txrx_path_stats(struct dp_soc *soc)
  3449. {
  3450. uint8_t error_code;
  3451. uint8_t loop_pdev;
  3452. struct dp_pdev *pdev;
  3453. uint8_t i;
  3454. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  3455. pdev = soc->pdev_list[loop_pdev];
  3456. dp_aggregate_pdev_stats(pdev);
  3457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3458. "Tx path Statistics:");
  3459. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  3460. pdev->stats.tx_i.rcvd.num,
  3461. pdev->stats.tx_i.rcvd.bytes);
  3462. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  3463. pdev->stats.tx_i.processed.num,
  3464. pdev->stats.tx_i.processed.bytes);
  3465. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  3466. pdev->stats.tx.tx_success.num,
  3467. pdev->stats.tx.tx_success.bytes);
  3468. DP_TRACE(FATAL, "Dropped in host:");
  3469. DP_TRACE(FATAL, "Total packets dropped: %u,",
  3470. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3471. DP_TRACE(FATAL, "Descriptor not available: %u",
  3472. pdev->stats.tx_i.dropped.desc_na);
  3473. DP_TRACE(FATAL, "Ring full: %u",
  3474. pdev->stats.tx_i.dropped.ring_full);
  3475. DP_TRACE(FATAL, "Enqueue fail: %u",
  3476. pdev->stats.tx_i.dropped.enqueue_fail);
  3477. DP_TRACE(FATAL, "DMA Error: %u",
  3478. pdev->stats.tx_i.dropped.dma_error);
  3479. DP_TRACE(FATAL, "Dropped in hardware:");
  3480. DP_TRACE(FATAL, "total packets dropped: %u",
  3481. pdev->stats.tx.tx_failed);
  3482. DP_TRACE(FATAL, "mpdu age out: %u",
  3483. pdev->stats.tx.dropped.mpdu_age_out);
  3484. DP_TRACE(FATAL, "firmware discard reason1: %u",
  3485. pdev->stats.tx.dropped.fw_discard_reason1);
  3486. DP_TRACE(FATAL, "firmware discard reason2: %u",
  3487. pdev->stats.tx.dropped.fw_discard_reason2);
  3488. DP_TRACE(FATAL, "firmware discard reason3: %u",
  3489. pdev->stats.tx.dropped.fw_discard_reason3);
  3490. DP_TRACE(FATAL, "peer_invalid: %u",
  3491. pdev->soc->stats.tx.tx_invalid_peer.num);
  3492. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  3493. DP_TRACE(FATAL, "Single Packet: %u",
  3494. pdev->stats.tx_comp_histogram.pkts_1);
  3495. DP_TRACE(FATAL, "2-20 Packets: %u",
  3496. pdev->stats.tx_comp_histogram.pkts_2_20);
  3497. DP_TRACE(FATAL, "21-40 Packets: %u",
  3498. pdev->stats.tx_comp_histogram.pkts_21_40);
  3499. DP_TRACE(FATAL, "41-60 Packets: %u",
  3500. pdev->stats.tx_comp_histogram.pkts_41_60);
  3501. DP_TRACE(FATAL, "61-80 Packets: %u",
  3502. pdev->stats.tx_comp_histogram.pkts_61_80);
  3503. DP_TRACE(FATAL, "81-100 Packets: %u",
  3504. pdev->stats.tx_comp_histogram.pkts_81_100);
  3505. DP_TRACE(FATAL, "101-200 Packets: %u",
  3506. pdev->stats.tx_comp_histogram.pkts_101_200);
  3507. DP_TRACE(FATAL, " 201+ Packets: %u",
  3508. pdev->stats.tx_comp_histogram.pkts_201_plus);
  3509. DP_TRACE(FATAL, "Rx path statistics");
  3510. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  3511. pdev->stats.rx.to_stack.num,
  3512. pdev->stats.rx.to_stack.bytes);
  3513. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3514. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  3515. i, pdev->stats.rx.rcvd_reo[i].num,
  3516. pdev->stats.rx.rcvd_reo[i].bytes);
  3517. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  3518. pdev->stats.rx.intra_bss.pkts.num,
  3519. pdev->stats.rx.intra_bss.pkts.bytes);
  3520. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  3521. pdev->stats.rx.raw.num,
  3522. pdev->stats.rx.raw.bytes);
  3523. DP_TRACE(FATAL, "dropped: error %u msdus",
  3524. pdev->stats.rx.err.mic_err);
  3525. DP_TRACE(FATAL, "peer invalid %u",
  3526. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  3527. DP_TRACE(FATAL, "Reo Statistics");
  3528. DP_TRACE(FATAL, "rbm error: %u msdus",
  3529. pdev->soc->stats.rx.err.invalid_rbm);
  3530. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  3531. pdev->soc->stats.rx.err.hal_ring_access_fail);
  3532. DP_TRACE(FATAL, "Reo errors");
  3533. for (error_code = 0; error_code < REO_ERROR_TYPE_MAX;
  3534. error_code++) {
  3535. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  3536. error_code,
  3537. pdev->soc->stats.rx.err.reo_error[error_code]);
  3538. }
  3539. for (error_code = 0; error_code < MAX_RXDMA_ERRORS;
  3540. error_code++) {
  3541. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  3542. error_code,
  3543. pdev->soc->stats.rx.err
  3544. .rxdma_error[error_code]);
  3545. }
  3546. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  3547. DP_TRACE(FATAL, "Single Packet: %u",
  3548. pdev->stats.rx_ind_histogram.pkts_1);
  3549. DP_TRACE(FATAL, "2-20 Packets: %u",
  3550. pdev->stats.rx_ind_histogram.pkts_2_20);
  3551. DP_TRACE(FATAL, "21-40 Packets: %u",
  3552. pdev->stats.rx_ind_histogram.pkts_21_40);
  3553. DP_TRACE(FATAL, "41-60 Packets: %u",
  3554. pdev->stats.rx_ind_histogram.pkts_41_60);
  3555. DP_TRACE(FATAL, "61-80 Packets: %u",
  3556. pdev->stats.rx_ind_histogram.pkts_61_80);
  3557. DP_TRACE(FATAL, "81-100 Packets: %u",
  3558. pdev->stats.rx_ind_histogram.pkts_81_100);
  3559. DP_TRACE(FATAL, "101-200 Packets: %u",
  3560. pdev->stats.rx_ind_histogram.pkts_101_200);
  3561. DP_TRACE(FATAL, " 201+ Packets: %u",
  3562. pdev->stats.rx_ind_histogram.pkts_201_plus);
  3563. }
  3564. }
  3565. /*
  3566. * dp_txrx_dump_stats() - Dump statistics
  3567. * @value - Statistics option
  3568. */
  3569. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  3570. {
  3571. struct dp_soc *soc =
  3572. (struct dp_soc *)psoc;
  3573. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3574. if (!soc) {
  3575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3576. "%s: soc is NULL", __func__);
  3577. return QDF_STATUS_E_INVAL;
  3578. }
  3579. switch (value) {
  3580. case CDP_TXRX_PATH_STATS:
  3581. dp_txrx_path_stats(soc);
  3582. break;
  3583. case CDP_RX_RING_STATS:
  3584. dp_print_per_ring_stats(soc);
  3585. break;
  3586. case CDP_TXRX_TSO_STATS:
  3587. /* TODO: NOT IMPLEMENTED */
  3588. break;
  3589. case CDP_DUMP_TX_FLOW_POOL_INFO:
  3590. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  3591. break;
  3592. case CDP_TXRX_DESC_STATS:
  3593. /* TODO: NOT IMPLEMENTED */
  3594. break;
  3595. default:
  3596. status = QDF_STATUS_E_INVAL;
  3597. break;
  3598. }
  3599. return status;
  3600. }
  3601. static struct cdp_wds_ops dp_ops_wds = {
  3602. .vdev_set_wds = dp_vdev_set_wds,
  3603. };
  3604. /*
  3605. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  3606. * @soc - datapath soc handle
  3607. * @peer - datapath peer handle
  3608. *
  3609. * Delete the AST entries belonging to a peer
  3610. */
  3611. #ifdef FEATURE_WDS
  3612. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  3613. struct dp_peer *peer)
  3614. {
  3615. struct dp_ast_entry *ast_entry;
  3616. qdf_spin_lock_bh(&soc->ast_lock);
  3617. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry) {
  3618. if (ast_entry->next_hop) {
  3619. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  3620. soc->osif_soc,
  3621. ast_entry->mac_addr.raw);
  3622. }
  3623. dp_peer_del_ast(soc, ast_entry);
  3624. }
  3625. qdf_spin_unlock_bh(&soc->ast_lock);
  3626. }
  3627. #else
  3628. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  3629. struct dp_peer *peer)
  3630. {
  3631. }
  3632. #endif
  3633. #ifdef CONFIG_WIN
  3634. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  3635. {
  3636. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  3637. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  3638. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  3639. dp_peer_delete_ast_entries(soc, peer);
  3640. }
  3641. #endif
  3642. static struct cdp_cmn_ops dp_ops_cmn = {
  3643. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  3644. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  3645. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  3646. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  3647. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  3648. .txrx_peer_create = dp_peer_create_wifi3,
  3649. .txrx_peer_setup = dp_peer_setup_wifi3,
  3650. #ifdef CONFIG_WIN
  3651. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  3652. #else
  3653. .txrx_peer_teardown = NULL,
  3654. #endif
  3655. .txrx_peer_delete = dp_peer_delete_wifi3,
  3656. .txrx_vdev_register = dp_vdev_register_wifi3,
  3657. .txrx_soc_detach = dp_soc_detach_wifi3,
  3658. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  3659. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  3660. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  3661. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  3662. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  3663. .delba_process = dp_delba_process_wifi3,
  3664. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  3665. .flush_cache_rx_queue = NULL,
  3666. /* TODO: get API's for dscp-tid need to be added*/
  3667. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  3668. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  3669. .txrx_stats = dp_txrx_stats,
  3670. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  3671. .display_stats = dp_txrx_dump_stats,
  3672. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  3673. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  3674. .txrx_intr_attach = dp_soc_interrupt_attach,
  3675. .txrx_intr_detach = dp_soc_interrupt_detach,
  3676. .set_pn_check = dp_set_pn_check_wifi3,
  3677. /* TODO: Add other functions */
  3678. };
  3679. static struct cdp_ctrl_ops dp_ops_ctrl = {
  3680. .txrx_peer_authorize = dp_peer_authorize,
  3681. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  3682. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  3683. #ifdef MESH_MODE_SUPPORT
  3684. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  3685. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  3686. #endif
  3687. .txrx_set_vdev_param = dp_set_vdev_param,
  3688. .txrx_peer_set_nawds = dp_peer_set_nawds,
  3689. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  3690. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  3691. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  3692. .txrx_update_filter_neighbour_peers =
  3693. dp_update_filter_neighbour_peers,
  3694. /* TODO: Add other functions */
  3695. .txrx_wdi_event_sub = dp_wdi_event_sub,
  3696. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  3697. };
  3698. static struct cdp_me_ops dp_ops_me = {
  3699. #ifdef ATH_SUPPORT_IQUE
  3700. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  3701. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  3702. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  3703. #endif
  3704. };
  3705. static struct cdp_mon_ops dp_ops_mon = {
  3706. .txrx_monitor_set_filter_ucast_data = NULL,
  3707. .txrx_monitor_set_filter_mcast_data = NULL,
  3708. .txrx_monitor_set_filter_non_data = NULL,
  3709. .txrx_monitor_get_filter_ucast_data = NULL,
  3710. .txrx_monitor_get_filter_mcast_data = NULL,
  3711. .txrx_monitor_get_filter_non_data = NULL,
  3712. .txrx_reset_monitor_mode = NULL,
  3713. };
  3714. static struct cdp_host_stats_ops dp_ops_host_stats = {
  3715. .txrx_per_peer_stats = dp_get_host_peer_stats,
  3716. .get_fw_peer_stats = dp_get_fw_peer_stats,
  3717. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  3718. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  3719. /* TODO */
  3720. };
  3721. static struct cdp_raw_ops dp_ops_raw = {
  3722. /* TODO */
  3723. };
  3724. #ifdef CONFIG_WIN
  3725. static struct cdp_pflow_ops dp_ops_pflow = {
  3726. /* TODO */
  3727. };
  3728. #endif /* CONFIG_WIN */
  3729. #ifdef DP_INTR_POLL_BASED
  3730. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  3731. {
  3732. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  3733. struct dp_soc *soc = pdev->soc;
  3734. qdf_timer_stop(&soc->int_timer);
  3735. return QDF_STATUS_SUCCESS;
  3736. }
  3737. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  3738. {
  3739. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  3740. struct dp_soc *soc = pdev->soc;
  3741. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  3742. return QDF_STATUS_SUCCESS;
  3743. }
  3744. #else
  3745. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  3746. {
  3747. return QDF_STATUS_SUCCESS;
  3748. }
  3749. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  3750. {
  3751. return QDF_STATUS_SUCCESS;
  3752. }
  3753. #endif /* DP_INTR_POLL_BASED */
  3754. #ifndef CONFIG_WIN
  3755. static struct cdp_misc_ops dp_ops_misc = {
  3756. .get_opmode = dp_get_opmode,
  3757. #ifdef FEATURE_RUNTIME_PM
  3758. .runtime_suspend = dp_bus_suspend,
  3759. .runtime_resume = dp_bus_resume,
  3760. #endif
  3761. };
  3762. static struct cdp_flowctl_ops dp_ops_flowctl = {
  3763. /* WIFI 3.0 DP implement as required. */
  3764. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3765. .register_pause_cb = dp_txrx_register_pause_cb,
  3766. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  3767. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  3768. };
  3769. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  3770. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3771. };
  3772. static struct cdp_ipa_ops dp_ops_ipa = {
  3773. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3774. };
  3775. static struct cdp_bus_ops dp_ops_bus = {
  3776. .bus_suspend = dp_bus_suspend,
  3777. .bus_resume = dp_bus_resume
  3778. };
  3779. static struct cdp_ocb_ops dp_ops_ocb = {
  3780. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3781. };
  3782. static struct cdp_throttle_ops dp_ops_throttle = {
  3783. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3784. };
  3785. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  3786. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3787. };
  3788. static struct cdp_cfg_ops dp_ops_cfg = {
  3789. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  3790. };
  3791. static struct cdp_peer_ops dp_ops_peer = {
  3792. .register_peer = dp_register_peer,
  3793. .clear_peer = dp_clear_peer,
  3794. .find_peer_by_addr = dp_find_peer_by_addr,
  3795. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  3796. .local_peer_id = dp_local_peer_id,
  3797. .peer_find_by_local_id = dp_peer_find_by_local_id,
  3798. .peer_state_update = dp_peer_state_update,
  3799. .get_vdevid = dp_get_vdevid,
  3800. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  3801. .get_vdev_for_peer = dp_get_vdev_for_peer,
  3802. .get_peer_state = dp_get_peer_state,
  3803. .last_assoc_received = dp_get_last_assoc_received,
  3804. .last_disassoc_received = dp_get_last_disassoc_received,
  3805. .last_deauth_received = dp_get_last_deauth_received,
  3806. };
  3807. #endif
  3808. static struct cdp_ops dp_txrx_ops = {
  3809. .cmn_drv_ops = &dp_ops_cmn,
  3810. .ctrl_ops = &dp_ops_ctrl,
  3811. .me_ops = &dp_ops_me,
  3812. .mon_ops = &dp_ops_mon,
  3813. .host_stats_ops = &dp_ops_host_stats,
  3814. .wds_ops = &dp_ops_wds,
  3815. .raw_ops = &dp_ops_raw,
  3816. #ifdef CONFIG_WIN
  3817. .pflow_ops = &dp_ops_pflow,
  3818. #endif /* CONFIG_WIN */
  3819. #ifndef CONFIG_WIN
  3820. .misc_ops = &dp_ops_misc,
  3821. .cfg_ops = &dp_ops_cfg,
  3822. .flowctl_ops = &dp_ops_flowctl,
  3823. .l_flowctl_ops = &dp_ops_l_flowctl,
  3824. .ipa_ops = &dp_ops_ipa,
  3825. .bus_ops = &dp_ops_bus,
  3826. .ocb_ops = &dp_ops_ocb,
  3827. .peer_ops = &dp_ops_peer,
  3828. .throttle_ops = &dp_ops_throttle,
  3829. .mob_stats_ops = &dp_ops_mob_stats,
  3830. #endif
  3831. };
  3832. /*
  3833. * dp_soc_set_txrx_ring_map()
  3834. * @dp_soc: DP handler for soc
  3835. *
  3836. * Return: Void
  3837. */
  3838. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  3839. {
  3840. uint32_t i;
  3841. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  3842. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  3843. }
  3844. }
  3845. /*
  3846. * dp_soc_attach_wifi3() - Attach txrx SOC
  3847. * @osif_soc: Opaque SOC handle from OSIF/HDD
  3848. * @htc_handle: Opaque HTC handle
  3849. * @hif_handle: Opaque HIF handle
  3850. * @qdf_osdev: QDF device
  3851. *
  3852. * Return: DP SOC handle on success, NULL on failure
  3853. */
  3854. /*
  3855. * Local prototype added to temporarily address warning caused by
  3856. * -Wmissing-prototypes. A more correct solution, namely to expose
  3857. * a prototype in an appropriate header file, will come later.
  3858. */
  3859. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  3860. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  3861. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  3862. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  3863. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  3864. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  3865. {
  3866. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  3867. if (!soc) {
  3868. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3869. FL("DP SOC memory allocation failed"));
  3870. goto fail0;
  3871. }
  3872. soc->cdp_soc.ops = &dp_txrx_ops;
  3873. soc->cdp_soc.ol_ops = ol_ops;
  3874. soc->osif_soc = osif_soc;
  3875. soc->osdev = qdf_osdev;
  3876. soc->hif_handle = hif_handle;
  3877. soc->psoc = psoc;
  3878. soc->hal_soc = hif_get_hal_handle(hif_handle);
  3879. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  3880. soc->hal_soc, qdf_osdev);
  3881. if (!soc->htt_handle) {
  3882. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3883. FL("HTT attach failed"));
  3884. goto fail1;
  3885. }
  3886. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  3887. if (!soc->wlan_cfg_ctx) {
  3888. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3889. FL("wlan_cfg_soc_attach failed"));
  3890. goto fail2;
  3891. }
  3892. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3893. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  3894. CDP_CFG_MAX_PEER_ID);
  3895. if (ret != -EINVAL) {
  3896. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  3897. }
  3898. }
  3899. qdf_spinlock_create(&soc->peer_ref_mutex);
  3900. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  3901. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  3902. /* fill the tx/rx cpu ring map*/
  3903. dp_soc_set_txrx_ring_map(soc);
  3904. return (void *)soc;
  3905. fail2:
  3906. htt_soc_detach(soc->htt_handle);
  3907. fail1:
  3908. qdf_mem_free(soc);
  3909. fail0:
  3910. return NULL;
  3911. }
  3912. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  3913. /*
  3914. * dp_set_pktlog_wifi3() - attach txrx vdev
  3915. * @pdev: Datapath PDEV handle
  3916. * @event: which event's notifications are being subscribed to
  3917. * @enable: WDI event subscribe or not. (True or False)
  3918. *
  3919. * Return: Success, NULL on failure
  3920. */
  3921. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  3922. bool enable)
  3923. {
  3924. struct dp_soc *soc = pdev->soc;
  3925. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  3926. if (enable) {
  3927. switch (event) {
  3928. case WDI_EVENT_RX_DESC:
  3929. if (pdev->monitor_vdev) {
  3930. /* Nothing needs to be done if monitor mode is
  3931. * enabled
  3932. */
  3933. return 0;
  3934. }
  3935. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  3936. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  3937. htt_tlv_filter.mpdu_start = 1;
  3938. htt_tlv_filter.msdu_start = 1;
  3939. htt_tlv_filter.msdu_end = 1;
  3940. htt_tlv_filter.mpdu_end = 1;
  3941. htt_tlv_filter.packet_header = 1;
  3942. htt_tlv_filter.attention = 1;
  3943. htt_tlv_filter.ppdu_start = 1;
  3944. htt_tlv_filter.ppdu_end = 1;
  3945. htt_tlv_filter.ppdu_end_user_stats = 1;
  3946. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3947. htt_tlv_filter.ppdu_end_status_done = 1;
  3948. htt_tlv_filter.enable_fp = 1;
  3949. htt_h2t_rx_ring_cfg(soc->htt_handle,
  3950. pdev->pdev_id,
  3951. pdev->rxdma_mon_status_ring.hal_srng,
  3952. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  3953. &htt_tlv_filter);
  3954. }
  3955. break;
  3956. case WDI_EVENT_LITE_RX:
  3957. if (pdev->monitor_vdev) {
  3958. /* Nothing needs to be done if monitor mode is
  3959. * enabled
  3960. */
  3961. return 0;
  3962. }
  3963. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  3964. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  3965. htt_tlv_filter.ppdu_start = 1;
  3966. htt_tlv_filter.ppdu_end = 1;
  3967. htt_tlv_filter.ppdu_end_user_stats = 1;
  3968. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3969. htt_tlv_filter.ppdu_end_status_done = 1;
  3970. htt_tlv_filter.enable_fp = 1;
  3971. htt_h2t_rx_ring_cfg(soc->htt_handle,
  3972. pdev->pdev_id,
  3973. pdev->rxdma_mon_status_ring.hal_srng,
  3974. RXDMA_MONITOR_STATUS,
  3975. RX_BUFFER_SIZE_PKTLOG_LITE,
  3976. &htt_tlv_filter);
  3977. }
  3978. break;
  3979. case WDI_EVENT_LITE_T2H:
  3980. if (pdev->monitor_vdev) {
  3981. /* Nothing needs to be done if monitor mode is
  3982. * enabled
  3983. */
  3984. return 0;
  3985. }
  3986. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  3987. * passing value 0xffff. Once these macros will define in htt
  3988. * header file will use proper macros
  3989. */
  3990. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  3991. break;
  3992. default:
  3993. /* Nothing needs to be done for other pktlog types */
  3994. break;
  3995. }
  3996. } else {
  3997. switch (event) {
  3998. case WDI_EVENT_RX_DESC:
  3999. case WDI_EVENT_LITE_RX:
  4000. if (pdev->monitor_vdev) {
  4001. /* Nothing needs to be done if monitor mode is
  4002. * enabled
  4003. */
  4004. return 0;
  4005. }
  4006. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4007. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4008. /* htt_tlv_filter is initialized to 0 */
  4009. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4010. pdev->pdev_id,
  4011. pdev->rxdma_mon_status_ring.hal_srng,
  4012. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4013. &htt_tlv_filter);
  4014. }
  4015. break;
  4016. case WDI_EVENT_LITE_T2H:
  4017. if (pdev->monitor_vdev) {
  4018. /* Nothing needs to be done if monitor mode is
  4019. * enabled
  4020. */
  4021. return 0;
  4022. }
  4023. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4024. * passing value 0. Once these macros will define in htt
  4025. * header file will use proper macros
  4026. */
  4027. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4028. break;
  4029. default:
  4030. /* Nothing needs to be done for other pktlog types */
  4031. break;
  4032. }
  4033. }
  4034. return 0;
  4035. }
  4036. #endif