dp_tx.c 100 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. bool is_last_seg;
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  121. is_last_seg = false;
  122. else
  123. is_last_seg = true;
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. tx_desc->tso_desc, is_last_seg);
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  167. struct dp_tx_desc_s *tx_desc)
  168. {
  169. }
  170. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  171. struct dp_tx_desc_s *tx_desc)
  172. {
  173. }
  174. #endif
  175. /**
  176. * dp_tx_desc_release() - Release Tx Descriptor
  177. * @tx_desc : Tx Descriptor
  178. * @desc_pool_id: Descriptor Pool ID
  179. *
  180. * Deallocate all resources attached to Tx descriptor and free the Tx
  181. * descriptor.
  182. *
  183. * Return:
  184. */
  185. static void
  186. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  187. {
  188. struct dp_pdev *pdev = tx_desc->pdev;
  189. struct dp_soc *soc;
  190. uint8_t comp_status = 0;
  191. qdf_assert(pdev);
  192. soc = pdev->soc;
  193. if (tx_desc->frm_type == dp_tx_frm_tso)
  194. dp_tx_tso_desc_release(soc, tx_desc);
  195. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  196. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  198. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  201. qdf_atomic_dec(&pdev->num_tx_exception);
  202. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  203. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  204. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  205. else
  206. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  208. "Tx Completion Release desc %d status %d outstanding %d",
  209. tx_desc->id, comp_status,
  210. qdf_atomic_read(&pdev->num_tx_outstanding));
  211. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  212. return;
  213. }
  214. /**
  215. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  216. * @vdev: DP vdev Handle
  217. * @nbuf: skb
  218. *
  219. * Prepares and fills HTT metadata in the frame pre-header for special frames
  220. * that should be transmitted using varying transmit parameters.
  221. * There are 2 VDEV modes that currently needs this special metadata -
  222. * 1) Mesh Mode
  223. * 2) DSRC Mode
  224. *
  225. * Return: HTT metadata size
  226. *
  227. */
  228. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  229. uint32_t *meta_data)
  230. {
  231. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  232. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  233. uint8_t htt_desc_size;
  234. /* Size rounded of multiple of 8 bytes */
  235. uint8_t htt_desc_size_aligned;
  236. uint8_t *hdr = NULL;
  237. /*
  238. * Metadata - HTT MSDU Extension header
  239. */
  240. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  241. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  242. if (vdev->mesh_vdev) {
  243. /* Fill and add HTT metaheader */
  244. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  245. if (hdr == NULL) {
  246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  247. "Error in filling HTT metadata");
  248. return 0;
  249. }
  250. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  251. } else if (vdev->opmode == wlan_op_mode_ocb) {
  252. /* Todo - Add support for DSRC */
  253. }
  254. return htt_desc_size_aligned;
  255. }
  256. /**
  257. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  258. * @tso_seg: TSO segment to process
  259. * @ext_desc: Pointer to MSDU extension descriptor
  260. *
  261. * Return: void
  262. */
  263. #if defined(FEATURE_TSO)
  264. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  265. void *ext_desc)
  266. {
  267. uint8_t num_frag;
  268. uint32_t tso_flags;
  269. /*
  270. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  271. * tcp_flag_mask
  272. *
  273. * Checksum enable flags are set in TCL descriptor and not in Extension
  274. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  275. */
  276. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  277. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  278. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  279. tso_seg->tso_flags.ip_len);
  280. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  281. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  282. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  283. uint32_t lo = 0;
  284. uint32_t hi = 0;
  285. qdf_dmaaddr_to_32s(
  286. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  287. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  288. tso_seg->tso_frags[num_frag].length);
  289. }
  290. return;
  291. }
  292. #else
  293. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  294. void *ext_desc)
  295. {
  296. return;
  297. }
  298. #endif
  299. #if defined(FEATURE_TSO)
  300. /**
  301. * dp_tx_free_tso_seg() - Loop through the tso segments
  302. * allocated and free them
  303. *
  304. * @soc: soc handle
  305. * @free_seg: list of tso segments
  306. * @msdu_info: msdu descriptor
  307. *
  308. * Return - void
  309. */
  310. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  311. struct qdf_tso_seg_elem_t *free_seg,
  312. struct dp_tx_msdu_info_s *msdu_info)
  313. {
  314. struct qdf_tso_seg_elem_t *next_seg;
  315. while (free_seg) {
  316. next_seg = free_seg->next;
  317. dp_tx_tso_desc_free(soc,
  318. msdu_info->tx_queue.desc_pool_id,
  319. free_seg);
  320. free_seg = next_seg;
  321. }
  322. }
  323. /**
  324. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  325. * allocated and free them
  326. *
  327. * @soc: soc handle
  328. * @free_seg: list of tso segments
  329. * @msdu_info: msdu descriptor
  330. * Return - void
  331. */
  332. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  333. struct qdf_tso_num_seg_elem_t *free_seg,
  334. struct dp_tx_msdu_info_s *msdu_info)
  335. {
  336. struct qdf_tso_num_seg_elem_t *next_seg;
  337. while (free_seg) {
  338. next_seg = free_seg->next;
  339. dp_tso_num_seg_free(soc,
  340. msdu_info->tx_queue.desc_pool_id,
  341. free_seg);
  342. free_seg = next_seg;
  343. }
  344. }
  345. /**
  346. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  347. * @vdev: virtual device handle
  348. * @msdu: network buffer
  349. * @msdu_info: meta data associated with the msdu
  350. *
  351. * Return: QDF_STATUS_SUCCESS success
  352. */
  353. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  354. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  355. {
  356. struct qdf_tso_seg_elem_t *tso_seg;
  357. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  358. struct dp_soc *soc = vdev->pdev->soc;
  359. struct qdf_tso_info_t *tso_info;
  360. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  361. tso_info = &msdu_info->u.tso_info;
  362. tso_info->curr_seg = NULL;
  363. tso_info->tso_seg_list = NULL;
  364. tso_info->num_segs = num_seg;
  365. msdu_info->frm_type = dp_tx_frm_tso;
  366. tso_info->tso_num_seg_list = NULL;
  367. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  368. while (num_seg) {
  369. tso_seg = dp_tx_tso_desc_alloc(
  370. soc, msdu_info->tx_queue.desc_pool_id);
  371. if (tso_seg) {
  372. tso_seg->next = tso_info->tso_seg_list;
  373. tso_info->tso_seg_list = tso_seg;
  374. num_seg--;
  375. } else {
  376. struct qdf_tso_seg_elem_t *free_seg =
  377. tso_info->tso_seg_list;
  378. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  379. return QDF_STATUS_E_NOMEM;
  380. }
  381. }
  382. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  383. tso_num_seg = dp_tso_num_seg_alloc(soc,
  384. msdu_info->tx_queue.desc_pool_id);
  385. if (tso_num_seg) {
  386. tso_num_seg->next = tso_info->tso_num_seg_list;
  387. tso_info->tso_num_seg_list = tso_num_seg;
  388. } else {
  389. /* Bug: free tso_num_seg and tso_seg */
  390. /* Free the already allocated num of segments */
  391. struct qdf_tso_seg_elem_t *free_seg =
  392. tso_info->tso_seg_list;
  393. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  394. __func__);
  395. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  396. return QDF_STATUS_E_NOMEM;
  397. }
  398. msdu_info->num_seg =
  399. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  400. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  401. msdu_info->num_seg);
  402. if (!(msdu_info->num_seg)) {
  403. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  404. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  405. msdu_info);
  406. return QDF_STATUS_E_INVAL;
  407. }
  408. tso_info->curr_seg = tso_info->tso_seg_list;
  409. return QDF_STATUS_SUCCESS;
  410. }
  411. #else
  412. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  413. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  414. {
  415. return QDF_STATUS_E_NOMEM;
  416. }
  417. #endif
  418. /**
  419. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  420. * @vdev: DP Vdev handle
  421. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  422. * @desc_pool_id: Descriptor Pool ID
  423. *
  424. * Return:
  425. */
  426. static
  427. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  428. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  429. {
  430. uint8_t i;
  431. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  432. struct dp_tx_seg_info_s *seg_info;
  433. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  434. struct dp_soc *soc = vdev->pdev->soc;
  435. /* Allocate an extension descriptor */
  436. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  437. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  438. if (!msdu_ext_desc) {
  439. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  440. return NULL;
  441. }
  442. if (msdu_info->exception_fw &&
  443. qdf_unlikely(vdev->mesh_vdev)) {
  444. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  445. &msdu_info->meta_data[0],
  446. sizeof(struct htt_tx_msdu_desc_ext2_t));
  447. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  448. }
  449. switch (msdu_info->frm_type) {
  450. case dp_tx_frm_sg:
  451. case dp_tx_frm_me:
  452. case dp_tx_frm_raw:
  453. seg_info = msdu_info->u.sg_info.curr_seg;
  454. /* Update the buffer pointers in MSDU Extension Descriptor */
  455. for (i = 0; i < seg_info->frag_cnt; i++) {
  456. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  457. seg_info->frags[i].paddr_lo,
  458. seg_info->frags[i].paddr_hi,
  459. seg_info->frags[i].len);
  460. }
  461. break;
  462. case dp_tx_frm_tso:
  463. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  464. &cached_ext_desc[0]);
  465. break;
  466. default:
  467. break;
  468. }
  469. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  470. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  471. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  472. msdu_ext_desc->vaddr);
  473. return msdu_ext_desc;
  474. }
  475. /**
  476. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  477. *
  478. * @skb: skb to be traced
  479. * @msdu_id: msdu_id of the packet
  480. * @vdev_id: vdev_id of the packet
  481. *
  482. * Return: None
  483. */
  484. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  485. uint8_t vdev_id)
  486. {
  487. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  488. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  489. DPTRACE(qdf_dp_trace_ptr(skb,
  490. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  491. QDF_TRACE_DEFAULT_PDEV_ID,
  492. qdf_nbuf_data_addr(skb),
  493. sizeof(qdf_nbuf_data(skb)),
  494. msdu_id, vdev_id));
  495. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  496. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  497. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  498. msdu_id, QDF_TX));
  499. }
  500. /**
  501. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  502. * @vdev: DP vdev handle
  503. * @nbuf: skb
  504. * @desc_pool_id: Descriptor pool ID
  505. * @meta_data: Metadata to the fw
  506. * @tx_exc_metadata: Handle that holds exception path metadata
  507. * Allocate and prepare Tx descriptor with msdu information.
  508. *
  509. * Return: Pointer to Tx Descriptor on success,
  510. * NULL on failure
  511. */
  512. static
  513. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  514. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  515. struct dp_tx_msdu_info_s *msdu_info,
  516. struct cdp_tx_exception_metadata *tx_exc_metadata)
  517. {
  518. uint8_t align_pad;
  519. uint8_t is_exception = 0;
  520. uint8_t htt_hdr_size;
  521. struct ether_header *eh;
  522. struct dp_tx_desc_s *tx_desc;
  523. struct dp_pdev *pdev = vdev->pdev;
  524. struct dp_soc *soc = pdev->soc;
  525. /* Allocate software Tx descriptor */
  526. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  527. if (qdf_unlikely(!tx_desc)) {
  528. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  529. return NULL;
  530. }
  531. /* Flow control/Congestion Control counters */
  532. qdf_atomic_inc(&pdev->num_tx_outstanding);
  533. /* Initialize the SW tx descriptor */
  534. tx_desc->nbuf = nbuf;
  535. tx_desc->frm_type = dp_tx_frm_std;
  536. tx_desc->tx_encap_type = (tx_exc_metadata ?
  537. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  538. tx_desc->vdev = vdev;
  539. tx_desc->pdev = pdev;
  540. tx_desc->msdu_ext_desc = NULL;
  541. tx_desc->pkt_offset = 0;
  542. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  543. /* Reset the control block */
  544. qdf_nbuf_reset_ctxt(nbuf);
  545. /*
  546. * For special modes (vdev_type == ocb or mesh), data frames should be
  547. * transmitted using varying transmit parameters (tx spec) which include
  548. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  549. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  550. * These frames are sent as exception packets to firmware.
  551. *
  552. * HW requirement is that metadata should always point to a
  553. * 8-byte aligned address. So we add alignment pad to start of buffer.
  554. * HTT Metadata should be ensured to be multiple of 8-bytes,
  555. * to get 8-byte aligned start address along with align_pad added
  556. *
  557. * |-----------------------------|
  558. * | |
  559. * |-----------------------------| <-----Buffer Pointer Address given
  560. * | | ^ in HW descriptor (aligned)
  561. * | HTT Metadata | |
  562. * | | |
  563. * | | | Packet Offset given in descriptor
  564. * | | |
  565. * |-----------------------------| |
  566. * | Alignment Pad | v
  567. * |-----------------------------| <----- Actual buffer start address
  568. * | SKB Data | (Unaligned)
  569. * | |
  570. * | |
  571. * | |
  572. * | |
  573. * | |
  574. * |-----------------------------|
  575. */
  576. if (qdf_unlikely((msdu_info->exception_fw)) ||
  577. (vdev->opmode == wlan_op_mode_ocb)) {
  578. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  579. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  581. "qdf_nbuf_push_head failed");
  582. goto failure;
  583. }
  584. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  585. msdu_info->meta_data);
  586. if (htt_hdr_size == 0)
  587. goto failure;
  588. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  589. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  590. is_exception = 1;
  591. }
  592. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  593. qdf_nbuf_map(soc->osdev, nbuf,
  594. QDF_DMA_TO_DEVICE))) {
  595. /* Handle failure */
  596. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  597. "qdf_nbuf_map failed");
  598. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  599. goto failure;
  600. }
  601. if (qdf_unlikely(vdev->nawds_enabled)) {
  602. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  603. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  604. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  605. is_exception = 1;
  606. }
  607. }
  608. #if !TQM_BYPASS_WAR
  609. if (is_exception || tx_exc_metadata)
  610. #endif
  611. {
  612. /* Temporary WAR due to TQM VP issues */
  613. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  614. qdf_atomic_inc(&pdev->num_tx_exception);
  615. }
  616. return tx_desc;
  617. failure:
  618. dp_tx_desc_release(tx_desc, desc_pool_id);
  619. return NULL;
  620. }
  621. /**
  622. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  623. * @vdev: DP vdev handle
  624. * @nbuf: skb
  625. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  626. * @desc_pool_id : Descriptor Pool ID
  627. *
  628. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  629. * information. For frames wth fragments, allocate and prepare
  630. * an MSDU extension descriptor
  631. *
  632. * Return: Pointer to Tx Descriptor on success,
  633. * NULL on failure
  634. */
  635. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  636. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  637. uint8_t desc_pool_id)
  638. {
  639. struct dp_tx_desc_s *tx_desc;
  640. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  641. struct dp_pdev *pdev = vdev->pdev;
  642. struct dp_soc *soc = pdev->soc;
  643. /* Allocate software Tx descriptor */
  644. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  645. if (!tx_desc) {
  646. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  647. return NULL;
  648. }
  649. /* Flow control/Congestion Control counters */
  650. qdf_atomic_inc(&pdev->num_tx_outstanding);
  651. /* Initialize the SW tx descriptor */
  652. tx_desc->nbuf = nbuf;
  653. tx_desc->frm_type = msdu_info->frm_type;
  654. tx_desc->tx_encap_type = vdev->tx_encap_type;
  655. tx_desc->vdev = vdev;
  656. tx_desc->pdev = pdev;
  657. tx_desc->pkt_offset = 0;
  658. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  659. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  660. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  661. /* Reset the control block */
  662. qdf_nbuf_reset_ctxt(nbuf);
  663. /* Handle scattered frames - TSO/SG/ME */
  664. /* Allocate and prepare an extension descriptor for scattered frames */
  665. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  666. if (!msdu_ext_desc) {
  667. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  668. "%s Tx Extension Descriptor Alloc Fail",
  669. __func__);
  670. goto failure;
  671. }
  672. #if TQM_BYPASS_WAR
  673. /* Temporary WAR due to TQM VP issues */
  674. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  675. qdf_atomic_inc(&pdev->num_tx_exception);
  676. #endif
  677. if (qdf_unlikely(msdu_info->exception_fw))
  678. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  679. tx_desc->msdu_ext_desc = msdu_ext_desc;
  680. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  681. return tx_desc;
  682. failure:
  683. dp_tx_desc_release(tx_desc, desc_pool_id);
  684. return NULL;
  685. }
  686. /**
  687. * dp_tx_prepare_raw() - Prepare RAW packet TX
  688. * @vdev: DP vdev handle
  689. * @nbuf: buffer pointer
  690. * @seg_info: Pointer to Segment info Descriptor to be prepared
  691. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  692. * descriptor
  693. *
  694. * Return:
  695. */
  696. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  697. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  698. {
  699. qdf_nbuf_t curr_nbuf = NULL;
  700. uint16_t total_len = 0;
  701. qdf_dma_addr_t paddr;
  702. int32_t i;
  703. int32_t mapped_buf_num = 0;
  704. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  705. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  706. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  707. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  708. if (vdev->raw_mode_war &&
  709. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  710. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  711. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  712. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  713. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  714. QDF_DMA_TO_DEVICE)) {
  715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  716. "%s dma map error ", __func__);
  717. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  718. mapped_buf_num = i;
  719. goto error;
  720. }
  721. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  722. seg_info->frags[i].paddr_lo = paddr;
  723. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  724. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  725. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  726. total_len += qdf_nbuf_len(curr_nbuf);
  727. }
  728. seg_info->frag_cnt = i;
  729. seg_info->total_len = total_len;
  730. seg_info->next = NULL;
  731. sg_info->curr_seg = seg_info;
  732. msdu_info->frm_type = dp_tx_frm_raw;
  733. msdu_info->num_seg = 1;
  734. return nbuf;
  735. error:
  736. i = 0;
  737. while (nbuf) {
  738. curr_nbuf = nbuf;
  739. if (i < mapped_buf_num) {
  740. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  741. i++;
  742. }
  743. nbuf = qdf_nbuf_next(nbuf);
  744. qdf_nbuf_free(curr_nbuf);
  745. }
  746. return NULL;
  747. }
  748. /**
  749. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  750. * @soc: DP Soc Handle
  751. * @vdev: DP vdev handle
  752. * @tx_desc: Tx Descriptor Handle
  753. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  754. * @fw_metadata: Metadata to send to Target Firmware along with frame
  755. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  756. * @tx_exc_metadata: Handle that holds exception path meta data
  757. *
  758. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  759. * from software Tx descriptor
  760. *
  761. * Return:
  762. */
  763. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  764. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  765. uint16_t fw_metadata, uint8_t ring_id,
  766. struct cdp_tx_exception_metadata
  767. *tx_exc_metadata)
  768. {
  769. uint8_t type;
  770. uint16_t length;
  771. void *hal_tx_desc, *hal_tx_desc_cached;
  772. qdf_dma_addr_t dma_addr;
  773. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  774. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  775. tx_exc_metadata->sec_type : vdev->sec_type);
  776. /* Return Buffer Manager ID */
  777. uint8_t bm_id = ring_id;
  778. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  779. hal_tx_desc_cached = (void *) cached_desc;
  780. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  781. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  782. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  783. type = HAL_TX_BUF_TYPE_EXT_DESC;
  784. dma_addr = tx_desc->msdu_ext_desc->paddr;
  785. } else {
  786. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  787. type = HAL_TX_BUF_TYPE_BUFFER;
  788. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  789. }
  790. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  791. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  792. dma_addr, bm_id, tx_desc->id,
  793. type, soc->hal_soc);
  794. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  795. return QDF_STATUS_E_RESOURCES;
  796. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  797. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  798. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  799. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  800. vdev->pdev->pdev_id);
  801. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  802. vdev->search_type);
  803. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  804. vdev->bss_ast_hash);
  805. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  806. vdev->dscp_tid_map_id);
  807. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  808. sec_type_map[sec_type]);
  809. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  810. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  811. __func__, length, type, (uint64_t)dma_addr,
  812. tx_desc->pkt_offset, tx_desc->id);
  813. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  814. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  815. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  816. vdev->hal_desc_addr_search_flags);
  817. /* verify checksum offload configuration*/
  818. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  819. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  820. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  821. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  822. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  823. }
  824. if (tid != HTT_TX_EXT_TID_INVALID)
  825. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  826. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  827. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  828. /* Sync cached descriptor with HW */
  829. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  830. if (!hal_tx_desc) {
  831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  832. "%s TCL ring full ring_id:%d", __func__, ring_id);
  833. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  834. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  835. return QDF_STATUS_E_RESOURCES;
  836. }
  837. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  838. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  839. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  840. return QDF_STATUS_SUCCESS;
  841. }
  842. /**
  843. * dp_cce_classify() - Classify the frame based on CCE rules
  844. * @vdev: DP vdev handle
  845. * @nbuf: skb
  846. *
  847. * Classify frames based on CCE rules
  848. * Return: bool( true if classified,
  849. * else false)
  850. */
  851. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  852. {
  853. struct ether_header *eh = NULL;
  854. uint16_t ether_type;
  855. qdf_llc_t *llcHdr;
  856. qdf_nbuf_t nbuf_clone = NULL;
  857. qdf_dot3_qosframe_t *qos_wh = NULL;
  858. /* for mesh packets don't do any classification */
  859. if (qdf_unlikely(vdev->mesh_vdev))
  860. return false;
  861. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  862. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  863. ether_type = eh->ether_type;
  864. llcHdr = (qdf_llc_t *)(nbuf->data +
  865. sizeof(struct ether_header));
  866. } else {
  867. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  868. /* For encrypted packets don't do any classification */
  869. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  870. return false;
  871. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  872. if (qdf_unlikely(
  873. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  874. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  875. ether_type = *(uint16_t *)(nbuf->data
  876. + QDF_IEEE80211_4ADDR_HDR_LEN
  877. + sizeof(qdf_llc_t)
  878. - sizeof(ether_type));
  879. llcHdr = (qdf_llc_t *)(nbuf->data +
  880. QDF_IEEE80211_4ADDR_HDR_LEN);
  881. } else {
  882. ether_type = *(uint16_t *)(nbuf->data
  883. + QDF_IEEE80211_3ADDR_HDR_LEN
  884. + sizeof(qdf_llc_t)
  885. - sizeof(ether_type));
  886. llcHdr = (qdf_llc_t *)(nbuf->data +
  887. QDF_IEEE80211_3ADDR_HDR_LEN);
  888. }
  889. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  890. && (ether_type ==
  891. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  892. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  893. return true;
  894. }
  895. }
  896. return false;
  897. }
  898. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  899. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  900. sizeof(*llcHdr));
  901. nbuf_clone = qdf_nbuf_clone(nbuf);
  902. if (qdf_unlikely(nbuf_clone)) {
  903. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  904. if (ether_type == htons(ETHERTYPE_8021Q)) {
  905. qdf_nbuf_pull_head(nbuf_clone,
  906. sizeof(qdf_net_vlanhdr_t));
  907. }
  908. }
  909. } else {
  910. if (ether_type == htons(ETHERTYPE_8021Q)) {
  911. nbuf_clone = qdf_nbuf_clone(nbuf);
  912. if (qdf_unlikely(nbuf_clone)) {
  913. qdf_nbuf_pull_head(nbuf_clone,
  914. sizeof(qdf_net_vlanhdr_t));
  915. }
  916. }
  917. }
  918. if (qdf_unlikely(nbuf_clone))
  919. nbuf = nbuf_clone;
  920. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  921. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  922. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  923. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  924. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  925. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  926. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  927. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  928. if (qdf_unlikely(nbuf_clone != NULL))
  929. qdf_nbuf_free(nbuf_clone);
  930. return true;
  931. }
  932. if (qdf_unlikely(nbuf_clone != NULL))
  933. qdf_nbuf_free(nbuf_clone);
  934. return false;
  935. }
  936. /**
  937. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  938. * @vdev: DP vdev handle
  939. * @nbuf: skb
  940. *
  941. * Extract the DSCP or PCP information from frame and map into TID value.
  942. * Software based TID classification is required when more than 2 DSCP-TID
  943. * mapping tables are needed.
  944. * Hardware supports 2 DSCP-TID mapping tables
  945. *
  946. * Return: void
  947. */
  948. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  949. struct dp_tx_msdu_info_s *msdu_info)
  950. {
  951. uint8_t tos = 0, dscp_tid_override = 0;
  952. uint8_t *hdr_ptr, *L3datap;
  953. uint8_t is_mcast = 0;
  954. struct ether_header *eh = NULL;
  955. qdf_ethervlan_header_t *evh = NULL;
  956. uint16_t ether_type;
  957. qdf_llc_t *llcHdr;
  958. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  959. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  960. if (vdev->dscp_tid_map_id <= 1)
  961. return;
  962. /* for mesh packets don't do any classification */
  963. if (qdf_unlikely(vdev->mesh_vdev))
  964. return;
  965. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  966. eh = (struct ether_header *) nbuf->data;
  967. hdr_ptr = eh->ether_dhost;
  968. L3datap = hdr_ptr + sizeof(struct ether_header);
  969. } else {
  970. qdf_dot3_qosframe_t *qos_wh =
  971. (qdf_dot3_qosframe_t *) nbuf->data;
  972. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  973. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  974. return;
  975. }
  976. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  977. ether_type = eh->ether_type;
  978. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  979. /*
  980. * Check if packet is dot3 or eth2 type.
  981. */
  982. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  983. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  984. sizeof(*llcHdr));
  985. if (ether_type == htons(ETHERTYPE_8021Q)) {
  986. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  987. sizeof(*llcHdr);
  988. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  989. + sizeof(*llcHdr) +
  990. sizeof(qdf_net_vlanhdr_t));
  991. } else {
  992. L3datap = hdr_ptr + sizeof(struct ether_header) +
  993. sizeof(*llcHdr);
  994. }
  995. } else {
  996. if (ether_type == htons(ETHERTYPE_8021Q)) {
  997. evh = (qdf_ethervlan_header_t *) eh;
  998. ether_type = evh->ether_type;
  999. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1000. }
  1001. }
  1002. /*
  1003. * Find priority from IP TOS DSCP field
  1004. */
  1005. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1006. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1007. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1008. /* Only for unicast frames */
  1009. if (!is_mcast) {
  1010. /* send it on VO queue */
  1011. msdu_info->tid = DP_VO_TID;
  1012. }
  1013. } else {
  1014. /*
  1015. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1016. * from TOS byte.
  1017. */
  1018. tos = ip->ip_tos;
  1019. dscp_tid_override = 1;
  1020. }
  1021. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1022. /* TODO
  1023. * use flowlabel
  1024. *igmpmld cases to be handled in phase 2
  1025. */
  1026. unsigned long ver_pri_flowlabel;
  1027. unsigned long pri;
  1028. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1029. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1030. DP_IPV6_PRIORITY_SHIFT;
  1031. tos = pri;
  1032. dscp_tid_override = 1;
  1033. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1034. msdu_info->tid = DP_VO_TID;
  1035. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1036. /* Only for unicast frames */
  1037. if (!is_mcast) {
  1038. /* send ucast arp on VO queue */
  1039. msdu_info->tid = DP_VO_TID;
  1040. }
  1041. }
  1042. /*
  1043. * Assign all MCAST packets to BE
  1044. */
  1045. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1046. if (is_mcast) {
  1047. tos = 0;
  1048. dscp_tid_override = 1;
  1049. }
  1050. }
  1051. if (dscp_tid_override == 1) {
  1052. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1053. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1054. }
  1055. return;
  1056. }
  1057. #ifdef CONVERGED_TDLS_ENABLE
  1058. /**
  1059. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1060. * @tx_desc: TX descriptor
  1061. *
  1062. * Return: None
  1063. */
  1064. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1065. {
  1066. if (tx_desc->vdev) {
  1067. if (tx_desc->vdev->is_tdls_frame)
  1068. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1069. tx_desc->vdev->is_tdls_frame = false;
  1070. }
  1071. }
  1072. /**
  1073. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1074. * @tx_desc: TX descriptor
  1075. * @vdev: datapath vdev handle
  1076. *
  1077. * Return: None
  1078. */
  1079. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1080. struct dp_vdev *vdev)
  1081. {
  1082. struct hal_tx_completion_status ts = {0};
  1083. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1084. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1085. if (vdev->tx_non_std_data_callback.func) {
  1086. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1087. vdev->tx_non_std_data_callback.func(
  1088. vdev->tx_non_std_data_callback.ctxt,
  1089. nbuf, ts.status);
  1090. return;
  1091. }
  1092. }
  1093. #endif
  1094. /**
  1095. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1096. * @vdev: DP vdev handle
  1097. * @nbuf: skb
  1098. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1099. * @meta_data: Metadata to the fw
  1100. * @tx_q: Tx queue to be used for this Tx frame
  1101. * @peer_id: peer_id of the peer in case of NAWDS frames
  1102. * @tx_exc_metadata: Handle that holds exception path metadata
  1103. *
  1104. * Return: NULL on success,
  1105. * nbuf when it fails to send
  1106. */
  1107. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1108. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1109. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1110. {
  1111. struct dp_pdev *pdev = vdev->pdev;
  1112. struct dp_soc *soc = pdev->soc;
  1113. struct dp_tx_desc_s *tx_desc;
  1114. QDF_STATUS status;
  1115. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1116. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1117. uint16_t htt_tcl_metadata = 0;
  1118. uint8_t tid = msdu_info->tid;
  1119. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1120. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1121. msdu_info, tx_exc_metadata);
  1122. if (!tx_desc) {
  1123. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1124. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1125. __func__, vdev, tx_q->desc_pool_id);
  1126. return nbuf;
  1127. }
  1128. if (qdf_unlikely(soc->cce_disable)) {
  1129. if (dp_cce_classify(vdev, nbuf) == true) {
  1130. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1131. tid = DP_VO_TID;
  1132. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1133. }
  1134. }
  1135. dp_tx_update_tdls_flags(tx_desc);
  1136. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1137. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1138. "%s %d : HAL RING Access Failed -- %pK",
  1139. __func__, __LINE__, hal_srng);
  1140. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1141. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1142. goto fail_return;
  1143. }
  1144. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1145. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1146. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1147. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1148. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1149. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1150. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1151. peer_id);
  1152. } else
  1153. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1154. if (msdu_info->exception_fw) {
  1155. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1156. }
  1157. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1158. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1159. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1160. if (status != QDF_STATUS_SUCCESS) {
  1161. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1162. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1163. __func__, tx_desc, tx_q->ring_id);
  1164. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1165. goto fail_return;
  1166. }
  1167. nbuf = NULL;
  1168. fail_return:
  1169. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1170. hal_srng_access_end(soc->hal_soc, hal_srng);
  1171. hif_pm_runtime_put(soc->hif_handle);
  1172. } else {
  1173. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1174. }
  1175. return nbuf;
  1176. }
  1177. /**
  1178. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1179. * @vdev: DP vdev handle
  1180. * @nbuf: skb
  1181. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1182. *
  1183. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1184. *
  1185. * Return: NULL on success,
  1186. * nbuf when it fails to send
  1187. */
  1188. #if QDF_LOCK_STATS
  1189. static noinline
  1190. #else
  1191. static
  1192. #endif
  1193. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1194. struct dp_tx_msdu_info_s *msdu_info)
  1195. {
  1196. uint8_t i;
  1197. struct dp_pdev *pdev = vdev->pdev;
  1198. struct dp_soc *soc = pdev->soc;
  1199. struct dp_tx_desc_s *tx_desc;
  1200. bool is_cce_classified = false;
  1201. QDF_STATUS status;
  1202. uint16_t htt_tcl_metadata = 0;
  1203. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1204. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1205. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1206. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1207. "%s %d : HAL RING Access Failed -- %pK",
  1208. __func__, __LINE__, hal_srng);
  1209. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1210. return nbuf;
  1211. }
  1212. if (qdf_unlikely(soc->cce_disable)) {
  1213. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1214. if (is_cce_classified) {
  1215. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1216. msdu_info->tid = DP_VO_TID;
  1217. }
  1218. }
  1219. if (msdu_info->frm_type == dp_tx_frm_me)
  1220. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1221. i = 0;
  1222. /* Print statement to track i and num_seg */
  1223. /*
  1224. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1225. * descriptors using information in msdu_info
  1226. */
  1227. while (i < msdu_info->num_seg) {
  1228. /*
  1229. * Setup Tx descriptor for an MSDU, and MSDU extension
  1230. * descriptor
  1231. */
  1232. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1233. tx_q->desc_pool_id);
  1234. if (!tx_desc) {
  1235. if (msdu_info->frm_type == dp_tx_frm_me) {
  1236. dp_tx_me_free_buf(pdev,
  1237. (void *)(msdu_info->u.sg_info
  1238. .curr_seg->frags[0].vaddr));
  1239. }
  1240. goto done;
  1241. }
  1242. if (msdu_info->frm_type == dp_tx_frm_me) {
  1243. tx_desc->me_buffer =
  1244. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1245. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1246. }
  1247. if (is_cce_classified)
  1248. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1249. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1250. if (msdu_info->exception_fw) {
  1251. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1252. }
  1253. /*
  1254. * Enqueue the Tx MSDU descriptor to HW for transmit
  1255. */
  1256. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1257. htt_tcl_metadata, tx_q->ring_id, NULL);
  1258. if (status != QDF_STATUS_SUCCESS) {
  1259. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1260. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1261. __func__, tx_desc, tx_q->ring_id);
  1262. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1263. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1264. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1265. goto done;
  1266. }
  1267. /*
  1268. * TODO
  1269. * if tso_info structure can be modified to have curr_seg
  1270. * as first element, following 2 blocks of code (for TSO and SG)
  1271. * can be combined into 1
  1272. */
  1273. /*
  1274. * For frames with multiple segments (TSO, ME), jump to next
  1275. * segment.
  1276. */
  1277. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1278. if (msdu_info->u.tso_info.curr_seg->next) {
  1279. msdu_info->u.tso_info.curr_seg =
  1280. msdu_info->u.tso_info.curr_seg->next;
  1281. /*
  1282. * If this is a jumbo nbuf, then increment the number of
  1283. * nbuf users for each additional segment of the msdu.
  1284. * This will ensure that the skb is freed only after
  1285. * receiving tx completion for all segments of an nbuf
  1286. */
  1287. qdf_nbuf_inc_users(nbuf);
  1288. /* Check with MCL if this is needed */
  1289. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1290. }
  1291. }
  1292. /*
  1293. * For Multicast-Unicast converted packets,
  1294. * each converted frame (for a client) is represented as
  1295. * 1 segment
  1296. */
  1297. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1298. (msdu_info->frm_type == dp_tx_frm_me)) {
  1299. if (msdu_info->u.sg_info.curr_seg->next) {
  1300. msdu_info->u.sg_info.curr_seg =
  1301. msdu_info->u.sg_info.curr_seg->next;
  1302. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1303. }
  1304. }
  1305. i++;
  1306. }
  1307. nbuf = NULL;
  1308. done:
  1309. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1310. hal_srng_access_end(soc->hal_soc, hal_srng);
  1311. hif_pm_runtime_put(soc->hif_handle);
  1312. } else {
  1313. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1314. }
  1315. return nbuf;
  1316. }
  1317. /**
  1318. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1319. * for SG frames
  1320. * @vdev: DP vdev handle
  1321. * @nbuf: skb
  1322. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1323. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1324. *
  1325. * Return: NULL on success,
  1326. * nbuf when it fails to send
  1327. */
  1328. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1329. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1330. {
  1331. uint32_t cur_frag, nr_frags;
  1332. qdf_dma_addr_t paddr;
  1333. struct dp_tx_sg_info_s *sg_info;
  1334. sg_info = &msdu_info->u.sg_info;
  1335. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1336. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1337. QDF_DMA_TO_DEVICE)) {
  1338. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1339. "dma map error");
  1340. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1341. qdf_nbuf_free(nbuf);
  1342. return NULL;
  1343. }
  1344. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1345. seg_info->frags[0].paddr_lo = paddr;
  1346. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1347. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1348. seg_info->frags[0].vaddr = (void *) nbuf;
  1349. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1350. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1351. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1352. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1353. "frag dma map error");
  1354. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1355. qdf_nbuf_free(nbuf);
  1356. return NULL;
  1357. }
  1358. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1359. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1360. seg_info->frags[cur_frag + 1].paddr_hi =
  1361. ((uint64_t) paddr) >> 32;
  1362. seg_info->frags[cur_frag + 1].len =
  1363. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1364. }
  1365. seg_info->frag_cnt = (cur_frag + 1);
  1366. seg_info->total_len = qdf_nbuf_len(nbuf);
  1367. seg_info->next = NULL;
  1368. sg_info->curr_seg = seg_info;
  1369. msdu_info->frm_type = dp_tx_frm_sg;
  1370. msdu_info->num_seg = 1;
  1371. return nbuf;
  1372. }
  1373. #ifdef MESH_MODE_SUPPORT
  1374. /**
  1375. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1376. and prepare msdu_info for mesh frames.
  1377. * @vdev: DP vdev handle
  1378. * @nbuf: skb
  1379. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1380. *
  1381. * Return: NULL on failure,
  1382. * nbuf when extracted successfully
  1383. */
  1384. static
  1385. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1386. struct dp_tx_msdu_info_s *msdu_info)
  1387. {
  1388. struct meta_hdr_s *mhdr;
  1389. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1390. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1391. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1392. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1393. msdu_info->exception_fw = 0;
  1394. goto remove_meta_hdr;
  1395. }
  1396. msdu_info->exception_fw = 1;
  1397. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1398. meta_data->host_tx_desc_pool = 1;
  1399. meta_data->update_peer_cache = 1;
  1400. meta_data->learning_frame = 1;
  1401. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1402. meta_data->power = mhdr->power;
  1403. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1404. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1405. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1406. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1407. meta_data->dyn_bw = 1;
  1408. meta_data->valid_pwr = 1;
  1409. meta_data->valid_mcs_mask = 1;
  1410. meta_data->valid_nss_mask = 1;
  1411. meta_data->valid_preamble_type = 1;
  1412. meta_data->valid_retries = 1;
  1413. meta_data->valid_bw_info = 1;
  1414. }
  1415. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1416. meta_data->encrypt_type = 0;
  1417. meta_data->valid_encrypt_type = 1;
  1418. meta_data->learning_frame = 0;
  1419. }
  1420. meta_data->valid_key_flags = 1;
  1421. meta_data->key_flags = (mhdr->keyix & 0x3);
  1422. remove_meta_hdr:
  1423. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1424. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1425. "qdf_nbuf_pull_head failed");
  1426. qdf_nbuf_free(nbuf);
  1427. return NULL;
  1428. }
  1429. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1430. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1431. else
  1432. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1434. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1435. " tid %d to_fw %d",
  1436. __func__, msdu_info->meta_data[0],
  1437. msdu_info->meta_data[1],
  1438. msdu_info->meta_data[2],
  1439. msdu_info->meta_data[3],
  1440. msdu_info->meta_data[4],
  1441. msdu_info->meta_data[5],
  1442. msdu_info->tid, msdu_info->exception_fw);
  1443. return nbuf;
  1444. }
  1445. #else
  1446. static
  1447. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1448. struct dp_tx_msdu_info_s *msdu_info)
  1449. {
  1450. return nbuf;
  1451. }
  1452. #endif
  1453. #ifdef DP_FEATURE_NAWDS_TX
  1454. /**
  1455. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1456. * @vdev: dp_vdev handle
  1457. * @nbuf: skb
  1458. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1459. * @tx_q: Tx queue to be used for this Tx frame
  1460. * @meta_data: Meta date for mesh
  1461. * @peer_id: peer_id of the peer in case of NAWDS frames
  1462. *
  1463. * return: NULL on success nbuf on failure
  1464. */
  1465. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1466. struct dp_tx_msdu_info_s *msdu_info)
  1467. {
  1468. struct dp_peer *peer = NULL;
  1469. struct dp_soc *soc = vdev->pdev->soc;
  1470. struct dp_ast_entry *ast_entry = NULL;
  1471. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1472. uint16_t peer_id = HTT_INVALID_PEER;
  1473. struct dp_peer *sa_peer = NULL;
  1474. qdf_nbuf_t nbuf_copy;
  1475. qdf_spin_lock_bh(&(soc->ast_lock));
  1476. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1477. if (ast_entry)
  1478. sa_peer = ast_entry->peer;
  1479. qdf_spin_unlock_bh(&(soc->ast_lock));
  1480. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1481. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1482. (peer->nawds_enabled)) {
  1483. if (sa_peer == peer) {
  1484. QDF_TRACE(QDF_MODULE_ID_DP,
  1485. QDF_TRACE_LEVEL_DEBUG,
  1486. " %s: broadcast multicast packet",
  1487. __func__);
  1488. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1489. continue;
  1490. }
  1491. nbuf_copy = qdf_nbuf_copy(nbuf);
  1492. if (!nbuf_copy) {
  1493. QDF_TRACE(QDF_MODULE_ID_DP,
  1494. QDF_TRACE_LEVEL_ERROR,
  1495. "nbuf copy failed");
  1496. }
  1497. peer_id = peer->peer_ids[0];
  1498. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1499. msdu_info, peer_id, NULL);
  1500. if (nbuf_copy != NULL) {
  1501. qdf_nbuf_free(nbuf_copy);
  1502. continue;
  1503. }
  1504. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1505. 1, qdf_nbuf_len(nbuf));
  1506. }
  1507. }
  1508. if (peer_id == HTT_INVALID_PEER)
  1509. return nbuf;
  1510. return NULL;
  1511. }
  1512. #endif
  1513. /**
  1514. * dp_check_exc_metadata() - Checks if parameters are valid
  1515. * @tx_exc - holds all exception path parameters
  1516. *
  1517. * Returns true when all the parameters are valid else false
  1518. *
  1519. */
  1520. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1521. {
  1522. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1523. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1524. tx_exc->sec_type > cdp_num_sec_types) {
  1525. return false;
  1526. }
  1527. return true;
  1528. }
  1529. /**
  1530. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1531. * @vap_dev: DP vdev handle
  1532. * @nbuf: skb
  1533. * @tx_exc_metadata: Handle that holds exception path meta data
  1534. *
  1535. * Entry point for Core Tx layer (DP_TX) invoked from
  1536. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1537. *
  1538. * Return: NULL on success,
  1539. * nbuf when it fails to send
  1540. */
  1541. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1542. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1543. {
  1544. struct ether_header *eh = NULL;
  1545. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1546. struct dp_tx_msdu_info_s msdu_info;
  1547. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1548. msdu_info.tid = tx_exc_metadata->tid;
  1549. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1550. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1551. "%s , skb %pM",
  1552. __func__, nbuf->data);
  1553. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1554. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1555. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1556. "Invalid parameters in exception path");
  1557. goto fail;
  1558. }
  1559. /* Basic sanity checks for unsupported packets */
  1560. /* MESH mode */
  1561. if (qdf_unlikely(vdev->mesh_vdev)) {
  1562. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1563. "Mesh mode is not supported in exception path");
  1564. goto fail;
  1565. }
  1566. /* TSO or SG */
  1567. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1568. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1570. "TSO and SG are not supported in exception path");
  1571. goto fail;
  1572. }
  1573. /* RAW */
  1574. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1576. "Raw frame is not supported in exception path");
  1577. goto fail;
  1578. }
  1579. /* Mcast enhancement*/
  1580. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1581. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1583. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1584. }
  1585. }
  1586. /*
  1587. * Get HW Queue to use for this frame.
  1588. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1589. * dedicated for data and 1 for command.
  1590. * "queue_id" maps to one hardware ring.
  1591. * With each ring, we also associate a unique Tx descriptor pool
  1592. * to minimize lock contention for these resources.
  1593. */
  1594. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1595. /* Single linear frame */
  1596. /*
  1597. * If nbuf is a simple linear frame, use send_single function to
  1598. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1599. * SRNG. There is no need to setup a MSDU extension descriptor.
  1600. */
  1601. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1602. tx_exc_metadata->peer_id, tx_exc_metadata);
  1603. return nbuf;
  1604. fail:
  1605. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1606. "pkt send failed");
  1607. return nbuf;
  1608. }
  1609. /**
  1610. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1611. * @vap_dev: DP vdev handle
  1612. * @nbuf: skb
  1613. *
  1614. * Entry point for Core Tx layer (DP_TX) invoked from
  1615. * hard_start_xmit in OSIF/HDD
  1616. *
  1617. * Return: NULL on success,
  1618. * nbuf when it fails to send
  1619. */
  1620. #ifdef MESH_MODE_SUPPORT
  1621. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1622. {
  1623. struct meta_hdr_s *mhdr;
  1624. qdf_nbuf_t nbuf_mesh = NULL;
  1625. qdf_nbuf_t nbuf_clone = NULL;
  1626. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1627. uint8_t no_enc_frame = 0;
  1628. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1629. if (nbuf_mesh == NULL) {
  1630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1631. "qdf_nbuf_unshare failed");
  1632. return nbuf;
  1633. }
  1634. nbuf = nbuf_mesh;
  1635. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1636. if ((vdev->sec_type != cdp_sec_type_none) &&
  1637. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1638. no_enc_frame = 1;
  1639. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1640. !no_enc_frame) {
  1641. nbuf_clone = qdf_nbuf_clone(nbuf);
  1642. if (nbuf_clone == NULL) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1644. "qdf_nbuf_clone failed");
  1645. return nbuf;
  1646. }
  1647. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1648. }
  1649. if (nbuf_clone) {
  1650. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1651. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1652. } else {
  1653. qdf_nbuf_free(nbuf_clone);
  1654. }
  1655. }
  1656. if (no_enc_frame)
  1657. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1658. else
  1659. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1660. nbuf = dp_tx_send(vap_dev, nbuf);
  1661. if ((nbuf == NULL) && no_enc_frame) {
  1662. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1663. }
  1664. return nbuf;
  1665. }
  1666. #else
  1667. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1668. {
  1669. return dp_tx_send(vap_dev, nbuf);
  1670. }
  1671. #endif
  1672. /**
  1673. * dp_tx_send() - Transmit a frame on a given VAP
  1674. * @vap_dev: DP vdev handle
  1675. * @nbuf: skb
  1676. *
  1677. * Entry point for Core Tx layer (DP_TX) invoked from
  1678. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1679. * cases
  1680. *
  1681. * Return: NULL on success,
  1682. * nbuf when it fails to send
  1683. */
  1684. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1685. {
  1686. struct ether_header *eh = NULL;
  1687. struct dp_tx_msdu_info_s msdu_info;
  1688. struct dp_tx_seg_info_s seg_info;
  1689. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1690. uint16_t peer_id = HTT_INVALID_PEER;
  1691. qdf_nbuf_t nbuf_mesh = NULL;
  1692. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1693. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1694. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1695. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1696. "%s , skb %pM",
  1697. __func__, nbuf->data);
  1698. /*
  1699. * Set Default Host TID value to invalid TID
  1700. * (TID override disabled)
  1701. */
  1702. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1703. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1704. if (qdf_unlikely(vdev->mesh_vdev)) {
  1705. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1706. &msdu_info);
  1707. if (nbuf_mesh == NULL) {
  1708. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1709. "Extracting mesh metadata failed");
  1710. return nbuf;
  1711. }
  1712. nbuf = nbuf_mesh;
  1713. }
  1714. /*
  1715. * Get HW Queue to use for this frame.
  1716. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1717. * dedicated for data and 1 for command.
  1718. * "queue_id" maps to one hardware ring.
  1719. * With each ring, we also associate a unique Tx descriptor pool
  1720. * to minimize lock contention for these resources.
  1721. */
  1722. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1723. /*
  1724. * TCL H/W supports 2 DSCP-TID mapping tables.
  1725. * Table 1 - Default DSCP-TID mapping table
  1726. * Table 2 - 1 DSCP-TID override table
  1727. *
  1728. * If we need a different DSCP-TID mapping for this vap,
  1729. * call tid_classify to extract DSCP/ToS from frame and
  1730. * map to a TID and store in msdu_info. This is later used
  1731. * to fill in TCL Input descriptor (per-packet TID override).
  1732. */
  1733. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1734. /*
  1735. * Classify the frame and call corresponding
  1736. * "prepare" function which extracts the segment (TSO)
  1737. * and fragmentation information (for TSO , SG, ME, or Raw)
  1738. * into MSDU_INFO structure which is later used to fill
  1739. * SW and HW descriptors.
  1740. */
  1741. if (qdf_nbuf_is_tso(nbuf)) {
  1742. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1743. "%s TSO frame %pK", __func__, vdev);
  1744. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1745. qdf_nbuf_len(nbuf));
  1746. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1747. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1748. qdf_nbuf_len(nbuf));
  1749. return nbuf;
  1750. }
  1751. goto send_multiple;
  1752. }
  1753. /* SG */
  1754. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1755. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1757. "%s non-TSO SG frame %pK", __func__, vdev);
  1758. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1759. qdf_nbuf_len(nbuf));
  1760. goto send_multiple;
  1761. }
  1762. #ifdef ATH_SUPPORT_IQUE
  1763. /* Mcast to Ucast Conversion*/
  1764. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1765. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1766. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1767. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1768. "%s Mcast frm for ME %pK", __func__, vdev);
  1769. DP_STATS_INC_PKT(vdev,
  1770. tx_i.mcast_en.mcast_pkt, 1,
  1771. qdf_nbuf_len(nbuf));
  1772. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1773. QDF_STATUS_SUCCESS) {
  1774. return NULL;
  1775. }
  1776. }
  1777. }
  1778. #endif
  1779. /* RAW */
  1780. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1781. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1782. if (nbuf == NULL)
  1783. return NULL;
  1784. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1785. "%s Raw frame %pK", __func__, vdev);
  1786. goto send_multiple;
  1787. }
  1788. /* Single linear frame */
  1789. /*
  1790. * If nbuf is a simple linear frame, use send_single function to
  1791. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1792. * SRNG. There is no need to setup a MSDU extension descriptor.
  1793. */
  1794. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1795. return nbuf;
  1796. send_multiple:
  1797. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1798. return nbuf;
  1799. }
  1800. /**
  1801. * dp_tx_reinject_handler() - Tx Reinject Handler
  1802. * @tx_desc: software descriptor head pointer
  1803. * @status : Tx completion status from HTT descriptor
  1804. *
  1805. * This function reinjects frames back to Target.
  1806. * Todo - Host queue needs to be added
  1807. *
  1808. * Return: none
  1809. */
  1810. static
  1811. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1812. {
  1813. struct dp_vdev *vdev;
  1814. struct dp_peer *peer = NULL;
  1815. uint32_t peer_id = HTT_INVALID_PEER;
  1816. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1817. qdf_nbuf_t nbuf_copy = NULL;
  1818. struct dp_tx_msdu_info_s msdu_info;
  1819. struct dp_peer *sa_peer = NULL;
  1820. struct dp_ast_entry *ast_entry = NULL;
  1821. struct dp_soc *soc = NULL;
  1822. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1823. #ifdef WDS_VENDOR_EXTENSION
  1824. int is_mcast = 0, is_ucast = 0;
  1825. int num_peers_3addr = 0;
  1826. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1827. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1828. #endif
  1829. vdev = tx_desc->vdev;
  1830. soc = vdev->pdev->soc;
  1831. qdf_assert(vdev);
  1832. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1833. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1834. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1835. "%s Tx reinject path", __func__);
  1836. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1837. qdf_nbuf_len(tx_desc->nbuf));
  1838. qdf_spin_lock_bh(&(soc->ast_lock));
  1839. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1840. if (ast_entry)
  1841. sa_peer = ast_entry->peer;
  1842. qdf_spin_unlock_bh(&(soc->ast_lock));
  1843. #ifdef WDS_VENDOR_EXTENSION
  1844. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1845. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1846. } else {
  1847. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1848. }
  1849. is_ucast = !is_mcast;
  1850. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1851. if (peer->bss_peer)
  1852. continue;
  1853. /* Detect wds peers that use 3-addr framing for mcast.
  1854. * if there are any, the bss_peer is used to send the
  1855. * the mcast frame using 3-addr format. all wds enabled
  1856. * peers that use 4-addr framing for mcast frames will
  1857. * be duplicated and sent as 4-addr frames below.
  1858. */
  1859. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1860. num_peers_3addr = 1;
  1861. break;
  1862. }
  1863. }
  1864. #endif
  1865. if (qdf_unlikely(vdev->mesh_vdev)) {
  1866. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1867. } else {
  1868. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1869. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1870. #ifdef WDS_VENDOR_EXTENSION
  1871. /*
  1872. * . if 3-addr STA, then send on BSS Peer
  1873. * . if Peer WDS enabled and accept 4-addr mcast,
  1874. * send mcast on that peer only
  1875. * . if Peer WDS enabled and accept 4-addr ucast,
  1876. * send ucast on that peer only
  1877. */
  1878. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1879. (peer->wds_enabled &&
  1880. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1881. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1882. #else
  1883. ((peer->bss_peer &&
  1884. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1885. peer->nawds_enabled)) {
  1886. #endif
  1887. peer_id = DP_INVALID_PEER;
  1888. if (peer->nawds_enabled) {
  1889. peer_id = peer->peer_ids[0];
  1890. if (sa_peer == peer) {
  1891. QDF_TRACE(
  1892. QDF_MODULE_ID_DP,
  1893. QDF_TRACE_LEVEL_DEBUG,
  1894. " %s: multicast packet",
  1895. __func__);
  1896. DP_STATS_INC(peer,
  1897. tx.nawds_mcast_drop, 1);
  1898. continue;
  1899. }
  1900. }
  1901. nbuf_copy = qdf_nbuf_copy(nbuf);
  1902. if (!nbuf_copy) {
  1903. QDF_TRACE(QDF_MODULE_ID_DP,
  1904. QDF_TRACE_LEVEL_DEBUG,
  1905. FL("nbuf copy failed"));
  1906. break;
  1907. }
  1908. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1909. nbuf_copy,
  1910. &msdu_info,
  1911. peer_id,
  1912. NULL);
  1913. if (nbuf_copy) {
  1914. QDF_TRACE(QDF_MODULE_ID_DP,
  1915. QDF_TRACE_LEVEL_DEBUG,
  1916. FL("pkt send failed"));
  1917. qdf_nbuf_free(nbuf_copy);
  1918. } else {
  1919. if (peer_id != DP_INVALID_PEER)
  1920. DP_STATS_INC_PKT(peer,
  1921. tx.nawds_mcast,
  1922. 1, qdf_nbuf_len(nbuf));
  1923. }
  1924. }
  1925. }
  1926. }
  1927. if (vdev->nawds_enabled) {
  1928. peer_id = DP_INVALID_PEER;
  1929. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1930. 1, qdf_nbuf_len(nbuf));
  1931. nbuf = dp_tx_send_msdu_single(vdev,
  1932. nbuf,
  1933. &msdu_info,
  1934. peer_id, NULL);
  1935. if (nbuf) {
  1936. QDF_TRACE(QDF_MODULE_ID_DP,
  1937. QDF_TRACE_LEVEL_DEBUG,
  1938. FL("pkt send failed"));
  1939. qdf_nbuf_free(nbuf);
  1940. }
  1941. } else
  1942. qdf_nbuf_free(nbuf);
  1943. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1944. }
  1945. /**
  1946. * dp_tx_inspect_handler() - Tx Inspect Handler
  1947. * @tx_desc: software descriptor head pointer
  1948. * @status : Tx completion status from HTT descriptor
  1949. *
  1950. * Handles Tx frames sent back to Host for inspection
  1951. * (ProxyARP)
  1952. *
  1953. * Return: none
  1954. */
  1955. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1956. {
  1957. struct dp_soc *soc;
  1958. struct dp_pdev *pdev = tx_desc->pdev;
  1959. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1960. "%s Tx inspect path",
  1961. __func__);
  1962. qdf_assert(pdev);
  1963. soc = pdev->soc;
  1964. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1965. qdf_nbuf_len(tx_desc->nbuf));
  1966. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1967. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1968. }
  1969. #ifdef FEATURE_PERPKT_INFO
  1970. /**
  1971. * dp_get_completion_indication_for_stack() - send completion to stack
  1972. * @soc : dp_soc handle
  1973. * @pdev: dp_pdev handle
  1974. * @peer_id: peer_id of the peer for which completion came
  1975. * @ppdu_id: ppdu_id
  1976. * @first_msdu: first msdu
  1977. * @last_msdu: last msdu
  1978. * @netbuf: Buffer pointer for free
  1979. *
  1980. * This function is used for indication whether buffer needs to be
  1981. * send to stack for free or not
  1982. */
  1983. QDF_STATUS
  1984. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1985. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1986. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1987. {
  1988. struct tx_capture_hdr *ppdu_hdr;
  1989. struct dp_peer *peer = NULL;
  1990. struct ether_header *eh;
  1991. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1992. return QDF_STATUS_E_NOSUPPORT;
  1993. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1994. dp_peer_find_by_id(soc, peer_id);
  1995. if (!peer) {
  1996. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1997. FL("Peer Invalid"));
  1998. return QDF_STATUS_E_INVAL;
  1999. }
  2000. if (pdev->mcopy_mode) {
  2001. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2002. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2003. return QDF_STATUS_E_INVAL;
  2004. }
  2005. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2006. pdev->m_copy_id.tx_peer_id = peer_id;
  2007. }
  2008. eh = (struct ether_header *)qdf_nbuf_data(netbuf);
  2009. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2010. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2011. FL("No headroom"));
  2012. return QDF_STATUS_E_NOMEM;
  2013. }
  2014. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2015. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2016. IEEE80211_ADDR_LEN);
  2017. if (peer->bss_peer) {
  2018. qdf_mem_copy(ppdu_hdr->ra, eh->ether_dhost, IEEE80211_ADDR_LEN);
  2019. } else {
  2020. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2021. IEEE80211_ADDR_LEN);
  2022. }
  2023. ppdu_hdr->ppdu_id = ppdu_id;
  2024. ppdu_hdr->peer_id = peer_id;
  2025. ppdu_hdr->first_msdu = first_msdu;
  2026. ppdu_hdr->last_msdu = last_msdu;
  2027. return QDF_STATUS_SUCCESS;
  2028. }
  2029. /**
  2030. * dp_send_completion_to_stack() - send completion to stack
  2031. * @soc : dp_soc handle
  2032. * @pdev: dp_pdev handle
  2033. * @peer_id: peer_id of the peer for which completion came
  2034. * @ppdu_id: ppdu_id
  2035. * @netbuf: Buffer pointer for free
  2036. *
  2037. * This function is used to send completion to stack
  2038. * to free buffer
  2039. */
  2040. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2041. uint16_t peer_id, uint32_t ppdu_id,
  2042. qdf_nbuf_t netbuf)
  2043. {
  2044. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2045. netbuf, peer_id,
  2046. WDI_NO_VAL, pdev->pdev_id);
  2047. }
  2048. #else
  2049. static QDF_STATUS
  2050. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2051. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  2052. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2053. {
  2054. return QDF_STATUS_E_NOSUPPORT;
  2055. }
  2056. static void
  2057. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2058. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2059. {
  2060. }
  2061. #endif
  2062. /**
  2063. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2064. * @soc: Soc handle
  2065. * @desc: software Tx descriptor to be processed
  2066. *
  2067. * Return: none
  2068. */
  2069. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2070. struct dp_tx_desc_s *desc)
  2071. {
  2072. struct dp_vdev *vdev = desc->vdev;
  2073. qdf_nbuf_t nbuf = desc->nbuf;
  2074. /* If it is TDLS mgmt, don't unmap or free the frame */
  2075. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2076. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2077. /* 0 : MSDU buffer, 1 : MLE */
  2078. if (desc->msdu_ext_desc) {
  2079. /* TSO free */
  2080. if (hal_tx_ext_desc_get_tso_enable(
  2081. desc->msdu_ext_desc->vaddr)) {
  2082. /* unmap eash TSO seg before free the nbuf */
  2083. dp_tx_tso_unmap_segment(soc, desc);
  2084. qdf_nbuf_free(nbuf);
  2085. return;
  2086. }
  2087. }
  2088. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2089. if (qdf_likely(!vdev->mesh_vdev))
  2090. qdf_nbuf_free(nbuf);
  2091. else {
  2092. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2093. qdf_nbuf_free(nbuf);
  2094. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2095. } else
  2096. vdev->osif_tx_free_ext((nbuf));
  2097. }
  2098. }
  2099. /**
  2100. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2101. * @vdev: pointer to dp dev handler
  2102. * @status : Tx completion status from HTT descriptor
  2103. *
  2104. * Handles MEC notify event sent from fw to Host
  2105. *
  2106. * Return: none
  2107. */
  2108. #ifdef FEATURE_WDS
  2109. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2110. {
  2111. struct dp_soc *soc;
  2112. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2113. struct dp_peer *peer;
  2114. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2115. if (!vdev->wds_enabled)
  2116. return;
  2117. /* MEC required only in STA mode */
  2118. if (vdev->opmode != wlan_op_mode_sta)
  2119. return;
  2120. soc = vdev->pdev->soc;
  2121. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2122. peer = TAILQ_FIRST(&vdev->peer_list);
  2123. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2124. if (!peer) {
  2125. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2126. FL("peer is NULL"));
  2127. return;
  2128. }
  2129. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2130. "%s Tx MEC Handler",
  2131. __func__);
  2132. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2133. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2134. status[(DP_MAC_ADDR_LEN - 2) + i];
  2135. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2136. dp_peer_add_ast(soc,
  2137. peer,
  2138. mac_addr,
  2139. CDP_TXRX_AST_TYPE_MEC,
  2140. flags);
  2141. }
  2142. #endif
  2143. /**
  2144. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2145. * @tx_desc: software descriptor head pointer
  2146. * @status : Tx completion status from HTT descriptor
  2147. *
  2148. * This function will process HTT Tx indication messages from Target
  2149. *
  2150. * Return: none
  2151. */
  2152. static
  2153. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2154. {
  2155. uint8_t tx_status;
  2156. struct dp_pdev *pdev;
  2157. struct dp_vdev *vdev;
  2158. struct dp_soc *soc;
  2159. uint32_t *htt_status_word = (uint32_t *) status;
  2160. qdf_assert(tx_desc->pdev);
  2161. pdev = tx_desc->pdev;
  2162. vdev = tx_desc->vdev;
  2163. soc = pdev->soc;
  2164. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2165. switch (tx_status) {
  2166. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2167. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2168. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2169. {
  2170. dp_tx_comp_free_buf(soc, tx_desc);
  2171. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2172. break;
  2173. }
  2174. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2175. {
  2176. dp_tx_reinject_handler(tx_desc, status);
  2177. break;
  2178. }
  2179. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2180. {
  2181. dp_tx_inspect_handler(tx_desc, status);
  2182. break;
  2183. }
  2184. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2185. {
  2186. dp_tx_mec_handler(vdev, status);
  2187. break;
  2188. }
  2189. default:
  2190. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2191. "%s Invalid HTT tx_status %d",
  2192. __func__, tx_status);
  2193. break;
  2194. }
  2195. }
  2196. #ifdef MESH_MODE_SUPPORT
  2197. /**
  2198. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2199. * in mesh meta header
  2200. * @tx_desc: software descriptor head pointer
  2201. * @ts: pointer to tx completion stats
  2202. * Return: none
  2203. */
  2204. static
  2205. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2206. struct hal_tx_completion_status *ts)
  2207. {
  2208. struct meta_hdr_s *mhdr;
  2209. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2210. if (!tx_desc->msdu_ext_desc) {
  2211. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2213. "netbuf %pK offset %d",
  2214. netbuf, tx_desc->pkt_offset);
  2215. return;
  2216. }
  2217. }
  2218. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2220. "netbuf %pK offset %d", netbuf,
  2221. sizeof(struct meta_hdr_s));
  2222. return;
  2223. }
  2224. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2225. mhdr->rssi = ts->ack_frame_rssi;
  2226. mhdr->channel = tx_desc->pdev->operating_channel;
  2227. }
  2228. #else
  2229. static
  2230. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2231. struct hal_tx_completion_status *ts)
  2232. {
  2233. }
  2234. #endif
  2235. /**
  2236. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2237. * @peer: Handle to DP peer
  2238. * @ts: pointer to HAL Tx completion stats
  2239. * @length: MSDU length
  2240. *
  2241. * Return: None
  2242. */
  2243. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2244. struct hal_tx_completion_status *ts, uint32_t length)
  2245. {
  2246. struct dp_pdev *pdev = peer->vdev->pdev;
  2247. struct dp_soc *soc = pdev->soc;
  2248. uint8_t mcs, pkt_type;
  2249. mcs = ts->mcs;
  2250. pkt_type = ts->pkt_type;
  2251. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2252. return;
  2253. if (peer->bss_peer) {
  2254. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2255. } else {
  2256. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2257. }
  2258. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2259. DP_STATS_INCC_PKT(peer, tx.tx_success, 1, length,
  2260. (ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  2261. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2262. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2263. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2264. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2265. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2266. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2267. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2268. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2269. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2270. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2271. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2272. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2273. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2274. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2275. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2276. return;
  2277. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2278. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2279. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2280. if (!(soc->process_tx_status))
  2281. return;
  2282. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2283. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2284. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2285. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2286. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2287. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2288. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2289. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2290. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2291. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2292. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2293. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2294. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2295. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2296. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2297. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2298. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2299. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2300. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2301. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2302. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2303. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2304. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2305. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2306. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2307. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2308. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2309. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2310. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2311. &peer->stats, ts->peer_id,
  2312. UPDATE_PEER_STATS);
  2313. }
  2314. }
  2315. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2316. /**
  2317. * dp_tx_flow_pool_lock() - take flow pool lock
  2318. * @soc: core txrx main context
  2319. * @tx_desc: tx desc
  2320. *
  2321. * Return: None
  2322. */
  2323. static inline
  2324. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2325. struct dp_tx_desc_s *tx_desc)
  2326. {
  2327. struct dp_tx_desc_pool_s *pool;
  2328. uint8_t desc_pool_id;
  2329. desc_pool_id = tx_desc->pool_id;
  2330. pool = &soc->tx_desc[desc_pool_id];
  2331. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2332. }
  2333. /**
  2334. * dp_tx_flow_pool_unlock() - release flow pool lock
  2335. * @soc: core txrx main context
  2336. * @tx_desc: tx desc
  2337. *
  2338. * Return: None
  2339. */
  2340. static inline
  2341. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2342. struct dp_tx_desc_s *tx_desc)
  2343. {
  2344. struct dp_tx_desc_pool_s *pool;
  2345. uint8_t desc_pool_id;
  2346. desc_pool_id = tx_desc->pool_id;
  2347. pool = &soc->tx_desc[desc_pool_id];
  2348. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2349. }
  2350. #else
  2351. static inline
  2352. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2353. {
  2354. }
  2355. static inline
  2356. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2357. {
  2358. }
  2359. #endif
  2360. /**
  2361. * dp_tx_notify_completion() - Notify tx completion for this desc
  2362. * @soc: core txrx main context
  2363. * @tx_desc: tx desc
  2364. * @netbuf: buffer
  2365. *
  2366. * Return: none
  2367. */
  2368. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2369. struct dp_tx_desc_s *tx_desc,
  2370. qdf_nbuf_t netbuf)
  2371. {
  2372. void *osif_dev;
  2373. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2374. qdf_assert(tx_desc);
  2375. dp_tx_flow_pool_lock(soc, tx_desc);
  2376. if (!tx_desc->vdev ||
  2377. !tx_desc->vdev->osif_vdev) {
  2378. dp_tx_flow_pool_unlock(soc, tx_desc);
  2379. return;
  2380. }
  2381. osif_dev = tx_desc->vdev->osif_vdev;
  2382. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2383. dp_tx_flow_pool_unlock(soc, tx_desc);
  2384. if (tx_compl_cbk)
  2385. tx_compl_cbk(netbuf, osif_dev);
  2386. }
  2387. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2388. * @pdev: pdev handle
  2389. * @tid: tid value
  2390. * @txdesc_ts: timestamp from txdesc
  2391. * @ppdu_id: ppdu id
  2392. *
  2393. * Return: none
  2394. */
  2395. #ifdef FEATURE_PERPKT_INFO
  2396. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2397. uint8_t tid,
  2398. uint64_t txdesc_ts,
  2399. uint32_t ppdu_id)
  2400. {
  2401. uint64_t delta_ms;
  2402. struct cdp_tx_sojourn_stats *sojourn_stats;
  2403. if (pdev->enhanced_stats_en == 0)
  2404. return;
  2405. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2406. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2407. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2408. if (!pdev->sojourn_buf)
  2409. return;
  2410. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2411. qdf_nbuf_data(pdev->sojourn_buf);
  2412. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2413. sizeof(struct cdp_tx_sojourn_stats));
  2414. qdf_mem_zero(&pdev->sojourn_stats,
  2415. sizeof(struct cdp_tx_sojourn_stats));
  2416. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2417. pdev->sojourn_buf, HTT_INVALID_PEER,
  2418. WDI_NO_VAL, pdev->pdev_id);
  2419. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2420. }
  2421. if (tid == HTT_INVALID_TID)
  2422. return;
  2423. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2424. txdesc_ts;
  2425. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2426. delta_ms);
  2427. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2428. pdev->sojourn_stats.num_msdus[tid]++;
  2429. }
  2430. #else
  2431. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2432. uint8_t tid,
  2433. uint64_t txdesc_ts,
  2434. uint32_t ppdu_id)
  2435. {
  2436. }
  2437. #endif
  2438. /**
  2439. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2440. * @tx_desc: software descriptor head pointer
  2441. * @length: packet length
  2442. *
  2443. * Return: none
  2444. */
  2445. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2446. uint32_t length)
  2447. {
  2448. struct hal_tx_completion_status ts;
  2449. struct dp_soc *soc = NULL;
  2450. struct dp_vdev *vdev = tx_desc->vdev;
  2451. struct dp_peer *peer = NULL;
  2452. struct ether_header *eh =
  2453. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2454. if (!vdev) {
  2455. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2456. "invalid vdev");
  2457. goto out;
  2458. }
  2459. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  2460. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2461. "-------------------- \n"
  2462. "Tx Completion Stats: \n"
  2463. "-------------------- \n"
  2464. "ack_frame_rssi = %d \n"
  2465. "first_msdu = %d \n"
  2466. "last_msdu = %d \n"
  2467. "msdu_part_of_amsdu = %d \n"
  2468. "rate_stats valid = %d \n"
  2469. "bw = %d \n"
  2470. "pkt_type = %d \n"
  2471. "stbc = %d \n"
  2472. "ldpc = %d \n"
  2473. "sgi = %d \n"
  2474. "mcs = %d \n"
  2475. "ofdma = %d \n"
  2476. "tones_in_ru = %d \n"
  2477. "tsf = %d \n"
  2478. "ppdu_id = %d \n"
  2479. "transmit_cnt = %d \n"
  2480. "tid = %d \n"
  2481. "peer_id = %d ",
  2482. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2483. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2484. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2485. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2486. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2487. ts.peer_id);
  2488. soc = vdev->pdev->soc;
  2489. /* Update SoC level stats */
  2490. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2491. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2492. /* Update per-packet stats */
  2493. if (qdf_unlikely(vdev->mesh_vdev) &&
  2494. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2495. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2496. /* Update peer level stats */
  2497. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2498. if (!peer) {
  2499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2500. "invalid peer");
  2501. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2502. goto out;
  2503. }
  2504. if (qdf_likely(peer->vdev->tx_encap_type ==
  2505. htt_cmn_pkt_type_ethernet)) {
  2506. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2507. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2508. }
  2509. dp_tx_sojourn_stats_process(vdev->pdev, ts.tid,
  2510. tx_desc->timestamp,
  2511. ts.ppdu_id);
  2512. dp_tx_update_peer_stats(peer, &ts, length);
  2513. out:
  2514. return;
  2515. }
  2516. /**
  2517. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2518. * @soc: core txrx main context
  2519. * @comp_head: software descriptor head pointer
  2520. *
  2521. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2522. * and release the software descriptors after processing is complete
  2523. *
  2524. * Return: none
  2525. */
  2526. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2527. struct dp_tx_desc_s *comp_head)
  2528. {
  2529. struct dp_tx_desc_s *desc;
  2530. struct dp_tx_desc_s *next;
  2531. struct hal_tx_completion_status ts = {0};
  2532. uint32_t length;
  2533. struct dp_peer *peer;
  2534. DP_HIST_INIT();
  2535. desc = comp_head;
  2536. while (desc) {
  2537. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2538. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2539. length = qdf_nbuf_len(desc->nbuf);
  2540. /* check tx completion notification */
  2541. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(desc->nbuf))
  2542. dp_tx_notify_completion(soc, desc, desc->nbuf);
  2543. dp_tx_comp_process_tx_status(desc, length);
  2544. DPTRACE(qdf_dp_trace_ptr
  2545. (desc->nbuf,
  2546. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2547. QDF_TRACE_DEFAULT_PDEV_ID,
  2548. qdf_nbuf_data_addr(desc->nbuf),
  2549. sizeof(qdf_nbuf_data(desc->nbuf)),
  2550. desc->id, ts.status)
  2551. );
  2552. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2553. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2554. desc->pdev, ts.peer_id, ts.ppdu_id,
  2555. ts.first_msdu, ts.last_msdu,
  2556. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2557. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2558. QDF_DMA_TO_DEVICE);
  2559. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2560. ts.ppdu_id, desc->nbuf);
  2561. } else {
  2562. dp_tx_comp_free_buf(soc, desc);
  2563. }
  2564. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2565. next = desc->next;
  2566. dp_tx_desc_release(desc, desc->pool_id);
  2567. desc = next;
  2568. }
  2569. DP_TX_HIST_STATS_PER_PDEV();
  2570. }
  2571. /**
  2572. * dp_tx_comp_handler() - Tx completion handler
  2573. * @soc: core txrx main context
  2574. * @ring_id: completion ring id
  2575. * @quota: No. of packets/descriptors that can be serviced in one loop
  2576. *
  2577. * This function will collect hardware release ring element contents and
  2578. * handle descriptor contents. Based on contents, free packet or handle error
  2579. * conditions
  2580. *
  2581. * Return: none
  2582. */
  2583. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2584. {
  2585. void *tx_comp_hal_desc;
  2586. uint8_t buffer_src;
  2587. uint8_t pool_id;
  2588. uint32_t tx_desc_id;
  2589. struct dp_tx_desc_s *tx_desc = NULL;
  2590. struct dp_tx_desc_s *head_desc = NULL;
  2591. struct dp_tx_desc_s *tail_desc = NULL;
  2592. uint32_t num_processed;
  2593. uint32_t count;
  2594. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2595. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2596. "%s %d : HAL RING Access Failed -- %pK",
  2597. __func__, __LINE__, hal_srng);
  2598. return 0;
  2599. }
  2600. num_processed = 0;
  2601. count = 0;
  2602. /* Find head descriptor from completion ring */
  2603. while (qdf_likely(tx_comp_hal_desc =
  2604. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2605. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2606. /* If this buffer was not released by TQM or FW, then it is not
  2607. * Tx completion indication, assert */
  2608. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2609. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2610. QDF_TRACE(QDF_MODULE_ID_DP,
  2611. QDF_TRACE_LEVEL_FATAL,
  2612. "Tx comp release_src != TQM | FW");
  2613. qdf_assert_always(0);
  2614. }
  2615. /* Get descriptor id */
  2616. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2617. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2618. DP_TX_DESC_ID_POOL_OS;
  2619. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2620. continue;
  2621. /* Find Tx descriptor */
  2622. tx_desc = dp_tx_desc_find(soc, pool_id,
  2623. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2624. DP_TX_DESC_ID_PAGE_OS,
  2625. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2626. DP_TX_DESC_ID_OFFSET_OS);
  2627. /*
  2628. * If the release source is FW, process the HTT status
  2629. */
  2630. if (qdf_unlikely(buffer_src ==
  2631. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2632. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2633. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2634. htt_tx_status);
  2635. dp_tx_process_htt_completion(tx_desc,
  2636. htt_tx_status);
  2637. } else {
  2638. /* Pool id is not matching. Error */
  2639. if (tx_desc->pool_id != pool_id) {
  2640. QDF_TRACE(QDF_MODULE_ID_DP,
  2641. QDF_TRACE_LEVEL_FATAL,
  2642. "Tx Comp pool id %d not matched %d",
  2643. pool_id, tx_desc->pool_id);
  2644. qdf_assert_always(0);
  2645. }
  2646. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2647. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2648. QDF_TRACE(QDF_MODULE_ID_DP,
  2649. QDF_TRACE_LEVEL_FATAL,
  2650. "Txdesc invalid, flgs = %x,id = %d",
  2651. tx_desc->flags, tx_desc_id);
  2652. qdf_assert_always(0);
  2653. }
  2654. /* First ring descriptor on the cycle */
  2655. if (!head_desc) {
  2656. head_desc = tx_desc;
  2657. tail_desc = tx_desc;
  2658. }
  2659. tail_desc->next = tx_desc;
  2660. tx_desc->next = NULL;
  2661. tail_desc = tx_desc;
  2662. /* Collect hw completion contents */
  2663. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2664. &tx_desc->comp, 1);
  2665. }
  2666. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2667. /*
  2668. * Processed packet count is more than given quota
  2669. * stop to processing
  2670. */
  2671. if ((num_processed >= quota))
  2672. break;
  2673. count++;
  2674. }
  2675. hal_srng_access_end(soc->hal_soc, hal_srng);
  2676. /* Process the reaped descriptors */
  2677. if (head_desc)
  2678. dp_tx_comp_process_desc(soc, head_desc);
  2679. return num_processed;
  2680. }
  2681. #ifdef CONVERGED_TDLS_ENABLE
  2682. /**
  2683. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2684. *
  2685. * @data_vdev - which vdev should transmit the tx data frames
  2686. * @tx_spec - what non-standard handling to apply to the tx data frames
  2687. * @msdu_list - NULL-terminated list of tx MSDUs
  2688. *
  2689. * Return: NULL on success,
  2690. * nbuf when it fails to send
  2691. */
  2692. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2693. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2694. {
  2695. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2696. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2697. vdev->is_tdls_frame = true;
  2698. return dp_tx_send(vdev_handle, msdu_list);
  2699. }
  2700. #endif
  2701. /**
  2702. * dp_tx_vdev_attach() - attach vdev to dp tx
  2703. * @vdev: virtual device instance
  2704. *
  2705. * Return: QDF_STATUS_SUCCESS: success
  2706. * QDF_STATUS_E_RESOURCES: Error return
  2707. */
  2708. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2709. {
  2710. /*
  2711. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2712. */
  2713. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2714. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2715. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2716. vdev->vdev_id);
  2717. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2718. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2719. /*
  2720. * Set HTT Extension Valid bit to 0 by default
  2721. */
  2722. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2723. dp_tx_vdev_update_search_flags(vdev);
  2724. return QDF_STATUS_SUCCESS;
  2725. }
  2726. /**
  2727. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2728. * @vdev: virtual device instance
  2729. *
  2730. * Return: void
  2731. *
  2732. */
  2733. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2734. {
  2735. /*
  2736. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2737. * for TDLS link
  2738. *
  2739. * Enable AddrY (SA based search) only for non-WDS STA and
  2740. * ProxySTA VAP modes.
  2741. *
  2742. * In all other VAP modes, only DA based search should be
  2743. * enabled
  2744. */
  2745. if (vdev->opmode == wlan_op_mode_sta &&
  2746. vdev->tdls_link_connected)
  2747. vdev->hal_desc_addr_search_flags =
  2748. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2749. else if ((vdev->opmode == wlan_op_mode_sta &&
  2750. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2751. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2752. else
  2753. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2754. if (vdev->opmode == wlan_op_mode_sta)
  2755. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2756. else
  2757. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2758. }
  2759. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2760. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2761. {
  2762. }
  2763. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2764. /* dp_tx_desc_flush() - release resources associated
  2765. * to tx_desc
  2766. * @vdev: virtual device instance
  2767. *
  2768. * This function will free all outstanding Tx buffers,
  2769. * including ME buffer for which either free during
  2770. * completion didn't happened or completion is not
  2771. * received.
  2772. */
  2773. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2774. {
  2775. uint8_t i, num_pool;
  2776. uint32_t j;
  2777. uint32_t num_desc;
  2778. struct dp_soc *soc = vdev->pdev->soc;
  2779. struct dp_tx_desc_s *tx_desc = NULL;
  2780. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2781. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2782. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2783. for (i = 0; i < num_pool; i++) {
  2784. for (j = 0; j < num_desc; j++) {
  2785. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2786. if (tx_desc_pool &&
  2787. tx_desc_pool->desc_pages.cacheable_pages) {
  2788. tx_desc = dp_tx_desc_find(soc, i,
  2789. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2790. DP_TX_DESC_ID_PAGE_OS,
  2791. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2792. DP_TX_DESC_ID_OFFSET_OS);
  2793. if (tx_desc && (tx_desc->vdev == vdev) &&
  2794. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2795. dp_tx_comp_free_buf(soc, tx_desc);
  2796. dp_tx_desc_release(tx_desc, i);
  2797. }
  2798. }
  2799. }
  2800. }
  2801. }
  2802. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2803. /**
  2804. * dp_tx_vdev_detach() - detach vdev from dp tx
  2805. * @vdev: virtual device instance
  2806. *
  2807. * Return: QDF_STATUS_SUCCESS: success
  2808. * QDF_STATUS_E_RESOURCES: Error return
  2809. */
  2810. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2811. {
  2812. dp_tx_desc_flush(vdev);
  2813. return QDF_STATUS_SUCCESS;
  2814. }
  2815. /**
  2816. * dp_tx_pdev_attach() - attach pdev to dp tx
  2817. * @pdev: physical device instance
  2818. *
  2819. * Return: QDF_STATUS_SUCCESS: success
  2820. * QDF_STATUS_E_RESOURCES: Error return
  2821. */
  2822. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2823. {
  2824. struct dp_soc *soc = pdev->soc;
  2825. /* Initialize Flow control counters */
  2826. qdf_atomic_init(&pdev->num_tx_exception);
  2827. qdf_atomic_init(&pdev->num_tx_outstanding);
  2828. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2829. /* Initialize descriptors in TCL Ring */
  2830. hal_tx_init_data_ring(soc->hal_soc,
  2831. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2832. }
  2833. return QDF_STATUS_SUCCESS;
  2834. }
  2835. /**
  2836. * dp_tx_pdev_detach() - detach pdev from dp tx
  2837. * @pdev: physical device instance
  2838. *
  2839. * Return: QDF_STATUS_SUCCESS: success
  2840. * QDF_STATUS_E_RESOURCES: Error return
  2841. */
  2842. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2843. {
  2844. dp_tx_me_exit(pdev);
  2845. return QDF_STATUS_SUCCESS;
  2846. }
  2847. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2848. /* Pools will be allocated dynamically */
  2849. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2850. int num_desc)
  2851. {
  2852. uint8_t i;
  2853. for (i = 0; i < num_pool; i++) {
  2854. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2855. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2856. }
  2857. return 0;
  2858. }
  2859. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2860. {
  2861. uint8_t i;
  2862. for (i = 0; i < num_pool; i++)
  2863. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2864. }
  2865. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2866. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2867. int num_desc)
  2868. {
  2869. uint8_t i;
  2870. /* Allocate software Tx descriptor pools */
  2871. for (i = 0; i < num_pool; i++) {
  2872. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2873. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2874. "%s Tx Desc Pool alloc %d failed %pK",
  2875. __func__, i, soc);
  2876. return ENOMEM;
  2877. }
  2878. }
  2879. return 0;
  2880. }
  2881. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2882. {
  2883. uint8_t i;
  2884. for (i = 0; i < num_pool; i++) {
  2885. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2886. if (dp_tx_desc_pool_free(soc, i)) {
  2887. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2888. "%s Tx Desc Pool Free failed", __func__);
  2889. }
  2890. }
  2891. }
  2892. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2893. /**
  2894. * dp_tx_soc_detach() - detach soc from dp tx
  2895. * @soc: core txrx main context
  2896. *
  2897. * This function will detach dp tx into main device context
  2898. * will free dp tx resource and initialize resources
  2899. *
  2900. * Return: QDF_STATUS_SUCCESS: success
  2901. * QDF_STATUS_E_RESOURCES: Error return
  2902. */
  2903. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2904. {
  2905. uint8_t num_pool;
  2906. uint16_t num_desc;
  2907. uint16_t num_ext_desc;
  2908. uint8_t i;
  2909. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2910. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2911. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2912. dp_tx_flow_control_deinit(soc);
  2913. dp_tx_delete_static_pools(soc, num_pool);
  2914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2915. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  2916. __func__, num_pool, num_desc);
  2917. for (i = 0; i < num_pool; i++) {
  2918. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2919. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2920. "%s Tx Ext Desc Pool Free failed",
  2921. __func__);
  2922. return QDF_STATUS_E_RESOURCES;
  2923. }
  2924. }
  2925. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2926. "%s MSDU Ext Desc Pool %d Free descs = %d",
  2927. __func__, num_pool, num_ext_desc);
  2928. for (i = 0; i < num_pool; i++) {
  2929. dp_tx_tso_desc_pool_free(soc, i);
  2930. }
  2931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2932. "%s TSO Desc Pool %d Free descs = %d",
  2933. __func__, num_pool, num_desc);
  2934. for (i = 0; i < num_pool; i++)
  2935. dp_tx_tso_num_seg_pool_free(soc, i);
  2936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2937. "%s TSO Num of seg Desc Pool %d Free descs = %d",
  2938. __func__, num_pool, num_desc);
  2939. return QDF_STATUS_SUCCESS;
  2940. }
  2941. /**
  2942. * dp_tx_soc_attach() - attach soc to dp tx
  2943. * @soc: core txrx main context
  2944. *
  2945. * This function will attach dp tx into main device context
  2946. * will allocate dp tx resource and initialize resources
  2947. *
  2948. * Return: QDF_STATUS_SUCCESS: success
  2949. * QDF_STATUS_E_RESOURCES: Error return
  2950. */
  2951. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2952. {
  2953. uint8_t i;
  2954. uint8_t num_pool;
  2955. uint32_t num_desc;
  2956. uint32_t num_ext_desc;
  2957. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2958. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2959. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2960. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2961. goto fail;
  2962. dp_tx_flow_control_init(soc);
  2963. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2964. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  2965. __func__, num_pool, num_desc);
  2966. /* Allocate extension tx descriptor pools */
  2967. for (i = 0; i < num_pool; i++) {
  2968. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2969. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2970. "MSDU Ext Desc Pool alloc %d failed %pK",
  2971. i, soc);
  2972. goto fail;
  2973. }
  2974. }
  2975. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2976. "%s MSDU Ext Desc Alloc %d, descs = %d",
  2977. __func__, num_pool, num_ext_desc);
  2978. for (i = 0; i < num_pool; i++) {
  2979. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2980. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2981. "TSO Desc Pool alloc %d failed %pK",
  2982. i, soc);
  2983. goto fail;
  2984. }
  2985. }
  2986. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2987. "%s TSO Desc Alloc %d, descs = %d",
  2988. __func__, num_pool, num_desc);
  2989. for (i = 0; i < num_pool; i++) {
  2990. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2992. "TSO Num of seg Pool alloc %d failed %pK",
  2993. i, soc);
  2994. goto fail;
  2995. }
  2996. }
  2997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2998. "%s TSO Num of seg pool Alloc %d, descs = %d",
  2999. __func__, num_pool, num_desc);
  3000. /* Initialize descriptors in TCL Rings */
  3001. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3002. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3003. hal_tx_init_data_ring(soc->hal_soc,
  3004. soc->tcl_data_ring[i].hal_srng);
  3005. }
  3006. }
  3007. /*
  3008. * todo - Add a runtime config option to enable this.
  3009. */
  3010. /*
  3011. * Due to multiple issues on NPR EMU, enable it selectively
  3012. * only for NPR EMU, should be removed, once NPR platforms
  3013. * are stable.
  3014. */
  3015. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3016. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3017. "%s HAL Tx init Success", __func__);
  3018. return QDF_STATUS_SUCCESS;
  3019. fail:
  3020. /* Detach will take care of freeing only allocated resources */
  3021. dp_tx_soc_detach(soc);
  3022. return QDF_STATUS_E_RESOURCES;
  3023. }
  3024. /*
  3025. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3026. * pdev: pointer to DP PDEV structure
  3027. * seg_info_head: Pointer to the head of list
  3028. *
  3029. * return: void
  3030. */
  3031. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3032. struct dp_tx_seg_info_s *seg_info_head)
  3033. {
  3034. struct dp_tx_me_buf_t *mc_uc_buf;
  3035. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3036. qdf_nbuf_t nbuf = NULL;
  3037. uint64_t phy_addr;
  3038. while (seg_info_head) {
  3039. nbuf = seg_info_head->nbuf;
  3040. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3041. seg_info_head->frags[0].vaddr;
  3042. phy_addr = seg_info_head->frags[0].paddr_hi;
  3043. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3044. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3045. phy_addr,
  3046. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3047. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3048. qdf_nbuf_free(nbuf);
  3049. seg_info_new = seg_info_head;
  3050. seg_info_head = seg_info_head->next;
  3051. qdf_mem_free(seg_info_new);
  3052. }
  3053. }
  3054. /**
  3055. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3056. * @vdev: DP VDEV handle
  3057. * @nbuf: Multicast nbuf
  3058. * @newmac: Table of the clients to which packets have to be sent
  3059. * @new_mac_cnt: No of clients
  3060. *
  3061. * return: no of converted packets
  3062. */
  3063. uint16_t
  3064. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3065. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3066. {
  3067. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3068. struct dp_pdev *pdev = vdev->pdev;
  3069. struct ether_header *eh;
  3070. uint8_t *data;
  3071. uint16_t len;
  3072. /* reference to frame dst addr */
  3073. uint8_t *dstmac;
  3074. /* copy of original frame src addr */
  3075. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3076. /* local index into newmac */
  3077. uint8_t new_mac_idx = 0;
  3078. struct dp_tx_me_buf_t *mc_uc_buf;
  3079. qdf_nbuf_t nbuf_clone;
  3080. struct dp_tx_msdu_info_s msdu_info;
  3081. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3082. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3083. struct dp_tx_seg_info_s *seg_info_new;
  3084. struct dp_tx_frag_info_s data_frag;
  3085. qdf_dma_addr_t paddr_data;
  3086. qdf_dma_addr_t paddr_mcbuf = 0;
  3087. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3088. QDF_STATUS status;
  3089. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3090. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3091. eh = (struct ether_header *) nbuf;
  3092. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3093. len = qdf_nbuf_len(nbuf);
  3094. data = qdf_nbuf_data(nbuf);
  3095. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3096. QDF_DMA_TO_DEVICE);
  3097. if (status) {
  3098. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3099. "Mapping failure Error:%d", status);
  3100. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3101. qdf_nbuf_free(nbuf);
  3102. return 1;
  3103. }
  3104. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3105. /*preparing data fragment*/
  3106. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3107. data_frag.paddr_lo = (uint32_t)paddr_data;
  3108. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3109. data_frag.len = len - DP_MAC_ADDR_LEN;
  3110. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3111. dstmac = newmac[new_mac_idx];
  3112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3113. "added mac addr (%pM)", dstmac);
  3114. /* Check for NULL Mac Address */
  3115. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3116. continue;
  3117. /* frame to self mac. skip */
  3118. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3119. continue;
  3120. /*
  3121. * TODO: optimize to avoid malloc in per-packet path
  3122. * For eg. seg_pool can be made part of vdev structure
  3123. */
  3124. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3125. if (!seg_info_new) {
  3126. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3127. "alloc failed");
  3128. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3129. goto fail_seg_alloc;
  3130. }
  3131. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3132. if (mc_uc_buf == NULL)
  3133. goto fail_buf_alloc;
  3134. /*
  3135. * TODO: Check if we need to clone the nbuf
  3136. * Or can we just use the reference for all cases
  3137. */
  3138. if (new_mac_idx < (new_mac_cnt - 1)) {
  3139. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3140. if (nbuf_clone == NULL) {
  3141. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3142. goto fail_clone;
  3143. }
  3144. } else {
  3145. /*
  3146. * Update the ref
  3147. * to account for frame sent without cloning
  3148. */
  3149. qdf_nbuf_ref(nbuf);
  3150. nbuf_clone = nbuf;
  3151. }
  3152. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3153. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3154. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3155. &paddr_mcbuf);
  3156. if (status) {
  3157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3158. "Mapping failure Error:%d", status);
  3159. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3160. goto fail_map;
  3161. }
  3162. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3163. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3164. seg_info_new->frags[0].paddr_hi =
  3165. ((uint64_t) paddr_mcbuf >> 32);
  3166. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3167. seg_info_new->frags[1] = data_frag;
  3168. seg_info_new->nbuf = nbuf_clone;
  3169. seg_info_new->frag_cnt = 2;
  3170. seg_info_new->total_len = len;
  3171. seg_info_new->next = NULL;
  3172. if (seg_info_head == NULL)
  3173. seg_info_head = seg_info_new;
  3174. else
  3175. seg_info_tail->next = seg_info_new;
  3176. seg_info_tail = seg_info_new;
  3177. }
  3178. if (!seg_info_head) {
  3179. goto free_return;
  3180. }
  3181. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3182. msdu_info.num_seg = new_mac_cnt;
  3183. msdu_info.frm_type = dp_tx_frm_me;
  3184. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3185. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3186. while (seg_info_head->next) {
  3187. seg_info_new = seg_info_head;
  3188. seg_info_head = seg_info_head->next;
  3189. qdf_mem_free(seg_info_new);
  3190. }
  3191. qdf_mem_free(seg_info_head);
  3192. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3193. qdf_nbuf_free(nbuf);
  3194. return new_mac_cnt;
  3195. fail_map:
  3196. qdf_nbuf_free(nbuf_clone);
  3197. fail_clone:
  3198. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3199. fail_buf_alloc:
  3200. qdf_mem_free(seg_info_new);
  3201. fail_seg_alloc:
  3202. dp_tx_me_mem_free(pdev, seg_info_head);
  3203. free_return:
  3204. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3205. qdf_nbuf_free(nbuf);
  3206. return 1;
  3207. }