wcd937x.c 102 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/regmap.h>
  14. #include <linux/pm_runtime.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <asoc/wcdcal-hwdep.h>
  21. #include <asoc/msm-cdc-pinctrl.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include "wcd937x-registers.h"
  25. #include "wcd937x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #include <linux/qti-regmap-debugfs.h>
  29. #define WCD9370_VARIANT 0
  30. #define WCD9375_VARIANT 5
  31. #define WCD937X_VARIANT_ENTRY_SIZE 32
  32. #define NUM_SWRS_DT_PARAMS 5
  33. #define WCD937X_VERSION_1_0 1
  34. #define WCD937X_VERSION_ENTRY_SIZE 32
  35. #define EAR_RX_PATH_AUX 1
  36. #define NUM_ATTEMPTS 5
  37. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  38. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  39. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  40. SNDRV_PCM_RATE_384000)
  41. /* Fractional Rates */
  42. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  43. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  44. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  45. SNDRV_PCM_FMTBIT_S24_LE |\
  46. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  47. enum {
  48. CODEC_TX = 0,
  49. CODEC_RX,
  50. };
  51. enum {
  52. ALLOW_BUCK_DISABLE,
  53. HPH_COMP_DELAY,
  54. HPH_PA_DELAY,
  55. AMIC2_BCS_ENABLE,
  56. };
  57. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  58. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  59. static int wcd937x_handle_post_irq(void *data);
  60. static int wcd937x_reset(struct device *dev);
  61. static int wcd937x_reset_low(struct device *dev);
  62. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  81. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  82. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  83. };
  84. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  85. .name = "wcd937x",
  86. .irqs = wcd937x_irqs,
  87. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  88. .num_regs = 3,
  89. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  90. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  91. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  92. .use_ack = 1,
  93. //#if IS_ENABLED(CONFIG_AUDIO_QGKI)
  94. .clear_ack = 1,
  95. //#endif
  96. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd937x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static struct snd_soc_dai_driver wcd937x_dai[] = {
  102. {
  103. .name = "wcd937x_cdc",
  104. .playback = {
  105. .stream_name = "WCD937X_AIF Playback",
  106. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  107. .formats = WCD937X_FORMATS,
  108. .rate_max = 384000,
  109. .rate_min = 8000,
  110. .channels_min = 1,
  111. .channels_max = 4,
  112. },
  113. .capture = {
  114. .stream_name = "WCD937X_AIF Capture",
  115. .rates = WCD937X_RATES,
  116. .formats = WCD937X_FORMATS,
  117. .rate_max = 192000,
  118. .rate_min = 8000,
  119. .channels_min = 1,
  120. .channels_max = 4,
  121. },
  122. },
  123. };
  124. static int wcd937x_handle_post_irq(void *data)
  125. {
  126. struct wcd937x_priv *wcd937x = data;
  127. u32 status1 = 0, status2 = 0, status3 = 0;
  128. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  129. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  130. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  131. wcd937x->tx_swr_dev->slave_irq_pending =
  132. ((status1 || status2 || status3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd937x_init_reg(struct snd_soc_component *component)
  136. {
  137. u32 val = 0;
  138. val = snd_soc_component_read(component, WCD937X_DIGITAL_EFUSE_REG_29)
  139. & 0x0F;
  140. if (snd_soc_component_read(component, WCD937X_DIGITAL_EFUSE_REG_16)
  141. == 0x02 || snd_soc_component_read(component,
  142. WCD937X_DIGITAL_EFUSE_REG_17) > 0x09) {
  143. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  144. 0x0E, val);
  145. } else {
  146. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  147. 0x0E, 0x0E);
  148. }
  149. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  150. 0x80, 0x80);
  151. usleep_range(1000, 1010);
  152. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  153. 0x40, 0x40);
  154. usleep_range(1000, 1010);
  155. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  156. 0x10, 0x00);
  157. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  158. 0xF0, 0x80);
  159. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  160. 0x80, 0x80);
  161. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  162. 0x40, 0x40);
  163. usleep_range(10000, 10010);
  164. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  165. 0x40, 0x00);
  166. snd_soc_component_update_bits(component,
  167. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  168. 0xFF, 0xD9);
  169. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  170. 0xFF, 0xFA);
  171. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  172. 0xFF, 0xFA);
  173. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  174. 0xFF, 0xFA);
  175. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_2,
  176. 0x38, 0x00);
  177. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_2,
  178. 0x38, 0x00);
  179. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_2,
  180. 0x38, 0x00);
  181. /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */
  182. if (snd_soc_component_read(component, WCD937X_DIGITAL_EFUSE_REG_16)
  183. == 0x01) {
  184. snd_soc_component_update_bits(component,
  185. WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
  186. } else if (snd_soc_component_read(component,
  187. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) {
  188. snd_soc_component_update_bits(component,
  189. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04);
  190. snd_soc_component_update_bits(component,
  191. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04);
  192. snd_soc_component_update_bits(component,
  193. WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
  194. snd_soc_component_update_bits(component,
  195. WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50);
  196. }
  197. return 0;
  198. }
  199. static int wcd937x_set_port_params(struct snd_soc_component *component,
  200. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  201. u8 *ch_mask, u32 *ch_rate,
  202. u8 *port_type, u8 path)
  203. {
  204. int i, j;
  205. u8 num_ports = 0;
  206. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  207. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  208. switch (path) {
  209. case CODEC_RX:
  210. map = &wcd937x->rx_port_mapping;
  211. num_ports = wcd937x->num_rx_ports;
  212. break;
  213. case CODEC_TX:
  214. map = &wcd937x->tx_port_mapping;
  215. num_ports = wcd937x->num_tx_ports;
  216. break;
  217. default:
  218. dev_err(component->dev, "%s Invalid path selected %u\n",
  219. __func__, path);
  220. return -EINVAL;
  221. }
  222. for (i = 0; i <= num_ports; i++) {
  223. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  224. if ((*map)[i][j].slave_port_type == slv_prt_type)
  225. goto found;
  226. }
  227. }
  228. found:
  229. if (i > num_ports || j == MAX_CH_PER_PORT) {
  230. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  231. __func__, slv_prt_type);
  232. return -EINVAL;
  233. }
  234. *port_id = i;
  235. *num_ch = (*map)[i][j].num_ch;
  236. *ch_mask = (*map)[i][j].ch_mask;
  237. *ch_rate = (*map)[i][j].ch_rate;
  238. *port_type = (*map)[i][j].master_port_type;
  239. return 0;
  240. }
  241. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  242. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  243. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  244. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  245. static int wcd937x_parse_port_params(struct device *dev,
  246. char *prop, u8 path)
  247. {
  248. u32 *dt_array, map_size, max_uc;
  249. int ret = 0;
  250. u32 cnt = 0;
  251. u32 i, j;
  252. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  253. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  254. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  255. switch (path) {
  256. case CODEC_TX:
  257. map = &wcd937x->tx_port_params;
  258. map_uc = &wcd937x->swr_tx_port_params;
  259. break;
  260. default:
  261. ret = -EINVAL;
  262. goto err_port_map;
  263. }
  264. if (!of_find_property(dev->of_node, prop,
  265. &map_size)) {
  266. dev_err(dev, "missing port mapping prop %s\n", prop);
  267. ret = -EINVAL;
  268. goto err_port_map;
  269. }
  270. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  271. if (max_uc != SWR_UC_MAX) {
  272. dev_err(dev, "%s: port params not provided for all usecases\n",
  273. __func__);
  274. ret = -EINVAL;
  275. goto err_port_map;
  276. }
  277. dt_array = kzalloc(map_size, GFP_KERNEL);
  278. if (!dt_array) {
  279. ret = -ENOMEM;
  280. goto err_alloc;
  281. }
  282. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  283. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  284. if (ret) {
  285. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  286. __func__, prop);
  287. goto err_pdata_fail;
  288. }
  289. for (i = 0; i < max_uc; i++) {
  290. for (j = 0; j < SWR_NUM_PORTS; j++) {
  291. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  292. (*map)[i][j].offset1 = dt_array[cnt];
  293. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  294. }
  295. (*map_uc)[i].pp = &(*map)[i][0];
  296. }
  297. kfree(dt_array);
  298. return 0;
  299. err_pdata_fail:
  300. kfree(dt_array);
  301. err_alloc:
  302. err_port_map:
  303. return ret;
  304. }
  305. static int wcd937x_parse_port_mapping(struct device *dev,
  306. char *prop, u8 path)
  307. {
  308. u32 *dt_array, map_size, map_length;
  309. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  310. u32 slave_port_type, master_port_type;
  311. u32 i, ch_iter = 0;
  312. int ret = 0;
  313. u8 *num_ports = NULL;
  314. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  315. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  316. switch (path) {
  317. case CODEC_RX:
  318. map = &wcd937x->rx_port_mapping;
  319. num_ports = &wcd937x->num_rx_ports;
  320. break;
  321. case CODEC_TX:
  322. map = &wcd937x->tx_port_mapping;
  323. num_ports = &wcd937x->num_tx_ports;
  324. break;
  325. default:
  326. dev_err(dev, "%s Invalid path selected %u\n",
  327. __func__, path);
  328. return -EINVAL;
  329. }
  330. if (!of_find_property(dev->of_node, prop,
  331. &map_size)) {
  332. dev_err(dev, "missing port mapping prop %s\n", prop);
  333. ret = -EINVAL;
  334. goto err;
  335. }
  336. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  337. dt_array = kzalloc(map_size, GFP_KERNEL);
  338. if (!dt_array) {
  339. ret = -ENOMEM;
  340. goto err;
  341. }
  342. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  343. NUM_SWRS_DT_PARAMS * map_length);
  344. if (ret) {
  345. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  346. __func__, prop);
  347. ret = -EINVAL;
  348. goto err_pdata_fail;
  349. }
  350. for (i = 0; i < map_length; i++) {
  351. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  352. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  353. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  354. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  355. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  356. if (port_num != old_port_num)
  357. ch_iter = 0;
  358. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  359. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  360. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  361. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  362. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  363. old_port_num = port_num;
  364. }
  365. *num_ports = port_num;
  366. kfree(dt_array);
  367. return 0;
  368. err_pdata_fail:
  369. kfree(dt_array);
  370. err:
  371. return ret;
  372. }
  373. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  374. u8 slv_port_type, u8 enable)
  375. {
  376. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  377. u8 port_id;
  378. u8 num_ch;
  379. u8 ch_mask;
  380. u32 ch_rate;
  381. u8 ch_type = 0;
  382. int slave_ch_idx;
  383. u8 num_port = 1;
  384. int ret = 0;
  385. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  386. &num_ch, &ch_mask, &ch_rate,
  387. &ch_type, CODEC_TX);
  388. if (ret)
  389. return ret;
  390. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  391. if (slave_ch_idx != -EINVAL)
  392. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  393. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  394. __func__, slave_ch_idx, ch_type);
  395. if (enable)
  396. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  397. num_port, &ch_mask, &ch_rate,
  398. &num_ch, &ch_type);
  399. else
  400. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  401. num_port, &ch_mask, &ch_type);
  402. return ret;
  403. }
  404. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  405. u8 slv_port_type, u8 enable)
  406. {
  407. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  408. u8 port_id;
  409. u8 num_ch;
  410. u8 ch_mask;
  411. u32 ch_rate;
  412. u8 port_type;
  413. u8 num_port = 1;
  414. int ret = 0;
  415. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  416. &num_ch, &ch_mask, &ch_rate,
  417. &port_type, CODEC_RX);
  418. if (ret)
  419. return ret;
  420. if (enable)
  421. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  422. num_port, &ch_mask, &ch_rate,
  423. &num_ch, &port_type);
  424. else
  425. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  426. num_port, &ch_mask, &port_type);
  427. return ret;
  428. }
  429. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  430. {
  431. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  432. if (wcd937x->rx_clk_cnt == 0) {
  433. snd_soc_component_update_bits(component,
  434. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  435. snd_soc_component_update_bits(component,
  436. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  437. snd_soc_component_update_bits(component,
  438. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  439. snd_soc_component_update_bits(component,
  440. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  441. snd_soc_component_update_bits(component,
  442. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  443. snd_soc_component_update_bits(component,
  444. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  445. snd_soc_component_update_bits(component,
  446. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  447. }
  448. wcd937x->rx_clk_cnt++;
  449. return 0;
  450. }
  451. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  452. {
  453. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  454. if (wcd937x->rx_clk_cnt == 0) {
  455. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  456. return 0;
  457. }
  458. wcd937x->rx_clk_cnt--;
  459. if (wcd937x->rx_clk_cnt == 0) {
  460. snd_soc_component_update_bits(component,
  461. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  462. snd_soc_component_update_bits(component,
  463. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  464. 0x02, 0x00);
  465. snd_soc_component_update_bits(component,
  466. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  467. 0x01, 0x00);
  468. }
  469. return 0;
  470. }
  471. /*
  472. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  473. * @component: handle to snd_soc_component *
  474. *
  475. * return wcd937x_mbhc handle or error code in case of failure
  476. */
  477. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  478. {
  479. struct wcd937x_priv *wcd937x;
  480. if (!component) {
  481. pr_err("%s: Invalid params, NULL component\n", __func__);
  482. return NULL;
  483. }
  484. wcd937x = snd_soc_component_get_drvdata(component);
  485. if (!wcd937x) {
  486. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  487. return NULL;
  488. }
  489. return wcd937x->mbhc;
  490. }
  491. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  492. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  493. struct snd_kcontrol *kcontrol,
  494. int event)
  495. {
  496. struct snd_soc_component *component =
  497. snd_soc_dapm_to_component(w->dapm);
  498. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  499. int hph_mode = wcd937x->hph_mode;
  500. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  501. w->name, event);
  502. switch (event) {
  503. case SND_SOC_DAPM_PRE_PMU:
  504. wcd937x_rx_clk_enable(component);
  505. snd_soc_component_update_bits(component,
  506. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  507. 0x01, 0x01);
  508. snd_soc_component_update_bits(component,
  509. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  510. 0x04, 0x04);
  511. snd_soc_component_update_bits(component,
  512. WCD937X_HPH_RDAC_CLK_CTL1,
  513. 0x80, 0x00);
  514. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  515. break;
  516. case SND_SOC_DAPM_POST_PMU:
  517. if ((snd_soc_component_read(component,
  518. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  519. ((snd_soc_component_read(component,
  520. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  521. snd_soc_component_update_bits(component,
  522. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90);
  523. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  524. snd_soc_component_update_bits(component,
  525. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  526. 0x0F, 0x02);
  527. else if (hph_mode == CLS_H_LOHIFI)
  528. snd_soc_component_update_bits(component,
  529. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  530. 0x0F, 0x06);
  531. if (wcd937x->comp1_enable) {
  532. snd_soc_component_update_bits(component,
  533. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  534. 0x02, 0x02);
  535. snd_soc_component_update_bits(component,
  536. WCD937X_HPH_L_EN, 0x20, 0x00);
  537. if (wcd937x->comp2_enable) {
  538. snd_soc_component_update_bits(component,
  539. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  540. 0x01, 0x01);
  541. snd_soc_component_update_bits(component,
  542. WCD937X_HPH_R_EN, 0x20, 0x00);
  543. }
  544. /*
  545. * 5ms sleep is required after COMP is enabled as per
  546. * HW requirement
  547. */
  548. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  549. usleep_range(5000, 5100);
  550. clear_bit(HPH_COMP_DELAY,
  551. &wcd937x->status_mask);
  552. }
  553. } else {
  554. snd_soc_component_update_bits(component,
  555. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  556. 0x02, 0x00);
  557. snd_soc_component_update_bits(component,
  558. WCD937X_HPH_L_EN, 0x20, 0x20);
  559. }
  560. snd_soc_component_update_bits(component,
  561. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  562. break;
  563. case SND_SOC_DAPM_POST_PMD:
  564. if ((snd_soc_component_read(component,
  565. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  566. ((snd_soc_component_read(component,
  567. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  568. snd_soc_component_update_bits(component,
  569. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80);
  570. snd_soc_component_update_bits(component,
  571. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  572. 0x0F, 0x01);
  573. break;
  574. }
  575. return 0;
  576. }
  577. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  578. struct snd_kcontrol *kcontrol,
  579. int event)
  580. {
  581. struct snd_soc_component *component =
  582. snd_soc_dapm_to_component(w->dapm);
  583. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  584. int hph_mode = wcd937x->hph_mode;
  585. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  586. w->name, event);
  587. switch (event) {
  588. case SND_SOC_DAPM_PRE_PMU:
  589. wcd937x_rx_clk_enable(component);
  590. snd_soc_component_update_bits(component,
  591. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  592. snd_soc_component_update_bits(component,
  593. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  594. snd_soc_component_update_bits(component,
  595. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  596. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  597. break;
  598. case SND_SOC_DAPM_POST_PMU:
  599. if ((snd_soc_component_read(component,
  600. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  601. ((snd_soc_component_read(component,
  602. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  603. snd_soc_component_update_bits(component,
  604. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90);
  605. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  606. snd_soc_component_update_bits(component,
  607. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  608. 0x0F, 0x02);
  609. else if (hph_mode == CLS_H_LOHIFI)
  610. snd_soc_component_update_bits(component,
  611. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  612. 0x0F, 0x06);
  613. if (wcd937x->comp2_enable) {
  614. snd_soc_component_update_bits(component,
  615. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  616. 0x01, 0x01);
  617. snd_soc_component_update_bits(component,
  618. WCD937X_HPH_R_EN, 0x20, 0x00);
  619. if (wcd937x->comp1_enable) {
  620. snd_soc_component_update_bits(component,
  621. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  622. 0x02, 0x02);
  623. snd_soc_component_update_bits(component,
  624. WCD937X_HPH_L_EN, 0x20, 0x00);
  625. }
  626. /*
  627. * 5ms sleep is required after COMP is enabled as per
  628. * HW requirement
  629. */
  630. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  631. usleep_range(5000, 5100);
  632. clear_bit(HPH_COMP_DELAY,
  633. &wcd937x->status_mask);
  634. }
  635. } else {
  636. snd_soc_component_update_bits(component,
  637. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  638. 0x01, 0x00);
  639. snd_soc_component_update_bits(component,
  640. WCD937X_HPH_R_EN, 0x20, 0x20);
  641. }
  642. snd_soc_component_update_bits(component,
  643. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  644. break;
  645. case SND_SOC_DAPM_POST_PMD:
  646. if ((snd_soc_component_read(component,
  647. WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) &&
  648. ((snd_soc_component_read(component,
  649. WCD937X_ANA_HPH) & 0x0C) == 0x0C))
  650. snd_soc_component_update_bits(component,
  651. WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80);
  652. snd_soc_component_update_bits(component,
  653. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  654. 0x0F, 0x01);
  655. break;
  656. }
  657. return 0;
  658. }
  659. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  660. struct snd_kcontrol *kcontrol,
  661. int event)
  662. {
  663. struct snd_soc_component *component =
  664. snd_soc_dapm_to_component(w->dapm);
  665. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  666. int hph_mode = wcd937x->hph_mode;
  667. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  668. w->name, event);
  669. switch (event) {
  670. case SND_SOC_DAPM_PRE_PMU:
  671. wcd937x_rx_clk_enable(component);
  672. snd_soc_component_update_bits(component,
  673. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  674. 0x04, 0x04);
  675. snd_soc_component_update_bits(component,
  676. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  677. 0x01, 0x01);
  678. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  679. snd_soc_component_update_bits(component,
  680. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  681. 0x0F, 0x02);
  682. else if (hph_mode == CLS_H_LOHIFI)
  683. snd_soc_component_update_bits(component,
  684. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  685. 0x0F, 0x06);
  686. if (wcd937x->comp1_enable)
  687. snd_soc_component_update_bits(component,
  688. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  689. 0x02, 0x02);
  690. usleep_range(5000, 5010);
  691. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  692. 0x04, 0x00);
  693. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  694. WCD_CLSH_EVENT_PRE_DAC,
  695. WCD_CLSH_STATE_EAR,
  696. hph_mode);
  697. break;
  698. case SND_SOC_DAPM_POST_PMD:
  699. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  700. hph_mode == CLS_H_HIFI)
  701. snd_soc_component_update_bits(component,
  702. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  703. 0x0F, 0x01);
  704. if (wcd937x->comp1_enable)
  705. snd_soc_component_update_bits(component,
  706. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  707. 0x02, 0x00);
  708. break;
  709. };
  710. return 0;
  711. }
  712. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  713. struct snd_kcontrol *kcontrol,
  714. int event)
  715. {
  716. struct snd_soc_component *component =
  717. snd_soc_dapm_to_component(w->dapm);
  718. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  719. int hph_mode = wcd937x->hph_mode;
  720. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  721. w->name, event);
  722. switch (event) {
  723. case SND_SOC_DAPM_PRE_PMU:
  724. wcd937x_rx_clk_enable(component);
  725. snd_soc_component_update_bits(component,
  726. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  727. 0x04, 0x04);
  728. snd_soc_component_update_bits(component,
  729. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  730. 0x04, 0x04);
  731. snd_soc_component_update_bits(component,
  732. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  733. 0x01, 0x01);
  734. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  735. WCD_CLSH_EVENT_PRE_DAC,
  736. WCD_CLSH_STATE_AUX,
  737. hph_mode);
  738. break;
  739. case SND_SOC_DAPM_POST_PMD:
  740. snd_soc_component_update_bits(component,
  741. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  742. 0x04, 0x00);
  743. break;
  744. };
  745. return 0;
  746. }
  747. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  748. struct snd_kcontrol *kcontrol,
  749. int event)
  750. {
  751. struct snd_soc_component *component =
  752. snd_soc_dapm_to_component(w->dapm);
  753. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  754. int ret = 0;
  755. int hph_mode = wcd937x->hph_mode;
  756. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  757. w->name, event);
  758. switch (event) {
  759. case SND_SOC_DAPM_PRE_PMU:
  760. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  761. wcd937x->rx_swr_dev->dev_num,
  762. true);
  763. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  764. WCD_CLSH_EVENT_PRE_DAC,
  765. WCD_CLSH_STATE_HPHR,
  766. hph_mode);
  767. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  768. 0x10, 0x10);
  769. usleep_range(100, 110);
  770. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  771. snd_soc_component_update_bits(component,
  772. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  773. break;
  774. case SND_SOC_DAPM_POST_PMU:
  775. /*
  776. * 7ms sleep is required after PA is enabled as per
  777. * HW requirement. If compander is disabled, then
  778. * 20ms delay is required.
  779. */
  780. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  781. if (!wcd937x->comp2_enable)
  782. usleep_range(20000, 20100);
  783. else
  784. usleep_range(7000, 7100);
  785. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  786. }
  787. snd_soc_component_update_bits(component,
  788. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  789. 0x02, 0x02);
  790. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  791. snd_soc_component_update_bits(component,
  792. WCD937X_ANA_RX_SUPPLIES,
  793. 0x02, 0x02);
  794. if (wcd937x->update_wcd_event)
  795. wcd937x->update_wcd_event(wcd937x->handle,
  796. SLV_BOLERO_EVT_RX_MUTE,
  797. (WCD_RX2 << 0x10));
  798. wcd_enable_irq(&wcd937x->irq_info,
  799. WCD937X_IRQ_HPHR_PDM_WD_INT);
  800. break;
  801. case SND_SOC_DAPM_PRE_PMD:
  802. wcd_disable_irq(&wcd937x->irq_info,
  803. WCD937X_IRQ_HPHR_PDM_WD_INT);
  804. if (wcd937x->update_wcd_event)
  805. wcd937x->update_wcd_event(wcd937x->handle,
  806. SLV_BOLERO_EVT_RX_MUTE,
  807. (WCD_RX2 << 0x10 | 0x1));
  808. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  809. WCD_EVENT_PRE_HPHR_PA_OFF,
  810. &wcd937x->mbhc->wcd_mbhc);
  811. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  812. break;
  813. case SND_SOC_DAPM_POST_PMD:
  814. /*
  815. * 7ms sleep is required after PA is disabled as per
  816. * HW requirement. If compander is disabled, then
  817. * 20ms delay is required.
  818. */
  819. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  820. if (!wcd937x->comp2_enable)
  821. usleep_range(20000, 20100);
  822. else
  823. usleep_range(7000, 7100);
  824. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  825. }
  826. snd_soc_component_update_bits(component,
  827. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  828. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  829. WCD_EVENT_POST_HPHR_PA_OFF,
  830. &wcd937x->mbhc->wcd_mbhc);
  831. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  832. 0x10, 0x00);
  833. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  834. WCD_CLSH_EVENT_POST_PA,
  835. WCD_CLSH_STATE_HPHR,
  836. hph_mode);
  837. break;
  838. };
  839. return ret;
  840. }
  841. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  842. struct snd_kcontrol *kcontrol,
  843. int event)
  844. {
  845. struct snd_soc_component *component =
  846. snd_soc_dapm_to_component(w->dapm);
  847. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  848. int ret = 0;
  849. int hph_mode = wcd937x->hph_mode;
  850. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  851. w->name, event);
  852. switch (event) {
  853. case SND_SOC_DAPM_PRE_PMU:
  854. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  855. wcd937x->rx_swr_dev->dev_num,
  856. true);
  857. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  858. WCD_CLSH_EVENT_PRE_DAC,
  859. WCD_CLSH_STATE_HPHL,
  860. hph_mode);
  861. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  862. 0x20, 0x20);
  863. usleep_range(100, 110);
  864. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  865. snd_soc_component_update_bits(component,
  866. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  867. break;
  868. case SND_SOC_DAPM_POST_PMU:
  869. /*
  870. * 7ms sleep is required after PA is enabled as per
  871. * HW requirement. If compander is disabled, then
  872. * 20ms delay is required.
  873. */
  874. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  875. if (!wcd937x->comp1_enable)
  876. usleep_range(20000, 20100);
  877. else
  878. usleep_range(7000, 7100);
  879. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  880. }
  881. snd_soc_component_update_bits(component,
  882. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  883. 0x02, 0x02);
  884. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  885. snd_soc_component_update_bits(component,
  886. WCD937X_ANA_RX_SUPPLIES,
  887. 0x02, 0x02);
  888. if (wcd937x->update_wcd_event)
  889. wcd937x->update_wcd_event(wcd937x->handle,
  890. SLV_BOLERO_EVT_RX_MUTE,
  891. (WCD_RX1 << 0x10));
  892. wcd_enable_irq(&wcd937x->irq_info,
  893. WCD937X_IRQ_HPHL_PDM_WD_INT);
  894. break;
  895. case SND_SOC_DAPM_PRE_PMD:
  896. wcd_disable_irq(&wcd937x->irq_info,
  897. WCD937X_IRQ_HPHL_PDM_WD_INT);
  898. if (wcd937x->update_wcd_event)
  899. wcd937x->update_wcd_event(wcd937x->handle,
  900. SLV_BOLERO_EVT_RX_MUTE,
  901. (WCD_RX1 << 0x10 | 0x1));
  902. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  903. WCD_EVENT_PRE_HPHL_PA_OFF,
  904. &wcd937x->mbhc->wcd_mbhc);
  905. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  906. break;
  907. case SND_SOC_DAPM_POST_PMD:
  908. /*
  909. * 7ms sleep is required after PA is disabled as per
  910. * HW requirement. If compander is disabled, then
  911. * 20ms delay is required.
  912. */
  913. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  914. if (!wcd937x->comp1_enable)
  915. usleep_range(20000, 20100);
  916. else
  917. usleep_range(7000, 7100);
  918. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  919. }
  920. snd_soc_component_update_bits(component,
  921. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  922. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  923. WCD_EVENT_POST_HPHL_PA_OFF,
  924. &wcd937x->mbhc->wcd_mbhc);
  925. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  926. 0x20, 0x00);
  927. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  928. WCD_CLSH_EVENT_POST_PA,
  929. WCD_CLSH_STATE_HPHL,
  930. hph_mode);
  931. break;
  932. };
  933. return ret;
  934. }
  935. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  936. struct snd_kcontrol *kcontrol,
  937. int event)
  938. {
  939. struct snd_soc_component *component =
  940. snd_soc_dapm_to_component(w->dapm);
  941. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  942. int hph_mode = wcd937x->hph_mode;
  943. int ret = 0;
  944. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  945. w->name, event);
  946. switch (event) {
  947. case SND_SOC_DAPM_PRE_PMU:
  948. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  949. wcd937x->rx_swr_dev->dev_num,
  950. true);
  951. snd_soc_component_update_bits(component,
  952. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  953. break;
  954. case SND_SOC_DAPM_POST_PMU:
  955. usleep_range(1000, 1010);
  956. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  957. snd_soc_component_update_bits(component,
  958. WCD937X_ANA_RX_SUPPLIES,
  959. 0x02, 0x02);
  960. if (wcd937x->update_wcd_event)
  961. wcd937x->update_wcd_event(wcd937x->handle,
  962. SLV_BOLERO_EVT_RX_MUTE,
  963. (WCD_RX3 << 0x10));
  964. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  965. break;
  966. case SND_SOC_DAPM_PRE_PMD:
  967. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  968. if (wcd937x->update_wcd_event)
  969. wcd937x->update_wcd_event(wcd937x->handle,
  970. SLV_BOLERO_EVT_RX_MUTE,
  971. (WCD_RX3 << 0x10 | 0x1));
  972. break;
  973. case SND_SOC_DAPM_POST_PMD:
  974. /* Add delay as per hw requirement */
  975. usleep_range(2000, 2010);
  976. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  977. WCD_CLSH_EVENT_POST_PA,
  978. WCD_CLSH_STATE_AUX,
  979. hph_mode);
  980. snd_soc_component_update_bits(component,
  981. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  982. break;
  983. };
  984. return ret;
  985. }
  986. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  987. struct snd_kcontrol *kcontrol,
  988. int event)
  989. {
  990. struct snd_soc_component *component =
  991. snd_soc_dapm_to_component(w->dapm);
  992. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  993. int hph_mode = wcd937x->hph_mode;
  994. int ret = 0;
  995. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  996. w->name, event);
  997. switch (event) {
  998. case SND_SOC_DAPM_PRE_PMU:
  999. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  1000. wcd937x->rx_swr_dev->dev_num,
  1001. true);
  1002. /*
  1003. * Enable watchdog interrupt for HPHL or AUX
  1004. * depending on mux value
  1005. */
  1006. wcd937x->ear_rx_path =
  1007. snd_soc_component_read(
  1008. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  1009. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1010. snd_soc_component_update_bits(component,
  1011. WCD937X_DIGITAL_PDM_WD_CTL2,
  1012. 0x05, 0x05);
  1013. else
  1014. snd_soc_component_update_bits(component,
  1015. WCD937X_DIGITAL_PDM_WD_CTL0,
  1016. 0x17, 0x13);
  1017. if (!wcd937x->comp1_enable)
  1018. snd_soc_component_update_bits(component,
  1019. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1020. break;
  1021. case SND_SOC_DAPM_POST_PMU:
  1022. usleep_range(6000, 6010);
  1023. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  1024. snd_soc_component_update_bits(component,
  1025. WCD937X_ANA_RX_SUPPLIES,
  1026. 0x02, 0x02);
  1027. if (wcd937x->update_wcd_event)
  1028. wcd937x->update_wcd_event(wcd937x->handle,
  1029. SLV_BOLERO_EVT_RX_MUTE,
  1030. (WCD_RX1 << 0x10));
  1031. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1032. wcd_enable_irq(&wcd937x->irq_info,
  1033. WCD937X_IRQ_AUX_PDM_WD_INT);
  1034. else
  1035. wcd_enable_irq(&wcd937x->irq_info,
  1036. WCD937X_IRQ_HPHL_PDM_WD_INT);
  1037. break;
  1038. case SND_SOC_DAPM_PRE_PMD:
  1039. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1040. wcd_disable_irq(&wcd937x->irq_info,
  1041. WCD937X_IRQ_AUX_PDM_WD_INT);
  1042. else
  1043. wcd_disable_irq(&wcd937x->irq_info,
  1044. WCD937X_IRQ_HPHL_PDM_WD_INT);
  1045. if (wcd937x->update_wcd_event)
  1046. wcd937x->update_wcd_event(wcd937x->handle,
  1047. SLV_BOLERO_EVT_RX_MUTE,
  1048. (WCD_RX1 << 0x10 | 0x1));
  1049. break;
  1050. case SND_SOC_DAPM_POST_PMD:
  1051. if (!wcd937x->comp1_enable)
  1052. snd_soc_component_update_bits(component,
  1053. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1054. usleep_range(7000, 7010);
  1055. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  1056. WCD_CLSH_EVENT_POST_PA,
  1057. WCD_CLSH_STATE_EAR,
  1058. hph_mode);
  1059. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1060. 0x04, 0x04);
  1061. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1062. snd_soc_component_update_bits(component,
  1063. WCD937X_DIGITAL_PDM_WD_CTL2,
  1064. 0x05, 0x00);
  1065. else
  1066. snd_soc_component_update_bits(component,
  1067. WCD937X_DIGITAL_PDM_WD_CTL0,
  1068. 0x17, 0x00);
  1069. break;
  1070. };
  1071. return ret;
  1072. }
  1073. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1074. struct snd_kcontrol *kcontrol,
  1075. int event)
  1076. {
  1077. struct snd_soc_component *component =
  1078. snd_soc_dapm_to_component(w->dapm);
  1079. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1080. int mode = wcd937x->hph_mode;
  1081. int ret = 0;
  1082. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1083. w->name, event);
  1084. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1085. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1086. wcd937x_rx_connect_port(component, CLSH,
  1087. SND_SOC_DAPM_EVENT_ON(event));
  1088. }
  1089. if (SND_SOC_DAPM_EVENT_OFF(event))
  1090. ret = swr_slvdev_datapath_control(
  1091. wcd937x->rx_swr_dev,
  1092. wcd937x->rx_swr_dev->dev_num,
  1093. false);
  1094. return ret;
  1095. }
  1096. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1097. struct snd_kcontrol *kcontrol,
  1098. int event)
  1099. {
  1100. struct snd_soc_component *component =
  1101. snd_soc_dapm_to_component(w->dapm);
  1102. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1103. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1104. w->name, event);
  1105. switch (event) {
  1106. case SND_SOC_DAPM_PRE_PMU:
  1107. wcd937x_rx_connect_port(component, HPH_L, true);
  1108. if (wcd937x->comp1_enable)
  1109. wcd937x_rx_connect_port(component, COMP_L, true);
  1110. break;
  1111. case SND_SOC_DAPM_POST_PMD:
  1112. wcd937x_rx_connect_port(component, HPH_L, false);
  1113. if (wcd937x->comp1_enable)
  1114. wcd937x_rx_connect_port(component, COMP_L, false);
  1115. wcd937x_rx_clk_disable(component);
  1116. snd_soc_component_update_bits(component,
  1117. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1118. 0x01, 0x00);
  1119. break;
  1120. };
  1121. return 0;
  1122. }
  1123. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1124. struct snd_kcontrol *kcontrol, int event)
  1125. {
  1126. struct snd_soc_component *component =
  1127. snd_soc_dapm_to_component(w->dapm);
  1128. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1129. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1130. w->name, event);
  1131. switch (event) {
  1132. case SND_SOC_DAPM_PRE_PMU:
  1133. wcd937x_rx_connect_port(component, HPH_R, true);
  1134. if (wcd937x->comp2_enable)
  1135. wcd937x_rx_connect_port(component, COMP_R, true);
  1136. break;
  1137. case SND_SOC_DAPM_POST_PMD:
  1138. wcd937x_rx_connect_port(component, HPH_R, false);
  1139. if (wcd937x->comp2_enable)
  1140. wcd937x_rx_connect_port(component, COMP_R, false);
  1141. wcd937x_rx_clk_disable(component);
  1142. snd_soc_component_update_bits(component,
  1143. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1144. 0x02, 0x00);
  1145. break;
  1146. };
  1147. return 0;
  1148. }
  1149. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1150. struct snd_kcontrol *kcontrol,
  1151. int event)
  1152. {
  1153. struct snd_soc_component *component =
  1154. snd_soc_dapm_to_component(w->dapm);
  1155. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1156. w->name, event);
  1157. switch (event) {
  1158. case SND_SOC_DAPM_PRE_PMU:
  1159. wcd937x_rx_connect_port(component, LO, true);
  1160. break;
  1161. case SND_SOC_DAPM_POST_PMD:
  1162. wcd937x_rx_connect_port(component, LO, false);
  1163. usleep_range(6000, 6010);
  1164. wcd937x_rx_clk_disable(component);
  1165. snd_soc_component_update_bits(component,
  1166. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1167. break;
  1168. }
  1169. return 0;
  1170. }
  1171. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1172. struct snd_kcontrol *kcontrol,
  1173. int event)
  1174. {
  1175. struct snd_soc_component *component =
  1176. snd_soc_dapm_to_component(w->dapm);
  1177. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1178. u16 dmic_clk_reg;
  1179. s32 *dmic_clk_cnt;
  1180. unsigned int dmic;
  1181. char *wname;
  1182. int ret = 0;
  1183. wname = strpbrk(w->name, "012345");
  1184. if (!wname) {
  1185. dev_err(component->dev, "%s: widget not found\n", __func__);
  1186. return -EINVAL;
  1187. }
  1188. ret = kstrtouint(wname, 10, &dmic);
  1189. if (ret < 0) {
  1190. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1191. __func__);
  1192. return -EINVAL;
  1193. }
  1194. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1195. w->name, event);
  1196. switch (dmic) {
  1197. case 0:
  1198. case 1:
  1199. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1200. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1201. break;
  1202. case 2:
  1203. case 3:
  1204. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1205. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1206. break;
  1207. case 4:
  1208. case 5:
  1209. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1210. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1211. break;
  1212. default:
  1213. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1214. __func__);
  1215. return -EINVAL;
  1216. };
  1217. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1218. __func__, event, dmic, *dmic_clk_cnt);
  1219. switch (event) {
  1220. case SND_SOC_DAPM_PRE_PMU:
  1221. snd_soc_component_update_bits(component,
  1222. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1223. snd_soc_component_update_bits(component,
  1224. dmic_clk_reg, 0x07, 0x02);
  1225. snd_soc_component_update_bits(component,
  1226. dmic_clk_reg, 0x08, 0x08);
  1227. snd_soc_component_update_bits(component,
  1228. dmic_clk_reg, 0x70, 0x20);
  1229. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1230. wcd937x->tx_swr_dev->dev_num,
  1231. true);
  1232. break;
  1233. case SND_SOC_DAPM_POST_PMD:
  1234. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1235. break;
  1236. };
  1237. return 0;
  1238. }
  1239. /*
  1240. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1241. * @micb_mv: micbias in mv
  1242. *
  1243. * return register value converted
  1244. */
  1245. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1246. {
  1247. /* min micbias voltage is 1V and maximum is 2.85V */
  1248. if (micb_mv < 1000 || micb_mv > 2850) {
  1249. pr_err("%s: unsupported micbias voltage\n", __func__);
  1250. return -EINVAL;
  1251. }
  1252. return (micb_mv - 1000) / 50;
  1253. }
  1254. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1255. /*
  1256. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1257. * @component: handle to snd_soc_component *
  1258. * @req_volt: micbias voltage to be set
  1259. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1260. *
  1261. * return 0 if adjustment is success or error code in case of failure
  1262. */
  1263. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1264. int req_volt, int micb_num)
  1265. {
  1266. struct wcd937x_priv *wcd937x =
  1267. snd_soc_component_get_drvdata(component);
  1268. int cur_vout_ctl, req_vout_ctl;
  1269. int micb_reg, micb_val, micb_en;
  1270. int ret = 0;
  1271. switch (micb_num) {
  1272. case MIC_BIAS_1:
  1273. micb_reg = WCD937X_ANA_MICB1;
  1274. break;
  1275. case MIC_BIAS_2:
  1276. micb_reg = WCD937X_ANA_MICB2;
  1277. break;
  1278. case MIC_BIAS_3:
  1279. micb_reg = WCD937X_ANA_MICB3;
  1280. break;
  1281. default:
  1282. return -EINVAL;
  1283. }
  1284. mutex_lock(&wcd937x->micb_lock);
  1285. /*
  1286. * If requested micbias voltage is same as current micbias
  1287. * voltage, then just return. Otherwise, adjust voltage as
  1288. * per requested value. If micbias is already enabled, then
  1289. * to avoid slow micbias ramp-up or down enable pull-up
  1290. * momentarily, change the micbias value and then re-enable
  1291. * micbias.
  1292. */
  1293. micb_val = snd_soc_component_read(component, micb_reg);
  1294. micb_en = (micb_val & 0xC0) >> 6;
  1295. cur_vout_ctl = micb_val & 0x3F;
  1296. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1297. if (req_vout_ctl < 0) {
  1298. ret = -EINVAL;
  1299. goto exit;
  1300. }
  1301. if (cur_vout_ctl == req_vout_ctl) {
  1302. ret = 0;
  1303. goto exit;
  1304. }
  1305. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1306. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1307. req_volt, micb_en);
  1308. if (micb_en == 0x1)
  1309. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1310. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1311. if (micb_en == 0x1) {
  1312. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1313. /*
  1314. * Add 2ms delay as per HW requirement after enabling
  1315. * micbias
  1316. */
  1317. usleep_range(2000, 2100);
  1318. }
  1319. exit:
  1320. mutex_unlock(&wcd937x->micb_lock);
  1321. return ret;
  1322. }
  1323. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1324. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1325. struct snd_kcontrol *kcontrol,
  1326. int event)
  1327. {
  1328. struct snd_soc_component *component =
  1329. snd_soc_dapm_to_component(w->dapm);
  1330. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1331. int ret = 0;
  1332. switch (event) {
  1333. case SND_SOC_DAPM_PRE_PMU:
  1334. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1335. /* Enable BCS for Headset mic */
  1336. if (w->shift == 1 && !(snd_soc_component_read(component,
  1337. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1338. if (!wcd937x->bcs_dis) {
  1339. wcd937x_tx_connect_port(
  1340. component, MBHC, true);
  1341. set_bit(AMIC2_BCS_ENABLE,
  1342. &wcd937x->status_mask);
  1343. }
  1344. }
  1345. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1346. } else {
  1347. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1348. }
  1349. break;
  1350. case SND_SOC_DAPM_POST_PMD:
  1351. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1352. wcd937x->tx_swr_dev->dev_num,
  1353. false);
  1354. break;
  1355. };
  1356. return ret;
  1357. }
  1358. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1359. struct snd_kcontrol *kcontrol,
  1360. int event){
  1361. struct snd_soc_component *component =
  1362. snd_soc_dapm_to_component(w->dapm);
  1363. struct wcd937x_priv *wcd937x =
  1364. snd_soc_component_get_drvdata(component);
  1365. int ret = 0;
  1366. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1367. w->name, event);
  1368. switch (event) {
  1369. case SND_SOC_DAPM_PRE_PMU:
  1370. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1371. wcd937x->ana_clk_count++;
  1372. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1373. wcd937x->adc_count++;
  1374. snd_soc_component_update_bits(component,
  1375. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1376. snd_soc_component_update_bits(component,
  1377. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1378. snd_soc_component_update_bits(component,
  1379. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1380. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1381. wcd937x->tx_swr_dev->dev_num,
  1382. true);
  1383. break;
  1384. case SND_SOC_DAPM_POST_PMD:
  1385. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1386. if (w->shift == 1 &&
  1387. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1388. wcd937x_tx_connect_port(component, MBHC, false);
  1389. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1390. }
  1391. wcd937x->adc_count--;
  1392. if (wcd937x->adc_count <= 0) {
  1393. snd_soc_component_update_bits(component,
  1394. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1395. wcd937x->adc_count = 0;
  1396. }
  1397. break;
  1398. };
  1399. return ret;
  1400. }
  1401. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1402. struct snd_kcontrol *kcontrol, int event)
  1403. {
  1404. struct snd_soc_component *component =
  1405. snd_soc_dapm_to_component(w->dapm);
  1406. struct wcd937x_priv *wcd937x =
  1407. snd_soc_component_get_drvdata(component);
  1408. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1409. w->name, event);
  1410. switch (event) {
  1411. case SND_SOC_DAPM_PRE_PMU:
  1412. snd_soc_component_update_bits(component,
  1413. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1414. snd_soc_component_update_bits(component,
  1415. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1416. snd_soc_component_update_bits(component,
  1417. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1418. snd_soc_component_update_bits(component,
  1419. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1420. snd_soc_component_update_bits(component,
  1421. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1422. snd_soc_component_update_bits(component,
  1423. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1424. snd_soc_component_update_bits(component,
  1425. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1426. snd_soc_component_update_bits(component,
  1427. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1428. snd_soc_component_update_bits(component,
  1429. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1430. break;
  1431. case SND_SOC_DAPM_POST_PMD:
  1432. if (wcd937x->adc_count == 0) {
  1433. snd_soc_component_update_bits(component,
  1434. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1435. snd_soc_component_update_bits(component,
  1436. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1437. snd_soc_component_update_bits(component,
  1438. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1439. snd_soc_component_update_bits(component,
  1440. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1441. snd_soc_component_update_bits(component,
  1442. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1443. }
  1444. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1445. wcd937x->ana_clk_count--;
  1446. if (wcd937x->ana_clk_count <= 0) {
  1447. snd_soc_component_update_bits(component,
  1448. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1449. wcd937x->ana_clk_count = 0;
  1450. }
  1451. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1452. break;
  1453. };
  1454. return 0;
  1455. }
  1456. int wcd937x_micbias_control(struct snd_soc_component *component,
  1457. int micb_num, int req, bool is_dapm)
  1458. {
  1459. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1460. int micb_index = micb_num - 1;
  1461. u16 micb_reg;
  1462. int pre_off_event = 0, post_off_event = 0;
  1463. int post_on_event = 0, post_dapm_off = 0;
  1464. int post_dapm_on = 0;
  1465. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1466. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1467. __func__, micb_index);
  1468. return -EINVAL;
  1469. }
  1470. switch (micb_num) {
  1471. case MIC_BIAS_1:
  1472. micb_reg = WCD937X_ANA_MICB1;
  1473. break;
  1474. case MIC_BIAS_2:
  1475. micb_reg = WCD937X_ANA_MICB2;
  1476. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1477. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1478. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1479. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1480. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1481. break;
  1482. case MIC_BIAS_3:
  1483. micb_reg = WCD937X_ANA_MICB3;
  1484. break;
  1485. default:
  1486. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1487. __func__, micb_num);
  1488. return -EINVAL;
  1489. };
  1490. mutex_lock(&wcd937x->micb_lock);
  1491. switch (req) {
  1492. case MICB_PULLUP_ENABLE:
  1493. wcd937x->pullup_ref[micb_index]++;
  1494. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1495. (wcd937x->micb_ref[micb_index] == 0))
  1496. snd_soc_component_update_bits(component, micb_reg,
  1497. 0xC0, 0x80);
  1498. break;
  1499. case MICB_PULLUP_DISABLE:
  1500. if (wcd937x->pullup_ref[micb_index] > 0)
  1501. wcd937x->pullup_ref[micb_index]--;
  1502. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1503. (wcd937x->micb_ref[micb_index] == 0))
  1504. snd_soc_component_update_bits(component, micb_reg,
  1505. 0xC0, 0x00);
  1506. break;
  1507. case MICB_ENABLE:
  1508. wcd937x->micb_ref[micb_index]++;
  1509. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1510. wcd937x->ana_clk_count++;
  1511. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1512. if (wcd937x->micb_ref[micb_index] == 1) {
  1513. snd_soc_component_update_bits(component,
  1514. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1515. snd_soc_component_update_bits(component,
  1516. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1517. snd_soc_component_update_bits(component,
  1518. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1519. snd_soc_component_update_bits(component,
  1520. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1521. snd_soc_component_update_bits(component,
  1522. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1523. snd_soc_component_update_bits(component,
  1524. micb_reg, 0xC0, 0x40);
  1525. if (post_on_event)
  1526. blocking_notifier_call_chain(
  1527. &wcd937x->mbhc->notifier, post_on_event,
  1528. &wcd937x->mbhc->wcd_mbhc);
  1529. }
  1530. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1531. blocking_notifier_call_chain(
  1532. &wcd937x->mbhc->notifier, post_dapm_on,
  1533. &wcd937x->mbhc->wcd_mbhc);
  1534. break;
  1535. case MICB_DISABLE:
  1536. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1537. wcd937x->ana_clk_count--;
  1538. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1539. if (wcd937x->micb_ref[micb_index] > 0)
  1540. wcd937x->micb_ref[micb_index]--;
  1541. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1542. (wcd937x->pullup_ref[micb_index] > 0))
  1543. snd_soc_component_update_bits(component, micb_reg,
  1544. 0xC0, 0x80);
  1545. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1546. (wcd937x->pullup_ref[micb_index] == 0)) {
  1547. if (pre_off_event && wcd937x->mbhc)
  1548. blocking_notifier_call_chain(
  1549. &wcd937x->mbhc->notifier, pre_off_event,
  1550. &wcd937x->mbhc->wcd_mbhc);
  1551. snd_soc_component_update_bits(component, micb_reg,
  1552. 0xC0, 0x00);
  1553. if (post_off_event && wcd937x->mbhc)
  1554. blocking_notifier_call_chain(
  1555. &wcd937x->mbhc->notifier,
  1556. post_off_event,
  1557. &wcd937x->mbhc->wcd_mbhc);
  1558. }
  1559. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1560. if (wcd937x->ana_clk_count <= 0) {
  1561. snd_soc_component_update_bits(component,
  1562. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1563. 0x10, 0x00);
  1564. wcd937x->ana_clk_count = 0;
  1565. }
  1566. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1567. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1568. blocking_notifier_call_chain(
  1569. &wcd937x->mbhc->notifier, post_dapm_off,
  1570. &wcd937x->mbhc->wcd_mbhc);
  1571. break;
  1572. };
  1573. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1574. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1575. wcd937x->pullup_ref[micb_index]);
  1576. mutex_unlock(&wcd937x->micb_lock);
  1577. return 0;
  1578. }
  1579. EXPORT_SYMBOL(wcd937x_micbias_control);
  1580. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1581. bool bcs_disable)
  1582. {
  1583. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1584. if (wcd937x->update_wcd_event) {
  1585. if (bcs_disable)
  1586. wcd937x->update_wcd_event(wcd937x->handle,
  1587. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1588. else
  1589. wcd937x->update_wcd_event(wcd937x->handle,
  1590. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1591. }
  1592. }
  1593. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1594. {
  1595. int ret = 0;
  1596. uint8_t devnum = 0;
  1597. int num_retry = NUM_ATTEMPTS;
  1598. do {
  1599. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1600. if (ret) {
  1601. dev_err(&swr_dev->dev,
  1602. "%s get devnum %d for dev addr %lx failed\n",
  1603. __func__, devnum, swr_dev->addr);
  1604. /* retry after 1ms */
  1605. usleep_range(1000, 1010);
  1606. }
  1607. } while (ret && --num_retry);
  1608. swr_dev->dev_num = devnum;
  1609. return 0;
  1610. }
  1611. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1612. struct wcd_mbhc_config *mbhc_cfg)
  1613. {
  1614. if (mbhc_cfg->enable_usbc_analog) {
  1615. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1616. & 0x20))
  1617. return true;
  1618. }
  1619. return false;
  1620. }
  1621. static int wcd937x_event_notify(struct notifier_block *block,
  1622. unsigned long val,
  1623. void *data)
  1624. {
  1625. u16 event = (val & 0xffff);
  1626. u16 amic = (val >> 0x10);
  1627. u16 mask = 0x40, reg = 0x0;
  1628. int ret = 0;
  1629. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1630. struct snd_soc_component *component = wcd937x->component;
  1631. struct wcd_mbhc *mbhc;
  1632. switch (event) {
  1633. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1634. if (amic == 0x1 || amic == 0x2)
  1635. reg = WCD937X_ANA_TX_CH2;
  1636. else if (amic == 0x3)
  1637. reg = WCD937X_ANA_TX_CH3_HPF;
  1638. else
  1639. return 0;
  1640. if (amic == 0x2)
  1641. mask = 0x20;
  1642. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1643. break;
  1644. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1645. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1646. 0xC0, 0x00);
  1647. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1648. 0x80, 0x00);
  1649. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1650. 0x80, 0x00);
  1651. break;
  1652. case BOLERO_SLV_EVT_SSR_DOWN:
  1653. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1654. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1655. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1656. mbhc->mbhc_cfg);
  1657. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1658. wcd937x_reset_low(wcd937x->dev);
  1659. break;
  1660. case BOLERO_SLV_EVT_SSR_UP:
  1661. wcd937x_reset(wcd937x->dev);
  1662. /* allow reset to take effect */
  1663. usleep_range(10000, 10010);
  1664. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1665. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1666. wcd937x_init_reg(component);
  1667. regcache_mark_dirty(wcd937x->regmap);
  1668. regcache_sync(wcd937x->regmap);
  1669. /* Initialize MBHC module */
  1670. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1671. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1672. if (ret) {
  1673. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1674. __func__);
  1675. } else {
  1676. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1677. if (wcd937x->usbc_hs_status)
  1678. mdelay(500);
  1679. }
  1680. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1681. break;
  1682. default:
  1683. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1684. event);
  1685. break;
  1686. }
  1687. return 0;
  1688. }
  1689. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1690. int event)
  1691. {
  1692. struct snd_soc_component *component =
  1693. snd_soc_dapm_to_component(w->dapm);
  1694. int micb_num;
  1695. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1696. __func__, w->name, event);
  1697. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1698. micb_num = MIC_BIAS_1;
  1699. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1700. micb_num = MIC_BIAS_2;
  1701. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1702. micb_num = MIC_BIAS_3;
  1703. else
  1704. return -EINVAL;
  1705. switch (event) {
  1706. case SND_SOC_DAPM_PRE_PMU:
  1707. wcd937x_micbias_control(component, micb_num,
  1708. MICB_ENABLE, true);
  1709. break;
  1710. case SND_SOC_DAPM_POST_PMU:
  1711. usleep_range(1000, 1100);
  1712. break;
  1713. case SND_SOC_DAPM_POST_PMD:
  1714. wcd937x_micbias_control(component, micb_num,
  1715. MICB_DISABLE, true);
  1716. break;
  1717. };
  1718. return 0;
  1719. }
  1720. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1721. struct snd_kcontrol *kcontrol,
  1722. int event)
  1723. {
  1724. return __wcd937x_codec_enable_micbias(w, event);
  1725. }
  1726. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1727. int event)
  1728. {
  1729. struct snd_soc_component *component =
  1730. snd_soc_dapm_to_component(w->dapm);
  1731. int micb_num;
  1732. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1733. __func__, w->name, event);
  1734. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1735. micb_num = MIC_BIAS_1;
  1736. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1737. micb_num = MIC_BIAS_2;
  1738. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1739. micb_num = MIC_BIAS_3;
  1740. else
  1741. return -EINVAL;
  1742. switch (event) {
  1743. case SND_SOC_DAPM_PRE_PMU:
  1744. wcd937x_micbias_control(component, micb_num,
  1745. MICB_PULLUP_ENABLE, true);
  1746. break;
  1747. case SND_SOC_DAPM_POST_PMU:
  1748. /* 1 msec delay as per HW requirement */
  1749. usleep_range(1000, 1100);
  1750. break;
  1751. case SND_SOC_DAPM_POST_PMD:
  1752. wcd937x_micbias_control(component, micb_num,
  1753. MICB_PULLUP_DISABLE, true);
  1754. break;
  1755. };
  1756. return 0;
  1757. }
  1758. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1759. struct snd_kcontrol *kcontrol,
  1760. int event)
  1761. {
  1762. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1763. }
  1764. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1765. struct snd_ctl_elem_value *ucontrol)
  1766. {
  1767. struct snd_soc_component *component =
  1768. snd_soc_kcontrol_component(kcontrol);
  1769. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1770. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1771. return 0;
  1772. }
  1773. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1774. struct snd_ctl_elem_value *ucontrol)
  1775. {
  1776. struct snd_soc_component *component =
  1777. snd_soc_kcontrol_component(kcontrol);
  1778. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1779. u32 mode_val;
  1780. mode_val = ucontrol->value.enumerated.item[0];
  1781. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1782. if (mode_val == 0) {
  1783. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1784. __func__);
  1785. mode_val = 3; /* enum will be updated later */
  1786. }
  1787. wcd937x->hph_mode = mode_val;
  1788. return 0;
  1789. }
  1790. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1791. struct snd_ctl_elem_value *ucontrol)
  1792. {
  1793. struct snd_soc_component *component =
  1794. snd_soc_kcontrol_component(kcontrol);
  1795. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1796. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1797. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1798. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1799. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1800. return 0;
  1801. }
  1802. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1803. struct snd_ctl_elem_value *ucontrol)
  1804. {
  1805. struct snd_soc_component *component =
  1806. snd_soc_kcontrol_component(kcontrol);
  1807. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1808. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1809. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1810. __func__, pwr_level);
  1811. if (strnstr(kcontrol->id.name, "CH1",
  1812. sizeof(kcontrol->id.name))) {
  1813. snd_soc_component_update_bits(component,
  1814. WCD937X_ANA_TX_CH1, 0x60,
  1815. pwr_level << 0x5);
  1816. wcd937x->tx_ch_pwr[0] = pwr_level;
  1817. } else if (strnstr(kcontrol->id.name, "CH3",
  1818. sizeof(kcontrol->id.name))) {
  1819. snd_soc_component_update_bits(component,
  1820. WCD937X_ANA_TX_CH3, 0x60,
  1821. pwr_level << 0x5);
  1822. wcd937x->tx_ch_pwr[1] = pwr_level;
  1823. }
  1824. return 0;
  1825. }
  1826. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1827. struct snd_ctl_elem_value *ucontrol)
  1828. {
  1829. u8 ear_pa_gain = 0;
  1830. struct snd_soc_component *component =
  1831. snd_soc_kcontrol_component(kcontrol);
  1832. ear_pa_gain = snd_soc_component_read(component,
  1833. WCD937X_ANA_EAR_COMPANDER_CTL);
  1834. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1835. ucontrol->value.integer.value[0] = ear_pa_gain;
  1836. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1837. ear_pa_gain);
  1838. return 0;
  1839. }
  1840. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1841. struct snd_ctl_elem_value *ucontrol)
  1842. {
  1843. u8 ear_pa_gain = 0;
  1844. struct snd_soc_component *component =
  1845. snd_soc_kcontrol_component(kcontrol);
  1846. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1847. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1848. __func__, ucontrol->value.integer.value[0]);
  1849. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1850. if (!wcd937x->comp1_enable) {
  1851. snd_soc_component_update_bits(component,
  1852. WCD937X_ANA_EAR_COMPANDER_CTL,
  1853. 0x7C, ear_pa_gain);
  1854. }
  1855. return 0;
  1856. }
  1857. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1858. struct snd_ctl_elem_value *ucontrol)
  1859. {
  1860. struct snd_soc_component *component =
  1861. snd_soc_kcontrol_component(kcontrol);
  1862. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1863. bool hphr;
  1864. struct soc_multi_mixer_control *mc;
  1865. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1866. hphr = mc->shift;
  1867. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1868. wcd937x->comp1_enable;
  1869. return 0;
  1870. }
  1871. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1872. struct snd_ctl_elem_value *ucontrol)
  1873. {
  1874. struct snd_soc_component *component =
  1875. snd_soc_kcontrol_component(kcontrol);
  1876. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1877. int value = ucontrol->value.integer.value[0];
  1878. bool hphr;
  1879. struct soc_multi_mixer_control *mc;
  1880. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1881. hphr = mc->shift;
  1882. if (hphr)
  1883. wcd937x->comp2_enable = value;
  1884. else
  1885. wcd937x->comp1_enable = value;
  1886. return 0;
  1887. }
  1888. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1889. struct snd_kcontrol *kcontrol,
  1890. int event)
  1891. {
  1892. struct snd_soc_component *component =
  1893. snd_soc_dapm_to_component(w->dapm);
  1894. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1895. struct wcd937x_pdata *pdata = NULL;
  1896. int ret = 0;
  1897. pdata = dev_get_platdata(wcd937x->dev);
  1898. if (!pdata) {
  1899. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1900. return -EINVAL;
  1901. }
  1902. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1903. w->name, event);
  1904. switch (event) {
  1905. case SND_SOC_DAPM_PRE_PMU:
  1906. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1907. dev_dbg(component->dev,
  1908. "%s: buck already in enabled state\n",
  1909. __func__);
  1910. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1911. return 0;
  1912. }
  1913. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1914. wcd937x->supplies,
  1915. pdata->regulator,
  1916. pdata->num_supplies,
  1917. "cdc-vdd-buck");
  1918. if (ret == -EINVAL) {
  1919. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1920. __func__);
  1921. return ret;
  1922. }
  1923. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1924. /*
  1925. * 200us sleep is required after LDO15 is enabled as per
  1926. * HW requirement
  1927. */
  1928. usleep_range(200, 250);
  1929. break;
  1930. case SND_SOC_DAPM_POST_PMD:
  1931. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1932. break;
  1933. }
  1934. return 0;
  1935. }
  1936. static const char * const rx_hph_mode_mux_text[] = {
  1937. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1938. "CLS_H_ULP", "CLS_AB_HIFI",
  1939. };
  1940. const char * const tx_master_ch_text[] = {
  1941. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1942. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1943. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1944. "SWRM_PCM_IN",
  1945. };
  1946. const struct soc_enum tx_master_ch_enum =
  1947. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1948. tx_master_ch_text);
  1949. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1950. {
  1951. u8 ch_type = 0;
  1952. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1953. ch_type = ADC1;
  1954. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1955. ch_type = ADC2;
  1956. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1957. ch_type = ADC3;
  1958. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1959. ch_type = DMIC0;
  1960. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1961. ch_type = DMIC1;
  1962. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1963. ch_type = MBHC;
  1964. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1965. ch_type = DMIC2;
  1966. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1967. ch_type = DMIC3;
  1968. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1969. ch_type = DMIC4;
  1970. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1971. ch_type = DMIC5;
  1972. else
  1973. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1974. if (ch_type)
  1975. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1976. else
  1977. *ch_idx = -EINVAL;
  1978. }
  1979. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1980. struct snd_ctl_elem_value *ucontrol)
  1981. {
  1982. struct snd_soc_component *component =
  1983. snd_soc_kcontrol_component(kcontrol);
  1984. struct wcd937x_priv *wcd937x = NULL;
  1985. int slave_ch_idx = -EINVAL;
  1986. if (component == NULL)
  1987. return -EINVAL;
  1988. wcd937x = snd_soc_component_get_drvdata(component);
  1989. if (wcd937x == NULL)
  1990. return -EINVAL;
  1991. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1992. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1993. return -EINVAL;
  1994. ucontrol->value.integer.value[0] =
  1995. wcd937x_slave_get_master_ch_val(
  1996. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1997. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1998. __func__, ucontrol->value.integer.value[0]);
  1999. return 0;
  2000. }
  2001. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2002. struct snd_ctl_elem_value *ucontrol)
  2003. {
  2004. struct snd_soc_component *component =
  2005. snd_soc_kcontrol_component(kcontrol);
  2006. struct wcd937x_priv *wcd937x;
  2007. int slave_ch_idx = -EINVAL, idx = 0;
  2008. if (component == NULL)
  2009. return -EINVAL;
  2010. wcd937x = snd_soc_component_get_drvdata(component);
  2011. if (wcd937x == NULL)
  2012. return -EINVAL;
  2013. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2014. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  2015. return -EINVAL;
  2016. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2017. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2018. __func__, ucontrol->value.enumerated.item[0]);
  2019. idx = ucontrol->value.enumerated.item[0];
  2020. if (idx < 0 || idx >= ARRAY_SIZE(wcd937x_swr_master_ch_map))
  2021. return -EINVAL;
  2022. wcd937x->tx_master_ch_map[slave_ch_idx] =
  2023. wcd937x_slave_get_master_ch(idx);
  2024. return 0;
  2025. }
  2026. static int wcd937x_bcs_get(struct snd_kcontrol *kcontrol,
  2027. struct snd_ctl_elem_value *ucontrol)
  2028. {
  2029. struct snd_soc_component *component =
  2030. snd_soc_kcontrol_component(kcontrol);
  2031. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2032. ucontrol->value.integer.value[0] = wcd937x->bcs_dis;
  2033. return 0;
  2034. }
  2035. static int wcd937x_bcs_put(struct snd_kcontrol *kcontrol,
  2036. struct snd_ctl_elem_value *ucontrol)
  2037. {
  2038. struct snd_soc_component *component =
  2039. snd_soc_kcontrol_component(kcontrol);
  2040. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2041. wcd937x->bcs_dis = ucontrol->value.integer.value[0];
  2042. dev_dbg(component->dev, "%s: BCS Disable %d\n", __func__, wcd937x->bcs_dis);
  2043. return 0;
  2044. }
  2045. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  2046. "L0", "L1", "L2", "L3",
  2047. };
  2048. static const char * const wcd937x_ear_pa_gain_text[] = {
  2049. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2050. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2051. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2052. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2053. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2054. };
  2055. static const struct soc_enum rx_hph_mode_mux_enum =
  2056. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2057. rx_hph_mode_mux_text);
  2058. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  2059. wcd937x_ear_pa_gain_text);
  2060. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  2061. wcd937x_tx_ch_pwr_level_text);
  2062. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  2063. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  2064. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  2065. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2066. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  2067. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2068. wcd937x_get_compander, wcd937x_set_compander),
  2069. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2070. wcd937x_get_compander, wcd937x_set_compander),
  2071. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2072. wcd937x_bcs_get, wcd937x_bcs_put),
  2073. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  2074. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  2075. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  2076. analog_gain),
  2077. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  2078. analog_gain),
  2079. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  2080. analog_gain),
  2081. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2082. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2083. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2084. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2085. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2086. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2087. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2088. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2089. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2090. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2091. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2092. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2093. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2094. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2095. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2096. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2097. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2098. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2099. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2100. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2101. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  2102. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2103. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  2104. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2105. };
  2106. static const struct snd_kcontrol_new adc1_switch[] = {
  2107. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2108. };
  2109. static const struct snd_kcontrol_new adc2_switch[] = {
  2110. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2111. };
  2112. static const struct snd_kcontrol_new adc3_switch[] = {
  2113. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2114. };
  2115. static const struct snd_kcontrol_new dmic1_switch[] = {
  2116. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2117. };
  2118. static const struct snd_kcontrol_new dmic2_switch[] = {
  2119. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2120. };
  2121. static const struct snd_kcontrol_new dmic3_switch[] = {
  2122. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2123. };
  2124. static const struct snd_kcontrol_new dmic4_switch[] = {
  2125. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2126. };
  2127. static const struct snd_kcontrol_new dmic5_switch[] = {
  2128. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2129. };
  2130. static const struct snd_kcontrol_new dmic6_switch[] = {
  2131. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2132. };
  2133. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2134. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2135. };
  2136. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2137. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2138. };
  2139. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2140. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2141. };
  2142. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2143. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2144. };
  2145. static const char * const adc2_mux_text[] = {
  2146. "INP2", "INP3"
  2147. };
  2148. static const char * const rdac3_mux_text[] = {
  2149. "RX1", "RX3"
  2150. };
  2151. static const struct soc_enum adc2_enum =
  2152. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2153. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2154. static const struct soc_enum rdac3_enum =
  2155. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2156. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2157. static const struct snd_kcontrol_new tx_adc2_mux =
  2158. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2159. static const struct snd_kcontrol_new rx_rdac3_mux =
  2160. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2161. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2162. /*input widgets*/
  2163. SND_SOC_DAPM_INPUT("AMIC1"),
  2164. SND_SOC_DAPM_INPUT("AMIC2"),
  2165. SND_SOC_DAPM_INPUT("AMIC3"),
  2166. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2167. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2168. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2169. /*
  2170. * These dummy widgets are null connected to WCD937x dapm input and
  2171. * output widgets which are not actual path endpoints. This ensures
  2172. * dapm doesnt set these dapm input and output widgets as endpoints.
  2173. */
  2174. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2175. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2176. /*tx widgets*/
  2177. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2178. wcd937x_codec_enable_adc,
  2179. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2180. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2181. wcd937x_codec_enable_adc,
  2182. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2183. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2184. NULL, 0, wcd937x_enable_req,
  2185. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2186. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2187. NULL, 0, wcd937x_enable_req,
  2188. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2189. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2190. &tx_adc2_mux),
  2191. /*tx mixers*/
  2192. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2193. adc1_switch, ARRAY_SIZE(adc1_switch),
  2194. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2195. SND_SOC_DAPM_POST_PMD),
  2196. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2197. adc2_switch, ARRAY_SIZE(adc2_switch),
  2198. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2199. SND_SOC_DAPM_POST_PMD),
  2200. /* micbias widgets*/
  2201. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2202. wcd937x_codec_enable_micbias,
  2203. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2204. SND_SOC_DAPM_POST_PMD),
  2205. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2206. wcd937x_codec_enable_micbias,
  2207. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2208. SND_SOC_DAPM_POST_PMD),
  2209. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2210. wcd937x_codec_enable_micbias,
  2211. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2212. SND_SOC_DAPM_POST_PMD),
  2213. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2214. wcd937x_codec_enable_vdd_buck,
  2215. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2216. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2217. wcd937x_enable_clsh,
  2218. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2219. /*rx widgets*/
  2220. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2221. wcd937x_codec_enable_ear_pa,
  2222. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2223. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2224. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2225. wcd937x_codec_enable_aux_pa,
  2226. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2227. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2228. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2229. wcd937x_codec_enable_hphl_pa,
  2230. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2231. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2232. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2233. wcd937x_codec_enable_hphr_pa,
  2234. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2235. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2236. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2237. wcd937x_codec_hphl_dac_event,
  2238. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2239. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2240. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2241. wcd937x_codec_hphr_dac_event,
  2242. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2243. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2244. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2245. wcd937x_codec_ear_dac_event,
  2246. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2247. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2248. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2249. wcd937x_codec_aux_dac_event,
  2250. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2251. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2252. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2253. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2254. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2255. SND_SOC_DAPM_POST_PMD),
  2256. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2257. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2258. SND_SOC_DAPM_POST_PMD),
  2259. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2260. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2261. SND_SOC_DAPM_POST_PMD),
  2262. /* rx mixer widgets*/
  2263. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2264. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2265. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2266. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2267. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2268. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2269. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2270. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2271. /*output widgets tx*/
  2272. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2273. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2274. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2275. /*output widgets rx*/
  2276. SND_SOC_DAPM_OUTPUT("EAR"),
  2277. SND_SOC_DAPM_OUTPUT("AUX"),
  2278. SND_SOC_DAPM_OUTPUT("HPHL"),
  2279. SND_SOC_DAPM_OUTPUT("HPHR"),
  2280. /* micbias pull up widgets*/
  2281. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2282. wcd937x_codec_enable_micbias_pullup,
  2283. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2284. SND_SOC_DAPM_POST_PMD),
  2285. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2286. wcd937x_codec_enable_micbias_pullup,
  2287. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2288. SND_SOC_DAPM_POST_PMD),
  2289. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2290. wcd937x_codec_enable_micbias_pullup,
  2291. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2292. SND_SOC_DAPM_POST_PMD),
  2293. };
  2294. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2295. /*input widgets*/
  2296. SND_SOC_DAPM_INPUT("AMIC4"),
  2297. /*tx widgets*/
  2298. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2299. wcd937x_codec_enable_adc,
  2300. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2301. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2302. NULL, 0, wcd937x_enable_req,
  2303. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2304. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2305. wcd937x_codec_enable_dmic,
  2306. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2307. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2308. wcd937x_codec_enable_dmic,
  2309. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2310. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2311. wcd937x_codec_enable_dmic,
  2312. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2313. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2314. wcd937x_codec_enable_dmic,
  2315. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2316. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2317. wcd937x_codec_enable_dmic,
  2318. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2319. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2320. wcd937x_codec_enable_dmic,
  2321. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2322. /*tx mixer widgets*/
  2323. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2324. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2325. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2326. SND_SOC_DAPM_POST_PMD),
  2327. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2328. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2329. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2330. SND_SOC_DAPM_POST_PMD),
  2331. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2332. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2333. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2334. SND_SOC_DAPM_POST_PMD),
  2335. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2336. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2337. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2338. SND_SOC_DAPM_POST_PMD),
  2339. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2340. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2341. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2342. SND_SOC_DAPM_POST_PMD),
  2343. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2344. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2345. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2346. SND_SOC_DAPM_POST_PMD),
  2347. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2348. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2349. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2350. /*output widgets*/
  2351. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2352. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2353. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2354. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2355. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2356. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2357. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2358. };
  2359. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2360. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2361. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2362. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2363. {"ADC1 REQ", NULL, "ADC1"},
  2364. {"ADC1", NULL, "AMIC1"},
  2365. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2366. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2367. {"ADC2 REQ", NULL, "ADC2"},
  2368. {"ADC2", NULL, "ADC2 MUX"},
  2369. {"ADC2 MUX", "INP3", "AMIC3"},
  2370. {"ADC2 MUX", "INP2", "AMIC2"},
  2371. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2372. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2373. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2374. {"RX1", NULL, "IN1_HPHL"},
  2375. {"RDAC1", NULL, "RX1"},
  2376. {"HPHL_RDAC", "Switch", "RDAC1"},
  2377. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2378. {"HPHL", NULL, "HPHL PGA"},
  2379. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2380. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2381. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2382. {"RX2", NULL, "IN2_HPHR"},
  2383. {"RDAC2", NULL, "RX2"},
  2384. {"HPHR_RDAC", "Switch", "RDAC2"},
  2385. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2386. {"HPHR", NULL, "HPHR PGA"},
  2387. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2388. {"IN3_AUX", NULL, "VDD_BUCK"},
  2389. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2390. {"RX3", NULL, "IN3_AUX"},
  2391. {"RDAC4", NULL, "RX3"},
  2392. {"AUX_RDAC", "Switch", "RDAC4"},
  2393. {"AUX PGA", NULL, "AUX_RDAC"},
  2394. {"AUX", NULL, "AUX PGA"},
  2395. {"RDAC3_MUX", "RX3", "RX3"},
  2396. {"RDAC3_MUX", "RX1", "RX1"},
  2397. {"RDAC3", NULL, "RDAC3_MUX"},
  2398. {"EAR_RDAC", "Switch", "RDAC3"},
  2399. {"EAR PGA", NULL, "EAR_RDAC"},
  2400. {"EAR", NULL, "EAR PGA"},
  2401. };
  2402. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2403. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2404. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2405. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2406. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2407. {"ADC3 REQ", NULL, "ADC3"},
  2408. {"ADC3", NULL, "AMIC4"},
  2409. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2410. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2411. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2412. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2413. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2414. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2415. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2416. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2417. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2418. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2419. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2420. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2421. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2422. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2423. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2424. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2425. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2426. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2427. };
  2428. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2429. void *file_private_data,
  2430. struct file *file,
  2431. char __user *buf, size_t count,
  2432. loff_t pos)
  2433. {
  2434. struct wcd937x_priv *priv;
  2435. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2436. int len = 0;
  2437. priv = (struct wcd937x_priv *) entry->private_data;
  2438. if (!priv) {
  2439. pr_err("%s: wcd937x priv is null\n", __func__);
  2440. return -EINVAL;
  2441. }
  2442. switch (priv->version) {
  2443. case WCD937X_VERSION_1_0:
  2444. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2445. break;
  2446. default:
  2447. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2448. }
  2449. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2450. }
  2451. static struct snd_info_entry_ops wcd937x_info_ops = {
  2452. .read = wcd937x_version_read,
  2453. };
  2454. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2455. void *file_private_data,
  2456. struct file *file,
  2457. char __user *buf, size_t count,
  2458. loff_t pos)
  2459. {
  2460. struct wcd937x_priv *priv;
  2461. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2462. int len = 0;
  2463. priv = (struct wcd937x_priv *) entry->private_data;
  2464. if (!priv) {
  2465. pr_err("%s: wcd937x priv is null\n", __func__);
  2466. return -EINVAL;
  2467. }
  2468. switch (priv->variant) {
  2469. case WCD9370_VARIANT:
  2470. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2471. break;
  2472. case WCD9375_VARIANT:
  2473. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2474. break;
  2475. default:
  2476. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2477. }
  2478. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2479. }
  2480. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2481. .read = wcd937x_variant_read,
  2482. };
  2483. /*
  2484. * wcd937x_info_create_codec_entry - creates wcd937x module
  2485. * @codec_root: The parent directory
  2486. * @component: component instance
  2487. *
  2488. * Creates wcd937x module, variant and version entry under the given
  2489. * parent directory.
  2490. *
  2491. * Return: 0 on success or negative error code on failure.
  2492. */
  2493. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2494. struct snd_soc_component *component)
  2495. {
  2496. struct snd_info_entry *version_entry;
  2497. struct snd_info_entry *variant_entry;
  2498. struct wcd937x_priv *priv;
  2499. struct snd_soc_card *card;
  2500. if (!codec_root || !component)
  2501. return -EINVAL;
  2502. priv = snd_soc_component_get_drvdata(component);
  2503. if (priv->entry) {
  2504. dev_dbg(priv->dev,
  2505. "%s:wcd937x module already created\n", __func__);
  2506. return 0;
  2507. }
  2508. card = component->card;
  2509. priv->entry = snd_info_create_module_entry(codec_root->module,
  2510. "wcd937x", codec_root);
  2511. if (!priv->entry) {
  2512. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2513. __func__);
  2514. return -ENOMEM;
  2515. }
  2516. priv->entry->mode = S_IFDIR | 0555;
  2517. if (snd_info_register(priv->entry) < 0) {
  2518. snd_info_free_entry(priv->entry);
  2519. return -ENOMEM;
  2520. }
  2521. version_entry = snd_info_create_card_entry(card->snd_card,
  2522. "version",
  2523. priv->entry);
  2524. if (!version_entry) {
  2525. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2526. __func__);
  2527. snd_info_free_entry(priv->entry);
  2528. return -ENOMEM;
  2529. }
  2530. version_entry->private_data = priv;
  2531. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2532. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2533. version_entry->c.ops = &wcd937x_info_ops;
  2534. if (snd_info_register(version_entry) < 0) {
  2535. snd_info_free_entry(version_entry);
  2536. snd_info_free_entry(priv->entry);
  2537. return -ENOMEM;
  2538. }
  2539. priv->version_entry = version_entry;
  2540. variant_entry = snd_info_create_card_entry(card->snd_card,
  2541. "variant",
  2542. priv->entry);
  2543. if (!variant_entry) {
  2544. dev_dbg(component->dev,
  2545. "%s: failed to create wcd937x variant entry\n",
  2546. __func__);
  2547. snd_info_free_entry(version_entry);
  2548. snd_info_free_entry(priv->entry);
  2549. return -ENOMEM;
  2550. }
  2551. variant_entry->private_data = priv;
  2552. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2553. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2554. variant_entry->c.ops = &wcd937x_variant_ops;
  2555. if (snd_info_register(variant_entry) < 0) {
  2556. snd_info_free_entry(variant_entry);
  2557. snd_info_free_entry(version_entry);
  2558. snd_info_free_entry(priv->entry);
  2559. return -ENOMEM;
  2560. }
  2561. priv->variant_entry = variant_entry;
  2562. return 0;
  2563. }
  2564. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2565. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2566. struct wcd937x_pdata *pdata)
  2567. {
  2568. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2569. int rc = 0;
  2570. if (!pdata) {
  2571. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2572. return -ENODEV;
  2573. }
  2574. /* set micbias voltage */
  2575. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2576. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2577. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2578. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2579. rc = -EINVAL;
  2580. goto done;
  2581. }
  2582. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2583. vout_ctl_1);
  2584. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2585. vout_ctl_2);
  2586. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2587. vout_ctl_3);
  2588. done:
  2589. return rc;
  2590. }
  2591. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2592. {
  2593. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2594. struct snd_soc_dapm_context *dapm =
  2595. snd_soc_component_get_dapm(component);
  2596. int variant;
  2597. int ret = -EINVAL;
  2598. dev_info(component->dev, "%s()\n", __func__);
  2599. wcd937x = snd_soc_component_get_drvdata(component);
  2600. if (!wcd937x)
  2601. return -EINVAL;
  2602. wcd937x->component = component;
  2603. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2604. devm_regmap_qti_debugfs_register(&wcd937x->tx_swr_dev->dev, wcd937x->regmap);
  2605. variant = (snd_soc_component_read(
  2606. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2607. wcd937x->variant = variant;
  2608. wcd937x->adc_count = 0;
  2609. wcd937x->fw_data = devm_kzalloc(component->dev,
  2610. sizeof(*(wcd937x->fw_data)),
  2611. GFP_KERNEL);
  2612. if (!wcd937x->fw_data) {
  2613. dev_err(component->dev, "Failed to allocate fw_data\n");
  2614. ret = -ENOMEM;
  2615. goto err;
  2616. }
  2617. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2618. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2619. WCD9XXX_CODEC_HWDEP_NODE, component);
  2620. if (ret < 0) {
  2621. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2622. goto err_hwdep;
  2623. }
  2624. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2625. if (ret) {
  2626. pr_err("%s: mbhc initialization failed\n", __func__);
  2627. goto err_hwdep;
  2628. }
  2629. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2630. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2631. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2632. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2633. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2634. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2635. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2636. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2637. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2638. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2639. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2640. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2641. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2642. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2643. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2644. snd_soc_dapm_sync(dapm);
  2645. wcd_cls_h_init(&wcd937x->clsh_info);
  2646. wcd937x_init_reg(component);
  2647. if (wcd937x->variant == WCD9375_VARIANT) {
  2648. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2649. ARRAY_SIZE(wcd9375_dapm_widgets));
  2650. if (ret < 0) {
  2651. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2652. __func__);
  2653. goto err_hwdep;
  2654. }
  2655. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2656. ARRAY_SIZE(wcd9375_audio_map));
  2657. if (ret < 0) {
  2658. dev_err(component->dev, "%s: Failed to add routes\n",
  2659. __func__);
  2660. goto err_hwdep;
  2661. }
  2662. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2663. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2664. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2665. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2666. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2667. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2668. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2669. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2670. snd_soc_dapm_sync(dapm);
  2671. }
  2672. wcd937x->version = WCD937X_VERSION_1_0;
  2673. /* Register event notifier */
  2674. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2675. if (wcd937x->register_notifier) {
  2676. ret = wcd937x->register_notifier(wcd937x->handle,
  2677. &wcd937x->nblock,
  2678. true);
  2679. if (ret) {
  2680. dev_err(component->dev,
  2681. "%s: Failed to register notifier %d\n",
  2682. __func__, ret);
  2683. return ret;
  2684. }
  2685. }
  2686. return ret;
  2687. err_hwdep:
  2688. wcd937x->fw_data = NULL;
  2689. err:
  2690. return ret;
  2691. }
  2692. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2693. {
  2694. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2695. if (!wcd937x)
  2696. return;
  2697. if (wcd937x->register_notifier)
  2698. wcd937x->register_notifier(wcd937x->handle,
  2699. &wcd937x->nblock,
  2700. false);
  2701. return;
  2702. }
  2703. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2704. .name = WCD937X_DRV_NAME,
  2705. .probe = wcd937x_soc_codec_probe,
  2706. .remove = wcd937x_soc_codec_remove,
  2707. .controls = wcd937x_snd_controls,
  2708. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2709. .dapm_widgets = wcd937x_dapm_widgets,
  2710. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2711. .dapm_routes = wcd937x_audio_map,
  2712. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2713. };
  2714. #ifdef CONFIG_PM_SLEEP
  2715. static int wcd937x_suspend(struct device *dev)
  2716. {
  2717. struct wcd937x_priv *wcd937x = NULL;
  2718. int ret = 0;
  2719. struct wcd937x_pdata *pdata = NULL;
  2720. if (!dev)
  2721. return -ENODEV;
  2722. wcd937x = dev_get_drvdata(dev);
  2723. if (!wcd937x)
  2724. return -EINVAL;
  2725. pdata = dev_get_platdata(wcd937x->dev);
  2726. if (!pdata) {
  2727. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2728. return -EINVAL;
  2729. }
  2730. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2731. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2732. wcd937x->supplies,
  2733. pdata->regulator,
  2734. pdata->num_supplies,
  2735. "cdc-vdd-buck");
  2736. if (ret == -EINVAL) {
  2737. dev_err(dev, "%s: vdd buck is not disabled\n",
  2738. __func__);
  2739. return 0;
  2740. }
  2741. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2742. }
  2743. return 0;
  2744. }
  2745. static int wcd937x_resume(struct device *dev)
  2746. {
  2747. return 0;
  2748. }
  2749. #endif
  2750. static int wcd937x_reset(struct device *dev)
  2751. {
  2752. struct wcd937x_priv *wcd937x = NULL;
  2753. int rc = 0;
  2754. int value = 0;
  2755. if (!dev)
  2756. return -ENODEV;
  2757. wcd937x = dev_get_drvdata(dev);
  2758. if (!wcd937x)
  2759. return -EINVAL;
  2760. if (!wcd937x->rst_np) {
  2761. dev_err(dev, "%s: reset gpio device node not specified\n",
  2762. __func__);
  2763. return -EINVAL;
  2764. }
  2765. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2766. if (value > 0)
  2767. return 0;
  2768. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2769. if (rc) {
  2770. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2771. __func__);
  2772. return rc;
  2773. }
  2774. /* 20ms sleep required after pulling the reset gpio to LOW */
  2775. usleep_range(20, 30);
  2776. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2777. if (rc) {
  2778. dev_err(dev, "%s: wcd active state request fail!\n",
  2779. __func__);
  2780. return rc;
  2781. }
  2782. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2783. usleep_range(20, 30);
  2784. return rc;
  2785. }
  2786. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2787. u32 *val)
  2788. {
  2789. int rc = 0;
  2790. rc = of_property_read_u32(dev->of_node, name, val);
  2791. if (rc)
  2792. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2793. __func__, name, dev->of_node->full_name);
  2794. return rc;
  2795. }
  2796. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2797. struct wcd937x_micbias_setting *mb)
  2798. {
  2799. u32 prop_val = 0;
  2800. int rc = 0;
  2801. /* MB1 */
  2802. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2803. NULL)) {
  2804. rc = wcd937x_read_of_property_u32(dev,
  2805. "qcom,cdc-micbias1-mv",
  2806. &prop_val);
  2807. if (!rc)
  2808. mb->micb1_mv = prop_val;
  2809. } else {
  2810. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2811. __func__);
  2812. }
  2813. /* MB2 */
  2814. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2815. NULL)) {
  2816. rc = wcd937x_read_of_property_u32(dev,
  2817. "qcom,cdc-micbias2-mv",
  2818. &prop_val);
  2819. if (!rc)
  2820. mb->micb2_mv = prop_val;
  2821. } else {
  2822. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2823. __func__);
  2824. }
  2825. /* MB3 */
  2826. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2827. NULL)) {
  2828. rc = wcd937x_read_of_property_u32(dev,
  2829. "qcom,cdc-micbias3-mv",
  2830. &prop_val);
  2831. if (!rc)
  2832. mb->micb3_mv = prop_val;
  2833. } else {
  2834. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2835. __func__);
  2836. }
  2837. }
  2838. static int wcd937x_reset_low(struct device *dev)
  2839. {
  2840. struct wcd937x_priv *wcd937x = NULL;
  2841. int rc = 0;
  2842. if (!dev)
  2843. return -ENODEV;
  2844. wcd937x = dev_get_drvdata(dev);
  2845. if (!wcd937x)
  2846. return -EINVAL;
  2847. if (!wcd937x->rst_np) {
  2848. dev_err(dev, "%s: reset gpio device node not specified\n",
  2849. __func__);
  2850. return -EINVAL;
  2851. }
  2852. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2853. if (rc) {
  2854. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2855. __func__);
  2856. return rc;
  2857. }
  2858. /* 20ms sleep required after pulling the reset gpio to LOW */
  2859. usleep_range(20, 30);
  2860. return rc;
  2861. }
  2862. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2863. {
  2864. struct wcd937x_pdata *pdata = NULL;
  2865. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2866. GFP_KERNEL);
  2867. if (!pdata)
  2868. return NULL;
  2869. pdata->rst_np = of_parse_phandle(dev->of_node,
  2870. "qcom,wcd-rst-gpio-node", 0);
  2871. if (!pdata->rst_np) {
  2872. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2873. __func__, "qcom,wcd-rst-gpio-node",
  2874. dev->of_node->full_name);
  2875. return NULL;
  2876. }
  2877. /* Parse power supplies */
  2878. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2879. &pdata->num_supplies);
  2880. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2881. dev_err(dev, "%s: no power supplies defined for codec\n",
  2882. __func__);
  2883. return NULL;
  2884. }
  2885. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2886. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2887. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2888. return pdata;
  2889. }
  2890. static int wcd937x_wakeup(void *handle, bool enable)
  2891. {
  2892. struct wcd937x_priv *priv;
  2893. if (!handle) {
  2894. pr_err("%s: NULL handle\n", __func__);
  2895. return -EINVAL;
  2896. }
  2897. priv = (struct wcd937x_priv *)handle;
  2898. if (!priv->tx_swr_dev) {
  2899. pr_err("%s: tx swr dev is NULL\n", __func__);
  2900. return -EINVAL;
  2901. }
  2902. if (enable)
  2903. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2904. else
  2905. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2906. }
  2907. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2908. {
  2909. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2910. __func__, irq);
  2911. return IRQ_HANDLED;
  2912. }
  2913. static int wcd937x_bind(struct device *dev)
  2914. {
  2915. int ret = 0, i = 0;
  2916. struct wcd937x_priv *wcd937x = NULL;
  2917. struct wcd937x_pdata *pdata = NULL;
  2918. struct wcd_ctrl_platform_data *plat_data = NULL;
  2919. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2920. if (!wcd937x)
  2921. return -ENOMEM;
  2922. dev_set_drvdata(dev, wcd937x);
  2923. pdata = wcd937x_populate_dt_data(dev);
  2924. if (!pdata) {
  2925. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2926. return -EINVAL;
  2927. }
  2928. wcd937x->dev = dev;
  2929. wcd937x->dev->platform_data = pdata;
  2930. wcd937x->rst_np = pdata->rst_np;
  2931. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2932. pdata->regulator, pdata->num_supplies);
  2933. if (!wcd937x->supplies) {
  2934. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2935. __func__);
  2936. goto err_bind_all;
  2937. }
  2938. plat_data = dev_get_platdata(dev->parent);
  2939. if (!plat_data) {
  2940. dev_err(dev, "%s: platform data from parent is NULL\n",
  2941. __func__);
  2942. ret = -EINVAL;
  2943. goto err_bind_all;
  2944. }
  2945. wcd937x->handle = (void *)plat_data->handle;
  2946. if (!wcd937x->handle) {
  2947. dev_err(dev, "%s: handle is NULL\n", __func__);
  2948. ret = -EINVAL;
  2949. goto err_bind_all;
  2950. }
  2951. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2952. if (!wcd937x->update_wcd_event) {
  2953. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2954. __func__);
  2955. ret = -EINVAL;
  2956. goto err_bind_all;
  2957. }
  2958. wcd937x->register_notifier = plat_data->register_notifier;
  2959. if (!wcd937x->register_notifier) {
  2960. dev_err(dev, "%s: register_notifier api is null!\n",
  2961. __func__);
  2962. ret = -EINVAL;
  2963. goto err_bind_all;
  2964. }
  2965. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2966. pdata->regulator,
  2967. pdata->num_supplies);
  2968. if (ret) {
  2969. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2970. __func__);
  2971. goto err_bind_all;
  2972. }
  2973. wcd937x_reset(dev);
  2974. /*
  2975. * Add 5msec delay to provide sufficient time for
  2976. * soundwire auto enumeration of slave devices as
  2977. * as per HW requirement.
  2978. */
  2979. usleep_range(5000, 5010);
  2980. wcd937x->wakeup = wcd937x_wakeup;
  2981. ret = component_bind_all(dev, wcd937x);
  2982. if (ret) {
  2983. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2984. __func__, ret);
  2985. goto err_bind_all;
  2986. }
  2987. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2988. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2989. if (ret) {
  2990. dev_err(dev, "Failed to read port mapping\n");
  2991. goto err;
  2992. }
  2993. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  2994. CODEC_TX);
  2995. if (ret) {
  2996. dev_err(dev, "Failed to read port params\n");
  2997. goto err;
  2998. }
  2999. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3000. if (!wcd937x->rx_swr_dev) {
  3001. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3002. __func__);
  3003. ret = -ENODEV;
  3004. goto err;
  3005. }
  3006. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3007. if (!wcd937x->tx_swr_dev) {
  3008. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3009. __func__);
  3010. ret = -ENODEV;
  3011. goto err;
  3012. }
  3013. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  3014. wcd937x->swr_tx_port_params);
  3015. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  3016. &wcd937x_regmap_config);
  3017. if (!wcd937x->regmap) {
  3018. dev_err(dev, "%s: Regmap init failed\n",
  3019. __func__);
  3020. goto err;
  3021. }
  3022. /* Set all interupts as edge triggered */
  3023. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  3024. regmap_write(wcd937x->regmap,
  3025. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3026. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  3027. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  3028. wcd937x->irq_info.codec_name = "WCD937X";
  3029. wcd937x->irq_info.regmap = wcd937x->regmap;
  3030. wcd937x->irq_info.dev = dev;
  3031. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  3032. if (ret) {
  3033. dev_err(dev, "%s: IRQ init failed: %d\n",
  3034. __func__, ret);
  3035. goto err;
  3036. }
  3037. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  3038. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  3039. if (ret < 0) {
  3040. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3041. goto err_irq;
  3042. }
  3043. /* default L1 power setting */
  3044. wcd937x->tx_ch_pwr[0] = 1;
  3045. wcd937x->tx_ch_pwr[1] = 1;
  3046. mutex_init(&wcd937x->micb_lock);
  3047. mutex_init(&wcd937x->ana_tx_clk_lock);
  3048. /* Request for watchdog interrupt */
  3049. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  3050. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  3051. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  3052. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  3053. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  3054. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  3055. /* Disable watchdog interrupt for HPH and AUX */
  3056. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  3057. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  3058. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  3059. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  3060. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  3061. if (ret) {
  3062. dev_err(dev, "%s: Codec registration failed\n",
  3063. __func__);
  3064. goto err_irq;
  3065. }
  3066. return ret;
  3067. err_irq:
  3068. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  3069. err:
  3070. component_unbind_all(dev, wcd937x);
  3071. err_bind_all:
  3072. dev_set_drvdata(dev, NULL);
  3073. kfree(pdata);
  3074. kfree(wcd937x);
  3075. return ret;
  3076. }
  3077. static void wcd937x_unbind(struct device *dev)
  3078. {
  3079. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  3080. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  3081. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  3082. snd_soc_unregister_component(dev);
  3083. component_unbind_all(dev, wcd937x);
  3084. mutex_destroy(&wcd937x->micb_lock);
  3085. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  3086. dev_set_drvdata(dev, NULL);
  3087. kfree(pdata);
  3088. kfree(wcd937x);
  3089. }
  3090. static const struct of_device_id wcd937x_dt_match[] = {
  3091. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  3092. {}
  3093. };
  3094. static const struct component_master_ops wcd937x_comp_ops = {
  3095. .bind = wcd937x_bind,
  3096. .unbind = wcd937x_unbind,
  3097. };
  3098. static int wcd937x_compare_of(struct device *dev, void *data)
  3099. {
  3100. return dev->of_node == data;
  3101. }
  3102. static void wcd937x_release_of(struct device *dev, void *data)
  3103. {
  3104. of_node_put(data);
  3105. }
  3106. static int wcd937x_add_slave_components(struct device *dev,
  3107. struct component_match **matchptr)
  3108. {
  3109. struct device_node *np, *rx_node, *tx_node;
  3110. np = dev->of_node;
  3111. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3112. if (!rx_node) {
  3113. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3114. return -ENODEV;
  3115. }
  3116. of_node_get(rx_node);
  3117. component_match_add_release(dev, matchptr,
  3118. wcd937x_release_of,
  3119. wcd937x_compare_of,
  3120. rx_node);
  3121. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3122. if (!tx_node) {
  3123. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3124. return -ENODEV;
  3125. }
  3126. of_node_get(tx_node);
  3127. component_match_add_release(dev, matchptr,
  3128. wcd937x_release_of,
  3129. wcd937x_compare_of,
  3130. tx_node);
  3131. return 0;
  3132. }
  3133. static int wcd937x_probe(struct platform_device *pdev)
  3134. {
  3135. struct component_match *match = NULL;
  3136. int ret;
  3137. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3138. if (ret)
  3139. return ret;
  3140. return component_master_add_with_match(&pdev->dev,
  3141. &wcd937x_comp_ops, match);
  3142. }
  3143. static int wcd937x_remove(struct platform_device *pdev)
  3144. {
  3145. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3146. dev_set_drvdata(&pdev->dev, NULL);
  3147. return 0;
  3148. }
  3149. #ifdef CONFIG_PM_SLEEP
  3150. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3151. SET_SYSTEM_SLEEP_PM_OPS(
  3152. wcd937x_suspend,
  3153. wcd937x_resume
  3154. )
  3155. };
  3156. #endif
  3157. static struct platform_driver wcd937x_codec_driver = {
  3158. .probe = wcd937x_probe,
  3159. .remove = wcd937x_remove,
  3160. .driver = {
  3161. .name = "wcd937x_codec",
  3162. .owner = THIS_MODULE,
  3163. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3164. #ifdef CONFIG_PM_SLEEP
  3165. .pm = &wcd937x_dev_pm_ops,
  3166. #endif
  3167. .suppress_bind_attrs = true,
  3168. },
  3169. };
  3170. module_platform_driver(wcd937x_codec_driver);
  3171. MODULE_DESCRIPTION("WCD937X Codec driver");
  3172. MODULE_LICENSE("GPL v2");