6dead69b1f
add lpass cdc va register VAD_MUX. Change-Id: I8dcad5f7edcefdac358be7a6d1b0c7fa3ca5c7ba Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
1363 خطوط
83 KiB
C
1363 خطوط
83 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _LPASS_CDC_REGISTERS_H
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#define _LPASS_CDC_REGISTERS_H
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#define TX_START_OFFSET 0x0000
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#define LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (TX_START_OFFSET + 0x0000)
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#define LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (TX_START_OFFSET + 0x0004)
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#define LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL (TX_START_OFFSET + 0x0008)
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#define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080)
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#define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084)
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#define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088)
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#define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094)
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#define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098)
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#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4)
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#define LPASS_CDC_TX_TOP_CSR_I2S_CLK (TX_START_OFFSET + 0x00A8)
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#define LPASS_CDC_TX_TOP_CSR_I2S_RESET (TX_START_OFFSET + 0x00AC)
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#define LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL (TX_START_OFFSET + 0x00C0)
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#define LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL (TX_START_OFFSET + 0x00C4)
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#define LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL (TX_START_OFFSET + 0x00C8)
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#define LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL (TX_START_OFFSET + 0x00CC)
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#define LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL (TX_START_OFFSET + 0x00D0)
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#define LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL (TX_START_OFFSET + 0x00D4)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 (TX_START_OFFSET + 0x0100)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 (TX_START_OFFSET + 0x0104)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0 (TX_START_OFFSET + 0x0108)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1 (TX_START_OFFSET + 0x010C)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0 (TX_START_OFFSET + 0x0110)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1 (TX_START_OFFSET + 0x0114)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0 (TX_START_OFFSET + 0x0118)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1 (TX_START_OFFSET + 0x011C)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0 (TX_START_OFFSET + 0x0120)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG1 (TX_START_OFFSET + 0x0124)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0 (TX_START_OFFSET + 0x0128)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG1 (TX_START_OFFSET + 0x012C)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0 (TX_START_OFFSET + 0x0130)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1 (TX_START_OFFSET + 0x0134)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0 (TX_START_OFFSET + 0x0138)
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#define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1 (TX_START_OFFSET + 0x013C)
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#define LPASS_CDC_TX_ANC0_CLK_RESET_CTL (TX_START_OFFSET + 0x0200)
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#define LPASS_CDC_TX_ANC0_MODE_1_CTL (TX_START_OFFSET + 0x0204)
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#define LPASS_CDC_TX_ANC0_MODE_2_CTL (TX_START_OFFSET + 0x0208)
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#define LPASS_CDC_TX_ANC0_FF_SHIFT (TX_START_OFFSET + 0x020C)
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#define LPASS_CDC_TX_ANC0_FB_SHIFT (TX_START_OFFSET + 0x0210)
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#define LPASS_CDC_TX_ANC0_LPF_FF_A_CTL (TX_START_OFFSET + 0x0214)
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#define LPASS_CDC_TX_ANC0_LPF_FF_B_CTL (TX_START_OFFSET + 0x0218)
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#define LPASS_CDC_TX_ANC0_LPF_FB_CTL (TX_START_OFFSET + 0x021C)
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#define LPASS_CDC_TX_ANC0_SMLPF_CTL (TX_START_OFFSET + 0x0220)
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#define LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL (TX_START_OFFSET + 0x0224)
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#define LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL (TX_START_OFFSET + 0x0228)
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#define LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL (TX_START_OFFSET + 0x022C)
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#define LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL (TX_START_OFFSET + 0x0230)
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#define LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL (TX_START_OFFSET + 0x0234)
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#define LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL (TX_START_OFFSET + 0x0238)
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#define LPASS_CDC_TX_ANC0_FB_GAIN_CTL (TX_START_OFFSET + 0x023C)
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#define LPASS_CDC_TX0_TX_PATH_CTL (TX_START_OFFSET + 0x0400)
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#define LPASS_CDC_TX0_TX_PATH_CFG0 (TX_START_OFFSET + 0x0404)
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#define LPASS_CDC_TX0_TX_PATH_CFG1 (TX_START_OFFSET + 0x0408)
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#define LPASS_CDC_TX0_TX_VOL_CTL (TX_START_OFFSET + 0x040C)
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#define LPASS_CDC_TX0_TX_PATH_SEC0 (TX_START_OFFSET + 0x0410)
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#define LPASS_CDC_TX0_TX_PATH_SEC1 (TX_START_OFFSET + 0x0414)
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#define LPASS_CDC_TX0_TX_PATH_SEC2 (TX_START_OFFSET + 0x0418)
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#define LPASS_CDC_TX0_TX_PATH_SEC3 (TX_START_OFFSET + 0x041C)
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#define LPASS_CDC_TX0_TX_PATH_SEC4 (TX_START_OFFSET + 0x0420)
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#define LPASS_CDC_TX0_TX_PATH_SEC5 (TX_START_OFFSET + 0x0424)
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#define LPASS_CDC_TX0_TX_PATH_SEC6 (TX_START_OFFSET + 0x0428)
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#define LPASS_CDC_TX0_TX_PATH_SEC7 (TX_START_OFFSET + 0x042C)
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#define LPASS_CDC_TX1_TX_PATH_CTL (TX_START_OFFSET + 0x0480)
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#define LPASS_CDC_TX1_TX_PATH_CFG0 (TX_START_OFFSET + 0x0484)
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#define LPASS_CDC_TX1_TX_PATH_CFG1 (TX_START_OFFSET + 0x0488)
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#define LPASS_CDC_TX1_TX_VOL_CTL (TX_START_OFFSET + 0x048C)
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#define LPASS_CDC_TX1_TX_PATH_SEC0 (TX_START_OFFSET + 0x0490)
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#define LPASS_CDC_TX1_TX_PATH_SEC1 (TX_START_OFFSET + 0x0494)
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#define LPASS_CDC_TX1_TX_PATH_SEC2 (TX_START_OFFSET + 0x0498)
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#define LPASS_CDC_TX1_TX_PATH_SEC3 (TX_START_OFFSET + 0x049C)
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#define LPASS_CDC_TX1_TX_PATH_SEC4 (TX_START_OFFSET + 0x04A0)
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#define LPASS_CDC_TX1_TX_PATH_SEC5 (TX_START_OFFSET + 0x04A4)
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#define LPASS_CDC_TX1_TX_PATH_SEC6 (TX_START_OFFSET + 0x04A8)
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#define LPASS_CDC_TX2_TX_PATH_CTL (TX_START_OFFSET + 0x0500)
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#define LPASS_CDC_TX2_TX_PATH_CFG0 (TX_START_OFFSET + 0x0504)
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#define LPASS_CDC_TX2_TX_PATH_CFG1 (TX_START_OFFSET + 0x0508)
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#define LPASS_CDC_TX2_TX_VOL_CTL (TX_START_OFFSET + 0x050C)
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#define LPASS_CDC_TX2_TX_PATH_SEC0 (TX_START_OFFSET + 0x0510)
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#define LPASS_CDC_TX2_TX_PATH_SEC1 (TX_START_OFFSET + 0x0514)
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#define LPASS_CDC_TX2_TX_PATH_SEC2 (TX_START_OFFSET + 0x0518)
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#define LPASS_CDC_TX2_TX_PATH_SEC3 (TX_START_OFFSET + 0x051C)
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#define LPASS_CDC_TX2_TX_PATH_SEC4 (TX_START_OFFSET + 0x0520)
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#define LPASS_CDC_TX2_TX_PATH_SEC5 (TX_START_OFFSET + 0x0524)
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#define LPASS_CDC_TX2_TX_PATH_SEC6 (TX_START_OFFSET + 0x0528)
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#define LPASS_CDC_TX3_TX_PATH_CTL (TX_START_OFFSET + 0x0580)
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#define LPASS_CDC_TX3_TX_PATH_CFG0 (TX_START_OFFSET + 0x0584)
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#define LPASS_CDC_TX3_TX_PATH_CFG1 (TX_START_OFFSET + 0x0588)
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#define LPASS_CDC_TX3_TX_VOL_CTL (TX_START_OFFSET + 0x058C)
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#define LPASS_CDC_TX3_TX_PATH_SEC0 (TX_START_OFFSET + 0x0590)
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#define LPASS_CDC_TX3_TX_PATH_SEC1 (TX_START_OFFSET + 0x0594)
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#define LPASS_CDC_TX3_TX_PATH_SEC2 (TX_START_OFFSET + 0x0598)
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#define LPASS_CDC_TX3_TX_PATH_SEC3 (TX_START_OFFSET + 0x059C)
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#define LPASS_CDC_TX3_TX_PATH_SEC4 (TX_START_OFFSET + 0x05A0)
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#define LPASS_CDC_TX3_TX_PATH_SEC5 (TX_START_OFFSET + 0x05A4)
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#define LPASS_CDC_TX3_TX_PATH_SEC6 (TX_START_OFFSET + 0x05A8)
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#define LPASS_CDC_TX4_TX_PATH_CTL (TX_START_OFFSET + 0x0600)
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#define LPASS_CDC_TX4_TX_PATH_CFG0 (TX_START_OFFSET + 0x0604)
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#define LPASS_CDC_TX4_TX_PATH_CFG1 (TX_START_OFFSET + 0x0608)
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#define LPASS_CDC_TX4_TX_VOL_CTL (TX_START_OFFSET + 0x060C)
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#define LPASS_CDC_TX4_TX_PATH_SEC0 (TX_START_OFFSET + 0x0610)
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#define LPASS_CDC_TX4_TX_PATH_SEC1 (TX_START_OFFSET + 0x0614)
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#define LPASS_CDC_TX4_TX_PATH_SEC2 (TX_START_OFFSET + 0x0618)
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#define LPASS_CDC_TX4_TX_PATH_SEC3 (TX_START_OFFSET + 0x061C)
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#define LPASS_CDC_TX4_TX_PATH_SEC4 (TX_START_OFFSET + 0x0620)
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#define LPASS_CDC_TX4_TX_PATH_SEC5 (TX_START_OFFSET + 0x0624)
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#define LPASS_CDC_TX4_TX_PATH_SEC6 (TX_START_OFFSET + 0x0628)
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#define LPASS_CDC_TX5_TX_PATH_CTL (TX_START_OFFSET + 0x0680)
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#define LPASS_CDC_TX5_TX_PATH_CFG0 (TX_START_OFFSET + 0x0684)
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#define LPASS_CDC_TX5_TX_PATH_CFG1 (TX_START_OFFSET + 0x0688)
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#define LPASS_CDC_TX5_TX_VOL_CTL (TX_START_OFFSET + 0x068C)
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#define LPASS_CDC_TX5_TX_PATH_SEC0 (TX_START_OFFSET + 0x0690)
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#define LPASS_CDC_TX5_TX_PATH_SEC1 (TX_START_OFFSET + 0x0694)
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#define LPASS_CDC_TX5_TX_PATH_SEC2 (TX_START_OFFSET + 0x0698)
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#define LPASS_CDC_TX5_TX_PATH_SEC3 (TX_START_OFFSET + 0x069C)
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#define LPASS_CDC_TX5_TX_PATH_SEC4 (TX_START_OFFSET + 0x06A0)
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#define LPASS_CDC_TX5_TX_PATH_SEC5 (TX_START_OFFSET + 0x06A4)
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#define LPASS_CDC_TX5_TX_PATH_SEC6 (TX_START_OFFSET + 0x06A8)
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#define LPASS_CDC_TX6_TX_PATH_CTL (TX_START_OFFSET + 0x0700)
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#define LPASS_CDC_TX6_TX_PATH_CFG0 (TX_START_OFFSET + 0x0704)
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#define LPASS_CDC_TX6_TX_PATH_CFG1 (TX_START_OFFSET + 0x0708)
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#define LPASS_CDC_TX6_TX_VOL_CTL (TX_START_OFFSET + 0x070C)
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#define LPASS_CDC_TX6_TX_PATH_SEC0 (TX_START_OFFSET + 0x0710)
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#define LPASS_CDC_TX6_TX_PATH_SEC1 (TX_START_OFFSET + 0x0714)
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#define LPASS_CDC_TX6_TX_PATH_SEC2 (TX_START_OFFSET + 0x0718)
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#define LPASS_CDC_TX6_TX_PATH_SEC3 (TX_START_OFFSET + 0x071C)
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#define LPASS_CDC_TX6_TX_PATH_SEC4 (TX_START_OFFSET + 0x0720)
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#define LPASS_CDC_TX6_TX_PATH_SEC5 (TX_START_OFFSET + 0x0724)
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#define LPASS_CDC_TX6_TX_PATH_SEC6 (TX_START_OFFSET + 0x0728)
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#define LPASS_CDC_TX7_TX_PATH_CTL (TX_START_OFFSET + 0x0780)
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#define LPASS_CDC_TX7_TX_PATH_CFG0 (TX_START_OFFSET + 0x0784)
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#define LPASS_CDC_TX7_TX_PATH_CFG1 (TX_START_OFFSET + 0x0788)
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#define LPASS_CDC_TX7_TX_VOL_CTL (TX_START_OFFSET + 0x078C)
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#define LPASS_CDC_TX7_TX_PATH_SEC0 (TX_START_OFFSET + 0x0790)
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#define LPASS_CDC_TX7_TX_PATH_SEC1 (TX_START_OFFSET + 0x0794)
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#define LPASS_CDC_TX7_TX_PATH_SEC2 (TX_START_OFFSET + 0x0798)
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#define LPASS_CDC_TX7_TX_PATH_SEC3 (TX_START_OFFSET + 0x079C)
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#define LPASS_CDC_TX7_TX_PATH_SEC4 (TX_START_OFFSET + 0x07A0)
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#define LPASS_CDC_TX7_TX_PATH_SEC5 (TX_START_OFFSET + 0x07A4)
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#define LPASS_CDC_TX7_TX_PATH_SEC6 (TX_START_OFFSET + 0x07A8)
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#define TX_MAX_OFFSET (TX_START_OFFSET + 0x07A8)
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#define LPASS_CDC_TX_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 */
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#define RX_START_OFFSET 0x1000
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#define LPASS_CDC_RX_TOP_TOP_CFG0 (RX_START_OFFSET + 0x0000)
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#define LPASS_CDC_RX_TOP_TOP_CFG1 (RX_START_OFFSET + 0x0004)
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#define LPASS_CDC_RX_TOP_SWR_CTRL (RX_START_OFFSET + 0x0008)
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#define LPASS_CDC_RX_TOP_DEBUG (RX_START_OFFSET + 0x000C)
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#define LPASS_CDC_RX_TOP_DEBUG_BUS (RX_START_OFFSET + 0x0010)
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#define LPASS_CDC_RX_TOP_DEBUG_EN0 (RX_START_OFFSET + 0x0014)
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#define LPASS_CDC_RX_TOP_DEBUG_EN1 (RX_START_OFFSET + 0x0018)
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#define LPASS_CDC_RX_TOP_DEBUG_EN2 (RX_START_OFFSET + 0x001C)
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#define LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB (RX_START_OFFSET + 0x0020)
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#define LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB (RX_START_OFFSET + 0x0024)
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#define LPASS_CDC_RX_TOP_HPHL_COMP_LUT (RX_START_OFFSET + 0x0028)
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#define LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB (RX_START_OFFSET + 0x002C)
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#define LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB (RX_START_OFFSET + 0x0030)
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#define LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB (RX_START_OFFSET + 0x0034)
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#define LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB (RX_START_OFFSET + 0x0038)
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#define LPASS_CDC_RX_TOP_HPHR_COMP_LUT (RX_START_OFFSET + 0x003C)
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#define LPASS_CDC_RX_TOP_HPHR_COMP_RD_LSB (RX_START_OFFSET + 0x0040)
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#define LPASS_CDC_RX_TOP_HPHR_COMP_RD_MSB (RX_START_OFFSET + 0x0044)
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#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0 (RX_START_OFFSET + 0x0070)
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#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1 (RX_START_OFFSET + 0x0074)
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#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2 (RX_START_OFFSET + 0x0078)
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#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3 (RX_START_OFFSET + 0x007C)
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#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0 (RX_START_OFFSET + 0x0080)
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#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1 (RX_START_OFFSET + 0x0084)
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#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2 (RX_START_OFFSET + 0x0088)
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#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3 (RX_START_OFFSET + 0x008C)
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#define LPASS_CDC_RX_TOP_RX_I2S_CTL (RX_START_OFFSET + 0x0090)
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#define LPASS_CDC_RX_TOP_TX_I2S2_CTL (RX_START_OFFSET + 0x0094)
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#define LPASS_CDC_RX_TOP_I2S_CLK (RX_START_OFFSET + 0x0098)
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#define LPASS_CDC_RX_TOP_I2S_RESET (RX_START_OFFSET + 0x009C)
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#define LPASS_CDC_RX_TOP_I2S_MUX (RX_START_OFFSET + 0x00A0)
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#define LPASS_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (RX_START_OFFSET + 0x0100)
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#define LPASS_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL \
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(RX_START_OFFSET + 0x0104)
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#define LPASS_CDC_RX_CLK_RST_CTRL_SWR_CONTROL (RX_START_OFFSET + 0x0108)
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#define LPASS_CDC_RX_CLK_RST_CTRL_DSD_CONTROL (RX_START_OFFSET + 0x010C)
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#define LPASS_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL \
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(RX_START_OFFSET + 0x0110)
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#define LPASS_CDC_RX_SOFTCLIP_CRC (RX_START_OFFSET + 0x0140)
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#define LPASS_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (RX_START_OFFSET + 0x0144)
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#define LPASS_CDC_RX_INP_MUX_RX_INT0_CFG0 (RX_START_OFFSET + 0x0180)
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#define LPASS_CDC_RX_INP_MUX_RX_INT0_CFG1 (RX_START_OFFSET + 0x0184)
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#define LPASS_CDC_RX_INP_MUX_RX_INT1_CFG0 (RX_START_OFFSET + 0x0188)
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#define LPASS_CDC_RX_INP_MUX_RX_INT1_CFG1 (RX_START_OFFSET + 0x018C)
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#define LPASS_CDC_RX_INP_MUX_RX_INT2_CFG0 (RX_START_OFFSET + 0x0190)
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#define LPASS_CDC_RX_INP_MUX_RX_INT2_CFG1 (RX_START_OFFSET + 0x0194)
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#define LPASS_CDC_RX_INP_MUX_RX_MIX_CFG4 (RX_START_OFFSET + 0x0198)
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#define LPASS_CDC_RX_INP_MUX_RX_MIX_CFG5 (RX_START_OFFSET + 0x019C)
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#define LPASS_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (RX_START_OFFSET + 0x01A0)
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#define LPASS_CDC_RX_CLSH_CRC (RX_START_OFFSET + 0x0200)
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#define LPASS_CDC_RX_CLSH_DLY_CTRL (RX_START_OFFSET + 0x0204)
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#define LPASS_CDC_RX_CLSH_DECAY_CTRL (RX_START_OFFSET + 0x0208)
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#define LPASS_CDC_RX_CLSH_HPH_V_PA (RX_START_OFFSET + 0x020C)
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#define LPASS_CDC_RX_CLSH_EAR_V_PA (RX_START_OFFSET + 0x0210)
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#define LPASS_CDC_RX_CLSH_HPH_V_HD (RX_START_OFFSET + 0x0214)
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#define LPASS_CDC_RX_CLSH_EAR_V_HD (RX_START_OFFSET + 0x0218)
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#define LPASS_CDC_RX_CLSH_K1_MSB (RX_START_OFFSET + 0x021C)
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#define LPASS_CDC_RX_CLSH_K1_LSB (RX_START_OFFSET + 0x0220)
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#define LPASS_CDC_RX_CLSH_K2_MSB (RX_START_OFFSET + 0x0224)
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#define LPASS_CDC_RX_CLSH_K2_LSB (RX_START_OFFSET + 0x0228)
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#define LPASS_CDC_RX_CLSH_IDLE_CTRL (RX_START_OFFSET + 0x022C)
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#define LPASS_CDC_RX_CLSH_IDLE_HPH (RX_START_OFFSET + 0x0230)
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#define LPASS_CDC_RX_CLSH_IDLE_EAR (RX_START_OFFSET + 0x0234)
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#define LPASS_CDC_RX_CLSH_TEST0 (RX_START_OFFSET + 0x0238)
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#define LPASS_CDC_RX_CLSH_TEST1 (RX_START_OFFSET + 0x023C)
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#define LPASS_CDC_RX_CLSH_OVR_VREF (RX_START_OFFSET + 0x0240)
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#define LPASS_CDC_RX_CLSH_CLSG_CTL (RX_START_OFFSET + 0x0244)
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#define LPASS_CDC_RX_CLSH_CLSG_CFG1 (RX_START_OFFSET + 0x0248)
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#define LPASS_CDC_RX_CLSH_CLSG_CFG2 (RX_START_OFFSET + 0x024C)
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#define LPASS_CDC_RX_BCL_VBAT_PATH_CTL (RX_START_OFFSET + 0x0280)
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#define LPASS_CDC_RX_BCL_VBAT_CFG (RX_START_OFFSET + 0x0284)
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#define LPASS_CDC_RX_BCL_VBAT_ADC_CAL1 (RX_START_OFFSET + 0x0288)
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#define LPASS_CDC_RX_BCL_VBAT_ADC_CAL2 (RX_START_OFFSET + 0x028C)
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#define LPASS_CDC_RX_BCL_VBAT_ADC_CAL3 (RX_START_OFFSET + 0x0290)
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#define LPASS_CDC_RX_BCL_VBAT_PK_EST1 (RX_START_OFFSET + 0x0294)
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#define LPASS_CDC_RX_BCL_VBAT_PK_EST2 (RX_START_OFFSET + 0x0298)
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#define LPASS_CDC_RX_BCL_VBAT_PK_EST3 (RX_START_OFFSET + 0x029C)
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#define LPASS_CDC_RX_BCL_VBAT_RF_PROC1 (RX_START_OFFSET + 0x02A0)
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#define LPASS_CDC_RX_BCL_VBAT_RF_PROC2 (RX_START_OFFSET + 0x02A4)
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#define LPASS_CDC_RX_BCL_VBAT_TAC1 (RX_START_OFFSET + 0x02A8)
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#define LPASS_CDC_RX_BCL_VBAT_TAC2 (RX_START_OFFSET + 0x02AC)
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#define LPASS_CDC_RX_BCL_VBAT_TAC3 (RX_START_OFFSET + 0x02B0)
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#define LPASS_CDC_RX_BCL_VBAT_TAC4 (RX_START_OFFSET + 0x02B4)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD1 (RX_START_OFFSET + 0x02B8)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD2 (RX_START_OFFSET + 0x02BC)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD3 (RX_START_OFFSET + 0x02C0)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD4 (RX_START_OFFSET + 0x02C4)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD5 (RX_START_OFFSET + 0x02C8)
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#define LPASS_CDC_RX_BCL_VBAT_DEBUG1 (RX_START_OFFSET + 0x02CC)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD_MON (RX_START_OFFSET + 0x02D0)
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#define LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL (RX_START_OFFSET + 0x02D4)
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#define LPASS_CDC_RX_BCL_VBAT_BAN (RX_START_OFFSET + 0x02D8)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (RX_START_OFFSET + 0x02DC)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (RX_START_OFFSET + 0x02E0)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (RX_START_OFFSET + 0x02E4)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (RX_START_OFFSET + 0x02E8)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (RX_START_OFFSET + 0x02EC)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (RX_START_OFFSET + 0x02F0)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (RX_START_OFFSET + 0x02F4)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (RX_START_OFFSET + 0x02F8)
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#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (RX_START_OFFSET + 0x02FC)
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#define LPASS_CDC_RX_BCL_VBAT_ATTN1 (RX_START_OFFSET + 0x0300)
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#define LPASS_CDC_RX_BCL_VBAT_ATTN2 (RX_START_OFFSET + 0x0304)
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#define LPASS_CDC_RX_BCL_VBAT_ATTN3 (RX_START_OFFSET + 0x0308)
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#define LPASS_CDC_RX_INTR_CTRL_CFG (RX_START_OFFSET + 0x0340)
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#define LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT (RX_START_OFFSET + 0x0344)
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#define LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0 (RX_START_OFFSET + 0x0360)
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#define LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0 (RX_START_OFFSET + 0x0368)
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#define LPASS_CDC_RX_INTR_CTRL_PIN1_CLEAR0 (RX_START_OFFSET + 0x0370)
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#define LPASS_CDC_RX_INTR_CTRL_PIN2_MASK0 (RX_START_OFFSET + 0x0380)
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#define LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0 (RX_START_OFFSET + 0x0388)
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#define LPASS_CDC_RX_INTR_CTRL_PIN2_CLEAR0 (RX_START_OFFSET + 0x0390)
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#define LPASS_CDC_RX_INTR_CTRL_LEVEL0 (RX_START_OFFSET + 0x03C0)
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#define LPASS_CDC_RX_INTR_CTRL_BYPASS0 (RX_START_OFFSET + 0x03C8)
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#define LPASS_CDC_RX_INTR_CTRL_SET0 (RX_START_OFFSET + 0x03D0)
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#define LPASS_CDC_RX_RX0_RX_PATH_CTL (RX_START_OFFSET + 0x0400)
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#define LPASS_CDC_RX_RX0_RX_PATH_CFG0 (RX_START_OFFSET + 0x0404)
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#define LPASS_CDC_RX_RX0_RX_PATH_CFG1 (RX_START_OFFSET + 0x0408)
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#define LPASS_CDC_RX_RX0_RX_PATH_CFG2 (RX_START_OFFSET + 0x040C)
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#define LPASS_CDC_RX_RX0_RX_PATH_CFG3 (RX_START_OFFSET + 0x0410)
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#define LPASS_CDC_RX_RX0_RX_VOL_CTL (RX_START_OFFSET + 0x0414)
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#define LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0418)
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#define LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x041C)
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#define LPASS_CDC_RX_RX0_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0420)
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#define LPASS_CDC_RX_RX0_RX_PATH_SEC1 (RX_START_OFFSET + 0x0424)
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#define LPASS_CDC_RX_RX0_RX_PATH_SEC2 (RX_START_OFFSET + 0x0428)
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#define LPASS_CDC_RX_RX0_RX_PATH_SEC3 (RX_START_OFFSET + 0x042C)
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#define LPASS_CDC_RX_RX0_RX_PATH_SEC4 (RX_START_OFFSET + 0x0430)
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#define LPASS_CDC_RX_RX0_RX_PATH_SEC7 (RX_START_OFFSET + 0x0434)
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#define LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0438)
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#define LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x043C)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x0440)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x0444)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x0448)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x044C)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454)
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#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458)
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#define LPASS_CDC_RX_RX0_RX_FIR_CTL (RX_START_OFFSET + 0x045C)
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#define LPASS_CDC_RX_RX0_RX_FIR_CFG (RX_START_OFFSET + 0x0460)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0464)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0 (RX_START_OFFSET + 0x0468)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1 (RX_START_OFFSET + 0x046C)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2 (RX_START_OFFSET + 0x0470)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3 (RX_START_OFFSET + 0x0474)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4 (RX_START_OFFSET + 0x0478)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5 (RX_START_OFFSET + 0x047C)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6 (RX_START_OFFSET + 0x0480)
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#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7 (RX_START_OFFSET + 0x0484)
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#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x04C0)
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#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x04C4)
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#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x04C8)
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#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x04CC)
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#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x04D0)
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#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x04D4)
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#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x04D8)
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#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x04DC)
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#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04E0)
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#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04E4)
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#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04E8)
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#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04EC)
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#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04F0)
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#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04F4)
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#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04F8)
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#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04FC)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x0500)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x0504)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x0508)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x050C)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0510)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0514)
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#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0518)
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#define LPASS_CDC_RX_RX1_RX_FIR_CTL (RX_START_OFFSET + 0x051C)
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#define LPASS_CDC_RX_RX1_RX_FIR_CFG (RX_START_OFFSET + 0x0520)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0524)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0 (RX_START_OFFSET + 0x0528)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1 (RX_START_OFFSET + 0x052C)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2 (RX_START_OFFSET + 0x0530)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3 (RX_START_OFFSET + 0x0534)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4 (RX_START_OFFSET + 0x0538)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5 (RX_START_OFFSET + 0x053C)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6 (RX_START_OFFSET + 0x0540)
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#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7 (RX_START_OFFSET + 0x0544)
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#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0580)
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#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0584)
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#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0588)
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#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x058C)
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#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0590)
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#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0594)
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#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0598)
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#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x059C)
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#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x05A0)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x05A4)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x05A8)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x05AC)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x05B0)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x05B4)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x05B8)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x05BC)
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#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x05C0)
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#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x05C4)
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#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x05C8)
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#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x05CC)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1 (RX_START_OFFSET + 0x0600)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2 (RX_START_OFFSET + 0x0604)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3 (RX_START_OFFSET + 0x0608)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1 (RX_START_OFFSET + 0x060C)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2 (RX_START_OFFSET + 0x0610)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3 (RX_START_OFFSET + 0x0614)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4 (RX_START_OFFSET + 0x0618)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5 (RX_START_OFFSET + 0x061C)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6 (RX_START_OFFSET + 0x0620)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7 (RX_START_OFFSET + 0x0624)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8 (RX_START_OFFSET + 0x0628)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1 (RX_START_OFFSET + 0x062C)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2 (RX_START_OFFSET + 0x0630)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3 (RX_START_OFFSET + 0x0634)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4 (RX_START_OFFSET + 0x0638)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1 (RX_START_OFFSET + 0x063C)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2 (RX_START_OFFSET + 0x0640)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3 (RX_START_OFFSET + 0x0644)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4 (RX_START_OFFSET + 0x0648)
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#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5 (RX_START_OFFSET + 0x064C)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL (RX_START_OFFSET + 0x0680)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG (RX_START_OFFSET + 0x0684)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1 (RX_START_OFFSET + 0x0688)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2 (RX_START_OFFSET + 0x068C)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3 (RX_START_OFFSET + 0x0690)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1 (RX_START_OFFSET + 0x0694)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2 (RX_START_OFFSET + 0x0698)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3 (RX_START_OFFSET + 0x069C)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1 (RX_START_OFFSET + 0x06A0)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2 (RX_START_OFFSET + 0x06A4)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1 (RX_START_OFFSET + 0x06A8)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2 (RX_START_OFFSET + 0x06AC)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3 (RX_START_OFFSET + 0x06B0)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4 (RX_START_OFFSET + 0x06B4)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1 (RX_START_OFFSET + 0x06B8)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2 (RX_START_OFFSET + 0x06BC)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3 (RX_START_OFFSET + 0x06C0)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4 (RX_START_OFFSET + 0x06C4)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5 (RX_START_OFFSET + 0x06C8)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1 (RX_START_OFFSET + 0x06CC)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON \
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(RX_START_OFFSET + 0x06D0)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL \
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(RX_START_OFFSET + 0x06D4)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN (RX_START_OFFSET + 0x06D8)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
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(RX_START_OFFSET + 0x06DC)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
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(RX_START_OFFSET + 0x06E0)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
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(RX_START_OFFSET + 0x06E4)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
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(RX_START_OFFSET + 0x06E8)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
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(RX_START_OFFSET + 0x06EC)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
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(RX_START_OFFSET + 0x06F0)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
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(RX_START_OFFSET + 0x06F4)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
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(RX_START_OFFSET + 0x06F8)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
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(RX_START_OFFSET + 0x06FC)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1 (RX_START_OFFSET + 0x0700)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2 (RX_START_OFFSET + 0x0704)
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#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3 (RX_START_OFFSET + 0x0708)
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#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
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#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
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#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
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#define LPASS_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C)
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#define LPASS_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790)
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#define LPASS_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800)
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#define LPASS_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804)
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#define LPASS_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808)
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#define LPASS_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C)
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#define LPASS_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810)
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#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
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#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
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#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
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#define LPASS_CDC_RX_COMPANDER0_CTL8 (RX_START_OFFSET + 0x0820)
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#define LPASS_CDC_RX_COMPANDER0_CTL9 (RX_START_OFFSET + 0x0824)
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#define LPASS_CDC_RX_COMPANDER0_CTL10 (RX_START_OFFSET + 0x0828)
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#define LPASS_CDC_RX_COMPANDER0_CTL11 (RX_START_OFFSET + 0x082C)
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#define LPASS_CDC_RX_COMPANDER0_CTL12 (RX_START_OFFSET + 0x0830)
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#define LPASS_CDC_RX_COMPANDER0_CTL13 (RX_START_OFFSET + 0x0834)
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#define LPASS_CDC_RX_COMPANDER0_CTL14 (RX_START_OFFSET + 0x0838)
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#define LPASS_CDC_RX_COMPANDER0_CTL15 (RX_START_OFFSET + 0x083C)
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#define LPASS_CDC_RX_COMPANDER0_CTL16 (RX_START_OFFSET + 0x0840)
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#define LPASS_CDC_RX_COMPANDER0_CTL17 (RX_START_OFFSET + 0x0844)
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#define LPASS_CDC_RX_COMPANDER0_CTL18 (RX_START_OFFSET + 0x0848)
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#define LPASS_CDC_RX_COMPANDER0_CTL19 (RX_START_OFFSET + 0x084C)
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#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0860)
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#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0864)
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#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0868)
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#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x086C)
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#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0870)
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#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0874)
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#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0878)
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#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x087C)
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#define LPASS_CDC_RX_COMPANDER1_CTL8 (RX_START_OFFSET + 0x0880)
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#define LPASS_CDC_RX_COMPANDER1_CTL9 (RX_START_OFFSET + 0x0884)
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#define LPASS_CDC_RX_COMPANDER1_CTL10 (RX_START_OFFSET + 0x0888)
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#define LPASS_CDC_RX_COMPANDER1_CTL11 (RX_START_OFFSET + 0x088C)
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#define LPASS_CDC_RX_COMPANDER1_CTL12 (RX_START_OFFSET + 0x0890)
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#define LPASS_CDC_RX_COMPANDER1_CTL13 (RX_START_OFFSET + 0x0894)
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#define LPASS_CDC_RX_COMPANDER1_CTL14 (RX_START_OFFSET + 0x0898)
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#define LPASS_CDC_RX_COMPANDER1_CTL15 (RX_START_OFFSET + 0x089C)
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#define LPASS_CDC_RX_COMPANDER1_CTL16 (RX_START_OFFSET + 0x08A0)
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#define LPASS_CDC_RX_COMPANDER1_CTL17 (RX_START_OFFSET + 0x08A4)
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#define LPASS_CDC_RX_COMPANDER1_CTL18 (RX_START_OFFSET + 0x08A8)
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#define LPASS_CDC_RX_COMPANDER1_CTL19 (RX_START_OFFSET + 0x08AC)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
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(RX_START_OFFSET + 0x0A00)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
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(RX_START_OFFSET + 0x0A04)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \
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(RX_START_OFFSET + 0x0A08)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \
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(RX_START_OFFSET + 0x0A0C)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \
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(RX_START_OFFSET + 0x0A10)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \
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(RX_START_OFFSET + 0x0A14)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \
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(RX_START_OFFSET + 0x0A18)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \
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(RX_START_OFFSET + 0x0A1C)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \
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(RX_START_OFFSET + 0x0A20)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \
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(RX_START_OFFSET + 0x0A28)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \
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(RX_START_OFFSET + 0x0A2C)
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#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \
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(RX_START_OFFSET + 0x0A30)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \
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(RX_START_OFFSET + 0x0A80)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \
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(RX_START_OFFSET + 0x0A84)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \
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(RX_START_OFFSET + 0x0A88)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \
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(RX_START_OFFSET + 0x0A8C)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \
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(RX_START_OFFSET + 0x0A90)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \
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(RX_START_OFFSET + 0x0A94)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \
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(RX_START_OFFSET + 0x0A98)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \
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(RX_START_OFFSET + 0x0A9C)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \
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(RX_START_OFFSET + 0x0AA0)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \
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(RX_START_OFFSET + 0x0AA8)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \
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(RX_START_OFFSET + 0x0AAC)
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#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \
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(RX_START_OFFSET + 0x0AB0)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18)
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#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C)
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#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \
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(RX_START_OFFSET + 0x0B40)
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#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
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(RX_START_OFFSET + 0x0B44)
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#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
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(RX_START_OFFSET + 0x0B50)
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#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
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(RX_START_OFFSET + 0x0B54)
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#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
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(RX_START_OFFSET + 0x0C00)
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#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04)
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#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
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(RX_START_OFFSET + 0x0C40)
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#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44)
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#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
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(RX_START_OFFSET + 0x0C80)
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#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84)
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#define LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00)
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#define LPASS_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04)
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#define LPASS_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08)
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#define LPASS_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C)
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#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
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(RX_START_OFFSET + 0x0D10)
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#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
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(RX_START_OFFSET + 0x0D14)
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#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
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(RX_START_OFFSET + 0x0D18)
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#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
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(RX_START_OFFSET + 0x0D1C)
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#define LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20)
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#define LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40)
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#define LPASS_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44)
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#define LPASS_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48)
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#define LPASS_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C)
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#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
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(RX_START_OFFSET + 0x0D50)
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#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
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(RX_START_OFFSET + 0x0D54)
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#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
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(RX_START_OFFSET + 0x0D58)
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#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
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(RX_START_OFFSET + 0x0D5C)
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#define LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60)
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#define LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80)
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#define LPASS_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84)
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#define LPASS_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88)
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#define LPASS_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C)
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#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
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(RX_START_OFFSET + 0x0D90)
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#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
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(RX_START_OFFSET + 0x0D94)
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#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
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(RX_START_OFFSET + 0x0D98)
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#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
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(RX_START_OFFSET + 0x0D9C)
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#define LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0)
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#define LPASS_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00)
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#define LPASS_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04)
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#define LPASS_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08)
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#define LPASS_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C)
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#define LPASS_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80)
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#define LPASS_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84)
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#define LPASS_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88)
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#define LPASS_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C)
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#define RX_MAX_OFFSET (RX_START_OFFSET + 0x0F8C)
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#define LPASS_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */
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/* WSA - macro#2 */
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#define WSA_START_OFFSET 0x2000
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#define LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL \
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(WSA_START_OFFSET + 0x0000)
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#define LPASS_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL \
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(WSA_START_OFFSET + 0x0004)
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#define LPASS_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (WSA_START_OFFSET + 0x0008)
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#define LPASS_CDC_WSA_TOP_TOP_CFG0 (WSA_START_OFFSET + 0x0080)
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#define LPASS_CDC_WSA_TOP_TOP_CFG1 (WSA_START_OFFSET + 0x0084)
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#define LPASS_CDC_WSA_TOP_FREQ_MCLK (WSA_START_OFFSET + 0x0088)
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#define LPASS_CDC_WSA_TOP_DEBUG_BUS_SEL (WSA_START_OFFSET + 0x008C)
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#define LPASS_CDC_WSA_TOP_DEBUG_EN0 (WSA_START_OFFSET + 0x0090)
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#define LPASS_CDC_WSA_TOP_DEBUG_EN1 (WSA_START_OFFSET + 0x0094)
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#define LPASS_CDC_WSA_TOP_DEBUG_DSM_LB (WSA_START_OFFSET + 0x0098)
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#define LPASS_CDC_WSA_TOP_RX_I2S_CTL (WSA_START_OFFSET + 0x009C)
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#define LPASS_CDC_WSA_TOP_TX_I2S_CTL (WSA_START_OFFSET + 0x00A0)
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#define LPASS_CDC_WSA_TOP_I2S_CLK (WSA_START_OFFSET + 0x00A4)
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#define LPASS_CDC_WSA_TOP_I2S_RESET (WSA_START_OFFSET + 0x00A8)
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#define LPASS_CDC_WSA_TOP_FS_UNGATE (WSA_START_OFFSET + 0x00AC)
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#define LPASS_CDC_WSA_TOP_GRP_SEL (WSA_START_OFFSET + 0x00B0)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB (WSA_START_OFFSET + 0x00B4)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB (WSA_START_OFFSET + 0x00B8)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT (WSA_START_OFFSET + 0x00BC)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB (WSA_START_OFFSET + 0x00C0)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB (WSA_START_OFFSET + 0x00C4)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB (WSA_START_OFFSET + 0x00C8)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB (WSA_START_OFFSET + 0x00CC)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT (WSA_START_OFFSET + 0x00D0)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB (WSA_START_OFFSET + 0x00D4)
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#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB (WSA_START_OFFSET + 0x00D8)
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#define LPASS_CDC_WSA_TOP_FS_UNGATE2 (WSA_START_OFFSET + 0x00DC)
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#define LPASS_CDC_WSA_TOP_SEQ_CTL0 (WSA_START_OFFSET + 0x00E0)
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#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (WSA_START_OFFSET + 0x0100)
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#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (WSA_START_OFFSET + 0x0104)
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#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (WSA_START_OFFSET + 0x0108)
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#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (WSA_START_OFFSET + 0x010C)
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#define LPASS_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (WSA_START_OFFSET + 0x0110)
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#define LPASS_CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (WSA_START_OFFSET + 0x0114)
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#define LPASS_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (WSA_START_OFFSET + 0x0118)
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/* VBAT registers */
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL (WSA_START_OFFSET + 0x0180)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_CFG (WSA_START_OFFSET + 0x0184)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1 (WSA_START_OFFSET + 0x0188)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2 (WSA_START_OFFSET + 0x018C)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3 (WSA_START_OFFSET + 0x0190)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST1 (WSA_START_OFFSET + 0x0194)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST2 (WSA_START_OFFSET + 0x0198)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST3 (WSA_START_OFFSET + 0x019C)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1 (WSA_START_OFFSET + 0x01A0)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2 (WSA_START_OFFSET + 0x01A4)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC1 (WSA_START_OFFSET + 0x01A8)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC2 (WSA_START_OFFSET + 0x01AC)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC3 (WSA_START_OFFSET + 0x01B0)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC4 (WSA_START_OFFSET + 0x01B4)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1 (WSA_START_OFFSET + 0x01B8)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2 (WSA_START_OFFSET + 0x01BC)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3 (WSA_START_OFFSET + 0x01C0)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4 (WSA_START_OFFSET + 0x01C4)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5 (WSA_START_OFFSET + 0x01C8)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DEBUG1 (WSA_START_OFFSET + 0x01CC)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON \
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(WSA_START_OFFSET + 0x01D0)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL \
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(WSA_START_OFFSET + 0x01D4)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BAN (WSA_START_OFFSET + 0x01D8)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \
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(WSA_START_OFFSET + 0x01DC)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \
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(WSA_START_OFFSET + 0x01E0)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \
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(WSA_START_OFFSET + 0x01E4)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \
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(WSA_START_OFFSET + 0x01E8)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \
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(WSA_START_OFFSET + 0x01EC)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \
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(WSA_START_OFFSET + 0x01F0)
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#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \
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|
(WSA_START_OFFSET + 0x01F4)
|
|
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \
|
|
(WSA_START_OFFSET + 0x01F8)
|
|
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \
|
|
(WSA_START_OFFSET + 0x01FC)
|
|
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0200)
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|
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0204)
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|
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0208)
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|
#define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0244)
|
|
#define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0248)
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|
#define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0264)
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|
#define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0268)
|
|
#define LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0284)
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|
#define LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0288)
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|
#define LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x02A4)
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|
#define LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x02A8)
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|
#define LPASS_CDC_WSA_INTR_CTRL_CFG (WSA_START_OFFSET + 0x0340)
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|
#define LPASS_CDC_WSA_INTR_CTRL_CLR_COMMIT (WSA_START_OFFSET + 0x0344)
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|
#define LPASS_CDC_WSA_INTR_CTRL_PIN1_MASK0 (WSA_START_OFFSET + 0x0360)
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|
#define LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0 (WSA_START_OFFSET + 0x0368)
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|
#define LPASS_CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (WSA_START_OFFSET + 0x0370)
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|
#define LPASS_CDC_WSA_INTR_CTRL_PIN2_MASK0 (WSA_START_OFFSET + 0x0380)
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#define LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0 (WSA_START_OFFSET + 0x0388)
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|
#define LPASS_CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (WSA_START_OFFSET + 0x0390)
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|
#define LPASS_CDC_WSA_INTR_CTRL_LEVEL0 (WSA_START_OFFSET + 0x03C0)
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|
#define LPASS_CDC_WSA_INTR_CTRL_BYPASS0 (WSA_START_OFFSET + 0x03C8)
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|
#define LPASS_CDC_WSA_INTR_CTRL_SET0 (WSA_START_OFFSET + 0x03D0)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_CTL (WSA_START_OFFSET + 0x0400)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG0 (WSA_START_OFFSET + 0x0404)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG1 (WSA_START_OFFSET + 0x0408)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG2 (WSA_START_OFFSET + 0x040C)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG3 (WSA_START_OFFSET + 0x0410)
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|
#define LPASS_CDC_WSA_RX0_RX_VOL_CTL (WSA_START_OFFSET + 0x0414)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_CTL (WSA_START_OFFSET + 0x0418)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_CFG (WSA_START_OFFSET + 0x041C)
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|
#define LPASS_CDC_WSA_RX0_RX_VOL_MIX_CTL (WSA_START_OFFSET + 0x0420)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC0 (WSA_START_OFFSET + 0x0424)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC1 (WSA_START_OFFSET + 0x0428)
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|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC2 (WSA_START_OFFSET + 0x042C)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC3 (WSA_START_OFFSET + 0x0430)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC5 (WSA_START_OFFSET + 0x0438)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC6 (WSA_START_OFFSET + 0x043C)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC7 (WSA_START_OFFSET + 0x0440)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC0 (WSA_START_OFFSET + 0x0444)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC1 (WSA_START_OFFSET + 0x0448)
|
|
#define LPASS_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (WSA_START_OFFSET + 0x044C)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_CTL (WSA_START_OFFSET + 0x0480)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG0 (WSA_START_OFFSET + 0x0484)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG1 (WSA_START_OFFSET + 0x0488)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG2 (WSA_START_OFFSET + 0x048C)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG3 (WSA_START_OFFSET + 0x0490)
|
|
#define LPASS_CDC_WSA_RX1_RX_VOL_CTL (WSA_START_OFFSET + 0x0494)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_CTL (WSA_START_OFFSET + 0x0498)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_CFG (WSA_START_OFFSET + 0x049C)
|
|
#define LPASS_CDC_WSA_RX1_RX_VOL_MIX_CTL (WSA_START_OFFSET + 0x04A0)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC0 (WSA_START_OFFSET + 0x04A4)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC1 (WSA_START_OFFSET + 0x04A8)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC2 (WSA_START_OFFSET + 0x04AC)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC3 (WSA_START_OFFSET + 0x04B0)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC5 (WSA_START_OFFSET + 0x04B8)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC6 (WSA_START_OFFSET + 0x04BC)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC7 (WSA_START_OFFSET + 0x04C0)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC0 (WSA_START_OFFSET + 0x04C4)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC1 (WSA_START_OFFSET + 0x04C8)
|
|
#define LPASS_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (WSA_START_OFFSET + 0x04CC)
|
|
#define LPASS_CDC_WSA_BOOST0_BOOST_PATH_CTL (WSA_START_OFFSET + 0x0500)
|
|
#define LPASS_CDC_WSA_BOOST0_BOOST_CTL (WSA_START_OFFSET + 0x0504)
|
|
#define LPASS_CDC_WSA_BOOST0_BOOST_CFG1 (WSA_START_OFFSET + 0x0508)
|
|
#define LPASS_CDC_WSA_BOOST0_BOOST_CFG2 (WSA_START_OFFSET + 0x050C)
|
|
#define LPASS_CDC_WSA_BOOST1_BOOST_PATH_CTL (WSA_START_OFFSET + 0x0540)
|
|
#define LPASS_CDC_WSA_BOOST1_BOOST_CTL (WSA_START_OFFSET + 0x0544)
|
|
#define LPASS_CDC_WSA_BOOST1_BOOST_CFG1 (WSA_START_OFFSET + 0x0548)
|
|
#define LPASS_CDC_WSA_BOOST1_BOOST_CFG2 (WSA_START_OFFSET + 0x054C)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL0 (WSA_START_OFFSET + 0x0580)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL1 (WSA_START_OFFSET + 0x0584)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL2 (WSA_START_OFFSET + 0x0588)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL3 (WSA_START_OFFSET + 0x058C)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL4 (WSA_START_OFFSET + 0x0590)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL5 (WSA_START_OFFSET + 0x0594)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL6 (WSA_START_OFFSET + 0x0598)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL7 (WSA_START_OFFSET + 0x059C)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL8 (WSA_START_OFFSET + 0x05A0)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL9 (WSA_START_OFFSET + 0x05A4)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL10 (WSA_START_OFFSET + 0x05A8)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL11 (WSA_START_OFFSET + 0x05AC)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL12 (WSA_START_OFFSET + 0x05B0)
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|
#define LPASS_CDC_WSA_COMPANDER0_CTL13 (WSA_START_OFFSET + 0x05B4)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL14 (WSA_START_OFFSET + 0x05B8)
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|
#define LPASS_CDC_WSA_COMPANDER0_CTL15 (WSA_START_OFFSET + 0x05BC)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL16 (WSA_START_OFFSET + 0x05C0)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL17 (WSA_START_OFFSET + 0x05C4)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL18 (WSA_START_OFFSET + 0x05C8)
|
|
#define LPASS_CDC_WSA_COMPANDER0_CTL19 (WSA_START_OFFSET + 0x05CC)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05E0)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05E4)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05E8)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05EC)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05F0)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05F4)
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|
#define LPASS_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05F8)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05FC)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL8 (WSA_START_OFFSET + 0x0600)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL9 (WSA_START_OFFSET + 0x0604)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL10 (WSA_START_OFFSET + 0x0608)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL11 (WSA_START_OFFSET + 0x060C)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL12 (WSA_START_OFFSET + 0x0610)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL13 (WSA_START_OFFSET + 0x0614)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL14 (WSA_START_OFFSET + 0x0618)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL15 (WSA_START_OFFSET + 0x061C)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL16 (WSA_START_OFFSET + 0x0620)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL17 (WSA_START_OFFSET + 0x0624)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL18 (WSA_START_OFFSET + 0x0628)
|
|
#define LPASS_CDC_WSA_COMPANDER1_CTL19 (WSA_START_OFFSET + 0x062C)
|
|
#define LPASS_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0640)
|
|
#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644)
|
|
#define LPASS_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0660)
|
|
#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0664)
|
|
#define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \
|
|
(WSA_START_OFFSET + 0x0680)
|
|
#define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x0684)
|
|
#define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \
|
|
(WSA_START_OFFSET + 0x06C0)
|
|
#define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x06C4)
|
|
#define LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL (WSA_START_OFFSET + 0x0780)
|
|
#define LPASS_CDC_WSA_IDLE_DETECT_CFG0 (WSA_START_OFFSET + 0x0784)
|
|
#define LPASS_CDC_WSA_IDLE_DETECT_CFG1 (WSA_START_OFFSET + 0x0788)
|
|
#define LPASS_CDC_WSA_IDLE_DETECT_CFG2 (WSA_START_OFFSET + 0x078C)
|
|
#define LPASS_CDC_WSA_IDLE_DETECT_CFG3 (WSA_START_OFFSET + 0x0790)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1 (WSA_START_OFFSET + 0x0900)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2 (WSA_START_OFFSET + 0x0904)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3 (WSA_START_OFFSET + 0x0908)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1 (WSA_START_OFFSET + 0x090C)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2 (WSA_START_OFFSET + 0x0910)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3 (WSA_START_OFFSET + 0x0914)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4 (WSA_START_OFFSET + 0x0918)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5 (WSA_START_OFFSET + 0x091C)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6 (WSA_START_OFFSET + 0x0920)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7 (WSA_START_OFFSET + 0x0924)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8 (WSA_START_OFFSET + 0x0928)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1 \
|
|
(WSA_START_OFFSET + 0x092C)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2 \
|
|
(WSA_START_OFFSET + 0x0930)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3 \
|
|
(WSA_START_OFFSET + 0x0934)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4 \
|
|
(WSA_START_OFFSET + 0x0938)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1 (WSA_START_OFFSET + 0x093C)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2 (WSA_START_OFFSET + 0x0940)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3 (WSA_START_OFFSET + 0x0944)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4 (WSA_START_OFFSET + 0x0948)
|
|
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5 (WSA_START_OFFSET + 0x094C)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL (WSA_START_OFFSET + 0x0980)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG (WSA_START_OFFSET + 0x0984)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1 (WSA_START_OFFSET + 0x0988)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2 (WSA_START_OFFSET + 0x098C)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3 (WSA_START_OFFSET + 0x0990)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1 (WSA_START_OFFSET + 0x0994)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2 (WSA_START_OFFSET + 0x0998)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3 (WSA_START_OFFSET + 0x099C)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1 (WSA_START_OFFSET + 0x09A0)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2 (WSA_START_OFFSET + 0x09A4)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1 (WSA_START_OFFSET + 0x09A8)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2 (WSA_START_OFFSET + 0x09AC)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3 (WSA_START_OFFSET + 0x09B0)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4 (WSA_START_OFFSET + 0x09B4)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1 (WSA_START_OFFSET + 0x09B8)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2 (WSA_START_OFFSET + 0x09BC)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3 (WSA_START_OFFSET + 0x09C0)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4 (WSA_START_OFFSET + 0x09C4)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5 (WSA_START_OFFSET + 0x09C8)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1 (WSA_START_OFFSET + 0x09CC)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON \
|
|
(WSA_START_OFFSET + 0x09D0)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL \
|
|
(WSA_START_OFFSET + 0x09D4)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN (WSA_START_OFFSET + 0x09D8)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
|
|
(WSA_START_OFFSET + 0x09DC)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
|
|
(WSA_START_OFFSET + 0x09E0)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
|
|
(WSA_START_OFFSET + 0x09E4)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
|
|
(WSA_START_OFFSET + 0x09E8)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
|
|
(WSA_START_OFFSET + 0x09EC)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
|
|
(WSA_START_OFFSET + 0x09F0)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
|
|
(WSA_START_OFFSET + 0x09F4)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
|
|
(WSA_START_OFFSET + 0x09F8)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
|
|
(WSA_START_OFFSET + 0x09FC)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0A00)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0A04)
|
|
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0A08)
|
|
/* lpass 2.6 new registers */
|
|
#define LPASS_CDC_WSA_PBR_PATH_CTL (WSA_START_OFFSET + 0xB00)
|
|
#define LPASS_CDC_WSA_LA_CFG (WSA_START_OFFSET + 0xB04)
|
|
#define LPASS_CDC_WSA_PBR_CFG1 (WSA_START_OFFSET + 0xB08)
|
|
#define LPASS_CDC_WSA_PBR_CFG2 (WSA_START_OFFSET + 0xB0C)
|
|
#define LPASS_CDC_WSA_PBR_CFG3 (WSA_START_OFFSET + 0xB10)
|
|
#define LPASS_CDC_WSA_PBR_CFG4 (WSA_START_OFFSET + 0xB14)
|
|
#define LPASS_CDC_WSA_PBR_CFG5 (WSA_START_OFFSET + 0xB18)
|
|
#define LPASS_CDC_WSA_PBR_CFG6 (WSA_START_OFFSET + 0xB1C)
|
|
#define LPASS_CDC_WSA_PBR_CFG7 (WSA_START_OFFSET + 0xB20)
|
|
#define LPASS_CDC_WSA_PBR_CFG8 (WSA_START_OFFSET + 0xB24)
|
|
#define LPASS_CDC_WSA_PBR_CFG9 (WSA_START_OFFSET + 0xB28)
|
|
#define LPASS_CDC_WSA_PBR_CFG10 (WSA_START_OFFSET + 0xB2C)
|
|
#define LPASS_CDC_WSA_PBR_CFG11 (WSA_START_OFFSET + 0xB30)
|
|
#define LPASS_CDC_WSA_PBR_CFG12 (WSA_START_OFFSET + 0xB34)
|
|
#define LPASS_CDC_WSA_PBR_CFG13 (WSA_START_OFFSET + 0xB38)
|
|
#define LPASS_CDC_WSA_PBR_CFG14 (WSA_START_OFFSET + 0xB3C)
|
|
#define LPASS_CDC_WSA_PBR_CFG15 (WSA_START_OFFSET + 0xB40)
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#define LPASS_CDC_WSA_PBR_CFG16 (WSA_START_OFFSET + 0xB44)
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#define LPASS_CDC_WSA_PBR_CFG17 (WSA_START_OFFSET + 0xB48)
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#define LPASS_CDC_WSA_ILIM_CFG0 (WSA_START_OFFSET + 0xB4C)
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#define LPASS_CDC_WSA_ILIM_CFG1 (WSA_START_OFFSET + 0xB50)
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#define LPASS_CDC_WSA_ILIM_CFG2 (WSA_START_OFFSET + 0xB54)
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#define LPASS_CDC_WSA_ILIM_CFG3 (WSA_START_OFFSET + 0xB58)
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#define LPASS_CDC_WSA_ILIM_CFG4 (WSA_START_OFFSET + 0xB5C)
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#define LPASS_CDC_WSA_ILIM_CFG5 (WSA_START_OFFSET + 0xB60)
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#define LPASS_CDC_WSA_ILIM_CFG6 (WSA_START_OFFSET + 0xB64)
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#define LPASS_CDC_WSA_ILIM_CFG7 (WSA_START_OFFSET + 0xB68)
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#define LPASS_CDC_WSA_ILIM_CFG8 (WSA_START_OFFSET + 0xB6C)
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#define LPASS_CDC_WSA_LA_CFG_1 (WSA_START_OFFSET + 0xB70)
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#define LPASS_CDC_WSA_PBR_CFG1_1 (WSA_START_OFFSET + 0xB74)
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#define LPASS_CDC_WSA_PBR_CFG2_1 (WSA_START_OFFSET + 0xB78)
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#define LPASS_CDC_WSA_PBR_CFG3_1 (WSA_START_OFFSET + 0xB7C)
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#define LPASS_CDC_WSA_PBR_CFG4_1 (WSA_START_OFFSET + 0xB80)
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#define LPASS_CDC_WSA_PBR_CFG5_1 (WSA_START_OFFSET + 0xB84)
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#define LPASS_CDC_WSA_PBR_CFG6_1 (WSA_START_OFFSET + 0xB88)
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#define LPASS_CDC_WSA_PBR_CFG7_1 (WSA_START_OFFSET + 0xB8C)
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#define LPASS_CDC_WSA_PBR_CFG8_1 (WSA_START_OFFSET + 0xB90)
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#define LPASS_CDC_WSA_PBR_CFG9_1 (WSA_START_OFFSET + 0xB94)
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#define LPASS_CDC_WSA_PBR_CFG10_1 (WSA_START_OFFSET + 0xB98)
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#define LPASS_CDC_WSA_PBR_CFG11_1 (WSA_START_OFFSET + 0xB9C)
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#define LPASS_CDC_WSA_PBR_CFG12_1 (WSA_START_OFFSET + 0xBA0)
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#define LPASS_CDC_WSA_PBR_CFG13_1 (WSA_START_OFFSET + 0xBA4)
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#define LPASS_CDC_WSA_PBR_CFG14_1 (WSA_START_OFFSET + 0xBA8)
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#define LPASS_CDC_WSA_PBR_CFG15_1 (WSA_START_OFFSET + 0xBAC)
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#define LPASS_CDC_WSA_PBR_CFG16_1 (WSA_START_OFFSET + 0xBB0)
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#define LPASS_CDC_WSA_ILIM_CFG0_1 (WSA_START_OFFSET + 0xBB4)
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#define LPASS_CDC_WSA_ILIM_CFG1_1 (WSA_START_OFFSET + 0xBB8)
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#define LPASS_CDC_WSA_ILIM_CFG2_1 (WSA_START_OFFSET + 0xBBC)
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#define LPASS_CDC_WSA_ILIM_CFG5_1 (WSA_START_OFFSET + 0xBC0)
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#define LPASS_CDC_WSA_ILIM_CFG9 (WSA_START_OFFSET + 0xBC4)
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#define LPASS_CDC_WSA_ILIM_CFG6_1 (WSA_START_OFFSET + 0xBC8)
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#define LPASS_CDC_WSA_PBR_CFG18 (WSA_START_OFFSET + 0xBCC)
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#define LPASS_CDC_WSA_PBR_CFG18_1 (WSA_START_OFFSET + 0xBD0)
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#define LPASS_CDC_WSA_PBR_CFG19 (WSA_START_OFFSET + 0xBD4)
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#define LPASS_CDC_WSA_PBR_CFG20 (WSA_START_OFFSET + 0xBD8)
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#define LPASS_CDC_WSA_PBR_CFG21 (WSA_START_OFFSET + 0xBDC)
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#define LPASS_CDC_WSA_PBR_CFG22 (WSA_START_OFFSET + 0xBE0)
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#define LPASS_CDC_WSA_PBR_CFG23 (WSA_START_OFFSET + 0xBE4)
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#define WSA_MAX_OFFSET (WSA_START_OFFSET + 0xBE4)
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#define LPASS_CDC_WSA_MACRO_MAX 0x2FA /* 0xBE4/4 = 0x2F9 + 1 registers */
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/* VA macro registers */
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#define VA_START_OFFSET 0x3000
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#define LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (VA_START_OFFSET + 0x0000)
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#define LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \
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(VA_START_OFFSET + 0x0004)
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#define LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL (VA_START_OFFSET + 0x0008)
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#define LPASS_CDC_VA_TOP_CSR_TOP_CFG0 (VA_START_OFFSET + 0x0080)
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#define LPASS_CDC_VA_TOP_CSR_DMIC0_CTL (VA_START_OFFSET + 0x0084)
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#define LPASS_CDC_VA_TOP_CSR_DMIC1_CTL (VA_START_OFFSET + 0x0088)
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#define LPASS_CDC_VA_TOP_CSR_DMIC2_CTL (VA_START_OFFSET + 0x008C)
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#define LPASS_CDC_VA_TOP_CSR_DMIC3_CTL (VA_START_OFFSET + 0x0090)
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#define LPASS_CDC_VA_TOP_CSR_DMIC_CFG (VA_START_OFFSET + 0x0094)
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#define LPASS_CDC_VA_TOP_CSR_VAD_MUX (VA_START_OFFSET + 0x0098)
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#define LPASS_CDC_VA_TOP_CSR_DEBUG_BUS (VA_START_OFFSET + 0x009C)
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#define LPASS_CDC_VA_TOP_CSR_DEBUG_EN (VA_START_OFFSET + 0x00A0)
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#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL (VA_START_OFFSET + 0x00A4)
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#define LPASS_CDC_VA_TOP_CSR_I2S_CLK (VA_START_OFFSET + 0x00A8)
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#define LPASS_CDC_VA_TOP_CSR_I2S_RESET (VA_START_OFFSET + 0x00AC)
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#define LPASS_CDC_VA_TOP_CSR_DEBUG_CLK (VA_START_OFFSET + 0x00B0)
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#define LPASS_CDC_VA_TOP_CSR_CORE_ID_0 (VA_START_OFFSET + 0x00C0)
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#define LPASS_CDC_VA_TOP_CSR_CORE_ID_1 (VA_START_OFFSET + 0x00C4)
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#define LPASS_CDC_VA_TOP_CSR_CORE_ID_2 (VA_START_OFFSET + 0x00C8)
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#define LPASS_CDC_VA_TOP_CSR_CORE_ID_3 (VA_START_OFFSET + 0x00CC)
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#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0 (VA_START_OFFSET + 0x00D0)
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#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1 (VA_START_OFFSET + 0x00D4)
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#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2 (VA_START_OFFSET + 0x00D8)
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#define LPASS_CDC_VA_TOP_CSR_SWR_CTRL (VA_START_OFFSET + 0x00DC)
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#define LPASS_CDC_VA_TOP_CSR_SEQ_CTL0 (VA_START_OFFSET + 0x00E0)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 (VA_START_OFFSET + 0x0100)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 (VA_START_OFFSET + 0x0104)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0 (VA_START_OFFSET + 0x0108)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1 (VA_START_OFFSET + 0x010C)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0 (VA_START_OFFSET + 0x0110)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1 (VA_START_OFFSET + 0x0114)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0 (VA_START_OFFSET + 0x0118)
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#define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1 (VA_START_OFFSET + 0x011C)
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#define LPASS_CDC_VA_TX0_TX_PATH_CTL (VA_START_OFFSET + 0x0400)
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#define LPASS_CDC_VA_TX0_TX_PATH_CFG0 (VA_START_OFFSET + 0x0404)
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#define LPASS_CDC_VA_TX0_TX_PATH_CFG1 (VA_START_OFFSET + 0x0408)
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#define LPASS_CDC_VA_TX0_TX_VOL_CTL (VA_START_OFFSET + 0x040C)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC0 (VA_START_OFFSET + 0x0410)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC1 (VA_START_OFFSET + 0x0414)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC2 (VA_START_OFFSET + 0x0418)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC3 (VA_START_OFFSET + 0x041C)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC4 (VA_START_OFFSET + 0x0420)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC5 (VA_START_OFFSET + 0x0424)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC6 (VA_START_OFFSET + 0x0428)
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#define LPASS_CDC_VA_TX0_TX_PATH_SEC7 (VA_START_OFFSET + 0x042C)
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#define LPASS_CDC_VA_TX1_TX_PATH_CTL (VA_START_OFFSET + 0x0480)
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#define LPASS_CDC_VA_TX1_TX_PATH_CFG0 (VA_START_OFFSET + 0x0484)
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#define LPASS_CDC_VA_TX1_TX_PATH_CFG1 (VA_START_OFFSET + 0x0488)
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#define LPASS_CDC_VA_TX1_TX_VOL_CTL (VA_START_OFFSET + 0x048C)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC0 (VA_START_OFFSET + 0x0490)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC1 (VA_START_OFFSET + 0x0494)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC2 (VA_START_OFFSET + 0x0498)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC3 (VA_START_OFFSET + 0x049C)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC4 (VA_START_OFFSET + 0x04A0)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC5 (VA_START_OFFSET + 0x04A4)
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#define LPASS_CDC_VA_TX1_TX_PATH_SEC6 (VA_START_OFFSET + 0x04A8)
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#define LPASS_CDC_VA_TX2_TX_PATH_CTL (VA_START_OFFSET + 0x0500)
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#define LPASS_CDC_VA_TX2_TX_PATH_CFG0 (VA_START_OFFSET + 0x0504)
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#define LPASS_CDC_VA_TX2_TX_PATH_CFG1 (VA_START_OFFSET + 0x0508)
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#define LPASS_CDC_VA_TX2_TX_VOL_CTL (VA_START_OFFSET + 0x050C)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC0 (VA_START_OFFSET + 0x0510)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC1 (VA_START_OFFSET + 0x0514)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC2 (VA_START_OFFSET + 0x0518)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC3 (VA_START_OFFSET + 0x051C)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC4 (VA_START_OFFSET + 0x0520)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC5 (VA_START_OFFSET + 0x0524)
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#define LPASS_CDC_VA_TX2_TX_PATH_SEC6 (VA_START_OFFSET + 0x0528)
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#define LPASS_CDC_VA_TX3_TX_PATH_CTL (VA_START_OFFSET + 0x0580)
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#define LPASS_CDC_VA_TX3_TX_PATH_CFG0 (VA_START_OFFSET + 0x0584)
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#define LPASS_CDC_VA_TX3_TX_PATH_CFG1 (VA_START_OFFSET + 0x0588)
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#define LPASS_CDC_VA_TX3_TX_VOL_CTL (VA_START_OFFSET + 0x058C)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC0 (VA_START_OFFSET + 0x0590)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC1 (VA_START_OFFSET + 0x0594)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC2 (VA_START_OFFSET + 0x0598)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC3 (VA_START_OFFSET + 0x059C)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC4 (VA_START_OFFSET + 0x05A0)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC5 (VA_START_OFFSET + 0x05A4)
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#define LPASS_CDC_VA_TX3_TX_PATH_SEC6 (VA_START_OFFSET + 0x05A8)
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#define VA_MAX_OFFSET (VA_START_OFFSET + 0x05A8)
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#define LPASS_CDC_VA_MACRO_MAX 0x16B /* 5A8/4 = 16A + 1 = 16B */
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/* WSA2 - macro#5 */
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#define WSA2_START_OFFSET 0x4000
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#define LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL \
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(WSA2_START_OFFSET + 0x0000)
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#define LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL \
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(WSA2_START_OFFSET + 0x0004)
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#define LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL (WSA2_START_OFFSET + 0x0008)
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#define LPASS_CDC_WSA2_TOP_TOP_CFG0 (WSA2_START_OFFSET + 0x0080)
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#define LPASS_CDC_WSA2_TOP_TOP_CFG1 (WSA2_START_OFFSET + 0x0084)
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#define LPASS_CDC_WSA2_TOP_FREQ_MCLK (WSA2_START_OFFSET + 0x0088)
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#define LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL (WSA2_START_OFFSET + 0x008C)
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#define LPASS_CDC_WSA2_TOP_DEBUG_EN0 (WSA2_START_OFFSET + 0x0090)
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#define LPASS_CDC_WSA2_TOP_DEBUG_EN1 (WSA2_START_OFFSET + 0x0094)
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#define LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB (WSA2_START_OFFSET + 0x0098)
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#define LPASS_CDC_WSA2_TOP_RX_I2S_CTL (WSA2_START_OFFSET + 0x009C)
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#define LPASS_CDC_WSA2_TOP_TX_I2S_CTL (WSA2_START_OFFSET + 0x00A0)
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#define LPASS_CDC_WSA2_TOP_I2S_CLK (WSA2_START_OFFSET + 0x00A4)
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#define LPASS_CDC_WSA2_TOP_I2S_RESET (WSA2_START_OFFSET + 0x00A8)
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#define LPASS_CDC_WSA2_TOP_FS_UNGATE (WSA2_START_OFFSET + 0x00AC)
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#define LPASS_CDC_WSA2_TOP_GRP_SEL (WSA2_START_OFFSET + 0x00B0)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB (WSA2_START_OFFSET + 0x00B4)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB (WSA2_START_OFFSET + 0x00B8)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT (WSA2_START_OFFSET + 0x00BC)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB (WSA2_START_OFFSET + 0x00C0)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB (WSA2_START_OFFSET + 0x00C4)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB (WSA2_START_OFFSET + 0x00C8)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB (WSA2_START_OFFSET + 0x00CC)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT (WSA2_START_OFFSET + 0x00D0)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB (WSA2_START_OFFSET + 0x00D4)
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#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB (WSA2_START_OFFSET + 0x00D8)
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#define LPASS_CDC_WSA2_TOP_FS_UNGATE2 (WSA2_START_OFFSET + 0x00DC)
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|
#define LPASS_CDC_WSA2_TOP_SEQ_CTL0 (WSA2_START_OFFSET + 0x00E0)
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|
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0 (WSA2_START_OFFSET + 0x0100)
|
|
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1 (WSA2_START_OFFSET + 0x0104)
|
|
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0 (WSA2_START_OFFSET + 0x0108)
|
|
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1 (WSA2_START_OFFSET + 0x010C)
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|
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0 (WSA2_START_OFFSET + 0x0110)
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|
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0 (WSA2_START_OFFSET + 0x0114)
|
|
#define LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0 (WSA2_START_OFFSET + 0x0118)
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|
/* VBAT registers */
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|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL (WSA2_START_OFFSET + 0x0180)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG (WSA2_START_OFFSET + 0x0184)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1 (WSA2_START_OFFSET + 0x0188)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2 (WSA2_START_OFFSET + 0x018C)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3 (WSA2_START_OFFSET + 0x0190)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1 (WSA2_START_OFFSET + 0x0194)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2 (WSA2_START_OFFSET + 0x0198)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3 (WSA2_START_OFFSET + 0x019C)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1 (WSA2_START_OFFSET + 0x01A0)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2 (WSA2_START_OFFSET + 0x01A4)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1 (WSA2_START_OFFSET + 0x01A8)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2 (WSA2_START_OFFSET + 0x01AC)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3 (WSA2_START_OFFSET + 0x01B0)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4 (WSA2_START_OFFSET + 0x01B4)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1 (WSA2_START_OFFSET + 0x01B8)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2 (WSA2_START_OFFSET + 0x01BC)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3 (WSA2_START_OFFSET + 0x01C0)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4 (WSA2_START_OFFSET + 0x01C4)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5 (WSA2_START_OFFSET + 0x01C8)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1 (WSA2_START_OFFSET + 0x01CC)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON \
|
|
(WSA2_START_OFFSET + 0x01D0)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL \
|
|
(WSA2_START_OFFSET + 0x01D4)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN (WSA2_START_OFFSET + 0x01D8)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \
|
|
(WSA2_START_OFFSET + 0x01DC)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \
|
|
(WSA2_START_OFFSET + 0x01E0)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \
|
|
(WSA2_START_OFFSET + 0x01E4)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \
|
|
(WSA2_START_OFFSET + 0x01E8)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \
|
|
(WSA2_START_OFFSET + 0x01EC)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \
|
|
(WSA2_START_OFFSET + 0x01F0)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \
|
|
(WSA2_START_OFFSET + 0x01F4)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \
|
|
(WSA2_START_OFFSET + 0x01F8)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \
|
|
(WSA2_START_OFFSET + 0x01FC)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1 (WSA2_START_OFFSET + 0x0200)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2 (WSA2_START_OFFSET + 0x0204)
|
|
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3 (WSA2_START_OFFSET + 0x0208)
|
|
#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0244)
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#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0248)
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#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0264)
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#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0268)
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#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0284)
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#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0288)
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#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x02A4)
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#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x02A8)
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#define LPASS_CDC_WSA2_INTR_CTRL_CFG (WSA2_START_OFFSET + 0x0340)
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#define LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT (WSA2_START_OFFSET + 0x0344)
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#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0 (WSA2_START_OFFSET + 0x0360)
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#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0 (WSA2_START_OFFSET + 0x0368)
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#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0 (WSA2_START_OFFSET + 0x0370)
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#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0 (WSA2_START_OFFSET + 0x0380)
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#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0 (WSA2_START_OFFSET + 0x0388)
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#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0 (WSA2_START_OFFSET + 0x0390)
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#define LPASS_CDC_WSA2_INTR_CTRL_LEVEL0 (WSA2_START_OFFSET + 0x03C0)
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#define LPASS_CDC_WSA2_INTR_CTRL_BYPASS0 (WSA2_START_OFFSET + 0x03C8)
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#define LPASS_CDC_WSA2_INTR_CTRL_SET0 (WSA2_START_OFFSET + 0x03D0)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_CTL (WSA2_START_OFFSET + 0x0400)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG0 (WSA2_START_OFFSET + 0x0404)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG1 (WSA2_START_OFFSET + 0x0408)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG2 (WSA2_START_OFFSET + 0x040C)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG3 (WSA2_START_OFFSET + 0x0410)
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#define LPASS_CDC_WSA2_RX0_RX_VOL_CTL (WSA2_START_OFFSET + 0x0414)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL (WSA2_START_OFFSET + 0x0418)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG (WSA2_START_OFFSET + 0x041C)
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#define LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL (WSA2_START_OFFSET + 0x0420)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC0 (WSA2_START_OFFSET + 0x0424)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC1 (WSA2_START_OFFSET + 0x0428)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC2 (WSA2_START_OFFSET + 0x042C)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC3 (WSA2_START_OFFSET + 0x0430)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC5 (WSA2_START_OFFSET + 0x0438)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC6 (WSA2_START_OFFSET + 0x043C)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC7 (WSA2_START_OFFSET + 0x0440)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0 (WSA2_START_OFFSET + 0x0444)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1 (WSA2_START_OFFSET + 0x0448)
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#define LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL (WSA2_START_OFFSET + 0x044C)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_CTL (WSA2_START_OFFSET + 0x0480)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG0 (WSA2_START_OFFSET + 0x0484)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG1 (WSA2_START_OFFSET + 0x0488)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG2 (WSA2_START_OFFSET + 0x048C)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG3 (WSA2_START_OFFSET + 0x0490)
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#define LPASS_CDC_WSA2_RX1_RX_VOL_CTL (WSA2_START_OFFSET + 0x0494)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL (WSA2_START_OFFSET + 0x0498)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG (WSA2_START_OFFSET + 0x049C)
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#define LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL (WSA2_START_OFFSET + 0x04A0)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC0 (WSA2_START_OFFSET + 0x04A4)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC1 (WSA2_START_OFFSET + 0x04A8)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC2 (WSA2_START_OFFSET + 0x04AC)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC3 (WSA2_START_OFFSET + 0x04B0)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC5 (WSA2_START_OFFSET + 0x04B8)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC6 (WSA2_START_OFFSET + 0x04BC)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC7 (WSA2_START_OFFSET + 0x04C0)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0 (WSA2_START_OFFSET + 0x04C4)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1 (WSA2_START_OFFSET + 0x04C8)
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#define LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL (WSA2_START_OFFSET + 0x04CC)
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#define LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL (WSA2_START_OFFSET + 0x0500)
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#define LPASS_CDC_WSA2_BOOST0_BOOST_CTL (WSA2_START_OFFSET + 0x0504)
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#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG1 (WSA2_START_OFFSET + 0x0508)
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#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG2 (WSA2_START_OFFSET + 0x050C)
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#define LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL (WSA2_START_OFFSET + 0x0540)
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#define LPASS_CDC_WSA2_BOOST1_BOOST_CTL (WSA2_START_OFFSET + 0x0544)
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#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG1 (WSA2_START_OFFSET + 0x0548)
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#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG2 (WSA2_START_OFFSET + 0x054C)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL0 (WSA2_START_OFFSET + 0x0580)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL1 (WSA2_START_OFFSET + 0x0584)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL2 (WSA2_START_OFFSET + 0x0588)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL3 (WSA2_START_OFFSET + 0x058C)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL4 (WSA2_START_OFFSET + 0x0590)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL5 (WSA2_START_OFFSET + 0x0594)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL6 (WSA2_START_OFFSET + 0x0598)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL7 (WSA2_START_OFFSET + 0x059C)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL8 (WSA2_START_OFFSET + 0x05A0)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL9 (WSA2_START_OFFSET + 0x05A4)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL10 (WSA2_START_OFFSET + 0x05A8)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL11 (WSA2_START_OFFSET + 0x05AC)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL12 (WSA2_START_OFFSET + 0x05B0)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL13 (WSA2_START_OFFSET + 0x05B4)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL14 (WSA2_START_OFFSET + 0x05B8)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL15 (WSA2_START_OFFSET + 0x05BC)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL16 (WSA2_START_OFFSET + 0x05C0)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL17 (WSA2_START_OFFSET + 0x05C4)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL18 (WSA2_START_OFFSET + 0x05C8)
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#define LPASS_CDC_WSA2_COMPANDER0_CTL19 (WSA2_START_OFFSET + 0x05CC)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL0 (WSA2_START_OFFSET + 0x05E0)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL1 (WSA2_START_OFFSET + 0x05E4)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL2 (WSA2_START_OFFSET + 0x05E8)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL3 (WSA2_START_OFFSET + 0x05EC)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL4 (WSA2_START_OFFSET + 0x05F0)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL5 (WSA2_START_OFFSET + 0x05F4)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL6 (WSA2_START_OFFSET + 0x05F8)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL7 (WSA2_START_OFFSET + 0x05FC)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL8 (WSA2_START_OFFSET + 0x0600)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL9 (WSA2_START_OFFSET + 0x0604)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL10 (WSA2_START_OFFSET + 0x0608)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL11 (WSA2_START_OFFSET + 0x060C)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL12 (WSA2_START_OFFSET + 0x0610)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL13 (WSA2_START_OFFSET + 0x0614)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL14 (WSA2_START_OFFSET + 0x0618)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL15 (WSA2_START_OFFSET + 0x061C)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL16 (WSA2_START_OFFSET + 0x0620)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL17 (WSA2_START_OFFSET + 0x0624)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL18 (WSA2_START_OFFSET + 0x0628)
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#define LPASS_CDC_WSA2_COMPANDER1_CTL19 (WSA2_START_OFFSET + 0x062C)
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#define LPASS_CDC_WSA2_SOFTCLIP0_CRC (WSA2_START_OFFSET + 0x0640)
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#define LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL (WSA2_START_OFFSET + 0x0644)
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#define LPASS_CDC_WSA2_SOFTCLIP1_CRC (WSA2_START_OFFSET + 0x0660)
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#define LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL (WSA2_START_OFFSET + 0x0664)
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#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL \
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(WSA2_START_OFFSET + 0x0680)
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#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0 (WSA2_START_OFFSET + 0x0684)
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#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL \
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(WSA2_START_OFFSET + 0x06C0)
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#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0 (WSA2_START_OFFSET + 0x06C4)
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#define LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL (WSA2_START_OFFSET + 0x0780)
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#define LPASS_CDC_WSA2_IDLE_DETECT_CFG0 (WSA2_START_OFFSET + 0x0784)
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#define LPASS_CDC_WSA2_IDLE_DETECT_CFG1 (WSA2_START_OFFSET + 0x0788)
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#define LPASS_CDC_WSA2_IDLE_DETECT_CFG2 (WSA2_START_OFFSET + 0x078C)
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#define LPASS_CDC_WSA2_IDLE_DETECT_CFG3 (WSA2_START_OFFSET + 0x0790)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1 (WSA2_START_OFFSET + 0x0900)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2 (WSA2_START_OFFSET + 0x0904)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3 (WSA2_START_OFFSET + 0x0908)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1 (WSA2_START_OFFSET + 0x090C)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2 (WSA2_START_OFFSET + 0x0910)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3 (WSA2_START_OFFSET + 0x0914)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4 (WSA2_START_OFFSET + 0x0918)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5 (WSA2_START_OFFSET + 0x091C)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6 (WSA2_START_OFFSET + 0x0920)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7 (WSA2_START_OFFSET + 0x0924)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8 (WSA2_START_OFFSET + 0x0928)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1 \
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(WSA2_START_OFFSET + 0x092C)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2 \
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(WSA2_START_OFFSET + 0x0930)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3 \
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(WSA2_START_OFFSET + 0x0934)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4 \
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(WSA2_START_OFFSET + 0x0938)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1 (WSA2_START_OFFSET + 0x093C)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2 (WSA2_START_OFFSET + 0x0940)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3 (WSA2_START_OFFSET + 0x0944)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4 (WSA2_START_OFFSET + 0x0948)
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#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5 (WSA2_START_OFFSET + 0x094C)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL (WSA2_START_OFFSET + 0x0980)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG (WSA2_START_OFFSET + 0x0984)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1 (WSA2_START_OFFSET + 0x0988)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2 (WSA2_START_OFFSET + 0x098C)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3 (WSA2_START_OFFSET + 0x0990)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1 (WSA2_START_OFFSET + 0x0994)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2 (WSA2_START_OFFSET + 0x0998)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3 (WSA2_START_OFFSET + 0x099C)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1 (WSA2_START_OFFSET + 0x09A0)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2 (WSA2_START_OFFSET + 0x09A4)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1 (WSA2_START_OFFSET + 0x09A8)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2 (WSA2_START_OFFSET + 0x09AC)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3 (WSA2_START_OFFSET + 0x09B0)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4 (WSA2_START_OFFSET + 0x09B4)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1 (WSA2_START_OFFSET + 0x09B8)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2 (WSA2_START_OFFSET + 0x09BC)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3 (WSA2_START_OFFSET + 0x09C0)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4 (WSA2_START_OFFSET + 0x09C4)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5 (WSA2_START_OFFSET + 0x09C8)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1 (WSA2_START_OFFSET + 0x09CC)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON \
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(WSA2_START_OFFSET + 0x09D0)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL \
|
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(WSA2_START_OFFSET + 0x09D4)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN (WSA2_START_OFFSET + 0x09D8)
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#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
|
|
(WSA2_START_OFFSET + 0x09DC)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
|
|
(WSA2_START_OFFSET + 0x09E0)
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|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
|
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(WSA2_START_OFFSET + 0x09E4)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
|
|
(WSA2_START_OFFSET + 0x09E8)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
|
|
(WSA2_START_OFFSET + 0x09EC)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
|
|
(WSA2_START_OFFSET + 0x09F0)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
|
|
(WSA2_START_OFFSET + 0x09F4)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
|
|
(WSA2_START_OFFSET + 0x09F8)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
|
|
(WSA2_START_OFFSET + 0x09FC)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1 (WSA2_START_OFFSET + 0x0A00)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2 (WSA2_START_OFFSET + 0x0A04)
|
|
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3 (WSA2_START_OFFSET + 0x0A08)
|
|
/* lpass 2.6 new registers */
|
|
#define LPASS_CDC_WSA2_PBR_PATH_CTL (WSA2_START_OFFSET + 0xB00)
|
|
#define LPASS_CDC_WSA2_LA_CFG (WSA2_START_OFFSET + 0xB04)
|
|
#define LPASS_CDC_WSA2_PBR_CFG1 (WSA2_START_OFFSET + 0xB08)
|
|
#define LPASS_CDC_WSA2_PBR_CFG2 (WSA2_START_OFFSET + 0xB0C)
|
|
#define LPASS_CDC_WSA2_PBR_CFG3 (WSA2_START_OFFSET + 0xB10)
|
|
#define LPASS_CDC_WSA2_PBR_CFG4 (WSA2_START_OFFSET + 0xB14)
|
|
#define LPASS_CDC_WSA2_PBR_CFG5 (WSA2_START_OFFSET + 0xB18)
|
|
#define LPASS_CDC_WSA2_PBR_CFG6 (WSA2_START_OFFSET + 0xB1C)
|
|
#define LPASS_CDC_WSA2_PBR_CFG7 (WSA2_START_OFFSET + 0xB20)
|
|
#define LPASS_CDC_WSA2_PBR_CFG8 (WSA2_START_OFFSET + 0xB24)
|
|
#define LPASS_CDC_WSA2_PBR_CFG9 (WSA2_START_OFFSET + 0xB28)
|
|
#define LPASS_CDC_WSA2_PBR_CFG10 (WSA2_START_OFFSET + 0xB2C)
|
|
#define LPASS_CDC_WSA2_PBR_CFG11 (WSA2_START_OFFSET + 0xB30)
|
|
#define LPASS_CDC_WSA2_PBR_CFG12 (WSA2_START_OFFSET + 0xB34)
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#define LPASS_CDC_WSA2_PBR_CFG13 (WSA2_START_OFFSET + 0xB38)
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#define LPASS_CDC_WSA2_PBR_CFG14 (WSA2_START_OFFSET + 0xB3C)
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#define LPASS_CDC_WSA2_PBR_CFG15 (WSA2_START_OFFSET + 0xB40)
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#define LPASS_CDC_WSA2_PBR_CFG16 (WSA2_START_OFFSET + 0xB44)
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#define LPASS_CDC_WSA2_PBR_CFG17 (WSA2_START_OFFSET + 0xB48)
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#define LPASS_CDC_WSA2_ILIM_CFG0 (WSA2_START_OFFSET + 0xB4C)
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#define LPASS_CDC_WSA2_ILIM_CFG1 (WSA2_START_OFFSET + 0xB50)
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#define LPASS_CDC_WSA2_ILIM_CFG2 (WSA2_START_OFFSET + 0xB54)
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#define LPASS_CDC_WSA2_ILIM_CFG3 (WSA2_START_OFFSET + 0xB58)
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#define LPASS_CDC_WSA2_ILIM_CFG4 (WSA2_START_OFFSET + 0xB5C)
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#define LPASS_CDC_WSA2_ILIM_CFG5 (WSA2_START_OFFSET + 0xB60)
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#define LPASS_CDC_WSA2_ILIM_CFG6 (WSA2_START_OFFSET + 0xB64)
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#define LPASS_CDC_WSA2_ILIM_CFG7 (WSA2_START_OFFSET + 0xB68)
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#define LPASS_CDC_WSA2_ILIM_CFG8 (WSA2_START_OFFSET + 0xB6C)
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#define LPASS_CDC_WSA2_LA_CFG_1 (WSA2_START_OFFSET + 0xB70)
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#define LPASS_CDC_WSA2_PBR_CFG1_1 (WSA2_START_OFFSET + 0xB74)
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#define LPASS_CDC_WSA2_PBR_CFG2_1 (WSA2_START_OFFSET + 0xB78)
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#define LPASS_CDC_WSA2_PBR_CFG3_1 (WSA2_START_OFFSET + 0xB7C)
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#define LPASS_CDC_WSA2_PBR_CFG4_1 (WSA2_START_OFFSET + 0xB80)
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#define LPASS_CDC_WSA2_PBR_CFG5_1 (WSA2_START_OFFSET + 0xB84)
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#define LPASS_CDC_WSA2_PBR_CFG6_1 (WSA2_START_OFFSET + 0xB88)
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#define LPASS_CDC_WSA2_PBR_CFG7_1 (WSA2_START_OFFSET + 0xB8C)
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#define LPASS_CDC_WSA2_PBR_CFG8_1 (WSA2_START_OFFSET + 0xB90)
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#define LPASS_CDC_WSA2_PBR_CFG9_1 (WSA2_START_OFFSET + 0xB94)
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#define LPASS_CDC_WSA2_PBR_CFG10_1 (WSA2_START_OFFSET + 0xB98)
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#define LPASS_CDC_WSA2_PBR_CFG11_1 (WSA2_START_OFFSET + 0xB9C)
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#define LPASS_CDC_WSA2_PBR_CFG12_1 (WSA2_START_OFFSET + 0xBA0)
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#define LPASS_CDC_WSA2_PBR_CFG13_1 (WSA2_START_OFFSET + 0xBA4)
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#define LPASS_CDC_WSA2_PBR_CFG14_1 (WSA2_START_OFFSET + 0xBA8)
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#define LPASS_CDC_WSA2_PBR_CFG15_1 (WSA2_START_OFFSET + 0xBAC)
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#define LPASS_CDC_WSA2_PBR_CFG16_1 (WSA2_START_OFFSET + 0xBB0)
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#define LPASS_CDC_WSA2_ILIM_CFG0_1 (WSA2_START_OFFSET + 0xBB4)
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#define LPASS_CDC_WSA2_ILIM_CFG1_1 (WSA2_START_OFFSET + 0xBB8)
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#define LPASS_CDC_WSA2_ILIM_CFG2_1 (WSA2_START_OFFSET + 0xBBC)
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#define LPASS_CDC_WSA2_ILIM_CFG5_1 (WSA2_START_OFFSET + 0xBC0)
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#define LPASS_CDC_WSA2_ILIM_CFG9 (WSA2_START_OFFSET + 0xBC4)
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#define LPASS_CDC_WSA2_ILIM_CFG6_1 (WSA2_START_OFFSET + 0xBC8)
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#define LPASS_CDC_WSA2_PBR_CFG18 (WSA2_START_OFFSET + 0xBCC)
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#define LPASS_CDC_WSA2_PBR_CFG18_1 (WSA2_START_OFFSET + 0xBD0)
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#define LPASS_CDC_WSA2_PBR_CFG19 (WSA2_START_OFFSET + 0xBD4)
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#define LPASS_CDC_WSA2_PBR_CFG20 (WSA2_START_OFFSET + 0xBD8)
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#define LPASS_CDC_WSA2_PBR_CFG21 (WSA2_START_OFFSET + 0xBDC)
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#define LPASS_CDC_WSA2_PBR_CFG22 (WSA2_START_OFFSET + 0xBE0)
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#define LPASS_CDC_WSA2_PBR_CFG23 (WSA2_START_OFFSET + 0xBE4)
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#define WSA2_MAX_OFFSET (WSA2_START_OFFSET + 0xBE4)
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#define LPASS_CDC_WSA2_MACRO_MAX 0x2FA /* 0xBE4/4 = 0x2F9 + 1 registers */
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#define LPASS_CDC_MAX_REGISTER WSA2_MAX_OFFSET
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#define LPASS_CDC_REG(reg) (((reg) & 0x0FFF)/4)
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#endif
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