sde_hw_intf.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/iopoll.h>
  6. #include "sde_hwio.h"
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_intf.h"
  9. #include "sde_dbg.h"
  10. #include "sde_kms.h"
  11. #define INTF_TIMING_ENGINE_EN 0x000
  12. #define INTF_CONFIG 0x004
  13. #define INTF_HSYNC_CTL 0x008
  14. #define INTF_VSYNC_PERIOD_F0 0x00C
  15. #define INTF_VSYNC_PERIOD_F1 0x010
  16. #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
  17. #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
  18. #define INTF_DISPLAY_V_START_F0 0x01C
  19. #define INTF_DISPLAY_V_START_F1 0x020
  20. #define INTF_DISPLAY_V_END_F0 0x024
  21. #define INTF_DISPLAY_V_END_F1 0x028
  22. #define INTF_ACTIVE_V_START_F0 0x02C
  23. #define INTF_ACTIVE_V_START_F1 0x030
  24. #define INTF_ACTIVE_V_END_F0 0x034
  25. #define INTF_ACTIVE_V_END_F1 0x038
  26. #define INTF_DISPLAY_HCTL 0x03C
  27. #define INTF_ACTIVE_HCTL 0x040
  28. #define INTF_BORDER_COLOR 0x044
  29. #define INTF_UNDERFLOW_COLOR 0x048
  30. #define INTF_HSYNC_SKEW 0x04C
  31. #define INTF_POLARITY_CTL 0x050
  32. #define INTF_TEST_CTL 0x054
  33. #define INTF_TP_COLOR0 0x058
  34. #define INTF_TP_COLOR1 0x05C
  35. #define INTF_CONFIG2 0x060
  36. #define INTF_DISPLAY_DATA_HCTL 0x064
  37. #define INTF_ACTIVE_DATA_HCTL 0x068
  38. #define INTF_FRAME_LINE_COUNT_EN 0x0A8
  39. #define INTF_FRAME_COUNT 0x0AC
  40. #define INTF_LINE_COUNT 0x0B0
  41. #define INTF_DEFLICKER_CONFIG 0x0F0
  42. #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
  43. #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
  44. #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
  45. #define INTF_PANEL_FORMAT 0x090
  46. #define INTF_TPG_ENABLE 0x100
  47. #define INTF_TPG_MAIN_CONTROL 0x104
  48. #define INTF_TPG_VIDEO_CONFIG 0x108
  49. #define INTF_TPG_COMPONENT_LIMITS 0x10C
  50. #define INTF_TPG_RECTANGLE 0x110
  51. #define INTF_TPG_INITIAL_VALUE 0x114
  52. #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
  53. #define INTF_TPG_RGB_MAPPING 0x11C
  54. #define INTF_PROG_FETCH_START 0x170
  55. #define INTF_PROG_ROT_START 0x174
  56. #define INTF_MISR_CTRL 0x180
  57. #define INTF_MISR_SIGNATURE 0x184
  58. #define INTF_MUX 0x25C
  59. #define INTF_STATUS 0x26C
  60. #define INTF_AVR_CONTROL 0x270
  61. #define INTF_AVR_MODE 0x274
  62. #define INTF_AVR_TRIGGER 0x278
  63. #define INTF_AVR_VTOTAL 0x27C
  64. #define INTF_TEAR_MDP_VSYNC_SEL 0x280
  65. #define INTF_TEAR_TEAR_CHECK_EN 0x284
  66. #define INTF_TEAR_SYNC_CONFIG_VSYNC 0x288
  67. #define INTF_TEAR_SYNC_CONFIG_HEIGHT 0x28C
  68. #define INTF_TEAR_SYNC_WRCOUNT 0x290
  69. #define INTF_TEAR_VSYNC_INIT_VAL 0x294
  70. #define INTF_TEAR_INT_COUNT_VAL 0x298
  71. #define INTF_TEAR_SYNC_THRESH 0x29C
  72. #define INTF_TEAR_START_POS 0x2A0
  73. #define INTF_TEAR_RD_PTR_IRQ 0x2A4
  74. #define INTF_TEAR_WR_PTR_IRQ 0x2A8
  75. #define INTF_TEAR_OUT_LINE_COUNT 0x2AC
  76. #define INTF_TEAR_LINE_COUNT 0x2B0
  77. #define INTF_TEAR_AUTOREFRESH_CONFIG 0x2B4
  78. #define INTF_TEAR_TEAR_DETECT_CTRL 0x2B8
  79. #define AVR_CONTINUOUS_MODE 1
  80. #define AVR_ONE_SHOT_MODE 2
  81. static struct sde_intf_cfg *_intf_offset(enum sde_intf intf,
  82. struct sde_mdss_cfg *m,
  83. void __iomem *addr,
  84. struct sde_hw_blk_reg_map *b)
  85. {
  86. int i;
  87. for (i = 0; i < m->intf_count; i++) {
  88. if ((intf == m->intf[i].id) &&
  89. (m->intf[i].type != INTF_NONE)) {
  90. b->base_off = addr;
  91. b->blk_off = m->intf[i].base;
  92. b->length = m->intf[i].len;
  93. b->hwversion = m->hwversion;
  94. b->log_mask = SDE_DBG_MASK_INTF;
  95. return &m->intf[i];
  96. }
  97. }
  98. return ERR_PTR(-EINVAL);
  99. }
  100. static void sde_hw_intf_avr_trigger(struct sde_hw_intf *ctx)
  101. {
  102. struct sde_hw_blk_reg_map *c;
  103. if (!ctx)
  104. return;
  105. c = &ctx->hw;
  106. SDE_REG_WRITE(c, INTF_AVR_TRIGGER, 0x1);
  107. SDE_DEBUG("AVR Triggered\n");
  108. }
  109. static int sde_hw_intf_avr_setup(struct sde_hw_intf *ctx,
  110. const struct intf_timing_params *params,
  111. const struct intf_avr_params *avr_params)
  112. {
  113. struct sde_hw_blk_reg_map *c;
  114. u32 hsync_period, vsync_period;
  115. u32 min_fps, default_fps, diff_fps;
  116. u32 vsync_period_slow;
  117. u32 avr_vtotal;
  118. u32 add_porches;
  119. if (!ctx || !params || !avr_params) {
  120. SDE_ERROR("invalid input parameter(s)\n");
  121. return -EINVAL;
  122. }
  123. c = &ctx->hw;
  124. min_fps = avr_params->min_fps;
  125. default_fps = avr_params->default_fps;
  126. diff_fps = default_fps - min_fps;
  127. hsync_period = params->hsync_pulse_width +
  128. params->h_back_porch + params->width +
  129. params->h_front_porch;
  130. vsync_period = params->vsync_pulse_width +
  131. params->v_back_porch + params->height +
  132. params->v_front_porch;
  133. add_porches = mult_frac(vsync_period, diff_fps, min_fps);
  134. vsync_period_slow = vsync_period + add_porches;
  135. avr_vtotal = vsync_period_slow * hsync_period;
  136. SDE_REG_WRITE(c, INTF_AVR_VTOTAL, avr_vtotal);
  137. return 0;
  138. }
  139. static void sde_hw_intf_avr_ctrl(struct sde_hw_intf *ctx,
  140. const struct intf_avr_params *avr_params)
  141. {
  142. struct sde_hw_blk_reg_map *c;
  143. u32 avr_mode = 0;
  144. u32 avr_ctrl = 0;
  145. if (!ctx || !avr_params)
  146. return;
  147. c = &ctx->hw;
  148. if (avr_params->avr_mode) {
  149. avr_ctrl = BIT(0);
  150. avr_mode = (avr_params->avr_mode == AVR_ONE_SHOT_MODE) ?
  151. (BIT(0) | BIT(8)) : 0x0;
  152. }
  153. SDE_REG_WRITE(c, INTF_AVR_CONTROL, avr_ctrl);
  154. SDE_REG_WRITE(c, INTF_AVR_MODE, avr_mode);
  155. }
  156. static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
  157. const struct intf_timing_params *p,
  158. const struct sde_format *fmt)
  159. {
  160. struct sde_hw_blk_reg_map *c = &ctx->hw;
  161. u32 hsync_period, vsync_period;
  162. u32 display_v_start, display_v_end;
  163. u32 hsync_start_x, hsync_end_x;
  164. u32 active_h_start, active_h_end;
  165. u32 active_v_start, active_v_end;
  166. u32 active_hctl, display_hctl, hsync_ctl;
  167. u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
  168. u32 panel_format;
  169. u32 intf_cfg, intf_cfg2;
  170. u32 display_data_hctl = 0, active_data_hctl = 0;
  171. bool dp_intf = false;
  172. /* read interface_cfg */
  173. intf_cfg = SDE_REG_READ(c, INTF_CONFIG);
  174. hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
  175. p->h_front_porch;
  176. vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
  177. p->v_front_porch;
  178. display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
  179. hsync_period) + p->hsync_skew;
  180. display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
  181. p->hsync_skew - 1;
  182. hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
  183. hsync_end_x = hsync_period - p->h_front_porch - 1;
  184. if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP)
  185. dp_intf = true;
  186. if (p->width != p->xres) {
  187. active_h_start = hsync_start_x;
  188. active_h_end = active_h_start + p->xres - 1;
  189. } else {
  190. active_h_start = 0;
  191. active_h_end = 0;
  192. }
  193. if (p->height != p->yres) {
  194. active_v_start = display_v_start;
  195. active_v_end = active_v_start + (p->yres * hsync_period) - 1;
  196. } else {
  197. active_v_start = 0;
  198. active_v_end = 0;
  199. }
  200. if (active_h_end) {
  201. active_hctl = (active_h_end << 16) | active_h_start;
  202. intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
  203. } else {
  204. active_hctl = 0;
  205. }
  206. if (active_v_end)
  207. intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
  208. hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
  209. display_hctl = (hsync_end_x << 16) | hsync_start_x;
  210. if (dp_intf) {
  211. active_h_start = hsync_start_x;
  212. active_h_end = active_h_start + p->xres - 1;
  213. active_v_start = display_v_start;
  214. active_v_end = active_v_start + (p->yres * hsync_period) - 1;
  215. display_v_start += p->hsync_pulse_width + p->h_back_porch;
  216. active_hctl = (active_h_end << 16) | active_h_start;
  217. display_hctl = active_hctl;
  218. }
  219. intf_cfg2 = 0;
  220. if (dp_intf && p->compression_en) {
  221. active_data_hctl = (hsync_start_x + p->extra_dto_cycles) << 16;
  222. active_data_hctl += hsync_start_x;
  223. display_data_hctl = active_data_hctl;
  224. intf_cfg2 |= BIT(4);
  225. }
  226. den_polarity = 0;
  227. if (ctx->cap->type == INTF_HDMI) {
  228. hsync_polarity = p->yres >= 720 ? 0 : 1;
  229. vsync_polarity = p->yres >= 720 ? 0 : 1;
  230. } else if (ctx->cap->type == INTF_DP) {
  231. hsync_polarity = p->hsync_polarity;
  232. vsync_polarity = p->vsync_polarity;
  233. } else {
  234. hsync_polarity = 0;
  235. vsync_polarity = 0;
  236. }
  237. polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
  238. (vsync_polarity << 1) | /* VSYNC Polarity */
  239. (hsync_polarity << 0); /* HSYNC Polarity */
  240. if (!SDE_FORMAT_IS_YUV(fmt))
  241. panel_format = (fmt->bits[C0_G_Y] |
  242. (fmt->bits[C1_B_Cb] << 2) |
  243. (fmt->bits[C2_R_Cr] << 4) |
  244. (0x21 << 8));
  245. else
  246. /* Interface treats all the pixel data in RGB888 format */
  247. panel_format = (COLOR_8BIT |
  248. (COLOR_8BIT << 2) |
  249. (COLOR_8BIT << 4) |
  250. (0x21 << 8));
  251. if (p->wide_bus_en)
  252. intf_cfg2 |= BIT(0);
  253. SDE_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
  254. SDE_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
  255. SDE_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
  256. p->vsync_pulse_width * hsync_period);
  257. SDE_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
  258. SDE_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
  259. SDE_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
  260. SDE_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
  261. SDE_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
  262. SDE_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
  263. SDE_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
  264. SDE_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
  265. SDE_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
  266. SDE_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
  267. SDE_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
  268. SDE_REG_WRITE(c, INTF_CONFIG, intf_cfg);
  269. SDE_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
  270. SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
  271. SDE_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
  272. SDE_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);
  273. }
  274. static void sde_hw_intf_enable_timing_engine(
  275. struct sde_hw_intf *intf,
  276. u8 enable)
  277. {
  278. struct sde_hw_blk_reg_map *c = &intf->hw;
  279. /* Note: Display interface select is handled in top block hw layer */
  280. SDE_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
  281. }
  282. static void sde_hw_intf_setup_prg_fetch(
  283. struct sde_hw_intf *intf,
  284. const struct intf_prog_fetch *fetch)
  285. {
  286. struct sde_hw_blk_reg_map *c = &intf->hw;
  287. int fetch_enable;
  288. /*
  289. * Fetch should always be outside the active lines. If the fetching
  290. * is programmed within active region, hardware behavior is unknown.
  291. */
  292. fetch_enable = SDE_REG_READ(c, INTF_CONFIG);
  293. if (fetch->enable) {
  294. fetch_enable |= BIT(31);
  295. SDE_REG_WRITE(c, INTF_PROG_FETCH_START,
  296. fetch->fetch_start);
  297. } else {
  298. fetch_enable &= ~BIT(31);
  299. }
  300. SDE_REG_WRITE(c, INTF_CONFIG, fetch_enable);
  301. }
  302. static void sde_hw_intf_bind_pingpong_blk(
  303. struct sde_hw_intf *intf,
  304. bool enable,
  305. const enum sde_pingpong pp)
  306. {
  307. struct sde_hw_blk_reg_map *c;
  308. u32 mux_cfg;
  309. if (!intf)
  310. return;
  311. c = &intf->hw;
  312. mux_cfg = SDE_REG_READ(c, INTF_MUX);
  313. mux_cfg &= ~0xf;
  314. if (enable)
  315. mux_cfg |= (pp - PINGPONG_0) & 0x7;
  316. else
  317. mux_cfg |= 0xf;
  318. SDE_REG_WRITE(c, INTF_MUX, mux_cfg);
  319. }
  320. static void sde_hw_intf_get_status(
  321. struct sde_hw_intf *intf,
  322. struct intf_status *s)
  323. {
  324. struct sde_hw_blk_reg_map *c = &intf->hw;
  325. s->is_en = SDE_REG_READ(c, INTF_TIMING_ENGINE_EN);
  326. if (s->is_en) {
  327. s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
  328. s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT);
  329. } else {
  330. s->line_count = 0;
  331. s->frame_count = 0;
  332. }
  333. }
  334. static void sde_hw_intf_v1_get_status(
  335. struct sde_hw_intf *intf,
  336. struct intf_status *s)
  337. {
  338. struct sde_hw_blk_reg_map *c = &intf->hw;
  339. s->is_en = SDE_REG_READ(c, INTF_STATUS) & BIT(0);
  340. if (s->is_en) {
  341. s->frame_count = SDE_REG_READ(c, INTF_FRAME_COUNT);
  342. s->line_count = SDE_REG_READ(c, INTF_LINE_COUNT);
  343. } else {
  344. s->line_count = 0;
  345. s->frame_count = 0;
  346. }
  347. }
  348. static void sde_hw_intf_setup_misr(struct sde_hw_intf *intf,
  349. bool enable, u32 frame_count)
  350. {
  351. struct sde_hw_blk_reg_map *c = &intf->hw;
  352. u32 config = 0;
  353. SDE_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
  354. /* clear misr data */
  355. wmb();
  356. if (enable)
  357. config = (frame_count & MISR_FRAME_COUNT_MASK) |
  358. MISR_CTRL_ENABLE |
  359. INTF_MISR_CTRL_FREE_RUN_MASK |
  360. INTF_MISR_CTRL_INPUT_SEL_DATA;
  361. SDE_REG_WRITE(c, INTF_MISR_CTRL, config);
  362. }
  363. static int sde_hw_intf_collect_misr(struct sde_hw_intf *intf, bool nonblock,
  364. u32 *misr_value)
  365. {
  366. struct sde_hw_blk_reg_map *c = &intf->hw;
  367. u32 ctrl = 0;
  368. if (!misr_value)
  369. return -EINVAL;
  370. ctrl = SDE_REG_READ(c, INTF_MISR_CTRL);
  371. if (!nonblock) {
  372. if (ctrl & MISR_CTRL_ENABLE) {
  373. int rc;
  374. rc = readl_poll_timeout(c->base_off + c->blk_off +
  375. INTF_MISR_CTRL, ctrl,
  376. (ctrl & MISR_CTRL_STATUS) > 0, 500,
  377. 84000);
  378. if (rc)
  379. return rc;
  380. } else {
  381. return -EINVAL;
  382. }
  383. }
  384. *misr_value = SDE_REG_READ(c, INTF_MISR_SIGNATURE);
  385. return 0;
  386. }
  387. static u32 sde_hw_intf_get_line_count(struct sde_hw_intf *intf)
  388. {
  389. struct sde_hw_blk_reg_map *c;
  390. if (!intf)
  391. return 0;
  392. c = &intf->hw;
  393. return SDE_REG_READ(c, INTF_LINE_COUNT);
  394. }
  395. static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
  396. struct sde_hw_tear_check *te)
  397. {
  398. struct sde_hw_blk_reg_map *c;
  399. int cfg;
  400. if (!intf)
  401. return -EINVAL;
  402. c = &intf->hw;
  403. cfg = BIT(19); /* VSYNC_COUNTER_EN */
  404. if (te->hw_vsync_mode)
  405. cfg |= BIT(20);
  406. cfg |= te->vsync_count;
  407. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  408. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
  409. SDE_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);
  410. SDE_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);
  411. SDE_REG_WRITE(c, INTF_TEAR_WR_PTR_IRQ, te->wr_ptr_irq);
  412. SDE_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);
  413. SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH,
  414. ((te->sync_threshold_continue << 16) |
  415. te->sync_threshold_start));
  416. SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
  417. (te->start_pos + te->sync_threshold_start + 1));
  418. return 0;
  419. }
  420. static int sde_hw_intf_setup_autorefresh_config(struct sde_hw_intf *intf,
  421. struct sde_hw_autorefresh *cfg)
  422. {
  423. struct sde_hw_blk_reg_map *c;
  424. u32 refresh_cfg;
  425. if (!intf || !cfg)
  426. return -EINVAL;
  427. c = &intf->hw;
  428. if (cfg->enable)
  429. refresh_cfg = BIT(31) | cfg->frame_count;
  430. else
  431. refresh_cfg = 0;
  432. SDE_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg);
  433. return 0;
  434. }
  435. static int sde_hw_intf_get_autorefresh_config(struct sde_hw_intf *intf,
  436. struct sde_hw_autorefresh *cfg)
  437. {
  438. struct sde_hw_blk_reg_map *c;
  439. u32 val;
  440. if (!intf || !cfg)
  441. return -EINVAL;
  442. c = &intf->hw;
  443. val = SDE_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG);
  444. cfg->enable = (val & BIT(31)) >> 31;
  445. cfg->frame_count = val & 0xffff;
  446. return 0;
  447. }
  448. static int sde_hw_intf_poll_timeout_wr_ptr(struct sde_hw_intf *intf,
  449. u32 timeout_us)
  450. {
  451. struct sde_hw_blk_reg_map *c;
  452. u32 val;
  453. int rc;
  454. if (!intf)
  455. return -EINVAL;
  456. c = &intf->hw;
  457. rc = readl_poll_timeout(c->base_off + c->blk_off + INTF_TEAR_LINE_COUNT,
  458. val, (val & 0xffff) >= 1, 10, timeout_us);
  459. return rc;
  460. }
  461. static int sde_hw_intf_enable_te(struct sde_hw_intf *intf, bool enable)
  462. {
  463. struct sde_hw_blk_reg_map *c;
  464. if (!intf)
  465. return -EINVAL;
  466. c = &intf->hw;
  467. SDE_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, enable);
  468. return 0;
  469. }
  470. static void sde_hw_intf_update_te(struct sde_hw_intf *intf,
  471. struct sde_hw_tear_check *te)
  472. {
  473. struct sde_hw_blk_reg_map *c;
  474. int cfg;
  475. if (!intf || !te)
  476. return;
  477. c = &intf->hw;
  478. cfg = SDE_REG_READ(c, INTF_TEAR_SYNC_THRESH);
  479. cfg &= ~0xFFFF;
  480. cfg |= te->sync_threshold_start;
  481. SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, cfg);
  482. }
  483. static int sde_hw_intf_connect_external_te(struct sde_hw_intf *intf,
  484. bool enable_external_te)
  485. {
  486. struct sde_hw_blk_reg_map *c = &intf->hw;
  487. u32 cfg;
  488. int orig;
  489. if (!intf)
  490. return -EINVAL;
  491. c = &intf->hw;
  492. cfg = SDE_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC);
  493. orig = (bool)(cfg & BIT(20));
  494. if (enable_external_te)
  495. cfg |= BIT(20);
  496. else
  497. cfg &= ~BIT(20);
  498. SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
  499. return orig;
  500. }
  501. static int sde_hw_intf_get_vsync_info(struct sde_hw_intf *intf,
  502. struct sde_hw_pp_vsync_info *info)
  503. {
  504. struct sde_hw_blk_reg_map *c = &intf->hw;
  505. u32 val;
  506. if (!intf || !info)
  507. return -EINVAL;
  508. c = &intf->hw;
  509. val = SDE_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL);
  510. info->rd_ptr_init_val = val & 0xffff;
  511. val = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);
  512. info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
  513. info->rd_ptr_line_count = val & 0xffff;
  514. val = SDE_REG_READ(c, INTF_TEAR_LINE_COUNT);
  515. info->wr_ptr_line_count = val & 0xffff;
  516. return 0;
  517. }
  518. static void sde_hw_intf_vsync_sel(struct sde_hw_intf *intf,
  519. u32 vsync_source)
  520. {
  521. struct sde_hw_blk_reg_map *c;
  522. if (!intf)
  523. return;
  524. c = &intf->hw;
  525. SDE_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf));
  526. }
  527. static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
  528. unsigned long cap)
  529. {
  530. ops->setup_timing_gen = sde_hw_intf_setup_timing_engine;
  531. ops->setup_prg_fetch = sde_hw_intf_setup_prg_fetch;
  532. ops->get_status = sde_hw_intf_get_status;
  533. ops->enable_timing = sde_hw_intf_enable_timing_engine;
  534. ops->setup_misr = sde_hw_intf_setup_misr;
  535. ops->collect_misr = sde_hw_intf_collect_misr;
  536. ops->get_line_count = sde_hw_intf_get_line_count;
  537. ops->avr_setup = sde_hw_intf_avr_setup;
  538. ops->avr_trigger = sde_hw_intf_avr_trigger;
  539. ops->avr_ctrl = sde_hw_intf_avr_ctrl;
  540. if (cap & BIT(SDE_INTF_INPUT_CTRL))
  541. ops->bind_pingpong_blk = sde_hw_intf_bind_pingpong_blk;
  542. if (cap & BIT(SDE_INTF_TE)) {
  543. ops->setup_tearcheck = sde_hw_intf_setup_te_config;
  544. ops->enable_tearcheck = sde_hw_intf_enable_te;
  545. ops->update_tearcheck = sde_hw_intf_update_te;
  546. ops->connect_external_te = sde_hw_intf_connect_external_te;
  547. ops->get_vsync_info = sde_hw_intf_get_vsync_info;
  548. ops->setup_autorefresh = sde_hw_intf_setup_autorefresh_config;
  549. ops->get_autorefresh = sde_hw_intf_get_autorefresh_config;
  550. ops->poll_timeout_wr_ptr = sde_hw_intf_poll_timeout_wr_ptr;
  551. ops->vsync_sel = sde_hw_intf_vsync_sel;
  552. ops->get_status = sde_hw_intf_v1_get_status;
  553. }
  554. }
  555. static struct sde_hw_blk_ops sde_hw_ops = {
  556. .start = NULL,
  557. .stop = NULL,
  558. };
  559. struct sde_hw_intf *sde_hw_intf_init(enum sde_intf idx,
  560. void __iomem *addr,
  561. struct sde_mdss_cfg *m)
  562. {
  563. struct sde_hw_intf *c;
  564. struct sde_intf_cfg *cfg;
  565. int rc;
  566. c = kzalloc(sizeof(*c), GFP_KERNEL);
  567. if (!c)
  568. return ERR_PTR(-ENOMEM);
  569. cfg = _intf_offset(idx, m, addr, &c->hw);
  570. if (IS_ERR_OR_NULL(cfg)) {
  571. kfree(c);
  572. pr_err("failed to create sde_hw_intf %d\n", idx);
  573. return ERR_PTR(-EINVAL);
  574. }
  575. /*
  576. * Assign ops
  577. */
  578. c->idx = idx;
  579. c->cap = cfg;
  580. c->mdss = m;
  581. _setup_intf_ops(&c->ops, c->cap->features);
  582. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_INTF, idx, &sde_hw_ops);
  583. if (rc) {
  584. SDE_ERROR("failed to init hw blk %d\n", rc);
  585. goto blk_init_error;
  586. }
  587. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  588. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  589. return c;
  590. blk_init_error:
  591. kzfree(c);
  592. return ERR_PTR(rc);
  593. }
  594. void sde_hw_intf_destroy(struct sde_hw_intf *intf)
  595. {
  596. if (intf)
  597. sde_hw_blk_destroy(&intf->base);
  598. kfree(intf);
  599. }