qcs405.c 215 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <sound/core.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/info.h>
  30. #include <dsp/audio_notifier.h>
  31. #include <dsp/q6afe-v2.h>
  32. #include <dsp/q6core.h>
  33. #include "device_event.h"
  34. #include "msm-pcm-routing-v2.h"
  35. #include "codecs/msm-cdc-pinctrl.h"
  36. #include "codecs/wcd9335.h"
  37. #include "codecs/wsa881x.h"
  38. #include "codecs/csra66x0/csra66x0.h"
  39. #include <dt-bindings/sound/audio-codec-port-types.h>
  40. #include "codecs/bolero/bolero-cdc.h"
  41. #include "codecs/bolero/wsa-macro.h"
  42. #define DRV_NAME "qcs405-asoc-snd"
  43. #define __CHIPSET__ "QCS405 "
  44. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  45. #define DEV_NAME_STR_LEN 32
  46. #define SAMPLING_RATE_8KHZ 8000
  47. #define SAMPLING_RATE_11P025KHZ 11025
  48. #define SAMPLING_RATE_16KHZ 16000
  49. #define SAMPLING_RATE_22P05KHZ 22050
  50. #define SAMPLING_RATE_32KHZ 32000
  51. #define SAMPLING_RATE_44P1KHZ 44100
  52. #define SAMPLING_RATE_48KHZ 48000
  53. #define SAMPLING_RATE_88P2KHZ 88200
  54. #define SAMPLING_RATE_96KHZ 96000
  55. #define SAMPLING_RATE_176P4KHZ 176400
  56. #define SAMPLING_RATE_192KHZ 192000
  57. #define SAMPLING_RATE_352P8KHZ 352800
  58. #define SAMPLING_RATE_384KHZ 384000
  59. #define WSA8810_NAME_1 "wsa881x.20170211"
  60. #define WSA8810_NAME_2 "wsa881x.20170212"
  61. #define WCN_CDC_SLIM_RX_CH_MAX 2
  62. #define WCN_CDC_SLIM_TX_CH_MAX 3
  63. #define TDM_CHANNEL_MAX 8
  64. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  65. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  66. enum {
  67. SLIM_RX_0 = 0,
  68. SLIM_RX_1,
  69. SLIM_RX_2,
  70. SLIM_RX_3,
  71. SLIM_RX_4,
  72. SLIM_RX_5,
  73. SLIM_RX_6,
  74. SLIM_RX_7,
  75. SLIM_RX_MAX,
  76. };
  77. enum {
  78. SLIM_TX_0 = 0,
  79. SLIM_TX_1,
  80. SLIM_TX_2,
  81. SLIM_TX_3,
  82. SLIM_TX_4,
  83. SLIM_TX_5,
  84. SLIM_TX_6,
  85. SLIM_TX_7,
  86. SLIM_TX_8,
  87. SLIM_TX_MAX,
  88. };
  89. enum {
  90. PRIM_MI2S = 0,
  91. SEC_MI2S,
  92. TERT_MI2S,
  93. QUAT_MI2S,
  94. QUIN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. AUX_PCM_MAX,
  104. };
  105. enum {
  106. WSA_CDC_DMA_RX_0 = 0,
  107. WSA_CDC_DMA_RX_1,
  108. CDC_DMA_RX_MAX,
  109. };
  110. enum {
  111. WSA_CDC_DMA_TX_0 = 0,
  112. WSA_CDC_DMA_TX_1,
  113. WSA_CDC_DMA_TX_2,
  114. VA_CDC_DMA_TX_0,
  115. VA_CDC_DMA_TX_1,
  116. CDC_DMA_TX_MAX,
  117. };
  118. struct mi2s_conf {
  119. struct mutex lock;
  120. u32 ref_cnt;
  121. u32 msm_is_mi2s_master;
  122. };
  123. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  124. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  125. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  126. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  127. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  128. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  129. };
  130. struct dev_config {
  131. u32 sample_rate;
  132. u32 bit_format;
  133. u32 channels;
  134. };
  135. struct msm_wsa881x_dev_info {
  136. struct device_node *of_node;
  137. u32 index;
  138. };
  139. struct msm_csra66x0_dev_info {
  140. struct device_node *of_node;
  141. u32 index;
  142. };
  143. enum pinctrl_pin_state {
  144. STATE_DISABLE = 0, /* All pins are in sleep state */
  145. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  146. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  147. };
  148. struct msm_pinctrl_info {
  149. struct pinctrl *pinctrl;
  150. struct pinctrl_state *mi2s_disable;
  151. struct pinctrl_state *tdm_disable;
  152. struct pinctrl_state *mi2s_active;
  153. struct pinctrl_state *tdm_active;
  154. enum pinctrl_pin_state curr_state;
  155. };
  156. struct msm_asoc_mach_data {
  157. struct snd_info_entry *codec_root;
  158. struct msm_pinctrl_info pinctrl_info;
  159. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  161. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  162. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  163. int dmic_01_gpio_cnt;
  164. int dmic_23_gpio_cnt;
  165. int dmic_45_gpio_cnt;
  166. int dmic_67_gpio_cnt;
  167. };
  168. struct msm_asoc_wcd93xx_codec {
  169. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  170. enum afe_config_type config_type);
  171. };
  172. static const char *const pin_states[] = {"sleep", "i2s-active",
  173. "tdm-active"};
  174. enum {
  175. TDM_0 = 0,
  176. TDM_1,
  177. TDM_2,
  178. TDM_3,
  179. TDM_4,
  180. TDM_5,
  181. TDM_6,
  182. TDM_7,
  183. TDM_PORT_MAX,
  184. };
  185. enum {
  186. TDM_PRI = 0,
  187. TDM_SEC,
  188. TDM_TERT,
  189. TDM_QUAT,
  190. TDM_QUIN,
  191. TDM_INTERFACE_MAX,
  192. };
  193. struct tdm_port {
  194. u32 mode;
  195. u32 channel;
  196. };
  197. /* TDM default config */
  198. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  199. { /* PRI TDM */
  200. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  208. },
  209. { /* SEC TDM */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  218. },
  219. { /* TERT TDM */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  228. },
  229. { /* QUAT TDM */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  238. },
  239. { /* QUIN TDM */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  248. }
  249. };
  250. /* TDM default config */
  251. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  252. { /* PRI TDM */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  261. },
  262. { /* SEC TDM */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  271. },
  272. { /* TERT TDM */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  281. },
  282. { /* QUAT TDM */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  291. },
  292. { /* QUIN TDM */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  301. }
  302. };
  303. /* Default configuration of slimbus channels */
  304. static struct dev_config slim_rx_cfg[] = {
  305. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  306. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. };
  314. static struct dev_config slim_tx_cfg[] = {
  315. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  324. };
  325. /* Default configuration of Codec DMA Interface Tx */
  326. static struct dev_config cdc_dma_rx_cfg[] = {
  327. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  329. };
  330. /* Default configuration of Codec DMA Interface Rx */
  331. static struct dev_config cdc_dma_tx_cfg[] = {
  332. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  335. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  336. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  337. };
  338. static struct dev_config usb_rx_cfg = {
  339. .sample_rate = SAMPLING_RATE_48KHZ,
  340. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  341. .channels = 2,
  342. };
  343. static struct dev_config usb_tx_cfg = {
  344. .sample_rate = SAMPLING_RATE_48KHZ,
  345. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  346. .channels = 1,
  347. };
  348. static struct dev_config proxy_rx_cfg = {
  349. .sample_rate = SAMPLING_RATE_48KHZ,
  350. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  351. .channels = 2,
  352. };
  353. /* Default configuration of MI2S channels */
  354. static struct dev_config mi2s_rx_cfg[] = {
  355. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  357. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  358. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  359. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  360. };
  361. static struct dev_config mi2s_tx_cfg[] = {
  362. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  365. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  366. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  367. };
  368. static struct dev_config aux_pcm_rx_cfg[] = {
  369. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  372. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  373. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  374. };
  375. static struct dev_config aux_pcm_tx_cfg[] = {
  376. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. };
  382. static int msm_vi_feed_tx_ch = 2;
  383. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  384. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  385. "Five", "Six", "Seven",
  386. "Eight"};
  387. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  388. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  389. "S32_LE"};
  390. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  391. "KHZ_32", "KHZ_44P1", "KHZ_48",
  392. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  393. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  394. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  395. "KHZ_44P1", "KHZ_48",
  396. "KHZ_88P2", "KHZ_96"};
  397. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  398. "Five", "Six", "Seven",
  399. "Eight"};
  400. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  401. "Six", "Seven", "Eight"};
  402. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  403. "KHZ_16", "KHZ_22P05",
  404. "KHZ_32", "KHZ_44P1", "KHZ_48",
  405. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  406. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  407. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  408. "Five", "Six", "Seven", "Eight"};
  409. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  410. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  411. "KHZ_48", "KHZ_176P4",
  412. "KHZ_352P8"};
  413. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  414. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  415. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  416. "KHZ_48", "KHZ_96", "KHZ_192"};
  417. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  418. "Five", "Six", "Seven",
  419. "Eight"};
  420. static const char *const qos_text[] = {"Disable", "Enable"};
  421. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  422. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  423. "Five", "Six", "Seven",
  424. "Eight"};
  425. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  426. "KHZ_16", "KHZ_22P05",
  427. "KHZ_32", "KHZ_44P1", "KHZ_48",
  428. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  429. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  508. cdc_dma_sample_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  510. cdc_dma_sample_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  512. cdc_dma_sample_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  514. cdc_dma_sample_rate_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  516. cdc_dma_sample_rate_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  518. cdc_dma_sample_rate_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  520. cdc_dma_sample_rate_text);
  521. static struct platform_device *spdev;
  522. static bool is_initial_boot;
  523. static bool codec_reg_done;
  524. static struct snd_soc_aux_dev *msm_aux_dev;
  525. static struct snd_soc_codec_conf *msm_codec_conf;
  526. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  527. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  528. int enable, bool dapm);
  529. static int msm_wsa881x_init(struct snd_soc_component *component);
  530. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  531. struct snd_ctl_elem_value *ucontrol);
  532. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  533. {"MIC BIAS1", NULL, "MCLK TX"},
  534. {"MIC BIAS2", NULL, "MCLK TX"},
  535. {"MIC BIAS3", NULL, "MCLK TX"},
  536. {"MIC BIAS4", NULL, "MCLK TX"},
  537. };
  538. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  539. {
  540. AFE_API_VERSION_I2S_CONFIG,
  541. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  542. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  543. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  544. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  545. 0,
  546. },
  547. {
  548. AFE_API_VERSION_I2S_CONFIG,
  549. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  550. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  551. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  552. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  553. 0,
  554. },
  555. {
  556. AFE_API_VERSION_I2S_CONFIG,
  557. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  558. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  559. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  560. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  561. 0,
  562. },
  563. {
  564. AFE_API_VERSION_I2S_CONFIG,
  565. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  566. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  567. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  568. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  569. 0,
  570. },
  571. {
  572. AFE_API_VERSION_I2S_CONFIG,
  573. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  574. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  575. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  576. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  577. 0,
  578. }
  579. };
  580. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  581. static int slim_get_sample_rate_val(int sample_rate)
  582. {
  583. int sample_rate_val = 0;
  584. switch (sample_rate) {
  585. case SAMPLING_RATE_8KHZ:
  586. sample_rate_val = 0;
  587. break;
  588. case SAMPLING_RATE_16KHZ:
  589. sample_rate_val = 1;
  590. break;
  591. case SAMPLING_RATE_32KHZ:
  592. sample_rate_val = 2;
  593. break;
  594. case SAMPLING_RATE_44P1KHZ:
  595. sample_rate_val = 3;
  596. break;
  597. case SAMPLING_RATE_48KHZ:
  598. sample_rate_val = 4;
  599. break;
  600. case SAMPLING_RATE_88P2KHZ:
  601. sample_rate_val = 5;
  602. break;
  603. case SAMPLING_RATE_96KHZ:
  604. sample_rate_val = 6;
  605. break;
  606. case SAMPLING_RATE_176P4KHZ:
  607. sample_rate_val = 7;
  608. break;
  609. case SAMPLING_RATE_192KHZ:
  610. sample_rate_val = 8;
  611. break;
  612. case SAMPLING_RATE_352P8KHZ:
  613. sample_rate_val = 9;
  614. break;
  615. case SAMPLING_RATE_384KHZ:
  616. sample_rate_val = 10;
  617. break;
  618. default:
  619. sample_rate_val = 4;
  620. break;
  621. }
  622. return sample_rate_val;
  623. }
  624. static int slim_get_sample_rate(int value)
  625. {
  626. int sample_rate = 0;
  627. switch (value) {
  628. case 0:
  629. sample_rate = SAMPLING_RATE_8KHZ;
  630. break;
  631. case 1:
  632. sample_rate = SAMPLING_RATE_16KHZ;
  633. break;
  634. case 2:
  635. sample_rate = SAMPLING_RATE_32KHZ;
  636. break;
  637. case 3:
  638. sample_rate = SAMPLING_RATE_44P1KHZ;
  639. break;
  640. case 4:
  641. sample_rate = SAMPLING_RATE_48KHZ;
  642. break;
  643. case 5:
  644. sample_rate = SAMPLING_RATE_88P2KHZ;
  645. break;
  646. case 6:
  647. sample_rate = SAMPLING_RATE_96KHZ;
  648. break;
  649. case 7:
  650. sample_rate = SAMPLING_RATE_176P4KHZ;
  651. break;
  652. case 8:
  653. sample_rate = SAMPLING_RATE_192KHZ;
  654. break;
  655. case 9:
  656. sample_rate = SAMPLING_RATE_352P8KHZ;
  657. break;
  658. case 10:
  659. sample_rate = SAMPLING_RATE_384KHZ;
  660. break;
  661. default:
  662. sample_rate = SAMPLING_RATE_48KHZ;
  663. break;
  664. }
  665. return sample_rate;
  666. }
  667. static int slim_get_bit_format_val(int bit_format)
  668. {
  669. int val = 0;
  670. switch (bit_format) {
  671. case SNDRV_PCM_FORMAT_S32_LE:
  672. val = 3;
  673. break;
  674. case SNDRV_PCM_FORMAT_S24_3LE:
  675. val = 2;
  676. break;
  677. case SNDRV_PCM_FORMAT_S24_LE:
  678. val = 1;
  679. break;
  680. case SNDRV_PCM_FORMAT_S16_LE:
  681. default:
  682. val = 0;
  683. break;
  684. }
  685. return val;
  686. }
  687. static int slim_get_bit_format(int val)
  688. {
  689. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  690. switch (val) {
  691. case 0:
  692. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  693. break;
  694. case 1:
  695. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  696. break;
  697. case 2:
  698. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  699. break;
  700. case 3:
  701. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  702. break;
  703. default:
  704. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  705. break;
  706. }
  707. return bit_fmt;
  708. }
  709. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  710. {
  711. int port_id = 0;
  712. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  713. port_id = SLIM_RX_0;
  714. } else if (strnstr(kcontrol->id.name,
  715. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  716. port_id = SLIM_RX_2;
  717. } else if (strnstr(kcontrol->id.name,
  718. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  719. port_id = SLIM_RX_5;
  720. } else if (strnstr(kcontrol->id.name,
  721. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  722. port_id = SLIM_RX_6;
  723. } else if (strnstr(kcontrol->id.name,
  724. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  725. port_id = SLIM_TX_0;
  726. } else if (strnstr(kcontrol->id.name,
  727. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  728. port_id = SLIM_TX_1;
  729. } else {
  730. pr_err("%s: unsupported channel: %s",
  731. __func__, kcontrol->id.name);
  732. return -EINVAL;
  733. }
  734. return port_id;
  735. }
  736. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  737. struct snd_ctl_elem_value *ucontrol)
  738. {
  739. int ch_num = slim_get_port_idx(kcontrol);
  740. if (ch_num < 0)
  741. return ch_num;
  742. ucontrol->value.enumerated.item[0] =
  743. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  744. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  745. ch_num, slim_rx_cfg[ch_num].sample_rate,
  746. ucontrol->value.enumerated.item[0]);
  747. return 0;
  748. }
  749. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  750. struct snd_ctl_elem_value *ucontrol)
  751. {
  752. int ch_num = slim_get_port_idx(kcontrol);
  753. if (ch_num < 0)
  754. return ch_num;
  755. slim_rx_cfg[ch_num].sample_rate =
  756. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  757. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  758. ch_num, slim_rx_cfg[ch_num].sample_rate,
  759. ucontrol->value.enumerated.item[0]);
  760. return 0;
  761. }
  762. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  763. struct snd_ctl_elem_value *ucontrol)
  764. {
  765. int ch_num = slim_get_port_idx(kcontrol);
  766. if (ch_num < 0)
  767. return ch_num;
  768. ucontrol->value.enumerated.item[0] =
  769. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  770. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  771. ch_num, slim_tx_cfg[ch_num].sample_rate,
  772. ucontrol->value.enumerated.item[0]);
  773. return 0;
  774. }
  775. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  776. struct snd_ctl_elem_value *ucontrol)
  777. {
  778. int sample_rate = 0;
  779. int ch_num = slim_get_port_idx(kcontrol);
  780. if (ch_num < 0)
  781. return ch_num;
  782. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  783. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  784. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  785. __func__, sample_rate);
  786. return -EINVAL;
  787. }
  788. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  789. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  790. ch_num, slim_tx_cfg[ch_num].sample_rate,
  791. ucontrol->value.enumerated.item[0]);
  792. return 0;
  793. }
  794. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  795. struct snd_ctl_elem_value *ucontrol)
  796. {
  797. int ch_num = slim_get_port_idx(kcontrol);
  798. if (ch_num < 0)
  799. return ch_num;
  800. ucontrol->value.enumerated.item[0] =
  801. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  802. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  803. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  804. ucontrol->value.enumerated.item[0]);
  805. return 0;
  806. }
  807. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  808. struct snd_ctl_elem_value *ucontrol)
  809. {
  810. int ch_num = slim_get_port_idx(kcontrol);
  811. if (ch_num < 0)
  812. return ch_num;
  813. slim_rx_cfg[ch_num].bit_format =
  814. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  815. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  816. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  817. ucontrol->value.enumerated.item[0]);
  818. return 0;
  819. }
  820. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  821. struct snd_ctl_elem_value *ucontrol)
  822. {
  823. int ch_num = slim_get_port_idx(kcontrol);
  824. if (ch_num < 0)
  825. return ch_num;
  826. ucontrol->value.enumerated.item[0] =
  827. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  828. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  829. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  830. ucontrol->value.enumerated.item[0]);
  831. return 0;
  832. }
  833. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  834. struct snd_ctl_elem_value *ucontrol)
  835. {
  836. int ch_num = slim_get_port_idx(kcontrol);
  837. if (ch_num < 0)
  838. return ch_num;
  839. slim_tx_cfg[ch_num].bit_format =
  840. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  841. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  842. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  843. ucontrol->value.enumerated.item[0]);
  844. return 0;
  845. }
  846. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  847. struct snd_ctl_elem_value *ucontrol)
  848. {
  849. int ch_num = slim_get_port_idx(kcontrol);
  850. if (ch_num < 0)
  851. return ch_num;
  852. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  853. ch_num, slim_rx_cfg[ch_num].channels);
  854. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  855. return 0;
  856. }
  857. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  858. struct snd_ctl_elem_value *ucontrol)
  859. {
  860. int ch_num = slim_get_port_idx(kcontrol);
  861. if (ch_num < 0)
  862. return ch_num;
  863. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  864. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  865. ch_num, slim_rx_cfg[ch_num].channels);
  866. return 1;
  867. }
  868. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  869. struct snd_ctl_elem_value *ucontrol)
  870. {
  871. int ch_num = slim_get_port_idx(kcontrol);
  872. if (ch_num < 0)
  873. return ch_num;
  874. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  875. ch_num, slim_tx_cfg[ch_num].channels);
  876. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  877. return 0;
  878. }
  879. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  880. struct snd_ctl_elem_value *ucontrol)
  881. {
  882. int ch_num = slim_get_port_idx(kcontrol);
  883. if (ch_num < 0)
  884. return ch_num;
  885. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  886. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  887. ch_num, slim_tx_cfg[ch_num].channels);
  888. return 1;
  889. }
  890. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  891. struct snd_ctl_elem_value *ucontrol)
  892. {
  893. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  894. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  895. ucontrol->value.integer.value[0]);
  896. return 0;
  897. }
  898. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  899. struct snd_ctl_elem_value *ucontrol)
  900. {
  901. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  902. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  903. return 1;
  904. }
  905. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  906. struct snd_ctl_elem_value *ucontrol)
  907. {
  908. /*
  909. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  910. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  911. * value.
  912. */
  913. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  914. case SAMPLING_RATE_96KHZ:
  915. ucontrol->value.integer.value[0] = 5;
  916. break;
  917. case SAMPLING_RATE_88P2KHZ:
  918. ucontrol->value.integer.value[0] = 4;
  919. break;
  920. case SAMPLING_RATE_48KHZ:
  921. ucontrol->value.integer.value[0] = 3;
  922. break;
  923. case SAMPLING_RATE_44P1KHZ:
  924. ucontrol->value.integer.value[0] = 2;
  925. break;
  926. case SAMPLING_RATE_16KHZ:
  927. ucontrol->value.integer.value[0] = 1;
  928. break;
  929. case SAMPLING_RATE_8KHZ:
  930. default:
  931. ucontrol->value.integer.value[0] = 0;
  932. break;
  933. }
  934. pr_debug("%s: sample rate = %d", __func__,
  935. slim_rx_cfg[SLIM_RX_7].sample_rate);
  936. return 0;
  937. }
  938. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  939. struct snd_ctl_elem_value *ucontrol)
  940. {
  941. switch (ucontrol->value.integer.value[0]) {
  942. case 1:
  943. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  944. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  945. break;
  946. case 2:
  947. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  948. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  949. break;
  950. case 3:
  951. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  952. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  953. break;
  954. case 4:
  955. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  956. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  957. break;
  958. case 5:
  959. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  960. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  961. break;
  962. case 0:
  963. default:
  964. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  965. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  966. break;
  967. }
  968. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  969. __func__,
  970. slim_rx_cfg[SLIM_RX_7].sample_rate,
  971. slim_tx_cfg[SLIM_TX_7].sample_rate,
  972. ucontrol->value.enumerated.item[0]);
  973. return 0;
  974. }
  975. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  976. {
  977. int idx = 0;
  978. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  979. sizeof("WSA_CDC_DMA_RX_0")))
  980. idx = WSA_CDC_DMA_RX_0;
  981. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  982. sizeof("WSA_CDC_DMA_RX_0")))
  983. idx = WSA_CDC_DMA_RX_1;
  984. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  985. sizeof("WSA_CDC_DMA_TX_0")))
  986. idx = WSA_CDC_DMA_TX_0;
  987. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  988. sizeof("WSA_CDC_DMA_TX_1")))
  989. idx = WSA_CDC_DMA_TX_1;
  990. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  991. sizeof("WSA_CDC_DMA_TX_2")))
  992. idx = WSA_CDC_DMA_TX_2;
  993. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  994. sizeof("VA_CDC_DMA_TX_0")))
  995. idx = VA_CDC_DMA_TX_0;
  996. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  997. sizeof("VA_CDC_DMA_TX_1")))
  998. idx = VA_CDC_DMA_TX_1;
  999. else {
  1000. pr_err("%s: unsupported port: %s\n",
  1001. __func__, kcontrol->id.name);
  1002. return -EINVAL;
  1003. }
  1004. return idx;
  1005. }
  1006. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1007. struct snd_ctl_elem_value *ucontrol)
  1008. {
  1009. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1010. if (ch_num < 0)
  1011. return ch_num;
  1012. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1013. cdc_dma_rx_cfg[ch_num].channels - 1);
  1014. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1015. return 0;
  1016. }
  1017. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1018. struct snd_ctl_elem_value *ucontrol)
  1019. {
  1020. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1021. if (ch_num < 0)
  1022. return ch_num;
  1023. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1024. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1025. cdc_dma_rx_cfg[ch_num].channels);
  1026. return 1;
  1027. }
  1028. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1029. struct snd_ctl_elem_value *ucontrol)
  1030. {
  1031. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1032. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1033. case SNDRV_PCM_FORMAT_S32_LE:
  1034. ucontrol->value.integer.value[0] = 3;
  1035. break;
  1036. case SNDRV_PCM_FORMAT_S24_3LE:
  1037. ucontrol->value.integer.value[0] = 2;
  1038. break;
  1039. case SNDRV_PCM_FORMAT_S24_LE:
  1040. ucontrol->value.integer.value[0] = 1;
  1041. break;
  1042. case SNDRV_PCM_FORMAT_S16_LE:
  1043. default:
  1044. ucontrol->value.integer.value[0] = 0;
  1045. break;
  1046. }
  1047. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1048. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1049. ucontrol->value.integer.value[0]);
  1050. return 0;
  1051. }
  1052. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1053. struct snd_ctl_elem_value *ucontrol)
  1054. {
  1055. int rc = 0;
  1056. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1057. switch (ucontrol->value.integer.value[0]) {
  1058. case 3:
  1059. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1060. break;
  1061. case 2:
  1062. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1063. break;
  1064. case 1:
  1065. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1066. break;
  1067. case 0:
  1068. default:
  1069. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1070. break;
  1071. }
  1072. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1073. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1074. ucontrol->value.integer.value[0]);
  1075. return rc;
  1076. }
  1077. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1078. {
  1079. int sample_rate_val = 0;
  1080. switch (sample_rate) {
  1081. case SAMPLING_RATE_8KHZ:
  1082. sample_rate_val = 0;
  1083. break;
  1084. case SAMPLING_RATE_16KHZ:
  1085. sample_rate_val = 1;
  1086. break;
  1087. case SAMPLING_RATE_32KHZ:
  1088. sample_rate_val = 2;
  1089. break;
  1090. case SAMPLING_RATE_44P1KHZ:
  1091. sample_rate_val = 3;
  1092. break;
  1093. case SAMPLING_RATE_48KHZ:
  1094. sample_rate_val = 4;
  1095. break;
  1096. case SAMPLING_RATE_88P2KHZ:
  1097. sample_rate_val = 5;
  1098. break;
  1099. case SAMPLING_RATE_96KHZ:
  1100. sample_rate_val = 6;
  1101. break;
  1102. case SAMPLING_RATE_176P4KHZ:
  1103. sample_rate_val = 7;
  1104. break;
  1105. case SAMPLING_RATE_192KHZ:
  1106. sample_rate_val = 8;
  1107. break;
  1108. case SAMPLING_RATE_352P8KHZ:
  1109. sample_rate_val = 9;
  1110. break;
  1111. case SAMPLING_RATE_384KHZ:
  1112. sample_rate_val = 10;
  1113. break;
  1114. default:
  1115. sample_rate_val = 4;
  1116. break;
  1117. }
  1118. return sample_rate_val;
  1119. }
  1120. static int cdc_dma_get_sample_rate(int value)
  1121. {
  1122. int sample_rate = 0;
  1123. switch (value) {
  1124. case 0:
  1125. sample_rate = SAMPLING_RATE_8KHZ;
  1126. break;
  1127. case 1:
  1128. sample_rate = SAMPLING_RATE_16KHZ;
  1129. break;
  1130. case 2:
  1131. sample_rate = SAMPLING_RATE_32KHZ;
  1132. break;
  1133. case 3:
  1134. sample_rate = SAMPLING_RATE_44P1KHZ;
  1135. break;
  1136. case 4:
  1137. sample_rate = SAMPLING_RATE_48KHZ;
  1138. break;
  1139. case 5:
  1140. sample_rate = SAMPLING_RATE_88P2KHZ;
  1141. break;
  1142. case 6:
  1143. sample_rate = SAMPLING_RATE_96KHZ;
  1144. break;
  1145. case 7:
  1146. sample_rate = SAMPLING_RATE_176P4KHZ;
  1147. break;
  1148. case 8:
  1149. sample_rate = SAMPLING_RATE_192KHZ;
  1150. break;
  1151. case 9:
  1152. sample_rate = SAMPLING_RATE_352P8KHZ;
  1153. break;
  1154. case 10:
  1155. sample_rate = SAMPLING_RATE_384KHZ;
  1156. break;
  1157. default:
  1158. sample_rate = SAMPLING_RATE_48KHZ;
  1159. break;
  1160. }
  1161. return sample_rate;
  1162. }
  1163. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1164. struct snd_ctl_elem_value *ucontrol)
  1165. {
  1166. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1167. if (ch_num < 0)
  1168. return ch_num;
  1169. ucontrol->value.enumerated.item[0] =
  1170. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1171. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1172. cdc_dma_rx_cfg[ch_num].sample_rate);
  1173. return 0;
  1174. }
  1175. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1176. struct snd_ctl_elem_value *ucontrol)
  1177. {
  1178. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1179. if (ch_num < 0)
  1180. return ch_num;
  1181. cdc_dma_rx_cfg[ch_num].sample_rate =
  1182. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1183. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1184. __func__, ucontrol->value.enumerated.item[0],
  1185. cdc_dma_rx_cfg[ch_num].sample_rate);
  1186. return 0;
  1187. }
  1188. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1189. struct snd_ctl_elem_value *ucontrol)
  1190. {
  1191. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1192. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1193. cdc_dma_tx_cfg[ch_num].channels);
  1194. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1195. return 0;
  1196. }
  1197. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1198. struct snd_ctl_elem_value *ucontrol)
  1199. {
  1200. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1201. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1202. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1203. cdc_dma_tx_cfg[ch_num].channels);
  1204. return 1;
  1205. }
  1206. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1207. struct snd_ctl_elem_value *ucontrol)
  1208. {
  1209. int sample_rate_val;
  1210. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1211. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1212. case SAMPLING_RATE_384KHZ:
  1213. sample_rate_val = 12;
  1214. break;
  1215. case SAMPLING_RATE_352P8KHZ:
  1216. sample_rate_val = 11;
  1217. break;
  1218. case SAMPLING_RATE_192KHZ:
  1219. sample_rate_val = 10;
  1220. break;
  1221. case SAMPLING_RATE_176P4KHZ:
  1222. sample_rate_val = 9;
  1223. break;
  1224. case SAMPLING_RATE_96KHZ:
  1225. sample_rate_val = 8;
  1226. break;
  1227. case SAMPLING_RATE_88P2KHZ:
  1228. sample_rate_val = 7;
  1229. break;
  1230. case SAMPLING_RATE_48KHZ:
  1231. sample_rate_val = 6;
  1232. break;
  1233. case SAMPLING_RATE_44P1KHZ:
  1234. sample_rate_val = 5;
  1235. break;
  1236. case SAMPLING_RATE_32KHZ:
  1237. sample_rate_val = 4;
  1238. break;
  1239. case SAMPLING_RATE_22P05KHZ:
  1240. sample_rate_val = 3;
  1241. break;
  1242. case SAMPLING_RATE_16KHZ:
  1243. sample_rate_val = 2;
  1244. break;
  1245. case SAMPLING_RATE_11P025KHZ:
  1246. sample_rate_val = 1;
  1247. break;
  1248. case SAMPLING_RATE_8KHZ:
  1249. sample_rate_val = 0;
  1250. break;
  1251. default:
  1252. sample_rate_val = 6;
  1253. break;
  1254. }
  1255. ucontrol->value.integer.value[0] = sample_rate_val;
  1256. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1257. cdc_dma_tx_cfg[ch_num].sample_rate);
  1258. return 0;
  1259. }
  1260. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1261. struct snd_ctl_elem_value *ucontrol)
  1262. {
  1263. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1264. switch (ucontrol->value.integer.value[0]) {
  1265. case 12:
  1266. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1267. break;
  1268. case 11:
  1269. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1270. break;
  1271. case 10:
  1272. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1273. break;
  1274. case 9:
  1275. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1276. break;
  1277. case 8:
  1278. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1279. break;
  1280. case 7:
  1281. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1282. break;
  1283. case 6:
  1284. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1285. break;
  1286. case 5:
  1287. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1288. break;
  1289. case 4:
  1290. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1291. break;
  1292. case 3:
  1293. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1294. break;
  1295. case 2:
  1296. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1297. break;
  1298. case 1:
  1299. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1300. break;
  1301. case 0:
  1302. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1303. break;
  1304. default:
  1305. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1306. break;
  1307. }
  1308. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1309. __func__, ucontrol->value.integer.value[0],
  1310. cdc_dma_tx_cfg[ch_num].sample_rate);
  1311. return 0;
  1312. }
  1313. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1314. struct snd_ctl_elem_value *ucontrol)
  1315. {
  1316. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1317. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1318. case SNDRV_PCM_FORMAT_S32_LE:
  1319. ucontrol->value.integer.value[0] = 3;
  1320. break;
  1321. case SNDRV_PCM_FORMAT_S24_3LE:
  1322. ucontrol->value.integer.value[0] = 2;
  1323. break;
  1324. case SNDRV_PCM_FORMAT_S24_LE:
  1325. ucontrol->value.integer.value[0] = 1;
  1326. break;
  1327. case SNDRV_PCM_FORMAT_S16_LE:
  1328. default:
  1329. ucontrol->value.integer.value[0] = 0;
  1330. break;
  1331. }
  1332. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1333. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1334. ucontrol->value.integer.value[0]);
  1335. return 0;
  1336. }
  1337. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1338. struct snd_ctl_elem_value *ucontrol)
  1339. {
  1340. int rc = 0;
  1341. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1342. switch (ucontrol->value.integer.value[0]) {
  1343. case 3:
  1344. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1345. break;
  1346. case 2:
  1347. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1348. break;
  1349. case 1:
  1350. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1351. break;
  1352. case 0:
  1353. default:
  1354. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1355. break;
  1356. }
  1357. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1358. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1359. ucontrol->value.integer.value[0]);
  1360. return rc;
  1361. }
  1362. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1363. struct snd_ctl_elem_value *ucontrol)
  1364. {
  1365. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1366. usb_rx_cfg.channels);
  1367. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1368. return 0;
  1369. }
  1370. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1371. struct snd_ctl_elem_value *ucontrol)
  1372. {
  1373. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1374. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1375. return 1;
  1376. }
  1377. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1378. struct snd_ctl_elem_value *ucontrol)
  1379. {
  1380. int sample_rate_val;
  1381. switch (usb_rx_cfg.sample_rate) {
  1382. case SAMPLING_RATE_384KHZ:
  1383. sample_rate_val = 12;
  1384. break;
  1385. case SAMPLING_RATE_352P8KHZ:
  1386. sample_rate_val = 11;
  1387. break;
  1388. case SAMPLING_RATE_192KHZ:
  1389. sample_rate_val = 10;
  1390. break;
  1391. case SAMPLING_RATE_176P4KHZ:
  1392. sample_rate_val = 9;
  1393. break;
  1394. case SAMPLING_RATE_96KHZ:
  1395. sample_rate_val = 8;
  1396. break;
  1397. case SAMPLING_RATE_88P2KHZ:
  1398. sample_rate_val = 7;
  1399. break;
  1400. case SAMPLING_RATE_48KHZ:
  1401. sample_rate_val = 6;
  1402. break;
  1403. case SAMPLING_RATE_44P1KHZ:
  1404. sample_rate_val = 5;
  1405. break;
  1406. case SAMPLING_RATE_32KHZ:
  1407. sample_rate_val = 4;
  1408. break;
  1409. case SAMPLING_RATE_22P05KHZ:
  1410. sample_rate_val = 3;
  1411. break;
  1412. case SAMPLING_RATE_16KHZ:
  1413. sample_rate_val = 2;
  1414. break;
  1415. case SAMPLING_RATE_11P025KHZ:
  1416. sample_rate_val = 1;
  1417. break;
  1418. case SAMPLING_RATE_8KHZ:
  1419. default:
  1420. sample_rate_val = 0;
  1421. break;
  1422. }
  1423. ucontrol->value.integer.value[0] = sample_rate_val;
  1424. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1425. usb_rx_cfg.sample_rate);
  1426. return 0;
  1427. }
  1428. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1429. struct snd_ctl_elem_value *ucontrol)
  1430. {
  1431. switch (ucontrol->value.integer.value[0]) {
  1432. case 12:
  1433. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1434. break;
  1435. case 11:
  1436. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1437. break;
  1438. case 10:
  1439. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1440. break;
  1441. case 9:
  1442. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1443. break;
  1444. case 8:
  1445. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1446. break;
  1447. case 7:
  1448. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1449. break;
  1450. case 6:
  1451. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1452. break;
  1453. case 5:
  1454. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1455. break;
  1456. case 4:
  1457. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1458. break;
  1459. case 3:
  1460. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1461. break;
  1462. case 2:
  1463. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1464. break;
  1465. case 1:
  1466. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1467. break;
  1468. case 0:
  1469. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1470. break;
  1471. default:
  1472. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1473. break;
  1474. }
  1475. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1476. __func__, ucontrol->value.integer.value[0],
  1477. usb_rx_cfg.sample_rate);
  1478. return 0;
  1479. }
  1480. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1481. struct snd_ctl_elem_value *ucontrol)
  1482. {
  1483. switch (usb_rx_cfg.bit_format) {
  1484. case SNDRV_PCM_FORMAT_S32_LE:
  1485. ucontrol->value.integer.value[0] = 3;
  1486. break;
  1487. case SNDRV_PCM_FORMAT_S24_3LE:
  1488. ucontrol->value.integer.value[0] = 2;
  1489. break;
  1490. case SNDRV_PCM_FORMAT_S24_LE:
  1491. ucontrol->value.integer.value[0] = 1;
  1492. break;
  1493. case SNDRV_PCM_FORMAT_S16_LE:
  1494. default:
  1495. ucontrol->value.integer.value[0] = 0;
  1496. break;
  1497. }
  1498. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1499. __func__, usb_rx_cfg.bit_format,
  1500. ucontrol->value.integer.value[0]);
  1501. return 0;
  1502. }
  1503. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1504. struct snd_ctl_elem_value *ucontrol)
  1505. {
  1506. int rc = 0;
  1507. switch (ucontrol->value.integer.value[0]) {
  1508. case 3:
  1509. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1510. break;
  1511. case 2:
  1512. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1513. break;
  1514. case 1:
  1515. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1516. break;
  1517. case 0:
  1518. default:
  1519. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1520. break;
  1521. }
  1522. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1523. __func__, usb_rx_cfg.bit_format,
  1524. ucontrol->value.integer.value[0]);
  1525. return rc;
  1526. }
  1527. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1528. struct snd_ctl_elem_value *ucontrol)
  1529. {
  1530. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1531. usb_tx_cfg.channels);
  1532. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1533. return 0;
  1534. }
  1535. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1536. struct snd_ctl_elem_value *ucontrol)
  1537. {
  1538. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1539. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1540. return 1;
  1541. }
  1542. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1543. struct snd_ctl_elem_value *ucontrol)
  1544. {
  1545. int sample_rate_val;
  1546. switch (usb_tx_cfg.sample_rate) {
  1547. case SAMPLING_RATE_384KHZ:
  1548. sample_rate_val = 12;
  1549. break;
  1550. case SAMPLING_RATE_352P8KHZ:
  1551. sample_rate_val = 11;
  1552. break;
  1553. case SAMPLING_RATE_192KHZ:
  1554. sample_rate_val = 10;
  1555. break;
  1556. case SAMPLING_RATE_176P4KHZ:
  1557. sample_rate_val = 9;
  1558. break;
  1559. case SAMPLING_RATE_96KHZ:
  1560. sample_rate_val = 8;
  1561. break;
  1562. case SAMPLING_RATE_88P2KHZ:
  1563. sample_rate_val = 7;
  1564. break;
  1565. case SAMPLING_RATE_48KHZ:
  1566. sample_rate_val = 6;
  1567. break;
  1568. case SAMPLING_RATE_44P1KHZ:
  1569. sample_rate_val = 5;
  1570. break;
  1571. case SAMPLING_RATE_32KHZ:
  1572. sample_rate_val = 4;
  1573. break;
  1574. case SAMPLING_RATE_22P05KHZ:
  1575. sample_rate_val = 3;
  1576. break;
  1577. case SAMPLING_RATE_16KHZ:
  1578. sample_rate_val = 2;
  1579. break;
  1580. case SAMPLING_RATE_11P025KHZ:
  1581. sample_rate_val = 1;
  1582. break;
  1583. case SAMPLING_RATE_8KHZ:
  1584. sample_rate_val = 0;
  1585. break;
  1586. default:
  1587. sample_rate_val = 6;
  1588. break;
  1589. }
  1590. ucontrol->value.integer.value[0] = sample_rate_val;
  1591. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1592. usb_tx_cfg.sample_rate);
  1593. return 0;
  1594. }
  1595. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_value *ucontrol)
  1597. {
  1598. switch (ucontrol->value.integer.value[0]) {
  1599. case 12:
  1600. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1601. break;
  1602. case 11:
  1603. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1604. break;
  1605. case 10:
  1606. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1607. break;
  1608. case 9:
  1609. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1610. break;
  1611. case 8:
  1612. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1613. break;
  1614. case 7:
  1615. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1616. break;
  1617. case 6:
  1618. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1619. break;
  1620. case 5:
  1621. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1622. break;
  1623. case 4:
  1624. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1625. break;
  1626. case 3:
  1627. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1628. break;
  1629. case 2:
  1630. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1631. break;
  1632. case 1:
  1633. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1634. break;
  1635. case 0:
  1636. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1637. break;
  1638. default:
  1639. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1640. break;
  1641. }
  1642. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1643. __func__, ucontrol->value.integer.value[0],
  1644. usb_tx_cfg.sample_rate);
  1645. return 0;
  1646. }
  1647. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1648. struct snd_ctl_elem_value *ucontrol)
  1649. {
  1650. switch (usb_tx_cfg.bit_format) {
  1651. case SNDRV_PCM_FORMAT_S32_LE:
  1652. ucontrol->value.integer.value[0] = 3;
  1653. break;
  1654. case SNDRV_PCM_FORMAT_S24_3LE:
  1655. ucontrol->value.integer.value[0] = 2;
  1656. break;
  1657. case SNDRV_PCM_FORMAT_S24_LE:
  1658. ucontrol->value.integer.value[0] = 1;
  1659. break;
  1660. case SNDRV_PCM_FORMAT_S16_LE:
  1661. default:
  1662. ucontrol->value.integer.value[0] = 0;
  1663. break;
  1664. }
  1665. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1666. __func__, usb_tx_cfg.bit_format,
  1667. ucontrol->value.integer.value[0]);
  1668. return 0;
  1669. }
  1670. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1671. struct snd_ctl_elem_value *ucontrol)
  1672. {
  1673. int rc = 0;
  1674. switch (ucontrol->value.integer.value[0]) {
  1675. case 3:
  1676. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1677. break;
  1678. case 2:
  1679. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1680. break;
  1681. case 1:
  1682. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1683. break;
  1684. case 0:
  1685. default:
  1686. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1687. break;
  1688. }
  1689. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1690. __func__, usb_tx_cfg.bit_format,
  1691. ucontrol->value.integer.value[0]);
  1692. return rc;
  1693. }
  1694. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1695. struct snd_ctl_elem_value *ucontrol)
  1696. {
  1697. pr_debug("%s: proxy_rx channels = %d\n",
  1698. __func__, proxy_rx_cfg.channels);
  1699. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1700. return 0;
  1701. }
  1702. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1703. struct snd_ctl_elem_value *ucontrol)
  1704. {
  1705. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1706. pr_debug("%s: proxy_rx channels = %d\n",
  1707. __func__, proxy_rx_cfg.channels);
  1708. return 1;
  1709. }
  1710. static int tdm_get_sample_rate(int value)
  1711. {
  1712. int sample_rate = 0;
  1713. switch (value) {
  1714. case 0:
  1715. sample_rate = SAMPLING_RATE_8KHZ;
  1716. break;
  1717. case 1:
  1718. sample_rate = SAMPLING_RATE_16KHZ;
  1719. break;
  1720. case 2:
  1721. sample_rate = SAMPLING_RATE_32KHZ;
  1722. break;
  1723. case 3:
  1724. sample_rate = SAMPLING_RATE_48KHZ;
  1725. break;
  1726. case 4:
  1727. sample_rate = SAMPLING_RATE_176P4KHZ;
  1728. break;
  1729. case 5:
  1730. sample_rate = SAMPLING_RATE_352P8KHZ;
  1731. break;
  1732. default:
  1733. sample_rate = SAMPLING_RATE_48KHZ;
  1734. break;
  1735. }
  1736. return sample_rate;
  1737. }
  1738. static int aux_pcm_get_sample_rate(int value)
  1739. {
  1740. int sample_rate;
  1741. switch (value) {
  1742. case 1:
  1743. sample_rate = SAMPLING_RATE_16KHZ;
  1744. break;
  1745. case 0:
  1746. default:
  1747. sample_rate = SAMPLING_RATE_8KHZ;
  1748. break;
  1749. }
  1750. return sample_rate;
  1751. }
  1752. static int tdm_get_sample_rate_val(int sample_rate)
  1753. {
  1754. int sample_rate_val = 0;
  1755. switch (sample_rate) {
  1756. case SAMPLING_RATE_8KHZ:
  1757. sample_rate_val = 0;
  1758. break;
  1759. case SAMPLING_RATE_16KHZ:
  1760. sample_rate_val = 1;
  1761. break;
  1762. case SAMPLING_RATE_32KHZ:
  1763. sample_rate_val = 2;
  1764. break;
  1765. case SAMPLING_RATE_48KHZ:
  1766. sample_rate_val = 3;
  1767. break;
  1768. case SAMPLING_RATE_176P4KHZ:
  1769. sample_rate_val = 4;
  1770. break;
  1771. case SAMPLING_RATE_352P8KHZ:
  1772. sample_rate_val = 5;
  1773. break;
  1774. default:
  1775. sample_rate_val = 3;
  1776. break;
  1777. }
  1778. return sample_rate_val;
  1779. }
  1780. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1781. {
  1782. int sample_rate_val;
  1783. switch (sample_rate) {
  1784. case SAMPLING_RATE_16KHZ:
  1785. sample_rate_val = 1;
  1786. break;
  1787. case SAMPLING_RATE_8KHZ:
  1788. default:
  1789. sample_rate_val = 0;
  1790. break;
  1791. }
  1792. return sample_rate_val;
  1793. }
  1794. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1795. struct tdm_port *port)
  1796. {
  1797. if (port) {
  1798. if (strnstr(kcontrol->id.name, "PRI",
  1799. sizeof(kcontrol->id.name))) {
  1800. port->mode = TDM_PRI;
  1801. } else if (strnstr(kcontrol->id.name, "SEC",
  1802. sizeof(kcontrol->id.name))) {
  1803. port->mode = TDM_SEC;
  1804. } else if (strnstr(kcontrol->id.name, "TERT",
  1805. sizeof(kcontrol->id.name))) {
  1806. port->mode = TDM_TERT;
  1807. } else if (strnstr(kcontrol->id.name, "QUAT",
  1808. sizeof(kcontrol->id.name))) {
  1809. port->mode = TDM_QUAT;
  1810. } else if (strnstr(kcontrol->id.name, "QUIN",
  1811. sizeof(kcontrol->id.name))) {
  1812. port->mode = TDM_QUIN;
  1813. } else {
  1814. pr_err("%s: unsupported mode in: %s",
  1815. __func__, kcontrol->id.name);
  1816. return -EINVAL;
  1817. }
  1818. if (strnstr(kcontrol->id.name, "RX_0",
  1819. sizeof(kcontrol->id.name)) ||
  1820. strnstr(kcontrol->id.name, "TX_0",
  1821. sizeof(kcontrol->id.name))) {
  1822. port->channel = TDM_0;
  1823. } else if (strnstr(kcontrol->id.name, "RX_1",
  1824. sizeof(kcontrol->id.name)) ||
  1825. strnstr(kcontrol->id.name, "TX_1",
  1826. sizeof(kcontrol->id.name))) {
  1827. port->channel = TDM_1;
  1828. } else if (strnstr(kcontrol->id.name, "RX_2",
  1829. sizeof(kcontrol->id.name)) ||
  1830. strnstr(kcontrol->id.name, "TX_2",
  1831. sizeof(kcontrol->id.name))) {
  1832. port->channel = TDM_2;
  1833. } else if (strnstr(kcontrol->id.name, "RX_3",
  1834. sizeof(kcontrol->id.name)) ||
  1835. strnstr(kcontrol->id.name, "TX_3",
  1836. sizeof(kcontrol->id.name))) {
  1837. port->channel = TDM_3;
  1838. } else if (strnstr(kcontrol->id.name, "RX_4",
  1839. sizeof(kcontrol->id.name)) ||
  1840. strnstr(kcontrol->id.name, "TX_4",
  1841. sizeof(kcontrol->id.name))) {
  1842. port->channel = TDM_4;
  1843. } else if (strnstr(kcontrol->id.name, "RX_5",
  1844. sizeof(kcontrol->id.name)) ||
  1845. strnstr(kcontrol->id.name, "TX_5",
  1846. sizeof(kcontrol->id.name))) {
  1847. port->channel = TDM_5;
  1848. } else if (strnstr(kcontrol->id.name, "RX_6",
  1849. sizeof(kcontrol->id.name)) ||
  1850. strnstr(kcontrol->id.name, "TX_6",
  1851. sizeof(kcontrol->id.name))) {
  1852. port->channel = TDM_6;
  1853. } else if (strnstr(kcontrol->id.name, "RX_7",
  1854. sizeof(kcontrol->id.name)) ||
  1855. strnstr(kcontrol->id.name, "TX_7",
  1856. sizeof(kcontrol->id.name))) {
  1857. port->channel = TDM_7;
  1858. } else {
  1859. pr_err("%s: unsupported channel in: %s",
  1860. __func__, kcontrol->id.name);
  1861. return -EINVAL;
  1862. }
  1863. } else
  1864. return -EINVAL;
  1865. return 0;
  1866. }
  1867. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1868. struct snd_ctl_elem_value *ucontrol)
  1869. {
  1870. struct tdm_port port;
  1871. int ret = tdm_get_port_idx(kcontrol, &port);
  1872. if (ret) {
  1873. pr_err("%s: unsupported control: %s",
  1874. __func__, kcontrol->id.name);
  1875. } else {
  1876. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1877. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1878. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1879. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1880. ucontrol->value.enumerated.item[0]);
  1881. }
  1882. return ret;
  1883. }
  1884. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1885. struct snd_ctl_elem_value *ucontrol)
  1886. {
  1887. struct tdm_port port;
  1888. int ret = tdm_get_port_idx(kcontrol, &port);
  1889. if (ret) {
  1890. pr_err("%s: unsupported control: %s",
  1891. __func__, kcontrol->id.name);
  1892. } else {
  1893. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1894. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1895. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1896. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1897. ucontrol->value.enumerated.item[0]);
  1898. }
  1899. return ret;
  1900. }
  1901. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1902. struct snd_ctl_elem_value *ucontrol)
  1903. {
  1904. struct tdm_port port;
  1905. int ret = tdm_get_port_idx(kcontrol, &port);
  1906. if (ret) {
  1907. pr_err("%s: unsupported control: %s",
  1908. __func__, kcontrol->id.name);
  1909. } else {
  1910. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1911. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1912. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1913. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1914. ucontrol->value.enumerated.item[0]);
  1915. }
  1916. return ret;
  1917. }
  1918. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1919. struct snd_ctl_elem_value *ucontrol)
  1920. {
  1921. struct tdm_port port;
  1922. int ret = tdm_get_port_idx(kcontrol, &port);
  1923. if (ret) {
  1924. pr_err("%s: unsupported control: %s",
  1925. __func__, kcontrol->id.name);
  1926. } else {
  1927. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1928. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1929. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1930. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1931. ucontrol->value.enumerated.item[0]);
  1932. }
  1933. return ret;
  1934. }
  1935. static int tdm_get_format(int value)
  1936. {
  1937. int format = 0;
  1938. switch (value) {
  1939. case 0:
  1940. format = SNDRV_PCM_FORMAT_S16_LE;
  1941. break;
  1942. case 1:
  1943. format = SNDRV_PCM_FORMAT_S24_LE;
  1944. break;
  1945. case 2:
  1946. format = SNDRV_PCM_FORMAT_S32_LE;
  1947. break;
  1948. default:
  1949. format = SNDRV_PCM_FORMAT_S16_LE;
  1950. break;
  1951. }
  1952. return format;
  1953. }
  1954. static int tdm_get_format_val(int format)
  1955. {
  1956. int value = 0;
  1957. switch (format) {
  1958. case SNDRV_PCM_FORMAT_S16_LE:
  1959. value = 0;
  1960. break;
  1961. case SNDRV_PCM_FORMAT_S24_LE:
  1962. value = 1;
  1963. break;
  1964. case SNDRV_PCM_FORMAT_S32_LE:
  1965. value = 2;
  1966. break;
  1967. default:
  1968. value = 0;
  1969. break;
  1970. }
  1971. return value;
  1972. }
  1973. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1974. struct snd_ctl_elem_value *ucontrol)
  1975. {
  1976. struct tdm_port port;
  1977. int ret = tdm_get_port_idx(kcontrol, &port);
  1978. if (ret) {
  1979. pr_err("%s: unsupported control: %s",
  1980. __func__, kcontrol->id.name);
  1981. } else {
  1982. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1983. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1984. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1985. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1986. ucontrol->value.enumerated.item[0]);
  1987. }
  1988. return ret;
  1989. }
  1990. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1991. struct snd_ctl_elem_value *ucontrol)
  1992. {
  1993. struct tdm_port port;
  1994. int ret = tdm_get_port_idx(kcontrol, &port);
  1995. if (ret) {
  1996. pr_err("%s: unsupported control: %s",
  1997. __func__, kcontrol->id.name);
  1998. } else {
  1999. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2000. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2001. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2002. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2003. ucontrol->value.enumerated.item[0]);
  2004. }
  2005. return ret;
  2006. }
  2007. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2008. struct snd_ctl_elem_value *ucontrol)
  2009. {
  2010. struct tdm_port port;
  2011. int ret = tdm_get_port_idx(kcontrol, &port);
  2012. if (ret) {
  2013. pr_err("%s: unsupported control: %s",
  2014. __func__, kcontrol->id.name);
  2015. } else {
  2016. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2017. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2018. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2019. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2020. ucontrol->value.enumerated.item[0]);
  2021. }
  2022. return ret;
  2023. }
  2024. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2025. struct snd_ctl_elem_value *ucontrol)
  2026. {
  2027. struct tdm_port port;
  2028. int ret = tdm_get_port_idx(kcontrol, &port);
  2029. if (ret) {
  2030. pr_err("%s: unsupported control: %s",
  2031. __func__, kcontrol->id.name);
  2032. } else {
  2033. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2034. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2035. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2036. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2037. ucontrol->value.enumerated.item[0]);
  2038. }
  2039. return ret;
  2040. }
  2041. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2042. struct snd_ctl_elem_value *ucontrol)
  2043. {
  2044. struct tdm_port port;
  2045. int ret = tdm_get_port_idx(kcontrol, &port);
  2046. if (ret) {
  2047. pr_err("%s: unsupported control: %s",
  2048. __func__, kcontrol->id.name);
  2049. } else {
  2050. ucontrol->value.enumerated.item[0] =
  2051. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2052. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2053. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2054. ucontrol->value.enumerated.item[0]);
  2055. }
  2056. return ret;
  2057. }
  2058. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2059. struct snd_ctl_elem_value *ucontrol)
  2060. {
  2061. struct tdm_port port;
  2062. int ret = tdm_get_port_idx(kcontrol, &port);
  2063. if (ret) {
  2064. pr_err("%s: unsupported control: %s",
  2065. __func__, kcontrol->id.name);
  2066. } else {
  2067. tdm_rx_cfg[port.mode][port.channel].channels =
  2068. ucontrol->value.enumerated.item[0] + 1;
  2069. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2070. tdm_rx_cfg[port.mode][port.channel].channels,
  2071. ucontrol->value.enumerated.item[0] + 1);
  2072. }
  2073. return ret;
  2074. }
  2075. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2076. struct snd_ctl_elem_value *ucontrol)
  2077. {
  2078. struct tdm_port port;
  2079. int ret = tdm_get_port_idx(kcontrol, &port);
  2080. if (ret) {
  2081. pr_err("%s: unsupported control: %s",
  2082. __func__, kcontrol->id.name);
  2083. } else {
  2084. ucontrol->value.enumerated.item[0] =
  2085. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2086. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2087. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2088. ucontrol->value.enumerated.item[0]);
  2089. }
  2090. return ret;
  2091. }
  2092. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2093. struct snd_ctl_elem_value *ucontrol)
  2094. {
  2095. struct tdm_port port;
  2096. int ret = tdm_get_port_idx(kcontrol, &port);
  2097. if (ret) {
  2098. pr_err("%s: unsupported control: %s",
  2099. __func__, kcontrol->id.name);
  2100. } else {
  2101. tdm_tx_cfg[port.mode][port.channel].channels =
  2102. ucontrol->value.enumerated.item[0] + 1;
  2103. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2104. tdm_tx_cfg[port.mode][port.channel].channels,
  2105. ucontrol->value.enumerated.item[0] + 1);
  2106. }
  2107. return ret;
  2108. }
  2109. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2110. {
  2111. int idx;
  2112. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2113. sizeof("PRIM_AUX_PCM")))
  2114. idx = PRIM_AUX_PCM;
  2115. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2116. sizeof("SEC_AUX_PCM")))
  2117. idx = SEC_AUX_PCM;
  2118. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2119. sizeof("TERT_AUX_PCM")))
  2120. idx = TERT_AUX_PCM;
  2121. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2122. sizeof("QUAT_AUX_PCM")))
  2123. idx = QUAT_AUX_PCM;
  2124. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2125. sizeof("QUIN_AUX_PCM")))
  2126. idx = QUIN_AUX_PCM;
  2127. else {
  2128. pr_err("%s: unsupported port: %s",
  2129. __func__, kcontrol->id.name);
  2130. idx = -EINVAL;
  2131. }
  2132. return idx;
  2133. }
  2134. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2135. struct snd_ctl_elem_value *ucontrol)
  2136. {
  2137. int idx = aux_pcm_get_port_idx(kcontrol);
  2138. if (idx < 0)
  2139. return idx;
  2140. aux_pcm_rx_cfg[idx].sample_rate =
  2141. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2142. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2143. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2144. ucontrol->value.enumerated.item[0]);
  2145. return 0;
  2146. }
  2147. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2148. struct snd_ctl_elem_value *ucontrol)
  2149. {
  2150. int idx = aux_pcm_get_port_idx(kcontrol);
  2151. if (idx < 0)
  2152. return idx;
  2153. ucontrol->value.enumerated.item[0] =
  2154. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2155. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2156. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2157. ucontrol->value.enumerated.item[0]);
  2158. return 0;
  2159. }
  2160. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2161. struct snd_ctl_elem_value *ucontrol)
  2162. {
  2163. int idx = aux_pcm_get_port_idx(kcontrol);
  2164. if (idx < 0)
  2165. return idx;
  2166. aux_pcm_tx_cfg[idx].sample_rate =
  2167. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2168. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2169. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2170. ucontrol->value.enumerated.item[0]);
  2171. return 0;
  2172. }
  2173. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2174. struct snd_ctl_elem_value *ucontrol)
  2175. {
  2176. int idx = aux_pcm_get_port_idx(kcontrol);
  2177. if (idx < 0)
  2178. return idx;
  2179. ucontrol->value.enumerated.item[0] =
  2180. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2181. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2182. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2183. ucontrol->value.enumerated.item[0]);
  2184. return 0;
  2185. }
  2186. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2187. {
  2188. int idx;
  2189. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2190. sizeof("PRIM_MI2S_RX")))
  2191. idx = PRIM_MI2S;
  2192. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2193. sizeof("SEC_MI2S_RX")))
  2194. idx = SEC_MI2S;
  2195. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2196. sizeof("TERT_MI2S_RX")))
  2197. idx = TERT_MI2S;
  2198. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2199. sizeof("QUAT_MI2S_RX")))
  2200. idx = QUAT_MI2S;
  2201. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2202. sizeof("QUIN_MI2S_RX")))
  2203. idx = QUIN_MI2S;
  2204. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2205. sizeof("PRIM_MI2S_TX")))
  2206. idx = PRIM_MI2S;
  2207. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2208. sizeof("SEC_MI2S_TX")))
  2209. idx = SEC_MI2S;
  2210. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2211. sizeof("TERT_MI2S_TX")))
  2212. idx = TERT_MI2S;
  2213. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2214. sizeof("QUAT_MI2S_TX")))
  2215. idx = QUAT_MI2S;
  2216. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2217. sizeof("QUIN_MI2S_TX")))
  2218. idx = QUIN_MI2S;
  2219. else {
  2220. pr_err("%s: unsupported channel: %s",
  2221. __func__, kcontrol->id.name);
  2222. idx = -EINVAL;
  2223. }
  2224. return idx;
  2225. }
  2226. static int mi2s_get_sample_rate_val(int sample_rate)
  2227. {
  2228. int sample_rate_val;
  2229. switch (sample_rate) {
  2230. case SAMPLING_RATE_8KHZ:
  2231. sample_rate_val = 0;
  2232. break;
  2233. case SAMPLING_RATE_11P025KHZ:
  2234. sample_rate_val = 1;
  2235. break;
  2236. case SAMPLING_RATE_16KHZ:
  2237. sample_rate_val = 2;
  2238. break;
  2239. case SAMPLING_RATE_22P05KHZ:
  2240. sample_rate_val = 3;
  2241. break;
  2242. case SAMPLING_RATE_32KHZ:
  2243. sample_rate_val = 4;
  2244. break;
  2245. case SAMPLING_RATE_44P1KHZ:
  2246. sample_rate_val = 5;
  2247. break;
  2248. case SAMPLING_RATE_48KHZ:
  2249. sample_rate_val = 6;
  2250. break;
  2251. case SAMPLING_RATE_96KHZ:
  2252. sample_rate_val = 7;
  2253. break;
  2254. case SAMPLING_RATE_192KHZ:
  2255. sample_rate_val = 8;
  2256. break;
  2257. default:
  2258. sample_rate_val = 6;
  2259. break;
  2260. }
  2261. return sample_rate_val;
  2262. }
  2263. static int mi2s_get_sample_rate(int value)
  2264. {
  2265. int sample_rate;
  2266. switch (value) {
  2267. case 0:
  2268. sample_rate = SAMPLING_RATE_8KHZ;
  2269. break;
  2270. case 1:
  2271. sample_rate = SAMPLING_RATE_11P025KHZ;
  2272. break;
  2273. case 2:
  2274. sample_rate = SAMPLING_RATE_16KHZ;
  2275. break;
  2276. case 3:
  2277. sample_rate = SAMPLING_RATE_22P05KHZ;
  2278. break;
  2279. case 4:
  2280. sample_rate = SAMPLING_RATE_32KHZ;
  2281. break;
  2282. case 5:
  2283. sample_rate = SAMPLING_RATE_44P1KHZ;
  2284. break;
  2285. case 6:
  2286. sample_rate = SAMPLING_RATE_48KHZ;
  2287. break;
  2288. case 7:
  2289. sample_rate = SAMPLING_RATE_96KHZ;
  2290. break;
  2291. case 8:
  2292. sample_rate = SAMPLING_RATE_192KHZ;
  2293. break;
  2294. default:
  2295. sample_rate = SAMPLING_RATE_48KHZ;
  2296. break;
  2297. }
  2298. return sample_rate;
  2299. }
  2300. static int mi2s_auxpcm_get_format(int value)
  2301. {
  2302. int format;
  2303. switch (value) {
  2304. case 0:
  2305. format = SNDRV_PCM_FORMAT_S16_LE;
  2306. break;
  2307. case 1:
  2308. format = SNDRV_PCM_FORMAT_S24_LE;
  2309. break;
  2310. case 2:
  2311. format = SNDRV_PCM_FORMAT_S24_3LE;
  2312. break;
  2313. case 3:
  2314. format = SNDRV_PCM_FORMAT_S32_LE;
  2315. break;
  2316. default:
  2317. format = SNDRV_PCM_FORMAT_S16_LE;
  2318. break;
  2319. }
  2320. return format;
  2321. }
  2322. static int mi2s_auxpcm_get_format_value(int format)
  2323. {
  2324. int value;
  2325. switch (format) {
  2326. case SNDRV_PCM_FORMAT_S16_LE:
  2327. value = 0;
  2328. break;
  2329. case SNDRV_PCM_FORMAT_S24_LE:
  2330. value = 1;
  2331. break;
  2332. case SNDRV_PCM_FORMAT_S24_3LE:
  2333. value = 2;
  2334. break;
  2335. case SNDRV_PCM_FORMAT_S32_LE:
  2336. value = 3;
  2337. break;
  2338. default:
  2339. value = 0;
  2340. break;
  2341. }
  2342. return value;
  2343. }
  2344. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2345. struct snd_ctl_elem_value *ucontrol)
  2346. {
  2347. int idx = mi2s_get_port_idx(kcontrol);
  2348. if (idx < 0)
  2349. return idx;
  2350. mi2s_rx_cfg[idx].sample_rate =
  2351. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2352. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2353. idx, mi2s_rx_cfg[idx].sample_rate,
  2354. ucontrol->value.enumerated.item[0]);
  2355. return 0;
  2356. }
  2357. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2358. struct snd_ctl_elem_value *ucontrol)
  2359. {
  2360. int idx = mi2s_get_port_idx(kcontrol);
  2361. if (idx < 0)
  2362. return idx;
  2363. ucontrol->value.enumerated.item[0] =
  2364. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2365. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2366. idx, mi2s_rx_cfg[idx].sample_rate,
  2367. ucontrol->value.enumerated.item[0]);
  2368. return 0;
  2369. }
  2370. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2371. struct snd_ctl_elem_value *ucontrol)
  2372. {
  2373. int idx = mi2s_get_port_idx(kcontrol);
  2374. if (idx < 0)
  2375. return idx;
  2376. mi2s_tx_cfg[idx].sample_rate =
  2377. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2378. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2379. idx, mi2s_tx_cfg[idx].sample_rate,
  2380. ucontrol->value.enumerated.item[0]);
  2381. return 0;
  2382. }
  2383. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2384. struct snd_ctl_elem_value *ucontrol)
  2385. {
  2386. int idx = mi2s_get_port_idx(kcontrol);
  2387. if (idx < 0)
  2388. return idx;
  2389. ucontrol->value.enumerated.item[0] =
  2390. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2391. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2392. idx, mi2s_tx_cfg[idx].sample_rate,
  2393. ucontrol->value.enumerated.item[0]);
  2394. return 0;
  2395. }
  2396. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2397. struct snd_ctl_elem_value *ucontrol)
  2398. {
  2399. int idx = mi2s_get_port_idx(kcontrol);
  2400. if (idx < 0)
  2401. return idx;
  2402. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2403. idx, mi2s_rx_cfg[idx].channels);
  2404. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2405. return 0;
  2406. }
  2407. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2408. struct snd_ctl_elem_value *ucontrol)
  2409. {
  2410. int idx = mi2s_get_port_idx(kcontrol);
  2411. if (idx < 0)
  2412. return idx;
  2413. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2414. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2415. idx, mi2s_rx_cfg[idx].channels);
  2416. return 1;
  2417. }
  2418. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2419. struct snd_ctl_elem_value *ucontrol)
  2420. {
  2421. int idx = mi2s_get_port_idx(kcontrol);
  2422. if (idx < 0)
  2423. return idx;
  2424. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2425. idx, mi2s_tx_cfg[idx].channels);
  2426. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2427. return 0;
  2428. }
  2429. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2430. struct snd_ctl_elem_value *ucontrol)
  2431. {
  2432. int idx = mi2s_get_port_idx(kcontrol);
  2433. if (idx < 0)
  2434. return idx;
  2435. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2436. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2437. idx, mi2s_tx_cfg[idx].channels);
  2438. return 1;
  2439. }
  2440. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2441. struct snd_ctl_elem_value *ucontrol)
  2442. {
  2443. int idx = mi2s_get_port_idx(kcontrol);
  2444. if (idx < 0)
  2445. return idx;
  2446. ucontrol->value.enumerated.item[0] =
  2447. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2448. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2449. idx, mi2s_rx_cfg[idx].bit_format,
  2450. ucontrol->value.enumerated.item[0]);
  2451. return 0;
  2452. }
  2453. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2454. struct snd_ctl_elem_value *ucontrol)
  2455. {
  2456. int idx = mi2s_get_port_idx(kcontrol);
  2457. if (idx < 0)
  2458. return idx;
  2459. mi2s_rx_cfg[idx].bit_format =
  2460. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2461. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2462. idx, mi2s_rx_cfg[idx].bit_format,
  2463. ucontrol->value.enumerated.item[0]);
  2464. return 0;
  2465. }
  2466. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2467. struct snd_ctl_elem_value *ucontrol)
  2468. {
  2469. int idx = mi2s_get_port_idx(kcontrol);
  2470. if (idx < 0)
  2471. return idx;
  2472. ucontrol->value.enumerated.item[0] =
  2473. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2474. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2475. idx, mi2s_tx_cfg[idx].bit_format,
  2476. ucontrol->value.enumerated.item[0]);
  2477. return 0;
  2478. }
  2479. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2480. struct snd_ctl_elem_value *ucontrol)
  2481. {
  2482. int idx = mi2s_get_port_idx(kcontrol);
  2483. if (idx < 0)
  2484. return idx;
  2485. mi2s_tx_cfg[idx].bit_format =
  2486. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2487. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2488. idx, mi2s_tx_cfg[idx].bit_format,
  2489. ucontrol->value.enumerated.item[0]);
  2490. return 0;
  2491. }
  2492. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2493. struct snd_ctl_elem_value *ucontrol)
  2494. {
  2495. int idx = aux_pcm_get_port_idx(kcontrol);
  2496. if (idx < 0)
  2497. return idx;
  2498. ucontrol->value.enumerated.item[0] =
  2499. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2500. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2501. idx, aux_pcm_rx_cfg[idx].bit_format,
  2502. ucontrol->value.enumerated.item[0]);
  2503. return 0;
  2504. }
  2505. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2506. struct snd_ctl_elem_value *ucontrol)
  2507. {
  2508. int idx = aux_pcm_get_port_idx(kcontrol);
  2509. if (idx < 0)
  2510. return idx;
  2511. aux_pcm_rx_cfg[idx].bit_format =
  2512. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2513. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2514. idx, aux_pcm_rx_cfg[idx].bit_format,
  2515. ucontrol->value.enumerated.item[0]);
  2516. return 0;
  2517. }
  2518. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2519. struct snd_ctl_elem_value *ucontrol)
  2520. {
  2521. int idx = aux_pcm_get_port_idx(kcontrol);
  2522. if (idx < 0)
  2523. return idx;
  2524. ucontrol->value.enumerated.item[0] =
  2525. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2526. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2527. idx, aux_pcm_tx_cfg[idx].bit_format,
  2528. ucontrol->value.enumerated.item[0]);
  2529. return 0;
  2530. }
  2531. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2532. struct snd_ctl_elem_value *ucontrol)
  2533. {
  2534. int idx = aux_pcm_get_port_idx(kcontrol);
  2535. if (idx < 0)
  2536. return idx;
  2537. aux_pcm_tx_cfg[idx].bit_format =
  2538. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2539. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2540. idx, aux_pcm_tx_cfg[idx].bit_format,
  2541. ucontrol->value.enumerated.item[0]);
  2542. return 0;
  2543. }
  2544. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2545. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2546. slim_rx_ch_get, slim_rx_ch_put),
  2547. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2548. slim_rx_ch_get, slim_rx_ch_put),
  2549. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2550. slim_tx_ch_get, slim_tx_ch_put),
  2551. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2552. slim_tx_ch_get, slim_tx_ch_put),
  2553. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2554. slim_rx_ch_get, slim_rx_ch_put),
  2555. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2556. slim_rx_ch_get, slim_rx_ch_put),
  2557. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2558. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2559. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2560. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2561. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2562. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2563. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2564. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2565. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2566. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2567. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2568. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2569. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2570. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2571. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2572. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2573. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2574. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2575. };
  2576. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2577. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2578. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2579. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2580. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2581. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2582. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2583. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2584. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2585. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2586. va_cdc_dma_tx_0_sample_rate,
  2587. cdc_dma_tx_sample_rate_get,
  2588. cdc_dma_tx_sample_rate_put),
  2589. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2590. va_cdc_dma_tx_1_sample_rate,
  2591. cdc_dma_tx_sample_rate_get,
  2592. cdc_dma_tx_sample_rate_put),
  2593. };
  2594. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2595. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2596. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2597. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2598. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2599. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2600. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2601. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2602. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2603. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2604. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2605. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2606. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2607. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2608. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2609. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2610. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2611. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2612. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2613. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2614. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2615. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2616. wsa_cdc_dma_rx_0_sample_rate,
  2617. cdc_dma_rx_sample_rate_get,
  2618. cdc_dma_rx_sample_rate_put),
  2619. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2620. wsa_cdc_dma_rx_1_sample_rate,
  2621. cdc_dma_rx_sample_rate_get,
  2622. cdc_dma_rx_sample_rate_put),
  2623. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2624. wsa_cdc_dma_tx_0_sample_rate,
  2625. cdc_dma_tx_sample_rate_get,
  2626. cdc_dma_tx_sample_rate_put),
  2627. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2628. wsa_cdc_dma_tx_1_sample_rate,
  2629. cdc_dma_tx_sample_rate_get,
  2630. cdc_dma_tx_sample_rate_put),
  2631. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2632. wsa_cdc_dma_tx_2_sample_rate,
  2633. cdc_dma_tx_sample_rate_get,
  2634. cdc_dma_tx_sample_rate_put),
  2635. };
  2636. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2637. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2638. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2639. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2640. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2641. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2642. proxy_rx_ch_get, proxy_rx_ch_put),
  2643. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2644. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2645. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2646. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2647. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2648. msm_bt_sample_rate_get,
  2649. msm_bt_sample_rate_put),
  2650. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2651. usb_audio_rx_sample_rate_get,
  2652. usb_audio_rx_sample_rate_put),
  2653. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2654. usb_audio_tx_sample_rate_get,
  2655. usb_audio_tx_sample_rate_put),
  2656. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2657. tdm_rx_sample_rate_get,
  2658. tdm_rx_sample_rate_put),
  2659. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2660. tdm_tx_sample_rate_get,
  2661. tdm_tx_sample_rate_put),
  2662. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2663. tdm_rx_format_get,
  2664. tdm_rx_format_put),
  2665. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2666. tdm_tx_format_get,
  2667. tdm_tx_format_put),
  2668. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2669. tdm_rx_ch_get,
  2670. tdm_rx_ch_put),
  2671. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2672. tdm_tx_ch_get,
  2673. tdm_tx_ch_put),
  2674. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2675. tdm_rx_sample_rate_get,
  2676. tdm_rx_sample_rate_put),
  2677. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2678. tdm_tx_sample_rate_get,
  2679. tdm_tx_sample_rate_put),
  2680. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2681. tdm_rx_format_get,
  2682. tdm_rx_format_put),
  2683. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2684. tdm_tx_format_get,
  2685. tdm_tx_format_put),
  2686. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2687. tdm_rx_ch_get,
  2688. tdm_rx_ch_put),
  2689. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2690. tdm_tx_ch_get,
  2691. tdm_tx_ch_put),
  2692. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2693. tdm_rx_sample_rate_get,
  2694. tdm_rx_sample_rate_put),
  2695. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2696. tdm_tx_sample_rate_get,
  2697. tdm_tx_sample_rate_put),
  2698. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2699. tdm_rx_format_get,
  2700. tdm_rx_format_put),
  2701. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2702. tdm_tx_format_get,
  2703. tdm_tx_format_put),
  2704. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2705. tdm_rx_ch_get,
  2706. tdm_rx_ch_put),
  2707. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2708. tdm_tx_ch_get,
  2709. tdm_tx_ch_put),
  2710. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2711. tdm_rx_sample_rate_get,
  2712. tdm_rx_sample_rate_put),
  2713. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2714. tdm_tx_sample_rate_get,
  2715. tdm_tx_sample_rate_put),
  2716. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2717. tdm_rx_format_get,
  2718. tdm_rx_format_put),
  2719. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2720. tdm_tx_format_get,
  2721. tdm_tx_format_put),
  2722. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2723. tdm_rx_ch_get,
  2724. tdm_rx_ch_put),
  2725. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2726. tdm_tx_ch_get,
  2727. tdm_tx_ch_put),
  2728. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2729. tdm_rx_sample_rate_get,
  2730. tdm_rx_sample_rate_put),
  2731. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2732. tdm_tx_sample_rate_get,
  2733. tdm_tx_sample_rate_put),
  2734. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2735. tdm_rx_format_get,
  2736. tdm_rx_format_put),
  2737. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2738. tdm_tx_format_get,
  2739. tdm_tx_format_put),
  2740. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2741. tdm_rx_ch_get,
  2742. tdm_rx_ch_put),
  2743. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2744. tdm_tx_ch_get,
  2745. tdm_tx_ch_put),
  2746. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2750. aux_pcm_rx_sample_rate_get,
  2751. aux_pcm_rx_sample_rate_put),
  2752. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2753. aux_pcm_rx_sample_rate_get,
  2754. aux_pcm_rx_sample_rate_put),
  2755. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2756. aux_pcm_rx_sample_rate_get,
  2757. aux_pcm_rx_sample_rate_put),
  2758. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2759. aux_pcm_rx_sample_rate_get,
  2760. aux_pcm_rx_sample_rate_put),
  2761. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2765. aux_pcm_tx_sample_rate_get,
  2766. aux_pcm_tx_sample_rate_put),
  2767. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2768. aux_pcm_tx_sample_rate_get,
  2769. aux_pcm_tx_sample_rate_put),
  2770. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2771. aux_pcm_tx_sample_rate_get,
  2772. aux_pcm_tx_sample_rate_put),
  2773. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2774. aux_pcm_tx_sample_rate_get,
  2775. aux_pcm_tx_sample_rate_put),
  2776. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2777. mi2s_rx_sample_rate_get,
  2778. mi2s_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2780. mi2s_rx_sample_rate_get,
  2781. mi2s_rx_sample_rate_put),
  2782. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2783. mi2s_rx_sample_rate_get,
  2784. mi2s_rx_sample_rate_put),
  2785. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2786. mi2s_rx_sample_rate_get,
  2787. mi2s_rx_sample_rate_put),
  2788. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2789. mi2s_rx_sample_rate_get,
  2790. mi2s_rx_sample_rate_put),
  2791. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2792. mi2s_tx_sample_rate_get,
  2793. mi2s_tx_sample_rate_put),
  2794. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2795. mi2s_tx_sample_rate_get,
  2796. mi2s_tx_sample_rate_put),
  2797. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2798. mi2s_tx_sample_rate_get,
  2799. mi2s_tx_sample_rate_put),
  2800. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2801. mi2s_tx_sample_rate_get,
  2802. mi2s_tx_sample_rate_put),
  2803. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2804. mi2s_tx_sample_rate_get,
  2805. mi2s_tx_sample_rate_put),
  2806. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2807. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2808. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2809. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2810. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2811. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2812. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2813. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2814. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2815. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2816. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2817. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2818. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2819. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2820. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2821. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2822. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2823. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2824. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2825. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2826. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2827. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2828. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2829. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2830. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2831. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2832. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2833. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2834. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2835. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2836. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2837. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2838. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2839. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2840. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2841. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2842. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2843. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2844. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2845. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2846. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2847. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2848. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2849. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2850. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2851. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2852. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2853. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2854. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2855. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2856. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2857. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2858. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2859. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2860. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2861. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2862. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2863. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2864. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2865. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2866. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2867. msm_snd_vad_cfg_put),
  2868. };
  2869. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2870. int enable, bool dapm)
  2871. {
  2872. int ret = 0;
  2873. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2874. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2875. } else {
  2876. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2877. __func__);
  2878. ret = -EINVAL;
  2879. }
  2880. return ret;
  2881. }
  2882. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2883. int enable, bool dapm)
  2884. {
  2885. int ret = 0;
  2886. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2887. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2888. } else {
  2889. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2890. __func__);
  2891. ret = -EINVAL;
  2892. }
  2893. return ret;
  2894. }
  2895. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2896. struct snd_kcontrol *kcontrol, int event)
  2897. {
  2898. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2899. pr_debug("%s: event = %d\n", __func__, event);
  2900. switch (event) {
  2901. case SND_SOC_DAPM_PRE_PMU:
  2902. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2903. case SND_SOC_DAPM_POST_PMD:
  2904. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2905. }
  2906. return 0;
  2907. }
  2908. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2909. struct snd_kcontrol *kcontrol, int event)
  2910. {
  2911. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2912. pr_debug("%s: event = %d\n", __func__, event);
  2913. switch (event) {
  2914. case SND_SOC_DAPM_PRE_PMU:
  2915. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2916. case SND_SOC_DAPM_POST_PMD:
  2917. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2918. }
  2919. return 0;
  2920. }
  2921. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2922. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2923. msm_mclk_event,
  2924. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2925. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2926. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2927. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2928. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2929. };
  2930. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2931. struct snd_kcontrol *kcontrol, int event)
  2932. {
  2933. struct msm_asoc_mach_data *pdata = NULL;
  2934. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2935. int ret = 0;
  2936. uint32_t dmic_idx;
  2937. int *dmic_gpio_cnt;
  2938. struct device_node *dmic_gpio;
  2939. char *wname;
  2940. wname = strpbrk(w->name, "01234567");
  2941. if (!wname) {
  2942. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2943. return -EINVAL;
  2944. }
  2945. ret = kstrtouint(wname, 10, &dmic_idx);
  2946. if (ret < 0) {
  2947. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2948. __func__);
  2949. return -EINVAL;
  2950. }
  2951. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2952. switch (dmic_idx) {
  2953. case 0:
  2954. case 1:
  2955. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2956. dmic_gpio = pdata->dmic_01_gpio_p;
  2957. break;
  2958. case 2:
  2959. case 3:
  2960. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2961. dmic_gpio = pdata->dmic_23_gpio_p;
  2962. break;
  2963. case 4:
  2964. case 5:
  2965. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2966. dmic_gpio = pdata->dmic_45_gpio_p;
  2967. break;
  2968. case 6:
  2969. case 7:
  2970. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2971. dmic_gpio = pdata->dmic_67_gpio_p;
  2972. break;
  2973. default:
  2974. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2975. __func__);
  2976. return -EINVAL;
  2977. }
  2978. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2979. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2980. switch (event) {
  2981. case SND_SOC_DAPM_PRE_PMU:
  2982. (*dmic_gpio_cnt)++;
  2983. if (*dmic_gpio_cnt == 1) {
  2984. ret = msm_cdc_pinctrl_select_active_state(
  2985. dmic_gpio);
  2986. if (ret < 0) {
  2987. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2988. __func__, "dmic_gpio");
  2989. return ret;
  2990. }
  2991. }
  2992. break;
  2993. case SND_SOC_DAPM_POST_PMD:
  2994. (*dmic_gpio_cnt)--;
  2995. if (*dmic_gpio_cnt == 0) {
  2996. ret = msm_cdc_pinctrl_select_sleep_state(
  2997. dmic_gpio);
  2998. if (ret < 0) {
  2999. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3000. __func__, "dmic_gpio");
  3001. return ret;
  3002. }
  3003. }
  3004. break;
  3005. default:
  3006. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3007. __func__, event);
  3008. return -EINVAL;
  3009. }
  3010. return 0;
  3011. }
  3012. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3013. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3014. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3015. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3016. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3017. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3018. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3019. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3020. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3021. };
  3022. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3023. };
  3024. static inline int param_is_mask(int p)
  3025. {
  3026. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3027. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3028. }
  3029. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3030. int n)
  3031. {
  3032. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3033. }
  3034. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3035. unsigned int bit)
  3036. {
  3037. if (bit >= SNDRV_MASK_MAX)
  3038. return;
  3039. if (param_is_mask(n)) {
  3040. struct snd_mask *m = param_to_mask(p, n);
  3041. m->bits[0] = 0;
  3042. m->bits[1] = 0;
  3043. m->bits[bit >> 5] |= (1 << (bit & 31));
  3044. }
  3045. }
  3046. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3047. {
  3048. int ch_id = 0;
  3049. switch (be_id) {
  3050. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3051. ch_id = SLIM_RX_0;
  3052. break;
  3053. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3054. ch_id = SLIM_RX_1;
  3055. break;
  3056. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3057. ch_id = SLIM_RX_2;
  3058. break;
  3059. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3060. ch_id = SLIM_RX_3;
  3061. break;
  3062. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3063. ch_id = SLIM_RX_4;
  3064. break;
  3065. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3066. ch_id = SLIM_RX_6;
  3067. break;
  3068. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3069. ch_id = SLIM_TX_0;
  3070. break;
  3071. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3072. ch_id = SLIM_TX_3;
  3073. break;
  3074. default:
  3075. ch_id = SLIM_RX_0;
  3076. break;
  3077. }
  3078. return ch_id;
  3079. }
  3080. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3081. {
  3082. *port_id = 0xFFFF;
  3083. switch (be_id) {
  3084. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3085. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3086. break;
  3087. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3088. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3089. break;
  3090. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3091. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3092. break;
  3093. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3094. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3095. break;
  3096. default:
  3097. return -EINVAL;
  3098. }
  3099. return 0;
  3100. }
  3101. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3102. {
  3103. int idx = 0;
  3104. switch (be_id) {
  3105. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3106. idx = WSA_CDC_DMA_RX_0;
  3107. break;
  3108. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3109. idx = WSA_CDC_DMA_TX_0;
  3110. break;
  3111. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3112. idx = WSA_CDC_DMA_RX_1;
  3113. break;
  3114. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3115. idx = WSA_CDC_DMA_TX_1;
  3116. break;
  3117. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3118. idx = WSA_CDC_DMA_TX_2;
  3119. break;
  3120. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3121. idx = VA_CDC_DMA_TX_0;
  3122. break;
  3123. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3124. idx = VA_CDC_DMA_TX_1;
  3125. break;
  3126. default:
  3127. idx = VA_CDC_DMA_TX_0;
  3128. break;
  3129. }
  3130. return idx;
  3131. }
  3132. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3133. struct snd_pcm_hw_params *params)
  3134. {
  3135. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3136. struct snd_interval *rate = hw_param_interval(params,
  3137. SNDRV_PCM_HW_PARAM_RATE);
  3138. struct snd_interval *channels = hw_param_interval(params,
  3139. SNDRV_PCM_HW_PARAM_CHANNELS);
  3140. int rc = 0;
  3141. int idx;
  3142. void *config = NULL;
  3143. struct snd_soc_codec *codec = NULL;
  3144. pr_debug("%s: format = %d, rate = %d\n",
  3145. __func__, params_format(params), params_rate(params));
  3146. switch (dai_link->id) {
  3147. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3148. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3149. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3150. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3151. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3152. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3153. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3154. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3155. slim_rx_cfg[idx].bit_format);
  3156. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3157. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3158. break;
  3159. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3160. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3161. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3162. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3163. slim_tx_cfg[idx].bit_format);
  3164. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3165. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3166. break;
  3167. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3168. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3169. slim_tx_cfg[1].bit_format);
  3170. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3171. channels->min = channels->max = slim_tx_cfg[1].channels;
  3172. break;
  3173. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3174. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3175. SNDRV_PCM_FORMAT_S32_LE);
  3176. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3177. channels->min = channels->max = msm_vi_feed_tx_ch;
  3178. break;
  3179. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3180. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3181. slim_rx_cfg[5].bit_format);
  3182. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3183. channels->min = channels->max = slim_rx_cfg[5].channels;
  3184. break;
  3185. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3186. codec = rtd->codec;
  3187. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3188. channels->min = channels->max = 1;
  3189. config = msm_codec_fn.get_afe_config_fn(codec,
  3190. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3191. if (config) {
  3192. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3193. config, SLIMBUS_5_TX);
  3194. if (rc)
  3195. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3196. __func__, rc);
  3197. }
  3198. break;
  3199. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3200. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3201. slim_rx_cfg[SLIM_RX_7].bit_format);
  3202. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3203. channels->min = channels->max =
  3204. slim_rx_cfg[SLIM_RX_7].channels;
  3205. break;
  3206. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3207. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3208. channels->min = channels->max =
  3209. slim_tx_cfg[SLIM_TX_7].channels;
  3210. break;
  3211. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3212. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3213. channels->min = channels->max =
  3214. slim_tx_cfg[SLIM_TX_8].channels;
  3215. break;
  3216. case MSM_BACKEND_DAI_USB_RX:
  3217. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3218. usb_rx_cfg.bit_format);
  3219. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3220. channels->min = channels->max = usb_rx_cfg.channels;
  3221. break;
  3222. case MSM_BACKEND_DAI_USB_TX:
  3223. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3224. usb_tx_cfg.bit_format);
  3225. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3226. channels->min = channels->max = usb_tx_cfg.channels;
  3227. break;
  3228. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3229. channels->min = channels->max = proxy_rx_cfg.channels;
  3230. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3231. break;
  3232. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3233. channels->min = channels->max =
  3234. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3235. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3236. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3237. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3238. break;
  3239. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3240. channels->min = channels->max =
  3241. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3242. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3243. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3244. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3245. break;
  3246. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3247. channels->min = channels->max =
  3248. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3249. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3250. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3251. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3252. break;
  3253. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3254. channels->min = channels->max =
  3255. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3256. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3257. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3258. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3259. break;
  3260. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3261. channels->min = channels->max =
  3262. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3263. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3264. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3265. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3266. break;
  3267. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3268. channels->min = channels->max =
  3269. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3270. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3271. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3272. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3273. break;
  3274. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3275. channels->min = channels->max =
  3276. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3277. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3278. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3279. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3280. break;
  3281. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3282. channels->min = channels->max =
  3283. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3284. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3285. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3286. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3287. break;
  3288. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3289. channels->min = channels->max =
  3290. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3291. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3292. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3293. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3294. break;
  3295. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3296. channels->min = channels->max =
  3297. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3298. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3299. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3300. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3301. break;
  3302. case MSM_BACKEND_DAI_AUXPCM_RX:
  3303. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3304. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3305. rate->min = rate->max =
  3306. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3307. channels->min = channels->max =
  3308. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3309. break;
  3310. case MSM_BACKEND_DAI_AUXPCM_TX:
  3311. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3312. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3313. rate->min = rate->max =
  3314. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3315. channels->min = channels->max =
  3316. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3317. break;
  3318. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3319. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3320. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3321. rate->min = rate->max =
  3322. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3323. channels->min = channels->max =
  3324. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3325. break;
  3326. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3327. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3328. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3329. rate->min = rate->max =
  3330. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3331. channels->min = channels->max =
  3332. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3333. break;
  3334. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3335. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3336. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3337. rate->min = rate->max =
  3338. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3339. channels->min = channels->max =
  3340. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3341. break;
  3342. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3343. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3344. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3345. rate->min = rate->max =
  3346. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3347. channels->min = channels->max =
  3348. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3349. break;
  3350. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3351. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3352. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3353. rate->min = rate->max =
  3354. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3355. channels->min = channels->max =
  3356. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3357. break;
  3358. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3359. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3360. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3361. rate->min = rate->max =
  3362. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3363. channels->min = channels->max =
  3364. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3365. break;
  3366. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3367. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3368. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3369. rate->min = rate->max =
  3370. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3371. channels->min = channels->max =
  3372. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3373. break;
  3374. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3375. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3376. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3377. rate->min = rate->max =
  3378. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3379. channels->min = channels->max =
  3380. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3381. break;
  3382. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3383. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3384. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3385. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3386. channels->min = channels->max =
  3387. mi2s_rx_cfg[PRIM_MI2S].channels;
  3388. break;
  3389. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3390. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3391. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3392. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3393. channels->min = channels->max =
  3394. mi2s_tx_cfg[PRIM_MI2S].channels;
  3395. break;
  3396. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3397. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3398. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3399. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3400. channels->min = channels->max =
  3401. mi2s_rx_cfg[SEC_MI2S].channels;
  3402. break;
  3403. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3404. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3405. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3406. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3407. channels->min = channels->max =
  3408. mi2s_tx_cfg[SEC_MI2S].channels;
  3409. break;
  3410. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3411. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3412. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3413. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3414. channels->min = channels->max =
  3415. mi2s_rx_cfg[TERT_MI2S].channels;
  3416. break;
  3417. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3418. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3419. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3420. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3421. channels->min = channels->max =
  3422. mi2s_tx_cfg[TERT_MI2S].channels;
  3423. break;
  3424. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3425. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3426. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3427. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3428. channels->min = channels->max =
  3429. mi2s_rx_cfg[QUAT_MI2S].channels;
  3430. break;
  3431. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3432. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3433. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3434. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3435. channels->min = channels->max =
  3436. mi2s_tx_cfg[QUAT_MI2S].channels;
  3437. break;
  3438. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3439. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3440. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3441. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3442. channels->min = channels->max =
  3443. mi2s_rx_cfg[QUIN_MI2S].channels;
  3444. break;
  3445. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3446. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3447. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3448. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3449. channels->min = channels->max =
  3450. mi2s_tx_cfg[QUIN_MI2S].channels;
  3451. break;
  3452. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3453. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3454. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3455. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3456. cdc_dma_rx_cfg[idx].bit_format);
  3457. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3458. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3459. break;
  3460. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3461. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3462. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3463. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3464. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3465. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3466. cdc_dma_tx_cfg[idx].bit_format);
  3467. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3468. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3469. break;
  3470. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3471. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3472. SNDRV_PCM_FORMAT_S32_LE);
  3473. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3474. channels->min = channels->max = msm_vi_feed_tx_ch;
  3475. break;
  3476. default:
  3477. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3478. break;
  3479. }
  3480. return rc;
  3481. }
  3482. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3483. {
  3484. int ret = 0;
  3485. void *config_data = NULL;
  3486. if (!msm_codec_fn.get_afe_config_fn) {
  3487. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3488. __func__);
  3489. return -EINVAL;
  3490. }
  3491. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3492. AFE_CDC_REGISTERS_CONFIG);
  3493. if (config_data) {
  3494. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3495. if (ret) {
  3496. dev_err(codec->dev,
  3497. "%s: Failed to set codec registers config %d\n",
  3498. __func__, ret);
  3499. return ret;
  3500. }
  3501. }
  3502. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3503. AFE_CDC_REGISTER_PAGE_CONFIG);
  3504. if (config_data) {
  3505. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3506. 0);
  3507. if (ret)
  3508. dev_err(codec->dev,
  3509. "%s: Failed to set cdc register page config\n",
  3510. __func__);
  3511. }
  3512. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3513. AFE_SLIMBUS_SLAVE_CONFIG);
  3514. if (config_data) {
  3515. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3516. if (ret) {
  3517. dev_err(codec->dev,
  3518. "%s: Failed to set slimbus slave config %d\n",
  3519. __func__, ret);
  3520. return ret;
  3521. }
  3522. }
  3523. return 0;
  3524. }
  3525. static void msm_afe_clear_config(void)
  3526. {
  3527. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3528. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3529. }
  3530. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3531. struct snd_card *card)
  3532. {
  3533. int ret = 0;
  3534. unsigned long timeout;
  3535. int adsp_ready = 0;
  3536. bool snd_card_online = 0;
  3537. timeout = jiffies +
  3538. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3539. do {
  3540. if (!snd_card_online) {
  3541. snd_card_online = snd_card_is_online_state(card);
  3542. pr_debug("%s: Sound card is %s\n", __func__,
  3543. snd_card_online ? "Online" : "Offline");
  3544. }
  3545. if (!adsp_ready) {
  3546. adsp_ready = q6core_is_adsp_ready();
  3547. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3548. adsp_ready ? "ready" : "not ready");
  3549. }
  3550. if (snd_card_online && adsp_ready)
  3551. break;
  3552. /*
  3553. * Sound card/ADSP will be coming up after subsystem restart and
  3554. * it might not be fully up when the control reaches
  3555. * here. So, wait for 50msec before checking ADSP state
  3556. */
  3557. msleep(50);
  3558. } while (time_after(timeout, jiffies));
  3559. if (!snd_card_online || !adsp_ready) {
  3560. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3561. __func__,
  3562. snd_card_online ? "Online" : "Offline",
  3563. adsp_ready ? "ready" : "not ready");
  3564. ret = -ETIMEDOUT;
  3565. goto err;
  3566. }
  3567. ret = msm_afe_set_config(codec);
  3568. if (ret)
  3569. pr_err("%s: Failed to set AFE config. err %d\n",
  3570. __func__, ret);
  3571. return 0;
  3572. err:
  3573. return ret;
  3574. }
  3575. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3576. unsigned long opcode, void *ptr)
  3577. {
  3578. int ret;
  3579. struct snd_soc_card *card = NULL;
  3580. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3581. struct snd_soc_pcm_runtime *rtd;
  3582. struct snd_soc_codec *codec;
  3583. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3584. switch (opcode) {
  3585. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3586. /*
  3587. * Use flag to ignore initial boot notifications
  3588. * On initial boot msm_adsp_power_up_config is
  3589. * called on init. There is no need to clear
  3590. * and set the config again on initial boot.
  3591. */
  3592. if (is_initial_boot)
  3593. break;
  3594. msm_afe_clear_config();
  3595. break;
  3596. case AUDIO_NOTIFIER_SERVICE_UP:
  3597. if (is_initial_boot) {
  3598. is_initial_boot = false;
  3599. break;
  3600. }
  3601. if (!spdev)
  3602. return -EINVAL;
  3603. card = platform_get_drvdata(spdev);
  3604. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3605. if (!rtd) {
  3606. dev_err(card->dev,
  3607. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3608. __func__, be_dl_name);
  3609. ret = -EINVAL;
  3610. goto err;
  3611. }
  3612. codec = rtd->codec;
  3613. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3614. if (ret < 0) {
  3615. dev_err(card->dev,
  3616. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3617. __func__, ret);
  3618. goto err;
  3619. }
  3620. break;
  3621. default:
  3622. break;
  3623. }
  3624. err:
  3625. return NOTIFY_OK;
  3626. }
  3627. static struct notifier_block service_nb = {
  3628. .notifier_call = qcs405_notifier_service_cb,
  3629. .priority = -INT_MAX,
  3630. };
  3631. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3632. {
  3633. int ret = 0;
  3634. void *config_data;
  3635. struct snd_soc_codec *codec = rtd->codec;
  3636. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3637. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3638. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3639. struct snd_card *card;
  3640. struct msm_asoc_mach_data *pdata =
  3641. snd_soc_card_get_drvdata(rtd->card);
  3642. /*
  3643. * Codec SLIMBUS configuration
  3644. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3645. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3646. * TX14, TX15, TX16
  3647. */
  3648. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3649. 151, 152, 153, 154, 155, 156};
  3650. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3651. 134, 135, 136, 137, 138, 139,
  3652. 140, 141, 142, 143};
  3653. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3654. rtd->pmdown_time = 0;
  3655. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3656. ARRAY_SIZE(msm_snd_sb_controls));
  3657. if (ret < 0) {
  3658. pr_err("%s: add_codec_controls failed, err %d\n",
  3659. __func__, ret);
  3660. return ret;
  3661. }
  3662. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3663. ARRAY_SIZE(msm_dapm_widgets));
  3664. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3665. ARRAY_SIZE(wcd_audio_paths));
  3666. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3667. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3668. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3669. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3670. snd_soc_dapm_sync(dapm);
  3671. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3672. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3673. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3674. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3675. if (ret) {
  3676. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3677. __func__, ret);
  3678. goto err;
  3679. }
  3680. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3681. AFE_AANC_VERSION);
  3682. if (config_data) {
  3683. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3684. if (ret) {
  3685. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3686. __func__, ret);
  3687. goto err;
  3688. }
  3689. }
  3690. card = rtd->card->snd_card;
  3691. if (!pdata->codec_root)
  3692. pdata->codec_root = snd_info_create_subdir(card->module,
  3693. "codecs", card->proc_root);
  3694. if (!pdata->codec_root) {
  3695. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  3696. __func__);
  3697. ret = 0;
  3698. goto err;
  3699. }
  3700. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3701. codec_reg_done = true;
  3702. return 0;
  3703. err:
  3704. return ret;
  3705. }
  3706. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3707. {
  3708. int ret = 0;
  3709. struct snd_soc_codec *codec = rtd->codec;
  3710. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3711. struct snd_card *card;
  3712. struct msm_asoc_mach_data *pdata =
  3713. snd_soc_card_get_drvdata(rtd->card);
  3714. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3715. ARRAY_SIZE(msm_snd_va_controls));
  3716. if (ret < 0) {
  3717. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3718. __func__, ret);
  3719. return ret;
  3720. }
  3721. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3722. ARRAY_SIZE(msm_va_dapm_widgets));
  3723. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3724. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3725. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3726. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3727. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3728. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3729. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3730. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3731. snd_soc_dapm_sync(dapm);
  3732. card = rtd->card->snd_card;
  3733. if (!pdata->codec_root)
  3734. pdata->codec_root = snd_info_create_subdir(card->module,
  3735. "codecs", card->proc_root);
  3736. if (!pdata->codec_root) {
  3737. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  3738. __func__);
  3739. ret = 0;
  3740. goto done;
  3741. }
  3742. bolero_info_create_codec_entry(pdata->codec_root, codec);
  3743. done:
  3744. return ret;
  3745. }
  3746. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3747. {
  3748. int ret = 0;
  3749. struct snd_soc_codec *codec = rtd->codec;
  3750. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3751. struct snd_soc_component *aux_comp;
  3752. struct snd_card *card;
  3753. struct msm_asoc_mach_data *pdata =
  3754. snd_soc_card_get_drvdata(rtd->card);
  3755. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3756. ARRAY_SIZE(msm_snd_wsa_controls));
  3757. if (ret < 0) {
  3758. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  3759. __func__, ret);
  3760. return ret;
  3761. }
  3762. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3763. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3764. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3765. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3766. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3767. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3768. snd_soc_dapm_sync(dapm);
  3769. /*
  3770. * Send speaker configuration only for WSA8810.
  3771. * Default configuration is for WSA8815.
  3772. */
  3773. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  3774. __func__, rtd->card->num_aux_devs);
  3775. if (rtd->card->num_aux_devs &&
  3776. !list_empty(&rtd->card->component_dev_list)) {
  3777. aux_comp = list_first_entry(
  3778. &rtd->card->component_dev_list,
  3779. struct snd_soc_component,
  3780. card_aux_list);
  3781. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  3782. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  3783. wsa_macro_set_spkr_mode(rtd->codec,
  3784. WSA_MACRO_SPKR_MODE_1);
  3785. wsa_macro_set_spkr_gain_offset(rtd->codec,
  3786. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  3787. }
  3788. }
  3789. card = rtd->card->snd_card;
  3790. if (!pdata->codec_root)
  3791. pdata->codec_root = snd_info_create_subdir(card->module,
  3792. "codecs", card->proc_root);
  3793. if (!pdata->codec_root) {
  3794. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  3795. __func__);
  3796. ret = 0;
  3797. goto done;
  3798. }
  3799. bolero_info_create_codec_entry(pdata->codec_root, codec);
  3800. done:
  3801. return ret;
  3802. }
  3803. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3804. {
  3805. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3806. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3807. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3808. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3809. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3810. }
  3811. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3812. struct snd_pcm_hw_params *params)
  3813. {
  3814. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3815. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3816. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3817. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3818. int ret = 0;
  3819. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3820. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3821. u32 user_set_tx_ch = 0;
  3822. u32 rx_ch_count;
  3823. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3824. ret = snd_soc_dai_get_channel_map(codec_dai,
  3825. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3826. if (ret < 0) {
  3827. pr_err("%s: failed to get codec chan map, err:%d\n",
  3828. __func__, ret);
  3829. goto err;
  3830. }
  3831. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3832. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3833. slim_rx_cfg[5].channels);
  3834. rx_ch_count = slim_rx_cfg[5].channels;
  3835. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3836. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3837. slim_rx_cfg[2].channels);
  3838. rx_ch_count = slim_rx_cfg[2].channels;
  3839. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3840. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3841. slim_rx_cfg[6].channels);
  3842. rx_ch_count = slim_rx_cfg[6].channels;
  3843. } else {
  3844. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3845. slim_rx_cfg[0].channels);
  3846. rx_ch_count = slim_rx_cfg[0].channels;
  3847. }
  3848. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3849. rx_ch_count, rx_ch);
  3850. if (ret < 0) {
  3851. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3852. __func__, ret);
  3853. goto err;
  3854. }
  3855. } else {
  3856. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3857. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3858. ret = snd_soc_dai_get_channel_map(codec_dai,
  3859. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3860. if (ret < 0) {
  3861. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3862. __func__, ret);
  3863. goto err;
  3864. }
  3865. /* For <codec>_tx1 case */
  3866. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3867. user_set_tx_ch = slim_tx_cfg[0].channels;
  3868. /* For <codec>_tx3 case */
  3869. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3870. user_set_tx_ch = slim_tx_cfg[1].channels;
  3871. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3872. user_set_tx_ch = msm_vi_feed_tx_ch;
  3873. else
  3874. user_set_tx_ch = tx_ch_cnt;
  3875. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3876. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3877. tx_ch_cnt, dai_link->id);
  3878. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3879. user_set_tx_ch, tx_ch, 0, 0);
  3880. if (ret < 0)
  3881. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3882. __func__, ret);
  3883. }
  3884. err:
  3885. return ret;
  3886. }
  3887. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3888. struct snd_pcm_hw_params *params)
  3889. {
  3890. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3891. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3892. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3893. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3894. int ret = 0;
  3895. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3896. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3897. u32 user_set_tx_ch = 0;
  3898. u32 user_set_rx_ch = 0;
  3899. u32 ch_id;
  3900. ret = snd_soc_dai_get_channel_map(codec_dai,
  3901. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3902. &rx_ch_cdc_dma);
  3903. if (ret < 0) {
  3904. pr_err("%s: failed to get codec chan map, err:%d\n",
  3905. __func__, ret);
  3906. goto err;
  3907. }
  3908. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3909. switch (dai_link->id) {
  3910. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3911. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3912. {
  3913. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3914. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3915. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3916. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3917. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3918. user_set_rx_ch, &rx_ch_cdc_dma);
  3919. if (ret < 0) {
  3920. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3921. __func__, ret);
  3922. goto err;
  3923. }
  3924. }
  3925. break;
  3926. }
  3927. } else {
  3928. switch (dai_link->id) {
  3929. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3930. {
  3931. user_set_tx_ch = msm_vi_feed_tx_ch;
  3932. }
  3933. break;
  3934. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3935. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3936. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3937. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3938. {
  3939. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3940. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3941. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3942. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3943. }
  3944. break;
  3945. }
  3946. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3947. &tx_ch_cdc_dma, 0, 0);
  3948. if (ret < 0) {
  3949. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3950. __func__, ret);
  3951. goto err;
  3952. }
  3953. }
  3954. err:
  3955. return ret;
  3956. }
  3957. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3958. struct snd_pcm_hw_params *params)
  3959. {
  3960. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3961. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3962. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3963. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3964. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3965. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3966. int ret;
  3967. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3968. codec_dai->name, codec_dai->id);
  3969. ret = snd_soc_dai_get_channel_map(codec_dai,
  3970. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3971. if (ret) {
  3972. dev_err(rtd->dev,
  3973. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3974. __func__, ret);
  3975. goto err;
  3976. }
  3977. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3978. __func__, tx_ch_cnt, dai_link->id);
  3979. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3980. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3981. if (ret)
  3982. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3983. __func__, ret);
  3984. err:
  3985. return ret;
  3986. }
  3987. static int msm_get_port_id(int be_id)
  3988. {
  3989. int afe_port_id;
  3990. switch (be_id) {
  3991. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3992. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3993. break;
  3994. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3995. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3996. break;
  3997. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3998. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3999. break;
  4000. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4001. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4002. break;
  4003. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4004. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4005. break;
  4006. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4007. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4008. break;
  4009. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4010. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4011. break;
  4012. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4013. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4014. break;
  4015. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4016. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4017. break;
  4018. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4019. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4020. break;
  4021. default:
  4022. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4023. afe_port_id = -EINVAL;
  4024. }
  4025. return afe_port_id;
  4026. }
  4027. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4028. {
  4029. u32 bit_per_sample;
  4030. switch (bit_format) {
  4031. case SNDRV_PCM_FORMAT_S32_LE:
  4032. case SNDRV_PCM_FORMAT_S24_3LE:
  4033. case SNDRV_PCM_FORMAT_S24_LE:
  4034. bit_per_sample = 32;
  4035. break;
  4036. case SNDRV_PCM_FORMAT_S16_LE:
  4037. default:
  4038. bit_per_sample = 16;
  4039. break;
  4040. }
  4041. return bit_per_sample;
  4042. }
  4043. static void update_mi2s_clk_val(int dai_id, int stream)
  4044. {
  4045. u32 bit_per_sample;
  4046. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4047. bit_per_sample =
  4048. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4049. mi2s_clk[dai_id].clk_freq_in_hz =
  4050. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4051. } else {
  4052. bit_per_sample =
  4053. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4054. mi2s_clk[dai_id].clk_freq_in_hz =
  4055. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4056. }
  4057. }
  4058. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4059. {
  4060. int ret = 0;
  4061. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4062. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4063. int port_id = 0;
  4064. int index = cpu_dai->id;
  4065. port_id = msm_get_port_id(rtd->dai_link->id);
  4066. if (port_id < 0) {
  4067. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4068. ret = port_id;
  4069. goto err;
  4070. }
  4071. if (enable) {
  4072. update_mi2s_clk_val(index, substream->stream);
  4073. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4074. mi2s_clk[index].clk_freq_in_hz);
  4075. }
  4076. mi2s_clk[index].enable = enable;
  4077. ret = afe_set_lpass_clock_v2(port_id,
  4078. &mi2s_clk[index]);
  4079. if (ret < 0) {
  4080. dev_err(rtd->card->dev,
  4081. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4082. __func__, port_id, ret);
  4083. goto err;
  4084. }
  4085. err:
  4086. return ret;
  4087. }
  4088. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4089. enum pinctrl_pin_state new_state)
  4090. {
  4091. int ret = 0;
  4092. int curr_state = 0;
  4093. if (pinctrl_info == NULL) {
  4094. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4095. ret = -EINVAL;
  4096. goto err;
  4097. }
  4098. if (pinctrl_info->pinctrl == NULL) {
  4099. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4100. ret = -EINVAL;
  4101. goto err;
  4102. }
  4103. curr_state = pinctrl_info->curr_state;
  4104. pinctrl_info->curr_state = new_state;
  4105. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4106. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4107. if (curr_state == pinctrl_info->curr_state) {
  4108. pr_debug("%s: Already in same state\n", __func__);
  4109. goto err;
  4110. }
  4111. if (curr_state != STATE_DISABLE &&
  4112. pinctrl_info->curr_state != STATE_DISABLE) {
  4113. pr_debug("%s: state already active cannot switch\n", __func__);
  4114. ret = -EIO;
  4115. goto err;
  4116. }
  4117. switch (pinctrl_info->curr_state) {
  4118. case STATE_MI2S_ACTIVE:
  4119. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4120. pinctrl_info->mi2s_active);
  4121. if (ret) {
  4122. pr_err("%s: MI2S state select failed with %d\n",
  4123. __func__, ret);
  4124. ret = -EIO;
  4125. goto err;
  4126. }
  4127. break;
  4128. case STATE_TDM_ACTIVE:
  4129. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4130. pinctrl_info->tdm_active);
  4131. if (ret) {
  4132. pr_err("%s: TDM state select failed with %d\n",
  4133. __func__, ret);
  4134. ret = -EIO;
  4135. goto err;
  4136. }
  4137. break;
  4138. case STATE_DISABLE:
  4139. if (curr_state == STATE_MI2S_ACTIVE) {
  4140. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4141. pinctrl_info->mi2s_disable);
  4142. } else {
  4143. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4144. pinctrl_info->tdm_disable);
  4145. }
  4146. if (ret) {
  4147. pr_err("%s: state disable failed with %d\n",
  4148. __func__, ret);
  4149. ret = -EIO;
  4150. goto err;
  4151. }
  4152. break;
  4153. default:
  4154. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4155. return -EINVAL;
  4156. }
  4157. err:
  4158. return ret;
  4159. }
  4160. static void msm_release_pinctrl(struct platform_device *pdev)
  4161. {
  4162. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4163. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4164. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4165. if (pinctrl_info->pinctrl) {
  4166. devm_pinctrl_put(pinctrl_info->pinctrl);
  4167. pinctrl_info->pinctrl = NULL;
  4168. }
  4169. }
  4170. static int msm_get_pinctrl(struct platform_device *pdev)
  4171. {
  4172. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4173. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4174. struct msm_pinctrl_info *pinctrl_info = NULL;
  4175. struct pinctrl *pinctrl;
  4176. int ret;
  4177. pinctrl_info = &pdata->pinctrl_info;
  4178. if (pinctrl_info == NULL) {
  4179. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4180. return -EINVAL;
  4181. }
  4182. pinctrl = devm_pinctrl_get(&pdev->dev);
  4183. if (IS_ERR_OR_NULL(pinctrl)) {
  4184. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4185. return -EINVAL;
  4186. }
  4187. pinctrl_info->pinctrl = pinctrl;
  4188. /* get all the states handles from Device Tree */
  4189. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4190. "quat-mi2s-sleep");
  4191. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4192. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4193. goto err;
  4194. }
  4195. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4196. "quat-mi2s-active");
  4197. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4198. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4199. goto err;
  4200. }
  4201. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4202. "quat-tdm-sleep");
  4203. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4204. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4205. goto err;
  4206. }
  4207. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4208. "quat-tdm-active");
  4209. if (IS_ERR(pinctrl_info->tdm_active)) {
  4210. pr_err("%s: could not get tdm_active pinstate\n",
  4211. __func__);
  4212. goto err;
  4213. }
  4214. /* Reset the TLMM pins to a default state */
  4215. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4216. pinctrl_info->mi2s_disable);
  4217. if (ret != 0) {
  4218. pr_err("%s: Disable TLMM pins failed with %d\n",
  4219. __func__, ret);
  4220. ret = -EIO;
  4221. goto err;
  4222. }
  4223. pinctrl_info->curr_state = STATE_DISABLE;
  4224. return 0;
  4225. err:
  4226. devm_pinctrl_put(pinctrl);
  4227. pinctrl_info->pinctrl = NULL;
  4228. return -EINVAL;
  4229. }
  4230. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4231. struct snd_pcm_hw_params *params)
  4232. {
  4233. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4234. struct snd_interval *rate = hw_param_interval(params,
  4235. SNDRV_PCM_HW_PARAM_RATE);
  4236. struct snd_interval *channels = hw_param_interval(params,
  4237. SNDRV_PCM_HW_PARAM_CHANNELS);
  4238. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4239. channels->min = channels->max =
  4240. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4241. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4242. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4243. rate->min = rate->max =
  4244. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4245. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4246. channels->min = channels->max =
  4247. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4248. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4249. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4250. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4251. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4252. channels->min = channels->max =
  4253. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4254. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4255. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4256. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4257. } else {
  4258. pr_err("%s: dai id 0x%x not supported\n",
  4259. __func__, cpu_dai->id);
  4260. return -EINVAL;
  4261. }
  4262. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4263. __func__, cpu_dai->id, channels->max, rate->max,
  4264. params_format(params));
  4265. return 0;
  4266. }
  4267. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4268. struct snd_pcm_hw_params *params)
  4269. {
  4270. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4271. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4272. int ret = 0;
  4273. int slot_width = 32;
  4274. int channels, slots;
  4275. unsigned int slot_mask, rate, clk_freq;
  4276. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4277. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4278. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4279. switch (cpu_dai->id) {
  4280. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4281. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4282. break;
  4283. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4284. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4285. break;
  4286. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4287. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4288. break;
  4289. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4290. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4291. break;
  4292. case AFE_PORT_ID_QUINARY_TDM_RX:
  4293. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4294. break;
  4295. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4296. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4297. break;
  4298. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4299. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4300. break;
  4301. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4302. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4303. break;
  4304. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4305. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4306. break;
  4307. case AFE_PORT_ID_QUINARY_TDM_TX:
  4308. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4309. break;
  4310. default:
  4311. pr_err("%s: dai id 0x%x not supported\n",
  4312. __func__, cpu_dai->id);
  4313. return -EINVAL;
  4314. }
  4315. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4316. /*2 slot config - bits 0 and 1 set for the first two slots */
  4317. slot_mask = 0x0000FFFF >> (16-slots);
  4318. channels = slots;
  4319. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4320. __func__, slot_width, slots);
  4321. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4322. slots, slot_width);
  4323. if (ret < 0) {
  4324. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4325. __func__, ret);
  4326. goto end;
  4327. }
  4328. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4329. 0, NULL, channels, slot_offset);
  4330. if (ret < 0) {
  4331. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4332. __func__, ret);
  4333. goto end;
  4334. }
  4335. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4336. /*2 slot config - bits 0 and 1 set for the first two slots */
  4337. slot_mask = 0x0000FFFF >> (16-slots);
  4338. channels = slots;
  4339. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4340. __func__, slot_width, slots);
  4341. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4342. slots, slot_width);
  4343. if (ret < 0) {
  4344. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4345. __func__, ret);
  4346. goto end;
  4347. }
  4348. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4349. channels, slot_offset, 0, NULL);
  4350. if (ret < 0) {
  4351. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4352. __func__, ret);
  4353. goto end;
  4354. }
  4355. } else {
  4356. ret = -EINVAL;
  4357. pr_err("%s: invalid use case, err:%d\n",
  4358. __func__, ret);
  4359. goto end;
  4360. }
  4361. rate = params_rate(params);
  4362. clk_freq = rate * slot_width * slots;
  4363. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4364. if (ret < 0)
  4365. pr_err("%s: failed to set tdm clk, err:%d\n",
  4366. __func__, ret);
  4367. end:
  4368. return ret;
  4369. }
  4370. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4371. {
  4372. int ret = 0;
  4373. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4374. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4375. struct snd_soc_card *card = rtd->card;
  4376. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4377. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4378. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4379. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4380. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4381. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4382. if (ret)
  4383. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4384. __func__, ret);
  4385. }
  4386. return ret;
  4387. }
  4388. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4389. {
  4390. int ret = 0;
  4391. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4392. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4393. struct snd_soc_card *card = rtd->card;
  4394. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4395. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4396. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4397. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4398. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4399. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4400. if (ret)
  4401. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4402. __func__, ret);
  4403. }
  4404. }
  4405. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4406. .hw_params = qcs405_tdm_snd_hw_params,
  4407. .startup = qcs405_tdm_snd_startup,
  4408. .shutdown = qcs405_tdm_snd_shutdown
  4409. };
  4410. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4411. {
  4412. cpumask_t mask;
  4413. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4414. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4415. cpumask_clear(&mask);
  4416. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4417. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4418. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4419. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4420. pm_qos_add_request(&substream->latency_pm_qos_req,
  4421. PM_QOS_CPU_DMA_LATENCY,
  4422. MSM_LL_QOS_VALUE);
  4423. return 0;
  4424. }
  4425. static struct snd_soc_ops msm_fe_qos_ops = {
  4426. .prepare = msm_fe_qos_prepare,
  4427. };
  4428. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4429. {
  4430. int ret = 0;
  4431. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4432. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4433. int index = cpu_dai->id;
  4434. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4435. struct snd_soc_card *card = rtd->card;
  4436. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4437. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4438. int ret_pinctrl = 0;
  4439. dev_dbg(rtd->card->dev,
  4440. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4441. __func__, substream->name, substream->stream,
  4442. cpu_dai->name, cpu_dai->id);
  4443. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4444. ret = -EINVAL;
  4445. dev_err(rtd->card->dev,
  4446. "%s: CPU DAI id (%d) out of range\n",
  4447. __func__, cpu_dai->id);
  4448. goto err;
  4449. }
  4450. /*
  4451. * Mutex protection in case the same MI2S
  4452. * interface using for both TX and RX so
  4453. * that the same clock won't be enable twice.
  4454. */
  4455. mutex_lock(&mi2s_intf_conf[index].lock);
  4456. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4457. /* Check if msm needs to provide the clock to the interface */
  4458. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4459. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4460. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4461. }
  4462. ret = msm_mi2s_set_sclk(substream, true);
  4463. if (ret < 0) {
  4464. dev_err(rtd->card->dev,
  4465. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4466. __func__, ret);
  4467. goto clean_up;
  4468. }
  4469. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4470. if (ret < 0) {
  4471. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4472. __func__, index, ret);
  4473. goto clk_off;
  4474. }
  4475. if (index == QUAT_MI2S) {
  4476. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4477. STATE_MI2S_ACTIVE);
  4478. if (ret_pinctrl)
  4479. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4480. __func__, ret_pinctrl);
  4481. }
  4482. }
  4483. clk_off:
  4484. if (ret < 0)
  4485. msm_mi2s_set_sclk(substream, false);
  4486. clean_up:
  4487. if (ret < 0)
  4488. mi2s_intf_conf[index].ref_cnt--;
  4489. mutex_unlock(&mi2s_intf_conf[index].lock);
  4490. err:
  4491. return ret;
  4492. }
  4493. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4494. {
  4495. int ret;
  4496. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4497. int index = rtd->cpu_dai->id;
  4498. struct snd_soc_card *card = rtd->card;
  4499. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4500. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4501. int ret_pinctrl = 0;
  4502. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4503. substream->name, substream->stream);
  4504. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4505. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4506. return;
  4507. }
  4508. mutex_lock(&mi2s_intf_conf[index].lock);
  4509. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4510. ret = msm_mi2s_set_sclk(substream, false);
  4511. if (ret < 0)
  4512. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4513. __func__, index, ret);
  4514. if (index == QUAT_MI2S) {
  4515. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4516. STATE_DISABLE);
  4517. if (ret_pinctrl)
  4518. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4519. __func__, ret_pinctrl);
  4520. }
  4521. }
  4522. mutex_unlock(&mi2s_intf_conf[index].lock);
  4523. }
  4524. static struct snd_soc_ops msm_mi2s_be_ops = {
  4525. .startup = msm_mi2s_snd_startup,
  4526. .shutdown = msm_mi2s_snd_shutdown,
  4527. };
  4528. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4529. .hw_params = msm_snd_cdc_dma_hw_params,
  4530. };
  4531. static struct snd_soc_ops msm_be_ops = {
  4532. .hw_params = msm_snd_hw_params,
  4533. };
  4534. static struct snd_soc_ops msm_wcn_ops = {
  4535. .hw_params = msm_wcn_hw_params,
  4536. };
  4537. /* Digital audio interface glue - connects codec <---> CPU */
  4538. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4539. /* FrontEnd DAI Links */
  4540. {
  4541. .name = MSM_DAILINK_NAME(Media1),
  4542. .stream_name = "MultiMedia1",
  4543. .cpu_dai_name = "MultiMedia1",
  4544. .platform_name = "msm-pcm-dsp.0",
  4545. .dynamic = 1,
  4546. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4547. .dpcm_playback = 1,
  4548. .dpcm_capture = 1,
  4549. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4550. SND_SOC_DPCM_TRIGGER_POST},
  4551. .codec_dai_name = "snd-soc-dummy-dai",
  4552. .codec_name = "snd-soc-dummy",
  4553. .ignore_suspend = 1,
  4554. /* this dainlink has playback support */
  4555. .ignore_pmdown_time = 1,
  4556. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4557. },
  4558. {
  4559. .name = MSM_DAILINK_NAME(Media2),
  4560. .stream_name = "MultiMedia2",
  4561. .cpu_dai_name = "MultiMedia2",
  4562. .platform_name = "msm-pcm-dsp.0",
  4563. .dynamic = 1,
  4564. .dpcm_playback = 1,
  4565. .dpcm_capture = 1,
  4566. .codec_dai_name = "snd-soc-dummy-dai",
  4567. .codec_name = "snd-soc-dummy",
  4568. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4569. SND_SOC_DPCM_TRIGGER_POST},
  4570. .ignore_suspend = 1,
  4571. /* this dainlink has playback support */
  4572. .ignore_pmdown_time = 1,
  4573. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4574. },
  4575. {
  4576. .name = "VoiceMMode1",
  4577. .stream_name = "VoiceMMode1",
  4578. .cpu_dai_name = "VoiceMMode1",
  4579. .platform_name = "msm-pcm-voice",
  4580. .dynamic = 1,
  4581. .dpcm_playback = 1,
  4582. .dpcm_capture = 1,
  4583. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4584. SND_SOC_DPCM_TRIGGER_POST},
  4585. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4586. .ignore_suspend = 1,
  4587. .ignore_pmdown_time = 1,
  4588. .codec_dai_name = "snd-soc-dummy-dai",
  4589. .codec_name = "snd-soc-dummy",
  4590. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4591. },
  4592. {
  4593. .name = "MSM VoIP",
  4594. .stream_name = "VoIP",
  4595. .cpu_dai_name = "VoIP",
  4596. .platform_name = "msm-voip-dsp",
  4597. .dynamic = 1,
  4598. .dpcm_playback = 1,
  4599. .dpcm_capture = 1,
  4600. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4601. SND_SOC_DPCM_TRIGGER_POST},
  4602. .codec_dai_name = "snd-soc-dummy-dai",
  4603. .codec_name = "snd-soc-dummy",
  4604. .ignore_suspend = 1,
  4605. /* this dainlink has playback support */
  4606. .ignore_pmdown_time = 1,
  4607. .id = MSM_FRONTEND_DAI_VOIP,
  4608. },
  4609. {
  4610. .name = MSM_DAILINK_NAME(ULL),
  4611. .stream_name = "MultiMedia3",
  4612. .cpu_dai_name = "MultiMedia3",
  4613. .platform_name = "msm-pcm-dsp.2",
  4614. .dynamic = 1,
  4615. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4616. .dpcm_playback = 1,
  4617. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4618. SND_SOC_DPCM_TRIGGER_POST},
  4619. .codec_dai_name = "snd-soc-dummy-dai",
  4620. .codec_name = "snd-soc-dummy",
  4621. .ignore_suspend = 1,
  4622. /* this dainlink has playback support */
  4623. .ignore_pmdown_time = 1,
  4624. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4625. },
  4626. /* Hostless PCM purpose */
  4627. {
  4628. .name = "SLIMBUS_0 Hostless",
  4629. .stream_name = "SLIMBUS_0 Hostless",
  4630. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4631. .platform_name = "msm-pcm-hostless",
  4632. .dynamic = 1,
  4633. .dpcm_playback = 1,
  4634. .dpcm_capture = 1,
  4635. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4636. SND_SOC_DPCM_TRIGGER_POST},
  4637. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4638. .ignore_suspend = 1,
  4639. /* this dailink has playback support */
  4640. .ignore_pmdown_time = 1,
  4641. .codec_dai_name = "snd-soc-dummy-dai",
  4642. .codec_name = "snd-soc-dummy",
  4643. },
  4644. {
  4645. .name = "MSM AFE-PCM RX",
  4646. .stream_name = "AFE-PROXY RX",
  4647. .cpu_dai_name = "msm-dai-q6-dev.241",
  4648. .codec_name = "msm-stub-codec.1",
  4649. .codec_dai_name = "msm-stub-rx",
  4650. .platform_name = "msm-pcm-afe",
  4651. .dpcm_playback = 1,
  4652. .ignore_suspend = 1,
  4653. /* this dainlink has playback support */
  4654. .ignore_pmdown_time = 1,
  4655. },
  4656. {
  4657. .name = "MSM AFE-PCM TX",
  4658. .stream_name = "AFE-PROXY TX",
  4659. .cpu_dai_name = "msm-dai-q6-dev.240",
  4660. .codec_name = "msm-stub-codec.1",
  4661. .codec_dai_name = "msm-stub-tx",
  4662. .platform_name = "msm-pcm-afe",
  4663. .dpcm_capture = 1,
  4664. .ignore_suspend = 1,
  4665. },
  4666. {
  4667. .name = MSM_DAILINK_NAME(Compress1),
  4668. .stream_name = "Compress1",
  4669. .cpu_dai_name = "MultiMedia4",
  4670. .platform_name = "msm-compress-dsp",
  4671. .dynamic = 1,
  4672. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4673. .dpcm_playback = 1,
  4674. .dpcm_capture = 1,
  4675. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4676. SND_SOC_DPCM_TRIGGER_POST},
  4677. .codec_dai_name = "snd-soc-dummy-dai",
  4678. .codec_name = "snd-soc-dummy",
  4679. .ignore_suspend = 1,
  4680. .ignore_pmdown_time = 1,
  4681. /* this dainlink has playback support */
  4682. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4683. },
  4684. {
  4685. .name = "AUXPCM Hostless",
  4686. .stream_name = "AUXPCM Hostless",
  4687. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4688. .platform_name = "msm-pcm-hostless",
  4689. .dynamic = 1,
  4690. .dpcm_playback = 1,
  4691. .dpcm_capture = 1,
  4692. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4693. SND_SOC_DPCM_TRIGGER_POST},
  4694. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4695. .ignore_suspend = 1,
  4696. /* this dainlink has playback support */
  4697. .ignore_pmdown_time = 1,
  4698. .codec_dai_name = "snd-soc-dummy-dai",
  4699. .codec_name = "snd-soc-dummy",
  4700. },
  4701. {
  4702. .name = "SLIMBUS_1 Hostless",
  4703. .stream_name = "SLIMBUS_1 Hostless",
  4704. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4705. .platform_name = "msm-pcm-hostless",
  4706. .dynamic = 1,
  4707. .dpcm_playback = 1,
  4708. .dpcm_capture = 1,
  4709. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4710. SND_SOC_DPCM_TRIGGER_POST},
  4711. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4712. .ignore_suspend = 1,
  4713. /* this dailink has playback support */
  4714. .ignore_pmdown_time = 1,
  4715. .codec_dai_name = "snd-soc-dummy-dai",
  4716. .codec_name = "snd-soc-dummy",
  4717. },
  4718. {
  4719. .name = "SLIMBUS_3 Hostless",
  4720. .stream_name = "SLIMBUS_3 Hostless",
  4721. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4722. .platform_name = "msm-pcm-hostless",
  4723. .dynamic = 1,
  4724. .dpcm_playback = 1,
  4725. .dpcm_capture = 1,
  4726. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4727. SND_SOC_DPCM_TRIGGER_POST},
  4728. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4729. .ignore_suspend = 1,
  4730. /* this dailink has playback support */
  4731. .ignore_pmdown_time = 1,
  4732. .codec_dai_name = "snd-soc-dummy-dai",
  4733. .codec_name = "snd-soc-dummy",
  4734. },
  4735. {
  4736. .name = "SLIMBUS_4 Hostless",
  4737. .stream_name = "SLIMBUS_4 Hostless",
  4738. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4739. .platform_name = "msm-pcm-hostless",
  4740. .dynamic = 1,
  4741. .dpcm_playback = 1,
  4742. .dpcm_capture = 1,
  4743. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4744. SND_SOC_DPCM_TRIGGER_POST},
  4745. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4746. .ignore_suspend = 1,
  4747. /* this dailink has playback support */
  4748. .ignore_pmdown_time = 1,
  4749. .codec_dai_name = "snd-soc-dummy-dai",
  4750. .codec_name = "snd-soc-dummy",
  4751. },
  4752. {
  4753. .name = MSM_DAILINK_NAME(LowLatency),
  4754. .stream_name = "MultiMedia5",
  4755. .cpu_dai_name = "MultiMedia5",
  4756. .platform_name = "msm-pcm-dsp.1",
  4757. .dynamic = 1,
  4758. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4759. .dpcm_playback = 1,
  4760. .dpcm_capture = 1,
  4761. .codec_dai_name = "snd-soc-dummy-dai",
  4762. .codec_name = "snd-soc-dummy",
  4763. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4764. SND_SOC_DPCM_TRIGGER_POST},
  4765. .ignore_suspend = 1,
  4766. /* this dainlink has playback support */
  4767. .ignore_pmdown_time = 1,
  4768. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4769. .ops = &msm_fe_qos_ops,
  4770. },
  4771. {
  4772. .name = "Listen 1 Audio Service",
  4773. .stream_name = "Listen 1 Audio Service",
  4774. .cpu_dai_name = "LSM1",
  4775. .platform_name = "msm-lsm-client",
  4776. .dynamic = 1,
  4777. .dpcm_capture = 1,
  4778. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4779. SND_SOC_DPCM_TRIGGER_POST },
  4780. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4781. .ignore_suspend = 1,
  4782. .codec_dai_name = "snd-soc-dummy-dai",
  4783. .codec_name = "snd-soc-dummy",
  4784. .id = MSM_FRONTEND_DAI_LSM1,
  4785. },
  4786. /* Multiple Tunnel instances */
  4787. {
  4788. .name = MSM_DAILINK_NAME(Compress2),
  4789. .stream_name = "Compress2",
  4790. .cpu_dai_name = "MultiMedia7",
  4791. .platform_name = "msm-compress-dsp",
  4792. .dynamic = 1,
  4793. .dpcm_playback = 1,
  4794. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4795. SND_SOC_DPCM_TRIGGER_POST},
  4796. .codec_dai_name = "snd-soc-dummy-dai",
  4797. .codec_name = "snd-soc-dummy",
  4798. .ignore_suspend = 1,
  4799. .ignore_pmdown_time = 1,
  4800. /* this dainlink has playback support */
  4801. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4802. },
  4803. {
  4804. .name = MSM_DAILINK_NAME(MultiMedia10),
  4805. .stream_name = "MultiMedia10",
  4806. .cpu_dai_name = "MultiMedia10",
  4807. .platform_name = "msm-pcm-dsp.1",
  4808. .dynamic = 1,
  4809. .dpcm_playback = 1,
  4810. .dpcm_capture = 1,
  4811. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4812. SND_SOC_DPCM_TRIGGER_POST},
  4813. .codec_dai_name = "snd-soc-dummy-dai",
  4814. .codec_name = "snd-soc-dummy",
  4815. .ignore_suspend = 1,
  4816. .ignore_pmdown_time = 1,
  4817. /* this dainlink has playback support */
  4818. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4819. },
  4820. {
  4821. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4822. .stream_name = "MM_NOIRQ",
  4823. .cpu_dai_name = "MultiMedia8",
  4824. .platform_name = "msm-pcm-dsp-noirq",
  4825. .dynamic = 1,
  4826. .dpcm_playback = 1,
  4827. .dpcm_capture = 1,
  4828. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4829. SND_SOC_DPCM_TRIGGER_POST},
  4830. .codec_dai_name = "snd-soc-dummy-dai",
  4831. .codec_name = "snd-soc-dummy",
  4832. .ignore_suspend = 1,
  4833. .ignore_pmdown_time = 1,
  4834. /* this dainlink has playback support */
  4835. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4836. .ops = &msm_fe_qos_ops,
  4837. },
  4838. /* HDMI Hostless */
  4839. {
  4840. .name = "HDMI_RX_HOSTLESS",
  4841. .stream_name = "HDMI_RX_HOSTLESS",
  4842. .cpu_dai_name = "HDMI_HOSTLESS",
  4843. .platform_name = "msm-pcm-hostless",
  4844. .dynamic = 1,
  4845. .dpcm_playback = 1,
  4846. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4847. SND_SOC_DPCM_TRIGGER_POST},
  4848. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4849. .ignore_suspend = 1,
  4850. .ignore_pmdown_time = 1,
  4851. .codec_dai_name = "snd-soc-dummy-dai",
  4852. .codec_name = "snd-soc-dummy",
  4853. },
  4854. {
  4855. .name = "VoiceMMode2",
  4856. .stream_name = "VoiceMMode2",
  4857. .cpu_dai_name = "VoiceMMode2",
  4858. .platform_name = "msm-pcm-voice",
  4859. .dynamic = 1,
  4860. .dpcm_playback = 1,
  4861. .dpcm_capture = 1,
  4862. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4863. SND_SOC_DPCM_TRIGGER_POST},
  4864. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4865. .ignore_suspend = 1,
  4866. .ignore_pmdown_time = 1,
  4867. .codec_dai_name = "snd-soc-dummy-dai",
  4868. .codec_name = "snd-soc-dummy",
  4869. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4870. },
  4871. /* LSM FE */
  4872. {
  4873. .name = "Listen 2 Audio Service",
  4874. .stream_name = "Listen 2 Audio Service",
  4875. .cpu_dai_name = "LSM2",
  4876. .platform_name = "msm-lsm-client",
  4877. .dynamic = 1,
  4878. .dpcm_capture = 1,
  4879. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4880. SND_SOC_DPCM_TRIGGER_POST },
  4881. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4882. .ignore_suspend = 1,
  4883. .codec_dai_name = "snd-soc-dummy-dai",
  4884. .codec_name = "snd-soc-dummy",
  4885. .id = MSM_FRONTEND_DAI_LSM2,
  4886. },
  4887. {
  4888. .name = "Listen 3 Audio Service",
  4889. .stream_name = "Listen 3 Audio Service",
  4890. .cpu_dai_name = "LSM3",
  4891. .platform_name = "msm-lsm-client",
  4892. .dynamic = 1,
  4893. .dpcm_capture = 1,
  4894. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4895. SND_SOC_DPCM_TRIGGER_POST },
  4896. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4897. .ignore_suspend = 1,
  4898. .codec_dai_name = "snd-soc-dummy-dai",
  4899. .codec_name = "snd-soc-dummy",
  4900. .id = MSM_FRONTEND_DAI_LSM3,
  4901. },
  4902. {
  4903. .name = "Listen 4 Audio Service",
  4904. .stream_name = "Listen 4 Audio Service",
  4905. .cpu_dai_name = "LSM4",
  4906. .platform_name = "msm-lsm-client",
  4907. .dynamic = 1,
  4908. .dpcm_capture = 1,
  4909. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4910. SND_SOC_DPCM_TRIGGER_POST },
  4911. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4912. .ignore_suspend = 1,
  4913. .codec_dai_name = "snd-soc-dummy-dai",
  4914. .codec_name = "snd-soc-dummy",
  4915. .id = MSM_FRONTEND_DAI_LSM4,
  4916. },
  4917. {
  4918. .name = "Listen 5 Audio Service",
  4919. .stream_name = "Listen 5 Audio Service",
  4920. .cpu_dai_name = "LSM5",
  4921. .platform_name = "msm-lsm-client",
  4922. .dynamic = 1,
  4923. .dpcm_capture = 1,
  4924. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4925. SND_SOC_DPCM_TRIGGER_POST },
  4926. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4927. .ignore_suspend = 1,
  4928. .codec_dai_name = "snd-soc-dummy-dai",
  4929. .codec_name = "snd-soc-dummy",
  4930. .id = MSM_FRONTEND_DAI_LSM5,
  4931. },
  4932. {
  4933. .name = "Listen 6 Audio Service",
  4934. .stream_name = "Listen 6 Audio Service",
  4935. .cpu_dai_name = "LSM6",
  4936. .platform_name = "msm-lsm-client",
  4937. .dynamic = 1,
  4938. .dpcm_capture = 1,
  4939. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4940. SND_SOC_DPCM_TRIGGER_POST },
  4941. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4942. .ignore_suspend = 1,
  4943. .codec_dai_name = "snd-soc-dummy-dai",
  4944. .codec_name = "snd-soc-dummy",
  4945. .id = MSM_FRONTEND_DAI_LSM6,
  4946. },
  4947. {
  4948. .name = "Listen 7 Audio Service",
  4949. .stream_name = "Listen 7 Audio Service",
  4950. .cpu_dai_name = "LSM7",
  4951. .platform_name = "msm-lsm-client",
  4952. .dynamic = 1,
  4953. .dpcm_capture = 1,
  4954. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4955. SND_SOC_DPCM_TRIGGER_POST },
  4956. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4957. .ignore_suspend = 1,
  4958. .codec_dai_name = "snd-soc-dummy-dai",
  4959. .codec_name = "snd-soc-dummy",
  4960. .id = MSM_FRONTEND_DAI_LSM7,
  4961. },
  4962. {
  4963. .name = "Listen 8 Audio Service",
  4964. .stream_name = "Listen 8 Audio Service",
  4965. .cpu_dai_name = "LSM8",
  4966. .platform_name = "msm-lsm-client",
  4967. .dynamic = 1,
  4968. .dpcm_capture = 1,
  4969. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4970. SND_SOC_DPCM_TRIGGER_POST },
  4971. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4972. .ignore_suspend = 1,
  4973. .codec_dai_name = "snd-soc-dummy-dai",
  4974. .codec_name = "snd-soc-dummy",
  4975. .id = MSM_FRONTEND_DAI_LSM8,
  4976. },
  4977. {
  4978. .name = MSM_DAILINK_NAME(Media9),
  4979. .stream_name = "MultiMedia9",
  4980. .cpu_dai_name = "MultiMedia9",
  4981. .platform_name = "msm-pcm-dsp.0",
  4982. .dynamic = 1,
  4983. .dpcm_playback = 1,
  4984. .dpcm_capture = 1,
  4985. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4986. SND_SOC_DPCM_TRIGGER_POST},
  4987. .codec_dai_name = "snd-soc-dummy-dai",
  4988. .codec_name = "snd-soc-dummy",
  4989. .ignore_suspend = 1,
  4990. /* this dainlink has playback support */
  4991. .ignore_pmdown_time = 1,
  4992. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4993. },
  4994. {
  4995. .name = MSM_DAILINK_NAME(Compress4),
  4996. .stream_name = "Compress4",
  4997. .cpu_dai_name = "MultiMedia11",
  4998. .platform_name = "msm-compress-dsp",
  4999. .dynamic = 1,
  5000. .dpcm_playback = 1,
  5001. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5002. SND_SOC_DPCM_TRIGGER_POST},
  5003. .codec_dai_name = "snd-soc-dummy-dai",
  5004. .codec_name = "snd-soc-dummy",
  5005. .ignore_suspend = 1,
  5006. .ignore_pmdown_time = 1,
  5007. /* this dainlink has playback support */
  5008. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5009. },
  5010. {
  5011. .name = MSM_DAILINK_NAME(Compress5),
  5012. .stream_name = "Compress5",
  5013. .cpu_dai_name = "MultiMedia12",
  5014. .platform_name = "msm-compress-dsp",
  5015. .dynamic = 1,
  5016. .dpcm_playback = 1,
  5017. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5018. SND_SOC_DPCM_TRIGGER_POST},
  5019. .codec_dai_name = "snd-soc-dummy-dai",
  5020. .codec_name = "snd-soc-dummy",
  5021. .ignore_suspend = 1,
  5022. .ignore_pmdown_time = 1,
  5023. /* this dainlink has playback support */
  5024. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5025. },
  5026. {
  5027. .name = MSM_DAILINK_NAME(Compress6),
  5028. .stream_name = "Compress6",
  5029. .cpu_dai_name = "MultiMedia13",
  5030. .platform_name = "msm-compress-dsp",
  5031. .dynamic = 1,
  5032. .dpcm_playback = 1,
  5033. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5034. SND_SOC_DPCM_TRIGGER_POST},
  5035. .codec_dai_name = "snd-soc-dummy-dai",
  5036. .codec_name = "snd-soc-dummy",
  5037. .ignore_suspend = 1,
  5038. .ignore_pmdown_time = 1,
  5039. /* this dainlink has playback support */
  5040. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5041. },
  5042. {
  5043. .name = MSM_DAILINK_NAME(Compress7),
  5044. .stream_name = "Compress7",
  5045. .cpu_dai_name = "MultiMedia14",
  5046. .platform_name = "msm-compress-dsp",
  5047. .dynamic = 1,
  5048. .dpcm_playback = 1,
  5049. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5050. SND_SOC_DPCM_TRIGGER_POST},
  5051. .codec_dai_name = "snd-soc-dummy-dai",
  5052. .codec_name = "snd-soc-dummy",
  5053. .ignore_suspend = 1,
  5054. .ignore_pmdown_time = 1,
  5055. /* this dainlink has playback support */
  5056. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5057. },
  5058. {
  5059. .name = MSM_DAILINK_NAME(Compress8),
  5060. .stream_name = "Compress8",
  5061. .cpu_dai_name = "MultiMedia15",
  5062. .platform_name = "msm-compress-dsp",
  5063. .dynamic = 1,
  5064. .dpcm_playback = 1,
  5065. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5066. SND_SOC_DPCM_TRIGGER_POST},
  5067. .codec_dai_name = "snd-soc-dummy-dai",
  5068. .codec_name = "snd-soc-dummy",
  5069. .ignore_suspend = 1,
  5070. .ignore_pmdown_time = 1,
  5071. /* this dainlink has playback support */
  5072. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5073. },
  5074. {
  5075. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5076. .stream_name = "MM_NOIRQ_2",
  5077. .cpu_dai_name = "MultiMedia16",
  5078. .platform_name = "msm-pcm-dsp-noirq",
  5079. .dynamic = 1,
  5080. .dpcm_playback = 1,
  5081. .dpcm_capture = 1,
  5082. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5083. SND_SOC_DPCM_TRIGGER_POST},
  5084. .codec_dai_name = "snd-soc-dummy-dai",
  5085. .codec_name = "snd-soc-dummy",
  5086. .ignore_suspend = 1,
  5087. .ignore_pmdown_time = 1,
  5088. /* this dainlink has playback support */
  5089. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5090. },
  5091. {
  5092. .name = "SLIMBUS_8 Hostless",
  5093. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5094. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5095. .platform_name = "msm-pcm-hostless",
  5096. .dynamic = 1,
  5097. .dpcm_capture = 1,
  5098. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5099. SND_SOC_DPCM_TRIGGER_POST},
  5100. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5101. .ignore_suspend = 1,
  5102. .codec_dai_name = "snd-soc-dummy-dai",
  5103. .codec_name = "snd-soc-dummy",
  5104. },
  5105. /* Hostless PCM purpose */
  5106. {
  5107. .name = "CDC_DMA Hostless",
  5108. .stream_name = "CDC_DMA Hostless",
  5109. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5110. .platform_name = "msm-pcm-hostless",
  5111. .dynamic = 1,
  5112. .dpcm_playback = 1,
  5113. .dpcm_capture = 1,
  5114. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5115. SND_SOC_DPCM_TRIGGER_POST},
  5116. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5117. .ignore_suspend = 1,
  5118. /* this dailink has playback support */
  5119. .ignore_pmdown_time = 1,
  5120. .codec_dai_name = "snd-soc-dummy-dai",
  5121. .codec_name = "snd-soc-dummy",
  5122. },
  5123. };
  5124. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5125. {
  5126. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5127. .stream_name = "WSA CDC DMA0 Capture",
  5128. .cpu_dai_name = "msm-dai-cdc-dma.45057",
  5129. .platform_name = "msm-pcm-hostless",
  5130. .codec_name = "bolero_codec",
  5131. .codec_dai_name = "wsa_macro_vifeedback",
  5132. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5133. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5134. .ignore_suspend = 1,
  5135. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5136. .ops = &msm_cdc_dma_be_ops,
  5137. },
  5138. };
  5139. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5140. {
  5141. .name = MSM_DAILINK_NAME(ASM Loopback),
  5142. .stream_name = "MultiMedia6",
  5143. .cpu_dai_name = "MultiMedia6",
  5144. .platform_name = "msm-pcm-loopback",
  5145. .dynamic = 1,
  5146. .dpcm_playback = 1,
  5147. .dpcm_capture = 1,
  5148. .codec_dai_name = "snd-soc-dummy-dai",
  5149. .codec_name = "snd-soc-dummy",
  5150. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5151. SND_SOC_DPCM_TRIGGER_POST},
  5152. .ignore_suspend = 1,
  5153. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5154. .ignore_pmdown_time = 1,
  5155. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5156. },
  5157. {
  5158. .name = "USB Audio Hostless",
  5159. .stream_name = "USB Audio Hostless",
  5160. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5161. .platform_name = "msm-pcm-hostless",
  5162. .dynamic = 1,
  5163. .dpcm_playback = 1,
  5164. .dpcm_capture = 1,
  5165. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5166. SND_SOC_DPCM_TRIGGER_POST},
  5167. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5168. .ignore_suspend = 1,
  5169. .ignore_pmdown_time = 1,
  5170. .codec_dai_name = "snd-soc-dummy-dai",
  5171. .codec_name = "snd-soc-dummy",
  5172. },
  5173. {
  5174. .name = "SLIMBUS_7 Hostless",
  5175. .stream_name = "SLIMBUS_7 Hostless",
  5176. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5177. .platform_name = "msm-pcm-hostless",
  5178. .dynamic = 1,
  5179. .dpcm_capture = 1,
  5180. .dpcm_playback = 1,
  5181. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5182. SND_SOC_DPCM_TRIGGER_POST},
  5183. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5184. .ignore_suspend = 1,
  5185. .ignore_pmdown_time = 1,
  5186. .codec_dai_name = "snd-soc-dummy-dai",
  5187. .codec_name = "snd-soc-dummy",
  5188. },
  5189. };
  5190. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5191. /* Backend AFE DAI Links */
  5192. {
  5193. .name = LPASS_BE_AFE_PCM_RX,
  5194. .stream_name = "AFE Playback",
  5195. .cpu_dai_name = "msm-dai-q6-dev.224",
  5196. .platform_name = "msm-pcm-routing",
  5197. .codec_name = "msm-stub-codec.1",
  5198. .codec_dai_name = "msm-stub-rx",
  5199. .no_pcm = 1,
  5200. .dpcm_playback = 1,
  5201. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5202. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5203. /* this dainlink has playback support */
  5204. .ignore_pmdown_time = 1,
  5205. .ignore_suspend = 1,
  5206. },
  5207. {
  5208. .name = LPASS_BE_AFE_PCM_TX,
  5209. .stream_name = "AFE Capture",
  5210. .cpu_dai_name = "msm-dai-q6-dev.225",
  5211. .platform_name = "msm-pcm-routing",
  5212. .codec_name = "msm-stub-codec.1",
  5213. .codec_dai_name = "msm-stub-tx",
  5214. .no_pcm = 1,
  5215. .dpcm_capture = 1,
  5216. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5217. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5218. .ignore_suspend = 1,
  5219. },
  5220. /* Incall Record Uplink BACK END DAI Link */
  5221. {
  5222. .name = LPASS_BE_INCALL_RECORD_TX,
  5223. .stream_name = "Voice Uplink Capture",
  5224. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5225. .platform_name = "msm-pcm-routing",
  5226. .codec_name = "msm-stub-codec.1",
  5227. .codec_dai_name = "msm-stub-tx",
  5228. .no_pcm = 1,
  5229. .dpcm_capture = 1,
  5230. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5231. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5232. .ignore_suspend = 1,
  5233. },
  5234. /* Incall Record Downlink BACK END DAI Link */
  5235. {
  5236. .name = LPASS_BE_INCALL_RECORD_RX,
  5237. .stream_name = "Voice Downlink Capture",
  5238. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5239. .platform_name = "msm-pcm-routing",
  5240. .codec_name = "msm-stub-codec.1",
  5241. .codec_dai_name = "msm-stub-tx",
  5242. .no_pcm = 1,
  5243. .dpcm_capture = 1,
  5244. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5245. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5246. .ignore_suspend = 1,
  5247. },
  5248. /* Incall Music BACK END DAI Link */
  5249. {
  5250. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5251. .stream_name = "Voice Farend Playback",
  5252. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5253. .platform_name = "msm-pcm-routing",
  5254. .codec_name = "msm-stub-codec.1",
  5255. .codec_dai_name = "msm-stub-rx",
  5256. .no_pcm = 1,
  5257. .dpcm_playback = 1,
  5258. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5259. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5260. .ignore_suspend = 1,
  5261. .ignore_pmdown_time = 1,
  5262. },
  5263. /* Incall Music 2 BACK END DAI Link */
  5264. {
  5265. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5266. .stream_name = "Voice2 Farend Playback",
  5267. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5268. .platform_name = "msm-pcm-routing",
  5269. .codec_name = "msm-stub-codec.1",
  5270. .codec_dai_name = "msm-stub-rx",
  5271. .no_pcm = 1,
  5272. .dpcm_playback = 1,
  5273. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5274. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5275. .ignore_suspend = 1,
  5276. .ignore_pmdown_time = 1,
  5277. },
  5278. {
  5279. .name = LPASS_BE_USB_AUDIO_RX,
  5280. .stream_name = "USB Audio Playback",
  5281. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5282. .platform_name = "msm-pcm-routing",
  5283. .codec_name = "msm-stub-codec.1",
  5284. .codec_dai_name = "msm-stub-rx",
  5285. .no_pcm = 1,
  5286. .dpcm_playback = 1,
  5287. .id = MSM_BACKEND_DAI_USB_RX,
  5288. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5289. .ignore_pmdown_time = 1,
  5290. .ignore_suspend = 1,
  5291. },
  5292. {
  5293. .name = LPASS_BE_USB_AUDIO_TX,
  5294. .stream_name = "USB Audio Capture",
  5295. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5296. .platform_name = "msm-pcm-routing",
  5297. .codec_name = "msm-stub-codec.1",
  5298. .codec_dai_name = "msm-stub-tx",
  5299. .no_pcm = 1,
  5300. .dpcm_capture = 1,
  5301. .id = MSM_BACKEND_DAI_USB_TX,
  5302. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5303. .ignore_suspend = 1,
  5304. },
  5305. {
  5306. .name = LPASS_BE_PRI_TDM_RX_0,
  5307. .stream_name = "Primary TDM0 Playback",
  5308. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5309. .platform_name = "msm-pcm-routing",
  5310. .codec_name = "msm-stub-codec.1",
  5311. .codec_dai_name = "msm-stub-rx",
  5312. .no_pcm = 1,
  5313. .dpcm_playback = 1,
  5314. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5315. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5316. .ops = &qcs405_tdm_be_ops,
  5317. .ignore_suspend = 1,
  5318. .ignore_pmdown_time = 1,
  5319. },
  5320. {
  5321. .name = LPASS_BE_PRI_TDM_TX_0,
  5322. .stream_name = "Primary TDM0 Capture",
  5323. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5324. .platform_name = "msm-pcm-routing",
  5325. .codec_name = "msm-stub-codec.1",
  5326. .codec_dai_name = "msm-stub-tx",
  5327. .no_pcm = 1,
  5328. .dpcm_capture = 1,
  5329. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5330. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5331. .ops = &qcs405_tdm_be_ops,
  5332. .ignore_suspend = 1,
  5333. },
  5334. {
  5335. .name = LPASS_BE_SEC_TDM_RX_0,
  5336. .stream_name = "Secondary TDM0 Playback",
  5337. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5338. .platform_name = "msm-pcm-routing",
  5339. .codec_name = "msm-stub-codec.1",
  5340. .codec_dai_name = "msm-stub-rx",
  5341. .no_pcm = 1,
  5342. .dpcm_playback = 1,
  5343. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5344. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5345. .ops = &qcs405_tdm_be_ops,
  5346. .ignore_suspend = 1,
  5347. .ignore_pmdown_time = 1,
  5348. },
  5349. {
  5350. .name = LPASS_BE_SEC_TDM_TX_0,
  5351. .stream_name = "Secondary TDM0 Capture",
  5352. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5353. .platform_name = "msm-pcm-routing",
  5354. .codec_name = "msm-stub-codec.1",
  5355. .codec_dai_name = "msm-stub-tx",
  5356. .no_pcm = 1,
  5357. .dpcm_capture = 1,
  5358. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5359. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5360. .ops = &qcs405_tdm_be_ops,
  5361. .ignore_suspend = 1,
  5362. },
  5363. {
  5364. .name = LPASS_BE_TERT_TDM_RX_0,
  5365. .stream_name = "Tertiary TDM0 Playback",
  5366. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5367. .platform_name = "msm-pcm-routing",
  5368. .codec_name = "msm-stub-codec.1",
  5369. .codec_dai_name = "msm-stub-rx",
  5370. .no_pcm = 1,
  5371. .dpcm_playback = 1,
  5372. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5373. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5374. .ops = &qcs405_tdm_be_ops,
  5375. .ignore_suspend = 1,
  5376. .ignore_pmdown_time = 1,
  5377. },
  5378. {
  5379. .name = LPASS_BE_TERT_TDM_TX_0,
  5380. .stream_name = "Tertiary TDM0 Capture",
  5381. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5382. .platform_name = "msm-pcm-routing",
  5383. .codec_name = "msm-stub-codec.1",
  5384. .codec_dai_name = "msm-stub-tx",
  5385. .no_pcm = 1,
  5386. .dpcm_capture = 1,
  5387. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5388. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5389. .ops = &qcs405_tdm_be_ops,
  5390. .ignore_suspend = 1,
  5391. },
  5392. {
  5393. .name = LPASS_BE_QUAT_TDM_RX_0,
  5394. .stream_name = "Quaternary TDM0 Playback",
  5395. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5396. .platform_name = "msm-pcm-routing",
  5397. .codec_name = "msm-stub-codec.1",
  5398. .codec_dai_name = "msm-stub-rx",
  5399. .no_pcm = 1,
  5400. .dpcm_playback = 1,
  5401. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5402. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5403. .ops = &qcs405_tdm_be_ops,
  5404. .ignore_suspend = 1,
  5405. .ignore_pmdown_time = 1,
  5406. },
  5407. {
  5408. .name = LPASS_BE_QUAT_TDM_TX_0,
  5409. .stream_name = "Quaternary TDM0 Capture",
  5410. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5411. .platform_name = "msm-pcm-routing",
  5412. .codec_name = "msm-stub-codec.1",
  5413. .codec_dai_name = "msm-stub-tx",
  5414. .no_pcm = 1,
  5415. .dpcm_capture = 1,
  5416. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5417. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5418. .ops = &qcs405_tdm_be_ops,
  5419. .ignore_suspend = 1,
  5420. },
  5421. {
  5422. .name = LPASS_BE_QUIN_TDM_RX_0,
  5423. .stream_name = "Quinary TDM0 Playback",
  5424. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5425. .platform_name = "msm-pcm-routing",
  5426. .codec_name = "msm-stub-codec.1",
  5427. .codec_dai_name = "msm-stub-rx",
  5428. .no_pcm = 1,
  5429. .dpcm_playback = 1,
  5430. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5431. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5432. .ops = &qcs405_tdm_be_ops,
  5433. .ignore_suspend = 1,
  5434. .ignore_pmdown_time = 1,
  5435. },
  5436. {
  5437. .name = LPASS_BE_QUIN_TDM_TX_0,
  5438. .stream_name = "Quinary TDM0 Capture",
  5439. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5440. .platform_name = "msm-pcm-routing",
  5441. .codec_name = "msm-stub-codec.1",
  5442. .codec_dai_name = "msm-stub-tx",
  5443. .no_pcm = 1,
  5444. .dpcm_capture = 1,
  5445. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5447. .ops = &qcs405_tdm_be_ops,
  5448. .ignore_suspend = 1,
  5449. },
  5450. };
  5451. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5452. {
  5453. .name = LPASS_BE_SLIMBUS_0_RX,
  5454. .stream_name = "Slimbus Playback",
  5455. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5456. .platform_name = "msm-pcm-routing",
  5457. .codec_name = "tasha_codec",
  5458. .codec_dai_name = "tasha_mix_rx1",
  5459. .no_pcm = 1,
  5460. .dpcm_playback = 1,
  5461. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5462. .init = &msm_audrx_init,
  5463. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5464. /* this dainlink has playback support */
  5465. .ignore_pmdown_time = 1,
  5466. .ignore_suspend = 1,
  5467. .ops = &msm_be_ops,
  5468. },
  5469. {
  5470. .name = LPASS_BE_SLIMBUS_0_TX,
  5471. .stream_name = "Slimbus Capture",
  5472. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5473. .platform_name = "msm-pcm-routing",
  5474. .codec_name = "tasha_codec",
  5475. .codec_dai_name = "tasha_tx1",
  5476. .no_pcm = 1,
  5477. .dpcm_capture = 1,
  5478. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5479. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5480. .ignore_suspend = 1,
  5481. .ops = &msm_be_ops,
  5482. },
  5483. {
  5484. .name = LPASS_BE_SLIMBUS_1_RX,
  5485. .stream_name = "Slimbus1 Playback",
  5486. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5487. .platform_name = "msm-pcm-routing",
  5488. .codec_name = "tasha_codec",
  5489. .codec_dai_name = "tasha_mix_rx1",
  5490. .no_pcm = 1,
  5491. .dpcm_playback = 1,
  5492. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5493. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5494. .ops = &msm_be_ops,
  5495. /* dai link has playback support */
  5496. .ignore_pmdown_time = 1,
  5497. .ignore_suspend = 1,
  5498. },
  5499. {
  5500. .name = LPASS_BE_SLIMBUS_1_TX,
  5501. .stream_name = "Slimbus1 Capture",
  5502. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5503. .platform_name = "msm-pcm-routing",
  5504. .codec_name = "tasha_codec",
  5505. .codec_dai_name = "tasha_tx3",
  5506. .no_pcm = 1,
  5507. .dpcm_capture = 1,
  5508. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5509. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5510. .ops = &msm_be_ops,
  5511. .ignore_suspend = 1,
  5512. },
  5513. {
  5514. .name = LPASS_BE_SLIMBUS_2_RX,
  5515. .stream_name = "Slimbus2 Playback",
  5516. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5517. .platform_name = "msm-pcm-routing",
  5518. .codec_name = "tasha_codec",
  5519. .codec_dai_name = "tasha_rx2",
  5520. .no_pcm = 1,
  5521. .dpcm_playback = 1,
  5522. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5523. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5524. .ops = &msm_be_ops,
  5525. .ignore_pmdown_time = 1,
  5526. .ignore_suspend = 1,
  5527. },
  5528. {
  5529. .name = LPASS_BE_SLIMBUS_3_RX,
  5530. .stream_name = "Slimbus3 Playback",
  5531. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5532. .platform_name = "msm-pcm-routing",
  5533. .codec_name = "tasha_codec",
  5534. .codec_dai_name = "tasha_mix_rx1",
  5535. .no_pcm = 1,
  5536. .dpcm_playback = 1,
  5537. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5538. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5539. .ops = &msm_be_ops,
  5540. /* dai link has playback support */
  5541. .ignore_pmdown_time = 1,
  5542. .ignore_suspend = 1,
  5543. },
  5544. {
  5545. .name = LPASS_BE_SLIMBUS_3_TX,
  5546. .stream_name = "Slimbus3 Capture",
  5547. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5548. .platform_name = "msm-pcm-routing",
  5549. .codec_name = "tasha_codec",
  5550. .codec_dai_name = "tasha_tx1",
  5551. .no_pcm = 1,
  5552. .dpcm_capture = 1,
  5553. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5554. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5555. .ops = &msm_be_ops,
  5556. .ignore_suspend = 1,
  5557. },
  5558. {
  5559. .name = LPASS_BE_SLIMBUS_4_RX,
  5560. .stream_name = "Slimbus4 Playback",
  5561. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5562. .platform_name = "msm-pcm-routing",
  5563. .codec_name = "tasha_codec",
  5564. .codec_dai_name = "tasha_mix_rx1",
  5565. .no_pcm = 1,
  5566. .dpcm_playback = 1,
  5567. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5568. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5569. .ops = &msm_be_ops,
  5570. /* dai link has playback support */
  5571. .ignore_pmdown_time = 1,
  5572. .ignore_suspend = 1,
  5573. },
  5574. {
  5575. .name = LPASS_BE_SLIMBUS_5_RX,
  5576. .stream_name = "Slimbus5 Playback",
  5577. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5578. .platform_name = "msm-pcm-routing",
  5579. .codec_name = "tasha_codec",
  5580. .codec_dai_name = "tasha_rx3",
  5581. .no_pcm = 1,
  5582. .dpcm_playback = 1,
  5583. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5584. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5585. .ops = &msm_be_ops,
  5586. /* dai link has playback support */
  5587. .ignore_pmdown_time = 1,
  5588. .ignore_suspend = 1,
  5589. },
  5590. {
  5591. .name = LPASS_BE_SLIMBUS_6_RX,
  5592. .stream_name = "Slimbus6 Playback",
  5593. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5594. .platform_name = "msm-pcm-routing",
  5595. .codec_name = "tasha_codec",
  5596. .codec_dai_name = "tasha_rx4",
  5597. .no_pcm = 1,
  5598. .dpcm_playback = 1,
  5599. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5600. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5601. .ops = &msm_be_ops,
  5602. /* dai link has playback support */
  5603. .ignore_pmdown_time = 1,
  5604. .ignore_suspend = 1,
  5605. },
  5606. /* Slimbus VI Recording */
  5607. {
  5608. .name = LPASS_BE_SLIMBUS_TX_VI,
  5609. .stream_name = "Slimbus4 Capture",
  5610. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5611. .platform_name = "msm-pcm-routing",
  5612. .codec_name = "tasha_codec",
  5613. .codec_dai_name = "tasha_vifeedback",
  5614. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5615. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5616. .ops = &msm_be_ops,
  5617. .ignore_suspend = 1,
  5618. .no_pcm = 1,
  5619. .dpcm_capture = 1,
  5620. .ignore_pmdown_time = 1,
  5621. },
  5622. };
  5623. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5624. {
  5625. .name = LPASS_BE_SLIMBUS_7_RX,
  5626. .stream_name = "Slimbus7 Playback",
  5627. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5628. .platform_name = "msm-pcm-routing",
  5629. .codec_name = "btfmslim_slave",
  5630. /* BT codec driver determines capabilities based on
  5631. * dai name, bt codecdai name should always contains
  5632. * supported usecase information
  5633. */
  5634. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5635. .no_pcm = 1,
  5636. .dpcm_playback = 1,
  5637. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5638. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5639. .ops = &msm_wcn_ops,
  5640. /* dai link has playback support */
  5641. .ignore_pmdown_time = 1,
  5642. .ignore_suspend = 1,
  5643. },
  5644. {
  5645. .name = LPASS_BE_SLIMBUS_7_TX,
  5646. .stream_name = "Slimbus7 Capture",
  5647. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5648. .platform_name = "msm-pcm-routing",
  5649. .codec_name = "btfmslim_slave",
  5650. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5651. .no_pcm = 1,
  5652. .dpcm_capture = 1,
  5653. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5654. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5655. .ops = &msm_wcn_ops,
  5656. .ignore_suspend = 1,
  5657. },
  5658. {
  5659. .name = LPASS_BE_SLIMBUS_8_TX,
  5660. .stream_name = "Slimbus8 Capture",
  5661. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5662. .platform_name = "msm-pcm-routing",
  5663. .codec_name = "btfmslim_slave",
  5664. .codec_dai_name = "btfm_fm_slim_tx",
  5665. .no_pcm = 1,
  5666. .dpcm_capture = 1,
  5667. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5668. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5669. .init = &msm_wcn_init,
  5670. .ops = &msm_wcn_ops,
  5671. .ignore_suspend = 1,
  5672. },
  5673. };
  5674. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5675. {
  5676. .name = LPASS_BE_PRI_MI2S_RX,
  5677. .stream_name = "Primary MI2S Playback",
  5678. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5679. .platform_name = "msm-pcm-routing",
  5680. .codec_name = "msm-stub-codec.1",
  5681. .codec_dai_name = "msm-stub-rx",
  5682. .no_pcm = 1,
  5683. .dpcm_playback = 1,
  5684. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5685. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5686. .ops = &msm_mi2s_be_ops,
  5687. .ignore_suspend = 1,
  5688. .ignore_pmdown_time = 1,
  5689. },
  5690. {
  5691. .name = LPASS_BE_PRI_MI2S_TX,
  5692. .stream_name = "Primary MI2S Capture",
  5693. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5694. .platform_name = "msm-pcm-routing",
  5695. .codec_name = "msm-stub-codec.1",
  5696. .codec_dai_name = "msm-stub-tx",
  5697. .no_pcm = 1,
  5698. .dpcm_capture = 1,
  5699. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5700. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5701. .ops = &msm_mi2s_be_ops,
  5702. .ignore_suspend = 1,
  5703. },
  5704. {
  5705. .name = LPASS_BE_SEC_MI2S_RX,
  5706. .stream_name = "Secondary MI2S Playback",
  5707. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5708. .platform_name = "msm-pcm-routing",
  5709. .codec_name = "msm-stub-codec.1",
  5710. .codec_dai_name = "msm-stub-rx",
  5711. .no_pcm = 1,
  5712. .dpcm_playback = 1,
  5713. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5714. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5715. .ops = &msm_mi2s_be_ops,
  5716. .ignore_suspend = 1,
  5717. .ignore_pmdown_time = 1,
  5718. },
  5719. {
  5720. .name = LPASS_BE_SEC_MI2S_TX,
  5721. .stream_name = "Secondary MI2S Capture",
  5722. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5723. .platform_name = "msm-pcm-routing",
  5724. .codec_name = "msm-stub-codec.1",
  5725. .codec_dai_name = "msm-stub-tx",
  5726. .no_pcm = 1,
  5727. .dpcm_capture = 1,
  5728. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5729. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5730. .ops = &msm_mi2s_be_ops,
  5731. .ignore_suspend = 1,
  5732. },
  5733. {
  5734. .name = LPASS_BE_TERT_MI2S_RX,
  5735. .stream_name = "Tertiary MI2S Playback",
  5736. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5737. .platform_name = "msm-pcm-routing",
  5738. .codec_name = "msm-stub-codec.1",
  5739. .codec_dai_name = "msm-stub-rx",
  5740. .no_pcm = 1,
  5741. .dpcm_playback = 1,
  5742. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5743. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5744. .ops = &msm_mi2s_be_ops,
  5745. .ignore_suspend = 1,
  5746. .ignore_pmdown_time = 1,
  5747. },
  5748. {
  5749. .name = LPASS_BE_TERT_MI2S_TX,
  5750. .stream_name = "Tertiary MI2S Capture",
  5751. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5752. .platform_name = "msm-pcm-routing",
  5753. .codec_name = "msm-stub-codec.1",
  5754. .codec_dai_name = "msm-stub-tx",
  5755. .no_pcm = 1,
  5756. .dpcm_capture = 1,
  5757. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5758. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5759. .ops = &msm_mi2s_be_ops,
  5760. .ignore_suspend = 1,
  5761. },
  5762. {
  5763. .name = LPASS_BE_QUAT_MI2S_RX,
  5764. .stream_name = "Quaternary MI2S Playback",
  5765. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5766. .platform_name = "msm-pcm-routing",
  5767. .codec_name = "msm-stub-codec.1",
  5768. .codec_dai_name = "msm-stub-rx",
  5769. .no_pcm = 1,
  5770. .dpcm_playback = 1,
  5771. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5772. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5773. .ops = &msm_mi2s_be_ops,
  5774. .ignore_suspend = 1,
  5775. .ignore_pmdown_time = 1,
  5776. },
  5777. {
  5778. .name = LPASS_BE_QUAT_MI2S_TX,
  5779. .stream_name = "Quaternary MI2S Capture",
  5780. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5781. .platform_name = "msm-pcm-routing",
  5782. .codec_name = "msm-stub-codec.1",
  5783. .codec_dai_name = "msm-stub-tx",
  5784. .no_pcm = 1,
  5785. .dpcm_capture = 1,
  5786. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5787. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5788. .ops = &msm_mi2s_be_ops,
  5789. .ignore_suspend = 1,
  5790. },
  5791. {
  5792. .name = LPASS_BE_QUIN_MI2S_RX,
  5793. .stream_name = "Quinary MI2S Playback",
  5794. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5795. .platform_name = "msm-pcm-routing",
  5796. .codec_name = "msm-stub-codec.1",
  5797. .codec_dai_name = "msm-stub-rx",
  5798. .no_pcm = 1,
  5799. .dpcm_playback = 1,
  5800. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5801. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5802. .ops = &msm_mi2s_be_ops,
  5803. .ignore_suspend = 1,
  5804. .ignore_pmdown_time = 1,
  5805. },
  5806. {
  5807. .name = LPASS_BE_QUIN_MI2S_TX,
  5808. .stream_name = "Quinary MI2S Capture",
  5809. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5810. .platform_name = "msm-pcm-routing",
  5811. .codec_name = "msm-stub-codec.1",
  5812. .codec_dai_name = "msm-stub-tx",
  5813. .no_pcm = 1,
  5814. .dpcm_capture = 1,
  5815. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5816. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5817. .ops = &msm_mi2s_be_ops,
  5818. .ignore_suspend = 1,
  5819. },
  5820. };
  5821. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5822. /* Primary AUX PCM Backend DAI Links */
  5823. {
  5824. .name = LPASS_BE_AUXPCM_RX,
  5825. .stream_name = "AUX PCM Playback",
  5826. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5827. .platform_name = "msm-pcm-routing",
  5828. .codec_name = "msm-stub-codec.1",
  5829. .codec_dai_name = "msm-stub-rx",
  5830. .no_pcm = 1,
  5831. .dpcm_playback = 1,
  5832. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5833. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5834. .ignore_pmdown_time = 1,
  5835. .ignore_suspend = 1,
  5836. },
  5837. {
  5838. .name = LPASS_BE_AUXPCM_TX,
  5839. .stream_name = "AUX PCM Capture",
  5840. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5841. .platform_name = "msm-pcm-routing",
  5842. .codec_name = "msm-stub-codec.1",
  5843. .codec_dai_name = "msm-stub-tx",
  5844. .no_pcm = 1,
  5845. .dpcm_capture = 1,
  5846. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5847. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5848. .ignore_suspend = 1,
  5849. },
  5850. /* Secondary AUX PCM Backend DAI Links */
  5851. {
  5852. .name = LPASS_BE_SEC_AUXPCM_RX,
  5853. .stream_name = "Sec AUX PCM Playback",
  5854. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-rx",
  5858. .no_pcm = 1,
  5859. .dpcm_playback = 1,
  5860. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ignore_pmdown_time = 1,
  5863. .ignore_suspend = 1,
  5864. },
  5865. {
  5866. .name = LPASS_BE_SEC_AUXPCM_TX,
  5867. .stream_name = "Sec AUX PCM Capture",
  5868. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5869. .platform_name = "msm-pcm-routing",
  5870. .codec_name = "msm-stub-codec.1",
  5871. .codec_dai_name = "msm-stub-tx",
  5872. .no_pcm = 1,
  5873. .dpcm_capture = 1,
  5874. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5875. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5876. .ignore_suspend = 1,
  5877. },
  5878. /* Tertiary AUX PCM Backend DAI Links */
  5879. {
  5880. .name = LPASS_BE_TERT_AUXPCM_RX,
  5881. .stream_name = "Tert AUX PCM Playback",
  5882. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5883. .platform_name = "msm-pcm-routing",
  5884. .codec_name = "msm-stub-codec.1",
  5885. .codec_dai_name = "msm-stub-rx",
  5886. .no_pcm = 1,
  5887. .dpcm_playback = 1,
  5888. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5889. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5890. .ignore_suspend = 1,
  5891. },
  5892. {
  5893. .name = LPASS_BE_TERT_AUXPCM_TX,
  5894. .stream_name = "Tert AUX PCM Capture",
  5895. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5896. .platform_name = "msm-pcm-routing",
  5897. .codec_name = "msm-stub-codec.1",
  5898. .codec_dai_name = "msm-stub-tx",
  5899. .no_pcm = 1,
  5900. .dpcm_capture = 1,
  5901. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5902. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5903. .ignore_suspend = 1,
  5904. },
  5905. /* Quaternary AUX PCM Backend DAI Links */
  5906. {
  5907. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5908. .stream_name = "Quat AUX PCM Playback",
  5909. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5910. .platform_name = "msm-pcm-routing",
  5911. .codec_name = "msm-stub-codec.1",
  5912. .codec_dai_name = "msm-stub-rx",
  5913. .no_pcm = 1,
  5914. .dpcm_playback = 1,
  5915. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5916. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5917. .ignore_pmdown_time = 1,
  5918. .ignore_suspend = 1,
  5919. },
  5920. {
  5921. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5922. .stream_name = "Quat AUX PCM Capture",
  5923. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5924. .platform_name = "msm-pcm-routing",
  5925. .codec_name = "msm-stub-codec.1",
  5926. .codec_dai_name = "msm-stub-tx",
  5927. .no_pcm = 1,
  5928. .dpcm_capture = 1,
  5929. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5930. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5931. .ignore_suspend = 1,
  5932. },
  5933. /* Quinary AUX PCM Backend DAI Links */
  5934. {
  5935. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5936. .stream_name = "Quin AUX PCM Playback",
  5937. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5938. .platform_name = "msm-pcm-routing",
  5939. .codec_name = "msm-stub-codec.1",
  5940. .codec_dai_name = "msm-stub-rx",
  5941. .no_pcm = 1,
  5942. .dpcm_playback = 1,
  5943. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5944. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5945. .ignore_pmdown_time = 1,
  5946. .ignore_suspend = 1,
  5947. },
  5948. {
  5949. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5950. .stream_name = "Quin AUX PCM Capture",
  5951. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5952. .platform_name = "msm-pcm-routing",
  5953. .codec_name = "msm-stub-codec.1",
  5954. .codec_dai_name = "msm-stub-tx",
  5955. .no_pcm = 1,
  5956. .dpcm_capture = 1,
  5957. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5958. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5959. .ignore_suspend = 1,
  5960. },
  5961. };
  5962. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5963. /* WSA CDC DMA Backend DAI Links */
  5964. {
  5965. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5966. .stream_name = "WSA CDC DMA0 Playback",
  5967. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5968. .platform_name = "msm-pcm-routing",
  5969. .codec_name = "bolero_codec",
  5970. .codec_dai_name = "wsa_macro_rx1",
  5971. .no_pcm = 1,
  5972. .dpcm_playback = 1,
  5973. .init = &msm_wsa_cdc_dma_init,
  5974. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5975. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5976. .ignore_pmdown_time = 1,
  5977. .ignore_suspend = 1,
  5978. .ops = &msm_cdc_dma_be_ops,
  5979. },
  5980. {
  5981. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5982. .stream_name = "WSA CDC DMA1 Playback",
  5983. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5984. .platform_name = "msm-pcm-routing",
  5985. .codec_name = "bolero_codec",
  5986. .codec_dai_name = "wsa_macro_rx_mix",
  5987. .no_pcm = 1,
  5988. .dpcm_playback = 1,
  5989. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5990. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5991. .ignore_pmdown_time = 1,
  5992. .ignore_suspend = 1,
  5993. .ops = &msm_cdc_dma_be_ops,
  5994. },
  5995. {
  5996. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5997. .stream_name = "WSA CDC DMA1 Capture",
  5998. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  5999. .platform_name = "msm-pcm-routing",
  6000. .codec_name = "bolero_codec",
  6001. .codec_dai_name = "wsa_macro_echo",
  6002. .no_pcm = 1,
  6003. .dpcm_capture = 1,
  6004. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6005. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6006. .ignore_suspend = 1,
  6007. .ops = &msm_cdc_dma_be_ops,
  6008. },
  6009. };
  6010. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6011. {
  6012. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6013. .stream_name = "VA CDC DMA0 Capture",
  6014. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6015. .platform_name = "msm-pcm-routing",
  6016. .codec_name = "bolero_codec",
  6017. .codec_dai_name = "va_macro_tx1",
  6018. .no_pcm = 1,
  6019. .dpcm_capture = 1,
  6020. .init = &msm_va_cdc_dma_init,
  6021. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6022. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6023. .ignore_suspend = 1,
  6024. .ops = &msm_cdc_dma_be_ops,
  6025. },
  6026. {
  6027. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6028. .stream_name = "VA CDC DMA1 Capture",
  6029. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6030. .platform_name = "msm-pcm-routing",
  6031. .codec_name = "bolero_codec",
  6032. .codec_dai_name = "va_macro_tx2",
  6033. .no_pcm = 1,
  6034. .dpcm_capture = 1,
  6035. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6036. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6037. .ignore_suspend = 1,
  6038. .ops = &msm_cdc_dma_be_ops,
  6039. },
  6040. };
  6041. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6042. ARRAY_SIZE(msm_common_dai_links) +
  6043. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6044. ARRAY_SIZE(msm_common_be_dai_links) +
  6045. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6046. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6047. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6048. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6049. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6050. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6051. ARRAY_SIZE(msm_bolero_fe_dai_links)];
  6052. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6053. {
  6054. int ret = 0;
  6055. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6056. &service_nb);
  6057. if (ret < 0)
  6058. pr_err("%s: Audio notifier register failed ret = %d\n",
  6059. __func__, ret);
  6060. return ret;
  6061. }
  6062. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6063. struct snd_ctl_elem_value *ucontrol)
  6064. {
  6065. int ret = 0;
  6066. int port_id;
  6067. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6068. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6069. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6070. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6071. (vad_enable < 0) || (vad_enable > 1) ||
  6072. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6073. pr_err("%s: Invalid arguments\n", __func__);
  6074. ret = -EINVAL;
  6075. goto done;
  6076. }
  6077. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6078. vad_enable, preroll_config, vad_intf);
  6079. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6080. if (ret) {
  6081. pr_err("%s: Invalid vad interface\n", __func__);
  6082. goto done;
  6083. }
  6084. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6085. done:
  6086. return ret;
  6087. }
  6088. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6089. {
  6090. int ret = 0;
  6091. uint32_t tasha_codec = 0;
  6092. ret = afe_cal_init_hwdep(card);
  6093. if (ret) {
  6094. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6095. ret = 0;
  6096. }
  6097. /* tasha late probe when it is present */
  6098. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6099. &tasha_codec);
  6100. if (ret) {
  6101. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6102. ret = 0;
  6103. } else {
  6104. if (tasha_codec) {
  6105. ret = msm_snd_card_tasha_late_probe(card);
  6106. if (ret)
  6107. dev_err(card->dev, "%s: tasha late probe err\n",
  6108. __func__);
  6109. }
  6110. }
  6111. return ret;
  6112. }
  6113. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6114. .name = "qcs405-snd-card",
  6115. .controls = msm_snd_controls,
  6116. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6117. .late_probe = msm_snd_card_codec_late_probe,
  6118. };
  6119. static int msm_populate_dai_link_component_of_node(
  6120. struct snd_soc_card *card)
  6121. {
  6122. int i, index, ret = 0;
  6123. struct device *cdev = card->dev;
  6124. struct snd_soc_dai_link *dai_link = card->dai_link;
  6125. struct device_node *np;
  6126. if (!cdev) {
  6127. pr_err("%s: Sound card device memory NULL\n", __func__);
  6128. return -ENODEV;
  6129. }
  6130. for (i = 0; i < card->num_links; i++) {
  6131. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6132. continue;
  6133. /* populate platform_of_node for snd card dai links */
  6134. if (dai_link[i].platform_name &&
  6135. !dai_link[i].platform_of_node) {
  6136. index = of_property_match_string(cdev->of_node,
  6137. "asoc-platform-names",
  6138. dai_link[i].platform_name);
  6139. if (index < 0) {
  6140. pr_err("%s: No match found for platform name: %s\n",
  6141. __func__, dai_link[i].platform_name);
  6142. ret = index;
  6143. goto err;
  6144. }
  6145. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6146. index);
  6147. if (!np) {
  6148. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6149. __func__, dai_link[i].platform_name,
  6150. index);
  6151. ret = -ENODEV;
  6152. goto err;
  6153. }
  6154. dai_link[i].platform_of_node = np;
  6155. dai_link[i].platform_name = NULL;
  6156. }
  6157. /* populate cpu_of_node for snd card dai links */
  6158. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6159. index = of_property_match_string(cdev->of_node,
  6160. "asoc-cpu-names",
  6161. dai_link[i].cpu_dai_name);
  6162. if (index >= 0) {
  6163. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6164. index);
  6165. if (!np) {
  6166. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6167. __func__,
  6168. dai_link[i].cpu_dai_name);
  6169. ret = -ENODEV;
  6170. goto err;
  6171. }
  6172. dai_link[i].cpu_of_node = np;
  6173. dai_link[i].cpu_dai_name = NULL;
  6174. }
  6175. }
  6176. /* populate codec_of_node for snd card dai links */
  6177. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6178. index = of_property_match_string(cdev->of_node,
  6179. "asoc-codec-names",
  6180. dai_link[i].codec_name);
  6181. if (index < 0)
  6182. continue;
  6183. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6184. index);
  6185. if (!np) {
  6186. pr_err("%s: retrieving phandle for codec %s failed\n",
  6187. __func__, dai_link[i].codec_name);
  6188. ret = -ENODEV;
  6189. goto err;
  6190. }
  6191. dai_link[i].codec_of_node = np;
  6192. dai_link[i].codec_name = NULL;
  6193. }
  6194. }
  6195. err:
  6196. return ret;
  6197. }
  6198. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6199. /* FrontEnd DAI Links */
  6200. {
  6201. .name = "MSMSTUB Media1",
  6202. .stream_name = "MultiMedia1",
  6203. .cpu_dai_name = "MultiMedia1",
  6204. .platform_name = "msm-pcm-dsp.0",
  6205. .dynamic = 1,
  6206. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6207. .dpcm_playback = 1,
  6208. .dpcm_capture = 1,
  6209. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6210. SND_SOC_DPCM_TRIGGER_POST},
  6211. .codec_dai_name = "snd-soc-dummy-dai",
  6212. .codec_name = "snd-soc-dummy",
  6213. .ignore_suspend = 1,
  6214. /* this dainlink has playback support */
  6215. .ignore_pmdown_time = 1,
  6216. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6217. },
  6218. };
  6219. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6220. /* Backend DAI Links */
  6221. {
  6222. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6223. .stream_name = "VA CDC DMA0 Capture",
  6224. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6225. .platform_name = "msm-pcm-routing",
  6226. .codec_name = "bolero_codec",
  6227. .codec_dai_name = "va_macro_tx1",
  6228. .no_pcm = 1,
  6229. .dpcm_capture = 1,
  6230. .init = &msm_va_cdc_dma_init,
  6231. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6232. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6233. .ignore_suspend = 1,
  6234. .ops = &msm_cdc_dma_be_ops,
  6235. },
  6236. {
  6237. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6238. .stream_name = "VA CDC DMA1 Capture",
  6239. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6240. .platform_name = "msm-pcm-routing",
  6241. .codec_name = "bolero_codec",
  6242. .codec_dai_name = "va_macro_tx2",
  6243. .no_pcm = 1,
  6244. .dpcm_capture = 1,
  6245. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6246. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6247. .ignore_suspend = 1,
  6248. .ops = &msm_cdc_dma_be_ops,
  6249. },
  6250. };
  6251. static struct snd_soc_dai_link msm_stub_dai_links[
  6252. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6253. ARRAY_SIZE(msm_stub_be_dai_links)];
  6254. struct snd_soc_card snd_soc_card_stub_msm = {
  6255. .name = "qcs405-stub-snd-card",
  6256. };
  6257. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6258. { .compatible = "qcom,qcs405-asoc-snd",
  6259. .data = "codec"},
  6260. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6261. .data = "stub_codec"},
  6262. {},
  6263. };
  6264. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6265. {
  6266. struct snd_soc_card *card = NULL;
  6267. struct snd_soc_dai_link *dailink;
  6268. int total_links = 0;
  6269. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6270. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6271. const struct of_device_id *match;
  6272. int rc = 0;
  6273. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6274. if (!match) {
  6275. dev_err(dev, "%s: No DT match found for sound card\n",
  6276. __func__);
  6277. return NULL;
  6278. }
  6279. if (!strcmp(match->data, "codec")) {
  6280. card = &snd_soc_card_qcs405_msm;
  6281. memcpy(msm_qcs405_dai_links + total_links,
  6282. msm_common_dai_links,
  6283. sizeof(msm_common_dai_links));
  6284. total_links += ARRAY_SIZE(msm_common_dai_links);
  6285. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6286. &wsa_bolero_codec);
  6287. if (rc) {
  6288. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6289. __func__);
  6290. } else {
  6291. if (wsa_bolero_codec) {
  6292. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6293. __func__);
  6294. memcpy(msm_qcs405_dai_links + total_links,
  6295. msm_bolero_fe_dai_links,
  6296. sizeof(msm_bolero_fe_dai_links));
  6297. total_links +=
  6298. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6299. }
  6300. }
  6301. memcpy(msm_qcs405_dai_links + total_links,
  6302. msm_common_misc_fe_dai_links,
  6303. sizeof(msm_common_misc_fe_dai_links));
  6304. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6305. memcpy(msm_qcs405_dai_links + total_links,
  6306. msm_common_be_dai_links,
  6307. sizeof(msm_common_be_dai_links));
  6308. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6309. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6310. &tasha_codec);
  6311. if (rc) {
  6312. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6313. __func__);
  6314. } else {
  6315. if (tasha_codec) {
  6316. memcpy(msm_qcs405_dai_links + total_links,
  6317. msm_tasha_be_dai_links,
  6318. sizeof(msm_tasha_be_dai_links));
  6319. total_links +=
  6320. ARRAY_SIZE(msm_tasha_be_dai_links);
  6321. }
  6322. }
  6323. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6324. &va_bolero_codec);
  6325. if (rc) {
  6326. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6327. __func__);
  6328. } else {
  6329. if (va_bolero_codec) {
  6330. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6331. __func__);
  6332. memcpy(msm_qcs405_dai_links + total_links,
  6333. msm_va_cdc_dma_be_dai_links,
  6334. sizeof(msm_va_cdc_dma_be_dai_links));
  6335. total_links +=
  6336. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6337. }
  6338. }
  6339. if (wsa_bolero_codec) {
  6340. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6341. __func__);
  6342. memcpy(msm_qcs405_dai_links + total_links,
  6343. msm_wsa_cdc_dma_be_dai_links,
  6344. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6345. total_links +=
  6346. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6347. }
  6348. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6349. &mi2s_audio_intf);
  6350. if (rc) {
  6351. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6352. __func__);
  6353. } else {
  6354. if (mi2s_audio_intf) {
  6355. memcpy(msm_qcs405_dai_links + total_links,
  6356. msm_mi2s_be_dai_links,
  6357. sizeof(msm_mi2s_be_dai_links));
  6358. total_links +=
  6359. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6360. }
  6361. }
  6362. rc = of_property_read_u32(dev->of_node,
  6363. "qcom,auxpcm-audio-intf",
  6364. &auxpcm_audio_intf);
  6365. if (rc) {
  6366. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6367. __func__);
  6368. } else {
  6369. if (auxpcm_audio_intf) {
  6370. memcpy(msm_qcs405_dai_links + total_links,
  6371. msm_auxpcm_be_dai_links,
  6372. sizeof(msm_auxpcm_be_dai_links));
  6373. total_links +=
  6374. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6375. }
  6376. }
  6377. dailink = msm_qcs405_dai_links;
  6378. } else if (!strcmp(match->data, "stub_codec")) {
  6379. card = &snd_soc_card_stub_msm;
  6380. memcpy(msm_stub_dai_links + total_links,
  6381. msm_stub_fe_dai_links,
  6382. sizeof(msm_stub_fe_dai_links));
  6383. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6384. memcpy(msm_stub_dai_links + total_links,
  6385. msm_stub_be_dai_links,
  6386. sizeof(msm_stub_be_dai_links));
  6387. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6388. dailink = msm_stub_dai_links;
  6389. }
  6390. if (card) {
  6391. card->dai_link = dailink;
  6392. card->num_links = total_links;
  6393. }
  6394. return card;
  6395. }
  6396. static int msm_wsa881x_init(struct snd_soc_component *component)
  6397. {
  6398. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6399. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6400. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6401. SPKR_L_BOOST, SPKR_L_VI};
  6402. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6403. SPKR_R_BOOST, SPKR_R_VI};
  6404. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6405. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6406. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6407. struct msm_asoc_mach_data *pdata;
  6408. struct snd_soc_dapm_context *dapm;
  6409. int ret = 0;
  6410. if (!codec) {
  6411. pr_err("%s codec is NULL\n", __func__);
  6412. return -EINVAL;
  6413. }
  6414. dapm = snd_soc_codec_get_dapm(codec);
  6415. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6416. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6417. __func__, codec->component.name);
  6418. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6419. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6420. &ch_rate[0], &spkleft_port_types[0]);
  6421. if (dapm->component) {
  6422. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6423. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6424. }
  6425. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6426. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6427. __func__, codec->component.name);
  6428. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6429. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6430. &ch_rate[0], &spkright_port_types[0]);
  6431. if (dapm->component) {
  6432. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6433. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6434. }
  6435. } else {
  6436. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6437. codec->component.name);
  6438. ret = -EINVAL;
  6439. goto err;
  6440. }
  6441. pdata = snd_soc_card_get_drvdata(component->card);
  6442. if (pdata && pdata->codec_root)
  6443. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6444. codec);
  6445. err:
  6446. return ret;
  6447. }
  6448. static int msm_init_wsa_dev(struct platform_device *pdev,
  6449. struct snd_soc_card *card)
  6450. {
  6451. struct device_node *wsa_of_node;
  6452. u32 wsa_max_devs;
  6453. u32 wsa_dev_cnt;
  6454. int i;
  6455. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6456. const char *wsa_auxdev_name_prefix[1];
  6457. char *dev_name_str = NULL;
  6458. int found = 0;
  6459. int ret = 0;
  6460. /* Get maximum WSA device count for this platform */
  6461. ret = of_property_read_u32(pdev->dev.of_node,
  6462. "qcom,wsa-max-devs", &wsa_max_devs);
  6463. if (ret) {
  6464. dev_info(&pdev->dev,
  6465. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6466. __func__, pdev->dev.of_node->full_name, ret);
  6467. card->num_aux_devs = 0;
  6468. return 0;
  6469. }
  6470. if (wsa_max_devs == 0) {
  6471. dev_warn(&pdev->dev,
  6472. "%s: Max WSA devices is 0 for this target?\n",
  6473. __func__);
  6474. card->num_aux_devs = 0;
  6475. return 0;
  6476. }
  6477. /* Get count of WSA device phandles for this platform */
  6478. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6479. "qcom,wsa-devs", NULL);
  6480. if (wsa_dev_cnt == -ENOENT) {
  6481. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6482. __func__);
  6483. goto err;
  6484. } else if (wsa_dev_cnt <= 0) {
  6485. dev_err(&pdev->dev,
  6486. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6487. __func__, wsa_dev_cnt);
  6488. ret = -EINVAL;
  6489. goto err;
  6490. }
  6491. /*
  6492. * Expect total phandles count to be NOT less than maximum possible
  6493. * WSA count. However, if it is less, then assign same value to
  6494. * max count as well.
  6495. */
  6496. if (wsa_dev_cnt < wsa_max_devs) {
  6497. dev_dbg(&pdev->dev,
  6498. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6499. __func__, wsa_max_devs, wsa_dev_cnt);
  6500. wsa_max_devs = wsa_dev_cnt;
  6501. }
  6502. /* Make sure prefix string passed for each WSA device */
  6503. ret = of_property_count_strings(pdev->dev.of_node,
  6504. "qcom,wsa-aux-dev-prefix");
  6505. if (ret != wsa_dev_cnt) {
  6506. dev_err(&pdev->dev,
  6507. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6508. __func__, wsa_dev_cnt, ret);
  6509. ret = -EINVAL;
  6510. goto err;
  6511. }
  6512. /*
  6513. * Alloc mem to store phandle and index info of WSA device, if already
  6514. * registered with ALSA core
  6515. */
  6516. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6517. sizeof(struct msm_wsa881x_dev_info),
  6518. GFP_KERNEL);
  6519. if (!wsa881x_dev_info) {
  6520. ret = -ENOMEM;
  6521. goto err;
  6522. }
  6523. /*
  6524. * search and check whether all WSA devices are already
  6525. * registered with ALSA core or not. If found a node, store
  6526. * the node and the index in a local array of struct for later
  6527. * use.
  6528. */
  6529. for (i = 0; i < wsa_dev_cnt; i++) {
  6530. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6531. "qcom,wsa-devs", i);
  6532. if (unlikely(!wsa_of_node)) {
  6533. /* we should not be here */
  6534. dev_err(&pdev->dev,
  6535. "%s: wsa dev node is not present\n",
  6536. __func__);
  6537. ret = -EINVAL;
  6538. goto err_free_dev_info;
  6539. }
  6540. if (soc_find_component(wsa_of_node, NULL)) {
  6541. /* WSA device registered with ALSA core */
  6542. wsa881x_dev_info[found].of_node = wsa_of_node;
  6543. wsa881x_dev_info[found].index = i;
  6544. found++;
  6545. if (found == wsa_max_devs)
  6546. break;
  6547. }
  6548. }
  6549. if (found < wsa_max_devs) {
  6550. dev_err(&pdev->dev,
  6551. "%s: failed to find %d components. Found only %d\n",
  6552. __func__, wsa_max_devs, found);
  6553. return -EPROBE_DEFER;
  6554. }
  6555. dev_info(&pdev->dev,
  6556. "%s: found %d wsa881x devices registered with ALSA core\n",
  6557. __func__, found);
  6558. card->num_aux_devs = wsa_max_devs;
  6559. card->num_configs = wsa_max_devs;
  6560. /* Alloc array of AUX devs struct */
  6561. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6562. sizeof(struct snd_soc_aux_dev),
  6563. GFP_KERNEL);
  6564. if (!msm_aux_dev) {
  6565. ret = -ENOMEM;
  6566. goto err_free_dev_info;
  6567. }
  6568. /* Alloc array of codec conf struct */
  6569. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6570. sizeof(struct snd_soc_codec_conf),
  6571. GFP_KERNEL);
  6572. if (!msm_codec_conf) {
  6573. ret = -ENOMEM;
  6574. goto err_free_aux_dev;
  6575. }
  6576. for (i = 0; i < card->num_aux_devs; i++) {
  6577. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6578. GFP_KERNEL);
  6579. if (!dev_name_str) {
  6580. ret = -ENOMEM;
  6581. goto err_free_cdc_conf;
  6582. }
  6583. ret = of_property_read_string_index(pdev->dev.of_node,
  6584. "qcom,wsa-aux-dev-prefix",
  6585. wsa881x_dev_info[i].index,
  6586. wsa_auxdev_name_prefix);
  6587. if (ret) {
  6588. dev_err(&pdev->dev,
  6589. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6590. __func__, ret);
  6591. ret = -EINVAL;
  6592. goto err_free_dev_name_str;
  6593. }
  6594. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6595. msm_aux_dev[i].name = dev_name_str;
  6596. msm_aux_dev[i].codec_name = NULL;
  6597. msm_aux_dev[i].codec_of_node =
  6598. wsa881x_dev_info[i].of_node;
  6599. msm_aux_dev[i].init = msm_wsa881x_init;
  6600. msm_codec_conf[i].dev_name = NULL;
  6601. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6602. msm_codec_conf[i].of_node =
  6603. wsa881x_dev_info[i].of_node;
  6604. }
  6605. card->codec_conf = msm_codec_conf;
  6606. card->aux_dev = msm_aux_dev;
  6607. return 0;
  6608. err_free_dev_name_str:
  6609. devm_kfree(&pdev->dev, dev_name_str);
  6610. err_free_cdc_conf:
  6611. devm_kfree(&pdev->dev, msm_codec_conf);
  6612. err_free_aux_dev:
  6613. devm_kfree(&pdev->dev, msm_aux_dev);
  6614. err_free_dev_info:
  6615. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6616. err:
  6617. return ret;
  6618. }
  6619. static int msm_csra66x0_init(struct snd_soc_component *component)
  6620. {
  6621. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6622. if (!codec) {
  6623. pr_err("%s codec is NULL\n", __func__);
  6624. return -EINVAL;
  6625. }
  6626. return 0;
  6627. }
  6628. static int msm_init_csra_dev(struct platform_device *pdev,
  6629. struct snd_soc_card *card)
  6630. {
  6631. struct device_node *csra_of_node;
  6632. u32 csra_max_devs;
  6633. u32 csra_dev_cnt;
  6634. char *dev_name_str = NULL;
  6635. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  6636. const char *csra_auxdev_name_prefix[1];
  6637. int i;
  6638. int found = 0;
  6639. int ret = 0;
  6640. /* Get maximum CSRA device count for this platform */
  6641. ret = of_property_read_u32(pdev->dev.of_node,
  6642. "qcom,csra-max-devs", &csra_max_devs);
  6643. if (ret) {
  6644. dev_info(&pdev->dev,
  6645. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  6646. __func__, pdev->dev.of_node->full_name, ret);
  6647. card->num_aux_devs = 0;
  6648. return 0;
  6649. }
  6650. if (csra_max_devs == 0) {
  6651. dev_warn(&pdev->dev,
  6652. "%s: Max CSRA devices is 0 for this target?\n",
  6653. __func__);
  6654. return 0;
  6655. }
  6656. /* Get count of CSRA device phandles for this platform */
  6657. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6658. "qcom,csra-devs", NULL);
  6659. if (csra_dev_cnt == -ENOENT) {
  6660. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  6661. __func__);
  6662. goto err;
  6663. } else if (csra_dev_cnt <= 0) {
  6664. dev_err(&pdev->dev,
  6665. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  6666. __func__, csra_dev_cnt);
  6667. ret = -EINVAL;
  6668. goto err;
  6669. }
  6670. /*
  6671. * Expect total phandles count to be NOT less than maximum possible
  6672. * CSRA count. However, if it is less, then assign same value to
  6673. * max count as well.
  6674. */
  6675. if (csra_dev_cnt < csra_max_devs) {
  6676. dev_dbg(&pdev->dev,
  6677. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  6678. __func__, csra_max_devs, csra_dev_cnt);
  6679. csra_max_devs = csra_dev_cnt;
  6680. }
  6681. /* Make sure prefix string passed for each CSRA device */
  6682. ret = of_property_count_strings(pdev->dev.of_node,
  6683. "qcom,csra-aux-dev-prefix");
  6684. if (ret != csra_dev_cnt) {
  6685. dev_err(&pdev->dev,
  6686. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  6687. __func__, csra_dev_cnt, ret);
  6688. ret = -EINVAL;
  6689. goto err;
  6690. }
  6691. /*
  6692. * Alloc mem to store phandle and index info of CSRA device, if already
  6693. * registered with ALSA core
  6694. */
  6695. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  6696. sizeof(struct msm_csra66x0_dev_info),
  6697. GFP_KERNEL);
  6698. if (!csra66x0_dev_info) {
  6699. ret = -ENOMEM;
  6700. goto err;
  6701. }
  6702. /*
  6703. * search and check whether all CSRA devices are already
  6704. * registered with ALSA core or not. If found a node, store
  6705. * the node and the index in a local array of struct for later
  6706. * use.
  6707. */
  6708. for (i = 0; i < csra_dev_cnt; i++) {
  6709. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  6710. "qcom,csra-devs", i);
  6711. if (unlikely(!csra_of_node)) {
  6712. /* we should not be here */
  6713. dev_err(&pdev->dev,
  6714. "%s: csra dev node is not present\n",
  6715. __func__);
  6716. ret = -EINVAL;
  6717. goto err_free_dev_info;
  6718. }
  6719. if (soc_find_component(csra_of_node, NULL)) {
  6720. /* CSRA device registered with ALSA core */
  6721. csra66x0_dev_info[found].of_node = csra_of_node;
  6722. csra66x0_dev_info[found].index = i;
  6723. found++;
  6724. if (found == csra_max_devs)
  6725. break;
  6726. }
  6727. }
  6728. if (found < csra_max_devs) {
  6729. dev_dbg(&pdev->dev,
  6730. "%s: failed to find %d components. Found only %d\n",
  6731. __func__, csra_max_devs, found);
  6732. return -EPROBE_DEFER;
  6733. }
  6734. dev_info(&pdev->dev,
  6735. "%s: found %d csra66x0 devices registered with ALSA core\n",
  6736. __func__, found);
  6737. card->num_aux_devs = csra_max_devs;
  6738. card->num_configs = csra_max_devs;
  6739. /* Alloc array of AUX devs struct */
  6740. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6741. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  6742. if (!msm_aux_dev) {
  6743. ret = -ENOMEM;
  6744. goto err_free_dev_info;
  6745. }
  6746. /* Alloc array of codec conf struct */
  6747. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6748. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  6749. if (!msm_codec_conf) {
  6750. ret = -ENOMEM;
  6751. goto err_free_aux_dev;
  6752. }
  6753. for (i = 0; i < card->num_aux_devs; i++) {
  6754. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6755. GFP_KERNEL);
  6756. if (!dev_name_str) {
  6757. ret = -ENOMEM;
  6758. goto err_free_cdc_conf;
  6759. }
  6760. ret = of_property_read_string_index(pdev->dev.of_node,
  6761. "qcom,csra-aux-dev-prefix",
  6762. csra66x0_dev_info[i].index,
  6763. csra_auxdev_name_prefix);
  6764. if (ret) {
  6765. dev_err(&pdev->dev,
  6766. "%s: failed to read csra aux dev prefix, ret = %d\n",
  6767. __func__, ret);
  6768. ret = -EINVAL;
  6769. goto err_free_dev_name_str;
  6770. }
  6771. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  6772. msm_aux_dev[i].name = dev_name_str;
  6773. msm_aux_dev[i].codec_name = NULL;
  6774. msm_aux_dev[i].codec_of_node =
  6775. csra66x0_dev_info[i].of_node;
  6776. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  6777. msm_codec_conf[i].dev_name = NULL;
  6778. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  6779. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  6780. }
  6781. card->codec_conf = msm_codec_conf;
  6782. card->aux_dev = msm_aux_dev;
  6783. return 0;
  6784. err_free_dev_name_str:
  6785. devm_kfree(&pdev->dev, dev_name_str);
  6786. err_free_cdc_conf:
  6787. devm_kfree(&pdev->dev, msm_codec_conf);
  6788. err_free_aux_dev:
  6789. devm_kfree(&pdev->dev, msm_aux_dev);
  6790. err_free_dev_info:
  6791. devm_kfree(&pdev->dev, csra66x0_dev_info);
  6792. err:
  6793. return ret;
  6794. }
  6795. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6796. {
  6797. int count;
  6798. u32 mi2s_master_slave[MI2S_MAX];
  6799. int ret;
  6800. for (count = 0; count < MI2S_MAX; count++) {
  6801. mutex_init(&mi2s_intf_conf[count].lock);
  6802. mi2s_intf_conf[count].ref_cnt = 0;
  6803. }
  6804. ret = of_property_read_u32_array(pdev->dev.of_node,
  6805. "qcom,msm-mi2s-master",
  6806. mi2s_master_slave, MI2S_MAX);
  6807. if (ret) {
  6808. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6809. __func__);
  6810. } else {
  6811. for (count = 0; count < MI2S_MAX; count++) {
  6812. mi2s_intf_conf[count].msm_is_mi2s_master =
  6813. mi2s_master_slave[count];
  6814. }
  6815. }
  6816. }
  6817. static void msm_i2s_auxpcm_deinit(void)
  6818. {
  6819. int count;
  6820. for (count = 0; count < MI2S_MAX; count++) {
  6821. mutex_destroy(&mi2s_intf_conf[count].lock);
  6822. mi2s_intf_conf[count].ref_cnt = 0;
  6823. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6824. }
  6825. }
  6826. static int msm_scan_i2c_addr(struct platform_device *pdev,
  6827. uint32_t busnum, uint32_t addr)
  6828. {
  6829. struct i2c_adapter *adap;
  6830. u8 rbuf;
  6831. struct i2c_msg msg;
  6832. int status = 0;
  6833. adap = i2c_get_adapter(busnum);
  6834. if (!adap) {
  6835. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  6836. __func__, busnum);
  6837. return -EBUSY;
  6838. }
  6839. /* to test presence, read one byte from device */
  6840. msg.addr = addr;
  6841. msg.flags = I2C_M_RD;
  6842. msg.len = 1;
  6843. msg.buf = &rbuf;
  6844. status = i2c_transfer(adap, &msg, 1);
  6845. i2c_put_adapter(adap);
  6846. if (status != 1) {
  6847. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  6848. __func__, addr);
  6849. return -ENODEV;
  6850. }
  6851. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  6852. __func__, addr);
  6853. return 0;
  6854. }
  6855. static int msm_detect_ep92_dev(struct platform_device *pdev,
  6856. struct snd_soc_card *card)
  6857. {
  6858. int i;
  6859. uint32_t ep92_busnum = 0;
  6860. uint32_t ep92_reg = 0;
  6861. const char *ep92_name = NULL;
  6862. struct snd_soc_dai_link *dai;
  6863. int rc = 0;
  6864. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  6865. &ep92_busnum);
  6866. if (rc) {
  6867. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  6868. return 0;
  6869. }
  6870. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  6871. &ep92_reg);
  6872. if (rc) {
  6873. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  6874. return 0;
  6875. }
  6876. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  6877. &ep92_name);
  6878. if (rc) {
  6879. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  6880. return 0;
  6881. }
  6882. /* check I2C bus for connected ep92 chip */
  6883. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  6884. /* check a second time after a short delay */
  6885. msleep(20);
  6886. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  6887. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  6888. __func__);
  6889. /* continue with snd_card registration without ep92 */
  6890. return 0;
  6891. }
  6892. }
  6893. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  6894. /* update codec info in MI2S dai link */
  6895. dai = &msm_mi2s_be_dai_links[0];
  6896. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  6897. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  6898. dev_dbg(&pdev->dev,
  6899. "%s: Set Sec MI2S dai to ep92 codec\n",
  6900. __func__);
  6901. dai->codec_name = ep92_name;
  6902. dai->codec_dai_name = "ep92-hdmi";
  6903. break;
  6904. }
  6905. dai++;
  6906. }
  6907. /* update codec info in SPDIF dai link */
  6908. dai = &msm_spdif_be_dai_links[0];
  6909. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  6910. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  6911. dev_dbg(&pdev->dev,
  6912. "%s: Set Sec SPDIF dai to ep92 codec\n",
  6913. __func__);
  6914. dai->codec_name = ep92_name;
  6915. dai->codec_dai_name = "ep92-arc";
  6916. break;
  6917. }
  6918. dai++;
  6919. }
  6920. return 0;
  6921. }
  6922. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6923. {
  6924. struct snd_soc_card *card;
  6925. struct msm_asoc_mach_data *pdata;
  6926. int ret;
  6927. u32 val;
  6928. if (!pdev->dev.of_node) {
  6929. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6930. return -EINVAL;
  6931. }
  6932. pdata = devm_kzalloc(&pdev->dev,
  6933. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6934. if (!pdata)
  6935. return -ENOMEM;
  6936. /* test for ep92 HDMI bridge and update dai links accordingly */
  6937. ret = msm_detect_ep92_dev(pdev, card);
  6938. if (ret)
  6939. goto err;
  6940. card = populate_snd_card_dailinks(&pdev->dev);
  6941. if (!card) {
  6942. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6943. ret = -EINVAL;
  6944. goto err;
  6945. }
  6946. card->dev = &pdev->dev;
  6947. platform_set_drvdata(pdev, card);
  6948. snd_soc_card_set_drvdata(card, pdata);
  6949. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6950. if (ret) {
  6951. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6952. ret);
  6953. goto err;
  6954. }
  6955. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6956. if (ret) {
  6957. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6958. ret);
  6959. goto err;
  6960. }
  6961. ret = msm_populate_dai_link_component_of_node(card);
  6962. if (ret) {
  6963. ret = -EPROBE_DEFER;
  6964. goto err;
  6965. }
  6966. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  6967. if (ret) {
  6968. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  6969. val = 0;
  6970. }
  6971. if (val) {
  6972. ret = msm_init_csra_dev(pdev, card);
  6973. if (ret)
  6974. goto err;
  6975. } else {
  6976. ret = msm_init_wsa_dev(pdev, card);
  6977. if (ret)
  6978. goto err;
  6979. }
  6980. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6981. "qcom,cdc-dmic01-gpios",
  6982. 0);
  6983. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6984. "qcom,cdc-dmic23-gpios",
  6985. 0);
  6986. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6987. "qcom,cdc-dmic45-gpios",
  6988. 0);
  6989. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6990. "qcom,cdc-dmic67-gpios",
  6991. 0);
  6992. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6993. if (ret == -EPROBE_DEFER) {
  6994. if (codec_reg_done)
  6995. ret = -EINVAL;
  6996. goto err;
  6997. } else if (ret) {
  6998. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6999. ret);
  7000. goto err;
  7001. }
  7002. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7003. spdev = pdev;
  7004. /* Parse pinctrl info from devicetree */
  7005. ret = msm_get_pinctrl(pdev);
  7006. if (!ret) {
  7007. pr_debug("%s: pinctrl parsing successful\n", __func__);
  7008. } else {
  7009. dev_dbg(&pdev->dev,
  7010. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  7011. __func__, ret);
  7012. ret = 0;
  7013. }
  7014. msm_i2s_auxpcm_init(pdev);
  7015. is_initial_boot = true;
  7016. return 0;
  7017. err:
  7018. msm_release_pinctrl(pdev);
  7019. return ret;
  7020. }
  7021. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7022. {
  7023. audio_notifier_deregister("qcs405");
  7024. msm_i2s_auxpcm_deinit();
  7025. msm_release_pinctrl(pdev);
  7026. return 0;
  7027. }
  7028. static struct platform_driver qcs405_asoc_machine_driver = {
  7029. .driver = {
  7030. .name = DRV_NAME,
  7031. .owner = THIS_MODULE,
  7032. .pm = &snd_soc_pm_ops,
  7033. .of_match_table = qcs405_asoc_machine_of_match,
  7034. },
  7035. .probe = msm_asoc_machine_probe,
  7036. .remove = msm_asoc_machine_remove,
  7037. };
  7038. module_platform_driver(qcs405_asoc_machine_driver);
  7039. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7040. MODULE_LICENSE("GPL v2");
  7041. MODULE_ALIAS("platform:" DRV_NAME);
  7042. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);