dp_tx.c 95 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #define DP_TX_QUEUE_MASK 0x3
  32. /* TODO Add support in TSO */
  33. #define DP_DESC_NUM_FRAG(x) 0
  34. /* disable TQM_BYPASS */
  35. #define TQM_BYPASS_WAR 0
  36. /* invalid peer id for reinject*/
  37. #define DP_INVALID_PEER 0XFFFE
  38. /*mapping between hal encrypt type and cdp_sec_type*/
  39. #define MAX_CDP_SEC_TYPE 12
  40. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  41. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  42. HAL_TX_ENCRYPT_TYPE_WEP_128,
  43. HAL_TX_ENCRYPT_TYPE_WEP_104,
  44. HAL_TX_ENCRYPT_TYPE_WEP_40,
  45. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  47. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  48. HAL_TX_ENCRYPT_TYPE_WAPI,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  50. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  53. /**
  54. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  55. * @vdev: DP Virtual device handle
  56. * @nbuf: Buffer pointer
  57. * @queue: queue ids container for nbuf
  58. *
  59. * TX packet queue has 2 instances, software descriptors id and dma ring id
  60. * Based on tx feature and hardware configuration queue id combination could be
  61. * different.
  62. * For example -
  63. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  64. * With no XPS,lock based resource protection, Descriptor pool ids are different
  65. * for each vdev, dma ring id will be same as single pdev id
  66. *
  67. * Return: None
  68. */
  69. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  70. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  71. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  72. {
  73. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  74. queue->desc_pool_id = queue_offset;
  75. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  76. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  77. "%s, pool_id:%d ring_id: %d",
  78. __func__, queue->desc_pool_id, queue->ring_id);
  79. return;
  80. }
  81. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  82. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  83. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  84. {
  85. /* get flow id */
  86. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  87. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  89. "%s, pool_id:%d ring_id: %d",
  90. __func__, queue->desc_pool_id, queue->ring_id);
  91. return;
  92. }
  93. #endif
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  167. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  170. qdf_atomic_dec(&pdev->num_tx_exception);
  171. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  172. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  173. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  174. else
  175. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  177. "Tx Completion Release desc %d status %d outstanding %d",
  178. tx_desc->id, comp_status,
  179. qdf_atomic_read(&pdev->num_tx_outstanding));
  180. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  181. return;
  182. }
  183. /**
  184. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  185. * @vdev: DP vdev Handle
  186. * @nbuf: skb
  187. *
  188. * Prepares and fills HTT metadata in the frame pre-header for special frames
  189. * that should be transmitted using varying transmit parameters.
  190. * There are 2 VDEV modes that currently needs this special metadata -
  191. * 1) Mesh Mode
  192. * 2) DSRC Mode
  193. *
  194. * Return: HTT metadata size
  195. *
  196. */
  197. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  198. uint32_t *meta_data)
  199. {
  200. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  201. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  202. uint8_t htt_desc_size;
  203. /* Size rounded of multiple of 8 bytes */
  204. uint8_t htt_desc_size_aligned;
  205. uint8_t *hdr = NULL;
  206. /*
  207. * Metadata - HTT MSDU Extension header
  208. */
  209. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  210. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  211. if (vdev->mesh_vdev) {
  212. /* Fill and add HTT metaheader */
  213. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  214. if (hdr == NULL) {
  215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  216. "Error in filling HTT metadata\n");
  217. return 0;
  218. }
  219. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  220. } else if (vdev->opmode == wlan_op_mode_ocb) {
  221. /* Todo - Add support for DSRC */
  222. }
  223. return htt_desc_size_aligned;
  224. }
  225. /**
  226. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  227. * @tso_seg: TSO segment to process
  228. * @ext_desc: Pointer to MSDU extension descriptor
  229. *
  230. * Return: void
  231. */
  232. #if defined(FEATURE_TSO)
  233. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  234. void *ext_desc)
  235. {
  236. uint8_t num_frag;
  237. uint32_t tso_flags;
  238. /*
  239. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  240. * tcp_flag_mask
  241. *
  242. * Checksum enable flags are set in TCL descriptor and not in Extension
  243. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  244. */
  245. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  246. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  247. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  248. tso_seg->tso_flags.ip_len);
  249. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  250. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  251. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  252. uint32_t lo = 0;
  253. uint32_t hi = 0;
  254. qdf_dmaaddr_to_32s(
  255. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  256. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  257. tso_seg->tso_frags[num_frag].length);
  258. }
  259. return;
  260. }
  261. #else
  262. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  263. void *ext_desc)
  264. {
  265. return;
  266. }
  267. #endif
  268. #if defined(FEATURE_TSO)
  269. /**
  270. * dp_tx_free_tso_seg() - Loop through the tso segments
  271. * allocated and free them
  272. *
  273. * @soc: soc handle
  274. * @free_seg: list of tso segments
  275. * @msdu_info: msdu descriptor
  276. *
  277. * Return - void
  278. */
  279. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  280. struct qdf_tso_seg_elem_t *free_seg,
  281. struct dp_tx_msdu_info_s *msdu_info)
  282. {
  283. struct qdf_tso_seg_elem_t *next_seg;
  284. while (free_seg) {
  285. next_seg = free_seg->next;
  286. dp_tx_tso_desc_free(soc,
  287. msdu_info->tx_queue.desc_pool_id,
  288. free_seg);
  289. free_seg = next_seg;
  290. }
  291. }
  292. /**
  293. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  294. * allocated and free them
  295. *
  296. * @soc: soc handle
  297. * @free_seg: list of tso segments
  298. * @msdu_info: msdu descriptor
  299. * Return - void
  300. */
  301. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  302. struct qdf_tso_num_seg_elem_t *free_seg,
  303. struct dp_tx_msdu_info_s *msdu_info)
  304. {
  305. struct qdf_tso_num_seg_elem_t *next_seg;
  306. while (free_seg) {
  307. next_seg = free_seg->next;
  308. dp_tso_num_seg_free(soc,
  309. msdu_info->tx_queue.desc_pool_id,
  310. free_seg);
  311. free_seg = next_seg;
  312. }
  313. }
  314. /**
  315. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  316. * @vdev: virtual device handle
  317. * @msdu: network buffer
  318. * @msdu_info: meta data associated with the msdu
  319. *
  320. * Return: QDF_STATUS_SUCCESS success
  321. */
  322. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  323. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  324. {
  325. struct qdf_tso_seg_elem_t *tso_seg;
  326. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  327. struct dp_soc *soc = vdev->pdev->soc;
  328. struct qdf_tso_info_t *tso_info;
  329. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  330. tso_info = &msdu_info->u.tso_info;
  331. tso_info->curr_seg = NULL;
  332. tso_info->tso_seg_list = NULL;
  333. tso_info->num_segs = num_seg;
  334. msdu_info->frm_type = dp_tx_frm_tso;
  335. tso_info->tso_num_seg_list = NULL;
  336. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  337. while (num_seg) {
  338. tso_seg = dp_tx_tso_desc_alloc(
  339. soc, msdu_info->tx_queue.desc_pool_id);
  340. if (tso_seg) {
  341. tso_seg->next = tso_info->tso_seg_list;
  342. tso_info->tso_seg_list = tso_seg;
  343. num_seg--;
  344. } else {
  345. struct qdf_tso_seg_elem_t *free_seg =
  346. tso_info->tso_seg_list;
  347. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  348. return QDF_STATUS_E_NOMEM;
  349. }
  350. }
  351. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  352. tso_num_seg = dp_tso_num_seg_alloc(soc,
  353. msdu_info->tx_queue.desc_pool_id);
  354. if (tso_num_seg) {
  355. tso_num_seg->next = tso_info->tso_num_seg_list;
  356. tso_info->tso_num_seg_list = tso_num_seg;
  357. } else {
  358. /* Bug: free tso_num_seg and tso_seg */
  359. /* Free the already allocated num of segments */
  360. struct qdf_tso_seg_elem_t *free_seg =
  361. tso_info->tso_seg_list;
  362. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  363. __func__);
  364. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  365. return QDF_STATUS_E_NOMEM;
  366. }
  367. msdu_info->num_seg =
  368. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  369. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  370. msdu_info->num_seg);
  371. if (!(msdu_info->num_seg)) {
  372. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  373. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  374. msdu_info);
  375. return QDF_STATUS_E_INVAL;
  376. }
  377. tso_info->curr_seg = tso_info->tso_seg_list;
  378. return QDF_STATUS_SUCCESS;
  379. }
  380. #else
  381. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  382. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  383. {
  384. return QDF_STATUS_E_NOMEM;
  385. }
  386. #endif
  387. /**
  388. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  389. * @vdev: DP Vdev handle
  390. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  391. * @desc_pool_id: Descriptor Pool ID
  392. *
  393. * Return:
  394. */
  395. static
  396. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  397. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  398. {
  399. uint8_t i;
  400. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  401. struct dp_tx_seg_info_s *seg_info;
  402. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  403. struct dp_soc *soc = vdev->pdev->soc;
  404. /* Allocate an extension descriptor */
  405. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  406. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  407. if (!msdu_ext_desc) {
  408. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  409. return NULL;
  410. }
  411. if (msdu_info->exception_fw &&
  412. qdf_unlikely(vdev->mesh_vdev)) {
  413. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  414. &msdu_info->meta_data[0],
  415. sizeof(struct htt_tx_msdu_desc_ext2_t));
  416. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  417. }
  418. switch (msdu_info->frm_type) {
  419. case dp_tx_frm_sg:
  420. case dp_tx_frm_me:
  421. case dp_tx_frm_raw:
  422. seg_info = msdu_info->u.sg_info.curr_seg;
  423. /* Update the buffer pointers in MSDU Extension Descriptor */
  424. for (i = 0; i < seg_info->frag_cnt; i++) {
  425. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  426. seg_info->frags[i].paddr_lo,
  427. seg_info->frags[i].paddr_hi,
  428. seg_info->frags[i].len);
  429. }
  430. break;
  431. case dp_tx_frm_tso:
  432. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  433. &cached_ext_desc[0]);
  434. break;
  435. default:
  436. break;
  437. }
  438. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  439. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  440. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  441. msdu_ext_desc->vaddr);
  442. return msdu_ext_desc;
  443. }
  444. /**
  445. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  446. * @vdev: DP vdev handle
  447. * @nbuf: skb
  448. * @desc_pool_id: Descriptor pool ID
  449. * @meta_data: Metadata to the fw
  450. * @tx_exc_metadata: Handle that holds exception path metadata
  451. * Allocate and prepare Tx descriptor with msdu information.
  452. *
  453. * Return: Pointer to Tx Descriptor on success,
  454. * NULL on failure
  455. */
  456. static
  457. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  458. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  459. struct dp_tx_msdu_info_s *msdu_info,
  460. struct cdp_tx_exception_metadata *tx_exc_metadata)
  461. {
  462. uint8_t align_pad;
  463. uint8_t is_exception = 0;
  464. uint8_t htt_hdr_size;
  465. struct ether_header *eh;
  466. struct dp_tx_desc_s *tx_desc;
  467. struct dp_pdev *pdev = vdev->pdev;
  468. struct dp_soc *soc = pdev->soc;
  469. /* Allocate software Tx descriptor */
  470. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  471. if (qdf_unlikely(!tx_desc)) {
  472. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  473. return NULL;
  474. }
  475. /* Flow control/Congestion Control counters */
  476. qdf_atomic_inc(&pdev->num_tx_outstanding);
  477. /* Initialize the SW tx descriptor */
  478. tx_desc->nbuf = nbuf;
  479. tx_desc->frm_type = dp_tx_frm_std;
  480. tx_desc->tx_encap_type = (tx_exc_metadata ?
  481. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  482. tx_desc->vdev = vdev;
  483. tx_desc->pdev = pdev;
  484. tx_desc->msdu_ext_desc = NULL;
  485. tx_desc->pkt_offset = 0;
  486. /*
  487. * For special modes (vdev_type == ocb or mesh), data frames should be
  488. * transmitted using varying transmit parameters (tx spec) which include
  489. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  490. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  491. * These frames are sent as exception packets to firmware.
  492. *
  493. * HW requirement is that metadata should always point to a
  494. * 8-byte aligned address. So we add alignment pad to start of buffer.
  495. * HTT Metadata should be ensured to be multiple of 8-bytes,
  496. * to get 8-byte aligned start address along with align_pad added
  497. *
  498. * |-----------------------------|
  499. * | |
  500. * |-----------------------------| <-----Buffer Pointer Address given
  501. * | | ^ in HW descriptor (aligned)
  502. * | HTT Metadata | |
  503. * | | |
  504. * | | | Packet Offset given in descriptor
  505. * | | |
  506. * |-----------------------------| |
  507. * | Alignment Pad | v
  508. * |-----------------------------| <----- Actual buffer start address
  509. * | SKB Data | (Unaligned)
  510. * | |
  511. * | |
  512. * | |
  513. * | |
  514. * | |
  515. * |-----------------------------|
  516. */
  517. if (qdf_unlikely((msdu_info->exception_fw)) ||
  518. (vdev->opmode == wlan_op_mode_ocb)) {
  519. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  520. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  521. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  522. "qdf_nbuf_push_head failed\n");
  523. goto failure;
  524. }
  525. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  526. msdu_info->meta_data);
  527. if (htt_hdr_size == 0)
  528. goto failure;
  529. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  530. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  531. is_exception = 1;
  532. }
  533. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  534. qdf_nbuf_map(soc->osdev, nbuf,
  535. QDF_DMA_TO_DEVICE))) {
  536. /* Handle failure */
  537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  538. "qdf_nbuf_map failed\n");
  539. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  540. goto failure;
  541. }
  542. if (qdf_unlikely(vdev->nawds_enabled)) {
  543. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  544. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  545. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  546. is_exception = 1;
  547. }
  548. }
  549. #if !TQM_BYPASS_WAR
  550. if (is_exception || tx_exc_metadata)
  551. #endif
  552. {
  553. /* Temporary WAR due to TQM VP issues */
  554. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  555. qdf_atomic_inc(&pdev->num_tx_exception);
  556. }
  557. return tx_desc;
  558. failure:
  559. dp_tx_desc_release(tx_desc, desc_pool_id);
  560. return NULL;
  561. }
  562. /**
  563. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  564. * @vdev: DP vdev handle
  565. * @nbuf: skb
  566. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  567. * @desc_pool_id : Descriptor Pool ID
  568. *
  569. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  570. * information. For frames wth fragments, allocate and prepare
  571. * an MSDU extension descriptor
  572. *
  573. * Return: Pointer to Tx Descriptor on success,
  574. * NULL on failure
  575. */
  576. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  577. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  578. uint8_t desc_pool_id)
  579. {
  580. struct dp_tx_desc_s *tx_desc;
  581. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  582. struct dp_pdev *pdev = vdev->pdev;
  583. struct dp_soc *soc = pdev->soc;
  584. /* Allocate software Tx descriptor */
  585. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  586. if (!tx_desc) {
  587. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  588. return NULL;
  589. }
  590. /* Flow control/Congestion Control counters */
  591. qdf_atomic_inc(&pdev->num_tx_outstanding);
  592. /* Initialize the SW tx descriptor */
  593. tx_desc->nbuf = nbuf;
  594. tx_desc->frm_type = msdu_info->frm_type;
  595. tx_desc->tx_encap_type = vdev->tx_encap_type;
  596. tx_desc->vdev = vdev;
  597. tx_desc->pdev = pdev;
  598. tx_desc->pkt_offset = 0;
  599. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  600. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  601. /* Handle scattered frames - TSO/SG/ME */
  602. /* Allocate and prepare an extension descriptor for scattered frames */
  603. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  604. if (!msdu_ext_desc) {
  605. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  606. "%s Tx Extension Descriptor Alloc Fail\n",
  607. __func__);
  608. goto failure;
  609. }
  610. #if TQM_BYPASS_WAR
  611. /* Temporary WAR due to TQM VP issues */
  612. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  613. qdf_atomic_inc(&pdev->num_tx_exception);
  614. #endif
  615. if (qdf_unlikely(msdu_info->exception_fw))
  616. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  617. tx_desc->msdu_ext_desc = msdu_ext_desc;
  618. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  619. return tx_desc;
  620. failure:
  621. dp_tx_desc_release(tx_desc, desc_pool_id);
  622. return NULL;
  623. }
  624. /**
  625. * dp_tx_prepare_raw() - Prepare RAW packet TX
  626. * @vdev: DP vdev handle
  627. * @nbuf: buffer pointer
  628. * @seg_info: Pointer to Segment info Descriptor to be prepared
  629. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  630. * descriptor
  631. *
  632. * Return:
  633. */
  634. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  635. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  636. {
  637. qdf_nbuf_t curr_nbuf = NULL;
  638. uint16_t total_len = 0;
  639. qdf_dma_addr_t paddr;
  640. int32_t i;
  641. int32_t mapped_buf_num = 0;
  642. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  643. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  644. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  645. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  646. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  647. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  648. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  649. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  650. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  651. QDF_DMA_TO_DEVICE)) {
  652. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  653. "%s dma map error \n", __func__);
  654. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  655. mapped_buf_num = i;
  656. goto error;
  657. }
  658. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  659. seg_info->frags[i].paddr_lo = paddr;
  660. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  661. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  662. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  663. total_len += qdf_nbuf_len(curr_nbuf);
  664. }
  665. seg_info->frag_cnt = i;
  666. seg_info->total_len = total_len;
  667. seg_info->next = NULL;
  668. sg_info->curr_seg = seg_info;
  669. msdu_info->frm_type = dp_tx_frm_raw;
  670. msdu_info->num_seg = 1;
  671. return nbuf;
  672. error:
  673. i = 0;
  674. while (nbuf) {
  675. curr_nbuf = nbuf;
  676. if (i < mapped_buf_num) {
  677. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  678. i++;
  679. }
  680. nbuf = qdf_nbuf_next(nbuf);
  681. qdf_nbuf_free(curr_nbuf);
  682. }
  683. return NULL;
  684. }
  685. /**
  686. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  687. * @soc: DP Soc Handle
  688. * @vdev: DP vdev handle
  689. * @tx_desc: Tx Descriptor Handle
  690. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  691. * @fw_metadata: Metadata to send to Target Firmware along with frame
  692. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  693. * @tx_exc_metadata: Handle that holds exception path meta data
  694. *
  695. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  696. * from software Tx descriptor
  697. *
  698. * Return:
  699. */
  700. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  701. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  702. uint16_t fw_metadata, uint8_t ring_id,
  703. struct cdp_tx_exception_metadata
  704. *tx_exc_metadata)
  705. {
  706. uint8_t type;
  707. uint16_t length;
  708. void *hal_tx_desc, *hal_tx_desc_cached;
  709. qdf_dma_addr_t dma_addr;
  710. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  711. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  712. tx_exc_metadata->sec_type : vdev->sec_type);
  713. /* Return Buffer Manager ID */
  714. uint8_t bm_id = ring_id;
  715. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  716. hal_tx_desc_cached = (void *) cached_desc;
  717. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  718. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  719. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  720. type = HAL_TX_BUF_TYPE_EXT_DESC;
  721. dma_addr = tx_desc->msdu_ext_desc->paddr;
  722. } else {
  723. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  724. type = HAL_TX_BUF_TYPE_BUFFER;
  725. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  726. }
  727. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  728. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  729. dma_addr , bm_id, tx_desc->id, type);
  730. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  731. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  732. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  733. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  734. HAL_TX_DESC_DEFAULT_LMAC_ID);
  735. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  736. vdev->dscp_tid_map_id);
  737. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  738. sec_type_map[sec_type]);
  739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  740. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  741. __func__, length, type, (uint64_t)dma_addr,
  742. tx_desc->pkt_offset, tx_desc->id);
  743. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  744. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  745. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  746. vdev->hal_desc_addr_search_flags);
  747. /* verify checksum offload configuration*/
  748. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  749. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  750. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  751. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  752. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  753. }
  754. if (tid != HTT_TX_EXT_TID_INVALID)
  755. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  756. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  757. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  758. /* Sync cached descriptor with HW */
  759. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  760. if (!hal_tx_desc) {
  761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  762. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  763. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  764. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  765. return QDF_STATUS_E_RESOURCES;
  766. }
  767. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  768. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  769. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  770. /*
  771. * If one packet is enqueued in HW, PM usage count needs to be
  772. * incremented by one to prevent future runtime suspend. This
  773. * should be tied with the success of enqueuing. It will be
  774. * decremented after the packet has been sent.
  775. */
  776. hif_pm_runtime_get_noresume(soc->hif_handle);
  777. return QDF_STATUS_SUCCESS;
  778. }
  779. /**
  780. * dp_cce_classify() - Classify the frame based on CCE rules
  781. * @vdev: DP vdev handle
  782. * @nbuf: skb
  783. *
  784. * Classify frames based on CCE rules
  785. * Return: bool( true if classified,
  786. * else false)
  787. */
  788. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  789. {
  790. struct ether_header *eh = NULL;
  791. uint16_t ether_type;
  792. qdf_llc_t *llcHdr;
  793. qdf_nbuf_t nbuf_clone = NULL;
  794. qdf_dot3_qosframe_t *qos_wh = NULL;
  795. /* for mesh packets don't do any classification */
  796. if (qdf_unlikely(vdev->mesh_vdev))
  797. return false;
  798. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  799. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  800. ether_type = eh->ether_type;
  801. llcHdr = (qdf_llc_t *)(nbuf->data +
  802. sizeof(struct ether_header));
  803. } else {
  804. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  805. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  806. if (qdf_unlikely(
  807. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  808. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  809. ether_type = *(uint16_t *)(nbuf->data
  810. + QDF_IEEE80211_4ADDR_HDR_LEN
  811. + sizeof(qdf_llc_t)
  812. - sizeof(ether_type));
  813. llcHdr = (qdf_llc_t *)(nbuf->data +
  814. QDF_IEEE80211_4ADDR_HDR_LEN);
  815. } else {
  816. ether_type = *(uint16_t *)(nbuf->data
  817. + QDF_IEEE80211_3ADDR_HDR_LEN
  818. + sizeof(qdf_llc_t)
  819. - sizeof(ether_type));
  820. llcHdr = (qdf_llc_t *)(nbuf->data +
  821. QDF_IEEE80211_3ADDR_HDR_LEN);
  822. }
  823. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  824. && (ether_type ==
  825. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  826. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  827. return true;
  828. }
  829. }
  830. return false;
  831. }
  832. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  833. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  834. sizeof(*llcHdr));
  835. nbuf_clone = qdf_nbuf_clone(nbuf);
  836. if (qdf_unlikely(nbuf_clone)) {
  837. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  838. if (ether_type == htons(ETHERTYPE_8021Q)) {
  839. qdf_nbuf_pull_head(nbuf_clone,
  840. sizeof(qdf_net_vlanhdr_t));
  841. }
  842. }
  843. } else {
  844. if (ether_type == htons(ETHERTYPE_8021Q)) {
  845. nbuf_clone = qdf_nbuf_clone(nbuf);
  846. if (qdf_unlikely(nbuf_clone)) {
  847. qdf_nbuf_pull_head(nbuf_clone,
  848. sizeof(qdf_net_vlanhdr_t));
  849. }
  850. }
  851. }
  852. if (qdf_unlikely(nbuf_clone))
  853. nbuf = nbuf_clone;
  854. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  855. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  856. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  857. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  858. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  859. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  860. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  861. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  862. if (qdf_unlikely(nbuf_clone != NULL))
  863. qdf_nbuf_free(nbuf_clone);
  864. return true;
  865. }
  866. if (qdf_unlikely(nbuf_clone != NULL))
  867. qdf_nbuf_free(nbuf_clone);
  868. return false;
  869. }
  870. /**
  871. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  872. * @vdev: DP vdev handle
  873. * @nbuf: skb
  874. *
  875. * Extract the DSCP or PCP information from frame and map into TID value.
  876. * Software based TID classification is required when more than 2 DSCP-TID
  877. * mapping tables are needed.
  878. * Hardware supports 2 DSCP-TID mapping tables
  879. *
  880. * Return: void
  881. */
  882. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  883. struct dp_tx_msdu_info_s *msdu_info)
  884. {
  885. uint8_t tos = 0, dscp_tid_override = 0;
  886. uint8_t *hdr_ptr, *L3datap;
  887. uint8_t is_mcast = 0;
  888. struct ether_header *eh = NULL;
  889. qdf_ethervlan_header_t *evh = NULL;
  890. uint16_t ether_type;
  891. qdf_llc_t *llcHdr;
  892. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  893. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  894. if (vdev->dscp_tid_map_id <= 1)
  895. return;
  896. /* for mesh packets don't do any classification */
  897. if (qdf_unlikely(vdev->mesh_vdev))
  898. return;
  899. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  900. eh = (struct ether_header *) nbuf->data;
  901. hdr_ptr = eh->ether_dhost;
  902. L3datap = hdr_ptr + sizeof(struct ether_header);
  903. } else {
  904. qdf_dot3_qosframe_t *qos_wh =
  905. (qdf_dot3_qosframe_t *) nbuf->data;
  906. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  907. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  908. return;
  909. }
  910. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  911. ether_type = eh->ether_type;
  912. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  913. /*
  914. * Check if packet is dot3 or eth2 type.
  915. */
  916. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  917. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  918. sizeof(*llcHdr));
  919. if (ether_type == htons(ETHERTYPE_8021Q)) {
  920. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  921. sizeof(*llcHdr);
  922. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  923. + sizeof(*llcHdr) +
  924. sizeof(qdf_net_vlanhdr_t));
  925. } else {
  926. L3datap = hdr_ptr + sizeof(struct ether_header) +
  927. sizeof(*llcHdr);
  928. }
  929. } else {
  930. if (ether_type == htons(ETHERTYPE_8021Q)) {
  931. evh = (qdf_ethervlan_header_t *) eh;
  932. ether_type = evh->ether_type;
  933. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  934. }
  935. }
  936. /*
  937. * Find priority from IP TOS DSCP field
  938. */
  939. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  940. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  941. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  942. /* Only for unicast frames */
  943. if (!is_mcast) {
  944. /* send it on VO queue */
  945. msdu_info->tid = DP_VO_TID;
  946. }
  947. } else {
  948. /*
  949. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  950. * from TOS byte.
  951. */
  952. tos = ip->ip_tos;
  953. dscp_tid_override = 1;
  954. }
  955. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  956. /* TODO
  957. * use flowlabel
  958. *igmpmld cases to be handled in phase 2
  959. */
  960. unsigned long ver_pri_flowlabel;
  961. unsigned long pri;
  962. ver_pri_flowlabel = *(unsigned long *) L3datap;
  963. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  964. DP_IPV6_PRIORITY_SHIFT;
  965. tos = pri;
  966. dscp_tid_override = 1;
  967. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  968. msdu_info->tid = DP_VO_TID;
  969. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  970. /* Only for unicast frames */
  971. if (!is_mcast) {
  972. /* send ucast arp on VO queue */
  973. msdu_info->tid = DP_VO_TID;
  974. }
  975. }
  976. /*
  977. * Assign all MCAST packets to BE
  978. */
  979. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  980. if (is_mcast) {
  981. tos = 0;
  982. dscp_tid_override = 1;
  983. }
  984. }
  985. if (dscp_tid_override == 1) {
  986. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  987. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  988. }
  989. return;
  990. }
  991. #ifdef CONVERGED_TDLS_ENABLE
  992. /**
  993. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  994. * @tx_desc: TX descriptor
  995. *
  996. * Return: None
  997. */
  998. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  999. {
  1000. if (tx_desc->vdev) {
  1001. if (tx_desc->vdev->is_tdls_frame)
  1002. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1003. tx_desc->vdev->is_tdls_frame = false;
  1004. }
  1005. }
  1006. /**
  1007. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1008. * @tx_desc: TX descriptor
  1009. * @vdev: datapath vdev handle
  1010. *
  1011. * Return: None
  1012. */
  1013. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1014. struct dp_vdev *vdev)
  1015. {
  1016. struct hal_tx_completion_status ts = {0};
  1017. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1018. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1019. if (vdev->tx_non_std_data_callback.func) {
  1020. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1021. vdev->tx_non_std_data_callback.func(
  1022. vdev->tx_non_std_data_callback.ctxt,
  1023. nbuf, ts.status);
  1024. return;
  1025. }
  1026. }
  1027. #endif
  1028. /**
  1029. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1030. * @vdev: DP vdev handle
  1031. * @nbuf: skb
  1032. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1033. * @meta_data: Metadata to the fw
  1034. * @tx_q: Tx queue to be used for this Tx frame
  1035. * @peer_id: peer_id of the peer in case of NAWDS frames
  1036. * @tx_exc_metadata: Handle that holds exception path metadata
  1037. *
  1038. * Return: NULL on success,
  1039. * nbuf when it fails to send
  1040. */
  1041. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1042. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1043. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1044. {
  1045. struct dp_pdev *pdev = vdev->pdev;
  1046. struct dp_soc *soc = pdev->soc;
  1047. struct dp_tx_desc_s *tx_desc;
  1048. QDF_STATUS status;
  1049. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1050. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1051. uint16_t htt_tcl_metadata = 0;
  1052. uint8_t tid = msdu_info->tid;
  1053. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1054. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1055. msdu_info, tx_exc_metadata);
  1056. if (!tx_desc) {
  1057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1058. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1059. __func__, vdev, tx_q->desc_pool_id);
  1060. return nbuf;
  1061. }
  1062. if (qdf_unlikely(soc->cce_disable)) {
  1063. if (dp_cce_classify(vdev, nbuf) == true) {
  1064. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1065. tid = DP_VO_TID;
  1066. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1067. }
  1068. }
  1069. dp_tx_update_tdls_flags(tx_desc);
  1070. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1071. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1072. "%s %d : HAL RING Access Failed -- %pK\n",
  1073. __func__, __LINE__, hal_srng);
  1074. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1075. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1076. goto fail_return;
  1077. }
  1078. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1079. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1080. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1081. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1082. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1083. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1084. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1085. peer_id);
  1086. } else
  1087. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1088. if (msdu_info->exception_fw) {
  1089. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1090. }
  1091. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1092. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1093. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1094. if (status != QDF_STATUS_SUCCESS) {
  1095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1096. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1097. __func__, tx_desc, tx_q->ring_id);
  1098. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1099. goto fail_return;
  1100. }
  1101. nbuf = NULL;
  1102. fail_return:
  1103. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1104. hal_srng_access_end(soc->hal_soc, hal_srng);
  1105. hif_pm_runtime_put(soc->hif_handle);
  1106. } else {
  1107. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1108. }
  1109. return nbuf;
  1110. }
  1111. /**
  1112. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1113. * @vdev: DP vdev handle
  1114. * @nbuf: skb
  1115. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1116. *
  1117. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1118. *
  1119. * Return: NULL on success,
  1120. * nbuf when it fails to send
  1121. */
  1122. #if QDF_LOCK_STATS
  1123. static noinline
  1124. #else
  1125. static
  1126. #endif
  1127. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1128. struct dp_tx_msdu_info_s *msdu_info)
  1129. {
  1130. uint8_t i;
  1131. struct dp_pdev *pdev = vdev->pdev;
  1132. struct dp_soc *soc = pdev->soc;
  1133. struct dp_tx_desc_s *tx_desc;
  1134. bool is_cce_classified = false;
  1135. QDF_STATUS status;
  1136. uint16_t htt_tcl_metadata = 0;
  1137. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1138. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1139. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1140. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1141. "%s %d : HAL RING Access Failed -- %pK\n",
  1142. __func__, __LINE__, hal_srng);
  1143. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1144. return nbuf;
  1145. }
  1146. if (qdf_unlikely(soc->cce_disable)) {
  1147. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1148. if (is_cce_classified) {
  1149. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1150. msdu_info->tid = DP_VO_TID;
  1151. }
  1152. }
  1153. if (msdu_info->frm_type == dp_tx_frm_me)
  1154. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1155. i = 0;
  1156. /* Print statement to track i and num_seg */
  1157. /*
  1158. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1159. * descriptors using information in msdu_info
  1160. */
  1161. while (i < msdu_info->num_seg) {
  1162. /*
  1163. * Setup Tx descriptor for an MSDU, and MSDU extension
  1164. * descriptor
  1165. */
  1166. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1167. tx_q->desc_pool_id);
  1168. if (!tx_desc) {
  1169. if (msdu_info->frm_type == dp_tx_frm_me) {
  1170. dp_tx_me_free_buf(pdev,
  1171. (void *)(msdu_info->u.sg_info
  1172. .curr_seg->frags[0].vaddr));
  1173. }
  1174. goto done;
  1175. }
  1176. if (msdu_info->frm_type == dp_tx_frm_me) {
  1177. tx_desc->me_buffer =
  1178. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1179. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1180. }
  1181. if (is_cce_classified)
  1182. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1183. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1184. if (msdu_info->exception_fw) {
  1185. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1186. }
  1187. /*
  1188. * Enqueue the Tx MSDU descriptor to HW for transmit
  1189. */
  1190. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1191. htt_tcl_metadata, tx_q->ring_id, NULL);
  1192. if (status != QDF_STATUS_SUCCESS) {
  1193. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1194. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1195. __func__, tx_desc, tx_q->ring_id);
  1196. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1197. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1198. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1199. goto done;
  1200. }
  1201. /*
  1202. * TODO
  1203. * if tso_info structure can be modified to have curr_seg
  1204. * as first element, following 2 blocks of code (for TSO and SG)
  1205. * can be combined into 1
  1206. */
  1207. /*
  1208. * For frames with multiple segments (TSO, ME), jump to next
  1209. * segment.
  1210. */
  1211. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1212. if (msdu_info->u.tso_info.curr_seg->next) {
  1213. msdu_info->u.tso_info.curr_seg =
  1214. msdu_info->u.tso_info.curr_seg->next;
  1215. /*
  1216. * If this is a jumbo nbuf, then increment the number of
  1217. * nbuf users for each additional segment of the msdu.
  1218. * This will ensure that the skb is freed only after
  1219. * receiving tx completion for all segments of an nbuf
  1220. */
  1221. qdf_nbuf_inc_users(nbuf);
  1222. /* Check with MCL if this is needed */
  1223. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1224. }
  1225. }
  1226. /*
  1227. * For Multicast-Unicast converted packets,
  1228. * each converted frame (for a client) is represented as
  1229. * 1 segment
  1230. */
  1231. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1232. (msdu_info->frm_type == dp_tx_frm_me)) {
  1233. if (msdu_info->u.sg_info.curr_seg->next) {
  1234. msdu_info->u.sg_info.curr_seg =
  1235. msdu_info->u.sg_info.curr_seg->next;
  1236. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1237. }
  1238. }
  1239. i++;
  1240. }
  1241. nbuf = NULL;
  1242. done:
  1243. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1244. hal_srng_access_end(soc->hal_soc, hal_srng);
  1245. hif_pm_runtime_put(soc->hif_handle);
  1246. } else {
  1247. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1248. }
  1249. return nbuf;
  1250. }
  1251. /**
  1252. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1253. * for SG frames
  1254. * @vdev: DP vdev handle
  1255. * @nbuf: skb
  1256. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1257. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1258. *
  1259. * Return: NULL on success,
  1260. * nbuf when it fails to send
  1261. */
  1262. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1263. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1264. {
  1265. uint32_t cur_frag, nr_frags;
  1266. qdf_dma_addr_t paddr;
  1267. struct dp_tx_sg_info_s *sg_info;
  1268. sg_info = &msdu_info->u.sg_info;
  1269. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1270. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1271. QDF_DMA_TO_DEVICE)) {
  1272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1273. "dma map error\n");
  1274. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1275. qdf_nbuf_free(nbuf);
  1276. return NULL;
  1277. }
  1278. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1279. seg_info->frags[0].paddr_lo = paddr;
  1280. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1281. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1282. seg_info->frags[0].vaddr = (void *) nbuf;
  1283. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1284. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1285. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1286. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1287. "frag dma map error\n");
  1288. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1289. qdf_nbuf_free(nbuf);
  1290. return NULL;
  1291. }
  1292. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1293. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1294. seg_info->frags[cur_frag + 1].paddr_hi =
  1295. ((uint64_t) paddr) >> 32;
  1296. seg_info->frags[cur_frag + 1].len =
  1297. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1298. }
  1299. seg_info->frag_cnt = (cur_frag + 1);
  1300. seg_info->total_len = qdf_nbuf_len(nbuf);
  1301. seg_info->next = NULL;
  1302. sg_info->curr_seg = seg_info;
  1303. msdu_info->frm_type = dp_tx_frm_sg;
  1304. msdu_info->num_seg = 1;
  1305. return nbuf;
  1306. }
  1307. #ifdef MESH_MODE_SUPPORT
  1308. /**
  1309. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1310. and prepare msdu_info for mesh frames.
  1311. * @vdev: DP vdev handle
  1312. * @nbuf: skb
  1313. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1314. *
  1315. * Return: NULL on failure,
  1316. * nbuf when extracted successfully
  1317. */
  1318. static
  1319. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1320. struct dp_tx_msdu_info_s *msdu_info)
  1321. {
  1322. struct meta_hdr_s *mhdr;
  1323. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1324. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1325. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1326. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1327. msdu_info->exception_fw = 0;
  1328. goto remove_meta_hdr;
  1329. }
  1330. msdu_info->exception_fw = 1;
  1331. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1332. meta_data->host_tx_desc_pool = 1;
  1333. meta_data->update_peer_cache = 1;
  1334. meta_data->learning_frame = 1;
  1335. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1336. meta_data->power = mhdr->power;
  1337. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1338. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1339. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1340. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1341. meta_data->dyn_bw = 1;
  1342. meta_data->valid_pwr = 1;
  1343. meta_data->valid_mcs_mask = 1;
  1344. meta_data->valid_nss_mask = 1;
  1345. meta_data->valid_preamble_type = 1;
  1346. meta_data->valid_retries = 1;
  1347. meta_data->valid_bw_info = 1;
  1348. }
  1349. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1350. meta_data->encrypt_type = 0;
  1351. meta_data->valid_encrypt_type = 1;
  1352. meta_data->learning_frame = 0;
  1353. }
  1354. meta_data->valid_key_flags = 1;
  1355. meta_data->key_flags = (mhdr->keyix & 0x3);
  1356. remove_meta_hdr:
  1357. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1358. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1359. "qdf_nbuf_pull_head failed\n");
  1360. qdf_nbuf_free(nbuf);
  1361. return NULL;
  1362. }
  1363. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1364. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1365. else
  1366. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1367. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1368. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1369. " tid %d to_fw %d\n",
  1370. __func__, msdu_info->meta_data[0],
  1371. msdu_info->meta_data[1],
  1372. msdu_info->meta_data[2],
  1373. msdu_info->meta_data[3],
  1374. msdu_info->meta_data[4],
  1375. msdu_info->meta_data[5],
  1376. msdu_info->tid, msdu_info->exception_fw);
  1377. return nbuf;
  1378. }
  1379. #else
  1380. static
  1381. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1382. struct dp_tx_msdu_info_s *msdu_info)
  1383. {
  1384. return nbuf;
  1385. }
  1386. #endif
  1387. #ifdef DP_FEATURE_NAWDS_TX
  1388. /**
  1389. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1390. * @vdev: dp_vdev handle
  1391. * @nbuf: skb
  1392. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1393. * @tx_q: Tx queue to be used for this Tx frame
  1394. * @meta_data: Meta date for mesh
  1395. * @peer_id: peer_id of the peer in case of NAWDS frames
  1396. *
  1397. * return: NULL on success nbuf on failure
  1398. */
  1399. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1400. struct dp_tx_msdu_info_s *msdu_info)
  1401. {
  1402. struct dp_peer *peer = NULL;
  1403. struct dp_soc *soc = vdev->pdev->soc;
  1404. struct dp_ast_entry *ast_entry = NULL;
  1405. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1406. uint16_t peer_id = HTT_INVALID_PEER;
  1407. struct dp_peer *sa_peer = NULL;
  1408. qdf_nbuf_t nbuf_copy;
  1409. qdf_spin_lock_bh(&(soc->ast_lock));
  1410. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1411. if (ast_entry)
  1412. sa_peer = ast_entry->peer;
  1413. qdf_spin_unlock_bh(&(soc->ast_lock));
  1414. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1415. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1416. (peer->nawds_enabled)) {
  1417. if (sa_peer == peer) {
  1418. QDF_TRACE(QDF_MODULE_ID_DP,
  1419. QDF_TRACE_LEVEL_DEBUG,
  1420. " %s: broadcast multicast packet",
  1421. __func__);
  1422. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1423. continue;
  1424. }
  1425. nbuf_copy = qdf_nbuf_copy(nbuf);
  1426. if (!nbuf_copy) {
  1427. QDF_TRACE(QDF_MODULE_ID_DP,
  1428. QDF_TRACE_LEVEL_ERROR,
  1429. "nbuf copy failed");
  1430. }
  1431. peer_id = peer->peer_ids[0];
  1432. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1433. msdu_info, peer_id, NULL);
  1434. if (nbuf_copy != NULL) {
  1435. qdf_nbuf_free(nbuf_copy);
  1436. continue;
  1437. }
  1438. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1439. 1, qdf_nbuf_len(nbuf));
  1440. }
  1441. }
  1442. if (peer_id == HTT_INVALID_PEER)
  1443. return nbuf;
  1444. return NULL;
  1445. }
  1446. #endif
  1447. /**
  1448. * dp_check_exc_metadata() - Checks if parameters are valid
  1449. * @tx_exc - holds all exception path parameters
  1450. *
  1451. * Returns true when all the parameters are valid else false
  1452. *
  1453. */
  1454. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1455. {
  1456. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1457. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1458. tx_exc->sec_type > cdp_num_sec_types) {
  1459. return false;
  1460. }
  1461. return true;
  1462. }
  1463. /**
  1464. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1465. * @vap_dev: DP vdev handle
  1466. * @nbuf: skb
  1467. * @tx_exc_metadata: Handle that holds exception path meta data
  1468. *
  1469. * Entry point for Core Tx layer (DP_TX) invoked from
  1470. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1471. *
  1472. * Return: NULL on success,
  1473. * nbuf when it fails to send
  1474. */
  1475. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1476. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1477. {
  1478. struct ether_header *eh = NULL;
  1479. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1480. struct dp_tx_msdu_info_s msdu_info;
  1481. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1482. msdu_info.tid = tx_exc_metadata->tid;
  1483. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1485. "%s , skb %pM",
  1486. __func__, nbuf->data);
  1487. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1488. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1489. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1490. "Invalid parameters in exception path");
  1491. goto fail;
  1492. }
  1493. /* Basic sanity checks for unsupported packets */
  1494. /* MESH mode */
  1495. if (qdf_unlikely(vdev->mesh_vdev)) {
  1496. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1497. "Mesh mode is not supported in exception path");
  1498. goto fail;
  1499. }
  1500. /* TSO or SG */
  1501. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1502. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1503. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1504. "TSO and SG are not supported in exception path");
  1505. goto fail;
  1506. }
  1507. /* RAW */
  1508. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1509. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1510. "Raw frame is not supported in exception path");
  1511. goto fail;
  1512. }
  1513. /* Mcast enhancement*/
  1514. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1515. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1516. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1517. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1518. }
  1519. }
  1520. /*
  1521. * Get HW Queue to use for this frame.
  1522. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1523. * dedicated for data and 1 for command.
  1524. * "queue_id" maps to one hardware ring.
  1525. * With each ring, we also associate a unique Tx descriptor pool
  1526. * to minimize lock contention for these resources.
  1527. */
  1528. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1529. /* Reset the control block */
  1530. qdf_nbuf_reset_ctxt(nbuf);
  1531. /* Single linear frame */
  1532. /*
  1533. * If nbuf is a simple linear frame, use send_single function to
  1534. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1535. * SRNG. There is no need to setup a MSDU extension descriptor.
  1536. */
  1537. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1538. tx_exc_metadata->peer_id, tx_exc_metadata);
  1539. return nbuf;
  1540. fail:
  1541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1542. "pkt send failed");
  1543. return nbuf;
  1544. }
  1545. /**
  1546. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1547. * @vap_dev: DP vdev handle
  1548. * @nbuf: skb
  1549. *
  1550. * Entry point for Core Tx layer (DP_TX) invoked from
  1551. * hard_start_xmit in OSIF/HDD
  1552. *
  1553. * Return: NULL on success,
  1554. * nbuf when it fails to send
  1555. */
  1556. #ifdef MESH_MODE_SUPPORT
  1557. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1558. {
  1559. struct meta_hdr_s *mhdr;
  1560. qdf_nbuf_t nbuf_mesh = NULL;
  1561. qdf_nbuf_t nbuf_clone = NULL;
  1562. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1563. uint8_t no_enc_frame = 0;
  1564. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1565. if (nbuf_mesh == NULL) {
  1566. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1567. "qdf_nbuf_unshare failed\n");
  1568. return nbuf;
  1569. }
  1570. nbuf = nbuf_mesh;
  1571. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1572. if ((vdev->sec_type != cdp_sec_type_none) &&
  1573. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1574. no_enc_frame = 1;
  1575. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1576. !no_enc_frame) {
  1577. nbuf_clone = qdf_nbuf_clone(nbuf);
  1578. if (nbuf_clone == NULL) {
  1579. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1580. "qdf_nbuf_clone failed\n");
  1581. return nbuf;
  1582. }
  1583. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1584. }
  1585. if (nbuf_clone) {
  1586. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1587. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1588. } else
  1589. qdf_nbuf_free(nbuf_clone);
  1590. }
  1591. if (no_enc_frame)
  1592. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1593. else
  1594. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1595. nbuf = dp_tx_send(vap_dev, nbuf);
  1596. if ((nbuf == NULL) && no_enc_frame) {
  1597. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1598. }
  1599. return nbuf;
  1600. }
  1601. #else
  1602. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1603. {
  1604. return dp_tx_send(vap_dev, nbuf);
  1605. }
  1606. #endif
  1607. /**
  1608. * dp_tx_send() - Transmit a frame on a given VAP
  1609. * @vap_dev: DP vdev handle
  1610. * @nbuf: skb
  1611. *
  1612. * Entry point for Core Tx layer (DP_TX) invoked from
  1613. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1614. * cases
  1615. *
  1616. * Return: NULL on success,
  1617. * nbuf when it fails to send
  1618. */
  1619. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1620. {
  1621. struct ether_header *eh = NULL;
  1622. struct dp_tx_msdu_info_s msdu_info;
  1623. struct dp_tx_seg_info_s seg_info;
  1624. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1625. uint16_t peer_id = HTT_INVALID_PEER;
  1626. qdf_nbuf_t nbuf_mesh = NULL;
  1627. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1628. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1629. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1630. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1631. "%s , skb %pM",
  1632. __func__, nbuf->data);
  1633. /*
  1634. * Set Default Host TID value to invalid TID
  1635. * (TID override disabled)
  1636. */
  1637. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1638. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1639. if (qdf_unlikely(vdev->mesh_vdev)) {
  1640. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1641. &msdu_info);
  1642. if (nbuf_mesh == NULL) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1644. "Extracting mesh metadata failed\n");
  1645. return nbuf;
  1646. }
  1647. nbuf = nbuf_mesh;
  1648. }
  1649. /*
  1650. * Get HW Queue to use for this frame.
  1651. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1652. * dedicated for data and 1 for command.
  1653. * "queue_id" maps to one hardware ring.
  1654. * With each ring, we also associate a unique Tx descriptor pool
  1655. * to minimize lock contention for these resources.
  1656. */
  1657. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1658. /*
  1659. * TCL H/W supports 2 DSCP-TID mapping tables.
  1660. * Table 1 - Default DSCP-TID mapping table
  1661. * Table 2 - 1 DSCP-TID override table
  1662. *
  1663. * If we need a different DSCP-TID mapping for this vap,
  1664. * call tid_classify to extract DSCP/ToS from frame and
  1665. * map to a TID and store in msdu_info. This is later used
  1666. * to fill in TCL Input descriptor (per-packet TID override).
  1667. */
  1668. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1669. /* Reset the control block */
  1670. qdf_nbuf_reset_ctxt(nbuf);
  1671. /*
  1672. * Classify the frame and call corresponding
  1673. * "prepare" function which extracts the segment (TSO)
  1674. * and fragmentation information (for TSO , SG, ME, or Raw)
  1675. * into MSDU_INFO structure which is later used to fill
  1676. * SW and HW descriptors.
  1677. */
  1678. if (qdf_nbuf_is_tso(nbuf)) {
  1679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1680. "%s TSO frame %pK\n", __func__, vdev);
  1681. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1682. qdf_nbuf_len(nbuf));
  1683. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1684. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1685. return nbuf;
  1686. }
  1687. goto send_multiple;
  1688. }
  1689. /* SG */
  1690. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1691. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1693. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1694. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1695. qdf_nbuf_len(nbuf));
  1696. goto send_multiple;
  1697. }
  1698. #ifdef ATH_SUPPORT_IQUE
  1699. /* Mcast to Ucast Conversion*/
  1700. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1701. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1702. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1704. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1705. DP_STATS_INC_PKT(vdev,
  1706. tx_i.mcast_en.mcast_pkt, 1,
  1707. qdf_nbuf_len(nbuf));
  1708. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1709. QDF_STATUS_SUCCESS) {
  1710. return NULL;
  1711. }
  1712. }
  1713. }
  1714. #endif
  1715. /* RAW */
  1716. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1717. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1718. if (nbuf == NULL)
  1719. return NULL;
  1720. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1721. "%s Raw frame %pK\n", __func__, vdev);
  1722. goto send_multiple;
  1723. }
  1724. /* Single linear frame */
  1725. /*
  1726. * If nbuf is a simple linear frame, use send_single function to
  1727. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1728. * SRNG. There is no need to setup a MSDU extension descriptor.
  1729. */
  1730. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1731. return nbuf;
  1732. send_multiple:
  1733. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1734. return nbuf;
  1735. }
  1736. /**
  1737. * dp_tx_reinject_handler() - Tx Reinject Handler
  1738. * @tx_desc: software descriptor head pointer
  1739. * @status : Tx completion status from HTT descriptor
  1740. *
  1741. * This function reinjects frames back to Target.
  1742. * Todo - Host queue needs to be added
  1743. *
  1744. * Return: none
  1745. */
  1746. static
  1747. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1748. {
  1749. struct dp_vdev *vdev;
  1750. struct dp_peer *peer = NULL;
  1751. uint32_t peer_id = HTT_INVALID_PEER;
  1752. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1753. qdf_nbuf_t nbuf_copy = NULL;
  1754. struct dp_tx_msdu_info_s msdu_info;
  1755. struct dp_peer *sa_peer = NULL;
  1756. struct dp_ast_entry *ast_entry = NULL;
  1757. struct dp_soc *soc = NULL;
  1758. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1759. #ifdef WDS_VENDOR_EXTENSION
  1760. int is_mcast = 0, is_ucast = 0;
  1761. int num_peers_3addr = 0;
  1762. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1763. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1764. #endif
  1765. vdev = tx_desc->vdev;
  1766. soc = vdev->pdev->soc;
  1767. qdf_assert(vdev);
  1768. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1769. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1771. "%s Tx reinject path\n", __func__);
  1772. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1773. qdf_nbuf_len(tx_desc->nbuf));
  1774. qdf_spin_lock_bh(&(soc->ast_lock));
  1775. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1776. if (ast_entry)
  1777. sa_peer = ast_entry->peer;
  1778. qdf_spin_unlock_bh(&(soc->ast_lock));
  1779. #ifdef WDS_VENDOR_EXTENSION
  1780. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1781. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1782. } else {
  1783. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1784. }
  1785. is_ucast = !is_mcast;
  1786. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1787. if (peer->bss_peer)
  1788. continue;
  1789. /* Detect wds peers that use 3-addr framing for mcast.
  1790. * if there are any, the bss_peer is used to send the
  1791. * the mcast frame using 3-addr format. all wds enabled
  1792. * peers that use 4-addr framing for mcast frames will
  1793. * be duplicated and sent as 4-addr frames below.
  1794. */
  1795. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1796. num_peers_3addr = 1;
  1797. break;
  1798. }
  1799. }
  1800. #endif
  1801. if (qdf_unlikely(vdev->mesh_vdev)) {
  1802. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1803. } else {
  1804. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1805. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1806. #ifdef WDS_VENDOR_EXTENSION
  1807. /*
  1808. * . if 3-addr STA, then send on BSS Peer
  1809. * . if Peer WDS enabled and accept 4-addr mcast,
  1810. * send mcast on that peer only
  1811. * . if Peer WDS enabled and accept 4-addr ucast,
  1812. * send ucast on that peer only
  1813. */
  1814. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1815. (peer->wds_enabled &&
  1816. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1817. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1818. #else
  1819. ((peer->bss_peer &&
  1820. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1821. peer->nawds_enabled)) {
  1822. #endif
  1823. peer_id = DP_INVALID_PEER;
  1824. if (peer->nawds_enabled) {
  1825. peer_id = peer->peer_ids[0];
  1826. if (sa_peer == peer) {
  1827. QDF_TRACE(
  1828. QDF_MODULE_ID_DP,
  1829. QDF_TRACE_LEVEL_DEBUG,
  1830. " %s: multicast packet",
  1831. __func__);
  1832. DP_STATS_INC(peer,
  1833. tx.nawds_mcast_drop, 1);
  1834. continue;
  1835. }
  1836. }
  1837. nbuf_copy = qdf_nbuf_copy(nbuf);
  1838. if (!nbuf_copy) {
  1839. QDF_TRACE(QDF_MODULE_ID_DP,
  1840. QDF_TRACE_LEVEL_DEBUG,
  1841. FL("nbuf copy failed"));
  1842. break;
  1843. }
  1844. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1845. nbuf_copy,
  1846. &msdu_info,
  1847. peer_id,
  1848. NULL);
  1849. if (nbuf_copy) {
  1850. QDF_TRACE(QDF_MODULE_ID_DP,
  1851. QDF_TRACE_LEVEL_DEBUG,
  1852. FL("pkt send failed"));
  1853. qdf_nbuf_free(nbuf_copy);
  1854. } else {
  1855. if (peer_id != DP_INVALID_PEER)
  1856. DP_STATS_INC_PKT(peer,
  1857. tx.nawds_mcast,
  1858. 1, qdf_nbuf_len(nbuf));
  1859. }
  1860. }
  1861. }
  1862. }
  1863. if (vdev->nawds_enabled) {
  1864. peer_id = DP_INVALID_PEER;
  1865. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1866. 1, qdf_nbuf_len(nbuf));
  1867. nbuf = dp_tx_send_msdu_single(vdev,
  1868. nbuf,
  1869. &msdu_info,
  1870. peer_id, NULL);
  1871. if (nbuf) {
  1872. QDF_TRACE(QDF_MODULE_ID_DP,
  1873. QDF_TRACE_LEVEL_DEBUG,
  1874. FL("pkt send failed"));
  1875. qdf_nbuf_free(nbuf);
  1876. }
  1877. } else
  1878. qdf_nbuf_free(nbuf);
  1879. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1880. }
  1881. /**
  1882. * dp_tx_inspect_handler() - Tx Inspect Handler
  1883. * @tx_desc: software descriptor head pointer
  1884. * @status : Tx completion status from HTT descriptor
  1885. *
  1886. * Handles Tx frames sent back to Host for inspection
  1887. * (ProxyARP)
  1888. *
  1889. * Return: none
  1890. */
  1891. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1892. {
  1893. struct dp_soc *soc;
  1894. struct dp_pdev *pdev = tx_desc->pdev;
  1895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1896. "%s Tx inspect path\n",
  1897. __func__);
  1898. qdf_assert(pdev);
  1899. soc = pdev->soc;
  1900. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1901. qdf_nbuf_len(tx_desc->nbuf));
  1902. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1903. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1904. }
  1905. #ifdef FEATURE_PERPKT_INFO
  1906. /**
  1907. * dp_get_completion_indication_for_stack() - send completion to stack
  1908. * @soc : dp_soc handle
  1909. * @pdev: dp_pdev handle
  1910. * @peer_id: peer_id of the peer for which completion came
  1911. * @ppdu_id: ppdu_id
  1912. * @first_msdu: first msdu
  1913. * @last_msdu: last msdu
  1914. * @netbuf: Buffer pointer for free
  1915. *
  1916. * This function is used for indication whether buffer needs to be
  1917. * send to stack for free or not
  1918. */
  1919. QDF_STATUS
  1920. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1921. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1922. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1923. {
  1924. struct tx_capture_hdr *ppdu_hdr;
  1925. struct dp_peer *peer = NULL;
  1926. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1927. return QDF_STATUS_E_NOSUPPORT;
  1928. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1929. dp_peer_find_by_id(soc, peer_id);
  1930. if (!peer) {
  1931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1932. FL("Peer Invalid"));
  1933. return QDF_STATUS_E_INVAL;
  1934. }
  1935. if (pdev->mcopy_mode) {
  1936. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1937. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1938. return QDF_STATUS_E_INVAL;
  1939. }
  1940. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  1941. pdev->m_copy_id.tx_peer_id = peer_id;
  1942. }
  1943. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1944. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1945. FL("No headroom"));
  1946. return QDF_STATUS_E_NOMEM;
  1947. }
  1948. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1949. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1950. IEEE80211_ADDR_LEN);
  1951. ppdu_hdr->ppdu_id = ppdu_id;
  1952. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1953. IEEE80211_ADDR_LEN);
  1954. ppdu_hdr->peer_id = peer_id;
  1955. ppdu_hdr->first_msdu = first_msdu;
  1956. ppdu_hdr->last_msdu = last_msdu;
  1957. return QDF_STATUS_SUCCESS;
  1958. }
  1959. /**
  1960. * dp_send_completion_to_stack() - send completion to stack
  1961. * @soc : dp_soc handle
  1962. * @pdev: dp_pdev handle
  1963. * @peer_id: peer_id of the peer for which completion came
  1964. * @ppdu_id: ppdu_id
  1965. * @netbuf: Buffer pointer for free
  1966. *
  1967. * This function is used to send completion to stack
  1968. * to free buffer
  1969. */
  1970. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1971. uint16_t peer_id, uint32_t ppdu_id,
  1972. qdf_nbuf_t netbuf)
  1973. {
  1974. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1975. netbuf, peer_id,
  1976. WDI_NO_VAL, pdev->pdev_id);
  1977. }
  1978. #else
  1979. static QDF_STATUS
  1980. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1981. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1982. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1983. {
  1984. return QDF_STATUS_E_NOSUPPORT;
  1985. }
  1986. static void
  1987. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1988. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1989. {
  1990. }
  1991. #endif
  1992. /**
  1993. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1994. * @soc: Soc handle
  1995. * @desc: software Tx descriptor to be processed
  1996. *
  1997. * Return: none
  1998. */
  1999. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2000. struct dp_tx_desc_s *desc)
  2001. {
  2002. struct dp_vdev *vdev = desc->vdev;
  2003. qdf_nbuf_t nbuf = desc->nbuf;
  2004. /* If it is TDLS mgmt, don't unmap or free the frame */
  2005. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2006. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2007. /* 0 : MSDU buffer, 1 : MLE */
  2008. if (desc->msdu_ext_desc) {
  2009. /* TSO free */
  2010. if (hal_tx_ext_desc_get_tso_enable(
  2011. desc->msdu_ext_desc->vaddr)) {
  2012. /* If remaining number of segment is 0
  2013. * actual TSO may unmap and free */
  2014. if (qdf_nbuf_get_users(nbuf) == 1)
  2015. __qdf_nbuf_unmap_single(soc->osdev,
  2016. nbuf,
  2017. QDF_DMA_TO_DEVICE);
  2018. qdf_nbuf_free(nbuf);
  2019. return;
  2020. }
  2021. }
  2022. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2023. if (qdf_likely(!vdev->mesh_vdev))
  2024. qdf_nbuf_free(nbuf);
  2025. else {
  2026. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2027. qdf_nbuf_free(nbuf);
  2028. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2029. } else
  2030. vdev->osif_tx_free_ext((nbuf));
  2031. }
  2032. }
  2033. /**
  2034. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2035. * @vdev: pointer to dp dev handler
  2036. * @status : Tx completion status from HTT descriptor
  2037. *
  2038. * Handles MEC notify event sent from fw to Host
  2039. *
  2040. * Return: none
  2041. */
  2042. #ifdef FEATURE_WDS
  2043. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2044. {
  2045. struct dp_soc *soc;
  2046. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2047. struct dp_peer *peer;
  2048. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2049. if (!vdev->wds_enabled)
  2050. return;
  2051. soc = vdev->pdev->soc;
  2052. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2053. peer = TAILQ_FIRST(&vdev->peer_list);
  2054. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2055. if (!peer) {
  2056. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2057. FL("peer is NULL"));
  2058. return;
  2059. }
  2060. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2061. "%s Tx MEC Handler\n",
  2062. __func__);
  2063. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2064. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2065. status[(DP_MAC_ADDR_LEN - 2) + i];
  2066. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2067. dp_peer_add_ast(soc,
  2068. peer,
  2069. mac_addr,
  2070. CDP_TXRX_AST_TYPE_MEC,
  2071. flags);
  2072. }
  2073. #endif
  2074. /**
  2075. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2076. * @tx_desc: software descriptor head pointer
  2077. * @status : Tx completion status from HTT descriptor
  2078. *
  2079. * This function will process HTT Tx indication messages from Target
  2080. *
  2081. * Return: none
  2082. */
  2083. static
  2084. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2085. {
  2086. uint8_t tx_status;
  2087. struct dp_pdev *pdev;
  2088. struct dp_vdev *vdev;
  2089. struct dp_soc *soc;
  2090. uint32_t *htt_status_word = (uint32_t *) status;
  2091. qdf_assert(tx_desc->pdev);
  2092. pdev = tx_desc->pdev;
  2093. vdev = tx_desc->vdev;
  2094. soc = pdev->soc;
  2095. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2096. switch (tx_status) {
  2097. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2098. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2099. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2100. {
  2101. dp_tx_comp_free_buf(soc, tx_desc);
  2102. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2103. break;
  2104. }
  2105. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2106. {
  2107. dp_tx_reinject_handler(tx_desc, status);
  2108. break;
  2109. }
  2110. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2111. {
  2112. dp_tx_inspect_handler(tx_desc, status);
  2113. break;
  2114. }
  2115. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2116. {
  2117. dp_tx_mec_handler(vdev, status);
  2118. break;
  2119. }
  2120. default:
  2121. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2122. "%s Invalid HTT tx_status %d\n",
  2123. __func__, tx_status);
  2124. break;
  2125. }
  2126. }
  2127. #ifdef MESH_MODE_SUPPORT
  2128. /**
  2129. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2130. * in mesh meta header
  2131. * @tx_desc: software descriptor head pointer
  2132. * @ts: pointer to tx completion stats
  2133. * Return: none
  2134. */
  2135. static
  2136. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2137. struct hal_tx_completion_status *ts)
  2138. {
  2139. struct meta_hdr_s *mhdr;
  2140. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2141. if (!tx_desc->msdu_ext_desc) {
  2142. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2143. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2144. "netbuf %pK offset %d\n",
  2145. netbuf, tx_desc->pkt_offset);
  2146. return;
  2147. }
  2148. }
  2149. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2150. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2151. "netbuf %pK offset %d\n", netbuf,
  2152. sizeof(struct meta_hdr_s));
  2153. return;
  2154. }
  2155. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2156. mhdr->rssi = ts->ack_frame_rssi;
  2157. mhdr->channel = tx_desc->pdev->operating_channel;
  2158. }
  2159. #else
  2160. static
  2161. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2162. struct hal_tx_completion_status *ts)
  2163. {
  2164. }
  2165. #endif
  2166. /**
  2167. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2168. * @peer: Handle to DP peer
  2169. * @ts: pointer to HAL Tx completion stats
  2170. * @length: MSDU length
  2171. *
  2172. * Return: None
  2173. */
  2174. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2175. struct hal_tx_completion_status *ts, uint32_t length)
  2176. {
  2177. struct dp_pdev *pdev = peer->vdev->pdev;
  2178. struct dp_soc *soc = pdev->soc;
  2179. uint8_t mcs, pkt_type;
  2180. mcs = ts->mcs;
  2181. pkt_type = ts->pkt_type;
  2182. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2183. return;
  2184. if (peer->bss_peer) {
  2185. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2186. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2187. } else {
  2188. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  2189. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2190. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2191. }
  2192. }
  2193. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2194. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2195. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2196. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2197. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2198. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2199. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2200. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2201. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2202. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2203. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2204. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2205. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2206. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2207. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2208. return;
  2209. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2210. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2211. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2212. if (!(soc->process_tx_status))
  2213. return;
  2214. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2215. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2216. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2217. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2218. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2219. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2220. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2221. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2222. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2223. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2224. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2225. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2226. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2227. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2228. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2229. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2230. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2231. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2232. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2233. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2234. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2235. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2236. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2237. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2238. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2239. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2240. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2241. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2242. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2243. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2244. &peer->stats, ts->peer_id,
  2245. UPDATE_PEER_STATS);
  2246. }
  2247. }
  2248. /**
  2249. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2250. * @tx_desc: software descriptor head pointer
  2251. * @length: packet length
  2252. *
  2253. * Return: none
  2254. */
  2255. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2256. uint32_t length)
  2257. {
  2258. struct hal_tx_completion_status ts;
  2259. struct dp_soc *soc = NULL;
  2260. struct dp_vdev *vdev = tx_desc->vdev;
  2261. struct dp_peer *peer = NULL;
  2262. struct ether_header *eh =
  2263. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2264. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2265. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2266. "-------------------- \n"
  2267. "Tx Completion Stats: \n"
  2268. "-------------------- \n"
  2269. "ack_frame_rssi = %d \n"
  2270. "first_msdu = %d \n"
  2271. "last_msdu = %d \n"
  2272. "msdu_part_of_amsdu = %d \n"
  2273. "rate_stats valid = %d \n"
  2274. "bw = %d \n"
  2275. "pkt_type = %d \n"
  2276. "stbc = %d \n"
  2277. "ldpc = %d \n"
  2278. "sgi = %d \n"
  2279. "mcs = %d \n"
  2280. "ofdma = %d \n"
  2281. "tones_in_ru = %d \n"
  2282. "tsf = %d \n"
  2283. "ppdu_id = %d \n"
  2284. "transmit_cnt = %d \n"
  2285. "tid = %d \n"
  2286. "peer_id = %d \n",
  2287. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2288. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2289. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2290. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2291. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2292. ts.peer_id);
  2293. if (!vdev) {
  2294. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2295. "invalid vdev");
  2296. goto out;
  2297. }
  2298. soc = vdev->pdev->soc;
  2299. /* Update SoC level stats */
  2300. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2301. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2302. /* Update per-packet stats */
  2303. if (qdf_unlikely(vdev->mesh_vdev) &&
  2304. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2305. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2306. /* Update peer level stats */
  2307. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2308. if (!peer) {
  2309. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2310. "invalid peer");
  2311. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2312. goto out;
  2313. }
  2314. if (qdf_likely(peer->vdev->tx_encap_type ==
  2315. htt_cmn_pkt_type_ethernet)) {
  2316. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2317. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2318. }
  2319. dp_tx_update_peer_stats(peer, &ts, length);
  2320. out:
  2321. return;
  2322. }
  2323. /**
  2324. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2325. * @soc: core txrx main context
  2326. * @comp_head: software descriptor head pointer
  2327. *
  2328. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2329. * and release the software descriptors after processing is complete
  2330. *
  2331. * Return: none
  2332. */
  2333. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2334. struct dp_tx_desc_s *comp_head)
  2335. {
  2336. struct dp_tx_desc_s *desc;
  2337. struct dp_tx_desc_s *next;
  2338. struct hal_tx_completion_status ts = {0};
  2339. uint32_t length;
  2340. struct dp_peer *peer;
  2341. DP_HIST_INIT();
  2342. desc = comp_head;
  2343. while (desc) {
  2344. hal_tx_comp_get_status(&desc->comp, &ts);
  2345. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2346. length = qdf_nbuf_len(desc->nbuf);
  2347. dp_tx_comp_process_tx_status(desc, length);
  2348. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2349. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2350. desc->pdev, ts.peer_id, ts.ppdu_id,
  2351. ts.first_msdu, ts.last_msdu,
  2352. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2353. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2354. QDF_DMA_TO_DEVICE);
  2355. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2356. ts.ppdu_id, desc->nbuf);
  2357. } else {
  2358. dp_tx_comp_free_buf(soc, desc);
  2359. }
  2360. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2361. next = desc->next;
  2362. dp_tx_desc_release(desc, desc->pool_id);
  2363. desc = next;
  2364. }
  2365. DP_TX_HIST_STATS_PER_PDEV();
  2366. }
  2367. /**
  2368. * dp_tx_comp_handler() - Tx completion handler
  2369. * @soc: core txrx main context
  2370. * @ring_id: completion ring id
  2371. * @quota: No. of packets/descriptors that can be serviced in one loop
  2372. *
  2373. * This function will collect hardware release ring element contents and
  2374. * handle descriptor contents. Based on contents, free packet or handle error
  2375. * conditions
  2376. *
  2377. * Return: none
  2378. */
  2379. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2380. {
  2381. void *tx_comp_hal_desc;
  2382. uint8_t buffer_src;
  2383. uint8_t pool_id;
  2384. uint32_t tx_desc_id;
  2385. struct dp_tx_desc_s *tx_desc = NULL;
  2386. struct dp_tx_desc_s *head_desc = NULL;
  2387. struct dp_tx_desc_s *tail_desc = NULL;
  2388. uint32_t num_processed;
  2389. uint32_t count;
  2390. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2391. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2392. "%s %d : HAL RING Access Failed -- %pK\n",
  2393. __func__, __LINE__, hal_srng);
  2394. return 0;
  2395. }
  2396. num_processed = 0;
  2397. count = 0;
  2398. /* Find head descriptor from completion ring */
  2399. while (qdf_likely(tx_comp_hal_desc =
  2400. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2401. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2402. /* If this buffer was not released by TQM or FW, then it is not
  2403. * Tx completion indication, assert */
  2404. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2405. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2406. QDF_TRACE(QDF_MODULE_ID_DP,
  2407. QDF_TRACE_LEVEL_FATAL,
  2408. "Tx comp release_src != TQM | FW");
  2409. qdf_assert_always(0);
  2410. }
  2411. /* Get descriptor id */
  2412. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2413. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2414. DP_TX_DESC_ID_POOL_OS;
  2415. /* Pool ID is out of limit. Error */
  2416. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2417. soc->wlan_cfg_ctx)) {
  2418. QDF_TRACE(QDF_MODULE_ID_DP,
  2419. QDF_TRACE_LEVEL_FATAL,
  2420. "Tx Comp pool id %d not valid",
  2421. pool_id);
  2422. qdf_assert_always(0);
  2423. }
  2424. /* Find Tx descriptor */
  2425. tx_desc = dp_tx_desc_find(soc, pool_id,
  2426. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2427. DP_TX_DESC_ID_PAGE_OS,
  2428. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2429. DP_TX_DESC_ID_OFFSET_OS);
  2430. /*
  2431. * If the release source is FW, process the HTT status
  2432. */
  2433. if (qdf_unlikely(buffer_src ==
  2434. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2435. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2436. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2437. htt_tx_status);
  2438. dp_tx_process_htt_completion(tx_desc,
  2439. htt_tx_status);
  2440. } else {
  2441. /* Pool id is not matching. Error */
  2442. if (tx_desc->pool_id != pool_id) {
  2443. QDF_TRACE(QDF_MODULE_ID_DP,
  2444. QDF_TRACE_LEVEL_FATAL,
  2445. "Tx Comp pool id %d not matched %d",
  2446. pool_id, tx_desc->pool_id);
  2447. qdf_assert_always(0);
  2448. }
  2449. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2450. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2451. QDF_TRACE(QDF_MODULE_ID_DP,
  2452. QDF_TRACE_LEVEL_FATAL,
  2453. "Txdesc invalid, flgs = %x,id = %d",
  2454. tx_desc->flags, tx_desc_id);
  2455. qdf_assert_always(0);
  2456. }
  2457. /* First ring descriptor on the cycle */
  2458. if (!head_desc) {
  2459. head_desc = tx_desc;
  2460. tail_desc = tx_desc;
  2461. }
  2462. tail_desc->next = tx_desc;
  2463. tx_desc->next = NULL;
  2464. tail_desc = tx_desc;
  2465. /* Collect hw completion contents */
  2466. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2467. &tx_desc->comp, 1);
  2468. }
  2469. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2470. /* Decrement PM usage count if the packet has been sent.*/
  2471. hif_pm_runtime_put(soc->hif_handle);
  2472. /*
  2473. * Processed packet count is more than given quota
  2474. * stop to processing
  2475. */
  2476. if ((num_processed >= quota))
  2477. break;
  2478. count++;
  2479. }
  2480. hal_srng_access_end(soc->hal_soc, hal_srng);
  2481. /* Process the reaped descriptors */
  2482. if (head_desc)
  2483. dp_tx_comp_process_desc(soc, head_desc);
  2484. return num_processed;
  2485. }
  2486. #ifdef CONVERGED_TDLS_ENABLE
  2487. /**
  2488. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2489. *
  2490. * @data_vdev - which vdev should transmit the tx data frames
  2491. * @tx_spec - what non-standard handling to apply to the tx data frames
  2492. * @msdu_list - NULL-terminated list of tx MSDUs
  2493. *
  2494. * Return: NULL on success,
  2495. * nbuf when it fails to send
  2496. */
  2497. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2498. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2499. {
  2500. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2501. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2502. vdev->is_tdls_frame = true;
  2503. return dp_tx_send(vdev_handle, msdu_list);
  2504. }
  2505. #endif
  2506. /**
  2507. * dp_tx_vdev_attach() - attach vdev to dp tx
  2508. * @vdev: virtual device instance
  2509. *
  2510. * Return: QDF_STATUS_SUCCESS: success
  2511. * QDF_STATUS_E_RESOURCES: Error return
  2512. */
  2513. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2514. {
  2515. /*
  2516. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2517. */
  2518. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2519. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2520. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2521. vdev->vdev_id);
  2522. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2523. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2524. /*
  2525. * Set HTT Extension Valid bit to 0 by default
  2526. */
  2527. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2528. dp_tx_vdev_update_search_flags(vdev);
  2529. return QDF_STATUS_SUCCESS;
  2530. }
  2531. /**
  2532. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2533. * @vdev: virtual device instance
  2534. *
  2535. * Return: void
  2536. *
  2537. */
  2538. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2539. {
  2540. /*
  2541. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2542. * for TDLS link
  2543. *
  2544. * Enable AddrY (SA based search) only for non-WDS STA and
  2545. * ProxySTA VAP modes.
  2546. *
  2547. * In all other VAP modes, only DA based search should be
  2548. * enabled
  2549. */
  2550. if (vdev->opmode == wlan_op_mode_sta &&
  2551. vdev->tdls_link_connected)
  2552. vdev->hal_desc_addr_search_flags =
  2553. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2554. else if ((vdev->opmode == wlan_op_mode_sta &&
  2555. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2556. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2557. else
  2558. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2559. }
  2560. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2561. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2562. {
  2563. }
  2564. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2565. /* dp_tx_desc_flush() - release resources associated
  2566. * to tx_desc
  2567. * @vdev: virtual device instance
  2568. *
  2569. * This function will free all outstanding Tx buffers,
  2570. * including ME buffer for which either free during
  2571. * completion didn't happened or completion is not
  2572. * received.
  2573. */
  2574. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2575. {
  2576. uint8_t i, num_pool;
  2577. uint32_t j;
  2578. uint32_t num_desc;
  2579. struct dp_soc *soc = vdev->pdev->soc;
  2580. struct dp_tx_desc_s *tx_desc = NULL;
  2581. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2582. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2583. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2584. for (i = 0; i < num_pool; i++) {
  2585. for (j = 0; j < num_desc; j++) {
  2586. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2587. if (tx_desc_pool &&
  2588. tx_desc_pool->desc_pages.cacheable_pages) {
  2589. tx_desc = dp_tx_desc_find(soc, i,
  2590. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2591. DP_TX_DESC_ID_PAGE_OS,
  2592. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2593. DP_TX_DESC_ID_OFFSET_OS);
  2594. if (tx_desc && (tx_desc->vdev == vdev) &&
  2595. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2596. dp_tx_comp_free_buf(soc, tx_desc);
  2597. dp_tx_desc_release(tx_desc, i);
  2598. }
  2599. }
  2600. }
  2601. }
  2602. }
  2603. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2604. /**
  2605. * dp_tx_vdev_detach() - detach vdev from dp tx
  2606. * @vdev: virtual device instance
  2607. *
  2608. * Return: QDF_STATUS_SUCCESS: success
  2609. * QDF_STATUS_E_RESOURCES: Error return
  2610. */
  2611. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2612. {
  2613. dp_tx_desc_flush(vdev);
  2614. return QDF_STATUS_SUCCESS;
  2615. }
  2616. /**
  2617. * dp_tx_pdev_attach() - attach pdev to dp tx
  2618. * @pdev: physical device instance
  2619. *
  2620. * Return: QDF_STATUS_SUCCESS: success
  2621. * QDF_STATUS_E_RESOURCES: Error return
  2622. */
  2623. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2624. {
  2625. struct dp_soc *soc = pdev->soc;
  2626. /* Initialize Flow control counters */
  2627. qdf_atomic_init(&pdev->num_tx_exception);
  2628. qdf_atomic_init(&pdev->num_tx_outstanding);
  2629. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2630. /* Initialize descriptors in TCL Ring */
  2631. hal_tx_init_data_ring(soc->hal_soc,
  2632. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2633. }
  2634. return QDF_STATUS_SUCCESS;
  2635. }
  2636. /**
  2637. * dp_tx_pdev_detach() - detach pdev from dp tx
  2638. * @pdev: physical device instance
  2639. *
  2640. * Return: QDF_STATUS_SUCCESS: success
  2641. * QDF_STATUS_E_RESOURCES: Error return
  2642. */
  2643. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2644. {
  2645. dp_tx_me_exit(pdev);
  2646. return QDF_STATUS_SUCCESS;
  2647. }
  2648. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2649. /* Pools will be allocated dynamically */
  2650. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2651. int num_desc)
  2652. {
  2653. uint8_t i;
  2654. for (i = 0; i < num_pool; i++) {
  2655. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2656. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2657. }
  2658. return 0;
  2659. }
  2660. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2661. {
  2662. uint8_t i;
  2663. for (i = 0; i < num_pool; i++)
  2664. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2665. }
  2666. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2667. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2668. int num_desc)
  2669. {
  2670. uint8_t i;
  2671. /* Allocate software Tx descriptor pools */
  2672. for (i = 0; i < num_pool; i++) {
  2673. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2675. "%s Tx Desc Pool alloc %d failed %pK\n",
  2676. __func__, i, soc);
  2677. return ENOMEM;
  2678. }
  2679. }
  2680. return 0;
  2681. }
  2682. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2683. {
  2684. uint8_t i;
  2685. for (i = 0; i < num_pool; i++) {
  2686. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2687. if (dp_tx_desc_pool_free(soc, i)) {
  2688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2689. "%s Tx Desc Pool Free failed\n", __func__);
  2690. }
  2691. }
  2692. }
  2693. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2694. /**
  2695. * dp_tx_soc_detach() - detach soc from dp tx
  2696. * @soc: core txrx main context
  2697. *
  2698. * This function will detach dp tx into main device context
  2699. * will free dp tx resource and initialize resources
  2700. *
  2701. * Return: QDF_STATUS_SUCCESS: success
  2702. * QDF_STATUS_E_RESOURCES: Error return
  2703. */
  2704. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2705. {
  2706. uint8_t num_pool;
  2707. uint16_t num_desc;
  2708. uint16_t num_ext_desc;
  2709. uint8_t i;
  2710. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2711. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2712. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2713. dp_tx_flow_control_deinit(soc);
  2714. dp_tx_delete_static_pools(soc, num_pool);
  2715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2716. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2717. __func__, num_pool, num_desc);
  2718. for (i = 0; i < num_pool; i++) {
  2719. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2720. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2721. "%s Tx Ext Desc Pool Free failed\n",
  2722. __func__);
  2723. return QDF_STATUS_E_RESOURCES;
  2724. }
  2725. }
  2726. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2727. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2728. __func__, num_pool, num_ext_desc);
  2729. for (i = 0; i < num_pool; i++) {
  2730. dp_tx_tso_desc_pool_free(soc, i);
  2731. }
  2732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2733. "%s TSO Desc Pool %d Free descs = %d\n",
  2734. __func__, num_pool, num_desc);
  2735. for (i = 0; i < num_pool; i++)
  2736. dp_tx_tso_num_seg_pool_free(soc, i);
  2737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2738. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2739. __func__, num_pool, num_desc);
  2740. return QDF_STATUS_SUCCESS;
  2741. }
  2742. /**
  2743. * dp_tx_soc_attach() - attach soc to dp tx
  2744. * @soc: core txrx main context
  2745. *
  2746. * This function will attach dp tx into main device context
  2747. * will allocate dp tx resource and initialize resources
  2748. *
  2749. * Return: QDF_STATUS_SUCCESS: success
  2750. * QDF_STATUS_E_RESOURCES: Error return
  2751. */
  2752. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2753. {
  2754. uint8_t i;
  2755. uint8_t num_pool;
  2756. uint32_t num_desc;
  2757. uint32_t num_ext_desc;
  2758. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2759. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2760. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2761. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2762. goto fail;
  2763. dp_tx_flow_control_init(soc);
  2764. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2765. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2766. __func__, num_pool, num_desc);
  2767. /* Allocate extension tx descriptor pools */
  2768. for (i = 0; i < num_pool; i++) {
  2769. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2771. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2772. i, soc);
  2773. goto fail;
  2774. }
  2775. }
  2776. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2777. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2778. __func__, num_pool, num_ext_desc);
  2779. for (i = 0; i < num_pool; i++) {
  2780. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2781. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2782. "TSO Desc Pool alloc %d failed %pK\n",
  2783. i, soc);
  2784. goto fail;
  2785. }
  2786. }
  2787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2788. "%s TSO Desc Alloc %d, descs = %d\n",
  2789. __func__, num_pool, num_desc);
  2790. for (i = 0; i < num_pool; i++) {
  2791. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2792. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2793. "TSO Num of seg Pool alloc %d failed %pK\n",
  2794. i, soc);
  2795. goto fail;
  2796. }
  2797. }
  2798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2799. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2800. __func__, num_pool, num_desc);
  2801. /* Initialize descriptors in TCL Rings */
  2802. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2803. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2804. hal_tx_init_data_ring(soc->hal_soc,
  2805. soc->tcl_data_ring[i].hal_srng);
  2806. }
  2807. }
  2808. /*
  2809. * todo - Add a runtime config option to enable this.
  2810. */
  2811. /*
  2812. * Due to multiple issues on NPR EMU, enable it selectively
  2813. * only for NPR EMU, should be removed, once NPR platforms
  2814. * are stable.
  2815. */
  2816. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2818. "%s HAL Tx init Success\n", __func__);
  2819. return QDF_STATUS_SUCCESS;
  2820. fail:
  2821. /* Detach will take care of freeing only allocated resources */
  2822. dp_tx_soc_detach(soc);
  2823. return QDF_STATUS_E_RESOURCES;
  2824. }
  2825. /*
  2826. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2827. * pdev: pointer to DP PDEV structure
  2828. * seg_info_head: Pointer to the head of list
  2829. *
  2830. * return: void
  2831. */
  2832. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2833. struct dp_tx_seg_info_s *seg_info_head)
  2834. {
  2835. struct dp_tx_me_buf_t *mc_uc_buf;
  2836. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2837. qdf_nbuf_t nbuf = NULL;
  2838. uint64_t phy_addr;
  2839. while (seg_info_head) {
  2840. nbuf = seg_info_head->nbuf;
  2841. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2842. seg_info_head->frags[0].vaddr;
  2843. phy_addr = seg_info_head->frags[0].paddr_hi;
  2844. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2845. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2846. phy_addr,
  2847. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2848. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2849. qdf_nbuf_free(nbuf);
  2850. seg_info_new = seg_info_head;
  2851. seg_info_head = seg_info_head->next;
  2852. qdf_mem_free(seg_info_new);
  2853. }
  2854. }
  2855. /**
  2856. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2857. * @vdev: DP VDEV handle
  2858. * @nbuf: Multicast nbuf
  2859. * @newmac: Table of the clients to which packets have to be sent
  2860. * @new_mac_cnt: No of clients
  2861. *
  2862. * return: no of converted packets
  2863. */
  2864. uint16_t
  2865. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2866. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2867. {
  2868. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2869. struct dp_pdev *pdev = vdev->pdev;
  2870. struct ether_header *eh;
  2871. uint8_t *data;
  2872. uint16_t len;
  2873. /* reference to frame dst addr */
  2874. uint8_t *dstmac;
  2875. /* copy of original frame src addr */
  2876. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2877. /* local index into newmac */
  2878. uint8_t new_mac_idx = 0;
  2879. struct dp_tx_me_buf_t *mc_uc_buf;
  2880. qdf_nbuf_t nbuf_clone;
  2881. struct dp_tx_msdu_info_s msdu_info;
  2882. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2883. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2884. struct dp_tx_seg_info_s *seg_info_new;
  2885. struct dp_tx_frag_info_s data_frag;
  2886. qdf_dma_addr_t paddr_data;
  2887. qdf_dma_addr_t paddr_mcbuf = 0;
  2888. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2889. QDF_STATUS status;
  2890. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2891. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2892. eh = (struct ether_header *) nbuf;
  2893. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2894. len = qdf_nbuf_len(nbuf);
  2895. data = qdf_nbuf_data(nbuf);
  2896. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2897. QDF_DMA_TO_DEVICE);
  2898. if (status) {
  2899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2900. "Mapping failure Error:%d", status);
  2901. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2902. qdf_nbuf_free(nbuf);
  2903. return 1;
  2904. }
  2905. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2906. /*preparing data fragment*/
  2907. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2908. data_frag.paddr_lo = (uint32_t)paddr_data;
  2909. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2910. data_frag.len = len - DP_MAC_ADDR_LEN;
  2911. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2912. dstmac = newmac[new_mac_idx];
  2913. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2914. "added mac addr (%pM)", dstmac);
  2915. /* Check for NULL Mac Address */
  2916. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2917. continue;
  2918. /* frame to self mac. skip */
  2919. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2920. continue;
  2921. /*
  2922. * TODO: optimize to avoid malloc in per-packet path
  2923. * For eg. seg_pool can be made part of vdev structure
  2924. */
  2925. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2926. if (!seg_info_new) {
  2927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2928. "alloc failed");
  2929. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2930. goto fail_seg_alloc;
  2931. }
  2932. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2933. if (mc_uc_buf == NULL)
  2934. goto fail_buf_alloc;
  2935. /*
  2936. * TODO: Check if we need to clone the nbuf
  2937. * Or can we just use the reference for all cases
  2938. */
  2939. if (new_mac_idx < (new_mac_cnt - 1)) {
  2940. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2941. if (nbuf_clone == NULL) {
  2942. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2943. goto fail_clone;
  2944. }
  2945. } else {
  2946. /*
  2947. * Update the ref
  2948. * to account for frame sent without cloning
  2949. */
  2950. qdf_nbuf_ref(nbuf);
  2951. nbuf_clone = nbuf;
  2952. }
  2953. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2954. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2955. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2956. &paddr_mcbuf);
  2957. if (status) {
  2958. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2959. "Mapping failure Error:%d", status);
  2960. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2961. goto fail_map;
  2962. }
  2963. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2964. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2965. seg_info_new->frags[0].paddr_hi =
  2966. ((uint64_t) paddr_mcbuf >> 32);
  2967. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2968. seg_info_new->frags[1] = data_frag;
  2969. seg_info_new->nbuf = nbuf_clone;
  2970. seg_info_new->frag_cnt = 2;
  2971. seg_info_new->total_len = len;
  2972. seg_info_new->next = NULL;
  2973. if (seg_info_head == NULL)
  2974. seg_info_head = seg_info_new;
  2975. else
  2976. seg_info_tail->next = seg_info_new;
  2977. seg_info_tail = seg_info_new;
  2978. }
  2979. if (!seg_info_head) {
  2980. goto free_return;
  2981. }
  2982. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2983. msdu_info.num_seg = new_mac_cnt;
  2984. msdu_info.frm_type = dp_tx_frm_me;
  2985. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2986. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2987. while (seg_info_head->next) {
  2988. seg_info_new = seg_info_head;
  2989. seg_info_head = seg_info_head->next;
  2990. qdf_mem_free(seg_info_new);
  2991. }
  2992. qdf_mem_free(seg_info_head);
  2993. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2994. qdf_nbuf_free(nbuf);
  2995. return new_mac_cnt;
  2996. fail_map:
  2997. qdf_nbuf_free(nbuf_clone);
  2998. fail_clone:
  2999. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3000. fail_buf_alloc:
  3001. qdf_mem_free(seg_info_new);
  3002. fail_seg_alloc:
  3003. dp_tx_me_mem_free(pdev, seg_info_head);
  3004. free_return:
  3005. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3006. qdf_nbuf_free(nbuf);
  3007. return 1;
  3008. }