wcd938x.c 135 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. #define NUM_ATTEMPTS 5
  38. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  39. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  40. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  41. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  42. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  43. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  44. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  45. SNDRV_PCM_RATE_384000)
  46. /* Fractional Rates */
  47. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  48. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  49. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  50. SNDRV_PCM_FMTBIT_S24_LE |\
  51. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  52. enum {
  53. CODEC_TX = 0,
  54. CODEC_RX,
  55. };
  56. enum {
  57. WCD_ADC1 = 0,
  58. WCD_ADC2,
  59. WCD_ADC3,
  60. WCD_ADC4,
  61. ALLOW_BUCK_DISABLE,
  62. HPH_COMP_DELAY,
  63. HPH_PA_DELAY,
  64. AMIC2_BCS_ENABLE,
  65. WCD_SUPPLIES_LPM_MODE,
  66. WCD_ADC1_MODE,
  67. WCD_ADC2_MODE,
  68. WCD_ADC3_MODE,
  69. WCD_ADC4_MODE,
  70. };
  71. enum {
  72. ADC_MODE_INVALID = 0,
  73. ADC_MODE_HIFI,
  74. ADC_MODE_LO_HIF,
  75. ADC_MODE_NORMAL,
  76. ADC_MODE_LP,
  77. ADC_MODE_ULP1,
  78. ADC_MODE_ULP2,
  79. };
  80. static u8 tx_mode_bit[] = {
  81. [ADC_MODE_INVALID] = 0x00,
  82. [ADC_MODE_HIFI] = 0x01,
  83. [ADC_MODE_LO_HIF] = 0x02,
  84. [ADC_MODE_NORMAL] = 0x04,
  85. [ADC_MODE_LP] = 0x08,
  86. [ADC_MODE_ULP1] = 0x10,
  87. [ADC_MODE_ULP2] = 0x20,
  88. };
  89. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  90. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  91. static int wcd938x_handle_post_irq(void *data);
  92. static int wcd938x_reset(struct device *dev);
  93. static int wcd938x_reset_low(struct device *dev);
  94. static int wcd938x_get_adc_mode(int val);
  95. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  96. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  115. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  116. };
  117. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  118. .name = "wcd938x",
  119. .irqs = wcd938x_irqs,
  120. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  121. .num_regs = 3,
  122. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  123. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  124. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  125. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  126. .use_ack = 1,
  127. .runtime_pm = false,
  128. .handle_post_irq = wcd938x_handle_post_irq,
  129. .irq_drv_data = NULL,
  130. };
  131. static int wcd938x_handle_post_irq(void *data)
  132. {
  133. struct wcd938x_priv *wcd938x = data;
  134. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  135. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  136. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  137. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  138. wcd938x->tx_swr_dev->slave_irq_pending =
  139. ((sts1 || sts2 || sts3) ? true : false);
  140. return IRQ_HANDLED;
  141. }
  142. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  143. {
  144. int ret = 0;
  145. int bank = 0;
  146. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  147. if (ret)
  148. return -EINVAL;
  149. return ((bank & 0x40) ? 1: 0);
  150. }
  151. static int wcd938x_get_clk_rate(int mode)
  152. {
  153. int rate;
  154. switch (mode) {
  155. case ADC_MODE_ULP2:
  156. rate = SWR_CLK_RATE_0P6MHZ;
  157. break;
  158. case ADC_MODE_ULP1:
  159. rate = SWR_CLK_RATE_1P2MHZ;
  160. break;
  161. case ADC_MODE_LP:
  162. rate = SWR_CLK_RATE_4P8MHZ;
  163. break;
  164. case ADC_MODE_NORMAL:
  165. case ADC_MODE_LO_HIF:
  166. case ADC_MODE_HIFI:
  167. case ADC_MODE_INVALID:
  168. default:
  169. rate = SWR_CLK_RATE_9P6MHZ;
  170. break;
  171. }
  172. return rate;
  173. }
  174. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  175. int rate, int bank)
  176. {
  177. u8 mask = (bank ? 0xF0 : 0x0F);
  178. u8 val = 0;
  179. switch (rate) {
  180. case SWR_CLK_RATE_0P6MHZ:
  181. val = (bank ? 0x60 : 0x06);
  182. break;
  183. case SWR_CLK_RATE_1P2MHZ:
  184. val = (bank ? 0x50 : 0x05);
  185. break;
  186. case SWR_CLK_RATE_2P4MHZ:
  187. val = (bank ? 0x30 : 0x03);
  188. break;
  189. case SWR_CLK_RATE_4P8MHZ:
  190. val = (bank ? 0x10 : 0x01);
  191. break;
  192. case SWR_CLK_RATE_9P6MHZ:
  193. default:
  194. val = 0x00;
  195. break;
  196. }
  197. snd_soc_component_update_bits(component,
  198. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  199. mask, val);
  200. return 0;
  201. }
  202. static int wcd938x_init_reg(struct snd_soc_component *component)
  203. {
  204. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  205. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  206. /* 1 msec delay as per HW requirement */
  207. usleep_range(1000, 1010);
  208. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  209. /* 1 msec delay as per HW requirement */
  210. usleep_range(1000, 1010);
  211. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  212. 0x10, 0x00);
  213. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  214. 0xF0, 0x80);
  215. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  216. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  217. /* 10 msec delay as per HW requirement */
  218. usleep_range(10000, 10010);
  219. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  220. snd_soc_component_update_bits(component,
  221. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  222. 0xF0, 0x00);
  223. snd_soc_component_update_bits(component,
  224. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  225. 0x1F, 0x15);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  228. 0x1F, 0x15);
  229. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  230. 0xC0, 0x80);
  231. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  232. 0x02, 0x02);
  233. snd_soc_component_update_bits(component,
  234. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  235. 0xFF, 0x14);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  238. 0x1F, 0x08);
  239. snd_soc_component_update_bits(component,
  240. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  241. snd_soc_component_update_bits(component,
  242. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  253. snd_soc_component_update_bits(component,
  254. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  255. snd_soc_component_update_bits(component,
  256. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  257. snd_soc_component_update_bits(component,
  258. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  259. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  260. ((snd_soc_component_read(component,
  261. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  262. snd_soc_component_update_bits(component,
  263. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  264. return 0;
  265. }
  266. static int wcd938x_set_port_params(struct snd_soc_component *component,
  267. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  268. u8 *ch_mask, u32 *ch_rate,
  269. u8 *port_type, u8 path)
  270. {
  271. int i, j;
  272. u8 num_ports = 0;
  273. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  274. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  275. switch (path) {
  276. case CODEC_RX:
  277. map = &wcd938x->rx_port_mapping;
  278. num_ports = wcd938x->num_rx_ports;
  279. break;
  280. case CODEC_TX:
  281. map = &wcd938x->tx_port_mapping;
  282. num_ports = wcd938x->num_tx_ports;
  283. break;
  284. default:
  285. dev_err(component->dev, "%s Invalid path selected %u\n",
  286. __func__, path);
  287. return -EINVAL;
  288. }
  289. for (i = 0; i <= num_ports; i++) {
  290. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  291. if ((*map)[i][j].slave_port_type == slv_prt_type)
  292. goto found;
  293. }
  294. }
  295. found:
  296. if (i > num_ports || j == MAX_CH_PER_PORT) {
  297. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  298. __func__, slv_prt_type);
  299. return -EINVAL;
  300. }
  301. *port_id = i;
  302. *num_ch = (*map)[i][j].num_ch;
  303. *ch_mask = (*map)[i][j].ch_mask;
  304. *ch_rate = (*map)[i][j].ch_rate;
  305. *port_type = (*map)[i][j].master_port_type;
  306. return 0;
  307. }
  308. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  309. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  310. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  311. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  312. static int wcd938x_parse_port_params(struct device *dev,
  313. char *prop, u8 path)
  314. {
  315. u32 *dt_array, map_size, max_uc;
  316. int ret = 0;
  317. u32 offset1, lane_ctrl, cnt = 0;
  318. struct port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  319. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  320. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  321. switch (path) {
  322. case CODEC_TX:
  323. map = &wcd938x->tx_port_params;
  324. map_uc = &wcd938x->swr_tx_port_params;
  325. break;
  326. default:
  327. ret = -EINVAL;
  328. goto err_port_map;
  329. }
  330. if (!of_find_property(dev->of_node, prop,
  331. &map_size)) {
  332. dev_err(dev, "missing port mapping prop %s\n", prop);
  333. ret = -EINVAL;
  334. goto err_port_map;
  335. }
  336. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  337. if (max_uc != SWR_UC_MAX) {
  338. dev_err(dev, "%s: port params not provided for all usecases\n",
  339. __func__);
  340. ret = -EINVAL;
  341. goto err_port_map;
  342. }
  343. dt_array = kzalloc(map_size, GFP_KERNEL);
  344. if (!dt_array) {
  345. ret = -ENOMEM;
  346. goto err_alloc;
  347. }
  348. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  349. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  350. if (ret) {
  351. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  352. __func__, prop);
  353. goto err_pdata_fail;
  354. }
  355. for (i = 0; i < max_uc; i++) {
  356. for (j = 0; j < SWR_NUM_PORTS; j++) {
  357. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  358. (*map)[i][j].offset1 = dt_array[cnt];
  359. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  360. }
  361. (*map_uc)[i] = &(*map)[i][0];
  362. }
  363. kfree(dt_array);
  364. return 0;
  365. err_pdata_fail:
  366. kfree(dt_array);
  367. err_alloc:
  368. err_port_map:
  369. return ret;
  370. }
  371. static int wcd938x_parse_port_mapping(struct device *dev,
  372. char *prop, u8 path)
  373. {
  374. u32 *dt_array, map_size, map_length;
  375. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  376. u32 slave_port_type, master_port_type;
  377. u32 i, ch_iter = 0;
  378. int ret = 0;
  379. u8 *num_ports = NULL;
  380. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  381. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  382. switch (path) {
  383. case CODEC_RX:
  384. map = &wcd938x->rx_port_mapping;
  385. num_ports = &wcd938x->num_rx_ports;
  386. break;
  387. case CODEC_TX:
  388. map = &wcd938x->tx_port_mapping;
  389. num_ports = &wcd938x->num_tx_ports;
  390. break;
  391. default:
  392. dev_err(dev, "%s Invalid path selected %u\n",
  393. __func__, path);
  394. return -EINVAL;
  395. }
  396. if (!of_find_property(dev->of_node, prop,
  397. &map_size)) {
  398. dev_err(dev, "missing port mapping prop %s\n", prop);
  399. ret = -EINVAL;
  400. goto err_port_map;
  401. }
  402. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  403. dt_array = kzalloc(map_size, GFP_KERNEL);
  404. if (!dt_array) {
  405. ret = -ENOMEM;
  406. goto err_alloc;
  407. }
  408. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  409. NUM_SWRS_DT_PARAMS * map_length);
  410. if (ret) {
  411. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  412. __func__, prop);
  413. goto err_pdata_fail;
  414. }
  415. for (i = 0; i < map_length; i++) {
  416. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  417. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  418. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  419. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  420. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  421. if (port_num != old_port_num)
  422. ch_iter = 0;
  423. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  424. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  425. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  426. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  427. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  428. old_port_num = port_num;
  429. }
  430. *num_ports = port_num;
  431. kfree(dt_array);
  432. return 0;
  433. err_pdata_fail:
  434. kfree(dt_array);
  435. err_alloc:
  436. err_port_map:
  437. return ret;
  438. }
  439. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  440. u8 slv_port_type, int clk_rate,
  441. u8 enable)
  442. {
  443. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  444. u8 port_id, num_ch, ch_mask;
  445. u8 ch_type = 0;
  446. u32 ch_rate;
  447. int slave_ch_idx;
  448. u8 num_port = 1;
  449. int ret = 0;
  450. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  451. &num_ch, &ch_mask, &ch_rate,
  452. &ch_type, CODEC_TX);
  453. if (ret)
  454. return ret;
  455. if (clk_rate)
  456. ch_rate = clk_rate;
  457. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  458. if (slave_ch_idx != -EINVAL)
  459. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  460. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  461. __func__, slave_ch_idx, ch_type);
  462. if (enable)
  463. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  464. num_port, &ch_mask, &ch_rate,
  465. &num_ch, &ch_type);
  466. else
  467. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  468. num_port, &ch_mask, &ch_type);
  469. return ret;
  470. }
  471. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  472. u8 slv_port_type, u8 enable)
  473. {
  474. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  475. u8 port_id, num_ch, ch_mask, port_type;
  476. u32 ch_rate;
  477. u8 num_port = 1;
  478. int ret = 0;
  479. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  480. &num_ch, &ch_mask, &ch_rate,
  481. &port_type, CODEC_RX);
  482. if (ret)
  483. return ret;
  484. if (enable)
  485. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  486. num_port, &ch_mask, &ch_rate,
  487. &num_ch, &port_type);
  488. else
  489. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  490. num_port, &ch_mask, &port_type);
  491. return ret;
  492. }
  493. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  494. {
  495. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  496. if (wcd938x->rx_clk_cnt == 0) {
  497. snd_soc_component_update_bits(component,
  498. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  499. snd_soc_component_update_bits(component,
  500. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  501. snd_soc_component_update_bits(component,
  502. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  503. snd_soc_component_update_bits(component,
  504. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  505. snd_soc_component_update_bits(component,
  506. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  509. snd_soc_component_update_bits(component,
  510. WCD938X_AUX_AUXPA, 0x10, 0x10);
  511. }
  512. wcd938x->rx_clk_cnt++;
  513. return 0;
  514. }
  515. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  516. {
  517. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  518. wcd938x->rx_clk_cnt--;
  519. if (wcd938x->rx_clk_cnt == 0) {
  520. snd_soc_component_update_bits(component,
  521. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  522. snd_soc_component_update_bits(component,
  523. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  524. snd_soc_component_update_bits(component,
  525. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  526. snd_soc_component_update_bits(component,
  527. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  528. snd_soc_component_update_bits(component,
  529. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  530. }
  531. return 0;
  532. }
  533. /*
  534. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  535. * @component: handle to snd_soc_component *
  536. *
  537. * return wcd938x_mbhc handle or error code in case of failure
  538. */
  539. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  540. {
  541. struct wcd938x_priv *wcd938x;
  542. if (!component) {
  543. pr_err("%s: Invalid params, NULL component\n", __func__);
  544. return NULL;
  545. }
  546. wcd938x = snd_soc_component_get_drvdata(component);
  547. if (!wcd938x) {
  548. pr_err("%s: wcd938x is NULL\n", __func__);
  549. return NULL;
  550. }
  551. return wcd938x->mbhc;
  552. }
  553. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  554. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  555. struct snd_kcontrol *kcontrol,
  556. int event)
  557. {
  558. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  559. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  560. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  561. w->name, event);
  562. switch (event) {
  563. case SND_SOC_DAPM_PRE_PMU:
  564. wcd938x_rx_clk_enable(component);
  565. snd_soc_component_update_bits(component,
  566. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  567. snd_soc_component_update_bits(component,
  568. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  569. snd_soc_component_update_bits(component,
  570. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  571. break;
  572. case SND_SOC_DAPM_POST_PMU:
  573. snd_soc_component_update_bits(component,
  574. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  575. if (wcd938x->comp1_enable) {
  576. snd_soc_component_update_bits(component,
  577. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  578. /* 5msec compander delay as per HW requirement */
  579. if (!wcd938x->comp2_enable ||
  580. (snd_soc_component_read(component,
  581. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  582. usleep_range(5000, 5010);
  583. snd_soc_component_update_bits(component,
  584. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  585. } else {
  586. snd_soc_component_update_bits(component,
  587. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  588. 0x02, 0x00);
  589. snd_soc_component_update_bits(component,
  590. WCD938X_HPH_L_EN, 0x20, 0x20);
  591. }
  592. break;
  593. case SND_SOC_DAPM_POST_PMD:
  594. snd_soc_component_update_bits(component,
  595. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  596. 0x0F, 0x01);
  597. break;
  598. }
  599. return 0;
  600. }
  601. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol,
  603. int event)
  604. {
  605. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  606. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  607. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  608. w->name, event);
  609. switch (event) {
  610. case SND_SOC_DAPM_PRE_PMU:
  611. wcd938x_rx_clk_enable(component);
  612. snd_soc_component_update_bits(component,
  613. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  614. snd_soc_component_update_bits(component,
  615. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  616. snd_soc_component_update_bits(component,
  617. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  618. break;
  619. case SND_SOC_DAPM_POST_PMU:
  620. snd_soc_component_update_bits(component,
  621. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  622. if (wcd938x->comp2_enable) {
  623. snd_soc_component_update_bits(component,
  624. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  625. /* 5msec compander delay as per HW requirement */
  626. if (!wcd938x->comp1_enable ||
  627. (snd_soc_component_read(component,
  628. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  629. usleep_range(5000, 5010);
  630. snd_soc_component_update_bits(component,
  631. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  632. } else {
  633. snd_soc_component_update_bits(component,
  634. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  635. 0x01, 0x00);
  636. snd_soc_component_update_bits(component,
  637. WCD938X_HPH_R_EN, 0x20, 0x20);
  638. }
  639. break;
  640. case SND_SOC_DAPM_POST_PMD:
  641. snd_soc_component_update_bits(component,
  642. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  643. 0x0F, 0x01);
  644. break;
  645. }
  646. return 0;
  647. }
  648. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  649. struct snd_kcontrol *kcontrol,
  650. int event)
  651. {
  652. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  653. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  654. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  655. w->name, event);
  656. switch (event) {
  657. case SND_SOC_DAPM_PRE_PMU:
  658. wcd938x_rx_clk_enable(component);
  659. wcd938x->ear_rx_path =
  660. snd_soc_component_read(
  661. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  662. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  663. snd_soc_component_update_bits(component,
  664. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  665. snd_soc_component_update_bits(component,
  666. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  667. snd_soc_component_update_bits(component,
  668. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  669. snd_soc_component_update_bits(component,
  670. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  671. } else {
  672. snd_soc_component_update_bits(component,
  673. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  674. snd_soc_component_update_bits(component,
  675. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  676. if (wcd938x->comp1_enable)
  677. snd_soc_component_update_bits(component,
  678. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  679. 0x02, 0x02);
  680. }
  681. /* 5 msec delay as per HW requirement */
  682. usleep_range(5000, 5010);
  683. if (wcd938x->flyback_cur_det_disable == 0)
  684. snd_soc_component_update_bits(component,
  685. WCD938X_FLYBACK_EN,
  686. 0x04, 0x00);
  687. wcd938x->flyback_cur_det_disable++;
  688. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  689. WCD_CLSH_EVENT_PRE_DAC,
  690. WCD_CLSH_STATE_EAR,
  691. wcd938x->hph_mode);
  692. break;
  693. case SND_SOC_DAPM_POST_PMD:
  694. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  695. snd_soc_component_update_bits(component,
  696. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  697. snd_soc_component_update_bits(component,
  698. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  699. } else {
  700. snd_soc_component_update_bits(component,
  701. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  702. snd_soc_component_update_bits(component,
  703. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  704. if (wcd938x->comp1_enable)
  705. snd_soc_component_update_bits(component,
  706. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  707. 0x02, 0x00);
  708. }
  709. snd_soc_component_update_bits(component,
  710. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  711. snd_soc_component_update_bits(component,
  712. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  713. break;
  714. };
  715. return 0;
  716. }
  717. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  718. struct snd_kcontrol *kcontrol,
  719. int event)
  720. {
  721. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  722. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  723. int ret = 0;
  724. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  725. w->name, event);
  726. switch (event) {
  727. case SND_SOC_DAPM_PRE_PMU:
  728. wcd938x_rx_clk_enable(component);
  729. snd_soc_component_update_bits(component,
  730. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  731. snd_soc_component_update_bits(component,
  732. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  733. snd_soc_component_update_bits(component,
  734. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  735. if (wcd938x->flyback_cur_det_disable == 0)
  736. snd_soc_component_update_bits(component,
  737. WCD938X_FLYBACK_EN,
  738. 0x04, 0x00);
  739. wcd938x->flyback_cur_det_disable++;
  740. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  741. WCD_CLSH_EVENT_PRE_DAC,
  742. WCD_CLSH_STATE_AUX,
  743. wcd938x->hph_mode);
  744. break;
  745. case SND_SOC_DAPM_POST_PMD:
  746. snd_soc_component_update_bits(component,
  747. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  748. break;
  749. };
  750. return ret;
  751. }
  752. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  753. struct snd_kcontrol *kcontrol,
  754. int event)
  755. {
  756. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  757. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  758. int ret = 0;
  759. int hph_mode = wcd938x->hph_mode;
  760. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  761. w->name, event);
  762. switch (event) {
  763. case SND_SOC_DAPM_PRE_PMU:
  764. if (wcd938x->ldoh)
  765. snd_soc_component_update_bits(component,
  766. WCD938X_LDOH_MODE,
  767. 0x80, 0x80);
  768. if (wcd938x->update_wcd_event)
  769. wcd938x->update_wcd_event(wcd938x->handle,
  770. SLV_BOLERO_EVT_RX_MUTE,
  771. (WCD_RX2 << 0x10 | 0x1));
  772. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  773. wcd938x->rx_swr_dev->dev_num,
  774. true);
  775. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  776. WCD_CLSH_EVENT_PRE_DAC,
  777. WCD_CLSH_STATE_HPHR,
  778. hph_mode);
  779. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  780. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  781. hph_mode == CLS_H_ULP) {
  782. snd_soc_component_update_bits(component,
  783. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  784. }
  785. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  786. 0x10, 0x10);
  787. wcd_clsh_set_hph_mode(component, hph_mode);
  788. /* 100 usec delay as per HW requirement */
  789. usleep_range(100, 110);
  790. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  791. snd_soc_component_update_bits(component,
  792. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  793. break;
  794. case SND_SOC_DAPM_POST_PMU:
  795. /*
  796. * 7ms sleep is required if compander is enabled as per
  797. * HW requirement. If compander is disabled, then
  798. * 20ms delay is required.
  799. */
  800. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  801. if (!wcd938x->comp2_enable)
  802. usleep_range(20000, 20100);
  803. else
  804. usleep_range(7000, 7100);
  805. if (hph_mode == CLS_H_LP ||
  806. hph_mode == CLS_H_LOHIFI ||
  807. hph_mode == CLS_H_ULP)
  808. snd_soc_component_update_bits(component,
  809. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  810. 0x00);
  811. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  812. }
  813. snd_soc_component_update_bits(component,
  814. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  815. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  816. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  817. snd_soc_component_update_bits(component,
  818. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  819. if (wcd938x->update_wcd_event)
  820. wcd938x->update_wcd_event(wcd938x->handle,
  821. SLV_BOLERO_EVT_RX_MUTE,
  822. (WCD_RX2 << 0x10));
  823. wcd_enable_irq(&wcd938x->irq_info,
  824. WCD938X_IRQ_HPHR_PDM_WD_INT);
  825. break;
  826. case SND_SOC_DAPM_PRE_PMD:
  827. if (wcd938x->update_wcd_event)
  828. wcd938x->update_wcd_event(wcd938x->handle,
  829. SLV_BOLERO_EVT_RX_MUTE,
  830. (WCD_RX2 << 0x10 | 0x1));
  831. wcd_disable_irq(&wcd938x->irq_info,
  832. WCD938X_IRQ_HPHR_PDM_WD_INT);
  833. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  834. wcd938x->update_wcd_event(wcd938x->handle,
  835. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  836. (WCD_RX2 << 0x10));
  837. /*
  838. * 7ms sleep is required if compander is enabled as per
  839. * HW requirement. If compander is disabled, then
  840. * 20ms delay is required.
  841. */
  842. if (!wcd938x->comp2_enable)
  843. usleep_range(20000, 20100);
  844. else
  845. usleep_range(7000, 7100);
  846. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  847. 0x40, 0x00);
  848. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  849. WCD_EVENT_PRE_HPHR_PA_OFF,
  850. &wcd938x->mbhc->wcd_mbhc);
  851. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  852. break;
  853. case SND_SOC_DAPM_POST_PMD:
  854. /*
  855. * 7ms sleep is required if compander is enabled as per
  856. * HW requirement. If compander is disabled, then
  857. * 20ms delay is required.
  858. */
  859. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  860. if (!wcd938x->comp2_enable)
  861. usleep_range(20000, 20100);
  862. else
  863. usleep_range(7000, 7100);
  864. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  865. }
  866. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  867. WCD_EVENT_POST_HPHR_PA_OFF,
  868. &wcd938x->mbhc->wcd_mbhc);
  869. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  870. 0x10, 0x00);
  871. snd_soc_component_update_bits(component,
  872. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  873. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  874. WCD_CLSH_EVENT_POST_PA,
  875. WCD_CLSH_STATE_HPHR,
  876. hph_mode);
  877. if (wcd938x->ldoh)
  878. snd_soc_component_update_bits(component,
  879. WCD938X_LDOH_MODE,
  880. 0x80, 0x00);
  881. break;
  882. };
  883. return ret;
  884. }
  885. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  886. struct snd_kcontrol *kcontrol,
  887. int event)
  888. {
  889. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  890. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  891. int ret = 0;
  892. int hph_mode = wcd938x->hph_mode;
  893. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  894. w->name, event);
  895. switch (event) {
  896. case SND_SOC_DAPM_PRE_PMU:
  897. if (wcd938x->ldoh)
  898. snd_soc_component_update_bits(component,
  899. WCD938X_LDOH_MODE,
  900. 0x80, 0x80);
  901. if (wcd938x->update_wcd_event)
  902. wcd938x->update_wcd_event(wcd938x->handle,
  903. SLV_BOLERO_EVT_RX_MUTE,
  904. (WCD_RX1 << 0x10 | 0x01));
  905. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  906. wcd938x->rx_swr_dev->dev_num,
  907. true);
  908. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  909. WCD_CLSH_EVENT_PRE_DAC,
  910. WCD_CLSH_STATE_HPHL,
  911. hph_mode);
  912. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  913. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  914. hph_mode == CLS_H_ULP) {
  915. snd_soc_component_update_bits(component,
  916. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  917. }
  918. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  919. 0x20, 0x20);
  920. wcd_clsh_set_hph_mode(component, hph_mode);
  921. /* 100 usec delay as per HW requirement */
  922. usleep_range(100, 110);
  923. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  924. snd_soc_component_update_bits(component,
  925. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  926. break;
  927. case SND_SOC_DAPM_POST_PMU:
  928. /*
  929. * 7ms sleep is required if compander is enabled as per
  930. * HW requirement. If compander is disabled, then
  931. * 20ms delay is required.
  932. */
  933. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  934. if (!wcd938x->comp1_enable)
  935. usleep_range(20000, 20100);
  936. else
  937. usleep_range(7000, 7100);
  938. if (hph_mode == CLS_H_LP ||
  939. hph_mode == CLS_H_LOHIFI ||
  940. hph_mode == CLS_H_ULP)
  941. snd_soc_component_update_bits(component,
  942. WCD938X_HPH_REFBUFF_LP_CTL,
  943. 0x01, 0x00);
  944. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  945. }
  946. snd_soc_component_update_bits(component,
  947. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  948. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  949. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  950. snd_soc_component_update_bits(component,
  951. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  952. if (wcd938x->update_wcd_event)
  953. wcd938x->update_wcd_event(wcd938x->handle,
  954. SLV_BOLERO_EVT_RX_MUTE,
  955. (WCD_RX1 << 0x10));
  956. wcd_enable_irq(&wcd938x->irq_info,
  957. WCD938X_IRQ_HPHL_PDM_WD_INT);
  958. break;
  959. case SND_SOC_DAPM_PRE_PMD:
  960. if (wcd938x->update_wcd_event)
  961. wcd938x->update_wcd_event(wcd938x->handle,
  962. SLV_BOLERO_EVT_RX_MUTE,
  963. (WCD_RX1 << 0x10 | 0x1));
  964. wcd_disable_irq(&wcd938x->irq_info,
  965. WCD938X_IRQ_HPHL_PDM_WD_INT);
  966. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  967. wcd938x->update_wcd_event(wcd938x->handle,
  968. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  969. (WCD_RX1 << 0x10));
  970. /*
  971. * 7ms sleep is required if compander is enabled as per
  972. * HW requirement. If compander is disabled, then
  973. * 20ms delay is required.
  974. */
  975. if (!wcd938x->comp1_enable)
  976. usleep_range(20000, 20100);
  977. else
  978. usleep_range(7000, 7100);
  979. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  980. 0x80, 0x00);
  981. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  982. WCD_EVENT_PRE_HPHL_PA_OFF,
  983. &wcd938x->mbhc->wcd_mbhc);
  984. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  985. break;
  986. case SND_SOC_DAPM_POST_PMD:
  987. /*
  988. * 7ms sleep is required if compander is enabled as per
  989. * HW requirement. If compander is disabled, then
  990. * 20ms delay is required.
  991. */
  992. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  993. if (!wcd938x->comp1_enable)
  994. usleep_range(21000, 21100);
  995. else
  996. usleep_range(7000, 7100);
  997. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  998. }
  999. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1000. WCD_EVENT_POST_HPHL_PA_OFF,
  1001. &wcd938x->mbhc->wcd_mbhc);
  1002. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1003. 0x20, 0x00);
  1004. snd_soc_component_update_bits(component,
  1005. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  1006. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1007. WCD_CLSH_EVENT_POST_PA,
  1008. WCD_CLSH_STATE_HPHL,
  1009. hph_mode);
  1010. if (wcd938x->ldoh)
  1011. snd_soc_component_update_bits(component,
  1012. WCD938X_LDOH_MODE,
  1013. 0x80, 0x00);
  1014. break;
  1015. };
  1016. return ret;
  1017. }
  1018. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1019. struct snd_kcontrol *kcontrol,
  1020. int event)
  1021. {
  1022. struct snd_soc_component *component =
  1023. snd_soc_dapm_to_component(w->dapm);
  1024. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1025. int hph_mode = wcd938x->hph_mode;
  1026. int ret = 0;
  1027. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1028. w->name, event);
  1029. switch (event) {
  1030. case SND_SOC_DAPM_PRE_PMU:
  1031. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1032. wcd938x->rx_swr_dev->dev_num,
  1033. true);
  1034. snd_soc_component_update_bits(component,
  1035. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  1036. break;
  1037. case SND_SOC_DAPM_POST_PMU:
  1038. /* 1 msec delay as per HW requirement */
  1039. usleep_range(1000, 1010);
  1040. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1041. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1042. snd_soc_component_update_bits(component,
  1043. WCD938X_ANA_RX_SUPPLIES,
  1044. 0x02, 0x02);
  1045. if (wcd938x->update_wcd_event)
  1046. wcd938x->update_wcd_event(wcd938x->handle,
  1047. SLV_BOLERO_EVT_RX_MUTE,
  1048. (WCD_RX3 << 0x10));
  1049. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  1050. break;
  1051. case SND_SOC_DAPM_PRE_PMD:
  1052. wcd_disable_irq(&wcd938x->irq_info,
  1053. WCD938X_IRQ_AUX_PDM_WD_INT);
  1054. if (wcd938x->update_wcd_event)
  1055. wcd938x->update_wcd_event(wcd938x->handle,
  1056. SLV_BOLERO_EVT_RX_MUTE,
  1057. (WCD_RX3 << 0x10 | 0x1));
  1058. break;
  1059. case SND_SOC_DAPM_POST_PMD:
  1060. /* 1 msec delay as per HW requirement */
  1061. usleep_range(1000, 1010);
  1062. snd_soc_component_update_bits(component,
  1063. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1064. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1065. WCD_CLSH_EVENT_POST_PA,
  1066. WCD_CLSH_STATE_AUX,
  1067. hph_mode);
  1068. wcd938x->flyback_cur_det_disable--;
  1069. if (wcd938x->flyback_cur_det_disable == 0)
  1070. snd_soc_component_update_bits(component,
  1071. WCD938X_FLYBACK_EN,
  1072. 0x04, 0x04);
  1073. break;
  1074. };
  1075. return ret;
  1076. }
  1077. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1078. struct snd_kcontrol *kcontrol,
  1079. int event)
  1080. {
  1081. struct snd_soc_component *component =
  1082. snd_soc_dapm_to_component(w->dapm);
  1083. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1084. int hph_mode = wcd938x->hph_mode;
  1085. int ret = 0;
  1086. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1087. w->name, event);
  1088. switch (event) {
  1089. case SND_SOC_DAPM_PRE_PMU:
  1090. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1091. wcd938x->rx_swr_dev->dev_num,
  1092. true);
  1093. /*
  1094. * Enable watchdog interrupt for HPHL or AUX
  1095. * depending on mux value
  1096. */
  1097. wcd938x->ear_rx_path =
  1098. snd_soc_component_read(
  1099. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1100. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1101. snd_soc_component_update_bits(component,
  1102. WCD938X_DIGITAL_PDM_WD_CTL2,
  1103. 0x01, 0x01);
  1104. else
  1105. snd_soc_component_update_bits(component,
  1106. WCD938X_DIGITAL_PDM_WD_CTL0,
  1107. 0x07, 0x03);
  1108. if (!wcd938x->comp1_enable)
  1109. snd_soc_component_update_bits(component,
  1110. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1111. break;
  1112. case SND_SOC_DAPM_POST_PMU:
  1113. /* 6 msec delay as per HW requirement */
  1114. usleep_range(6000, 6010);
  1115. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1116. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1117. snd_soc_component_update_bits(component,
  1118. WCD938X_ANA_RX_SUPPLIES,
  1119. 0x02, 0x02);
  1120. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1121. if (wcd938x->update_wcd_event)
  1122. wcd938x->update_wcd_event(wcd938x->handle,
  1123. SLV_BOLERO_EVT_RX_MUTE,
  1124. (WCD_RX3 << 0x10));
  1125. wcd_enable_irq(&wcd938x->irq_info,
  1126. WCD938X_IRQ_AUX_PDM_WD_INT);
  1127. } else {
  1128. if (wcd938x->update_wcd_event)
  1129. wcd938x->update_wcd_event(wcd938x->handle,
  1130. SLV_BOLERO_EVT_RX_MUTE,
  1131. (WCD_RX1 << 0x10));
  1132. wcd_enable_irq(&wcd938x->irq_info,
  1133. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1134. }
  1135. break;
  1136. case SND_SOC_DAPM_PRE_PMD:
  1137. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1138. wcd_disable_irq(&wcd938x->irq_info,
  1139. WCD938X_IRQ_AUX_PDM_WD_INT);
  1140. if (wcd938x->update_wcd_event)
  1141. wcd938x->update_wcd_event(wcd938x->handle,
  1142. SLV_BOLERO_EVT_RX_MUTE,
  1143. (WCD_RX3 << 0x10 | 0x1));
  1144. } else {
  1145. wcd_disable_irq(&wcd938x->irq_info,
  1146. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1147. if (wcd938x->update_wcd_event)
  1148. wcd938x->update_wcd_event(wcd938x->handle,
  1149. SLV_BOLERO_EVT_RX_MUTE,
  1150. (WCD_RX1 << 0x10 | 0x1));
  1151. }
  1152. break;
  1153. case SND_SOC_DAPM_POST_PMD:
  1154. if (!wcd938x->comp1_enable)
  1155. snd_soc_component_update_bits(component,
  1156. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1157. /* 7 msec delay as per HW requirement */
  1158. usleep_range(7000, 7010);
  1159. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1160. snd_soc_component_update_bits(component,
  1161. WCD938X_DIGITAL_PDM_WD_CTL2,
  1162. 0x01, 0x00);
  1163. else
  1164. snd_soc_component_update_bits(component,
  1165. WCD938X_DIGITAL_PDM_WD_CTL0,
  1166. 0x07, 0x00);
  1167. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1168. WCD_CLSH_EVENT_POST_PA,
  1169. WCD_CLSH_STATE_EAR,
  1170. hph_mode);
  1171. wcd938x->flyback_cur_det_disable--;
  1172. if (wcd938x->flyback_cur_det_disable == 0)
  1173. snd_soc_component_update_bits(component,
  1174. WCD938X_FLYBACK_EN,
  1175. 0x04, 0x04);
  1176. break;
  1177. };
  1178. return ret;
  1179. }
  1180. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1181. struct snd_kcontrol *kcontrol,
  1182. int event)
  1183. {
  1184. struct snd_soc_component *component =
  1185. snd_soc_dapm_to_component(w->dapm);
  1186. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1187. int mode = wcd938x->hph_mode;
  1188. int ret = 0;
  1189. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1190. w->name, event);
  1191. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1192. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1193. wcd938x_rx_connect_port(component, CLSH,
  1194. SND_SOC_DAPM_EVENT_ON(event));
  1195. }
  1196. if (SND_SOC_DAPM_EVENT_OFF(event))
  1197. ret = swr_slvdev_datapath_control(
  1198. wcd938x->rx_swr_dev,
  1199. wcd938x->rx_swr_dev->dev_num,
  1200. false);
  1201. return ret;
  1202. }
  1203. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1204. struct snd_kcontrol *kcontrol,
  1205. int event)
  1206. {
  1207. struct snd_soc_component *component =
  1208. snd_soc_dapm_to_component(w->dapm);
  1209. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1210. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1211. w->name, event);
  1212. switch (event) {
  1213. case SND_SOC_DAPM_PRE_PMU:
  1214. wcd938x_rx_connect_port(component, HPH_L, true);
  1215. if (wcd938x->comp1_enable)
  1216. wcd938x_rx_connect_port(component, COMP_L, true);
  1217. break;
  1218. case SND_SOC_DAPM_POST_PMD:
  1219. wcd938x_rx_connect_port(component, HPH_L, false);
  1220. if (wcd938x->comp1_enable)
  1221. wcd938x_rx_connect_port(component, COMP_L, false);
  1222. wcd938x_rx_clk_disable(component);
  1223. snd_soc_component_update_bits(component,
  1224. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1225. 0x01, 0x00);
  1226. break;
  1227. };
  1228. return 0;
  1229. }
  1230. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1231. struct snd_kcontrol *kcontrol, int event)
  1232. {
  1233. struct snd_soc_component *component =
  1234. snd_soc_dapm_to_component(w->dapm);
  1235. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1236. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1237. w->name, event);
  1238. switch (event) {
  1239. case SND_SOC_DAPM_PRE_PMU:
  1240. wcd938x_rx_connect_port(component, HPH_R, true);
  1241. if (wcd938x->comp2_enable)
  1242. wcd938x_rx_connect_port(component, COMP_R, true);
  1243. break;
  1244. case SND_SOC_DAPM_POST_PMD:
  1245. wcd938x_rx_connect_port(component, HPH_R, false);
  1246. if (wcd938x->comp2_enable)
  1247. wcd938x_rx_connect_port(component, COMP_R, false);
  1248. wcd938x_rx_clk_disable(component);
  1249. snd_soc_component_update_bits(component,
  1250. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1251. 0x02, 0x00);
  1252. break;
  1253. };
  1254. return 0;
  1255. }
  1256. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1257. struct snd_kcontrol *kcontrol,
  1258. int event)
  1259. {
  1260. struct snd_soc_component *component =
  1261. snd_soc_dapm_to_component(w->dapm);
  1262. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1263. w->name, event);
  1264. switch (event) {
  1265. case SND_SOC_DAPM_PRE_PMU:
  1266. wcd938x_rx_connect_port(component, LO, true);
  1267. break;
  1268. case SND_SOC_DAPM_POST_PMD:
  1269. wcd938x_rx_connect_port(component, LO, false);
  1270. /* 6 msec delay as per HW requirement */
  1271. usleep_range(6000, 6010);
  1272. wcd938x_rx_clk_disable(component);
  1273. snd_soc_component_update_bits(component,
  1274. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1275. break;
  1276. }
  1277. return 0;
  1278. }
  1279. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1280. struct snd_kcontrol *kcontrol,
  1281. int event)
  1282. {
  1283. struct snd_soc_component *component =
  1284. snd_soc_dapm_to_component(w->dapm);
  1285. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1286. u16 dmic_clk_reg, dmic_clk_en_reg;
  1287. s32 *dmic_clk_cnt;
  1288. u8 dmic_ctl_shift = 0;
  1289. u8 dmic_clk_shift = 0;
  1290. u8 dmic_clk_mask = 0;
  1291. u16 dmic2_left_en = 0;
  1292. int ret = 0;
  1293. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1294. w->name, event);
  1295. switch (w->shift) {
  1296. case 0:
  1297. case 1:
  1298. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1299. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1300. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1301. dmic_clk_mask = 0x0F;
  1302. dmic_clk_shift = 0x00;
  1303. dmic_ctl_shift = 0x00;
  1304. break;
  1305. case 2:
  1306. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1307. case 3:
  1308. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1309. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1310. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1311. dmic_clk_mask = 0xF0;
  1312. dmic_clk_shift = 0x04;
  1313. dmic_ctl_shift = 0x01;
  1314. break;
  1315. case 4:
  1316. case 5:
  1317. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1318. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1319. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1320. dmic_clk_mask = 0x0F;
  1321. dmic_clk_shift = 0x00;
  1322. dmic_ctl_shift = 0x02;
  1323. break;
  1324. case 6:
  1325. case 7:
  1326. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1327. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1328. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1329. dmic_clk_mask = 0xF0;
  1330. dmic_clk_shift = 0x04;
  1331. dmic_ctl_shift = 0x03;
  1332. break;
  1333. default:
  1334. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1335. __func__);
  1336. return -EINVAL;
  1337. };
  1338. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1339. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1340. switch (event) {
  1341. case SND_SOC_DAPM_PRE_PMU:
  1342. snd_soc_component_update_bits(component,
  1343. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1344. (0x01 << dmic_ctl_shift), 0x00);
  1345. /* 250us sleep as per HW requirement */
  1346. usleep_range(250, 260);
  1347. if (dmic2_left_en)
  1348. snd_soc_component_update_bits(component,
  1349. dmic2_left_en, 0x80, 0x80);
  1350. /* Setting DMIC clock rate to 2.4MHz */
  1351. snd_soc_component_update_bits(component,
  1352. dmic_clk_reg, dmic_clk_mask,
  1353. (0x03 << dmic_clk_shift));
  1354. snd_soc_component_update_bits(component,
  1355. dmic_clk_en_reg, 0x08, 0x08);
  1356. /* enable clock scaling */
  1357. snd_soc_component_update_bits(component,
  1358. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1359. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1360. wcd938x->tx_swr_dev->dev_num,
  1361. true);
  1362. break;
  1363. case SND_SOC_DAPM_POST_PMD:
  1364. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1365. false);
  1366. snd_soc_component_update_bits(component,
  1367. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1368. (0x01 << dmic_ctl_shift),
  1369. (0x01 << dmic_ctl_shift));
  1370. if (dmic2_left_en)
  1371. snd_soc_component_update_bits(component,
  1372. dmic2_left_en, 0x80, 0x00);
  1373. snd_soc_component_update_bits(component,
  1374. dmic_clk_en_reg, 0x08, 0x00);
  1375. break;
  1376. };
  1377. return ret;
  1378. }
  1379. /*
  1380. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1381. * @micb_mv: micbias in mv
  1382. *
  1383. * return register value converted
  1384. */
  1385. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1386. {
  1387. /* min micbias voltage is 1V and maximum is 2.85V */
  1388. if (micb_mv < 1000 || micb_mv > 2850) {
  1389. pr_err("%s: unsupported micbias voltage\n", __func__);
  1390. return -EINVAL;
  1391. }
  1392. return (micb_mv - 1000) / 50;
  1393. }
  1394. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1395. /*
  1396. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1397. * @component: handle to snd_soc_component *
  1398. * @req_volt: micbias voltage to be set
  1399. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1400. *
  1401. * return 0 if adjustment is success or error code in case of failure
  1402. */
  1403. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1404. int req_volt, int micb_num)
  1405. {
  1406. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1407. int cur_vout_ctl, req_vout_ctl;
  1408. int micb_reg, micb_val, micb_en;
  1409. int ret = 0;
  1410. switch (micb_num) {
  1411. case MIC_BIAS_1:
  1412. micb_reg = WCD938X_ANA_MICB1;
  1413. break;
  1414. case MIC_BIAS_2:
  1415. micb_reg = WCD938X_ANA_MICB2;
  1416. break;
  1417. case MIC_BIAS_3:
  1418. micb_reg = WCD938X_ANA_MICB3;
  1419. break;
  1420. case MIC_BIAS_4:
  1421. micb_reg = WCD938X_ANA_MICB4;
  1422. break;
  1423. default:
  1424. return -EINVAL;
  1425. }
  1426. mutex_lock(&wcd938x->micb_lock);
  1427. /*
  1428. * If requested micbias voltage is same as current micbias
  1429. * voltage, then just return. Otherwise, adjust voltage as
  1430. * per requested value. If micbias is already enabled, then
  1431. * to avoid slow micbias ramp-up or down enable pull-up
  1432. * momentarily, change the micbias value and then re-enable
  1433. * micbias.
  1434. */
  1435. micb_val = snd_soc_component_read(component, micb_reg);
  1436. micb_en = (micb_val & 0xC0) >> 6;
  1437. cur_vout_ctl = micb_val & 0x3F;
  1438. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1439. if (req_vout_ctl < 0) {
  1440. ret = -EINVAL;
  1441. goto exit;
  1442. }
  1443. if (cur_vout_ctl == req_vout_ctl) {
  1444. ret = 0;
  1445. goto exit;
  1446. }
  1447. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1448. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1449. req_volt, micb_en);
  1450. if (micb_en == 0x1)
  1451. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1452. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1453. if (micb_en == 0x1) {
  1454. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1455. /*
  1456. * Add 2ms delay as per HW requirement after enabling
  1457. * micbias
  1458. */
  1459. usleep_range(2000, 2100);
  1460. }
  1461. exit:
  1462. mutex_unlock(&wcd938x->micb_lock);
  1463. return ret;
  1464. }
  1465. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1466. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1467. struct snd_kcontrol *kcontrol,
  1468. int event)
  1469. {
  1470. struct snd_soc_component *component =
  1471. snd_soc_dapm_to_component(w->dapm);
  1472. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1473. int ret = 0;
  1474. int bank = 0;
  1475. u8 mode = 0;
  1476. int i = 0;
  1477. int rate = 0;
  1478. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1479. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1480. /* power mode is applicable only to analog mics */
  1481. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1482. /* Get channel rate */
  1483. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1484. }
  1485. switch (event) {
  1486. case SND_SOC_DAPM_PRE_PMU:
  1487. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1488. if (w->shift == ADC2 && !(snd_soc_component_read(component,
  1489. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1490. if (!wcd938x->bcs_dis)
  1491. wcd938x_tx_connect_port(component, MBHC,
  1492. SWR_CLK_RATE_4P8MHZ, true);
  1493. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1494. }
  1495. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1496. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1497. wcd938x_tx_connect_port(component, w->shift, rate,
  1498. true);
  1499. } else {
  1500. wcd938x_tx_connect_port(component, w->shift,
  1501. SWR_CLK_RATE_2P4MHZ, true);
  1502. }
  1503. break;
  1504. case SND_SOC_DAPM_POST_PMD:
  1505. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1506. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1507. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1508. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1509. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1510. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1511. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1512. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1513. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1514. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1515. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1516. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1517. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1518. }
  1519. }
  1520. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1521. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1522. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1523. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1524. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1525. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1526. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1527. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1528. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1529. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1530. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1531. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1532. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1533. if (mode != 0) {
  1534. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1535. if (mode & (1 << i)) {
  1536. i++;
  1537. break;
  1538. }
  1539. }
  1540. }
  1541. rate = wcd938x_get_clk_rate(i);
  1542. if (wcd938x->adc_count) {
  1543. rate = (wcd938x->adc_count * rate);
  1544. if (rate > SWR_CLK_RATE_9P6MHZ)
  1545. rate = SWR_CLK_RATE_9P6MHZ;
  1546. }
  1547. wcd938x_set_swr_clk_rate(component, rate, bank);
  1548. }
  1549. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1550. wcd938x->tx_swr_dev->dev_num,
  1551. false);
  1552. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1553. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1554. break;
  1555. };
  1556. return ret;
  1557. }
  1558. static int wcd938x_get_adc_mode(int val)
  1559. {
  1560. int ret = 0;
  1561. switch (val) {
  1562. case ADC_MODE_INVALID:
  1563. ret = ADC_MODE_VAL_NORMAL;
  1564. break;
  1565. case ADC_MODE_HIFI:
  1566. ret = ADC_MODE_VAL_HIFI;
  1567. break;
  1568. case ADC_MODE_LO_HIF:
  1569. ret = ADC_MODE_VAL_LO_HIF;
  1570. break;
  1571. case ADC_MODE_NORMAL:
  1572. ret = ADC_MODE_VAL_NORMAL;
  1573. break;
  1574. case ADC_MODE_LP:
  1575. ret = ADC_MODE_VAL_LP;
  1576. break;
  1577. case ADC_MODE_ULP1:
  1578. ret = ADC_MODE_VAL_ULP1;
  1579. break;
  1580. case ADC_MODE_ULP2:
  1581. ret = ADC_MODE_VAL_ULP2;
  1582. break;
  1583. default:
  1584. ret = -EINVAL;
  1585. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1586. break;
  1587. }
  1588. return ret;
  1589. }
  1590. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1591. int channel, int mode)
  1592. {
  1593. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1594. int ret = 0;
  1595. switch (channel) {
  1596. case 0:
  1597. reg = WCD938X_ANA_TX_CH2;
  1598. mask = 0x40;
  1599. break;
  1600. case 1:
  1601. reg = WCD938X_ANA_TX_CH2;
  1602. mask = 0x20;
  1603. break;
  1604. case 2:
  1605. reg = WCD938X_ANA_TX_CH4;
  1606. mask = 0x40;
  1607. break;
  1608. case 3:
  1609. reg = WCD938X_ANA_TX_CH4;
  1610. mask = 0x20;
  1611. break;
  1612. default:
  1613. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1614. ret = -EINVAL;
  1615. break;
  1616. }
  1617. if (!mode)
  1618. val = 0x00;
  1619. else
  1620. val = mask;
  1621. if (!ret)
  1622. snd_soc_component_update_bits(component, reg, mask, val);
  1623. return ret;
  1624. }
  1625. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1626. struct snd_kcontrol *kcontrol,
  1627. int event){
  1628. struct snd_soc_component *component =
  1629. snd_soc_dapm_to_component(w->dapm);
  1630. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1631. int clk_rate = 0, ret = 0;
  1632. int mode = 0, i = 0, bank = 0;
  1633. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1634. w->name, event);
  1635. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1636. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1637. switch (event) {
  1638. case SND_SOC_DAPM_PRE_PMU:
  1639. wcd938x->adc_count++;
  1640. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1641. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1642. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1643. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1644. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1645. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1646. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1647. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1648. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1649. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1650. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1651. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1652. if (mode != 0) {
  1653. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1654. if (mode & (1 << i)) {
  1655. i++;
  1656. break;
  1657. }
  1658. }
  1659. }
  1660. clk_rate = wcd938x_get_clk_rate(i);
  1661. /* clk_rate depends on number of paths getting enabled */
  1662. clk_rate = (wcd938x->adc_count * clk_rate);
  1663. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1664. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1665. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1666. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1667. wcd938x->tx_swr_dev->dev_num,
  1668. true);
  1669. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1670. break;
  1671. case SND_SOC_DAPM_POST_PMD:
  1672. wcd938x->adc_count--;
  1673. if (wcd938x->adc_count < 0)
  1674. wcd938x->adc_count = 0;
  1675. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1676. if (w->shift + ADC1 == ADC2 &&
  1677. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1678. if (!wcd938x->bcs_dis)
  1679. wcd938x_tx_connect_port(component, MBHC, 0,
  1680. false);
  1681. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1682. }
  1683. break;
  1684. };
  1685. return ret;
  1686. }
  1687. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1688. bool bcs_disable)
  1689. {
  1690. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1691. if (wcd938x->update_wcd_event) {
  1692. if (bcs_disable)
  1693. wcd938x->update_wcd_event(wcd938x->handle,
  1694. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1695. else
  1696. wcd938x->update_wcd_event(wcd938x->handle,
  1697. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1698. }
  1699. }
  1700. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1701. struct snd_kcontrol *kcontrol, int event)
  1702. {
  1703. struct snd_soc_component *component =
  1704. snd_soc_dapm_to_component(w->dapm);
  1705. struct wcd938x_priv *wcd938x =
  1706. snd_soc_component_get_drvdata(component);
  1707. int ret = 0;
  1708. u8 mode = 0;
  1709. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1710. w->name, event);
  1711. switch (event) {
  1712. case SND_SOC_DAPM_PRE_PMU:
  1713. snd_soc_component_update_bits(component,
  1714. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1715. snd_soc_component_update_bits(component,
  1716. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1717. snd_soc_component_update_bits(component,
  1718. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1719. snd_soc_component_update_bits(component,
  1720. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1721. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1722. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1723. if (mode < 0) {
  1724. dev_info(component->dev,
  1725. "%s: invalid mode, setting to normal mode\n",
  1726. __func__);
  1727. mode = ADC_MODE_VAL_NORMAL;
  1728. }
  1729. switch (w->shift) {
  1730. case 0:
  1731. snd_soc_component_update_bits(component,
  1732. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1733. mode);
  1734. snd_soc_component_update_bits(component,
  1735. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1736. break;
  1737. case 1:
  1738. snd_soc_component_update_bits(component,
  1739. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1740. mode << 4);
  1741. snd_soc_component_update_bits(component,
  1742. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1743. break;
  1744. case 2:
  1745. snd_soc_component_update_bits(component,
  1746. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1747. mode);
  1748. snd_soc_component_update_bits(component,
  1749. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1750. break;
  1751. case 3:
  1752. snd_soc_component_update_bits(component,
  1753. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1754. mode << 4);
  1755. snd_soc_component_update_bits(component,
  1756. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1757. break;
  1758. default:
  1759. break;
  1760. }
  1761. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1762. break;
  1763. case SND_SOC_DAPM_POST_PMD:
  1764. switch (w->shift) {
  1765. case 0:
  1766. snd_soc_component_update_bits(component,
  1767. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1768. 0x00);
  1769. snd_soc_component_update_bits(component,
  1770. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1771. break;
  1772. case 1:
  1773. snd_soc_component_update_bits(component,
  1774. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1775. 0x00);
  1776. snd_soc_component_update_bits(component,
  1777. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1778. break;
  1779. case 2:
  1780. snd_soc_component_update_bits(component,
  1781. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1782. 0x00);
  1783. snd_soc_component_update_bits(component,
  1784. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1785. break;
  1786. case 3:
  1787. snd_soc_component_update_bits(component,
  1788. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1789. 0x00);
  1790. snd_soc_component_update_bits(component,
  1791. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1792. break;
  1793. default:
  1794. break;
  1795. }
  1796. if (wcd938x->adc_count == 0) {
  1797. snd_soc_component_update_bits(component,
  1798. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1799. snd_soc_component_update_bits(component,
  1800. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1801. }
  1802. break;
  1803. };
  1804. return ret;
  1805. }
  1806. int wcd938x_micbias_control(struct snd_soc_component *component,
  1807. int micb_num, int req, bool is_dapm)
  1808. {
  1809. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1810. int micb_index = micb_num - 1;
  1811. u16 micb_reg;
  1812. int pre_off_event = 0, post_off_event = 0;
  1813. int post_on_event = 0, post_dapm_off = 0;
  1814. int post_dapm_on = 0;
  1815. int ret = 0;
  1816. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1817. dev_err(component->dev,
  1818. "%s: Invalid micbias index, micb_ind:%d\n",
  1819. __func__, micb_index);
  1820. return -EINVAL;
  1821. }
  1822. if (NULL == wcd938x) {
  1823. dev_err(component->dev,
  1824. "%s: wcd938x private data is NULL\n", __func__);
  1825. return -EINVAL;
  1826. }
  1827. switch (micb_num) {
  1828. case MIC_BIAS_1:
  1829. micb_reg = WCD938X_ANA_MICB1;
  1830. break;
  1831. case MIC_BIAS_2:
  1832. micb_reg = WCD938X_ANA_MICB2;
  1833. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1834. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1835. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1836. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1837. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1838. break;
  1839. case MIC_BIAS_3:
  1840. micb_reg = WCD938X_ANA_MICB3;
  1841. break;
  1842. case MIC_BIAS_4:
  1843. micb_reg = WCD938X_ANA_MICB4;
  1844. break;
  1845. default:
  1846. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1847. __func__, micb_num);
  1848. return -EINVAL;
  1849. };
  1850. mutex_lock(&wcd938x->micb_lock);
  1851. switch (req) {
  1852. case MICB_PULLUP_ENABLE:
  1853. if (!wcd938x->dev_up) {
  1854. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1855. __func__, req);
  1856. ret = -ENODEV;
  1857. goto done;
  1858. }
  1859. wcd938x->pullup_ref[micb_index]++;
  1860. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1861. (wcd938x->micb_ref[micb_index] == 0))
  1862. snd_soc_component_update_bits(component, micb_reg,
  1863. 0xC0, 0x80);
  1864. break;
  1865. case MICB_PULLUP_DISABLE:
  1866. if (wcd938x->pullup_ref[micb_index] > 0)
  1867. wcd938x->pullup_ref[micb_index]--;
  1868. if (!wcd938x->dev_up) {
  1869. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1870. __func__, req);
  1871. ret = -ENODEV;
  1872. goto done;
  1873. }
  1874. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1875. (wcd938x->micb_ref[micb_index] == 0))
  1876. snd_soc_component_update_bits(component, micb_reg,
  1877. 0xC0, 0x00);
  1878. break;
  1879. case MICB_ENABLE:
  1880. if (!wcd938x->dev_up) {
  1881. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1882. __func__, req);
  1883. ret = -ENODEV;
  1884. goto done;
  1885. }
  1886. wcd938x->micb_ref[micb_index]++;
  1887. if (wcd938x->micb_ref[micb_index] == 1) {
  1888. snd_soc_component_update_bits(component,
  1889. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1890. snd_soc_component_update_bits(component,
  1891. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1892. snd_soc_component_update_bits(component,
  1893. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1894. snd_soc_component_update_bits(component,
  1895. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1896. snd_soc_component_update_bits(component,
  1897. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1898. snd_soc_component_update_bits(component,
  1899. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1900. snd_soc_component_update_bits(component,
  1901. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1902. snd_soc_component_update_bits(component,
  1903. micb_reg, 0xC0, 0x40);
  1904. if (post_on_event)
  1905. blocking_notifier_call_chain(
  1906. &wcd938x->mbhc->notifier,
  1907. post_on_event,
  1908. &wcd938x->mbhc->wcd_mbhc);
  1909. }
  1910. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1911. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1912. post_dapm_on,
  1913. &wcd938x->mbhc->wcd_mbhc);
  1914. break;
  1915. case MICB_DISABLE:
  1916. if (wcd938x->micb_ref[micb_index] > 0)
  1917. wcd938x->micb_ref[micb_index]--;
  1918. if (!wcd938x->dev_up) {
  1919. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1920. __func__, req);
  1921. ret = -ENODEV;
  1922. goto done;
  1923. }
  1924. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1925. (wcd938x->pullup_ref[micb_index] > 0))
  1926. snd_soc_component_update_bits(component, micb_reg,
  1927. 0xC0, 0x80);
  1928. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1929. (wcd938x->pullup_ref[micb_index] == 0)) {
  1930. if (pre_off_event && wcd938x->mbhc)
  1931. blocking_notifier_call_chain(
  1932. &wcd938x->mbhc->notifier,
  1933. pre_off_event,
  1934. &wcd938x->mbhc->wcd_mbhc);
  1935. snd_soc_component_update_bits(component, micb_reg,
  1936. 0xC0, 0x00);
  1937. if (post_off_event && wcd938x->mbhc)
  1938. blocking_notifier_call_chain(
  1939. &wcd938x->mbhc->notifier,
  1940. post_off_event,
  1941. &wcd938x->mbhc->wcd_mbhc);
  1942. }
  1943. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1944. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1945. post_dapm_off,
  1946. &wcd938x->mbhc->wcd_mbhc);
  1947. break;
  1948. };
  1949. dev_dbg(component->dev,
  1950. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1951. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1952. wcd938x->pullup_ref[micb_index]);
  1953. done:
  1954. mutex_unlock(&wcd938x->micb_lock);
  1955. return ret;
  1956. }
  1957. EXPORT_SYMBOL(wcd938x_micbias_control);
  1958. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1959. {
  1960. int ret = 0;
  1961. uint8_t devnum = 0;
  1962. int num_retry = NUM_ATTEMPTS;
  1963. do {
  1964. /* retry after 1ms */
  1965. usleep_range(1000, 1010);
  1966. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1967. } while (ret && --num_retry);
  1968. if (ret)
  1969. dev_err(&swr_dev->dev,
  1970. "%s get devnum %d for dev addr %llx failed\n",
  1971. __func__, devnum, swr_dev->addr);
  1972. swr_dev->dev_num = devnum;
  1973. return 0;
  1974. }
  1975. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1976. struct wcd_mbhc_config *mbhc_cfg)
  1977. {
  1978. if (mbhc_cfg->enable_usbc_analog) {
  1979. if (!(snd_soc_component_read(component, WCD938X_ANA_MBHC_MECH)
  1980. & 0x20))
  1981. return true;
  1982. }
  1983. return false;
  1984. }
  1985. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  1986. struct notifier_block *nblock,
  1987. bool enable)
  1988. {
  1989. struct wcd938x_priv *wcd938x_priv;
  1990. if(NULL == component) {
  1991. pr_err("%s: wcd938x component is NULL\n", __func__);
  1992. return -EINVAL;
  1993. }
  1994. wcd938x_priv = snd_soc_component_get_drvdata(component);
  1995. wcd938x_priv->notify_swr_dmic = enable;
  1996. if (enable)
  1997. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  1998. nblock);
  1999. else
  2000. return blocking_notifier_chain_unregister(
  2001. &wcd938x_priv->notifier, nblock);
  2002. }
  2003. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  2004. static int wcd938x_event_notify(struct notifier_block *block,
  2005. unsigned long val,
  2006. void *data)
  2007. {
  2008. u16 event = (val & 0xffff);
  2009. int ret = 0;
  2010. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  2011. struct snd_soc_component *component = wcd938x->component;
  2012. struct wcd_mbhc *mbhc;
  2013. switch (event) {
  2014. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2015. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  2016. snd_soc_component_update_bits(component,
  2017. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  2018. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  2019. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  2020. }
  2021. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  2022. snd_soc_component_update_bits(component,
  2023. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  2024. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  2025. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  2026. }
  2027. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  2028. snd_soc_component_update_bits(component,
  2029. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  2030. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  2031. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  2032. }
  2033. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  2034. snd_soc_component_update_bits(component,
  2035. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  2036. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  2037. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  2038. }
  2039. break;
  2040. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2041. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  2042. 0xC0, 0x00);
  2043. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  2044. 0x80, 0x00);
  2045. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  2046. 0x80, 0x00);
  2047. break;
  2048. case BOLERO_SLV_EVT_SSR_DOWN:
  2049. wcd938x->dev_up = false;
  2050. if(wcd938x->notify_swr_dmic)
  2051. blocking_notifier_call_chain(&wcd938x->notifier,
  2052. WCD938X_EVT_SSR_DOWN,
  2053. NULL);
  2054. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2055. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2056. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  2057. mbhc->mbhc_cfg);
  2058. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  2059. wcd938x_reset_low(wcd938x->dev);
  2060. break;
  2061. case BOLERO_SLV_EVT_SSR_UP:
  2062. wcd938x_reset(wcd938x->dev);
  2063. /* allow reset to take effect */
  2064. usleep_range(10000, 10010);
  2065. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2066. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2067. wcd938x_init_reg(component);
  2068. regcache_mark_dirty(wcd938x->regmap);
  2069. regcache_sync(wcd938x->regmap);
  2070. /* Initialize MBHC module */
  2071. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2072. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2073. if (ret) {
  2074. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2075. __func__);
  2076. } else {
  2077. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2078. }
  2079. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2080. wcd938x->dev_up = true;
  2081. if(wcd938x->notify_swr_dmic)
  2082. blocking_notifier_call_chain(&wcd938x->notifier,
  2083. WCD938X_EVT_SSR_UP,
  2084. NULL);
  2085. if (wcd938x->usbc_hs_status)
  2086. mdelay(500);
  2087. break;
  2088. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2089. snd_soc_component_update_bits(component,
  2090. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2091. ((val >> 0x10) << 0x01));
  2092. break;
  2093. default:
  2094. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2095. break;
  2096. }
  2097. return 0;
  2098. }
  2099. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2100. int event)
  2101. {
  2102. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2103. int micb_num;
  2104. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2105. __func__, w->name, event);
  2106. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2107. micb_num = MIC_BIAS_1;
  2108. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2109. micb_num = MIC_BIAS_2;
  2110. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2111. micb_num = MIC_BIAS_3;
  2112. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2113. micb_num = MIC_BIAS_4;
  2114. else
  2115. return -EINVAL;
  2116. switch (event) {
  2117. case SND_SOC_DAPM_PRE_PMU:
  2118. wcd938x_micbias_control(component, micb_num,
  2119. MICB_ENABLE, true);
  2120. break;
  2121. case SND_SOC_DAPM_POST_PMU:
  2122. /* 1 msec delay as per HW requirement */
  2123. usleep_range(1000, 1100);
  2124. break;
  2125. case SND_SOC_DAPM_POST_PMD:
  2126. wcd938x_micbias_control(component, micb_num,
  2127. MICB_DISABLE, true);
  2128. break;
  2129. };
  2130. return 0;
  2131. }
  2132. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2133. struct snd_kcontrol *kcontrol,
  2134. int event)
  2135. {
  2136. return __wcd938x_codec_enable_micbias(w, event);
  2137. }
  2138. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2139. int event)
  2140. {
  2141. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2142. int micb_num;
  2143. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2144. __func__, w->name, event);
  2145. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2146. micb_num = MIC_BIAS_1;
  2147. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2148. micb_num = MIC_BIAS_2;
  2149. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2150. micb_num = MIC_BIAS_3;
  2151. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2152. micb_num = MIC_BIAS_4;
  2153. else
  2154. return -EINVAL;
  2155. switch (event) {
  2156. case SND_SOC_DAPM_PRE_PMU:
  2157. wcd938x_micbias_control(component, micb_num,
  2158. MICB_PULLUP_ENABLE, true);
  2159. break;
  2160. case SND_SOC_DAPM_POST_PMU:
  2161. /* 1 msec delay as per HW requirement */
  2162. usleep_range(1000, 1100);
  2163. break;
  2164. case SND_SOC_DAPM_POST_PMD:
  2165. wcd938x_micbias_control(component, micb_num,
  2166. MICB_PULLUP_DISABLE, true);
  2167. break;
  2168. };
  2169. return 0;
  2170. }
  2171. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2172. struct snd_kcontrol *kcontrol,
  2173. int event)
  2174. {
  2175. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2176. }
  2177. static int wcd938x_wakeup(void *handle, bool enable)
  2178. {
  2179. struct wcd938x_priv *priv;
  2180. int ret = 0;
  2181. if (!handle) {
  2182. pr_err("%s: NULL handle\n", __func__);
  2183. return -EINVAL;
  2184. }
  2185. priv = (struct wcd938x_priv *)handle;
  2186. if (!priv->tx_swr_dev) {
  2187. pr_err("%s: tx swr dev is NULL\n", __func__);
  2188. return -EINVAL;
  2189. }
  2190. mutex_lock(&priv->wakeup_lock);
  2191. if (enable)
  2192. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2193. else
  2194. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2195. mutex_unlock(&priv->wakeup_lock);
  2196. return ret;
  2197. }
  2198. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2199. struct snd_kcontrol *kcontrol,
  2200. int event)
  2201. {
  2202. int ret = 0;
  2203. struct snd_soc_component *component =
  2204. snd_soc_dapm_to_component(w->dapm);
  2205. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2206. switch (event) {
  2207. case SND_SOC_DAPM_PRE_PMU:
  2208. wcd938x_wakeup(wcd938x, true);
  2209. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2210. wcd938x_wakeup(wcd938x, false);
  2211. break;
  2212. case SND_SOC_DAPM_POST_PMD:
  2213. wcd938x_wakeup(wcd938x, true);
  2214. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2215. wcd938x_wakeup(wcd938x, false);
  2216. break;
  2217. }
  2218. return ret;
  2219. }
  2220. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2221. int micb_num, int req)
  2222. {
  2223. int micb_index = micb_num - 1;
  2224. u16 micb_reg;
  2225. if (NULL == wcd938x) {
  2226. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2227. return -EINVAL;
  2228. }
  2229. switch (micb_num) {
  2230. case MIC_BIAS_1:
  2231. micb_reg = WCD938X_ANA_MICB1;
  2232. break;
  2233. case MIC_BIAS_2:
  2234. micb_reg = WCD938X_ANA_MICB2;
  2235. break;
  2236. case MIC_BIAS_3:
  2237. micb_reg = WCD938X_ANA_MICB3;
  2238. break;
  2239. case MIC_BIAS_4:
  2240. micb_reg = WCD938X_ANA_MICB4;
  2241. break;
  2242. default:
  2243. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2244. return -EINVAL;
  2245. };
  2246. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2247. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2248. wcd938x->pullup_ref[micb_index]);
  2249. mutex_lock(&wcd938x->micb_lock);
  2250. switch (req) {
  2251. case MICB_ENABLE:
  2252. wcd938x->micb_ref[micb_index]++;
  2253. if (wcd938x->micb_ref[micb_index] == 1) {
  2254. regmap_update_bits(wcd938x->regmap,
  2255. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2256. regmap_update_bits(wcd938x->regmap,
  2257. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2258. regmap_update_bits(wcd938x->regmap,
  2259. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2260. regmap_update_bits(wcd938x->regmap,
  2261. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2262. regmap_update_bits(wcd938x->regmap,
  2263. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2264. regmap_update_bits(wcd938x->regmap,
  2265. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2266. regmap_update_bits(wcd938x->regmap,
  2267. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2268. regmap_update_bits(wcd938x->regmap,
  2269. micb_reg, 0xC0, 0x40);
  2270. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2271. }
  2272. break;
  2273. case MICB_PULLUP_ENABLE:
  2274. wcd938x->pullup_ref[micb_index]++;
  2275. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2276. (wcd938x->micb_ref[micb_index] == 0))
  2277. regmap_update_bits(wcd938x->regmap, micb_reg,
  2278. 0xC0, 0x80);
  2279. break;
  2280. case MICB_PULLUP_DISABLE:
  2281. if (wcd938x->pullup_ref[micb_index] > 0)
  2282. wcd938x->pullup_ref[micb_index]--;
  2283. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2284. (wcd938x->micb_ref[micb_index] == 0))
  2285. regmap_update_bits(wcd938x->regmap, micb_reg,
  2286. 0xC0, 0x00);
  2287. break;
  2288. case MICB_DISABLE:
  2289. if (wcd938x->micb_ref[micb_index] > 0)
  2290. wcd938x->micb_ref[micb_index]--;
  2291. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2292. (wcd938x->pullup_ref[micb_index] > 0))
  2293. regmap_update_bits(wcd938x->regmap, micb_reg,
  2294. 0xC0, 0x80);
  2295. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2296. (wcd938x->pullup_ref[micb_index] == 0))
  2297. regmap_update_bits(wcd938x->regmap, micb_reg,
  2298. 0xC0, 0x00);
  2299. break;
  2300. };
  2301. mutex_unlock(&wcd938x->micb_lock);
  2302. return 0;
  2303. }
  2304. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2305. int event, int micb_num)
  2306. {
  2307. struct wcd938x_priv *wcd938x_priv = NULL;
  2308. int ret = 0;
  2309. int micb_index = micb_num - 1;
  2310. if(NULL == component) {
  2311. pr_err("%s: wcd938x component is NULL\n", __func__);
  2312. return -EINVAL;
  2313. }
  2314. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2315. pr_err("%s: invalid event: %d\n", __func__, event);
  2316. return -EINVAL;
  2317. }
  2318. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2319. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2320. return -EINVAL;
  2321. }
  2322. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2323. if (!wcd938x_priv->dev_up) {
  2324. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2325. (event == SND_SOC_DAPM_POST_PMD)) {
  2326. wcd938x_priv->pullup_ref[micb_index]--;
  2327. ret = -ENODEV;
  2328. goto done;
  2329. }
  2330. }
  2331. switch (event) {
  2332. case SND_SOC_DAPM_PRE_PMU:
  2333. wcd938x_wakeup(wcd938x_priv, true);
  2334. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2335. wcd938x_wakeup(wcd938x_priv, false);
  2336. break;
  2337. case SND_SOC_DAPM_POST_PMD:
  2338. wcd938x_wakeup(wcd938x_priv, true);
  2339. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2340. wcd938x_wakeup(wcd938x_priv, false);
  2341. break;
  2342. }
  2343. done:
  2344. return ret;
  2345. }
  2346. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2347. static inline int wcd938x_tx_path_get(const char *wname,
  2348. unsigned int *path_num)
  2349. {
  2350. int ret = 0;
  2351. char *widget_name = NULL;
  2352. char *w_name = NULL;
  2353. char *path_num_char = NULL;
  2354. char *path_name = NULL;
  2355. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2356. if (!widget_name)
  2357. return -EINVAL;
  2358. w_name = widget_name;
  2359. path_name = strsep(&widget_name, " ");
  2360. if (!path_name) {
  2361. pr_err("%s: Invalid widget name = %s\n",
  2362. __func__, widget_name);
  2363. ret = -EINVAL;
  2364. goto err;
  2365. }
  2366. path_num_char = strpbrk(path_name, "0123");
  2367. if (!path_num_char) {
  2368. pr_err("%s: tx path index not found\n",
  2369. __func__);
  2370. ret = -EINVAL;
  2371. goto err;
  2372. }
  2373. ret = kstrtouint(path_num_char, 10, path_num);
  2374. if (ret < 0)
  2375. pr_err("%s: Invalid tx path = %s\n",
  2376. __func__, w_name);
  2377. err:
  2378. kfree(w_name);
  2379. return ret;
  2380. }
  2381. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2382. struct snd_ctl_elem_value *ucontrol)
  2383. {
  2384. struct snd_soc_component *component =
  2385. snd_soc_kcontrol_component(kcontrol);
  2386. struct wcd938x_priv *wcd938x = NULL;
  2387. int ret = 0;
  2388. unsigned int path = 0;
  2389. if (!component)
  2390. return -EINVAL;
  2391. wcd938x = snd_soc_component_get_drvdata(component);
  2392. if (!wcd938x)
  2393. return -EINVAL;
  2394. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2395. if (ret < 0)
  2396. return ret;
  2397. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2398. return 0;
  2399. }
  2400. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2401. struct snd_ctl_elem_value *ucontrol)
  2402. {
  2403. struct snd_soc_component *component =
  2404. snd_soc_kcontrol_component(kcontrol);
  2405. struct wcd938x_priv *wcd938x = NULL;
  2406. u32 mode_val;
  2407. unsigned int path = 0;
  2408. int ret = 0;
  2409. if (!component)
  2410. return -EINVAL;
  2411. wcd938x = snd_soc_component_get_drvdata(component);
  2412. if (!wcd938x)
  2413. return -EINVAL;
  2414. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2415. if (ret)
  2416. return ret;
  2417. mode_val = ucontrol->value.enumerated.item[0];
  2418. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2419. wcd938x->tx_mode[path] = mode_val;
  2420. return 0;
  2421. }
  2422. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2423. struct snd_ctl_elem_value *ucontrol)
  2424. {
  2425. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2426. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2427. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2428. return 0;
  2429. }
  2430. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2431. struct snd_ctl_elem_value *ucontrol)
  2432. {
  2433. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2434. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2435. u32 mode_val;
  2436. mode_val = ucontrol->value.enumerated.item[0];
  2437. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2438. if (wcd938x->variant == WCD9380) {
  2439. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2440. dev_info(component->dev,
  2441. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2442. __func__);
  2443. mode_val = CLS_H_ULP;
  2444. }
  2445. }
  2446. if (mode_val == CLS_H_NORMAL) {
  2447. dev_info(component->dev,
  2448. "%s:Invalid HPH Mode, default to class_AB\n",
  2449. __func__);
  2450. mode_val = CLS_H_ULP;
  2451. }
  2452. wcd938x->hph_mode = mode_val;
  2453. return 0;
  2454. }
  2455. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2456. struct snd_ctl_elem_value *ucontrol)
  2457. {
  2458. u8 ear_pa_gain = 0;
  2459. struct snd_soc_component *component =
  2460. snd_soc_kcontrol_component(kcontrol);
  2461. ear_pa_gain = snd_soc_component_read(component,
  2462. WCD938X_ANA_EAR_COMPANDER_CTL);
  2463. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2464. ucontrol->value.integer.value[0] = ear_pa_gain;
  2465. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2466. ear_pa_gain);
  2467. return 0;
  2468. }
  2469. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2470. struct snd_ctl_elem_value *ucontrol)
  2471. {
  2472. u8 ear_pa_gain = 0;
  2473. struct snd_soc_component *component =
  2474. snd_soc_kcontrol_component(kcontrol);
  2475. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2476. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2477. __func__, ucontrol->value.integer.value[0]);
  2478. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2479. if (!wcd938x->comp1_enable) {
  2480. snd_soc_component_update_bits(component,
  2481. WCD938X_ANA_EAR_COMPANDER_CTL,
  2482. 0x7C, ear_pa_gain);
  2483. }
  2484. return 0;
  2485. }
  2486. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2487. struct snd_ctl_elem_value *ucontrol)
  2488. {
  2489. struct snd_soc_component *component =
  2490. snd_soc_kcontrol_component(kcontrol);
  2491. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2492. bool hphr;
  2493. struct soc_multi_mixer_control *mc;
  2494. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2495. hphr = mc->shift;
  2496. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2497. wcd938x->comp1_enable;
  2498. return 0;
  2499. }
  2500. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2501. struct snd_ctl_elem_value *ucontrol)
  2502. {
  2503. struct snd_soc_component *component =
  2504. snd_soc_kcontrol_component(kcontrol);
  2505. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2506. int value = ucontrol->value.integer.value[0];
  2507. bool hphr;
  2508. struct soc_multi_mixer_control *mc;
  2509. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2510. hphr = mc->shift;
  2511. if (hphr)
  2512. wcd938x->comp2_enable = value;
  2513. else
  2514. wcd938x->comp1_enable = value;
  2515. return 0;
  2516. }
  2517. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2518. struct snd_kcontrol *kcontrol,
  2519. int event)
  2520. {
  2521. struct snd_soc_component *component =
  2522. snd_soc_dapm_to_component(w->dapm);
  2523. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2524. struct wcd938x_pdata *pdata = NULL;
  2525. int ret = 0;
  2526. pdata = dev_get_platdata(wcd938x->dev);
  2527. if (!pdata) {
  2528. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2529. return -EINVAL;
  2530. }
  2531. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2532. wcd938x->supplies,
  2533. pdata->regulator,
  2534. pdata->num_supplies,
  2535. "cdc-vdd-buck"))
  2536. return 0;
  2537. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2538. w->name, event);
  2539. switch (event) {
  2540. case SND_SOC_DAPM_PRE_PMU:
  2541. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2542. dev_dbg(component->dev,
  2543. "%s: buck already in enabled state\n",
  2544. __func__);
  2545. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2546. return 0;
  2547. }
  2548. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2549. wcd938x->supplies,
  2550. pdata->regulator,
  2551. pdata->num_supplies,
  2552. "cdc-vdd-buck");
  2553. if (ret == -EINVAL) {
  2554. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2555. __func__);
  2556. return ret;
  2557. }
  2558. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2559. /*
  2560. * 200us sleep is required after LDO is enabled as per
  2561. * HW requirement
  2562. */
  2563. usleep_range(200, 250);
  2564. break;
  2565. case SND_SOC_DAPM_POST_PMD:
  2566. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2567. break;
  2568. }
  2569. return 0;
  2570. }
  2571. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2572. struct snd_ctl_elem_value *ucontrol)
  2573. {
  2574. struct snd_soc_component *component =
  2575. snd_soc_kcontrol_component(kcontrol);
  2576. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2577. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2578. return 0;
  2579. }
  2580. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2581. struct snd_ctl_elem_value *ucontrol)
  2582. {
  2583. struct snd_soc_component *component =
  2584. snd_soc_kcontrol_component(kcontrol);
  2585. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2586. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2587. return 0;
  2588. }
  2589. const char * const tx_master_ch_text[] = {
  2590. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2591. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2592. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2593. "SWRM_PCM_IN",
  2594. };
  2595. const struct soc_enum tx_master_ch_enum =
  2596. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2597. tx_master_ch_text);
  2598. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2599. {
  2600. u8 ch_type = 0;
  2601. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2602. ch_type = ADC1;
  2603. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2604. ch_type = ADC2;
  2605. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2606. ch_type = ADC3;
  2607. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2608. ch_type = ADC4;
  2609. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2610. ch_type = DMIC0;
  2611. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2612. ch_type = DMIC1;
  2613. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2614. ch_type = MBHC;
  2615. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2616. ch_type = DMIC2;
  2617. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2618. ch_type = DMIC3;
  2619. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2620. ch_type = DMIC4;
  2621. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2622. ch_type = DMIC5;
  2623. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2624. ch_type = DMIC6;
  2625. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2626. ch_type = DMIC7;
  2627. else
  2628. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2629. if (ch_type)
  2630. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2631. else
  2632. *ch_idx = -EINVAL;
  2633. }
  2634. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2635. struct snd_ctl_elem_value *ucontrol)
  2636. {
  2637. struct snd_soc_component *component =
  2638. snd_soc_kcontrol_component(kcontrol);
  2639. struct wcd938x_priv *wcd938x = NULL;
  2640. int slave_ch_idx = -EINVAL;
  2641. if (component == NULL)
  2642. return -EINVAL;
  2643. wcd938x = snd_soc_component_get_drvdata(component);
  2644. if (wcd938x == NULL)
  2645. return -EINVAL;
  2646. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2647. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2648. return -EINVAL;
  2649. ucontrol->value.integer.value[0] = wcd938x_slave_get_master_ch_val(
  2650. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2651. return 0;
  2652. }
  2653. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2654. struct snd_ctl_elem_value *ucontrol)
  2655. {
  2656. struct snd_soc_component *component =
  2657. snd_soc_kcontrol_component(kcontrol);
  2658. struct wcd938x_priv *wcd938x = NULL;
  2659. int slave_ch_idx = -EINVAL;
  2660. if (component == NULL)
  2661. return -EINVAL;
  2662. wcd938x = snd_soc_component_get_drvdata(component);
  2663. if (wcd938x == NULL)
  2664. return -EINVAL;
  2665. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2666. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2667. return -EINVAL;
  2668. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2669. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2670. __func__, ucontrol->value.enumerated.item[0]);
  2671. wcd938x->tx_master_ch_map[slave_ch_idx] = wcd938x_slave_get_master_ch(
  2672. ucontrol->value.enumerated.item[0]);
  2673. return 0;
  2674. }
  2675. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2676. struct snd_ctl_elem_value *ucontrol)
  2677. {
  2678. struct snd_soc_component *component =
  2679. snd_soc_kcontrol_component(kcontrol);
  2680. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2681. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2682. return 0;
  2683. }
  2684. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2685. struct snd_ctl_elem_value *ucontrol)
  2686. {
  2687. struct snd_soc_component *component =
  2688. snd_soc_kcontrol_component(kcontrol);
  2689. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2690. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2691. return 0;
  2692. }
  2693. static const char * const tx_mode_mux_text_wcd9380[] = {
  2694. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2695. };
  2696. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2697. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2698. tx_mode_mux_text_wcd9380);
  2699. static const char * const tx_mode_mux_text[] = {
  2700. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2701. "ADC_ULP1", "ADC_ULP2",
  2702. };
  2703. static const struct soc_enum tx_mode_mux_enum =
  2704. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2705. tx_mode_mux_text);
  2706. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2707. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2708. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2709. "CLS_AB_LOHIFI",
  2710. };
  2711. static const char * const wcd938x_ear_pa_gain_text[] = {
  2712. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2713. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2714. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2715. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2716. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2717. };
  2718. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2719. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2720. rx_hph_mode_mux_text_wcd9380);
  2721. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2722. wcd938x_ear_pa_gain_text);
  2723. static const char * const rx_hph_mode_mux_text[] = {
  2724. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2725. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2726. };
  2727. static const struct soc_enum rx_hph_mode_mux_enum =
  2728. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2729. rx_hph_mode_mux_text);
  2730. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2731. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2732. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2733. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2734. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2735. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2736. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2737. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2738. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2739. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2740. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2741. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2742. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2743. };
  2744. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2745. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2746. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2747. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2748. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2749. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2750. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2751. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2752. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2753. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2754. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2755. };
  2756. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2757. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2758. wcd938x_get_compander, wcd938x_set_compander),
  2759. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2760. wcd938x_get_compander, wcd938x_set_compander),
  2761. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2762. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2763. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2764. wcd938x_bcs_get, wcd938x_bcs_put),
  2765. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2766. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2767. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2768. analog_gain),
  2769. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2770. analog_gain),
  2771. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2772. analog_gain),
  2773. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2774. analog_gain),
  2775. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2776. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2777. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2778. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2779. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2780. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2781. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2782. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2783. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2784. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2785. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2786. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2787. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2788. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2789. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2790. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2791. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2792. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2793. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2794. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2795. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2796. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2797. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2798. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2799. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2800. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2801. };
  2802. static const struct snd_kcontrol_new adc1_switch[] = {
  2803. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2804. };
  2805. static const struct snd_kcontrol_new adc2_switch[] = {
  2806. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2807. };
  2808. static const struct snd_kcontrol_new adc3_switch[] = {
  2809. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2810. };
  2811. static const struct snd_kcontrol_new adc4_switch[] = {
  2812. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2813. };
  2814. static const struct snd_kcontrol_new amic1_switch[] = {
  2815. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2816. };
  2817. static const struct snd_kcontrol_new amic2_switch[] = {
  2818. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2819. };
  2820. static const struct snd_kcontrol_new amic3_switch[] = {
  2821. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2822. };
  2823. static const struct snd_kcontrol_new amic4_switch[] = {
  2824. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2825. };
  2826. static const struct snd_kcontrol_new amic5_switch[] = {
  2827. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2828. };
  2829. static const struct snd_kcontrol_new amic6_switch[] = {
  2830. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2831. };
  2832. static const struct snd_kcontrol_new amic7_switch[] = {
  2833. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2834. };
  2835. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2836. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2837. };
  2838. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2839. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2840. };
  2841. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2842. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2843. };
  2844. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2845. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2846. };
  2847. static const struct snd_kcontrol_new va_amic5_switch[] = {
  2848. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2849. };
  2850. static const struct snd_kcontrol_new va_amic6_switch[] = {
  2851. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2852. };
  2853. static const struct snd_kcontrol_new va_amic7_switch[] = {
  2854. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2855. };
  2856. static const struct snd_kcontrol_new dmic1_switch[] = {
  2857. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2858. };
  2859. static const struct snd_kcontrol_new dmic2_switch[] = {
  2860. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2861. };
  2862. static const struct snd_kcontrol_new dmic3_switch[] = {
  2863. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2864. };
  2865. static const struct snd_kcontrol_new dmic4_switch[] = {
  2866. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2867. };
  2868. static const struct snd_kcontrol_new dmic5_switch[] = {
  2869. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2870. };
  2871. static const struct snd_kcontrol_new dmic6_switch[] = {
  2872. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2873. };
  2874. static const struct snd_kcontrol_new dmic7_switch[] = {
  2875. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2876. };
  2877. static const struct snd_kcontrol_new dmic8_switch[] = {
  2878. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2879. };
  2880. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2881. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2882. };
  2883. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2884. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2885. };
  2886. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2887. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2888. };
  2889. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2890. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2891. };
  2892. static const char * const adc2_mux_text[] = {
  2893. "INP2", "INP3"
  2894. };
  2895. static const struct soc_enum adc2_enum =
  2896. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2897. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2898. static const struct snd_kcontrol_new tx_adc2_mux =
  2899. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2900. static const char * const adc3_mux_text[] = {
  2901. "INP4", "INP6"
  2902. };
  2903. static const struct soc_enum adc3_enum =
  2904. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2905. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2906. static const struct snd_kcontrol_new tx_adc3_mux =
  2907. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2908. static const char * const adc4_mux_text[] = {
  2909. "INP5", "INP7"
  2910. };
  2911. static const struct soc_enum adc4_enum =
  2912. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2913. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2914. static const struct snd_kcontrol_new tx_adc4_mux =
  2915. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2916. static const char * const rdac3_mux_text[] = {
  2917. "RX1", "RX3"
  2918. };
  2919. static const char * const hdr12_mux_text[] = {
  2920. "NO_HDR12", "HDR12"
  2921. };
  2922. static const struct soc_enum hdr12_enum =
  2923. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2924. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2925. static const struct snd_kcontrol_new tx_hdr12_mux =
  2926. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2927. static const char * const hdr34_mux_text[] = {
  2928. "NO_HDR34", "HDR34"
  2929. };
  2930. static const struct soc_enum hdr34_enum =
  2931. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2932. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2933. static const struct snd_kcontrol_new tx_hdr34_mux =
  2934. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2935. static const struct soc_enum rdac3_enum =
  2936. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2937. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2938. static const struct snd_kcontrol_new rx_rdac3_mux =
  2939. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2940. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2941. /*input widgets*/
  2942. SND_SOC_DAPM_INPUT("AMIC1"),
  2943. SND_SOC_DAPM_INPUT("AMIC2"),
  2944. SND_SOC_DAPM_INPUT("AMIC3"),
  2945. SND_SOC_DAPM_INPUT("AMIC4"),
  2946. SND_SOC_DAPM_INPUT("AMIC5"),
  2947. SND_SOC_DAPM_INPUT("AMIC6"),
  2948. SND_SOC_DAPM_INPUT("AMIC7"),
  2949. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2950. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2951. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2952. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2953. SND_SOC_DAPM_INPUT("VA AMIC5"),
  2954. SND_SOC_DAPM_INPUT("VA AMIC6"),
  2955. SND_SOC_DAPM_INPUT("VA AMIC7"),
  2956. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2957. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2958. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2959. /*
  2960. * These dummy widgets are null connected to WCD938x dapm input and
  2961. * output widgets which are not actual path endpoints. This ensures
  2962. * dapm doesnt set these dapm input and output widgets as endpoints.
  2963. */
  2964. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2965. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2966. /*tx widgets*/
  2967. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2968. wcd938x_codec_enable_adc,
  2969. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2970. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2971. wcd938x_codec_enable_adc,
  2972. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2973. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2974. wcd938x_codec_enable_adc,
  2975. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2976. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2977. wcd938x_codec_enable_adc,
  2978. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2979. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2980. wcd938x_codec_enable_dmic,
  2981. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2982. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2983. wcd938x_codec_enable_dmic,
  2984. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2985. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2986. wcd938x_codec_enable_dmic,
  2987. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2988. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2989. wcd938x_codec_enable_dmic,
  2990. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2991. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2992. wcd938x_codec_enable_dmic,
  2993. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2994. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2995. wcd938x_codec_enable_dmic,
  2996. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2997. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2998. wcd938x_codec_enable_dmic,
  2999. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3000. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3001. wcd938x_codec_enable_dmic,
  3002. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3003. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3004. NULL, 0, wcd938x_enable_req,
  3005. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3006. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3007. NULL, 0, wcd938x_enable_req,
  3008. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3009. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3010. NULL, 0, wcd938x_enable_req,
  3011. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3012. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3013. NULL, 0, wcd938x_enable_req,
  3014. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3015. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3016. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3017. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3018. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3019. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3020. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3021. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3022. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3023. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3024. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3025. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3026. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3027. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3028. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3029. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3030. SND_SOC_DAPM_MIXER_E("AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3031. amic6_switch, ARRAY_SIZE(amic6_switch), NULL,
  3032. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3033. SND_SOC_DAPM_MIXER_E("AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3034. amic7_switch, ARRAY_SIZE(amic7_switch), NULL,
  3035. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3036. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3037. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3038. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3039. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3040. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3041. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3042. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3043. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3044. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3045. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3046. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3047. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3048. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3049. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3050. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3051. SND_SOC_DAPM_MIXER_E("VA_AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3052. va_amic6_switch, ARRAY_SIZE(va_amic6_switch), NULL,
  3053. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3054. SND_SOC_DAPM_MIXER_E("VA_AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3055. va_amic7_switch, ARRAY_SIZE(va_amic7_switch), NULL,
  3056. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3057. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3058. &tx_adc2_mux),
  3059. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3060. &tx_adc3_mux),
  3061. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3062. &tx_adc4_mux),
  3063. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  3064. &tx_hdr12_mux),
  3065. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  3066. &tx_hdr34_mux),
  3067. /*tx mixers*/
  3068. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3069. adc1_switch, ARRAY_SIZE(adc1_switch),
  3070. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3071. SND_SOC_DAPM_POST_PMD),
  3072. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3073. adc2_switch, ARRAY_SIZE(adc2_switch),
  3074. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3075. SND_SOC_DAPM_POST_PMD),
  3076. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3077. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  3078. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3079. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3080. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  3081. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3082. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3083. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3084. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3085. SND_SOC_DAPM_POST_PMD),
  3086. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3087. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3088. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3089. SND_SOC_DAPM_POST_PMD),
  3090. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3091. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3092. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3093. SND_SOC_DAPM_POST_PMD),
  3094. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3095. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3096. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3097. SND_SOC_DAPM_POST_PMD),
  3098. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3099. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3100. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3101. SND_SOC_DAPM_POST_PMD),
  3102. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3103. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3104. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3105. SND_SOC_DAPM_POST_PMD),
  3106. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3107. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3108. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3109. SND_SOC_DAPM_POST_PMD),
  3110. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3111. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3112. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3113. SND_SOC_DAPM_POST_PMD),
  3114. /* micbias widgets*/
  3115. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3116. wcd938x_codec_enable_micbias,
  3117. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3118. SND_SOC_DAPM_POST_PMD),
  3119. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3120. wcd938x_codec_enable_micbias,
  3121. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3122. SND_SOC_DAPM_POST_PMD),
  3123. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3124. wcd938x_codec_enable_micbias,
  3125. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3126. SND_SOC_DAPM_POST_PMD),
  3127. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3128. wcd938x_codec_enable_micbias,
  3129. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3130. SND_SOC_DAPM_POST_PMD),
  3131. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3132. wcd938x_codec_force_enable_micbias,
  3133. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3134. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3135. wcd938x_codec_force_enable_micbias,
  3136. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3137. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3138. wcd938x_codec_force_enable_micbias,
  3139. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3140. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3141. wcd938x_codec_force_enable_micbias,
  3142. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3143. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3144. wcd938x_codec_enable_vdd_buck,
  3145. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3146. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3147. wcd938x_enable_clsh,
  3148. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3149. /*rx widgets*/
  3150. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  3151. wcd938x_codec_enable_ear_pa,
  3152. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3153. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3154. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  3155. wcd938x_codec_enable_aux_pa,
  3156. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3157. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3158. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  3159. wcd938x_codec_enable_hphl_pa,
  3160. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3161. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3162. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  3163. wcd938x_codec_enable_hphr_pa,
  3164. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3165. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3166. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3167. wcd938x_codec_hphl_dac_event,
  3168. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3169. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3170. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3171. wcd938x_codec_hphr_dac_event,
  3172. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3173. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3174. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3175. wcd938x_codec_ear_dac_event,
  3176. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3177. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3178. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3179. wcd938x_codec_aux_dac_event,
  3180. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3181. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3182. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3183. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3184. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3185. SND_SOC_DAPM_POST_PMD),
  3186. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3187. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3188. SND_SOC_DAPM_POST_PMD),
  3189. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3190. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3191. SND_SOC_DAPM_POST_PMD),
  3192. /* rx mixer widgets*/
  3193. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3194. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3195. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3196. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3197. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3198. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3199. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3200. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3201. /*output widgets tx*/
  3202. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3203. /*output widgets rx*/
  3204. SND_SOC_DAPM_OUTPUT("EAR"),
  3205. SND_SOC_DAPM_OUTPUT("AUX"),
  3206. SND_SOC_DAPM_OUTPUT("HPHL"),
  3207. SND_SOC_DAPM_OUTPUT("HPHR"),
  3208. /* micbias pull up widgets*/
  3209. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3210. wcd938x_codec_enable_micbias_pullup,
  3211. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3212. SND_SOC_DAPM_POST_PMD),
  3213. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3214. wcd938x_codec_enable_micbias_pullup,
  3215. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3216. SND_SOC_DAPM_POST_PMD),
  3217. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3218. wcd938x_codec_enable_micbias_pullup,
  3219. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3220. SND_SOC_DAPM_POST_PMD),
  3221. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3222. wcd938x_codec_enable_micbias_pullup,
  3223. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3224. SND_SOC_DAPM_POST_PMD),
  3225. };
  3226. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3227. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3228. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3229. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3230. {"ADC1 REQ", NULL, "ADC1"},
  3231. {"ADC1", NULL, "AMIC1_MIXER"},
  3232. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3233. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3234. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3235. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3236. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3237. {"ADC2 REQ", NULL, "ADC2"},
  3238. {"ADC2", NULL, "HDR12 MUX"},
  3239. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3240. {"HDR12 MUX", "HDR12", "AMIC1_MIXER"},
  3241. {"ADC2 MUX", "INP3", "AMIC3_MIXER"},
  3242. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3243. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3244. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3245. {"ADC2 MUX", "INP2", "AMIC2_MIXER"},
  3246. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3247. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3248. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3249. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3250. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3251. {"ADC3 REQ", NULL, "ADC3"},
  3252. {"ADC3", NULL, "HDR34 MUX"},
  3253. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3254. {"HDR34 MUX", "HDR34", "AMIC5_MIXER"},
  3255. {"ADC3 MUX", "INP4", "AMIC4_MIXER"},
  3256. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3257. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3258. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3259. {"ADC3 MUX", "INP6", "AMIC6_MIXER"},
  3260. {"AMIC6_MIXER", "Switch", "AMIC6"},
  3261. {"AMIC6_MIXER", NULL, "VA_AMIC6_MIXER"},
  3262. {"VA_AMIC6_MIXER", "Switch", "VA AMIC6"},
  3263. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3264. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3265. {"ADC4 REQ", NULL, "ADC4"},
  3266. {"ADC4", NULL, "ADC4 MUX"},
  3267. {"ADC4 MUX", "INP5", "AMIC5_MIXER"},
  3268. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3269. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3270. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3271. {"ADC4 MUX", "INP7", "AMIC7_MIXER"},
  3272. {"AMIC7_MIXER", "Switch", "AMIC7"},
  3273. {"AMIC7_MIXER", NULL, "VA_AMIC7_MIXER"},
  3274. {"VA_AMIC7_MIXER", "Switch", "VA AMIC7"},
  3275. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3276. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3277. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3278. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3279. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3280. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3281. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3282. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3283. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3284. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3285. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3286. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3287. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3288. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3289. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3290. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3291. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3292. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3293. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3294. {"RX1", NULL, "IN1_HPHL"},
  3295. {"RDAC1", NULL, "RX1"},
  3296. {"HPHL_RDAC", "Switch", "RDAC1"},
  3297. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3298. {"HPHL", NULL, "HPHL PGA"},
  3299. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3300. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3301. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3302. {"RX2", NULL, "IN2_HPHR"},
  3303. {"RDAC2", NULL, "RX2"},
  3304. {"HPHR_RDAC", "Switch", "RDAC2"},
  3305. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3306. {"HPHR", NULL, "HPHR PGA"},
  3307. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3308. {"IN3_AUX", NULL, "VDD_BUCK"},
  3309. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3310. {"RX3", NULL, "IN3_AUX"},
  3311. {"RDAC4", NULL, "RX3"},
  3312. {"AUX_RDAC", "Switch", "RDAC4"},
  3313. {"AUX PGA", NULL, "AUX_RDAC"},
  3314. {"AUX", NULL, "AUX PGA"},
  3315. {"RDAC3_MUX", "RX3", "RX3"},
  3316. {"RDAC3_MUX", "RX1", "RX1"},
  3317. {"RDAC3", NULL, "RDAC3_MUX"},
  3318. {"EAR_RDAC", "Switch", "RDAC3"},
  3319. {"EAR PGA", NULL, "EAR_RDAC"},
  3320. {"EAR", NULL, "EAR PGA"},
  3321. };
  3322. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3323. void *file_private_data,
  3324. struct file *file,
  3325. char __user *buf, size_t count,
  3326. loff_t pos)
  3327. {
  3328. struct wcd938x_priv *priv;
  3329. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3330. int len = 0;
  3331. priv = (struct wcd938x_priv *) entry->private_data;
  3332. if (!priv) {
  3333. pr_err("%s: wcd938x priv is null\n", __func__);
  3334. return -EINVAL;
  3335. }
  3336. switch (priv->version) {
  3337. case WCD938X_VERSION_1_0:
  3338. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3339. break;
  3340. default:
  3341. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3342. }
  3343. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3344. }
  3345. static struct snd_info_entry_ops wcd938x_info_ops = {
  3346. .read = wcd938x_version_read,
  3347. };
  3348. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3349. void *file_private_data,
  3350. struct file *file,
  3351. char __user *buf, size_t count,
  3352. loff_t pos)
  3353. {
  3354. struct wcd938x_priv *priv;
  3355. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3356. int len = 0;
  3357. priv = (struct wcd938x_priv *) entry->private_data;
  3358. if (!priv) {
  3359. pr_err("%s: wcd938x priv is null\n", __func__);
  3360. return -EINVAL;
  3361. }
  3362. switch (priv->variant) {
  3363. case WCD9380:
  3364. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3365. break;
  3366. case WCD9385:
  3367. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3368. break;
  3369. default:
  3370. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3371. }
  3372. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3373. }
  3374. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3375. .read = wcd938x_variant_read,
  3376. };
  3377. /*
  3378. * wcd938x_get_codec_variant
  3379. * @component: component instance
  3380. *
  3381. * Return: codec variant or -EINVAL in error.
  3382. */
  3383. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3384. {
  3385. struct wcd938x_priv *priv = NULL;
  3386. if (!component)
  3387. return -EINVAL;
  3388. priv = snd_soc_component_get_drvdata(component);
  3389. if (!priv) {
  3390. dev_err(component->dev,
  3391. "%s:wcd938x not probed\n", __func__);
  3392. return 0;
  3393. }
  3394. return priv->variant;
  3395. }
  3396. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3397. /*
  3398. * wcd938x_info_create_codec_entry - creates wcd938x module
  3399. * @codec_root: The parent directory
  3400. * @component: component instance
  3401. *
  3402. * Creates wcd938x module, variant and version entry under the given
  3403. * parent directory.
  3404. *
  3405. * Return: 0 on success or negative error code on failure.
  3406. */
  3407. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3408. struct snd_soc_component *component)
  3409. {
  3410. struct snd_info_entry *version_entry;
  3411. struct snd_info_entry *variant_entry;
  3412. struct wcd938x_priv *priv;
  3413. struct snd_soc_card *card;
  3414. if (!codec_root || !component)
  3415. return -EINVAL;
  3416. priv = snd_soc_component_get_drvdata(component);
  3417. if (priv->entry) {
  3418. dev_dbg(priv->dev,
  3419. "%s:wcd938x module already created\n", __func__);
  3420. return 0;
  3421. }
  3422. card = component->card;
  3423. priv->entry = snd_info_create_module_entry(codec_root->module,
  3424. "wcd938x", codec_root);
  3425. if (!priv->entry) {
  3426. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3427. __func__);
  3428. return -ENOMEM;
  3429. }
  3430. priv->entry->mode = S_IFDIR | 0555;
  3431. if (snd_info_register(priv->entry) < 0) {
  3432. snd_info_free_entry(priv->entry);
  3433. return -ENOMEM;
  3434. }
  3435. version_entry = snd_info_create_card_entry(card->snd_card,
  3436. "version",
  3437. priv->entry);
  3438. if (!version_entry) {
  3439. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3440. __func__);
  3441. snd_info_free_entry(priv->entry);
  3442. return -ENOMEM;
  3443. }
  3444. version_entry->private_data = priv;
  3445. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3446. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3447. version_entry->c.ops = &wcd938x_info_ops;
  3448. if (snd_info_register(version_entry) < 0) {
  3449. snd_info_free_entry(version_entry);
  3450. snd_info_free_entry(priv->entry);
  3451. return -ENOMEM;
  3452. }
  3453. priv->version_entry = version_entry;
  3454. variant_entry = snd_info_create_card_entry(card->snd_card,
  3455. "variant",
  3456. priv->entry);
  3457. if (!variant_entry) {
  3458. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3459. __func__);
  3460. snd_info_free_entry(version_entry);
  3461. snd_info_free_entry(priv->entry);
  3462. return -ENOMEM;
  3463. }
  3464. variant_entry->private_data = priv;
  3465. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3466. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3467. variant_entry->c.ops = &wcd938x_variant_ops;
  3468. if (snd_info_register(variant_entry) < 0) {
  3469. snd_info_free_entry(variant_entry);
  3470. snd_info_free_entry(version_entry);
  3471. snd_info_free_entry(priv->entry);
  3472. return -ENOMEM;
  3473. }
  3474. priv->variant_entry = variant_entry;
  3475. return 0;
  3476. }
  3477. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3478. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3479. struct wcd938x_pdata *pdata)
  3480. {
  3481. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3482. int rc = 0;
  3483. if (!pdata) {
  3484. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3485. return -ENODEV;
  3486. }
  3487. /* set micbias voltage */
  3488. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3489. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3490. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3491. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3492. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3493. vout_ctl_4 < 0) {
  3494. rc = -EINVAL;
  3495. goto done;
  3496. }
  3497. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3498. vout_ctl_1);
  3499. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3500. vout_ctl_2);
  3501. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3502. vout_ctl_3);
  3503. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3504. vout_ctl_4);
  3505. done:
  3506. return rc;
  3507. }
  3508. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3509. {
  3510. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3511. struct snd_soc_dapm_context *dapm =
  3512. snd_soc_component_get_dapm(component);
  3513. int variant;
  3514. int ret = -EINVAL;
  3515. dev_info(component->dev, "%s()\n", __func__);
  3516. wcd938x = snd_soc_component_get_drvdata(component);
  3517. if (!wcd938x)
  3518. return -EINVAL;
  3519. wcd938x->component = component;
  3520. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3521. variant = (snd_soc_component_read(component,
  3522. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3523. wcd938x->variant = variant;
  3524. wcd938x->fw_data = devm_kzalloc(component->dev,
  3525. sizeof(*(wcd938x->fw_data)),
  3526. GFP_KERNEL);
  3527. if (!wcd938x->fw_data) {
  3528. dev_err(component->dev, "Failed to allocate fw_data\n");
  3529. ret = -ENOMEM;
  3530. goto err;
  3531. }
  3532. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3533. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3534. WCD9XXX_CODEC_HWDEP_NODE, component);
  3535. if (ret < 0) {
  3536. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3537. goto err_hwdep;
  3538. }
  3539. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3540. if (ret) {
  3541. pr_err("%s: mbhc initialization failed\n", __func__);
  3542. goto err_hwdep;
  3543. }
  3544. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3545. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3546. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3547. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3548. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3549. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3550. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3551. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3552. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3553. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3554. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3555. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3556. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3557. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3558. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC6");
  3559. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC7");
  3560. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3561. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3562. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3563. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3564. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3565. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3566. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3567. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3568. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3569. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3570. snd_soc_dapm_sync(dapm);
  3571. wcd_cls_h_init(&wcd938x->clsh_info);
  3572. wcd938x_init_reg(component);
  3573. if (wcd938x->variant == WCD9380) {
  3574. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3575. ARRAY_SIZE(wcd9380_snd_controls));
  3576. if (ret < 0) {
  3577. dev_err(component->dev,
  3578. "%s: Failed to add snd ctrls for variant: %d\n",
  3579. __func__, wcd938x->variant);
  3580. goto err_hwdep;
  3581. }
  3582. }
  3583. if (wcd938x->variant == WCD9385) {
  3584. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3585. ARRAY_SIZE(wcd9385_snd_controls));
  3586. if (ret < 0) {
  3587. dev_err(component->dev,
  3588. "%s: Failed to add snd ctrls for variant: %d\n",
  3589. __func__, wcd938x->variant);
  3590. goto err_hwdep;
  3591. }
  3592. }
  3593. wcd938x->version = WCD938X_VERSION_1_0;
  3594. /* Register event notifier */
  3595. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3596. if (wcd938x->register_notifier) {
  3597. ret = wcd938x->register_notifier(wcd938x->handle,
  3598. &wcd938x->nblock,
  3599. true);
  3600. if (ret) {
  3601. dev_err(component->dev,
  3602. "%s: Failed to register notifier %d\n",
  3603. __func__, ret);
  3604. return ret;
  3605. }
  3606. }
  3607. return ret;
  3608. err_hwdep:
  3609. wcd938x->fw_data = NULL;
  3610. err:
  3611. return ret;
  3612. }
  3613. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3614. {
  3615. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3616. if (!wcd938x) {
  3617. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3618. __func__);
  3619. return;
  3620. }
  3621. if (wcd938x->register_notifier)
  3622. wcd938x->register_notifier(wcd938x->handle,
  3623. &wcd938x->nblock,
  3624. false);
  3625. }
  3626. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3627. {
  3628. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3629. if (!wcd938x)
  3630. return 0;
  3631. wcd938x->dapm_bias_off = true;
  3632. return 0;
  3633. }
  3634. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3635. {
  3636. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3637. if (!wcd938x)
  3638. return 0;
  3639. wcd938x->dapm_bias_off = false;
  3640. return 0;
  3641. }
  3642. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3643. .name = WCD938X_DRV_NAME,
  3644. .probe = wcd938x_soc_codec_probe,
  3645. .remove = wcd938x_soc_codec_remove,
  3646. .controls = wcd938x_snd_controls,
  3647. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3648. .dapm_widgets = wcd938x_dapm_widgets,
  3649. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3650. .dapm_routes = wcd938x_audio_map,
  3651. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3652. .suspend = wcd938x_soc_codec_suspend,
  3653. .resume = wcd938x_soc_codec_resume,
  3654. };
  3655. static int wcd938x_reset(struct device *dev)
  3656. {
  3657. struct wcd938x_priv *wcd938x = NULL;
  3658. int rc = 0;
  3659. int value = 0;
  3660. if (!dev)
  3661. return -ENODEV;
  3662. wcd938x = dev_get_drvdata(dev);
  3663. if (!wcd938x)
  3664. return -EINVAL;
  3665. if (!wcd938x->rst_np) {
  3666. dev_err(dev, "%s: reset gpio device node not specified\n",
  3667. __func__);
  3668. return -EINVAL;
  3669. }
  3670. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3671. if (value > 0)
  3672. return 0;
  3673. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3674. if (rc) {
  3675. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3676. __func__);
  3677. return rc;
  3678. }
  3679. /* 20us sleep required after pulling the reset gpio to LOW */
  3680. usleep_range(20, 30);
  3681. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3682. if (rc) {
  3683. dev_err(dev, "%s: wcd active state request fail!\n",
  3684. __func__);
  3685. return rc;
  3686. }
  3687. /* 20us sleep required after pulling the reset gpio to HIGH */
  3688. usleep_range(20, 30);
  3689. return rc;
  3690. }
  3691. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3692. u32 *val)
  3693. {
  3694. int rc = 0;
  3695. rc = of_property_read_u32(dev->of_node, name, val);
  3696. if (rc)
  3697. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3698. __func__, name, dev->of_node->full_name);
  3699. return rc;
  3700. }
  3701. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3702. struct wcd938x_micbias_setting *mb)
  3703. {
  3704. u32 prop_val = 0;
  3705. int rc = 0;
  3706. /* MB1 */
  3707. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3708. NULL)) {
  3709. rc = wcd938x_read_of_property_u32(dev,
  3710. "qcom,cdc-micbias1-mv",
  3711. &prop_val);
  3712. if (!rc)
  3713. mb->micb1_mv = prop_val;
  3714. } else {
  3715. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3716. __func__);
  3717. }
  3718. /* MB2 */
  3719. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3720. NULL)) {
  3721. rc = wcd938x_read_of_property_u32(dev,
  3722. "qcom,cdc-micbias2-mv",
  3723. &prop_val);
  3724. if (!rc)
  3725. mb->micb2_mv = prop_val;
  3726. } else {
  3727. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3728. __func__);
  3729. }
  3730. /* MB3 */
  3731. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3732. NULL)) {
  3733. rc = wcd938x_read_of_property_u32(dev,
  3734. "qcom,cdc-micbias3-mv",
  3735. &prop_val);
  3736. if (!rc)
  3737. mb->micb3_mv = prop_val;
  3738. } else {
  3739. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3740. __func__);
  3741. }
  3742. /* MB4 */
  3743. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3744. NULL)) {
  3745. rc = wcd938x_read_of_property_u32(dev,
  3746. "qcom,cdc-micbias4-mv",
  3747. &prop_val);
  3748. if (!rc)
  3749. mb->micb4_mv = prop_val;
  3750. } else {
  3751. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3752. __func__);
  3753. }
  3754. }
  3755. static int wcd938x_reset_low(struct device *dev)
  3756. {
  3757. struct wcd938x_priv *wcd938x = NULL;
  3758. int rc = 0;
  3759. if (!dev)
  3760. return -ENODEV;
  3761. wcd938x = dev_get_drvdata(dev);
  3762. if (!wcd938x)
  3763. return -EINVAL;
  3764. if (!wcd938x->rst_np) {
  3765. dev_err(dev, "%s: reset gpio device node not specified\n",
  3766. __func__);
  3767. return -EINVAL;
  3768. }
  3769. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3770. if (rc) {
  3771. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3772. __func__);
  3773. return rc;
  3774. }
  3775. /* 20us sleep required after pulling the reset gpio to LOW */
  3776. usleep_range(20, 30);
  3777. return rc;
  3778. }
  3779. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3780. {
  3781. struct wcd938x_pdata *pdata = NULL;
  3782. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3783. GFP_KERNEL);
  3784. if (!pdata)
  3785. return NULL;
  3786. pdata->rst_np = of_parse_phandle(dev->of_node,
  3787. "qcom,wcd-rst-gpio-node", 0);
  3788. if (!pdata->rst_np) {
  3789. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3790. __func__, "qcom,wcd-rst-gpio-node",
  3791. dev->of_node->full_name);
  3792. return NULL;
  3793. }
  3794. /* Parse power supplies */
  3795. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3796. &pdata->num_supplies);
  3797. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3798. dev_err(dev, "%s: no power supplies defined for codec\n",
  3799. __func__);
  3800. return NULL;
  3801. }
  3802. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3803. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3804. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3805. return pdata;
  3806. }
  3807. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3808. {
  3809. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3810. __func__, irq);
  3811. return IRQ_HANDLED;
  3812. }
  3813. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3814. {
  3815. .name = "wcd938x_cdc",
  3816. .playback = {
  3817. .stream_name = "WCD938X_AIF Playback",
  3818. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3819. .formats = WCD938X_FORMATS,
  3820. .rate_max = 384000,
  3821. .rate_min = 8000,
  3822. .channels_min = 1,
  3823. .channels_max = 4,
  3824. },
  3825. .capture = {
  3826. .stream_name = "WCD938X_AIF Capture",
  3827. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3828. .formats = WCD938X_FORMATS,
  3829. .rate_max = 384000,
  3830. .rate_min = 8000,
  3831. .channels_min = 1,
  3832. .channels_max = 4,
  3833. },
  3834. },
  3835. };
  3836. static int wcd938x_bind(struct device *dev)
  3837. {
  3838. int ret = 0, i = 0;
  3839. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3840. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3841. /*
  3842. * Add 5msec delay to provide sufficient time for
  3843. * soundwire auto enumeration of slave devices as
  3844. * as per HW requirement.
  3845. */
  3846. usleep_range(5000, 5010);
  3847. ret = component_bind_all(dev, wcd938x);
  3848. if (ret) {
  3849. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3850. __func__, ret);
  3851. return ret;
  3852. }
  3853. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3854. if (!wcd938x->rx_swr_dev) {
  3855. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3856. __func__);
  3857. ret = -ENODEV;
  3858. goto err;
  3859. }
  3860. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3861. if (!wcd938x->tx_swr_dev) {
  3862. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3863. __func__);
  3864. ret = -ENODEV;
  3865. goto err;
  3866. }
  3867. swr_init_port_params(wcd938x->tx_swr_dev, SWR_NUM_PORTS,
  3868. wcd938x->swr_tx_port_params);
  3869. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3870. &wcd938x_regmap_config);
  3871. if (!wcd938x->regmap) {
  3872. dev_err(dev, "%s: Regmap init failed\n",
  3873. __func__);
  3874. goto err;
  3875. }
  3876. /* Set all interupts as edge triggered */
  3877. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3878. regmap_write(wcd938x->regmap,
  3879. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3880. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3881. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3882. wcd938x->irq_info.codec_name = "WCD938X";
  3883. wcd938x->irq_info.regmap = wcd938x->regmap;
  3884. wcd938x->irq_info.dev = dev;
  3885. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3886. if (ret) {
  3887. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3888. __func__, ret);
  3889. goto err;
  3890. }
  3891. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3892. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3893. if (ret < 0) {
  3894. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3895. goto err_irq;
  3896. }
  3897. /* Request for watchdog interrupt */
  3898. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3899. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3900. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3901. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3902. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3903. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3904. /* Disable watchdog interrupt for HPH and AUX */
  3905. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3906. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3907. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3908. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3909. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3910. if (ret) {
  3911. dev_err(dev, "%s: Codec registration failed\n",
  3912. __func__);
  3913. goto err_irq;
  3914. }
  3915. wcd938x->dev_up = true;
  3916. return ret;
  3917. err_irq:
  3918. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3919. err:
  3920. component_unbind_all(dev, wcd938x);
  3921. return ret;
  3922. }
  3923. static void wcd938x_unbind(struct device *dev)
  3924. {
  3925. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3926. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3927. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3928. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3929. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3930. snd_soc_unregister_component(dev);
  3931. component_unbind_all(dev, wcd938x);
  3932. }
  3933. static const struct of_device_id wcd938x_dt_match[] = {
  3934. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3935. {}
  3936. };
  3937. static const struct component_master_ops wcd938x_comp_ops = {
  3938. .bind = wcd938x_bind,
  3939. .unbind = wcd938x_unbind,
  3940. };
  3941. static int wcd938x_compare_of(struct device *dev, void *data)
  3942. {
  3943. return dev->of_node == data;
  3944. }
  3945. static void wcd938x_release_of(struct device *dev, void *data)
  3946. {
  3947. of_node_put(data);
  3948. }
  3949. static int wcd938x_add_slave_components(struct device *dev,
  3950. struct component_match **matchptr)
  3951. {
  3952. struct device_node *np, *rx_node, *tx_node;
  3953. np = dev->of_node;
  3954. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3955. if (!rx_node) {
  3956. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3957. return -ENODEV;
  3958. }
  3959. of_node_get(rx_node);
  3960. component_match_add_release(dev, matchptr,
  3961. wcd938x_release_of,
  3962. wcd938x_compare_of,
  3963. rx_node);
  3964. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3965. if (!tx_node) {
  3966. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3967. return -ENODEV;
  3968. }
  3969. of_node_get(tx_node);
  3970. component_match_add_release(dev, matchptr,
  3971. wcd938x_release_of,
  3972. wcd938x_compare_of,
  3973. tx_node);
  3974. return 0;
  3975. }
  3976. static int wcd938x_probe(struct platform_device *pdev)
  3977. {
  3978. struct component_match *match = NULL;
  3979. struct wcd938x_priv *wcd938x = NULL;
  3980. struct wcd938x_pdata *pdata = NULL;
  3981. struct wcd_ctrl_platform_data *plat_data = NULL;
  3982. struct device *dev = &pdev->dev;
  3983. int ret;
  3984. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3985. GFP_KERNEL);
  3986. if (!wcd938x)
  3987. return -ENOMEM;
  3988. dev_set_drvdata(dev, wcd938x);
  3989. wcd938x->dev = dev;
  3990. pdata = wcd938x_populate_dt_data(dev);
  3991. if (!pdata) {
  3992. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3993. return -EINVAL;
  3994. }
  3995. dev->platform_data = pdata;
  3996. wcd938x->rst_np = pdata->rst_np;
  3997. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3998. pdata->regulator, pdata->num_supplies);
  3999. if (!wcd938x->supplies) {
  4000. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4001. __func__);
  4002. return ret;
  4003. }
  4004. plat_data = dev_get_platdata(dev->parent);
  4005. if (!plat_data) {
  4006. dev_err(dev, "%s: platform data from parent is NULL\n",
  4007. __func__);
  4008. return -EINVAL;
  4009. }
  4010. wcd938x->handle = (void *)plat_data->handle;
  4011. if (!wcd938x->handle) {
  4012. dev_err(dev, "%s: handle is NULL\n", __func__);
  4013. return -EINVAL;
  4014. }
  4015. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  4016. if (!wcd938x->update_wcd_event) {
  4017. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4018. __func__);
  4019. return -EINVAL;
  4020. }
  4021. wcd938x->register_notifier = plat_data->register_notifier;
  4022. if (!wcd938x->register_notifier) {
  4023. dev_err(dev, "%s: register_notifier api is null!\n",
  4024. __func__);
  4025. return -EINVAL;
  4026. }
  4027. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  4028. pdata->regulator,
  4029. pdata->num_supplies);
  4030. if (ret) {
  4031. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4032. __func__);
  4033. return ret;
  4034. }
  4035. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4036. CODEC_RX);
  4037. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4038. CODEC_TX);
  4039. if (ret) {
  4040. dev_err(dev, "Failed to read port mapping\n");
  4041. goto err;
  4042. }
  4043. ret = wcd938x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4044. CODEC_TX);
  4045. if (ret) {
  4046. dev_err(dev, "Failed to read port params\n");
  4047. goto err;
  4048. }
  4049. mutex_init(&wcd938x->wakeup_lock);
  4050. mutex_init(&wcd938x->micb_lock);
  4051. ret = wcd938x_add_slave_components(dev, &match);
  4052. if (ret)
  4053. goto err_lock_init;
  4054. wcd938x_reset(dev);
  4055. wcd938x->wakeup = wcd938x_wakeup;
  4056. return component_master_add_with_match(dev,
  4057. &wcd938x_comp_ops, match);
  4058. err_lock_init:
  4059. mutex_destroy(&wcd938x->micb_lock);
  4060. mutex_destroy(&wcd938x->wakeup_lock);
  4061. err:
  4062. return ret;
  4063. }
  4064. static int wcd938x_remove(struct platform_device *pdev)
  4065. {
  4066. struct wcd938x_priv *wcd938x = NULL;
  4067. wcd938x = platform_get_drvdata(pdev);
  4068. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  4069. mutex_destroy(&wcd938x->micb_lock);
  4070. mutex_destroy(&wcd938x->wakeup_lock);
  4071. dev_set_drvdata(&pdev->dev, NULL);
  4072. return 0;
  4073. }
  4074. #ifdef CONFIG_PM_SLEEP
  4075. static int wcd938x_suspend(struct device *dev)
  4076. {
  4077. struct wcd938x_priv *wcd938x = NULL;
  4078. int ret = 0;
  4079. struct wcd938x_pdata *pdata = NULL;
  4080. if (!dev)
  4081. return -ENODEV;
  4082. wcd938x = dev_get_drvdata(dev);
  4083. if (!wcd938x)
  4084. return -EINVAL;
  4085. pdata = dev_get_platdata(wcd938x->dev);
  4086. if (!pdata) {
  4087. dev_err(dev, "%s: pdata is NULL\n", __func__);
  4088. return -EINVAL;
  4089. }
  4090. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  4091. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  4092. wcd938x->supplies,
  4093. pdata->regulator,
  4094. pdata->num_supplies,
  4095. "cdc-vdd-buck");
  4096. if (ret == -EINVAL) {
  4097. dev_err(dev, "%s: vdd buck is not disabled\n",
  4098. __func__);
  4099. return 0;
  4100. }
  4101. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  4102. }
  4103. if (wcd938x->dapm_bias_off) {
  4104. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4105. wcd938x->supplies,
  4106. pdata->regulator,
  4107. pdata->num_supplies,
  4108. true);
  4109. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4110. }
  4111. return 0;
  4112. }
  4113. static int wcd938x_resume(struct device *dev)
  4114. {
  4115. struct wcd938x_priv *wcd938x = NULL;
  4116. struct wcd938x_pdata *pdata = NULL;
  4117. if (!dev)
  4118. return -ENODEV;
  4119. wcd938x = dev_get_drvdata(dev);
  4120. if (!wcd938x)
  4121. return -EINVAL;
  4122. pdata = dev_get_platdata(wcd938x->dev);
  4123. if (!pdata) {
  4124. dev_err(dev, "%s: pdata is NULL\n", __func__);
  4125. return -EINVAL;
  4126. }
  4127. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  4128. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4129. wcd938x->supplies,
  4130. pdata->regulator,
  4131. pdata->num_supplies,
  4132. false);
  4133. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4134. }
  4135. return 0;
  4136. }
  4137. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  4138. .suspend_late = wcd938x_suspend,
  4139. .resume_early = wcd938x_resume,
  4140. };
  4141. #endif
  4142. static struct platform_driver wcd938x_codec_driver = {
  4143. .probe = wcd938x_probe,
  4144. .remove = wcd938x_remove,
  4145. .driver = {
  4146. .name = "wcd938x_codec",
  4147. .owner = THIS_MODULE,
  4148. .of_match_table = of_match_ptr(wcd938x_dt_match),
  4149. #ifdef CONFIG_PM_SLEEP
  4150. .pm = &wcd938x_dev_pm_ops,
  4151. #endif
  4152. .suppress_bind_attrs = true,
  4153. },
  4154. };
  4155. module_platform_driver(wcd938x_codec_driver);
  4156. MODULE_DESCRIPTION("WCD938X Codec driver");
  4157. MODULE_LICENSE("GPL v2");