wcd937x.c 98 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #include "asoc/bolero-slave-internal.h"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. #define NUM_ATTEMPTS 5
  35. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  36. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  37. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  38. SNDRV_PCM_RATE_384000)
  39. /* Fractional Rates */
  40. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  41. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  42. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  43. SNDRV_PCM_FMTBIT_S24_LE |\
  44. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  45. enum {
  46. CODEC_TX = 0,
  47. CODEC_RX,
  48. };
  49. enum {
  50. ALLOW_BUCK_DISABLE,
  51. HPH_COMP_DELAY,
  52. HPH_PA_DELAY,
  53. AMIC2_BCS_ENABLE,
  54. };
  55. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  56. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  57. static int wcd937x_handle_post_irq(void *data);
  58. static int wcd937x_reset(struct device *dev);
  59. static int wcd937x_reset_low(struct device *dev);
  60. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  61. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  81. };
  82. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  83. .name = "wcd937x",
  84. .irqs = wcd937x_irqs,
  85. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  86. .num_regs = 3,
  87. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  88. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  89. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  90. .use_ack = 1,
  91. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  92. .clear_ack = 1,
  93. #endif
  94. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  95. .runtime_pm = false,
  96. .handle_post_irq = wcd937x_handle_post_irq,
  97. .irq_drv_data = NULL,
  98. };
  99. static struct snd_soc_dai_driver wcd937x_dai[] = {
  100. {
  101. .name = "wcd937x_cdc",
  102. .playback = {
  103. .stream_name = "WCD937X_AIF Playback",
  104. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  105. .formats = WCD937X_FORMATS,
  106. .rate_max = 384000,
  107. .rate_min = 8000,
  108. .channels_min = 1,
  109. .channels_max = 4,
  110. },
  111. .capture = {
  112. .stream_name = "WCD937X_AIF Capture",
  113. .rates = WCD937X_RATES,
  114. .formats = WCD937X_FORMATS,
  115. .rate_max = 192000,
  116. .rate_min = 8000,
  117. .channels_min = 1,
  118. .channels_max = 4,
  119. },
  120. },
  121. };
  122. static int wcd937x_handle_post_irq(void *data)
  123. {
  124. struct wcd937x_priv *wcd937x = data;
  125. u32 status1 = 0, status2 = 0, status3 = 0;
  126. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  127. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  128. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  129. wcd937x->tx_swr_dev->slave_irq_pending =
  130. ((status1 || status2 || status3) ? true : false);
  131. return IRQ_HANDLED;
  132. }
  133. static int wcd937x_init_reg(struct snd_soc_component *component)
  134. {
  135. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  136. 0x0E, 0x0E);
  137. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  138. 0x80, 0x80);
  139. usleep_range(1000, 1010);
  140. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  141. 0x40, 0x40);
  142. usleep_range(1000, 1010);
  143. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  144. 0x10, 0x00);
  145. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  146. 0xF0, 0x80);
  147. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  148. 0x80, 0x80);
  149. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  150. 0x40, 0x40);
  151. usleep_range(10000, 10010);
  152. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  153. 0x40, 0x00);
  154. snd_soc_component_update_bits(component,
  155. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  156. 0xFF, 0xD9);
  157. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  158. 0xFF, 0xFA);
  159. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  160. 0xFF, 0xFA);
  161. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  162. 0xFF, 0xFA);
  163. return 0;
  164. }
  165. static int wcd937x_set_port_params(struct snd_soc_component *component,
  166. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  167. u8 *ch_mask, u32 *ch_rate,
  168. u8 *port_type, u8 path)
  169. {
  170. int i, j;
  171. u8 num_ports = 0;
  172. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  173. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  174. switch (path) {
  175. case CODEC_RX:
  176. map = &wcd937x->rx_port_mapping;
  177. num_ports = wcd937x->num_rx_ports;
  178. break;
  179. case CODEC_TX:
  180. map = &wcd937x->tx_port_mapping;
  181. num_ports = wcd937x->num_tx_ports;
  182. break;
  183. default:
  184. dev_err(component->dev, "%s Invalid path selected %u\n",
  185. __func__, path);
  186. return -EINVAL;
  187. }
  188. for (i = 0; i <= num_ports; i++) {
  189. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  190. if ((*map)[i][j].slave_port_type == slv_prt_type)
  191. goto found;
  192. }
  193. }
  194. found:
  195. if (i > num_ports || j == MAX_CH_PER_PORT) {
  196. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  197. __func__, slv_prt_type);
  198. return -EINVAL;
  199. }
  200. *port_id = i;
  201. *num_ch = (*map)[i][j].num_ch;
  202. *ch_mask = (*map)[i][j].ch_mask;
  203. *ch_rate = (*map)[i][j].ch_rate;
  204. *port_type = (*map)[i][j].master_port_type;
  205. return 0;
  206. }
  207. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  208. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  209. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  210. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  211. static int wcd937x_parse_port_params(struct device *dev,
  212. char *prop, u8 path)
  213. {
  214. u32 *dt_array, map_size, max_uc;
  215. int ret = 0;
  216. u32 offset1, lane_ctrl, cnt = 0;
  217. struct port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  218. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  219. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  220. switch (path) {
  221. case CODEC_TX:
  222. map = &wcd937x->tx_port_params;
  223. map_uc = &wcd937x->swr_tx_port_params;
  224. break;
  225. default:
  226. ret = -EINVAL;
  227. goto err_port_map;
  228. }
  229. if (!of_find_property(dev->of_node, prop,
  230. &map_size)) {
  231. dev_err(dev, "missing port mapping prop %s\n", prop);
  232. ret = -EINVAL;
  233. goto err_port_map;
  234. }
  235. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  236. if (max_uc != SWR_UC_MAX) {
  237. dev_err(dev, "%s: port params not provided for all usecases\n",
  238. __func__);
  239. ret = -EINVAL;
  240. goto err_port_map;
  241. }
  242. dt_array = kzalloc(map_size, GFP_KERNEL);
  243. if (!dt_array) {
  244. ret = -ENOMEM;
  245. goto err_alloc;
  246. }
  247. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  248. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  249. if (ret) {
  250. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  251. __func__, prop);
  252. goto err_pdata_fail;
  253. }
  254. for (i = 0; i < max_uc; i++) {
  255. for (j = 0; j < SWR_NUM_PORTS; j++) {
  256. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  257. (*map)[i][j].offset1 = dt_array[cnt];
  258. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  259. }
  260. (*map_uc)[i] = &(*map)[i][0];
  261. }
  262. kfree(dt_array);
  263. return 0;
  264. err_pdata_fail:
  265. kfree(dt_array);
  266. err_alloc:
  267. err_port_map:
  268. return ret;
  269. }
  270. static int wcd937x_parse_port_mapping(struct device *dev,
  271. char *prop, u8 path)
  272. {
  273. u32 *dt_array, map_size, map_length;
  274. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  275. u32 slave_port_type, master_port_type;
  276. u32 i, ch_iter = 0;
  277. int ret = 0;
  278. u8 *num_ports = NULL;
  279. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  280. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  281. switch (path) {
  282. case CODEC_RX:
  283. map = &wcd937x->rx_port_mapping;
  284. num_ports = &wcd937x->num_rx_ports;
  285. break;
  286. case CODEC_TX:
  287. map = &wcd937x->tx_port_mapping;
  288. num_ports = &wcd937x->num_tx_ports;
  289. break;
  290. default:
  291. dev_err(dev, "%s Invalid path selected %u\n",
  292. __func__, path);
  293. return -EINVAL;
  294. }
  295. if (!of_find_property(dev->of_node, prop,
  296. &map_size)) {
  297. dev_err(dev, "missing port mapping prop %s\n", prop);
  298. ret = -EINVAL;
  299. goto err;
  300. }
  301. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  302. dt_array = kzalloc(map_size, GFP_KERNEL);
  303. if (!dt_array) {
  304. ret = -ENOMEM;
  305. goto err;
  306. }
  307. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  308. NUM_SWRS_DT_PARAMS * map_length);
  309. if (ret) {
  310. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  311. __func__, prop);
  312. ret = -EINVAL;
  313. goto err_pdata_fail;
  314. }
  315. for (i = 0; i < map_length; i++) {
  316. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  317. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  318. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  319. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  320. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  321. if (port_num != old_port_num)
  322. ch_iter = 0;
  323. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  324. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  325. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  326. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  327. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  328. old_port_num = port_num;
  329. }
  330. *num_ports = port_num;
  331. kfree(dt_array);
  332. return 0;
  333. err_pdata_fail:
  334. kfree(dt_array);
  335. err:
  336. return ret;
  337. }
  338. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  339. u8 slv_port_type, u8 enable)
  340. {
  341. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  342. u8 port_id;
  343. u8 num_ch;
  344. u8 ch_mask;
  345. u32 ch_rate;
  346. u8 ch_type = 0;
  347. int slave_ch_idx;
  348. u8 num_port = 1;
  349. int ret = 0;
  350. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  351. &num_ch, &ch_mask, &ch_rate,
  352. &ch_type, CODEC_TX);
  353. if (ret)
  354. return ret;
  355. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  356. if (slave_ch_idx != -EINVAL)
  357. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  358. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  359. __func__, slave_ch_idx, ch_type);
  360. if (enable)
  361. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  362. num_port, &ch_mask, &ch_rate,
  363. &num_ch, &ch_type);
  364. else
  365. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  366. num_port, &ch_mask, &ch_type);
  367. return ret;
  368. }
  369. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  370. u8 slv_port_type, u8 enable)
  371. {
  372. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  373. u8 port_id;
  374. u8 num_ch;
  375. u8 ch_mask;
  376. u32 ch_rate;
  377. u8 port_type;
  378. u8 num_port = 1;
  379. int ret = 0;
  380. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  381. &num_ch, &ch_mask, &ch_rate,
  382. &port_type, CODEC_RX);
  383. if (ret)
  384. return ret;
  385. if (enable)
  386. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  387. num_port, &ch_mask, &ch_rate,
  388. &num_ch, &port_type);
  389. else
  390. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  391. num_port, &ch_mask, &port_type);
  392. return ret;
  393. }
  394. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  395. {
  396. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  397. if (wcd937x->rx_clk_cnt == 0) {
  398. snd_soc_component_update_bits(component,
  399. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  400. snd_soc_component_update_bits(component,
  401. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  402. snd_soc_component_update_bits(component,
  403. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  404. snd_soc_component_update_bits(component,
  405. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  406. snd_soc_component_update_bits(component,
  407. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  408. snd_soc_component_update_bits(component,
  409. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  410. snd_soc_component_update_bits(component,
  411. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  412. }
  413. wcd937x->rx_clk_cnt++;
  414. return 0;
  415. }
  416. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  417. {
  418. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  419. if (wcd937x->rx_clk_cnt == 0) {
  420. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  421. return 0;
  422. }
  423. wcd937x->rx_clk_cnt--;
  424. if (wcd937x->rx_clk_cnt == 0) {
  425. snd_soc_component_update_bits(component,
  426. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  427. snd_soc_component_update_bits(component,
  428. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  429. 0x02, 0x00);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  432. 0x01, 0x00);
  433. }
  434. return 0;
  435. }
  436. /*
  437. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  438. * @component: handle to snd_soc_component *
  439. *
  440. * return wcd937x_mbhc handle or error code in case of failure
  441. */
  442. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  443. {
  444. struct wcd937x_priv *wcd937x;
  445. if (!component) {
  446. pr_err("%s: Invalid params, NULL component\n", __func__);
  447. return NULL;
  448. }
  449. wcd937x = snd_soc_component_get_drvdata(component);
  450. if (!wcd937x) {
  451. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  452. return NULL;
  453. }
  454. return wcd937x->mbhc;
  455. }
  456. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  457. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  458. struct snd_kcontrol *kcontrol,
  459. int event)
  460. {
  461. struct snd_soc_component *component =
  462. snd_soc_dapm_to_component(w->dapm);
  463. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  464. int hph_mode = wcd937x->hph_mode;
  465. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  466. w->name, event);
  467. switch (event) {
  468. case SND_SOC_DAPM_PRE_PMU:
  469. wcd937x_rx_clk_enable(component);
  470. snd_soc_component_update_bits(component,
  471. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  472. 0x01, 0x01);
  473. snd_soc_component_update_bits(component,
  474. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  475. 0x04, 0x04);
  476. snd_soc_component_update_bits(component,
  477. WCD937X_HPH_RDAC_CLK_CTL1,
  478. 0x80, 0x00);
  479. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  480. break;
  481. case SND_SOC_DAPM_POST_PMU:
  482. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  483. snd_soc_component_update_bits(component,
  484. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  485. 0x0F, 0x02);
  486. else if (hph_mode == CLS_H_LOHIFI)
  487. snd_soc_component_update_bits(component,
  488. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  489. 0x0F, 0x06);
  490. if (wcd937x->comp1_enable) {
  491. snd_soc_component_update_bits(component,
  492. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  493. 0x02, 0x02);
  494. snd_soc_component_update_bits(component,
  495. WCD937X_HPH_L_EN, 0x20, 0x00);
  496. if (wcd937x->comp2_enable) {
  497. snd_soc_component_update_bits(component,
  498. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  499. 0x01, 0x01);
  500. snd_soc_component_update_bits(component,
  501. WCD937X_HPH_R_EN, 0x20, 0x00);
  502. }
  503. /*
  504. * 5ms sleep is required after COMP is enabled as per
  505. * HW requirement
  506. */
  507. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  508. usleep_range(5000, 5100);
  509. clear_bit(HPH_COMP_DELAY,
  510. &wcd937x->status_mask);
  511. }
  512. } else {
  513. snd_soc_component_update_bits(component,
  514. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  515. 0x02, 0x00);
  516. snd_soc_component_update_bits(component,
  517. WCD937X_HPH_L_EN, 0x20, 0x20);
  518. }
  519. snd_soc_component_update_bits(component,
  520. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  521. break;
  522. case SND_SOC_DAPM_POST_PMD:
  523. snd_soc_component_update_bits(component,
  524. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  525. 0x0F, 0x01);
  526. break;
  527. }
  528. return 0;
  529. }
  530. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  531. struct snd_kcontrol *kcontrol,
  532. int event)
  533. {
  534. struct snd_soc_component *component =
  535. snd_soc_dapm_to_component(w->dapm);
  536. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  537. int hph_mode = wcd937x->hph_mode;
  538. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  539. w->name, event);
  540. switch (event) {
  541. case SND_SOC_DAPM_PRE_PMU:
  542. wcd937x_rx_clk_enable(component);
  543. snd_soc_component_update_bits(component,
  544. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  545. snd_soc_component_update_bits(component,
  546. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  547. snd_soc_component_update_bits(component,
  548. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  549. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  550. break;
  551. case SND_SOC_DAPM_POST_PMU:
  552. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  553. snd_soc_component_update_bits(component,
  554. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  555. 0x0F, 0x02);
  556. else if (hph_mode == CLS_H_LOHIFI)
  557. snd_soc_component_update_bits(component,
  558. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  559. 0x0F, 0x06);
  560. if (wcd937x->comp2_enable) {
  561. snd_soc_component_update_bits(component,
  562. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  563. 0x01, 0x01);
  564. snd_soc_component_update_bits(component,
  565. WCD937X_HPH_R_EN, 0x20, 0x00);
  566. if (wcd937x->comp1_enable) {
  567. snd_soc_component_update_bits(component,
  568. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  569. 0x02, 0x02);
  570. snd_soc_component_update_bits(component,
  571. WCD937X_HPH_L_EN, 0x20, 0x00);
  572. }
  573. /*
  574. * 5ms sleep is required after COMP is enabled as per
  575. * HW requirement
  576. */
  577. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  578. usleep_range(5000, 5100);
  579. clear_bit(HPH_COMP_DELAY,
  580. &wcd937x->status_mask);
  581. }
  582. } else {
  583. snd_soc_component_update_bits(component,
  584. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  585. 0x01, 0x00);
  586. snd_soc_component_update_bits(component,
  587. WCD937X_HPH_R_EN, 0x20, 0x20);
  588. }
  589. snd_soc_component_update_bits(component,
  590. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. snd_soc_component_update_bits(component,
  594. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  595. 0x0F, 0x01);
  596. break;
  597. }
  598. return 0;
  599. }
  600. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  601. struct snd_kcontrol *kcontrol,
  602. int event)
  603. {
  604. struct snd_soc_component *component =
  605. snd_soc_dapm_to_component(w->dapm);
  606. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  607. int hph_mode = wcd937x->hph_mode;
  608. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  609. w->name, event);
  610. switch (event) {
  611. case SND_SOC_DAPM_PRE_PMU:
  612. wcd937x_rx_clk_enable(component);
  613. snd_soc_component_update_bits(component,
  614. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  615. 0x04, 0x04);
  616. snd_soc_component_update_bits(component,
  617. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  618. 0x01, 0x01);
  619. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  620. snd_soc_component_update_bits(component,
  621. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  622. 0x0F, 0x02);
  623. else if (hph_mode == CLS_H_LOHIFI)
  624. snd_soc_component_update_bits(component,
  625. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  626. 0x0F, 0x06);
  627. if (wcd937x->comp1_enable)
  628. snd_soc_component_update_bits(component,
  629. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  630. 0x02, 0x02);
  631. usleep_range(5000, 5010);
  632. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  633. 0x04, 0x00);
  634. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  635. WCD_CLSH_EVENT_PRE_DAC,
  636. WCD_CLSH_STATE_EAR,
  637. hph_mode);
  638. break;
  639. case SND_SOC_DAPM_POST_PMD:
  640. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  641. hph_mode == CLS_H_HIFI)
  642. snd_soc_component_update_bits(component,
  643. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  644. 0x0F, 0x01);
  645. if (wcd937x->comp1_enable)
  646. snd_soc_component_update_bits(component,
  647. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  648. 0x02, 0x00);
  649. break;
  650. };
  651. return 0;
  652. }
  653. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  654. struct snd_kcontrol *kcontrol,
  655. int event)
  656. {
  657. struct snd_soc_component *component =
  658. snd_soc_dapm_to_component(w->dapm);
  659. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  660. int hph_mode = wcd937x->hph_mode;
  661. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  662. w->name, event);
  663. switch (event) {
  664. case SND_SOC_DAPM_PRE_PMU:
  665. wcd937x_rx_clk_enable(component);
  666. snd_soc_component_update_bits(component,
  667. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  668. 0x04, 0x04);
  669. snd_soc_component_update_bits(component,
  670. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  671. 0x04, 0x04);
  672. snd_soc_component_update_bits(component,
  673. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  674. 0x01, 0x01);
  675. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  676. WCD_CLSH_EVENT_PRE_DAC,
  677. WCD_CLSH_STATE_AUX,
  678. hph_mode);
  679. break;
  680. case SND_SOC_DAPM_POST_PMD:
  681. snd_soc_component_update_bits(component,
  682. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  683. 0x04, 0x00);
  684. break;
  685. };
  686. return 0;
  687. }
  688. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  689. struct snd_kcontrol *kcontrol,
  690. int event)
  691. {
  692. struct snd_soc_component *component =
  693. snd_soc_dapm_to_component(w->dapm);
  694. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  695. int ret = 0;
  696. int hph_mode = wcd937x->hph_mode;
  697. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  698. w->name, event);
  699. switch (event) {
  700. case SND_SOC_DAPM_PRE_PMU:
  701. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  702. wcd937x->rx_swr_dev->dev_num,
  703. true);
  704. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  705. WCD_CLSH_EVENT_PRE_DAC,
  706. WCD_CLSH_STATE_HPHR,
  707. hph_mode);
  708. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  709. 0x10, 0x10);
  710. usleep_range(100, 110);
  711. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  712. snd_soc_component_update_bits(component,
  713. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  714. break;
  715. case SND_SOC_DAPM_POST_PMU:
  716. /*
  717. * 7ms sleep is required after PA is enabled as per
  718. * HW requirement. If compander is disabled, then
  719. * 20ms delay is required.
  720. */
  721. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  722. if (!wcd937x->comp2_enable)
  723. usleep_range(20000, 20100);
  724. else
  725. usleep_range(7000, 7100);
  726. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  727. }
  728. snd_soc_component_update_bits(component,
  729. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  730. 0x02, 0x02);
  731. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  732. snd_soc_component_update_bits(component,
  733. WCD937X_ANA_RX_SUPPLIES,
  734. 0x02, 0x02);
  735. if (wcd937x->update_wcd_event)
  736. wcd937x->update_wcd_event(wcd937x->handle,
  737. SLV_BOLERO_EVT_RX_MUTE,
  738. (WCD_RX2 << 0x10));
  739. wcd_enable_irq(&wcd937x->irq_info,
  740. WCD937X_IRQ_HPHR_PDM_WD_INT);
  741. break;
  742. case SND_SOC_DAPM_PRE_PMD:
  743. wcd_disable_irq(&wcd937x->irq_info,
  744. WCD937X_IRQ_HPHR_PDM_WD_INT);
  745. if (wcd937x->update_wcd_event)
  746. wcd937x->update_wcd_event(wcd937x->handle,
  747. SLV_BOLERO_EVT_RX_MUTE,
  748. (WCD_RX2 << 0x10 | 0x1));
  749. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  750. WCD_EVENT_PRE_HPHR_PA_OFF,
  751. &wcd937x->mbhc->wcd_mbhc);
  752. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  753. break;
  754. case SND_SOC_DAPM_POST_PMD:
  755. /*
  756. * 7ms sleep is required after PA is disabled as per
  757. * HW requirement. If compander is disabled, then
  758. * 20ms delay is required.
  759. */
  760. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  761. if (!wcd937x->comp2_enable)
  762. usleep_range(20000, 20100);
  763. else
  764. usleep_range(7000, 7100);
  765. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  766. }
  767. snd_soc_component_update_bits(component,
  768. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  769. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  770. WCD_EVENT_POST_HPHR_PA_OFF,
  771. &wcd937x->mbhc->wcd_mbhc);
  772. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  773. 0x10, 0x00);
  774. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  775. WCD_CLSH_EVENT_POST_PA,
  776. WCD_CLSH_STATE_HPHR,
  777. hph_mode);
  778. break;
  779. };
  780. return ret;
  781. }
  782. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  783. struct snd_kcontrol *kcontrol,
  784. int event)
  785. {
  786. struct snd_soc_component *component =
  787. snd_soc_dapm_to_component(w->dapm);
  788. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  789. int ret = 0;
  790. int hph_mode = wcd937x->hph_mode;
  791. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  792. w->name, event);
  793. switch (event) {
  794. case SND_SOC_DAPM_PRE_PMU:
  795. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  796. wcd937x->rx_swr_dev->dev_num,
  797. true);
  798. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  799. WCD_CLSH_EVENT_PRE_DAC,
  800. WCD_CLSH_STATE_HPHL,
  801. hph_mode);
  802. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  803. 0x20, 0x20);
  804. usleep_range(100, 110);
  805. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  806. snd_soc_component_update_bits(component,
  807. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  808. break;
  809. case SND_SOC_DAPM_POST_PMU:
  810. /*
  811. * 7ms sleep is required after PA is enabled as per
  812. * HW requirement. If compander is disabled, then
  813. * 20ms delay is required.
  814. */
  815. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  816. if (!wcd937x->comp1_enable)
  817. usleep_range(20000, 20100);
  818. else
  819. usleep_range(7000, 7100);
  820. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  821. }
  822. snd_soc_component_update_bits(component,
  823. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  824. 0x02, 0x02);
  825. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  826. snd_soc_component_update_bits(component,
  827. WCD937X_ANA_RX_SUPPLIES,
  828. 0x02, 0x02);
  829. if (wcd937x->update_wcd_event)
  830. wcd937x->update_wcd_event(wcd937x->handle,
  831. SLV_BOLERO_EVT_RX_MUTE,
  832. (WCD_RX1 << 0x10));
  833. wcd_enable_irq(&wcd937x->irq_info,
  834. WCD937X_IRQ_HPHL_PDM_WD_INT);
  835. break;
  836. case SND_SOC_DAPM_PRE_PMD:
  837. wcd_disable_irq(&wcd937x->irq_info,
  838. WCD937X_IRQ_HPHL_PDM_WD_INT);
  839. if (wcd937x->update_wcd_event)
  840. wcd937x->update_wcd_event(wcd937x->handle,
  841. SLV_BOLERO_EVT_RX_MUTE,
  842. (WCD_RX1 << 0x10 | 0x1));
  843. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  844. WCD_EVENT_PRE_HPHL_PA_OFF,
  845. &wcd937x->mbhc->wcd_mbhc);
  846. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  847. break;
  848. case SND_SOC_DAPM_POST_PMD:
  849. /*
  850. * 7ms sleep is required after PA is disabled as per
  851. * HW requirement. If compander is disabled, then
  852. * 20ms delay is required.
  853. */
  854. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  855. if (!wcd937x->comp1_enable)
  856. usleep_range(20000, 20100);
  857. else
  858. usleep_range(7000, 7100);
  859. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  860. }
  861. snd_soc_component_update_bits(component,
  862. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  863. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  864. WCD_EVENT_POST_HPHL_PA_OFF,
  865. &wcd937x->mbhc->wcd_mbhc);
  866. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  867. 0x20, 0x00);
  868. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  869. WCD_CLSH_EVENT_POST_PA,
  870. WCD_CLSH_STATE_HPHL,
  871. hph_mode);
  872. break;
  873. };
  874. return ret;
  875. }
  876. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  877. struct snd_kcontrol *kcontrol,
  878. int event)
  879. {
  880. struct snd_soc_component *component =
  881. snd_soc_dapm_to_component(w->dapm);
  882. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  883. int hph_mode = wcd937x->hph_mode;
  884. int ret = 0;
  885. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  886. w->name, event);
  887. switch (event) {
  888. case SND_SOC_DAPM_PRE_PMU:
  889. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  890. wcd937x->rx_swr_dev->dev_num,
  891. true);
  892. snd_soc_component_update_bits(component,
  893. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  894. break;
  895. case SND_SOC_DAPM_POST_PMU:
  896. usleep_range(1000, 1010);
  897. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  898. snd_soc_component_update_bits(component,
  899. WCD937X_ANA_RX_SUPPLIES,
  900. 0x02, 0x02);
  901. if (wcd937x->update_wcd_event)
  902. wcd937x->update_wcd_event(wcd937x->handle,
  903. SLV_BOLERO_EVT_RX_MUTE,
  904. (WCD_RX3 << 0x10));
  905. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  906. break;
  907. case SND_SOC_DAPM_PRE_PMD:
  908. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  909. if (wcd937x->update_wcd_event)
  910. wcd937x->update_wcd_event(wcd937x->handle,
  911. SLV_BOLERO_EVT_RX_MUTE,
  912. (WCD_RX3 << 0x10 | 0x1));
  913. break;
  914. case SND_SOC_DAPM_POST_PMD:
  915. /* Add delay as per hw requirement */
  916. usleep_range(2000, 2010);
  917. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  918. WCD_CLSH_EVENT_POST_PA,
  919. WCD_CLSH_STATE_AUX,
  920. hph_mode);
  921. snd_soc_component_update_bits(component,
  922. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  923. break;
  924. };
  925. return ret;
  926. }
  927. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  928. struct snd_kcontrol *kcontrol,
  929. int event)
  930. {
  931. struct snd_soc_component *component =
  932. snd_soc_dapm_to_component(w->dapm);
  933. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  934. int hph_mode = wcd937x->hph_mode;
  935. int ret = 0;
  936. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  937. w->name, event);
  938. switch (event) {
  939. case SND_SOC_DAPM_PRE_PMU:
  940. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  941. wcd937x->rx_swr_dev->dev_num,
  942. true);
  943. /*
  944. * Enable watchdog interrupt for HPHL or AUX
  945. * depending on mux value
  946. */
  947. wcd937x->ear_rx_path =
  948. snd_soc_component_read(
  949. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  950. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  951. snd_soc_component_update_bits(component,
  952. WCD937X_DIGITAL_PDM_WD_CTL2,
  953. 0x05, 0x05);
  954. else
  955. snd_soc_component_update_bits(component,
  956. WCD937X_DIGITAL_PDM_WD_CTL0,
  957. 0x17, 0x13);
  958. if (!wcd937x->comp1_enable)
  959. snd_soc_component_update_bits(component,
  960. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  961. break;
  962. case SND_SOC_DAPM_POST_PMU:
  963. usleep_range(6000, 6010);
  964. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  965. snd_soc_component_update_bits(component,
  966. WCD937X_ANA_RX_SUPPLIES,
  967. 0x02, 0x02);
  968. if (wcd937x->update_wcd_event)
  969. wcd937x->update_wcd_event(wcd937x->handle,
  970. SLV_BOLERO_EVT_RX_MUTE,
  971. (WCD_RX1 << 0x10));
  972. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  973. wcd_enable_irq(&wcd937x->irq_info,
  974. WCD937X_IRQ_AUX_PDM_WD_INT);
  975. else
  976. wcd_enable_irq(&wcd937x->irq_info,
  977. WCD937X_IRQ_HPHL_PDM_WD_INT);
  978. break;
  979. case SND_SOC_DAPM_PRE_PMD:
  980. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  981. wcd_disable_irq(&wcd937x->irq_info,
  982. WCD937X_IRQ_AUX_PDM_WD_INT);
  983. else
  984. wcd_disable_irq(&wcd937x->irq_info,
  985. WCD937X_IRQ_HPHL_PDM_WD_INT);
  986. if (wcd937x->update_wcd_event)
  987. wcd937x->update_wcd_event(wcd937x->handle,
  988. SLV_BOLERO_EVT_RX_MUTE,
  989. (WCD_RX1 << 0x10 | 0x1));
  990. break;
  991. case SND_SOC_DAPM_POST_PMD:
  992. if (!wcd937x->comp1_enable)
  993. snd_soc_component_update_bits(component,
  994. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  995. usleep_range(7000, 7010);
  996. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  997. WCD_CLSH_EVENT_POST_PA,
  998. WCD_CLSH_STATE_EAR,
  999. hph_mode);
  1000. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1001. 0x04, 0x04);
  1002. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1003. snd_soc_component_update_bits(component,
  1004. WCD937X_DIGITAL_PDM_WD_CTL2,
  1005. 0x05, 0x00);
  1006. else
  1007. snd_soc_component_update_bits(component,
  1008. WCD937X_DIGITAL_PDM_WD_CTL0,
  1009. 0x17, 0x00);
  1010. break;
  1011. };
  1012. return ret;
  1013. }
  1014. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1015. struct snd_kcontrol *kcontrol,
  1016. int event)
  1017. {
  1018. struct snd_soc_component *component =
  1019. snd_soc_dapm_to_component(w->dapm);
  1020. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1021. int mode = wcd937x->hph_mode;
  1022. int ret = 0;
  1023. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1024. w->name, event);
  1025. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1026. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1027. wcd937x_rx_connect_port(component, CLSH,
  1028. SND_SOC_DAPM_EVENT_ON(event));
  1029. }
  1030. if (SND_SOC_DAPM_EVENT_OFF(event))
  1031. ret = swr_slvdev_datapath_control(
  1032. wcd937x->rx_swr_dev,
  1033. wcd937x->rx_swr_dev->dev_num,
  1034. false);
  1035. return ret;
  1036. }
  1037. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1038. struct snd_kcontrol *kcontrol,
  1039. int event)
  1040. {
  1041. struct snd_soc_component *component =
  1042. snd_soc_dapm_to_component(w->dapm);
  1043. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1044. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1045. w->name, event);
  1046. switch (event) {
  1047. case SND_SOC_DAPM_PRE_PMU:
  1048. wcd937x_rx_connect_port(component, HPH_L, true);
  1049. if (wcd937x->comp1_enable)
  1050. wcd937x_rx_connect_port(component, COMP_L, true);
  1051. break;
  1052. case SND_SOC_DAPM_POST_PMD:
  1053. wcd937x_rx_connect_port(component, HPH_L, false);
  1054. if (wcd937x->comp1_enable)
  1055. wcd937x_rx_connect_port(component, COMP_L, false);
  1056. wcd937x_rx_clk_disable(component);
  1057. snd_soc_component_update_bits(component,
  1058. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1059. 0x01, 0x00);
  1060. break;
  1061. };
  1062. return 0;
  1063. }
  1064. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1065. struct snd_kcontrol *kcontrol, int event)
  1066. {
  1067. struct snd_soc_component *component =
  1068. snd_soc_dapm_to_component(w->dapm);
  1069. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1070. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1071. w->name, event);
  1072. switch (event) {
  1073. case SND_SOC_DAPM_PRE_PMU:
  1074. wcd937x_rx_connect_port(component, HPH_R, true);
  1075. if (wcd937x->comp2_enable)
  1076. wcd937x_rx_connect_port(component, COMP_R, true);
  1077. break;
  1078. case SND_SOC_DAPM_POST_PMD:
  1079. wcd937x_rx_connect_port(component, HPH_R, false);
  1080. if (wcd937x->comp2_enable)
  1081. wcd937x_rx_connect_port(component, COMP_R, false);
  1082. wcd937x_rx_clk_disable(component);
  1083. snd_soc_component_update_bits(component,
  1084. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1085. 0x02, 0x00);
  1086. break;
  1087. };
  1088. return 0;
  1089. }
  1090. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1091. struct snd_kcontrol *kcontrol,
  1092. int event)
  1093. {
  1094. struct snd_soc_component *component =
  1095. snd_soc_dapm_to_component(w->dapm);
  1096. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1097. w->name, event);
  1098. switch (event) {
  1099. case SND_SOC_DAPM_PRE_PMU:
  1100. wcd937x_rx_connect_port(component, LO, true);
  1101. break;
  1102. case SND_SOC_DAPM_POST_PMD:
  1103. wcd937x_rx_connect_port(component, LO, false);
  1104. usleep_range(6000, 6010);
  1105. wcd937x_rx_clk_disable(component);
  1106. snd_soc_component_update_bits(component,
  1107. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1108. break;
  1109. }
  1110. return 0;
  1111. }
  1112. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1113. struct snd_kcontrol *kcontrol,
  1114. int event)
  1115. {
  1116. struct snd_soc_component *component =
  1117. snd_soc_dapm_to_component(w->dapm);
  1118. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1119. u16 dmic_clk_reg;
  1120. s32 *dmic_clk_cnt;
  1121. unsigned int dmic;
  1122. char *wname;
  1123. int ret = 0;
  1124. wname = strpbrk(w->name, "012345");
  1125. if (!wname) {
  1126. dev_err(component->dev, "%s: widget not found\n", __func__);
  1127. return -EINVAL;
  1128. }
  1129. ret = kstrtouint(wname, 10, &dmic);
  1130. if (ret < 0) {
  1131. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1132. __func__);
  1133. return -EINVAL;
  1134. }
  1135. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1136. w->name, event);
  1137. switch (dmic) {
  1138. case 0:
  1139. case 1:
  1140. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1141. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1142. break;
  1143. case 2:
  1144. case 3:
  1145. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1146. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1147. break;
  1148. case 4:
  1149. case 5:
  1150. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1151. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1152. break;
  1153. default:
  1154. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1155. __func__);
  1156. return -EINVAL;
  1157. };
  1158. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1159. __func__, event, dmic, *dmic_clk_cnt);
  1160. switch (event) {
  1161. case SND_SOC_DAPM_PRE_PMU:
  1162. snd_soc_component_update_bits(component,
  1163. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1164. snd_soc_component_update_bits(component,
  1165. dmic_clk_reg, 0x07, 0x02);
  1166. snd_soc_component_update_bits(component,
  1167. dmic_clk_reg, 0x08, 0x08);
  1168. snd_soc_component_update_bits(component,
  1169. dmic_clk_reg, 0x70, 0x20);
  1170. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1171. wcd937x->tx_swr_dev->dev_num,
  1172. true);
  1173. break;
  1174. case SND_SOC_DAPM_POST_PMD:
  1175. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1176. break;
  1177. };
  1178. return 0;
  1179. }
  1180. /*
  1181. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1182. * @micb_mv: micbias in mv
  1183. *
  1184. * return register value converted
  1185. */
  1186. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1187. {
  1188. /* min micbias voltage is 1V and maximum is 2.85V */
  1189. if (micb_mv < 1000 || micb_mv > 2850) {
  1190. pr_err("%s: unsupported micbias voltage\n", __func__);
  1191. return -EINVAL;
  1192. }
  1193. return (micb_mv - 1000) / 50;
  1194. }
  1195. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1196. /*
  1197. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1198. * @component: handle to snd_soc_component *
  1199. * @req_volt: micbias voltage to be set
  1200. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1201. *
  1202. * return 0 if adjustment is success or error code in case of failure
  1203. */
  1204. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1205. int req_volt, int micb_num)
  1206. {
  1207. struct wcd937x_priv *wcd937x =
  1208. snd_soc_component_get_drvdata(component);
  1209. int cur_vout_ctl, req_vout_ctl;
  1210. int micb_reg, micb_val, micb_en;
  1211. int ret = 0;
  1212. switch (micb_num) {
  1213. case MIC_BIAS_1:
  1214. micb_reg = WCD937X_ANA_MICB1;
  1215. break;
  1216. case MIC_BIAS_2:
  1217. micb_reg = WCD937X_ANA_MICB2;
  1218. break;
  1219. case MIC_BIAS_3:
  1220. micb_reg = WCD937X_ANA_MICB3;
  1221. break;
  1222. default:
  1223. return -EINVAL;
  1224. }
  1225. mutex_lock(&wcd937x->micb_lock);
  1226. /*
  1227. * If requested micbias voltage is same as current micbias
  1228. * voltage, then just return. Otherwise, adjust voltage as
  1229. * per requested value. If micbias is already enabled, then
  1230. * to avoid slow micbias ramp-up or down enable pull-up
  1231. * momentarily, change the micbias value and then re-enable
  1232. * micbias.
  1233. */
  1234. micb_val = snd_soc_component_read(component, micb_reg);
  1235. micb_en = (micb_val & 0xC0) >> 6;
  1236. cur_vout_ctl = micb_val & 0x3F;
  1237. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1238. if (req_vout_ctl < 0) {
  1239. ret = -EINVAL;
  1240. goto exit;
  1241. }
  1242. if (cur_vout_ctl == req_vout_ctl) {
  1243. ret = 0;
  1244. goto exit;
  1245. }
  1246. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1247. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1248. req_volt, micb_en);
  1249. if (micb_en == 0x1)
  1250. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1251. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1252. if (micb_en == 0x1) {
  1253. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1254. /*
  1255. * Add 2ms delay as per HW requirement after enabling
  1256. * micbias
  1257. */
  1258. usleep_range(2000, 2100);
  1259. }
  1260. exit:
  1261. mutex_unlock(&wcd937x->micb_lock);
  1262. return ret;
  1263. }
  1264. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1265. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1266. struct snd_kcontrol *kcontrol,
  1267. int event)
  1268. {
  1269. struct snd_soc_component *component =
  1270. snd_soc_dapm_to_component(w->dapm);
  1271. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1272. int ret = 0;
  1273. switch (event) {
  1274. case SND_SOC_DAPM_PRE_PMU:
  1275. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1276. /* Enable BCS for Headset mic */
  1277. if (w->shift == 1 && !(snd_soc_component_read(component,
  1278. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1279. wcd937x_tx_connect_port(component, MBHC, true);
  1280. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1281. }
  1282. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1283. } else {
  1284. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1285. }
  1286. break;
  1287. case SND_SOC_DAPM_POST_PMD:
  1288. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1289. wcd937x->tx_swr_dev->dev_num,
  1290. false);
  1291. break;
  1292. };
  1293. return ret;
  1294. }
  1295. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1296. struct snd_kcontrol *kcontrol,
  1297. int event){
  1298. struct snd_soc_component *component =
  1299. snd_soc_dapm_to_component(w->dapm);
  1300. struct wcd937x_priv *wcd937x =
  1301. snd_soc_component_get_drvdata(component);
  1302. int ret = 0;
  1303. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1304. w->name, event);
  1305. switch (event) {
  1306. case SND_SOC_DAPM_PRE_PMU:
  1307. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1308. wcd937x->ana_clk_count++;
  1309. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1310. snd_soc_component_update_bits(component,
  1311. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1312. snd_soc_component_update_bits(component,
  1313. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1314. snd_soc_component_update_bits(component,
  1315. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1316. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1317. wcd937x->tx_swr_dev->dev_num,
  1318. true);
  1319. break;
  1320. case SND_SOC_DAPM_POST_PMD:
  1321. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1322. if (w->shift == 1 &&
  1323. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1324. wcd937x_tx_connect_port(component, MBHC, false);
  1325. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1326. }
  1327. snd_soc_component_update_bits(component,
  1328. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1329. break;
  1330. };
  1331. return ret;
  1332. }
  1333. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1334. struct snd_kcontrol *kcontrol, int event)
  1335. {
  1336. struct snd_soc_component *component =
  1337. snd_soc_dapm_to_component(w->dapm);
  1338. struct wcd937x_priv *wcd937x =
  1339. snd_soc_component_get_drvdata(component);
  1340. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1341. w->name, event);
  1342. switch (event) {
  1343. case SND_SOC_DAPM_PRE_PMU:
  1344. snd_soc_component_update_bits(component,
  1345. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1346. snd_soc_component_update_bits(component,
  1347. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1348. snd_soc_component_update_bits(component,
  1349. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1350. snd_soc_component_update_bits(component,
  1351. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1352. snd_soc_component_update_bits(component,
  1353. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1354. snd_soc_component_update_bits(component,
  1355. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1356. snd_soc_component_update_bits(component,
  1357. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1358. snd_soc_component_update_bits(component,
  1359. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1360. snd_soc_component_update_bits(component,
  1361. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1362. break;
  1363. case SND_SOC_DAPM_POST_PMD:
  1364. snd_soc_component_update_bits(component,
  1365. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1366. snd_soc_component_update_bits(component,
  1367. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1368. snd_soc_component_update_bits(component,
  1369. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1370. snd_soc_component_update_bits(component,
  1371. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1372. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1373. wcd937x->ana_clk_count--;
  1374. if (wcd937x->ana_clk_count <= 0) {
  1375. snd_soc_component_update_bits(component,
  1376. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1377. wcd937x->ana_clk_count = 0;
  1378. }
  1379. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1380. snd_soc_component_update_bits(component,
  1381. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1382. break;
  1383. };
  1384. return 0;
  1385. }
  1386. int wcd937x_micbias_control(struct snd_soc_component *component,
  1387. int micb_num, int req, bool is_dapm)
  1388. {
  1389. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1390. int micb_index = micb_num - 1;
  1391. u16 micb_reg;
  1392. int pre_off_event = 0, post_off_event = 0;
  1393. int post_on_event = 0, post_dapm_off = 0;
  1394. int post_dapm_on = 0;
  1395. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1396. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1397. __func__, micb_index);
  1398. return -EINVAL;
  1399. }
  1400. switch (micb_num) {
  1401. case MIC_BIAS_1:
  1402. micb_reg = WCD937X_ANA_MICB1;
  1403. break;
  1404. case MIC_BIAS_2:
  1405. micb_reg = WCD937X_ANA_MICB2;
  1406. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1407. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1408. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1409. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1410. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1411. break;
  1412. case MIC_BIAS_3:
  1413. micb_reg = WCD937X_ANA_MICB3;
  1414. break;
  1415. default:
  1416. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1417. __func__, micb_num);
  1418. return -EINVAL;
  1419. };
  1420. mutex_lock(&wcd937x->micb_lock);
  1421. switch (req) {
  1422. case MICB_PULLUP_ENABLE:
  1423. wcd937x->pullup_ref[micb_index]++;
  1424. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1425. (wcd937x->micb_ref[micb_index] == 0))
  1426. snd_soc_component_update_bits(component, micb_reg,
  1427. 0xC0, 0x80);
  1428. break;
  1429. case MICB_PULLUP_DISABLE:
  1430. if (wcd937x->pullup_ref[micb_index] > 0)
  1431. wcd937x->pullup_ref[micb_index]--;
  1432. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1433. (wcd937x->micb_ref[micb_index] == 0))
  1434. snd_soc_component_update_bits(component, micb_reg,
  1435. 0xC0, 0x00);
  1436. break;
  1437. case MICB_ENABLE:
  1438. wcd937x->micb_ref[micb_index]++;
  1439. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1440. wcd937x->ana_clk_count++;
  1441. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1442. if (wcd937x->micb_ref[micb_index] == 1) {
  1443. snd_soc_component_update_bits(component,
  1444. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1445. snd_soc_component_update_bits(component,
  1446. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1447. snd_soc_component_update_bits(component,
  1448. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1449. snd_soc_component_update_bits(component,
  1450. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1451. snd_soc_component_update_bits(component,
  1452. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1453. snd_soc_component_update_bits(component,
  1454. micb_reg, 0xC0, 0x40);
  1455. if (post_on_event)
  1456. blocking_notifier_call_chain(
  1457. &wcd937x->mbhc->notifier, post_on_event,
  1458. &wcd937x->mbhc->wcd_mbhc);
  1459. }
  1460. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1461. blocking_notifier_call_chain(
  1462. &wcd937x->mbhc->notifier, post_dapm_on,
  1463. &wcd937x->mbhc->wcd_mbhc);
  1464. break;
  1465. case MICB_DISABLE:
  1466. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1467. wcd937x->ana_clk_count--;
  1468. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1469. if (wcd937x->micb_ref[micb_index] > 0)
  1470. wcd937x->micb_ref[micb_index]--;
  1471. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1472. (wcd937x->pullup_ref[micb_index] > 0))
  1473. snd_soc_component_update_bits(component, micb_reg,
  1474. 0xC0, 0x80);
  1475. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1476. (wcd937x->pullup_ref[micb_index] == 0)) {
  1477. if (pre_off_event && wcd937x->mbhc)
  1478. blocking_notifier_call_chain(
  1479. &wcd937x->mbhc->notifier, pre_off_event,
  1480. &wcd937x->mbhc->wcd_mbhc);
  1481. snd_soc_component_update_bits(component, micb_reg,
  1482. 0xC0, 0x00);
  1483. if (post_off_event && wcd937x->mbhc)
  1484. blocking_notifier_call_chain(
  1485. &wcd937x->mbhc->notifier,
  1486. post_off_event,
  1487. &wcd937x->mbhc->wcd_mbhc);
  1488. }
  1489. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1490. if (wcd937x->ana_clk_count <= 0) {
  1491. snd_soc_component_update_bits(component,
  1492. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1493. 0x10, 0x00);
  1494. wcd937x->ana_clk_count = 0;
  1495. }
  1496. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1497. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1498. blocking_notifier_call_chain(
  1499. &wcd937x->mbhc->notifier, post_dapm_off,
  1500. &wcd937x->mbhc->wcd_mbhc);
  1501. break;
  1502. };
  1503. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1504. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1505. wcd937x->pullup_ref[micb_index]);
  1506. mutex_unlock(&wcd937x->micb_lock);
  1507. return 0;
  1508. }
  1509. EXPORT_SYMBOL(wcd937x_micbias_control);
  1510. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1511. bool bcs_disable)
  1512. {
  1513. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1514. if (wcd937x->update_wcd_event) {
  1515. if (bcs_disable)
  1516. wcd937x->update_wcd_event(wcd937x->handle,
  1517. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1518. else
  1519. wcd937x->update_wcd_event(wcd937x->handle,
  1520. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1521. }
  1522. }
  1523. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1524. {
  1525. int ret = 0;
  1526. uint8_t devnum = 0;
  1527. int num_retry = NUM_ATTEMPTS;
  1528. do {
  1529. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1530. if (ret) {
  1531. dev_err(&swr_dev->dev,
  1532. "%s get devnum %d for dev addr %lx failed\n",
  1533. __func__, devnum, swr_dev->addr);
  1534. /* retry after 1ms */
  1535. usleep_range(1000, 1010);
  1536. }
  1537. } while (ret && --num_retry);
  1538. swr_dev->dev_num = devnum;
  1539. return 0;
  1540. }
  1541. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1542. struct wcd_mbhc_config *mbhc_cfg)
  1543. {
  1544. if (mbhc_cfg->enable_usbc_analog) {
  1545. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1546. & 0x20))
  1547. return true;
  1548. }
  1549. return false;
  1550. }
  1551. static int wcd937x_event_notify(struct notifier_block *block,
  1552. unsigned long val,
  1553. void *data)
  1554. {
  1555. u16 event = (val & 0xffff);
  1556. u16 amic = (val >> 0x10);
  1557. u16 mask = 0x40, reg = 0x0;
  1558. int ret = 0;
  1559. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1560. struct snd_soc_component *component = wcd937x->component;
  1561. struct wcd_mbhc *mbhc;
  1562. switch (event) {
  1563. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1564. if (amic == 0x1 || amic == 0x2)
  1565. reg = WCD937X_ANA_TX_CH2;
  1566. else if (amic == 0x3)
  1567. reg = WCD937X_ANA_TX_CH3_HPF;
  1568. else
  1569. return 0;
  1570. if (amic == 0x2)
  1571. mask = 0x20;
  1572. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1573. break;
  1574. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1575. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1576. 0xC0, 0x00);
  1577. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1578. 0x80, 0x00);
  1579. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1580. 0x80, 0x00);
  1581. break;
  1582. case BOLERO_SLV_EVT_SSR_DOWN:
  1583. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1584. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1585. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1586. mbhc->mbhc_cfg);
  1587. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1588. wcd937x_reset_low(wcd937x->dev);
  1589. break;
  1590. case BOLERO_SLV_EVT_SSR_UP:
  1591. wcd937x_reset(wcd937x->dev);
  1592. /* allow reset to take effect */
  1593. usleep_range(10000, 10010);
  1594. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1595. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1596. wcd937x_init_reg(component);
  1597. regcache_mark_dirty(wcd937x->regmap);
  1598. regcache_sync(wcd937x->regmap);
  1599. /* Initialize MBHC module */
  1600. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1601. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1602. if (ret) {
  1603. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1604. __func__);
  1605. } else {
  1606. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1607. if (wcd937x->usbc_hs_status)
  1608. mdelay(500);
  1609. }
  1610. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1611. break;
  1612. default:
  1613. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1614. event);
  1615. break;
  1616. }
  1617. return 0;
  1618. }
  1619. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1620. int event)
  1621. {
  1622. struct snd_soc_component *component =
  1623. snd_soc_dapm_to_component(w->dapm);
  1624. int micb_num;
  1625. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1626. __func__, w->name, event);
  1627. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1628. micb_num = MIC_BIAS_1;
  1629. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1630. micb_num = MIC_BIAS_2;
  1631. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1632. micb_num = MIC_BIAS_3;
  1633. else
  1634. return -EINVAL;
  1635. switch (event) {
  1636. case SND_SOC_DAPM_PRE_PMU:
  1637. wcd937x_micbias_control(component, micb_num,
  1638. MICB_ENABLE, true);
  1639. break;
  1640. case SND_SOC_DAPM_POST_PMU:
  1641. usleep_range(1000, 1100);
  1642. break;
  1643. case SND_SOC_DAPM_POST_PMD:
  1644. wcd937x_micbias_control(component, micb_num,
  1645. MICB_DISABLE, true);
  1646. break;
  1647. };
  1648. return 0;
  1649. }
  1650. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1651. struct snd_kcontrol *kcontrol,
  1652. int event)
  1653. {
  1654. return __wcd937x_codec_enable_micbias(w, event);
  1655. }
  1656. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1657. int event)
  1658. {
  1659. struct snd_soc_component *component =
  1660. snd_soc_dapm_to_component(w->dapm);
  1661. int micb_num;
  1662. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1663. __func__, w->name, event);
  1664. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1665. micb_num = MIC_BIAS_1;
  1666. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1667. micb_num = MIC_BIAS_2;
  1668. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1669. micb_num = MIC_BIAS_3;
  1670. else
  1671. return -EINVAL;
  1672. switch (event) {
  1673. case SND_SOC_DAPM_PRE_PMU:
  1674. wcd937x_micbias_control(component, micb_num,
  1675. MICB_PULLUP_ENABLE, true);
  1676. break;
  1677. case SND_SOC_DAPM_POST_PMU:
  1678. /* 1 msec delay as per HW requirement */
  1679. usleep_range(1000, 1100);
  1680. break;
  1681. case SND_SOC_DAPM_POST_PMD:
  1682. wcd937x_micbias_control(component, micb_num,
  1683. MICB_PULLUP_DISABLE, true);
  1684. break;
  1685. };
  1686. return 0;
  1687. }
  1688. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1689. struct snd_kcontrol *kcontrol,
  1690. int event)
  1691. {
  1692. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1693. }
  1694. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1695. struct snd_ctl_elem_value *ucontrol)
  1696. {
  1697. struct snd_soc_component *component =
  1698. snd_soc_kcontrol_component(kcontrol);
  1699. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1700. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1701. return 0;
  1702. }
  1703. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1704. struct snd_ctl_elem_value *ucontrol)
  1705. {
  1706. struct snd_soc_component *component =
  1707. snd_soc_kcontrol_component(kcontrol);
  1708. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1709. u32 mode_val;
  1710. mode_val = ucontrol->value.enumerated.item[0];
  1711. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1712. if (mode_val == 0) {
  1713. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1714. __func__);
  1715. mode_val = 3; /* enum will be updated later */
  1716. }
  1717. wcd937x->hph_mode = mode_val;
  1718. return 0;
  1719. }
  1720. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1721. struct snd_ctl_elem_value *ucontrol)
  1722. {
  1723. struct snd_soc_component *component =
  1724. snd_soc_kcontrol_component(kcontrol);
  1725. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1726. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1727. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1728. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1729. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1730. return 0;
  1731. }
  1732. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1733. struct snd_ctl_elem_value *ucontrol)
  1734. {
  1735. struct snd_soc_component *component =
  1736. snd_soc_kcontrol_component(kcontrol);
  1737. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1738. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1739. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1740. __func__, pwr_level);
  1741. if (strnstr(kcontrol->id.name, "CH1",
  1742. sizeof(kcontrol->id.name))) {
  1743. snd_soc_component_update_bits(component,
  1744. WCD937X_ANA_TX_CH1, 0x60,
  1745. pwr_level << 0x5);
  1746. wcd937x->tx_ch_pwr[0] = pwr_level;
  1747. } else if (strnstr(kcontrol->id.name, "CH3",
  1748. sizeof(kcontrol->id.name))) {
  1749. snd_soc_component_update_bits(component,
  1750. WCD937X_ANA_TX_CH3, 0x60,
  1751. pwr_level << 0x5);
  1752. wcd937x->tx_ch_pwr[1] = pwr_level;
  1753. }
  1754. return 0;
  1755. }
  1756. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. u8 ear_pa_gain = 0;
  1760. struct snd_soc_component *component =
  1761. snd_soc_kcontrol_component(kcontrol);
  1762. ear_pa_gain = snd_soc_component_read(component,
  1763. WCD937X_ANA_EAR_COMPANDER_CTL);
  1764. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1765. ucontrol->value.integer.value[0] = ear_pa_gain;
  1766. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1767. ear_pa_gain);
  1768. return 0;
  1769. }
  1770. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1771. struct snd_ctl_elem_value *ucontrol)
  1772. {
  1773. u8 ear_pa_gain = 0;
  1774. struct snd_soc_component *component =
  1775. snd_soc_kcontrol_component(kcontrol);
  1776. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1777. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1778. __func__, ucontrol->value.integer.value[0]);
  1779. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1780. if (!wcd937x->comp1_enable) {
  1781. snd_soc_component_update_bits(component,
  1782. WCD937X_ANA_EAR_COMPANDER_CTL,
  1783. 0x7C, ear_pa_gain);
  1784. }
  1785. return 0;
  1786. }
  1787. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1788. struct snd_ctl_elem_value *ucontrol)
  1789. {
  1790. struct snd_soc_component *component =
  1791. snd_soc_kcontrol_component(kcontrol);
  1792. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1793. bool hphr;
  1794. struct soc_multi_mixer_control *mc;
  1795. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1796. hphr = mc->shift;
  1797. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1798. wcd937x->comp1_enable;
  1799. return 0;
  1800. }
  1801. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1802. struct snd_ctl_elem_value *ucontrol)
  1803. {
  1804. struct snd_soc_component *component =
  1805. snd_soc_kcontrol_component(kcontrol);
  1806. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1807. int value = ucontrol->value.integer.value[0];
  1808. bool hphr;
  1809. struct soc_multi_mixer_control *mc;
  1810. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1811. hphr = mc->shift;
  1812. if (hphr)
  1813. wcd937x->comp2_enable = value;
  1814. else
  1815. wcd937x->comp1_enable = value;
  1816. return 0;
  1817. }
  1818. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1819. struct snd_kcontrol *kcontrol,
  1820. int event)
  1821. {
  1822. struct snd_soc_component *component =
  1823. snd_soc_dapm_to_component(w->dapm);
  1824. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1825. struct wcd937x_pdata *pdata = NULL;
  1826. int ret = 0;
  1827. pdata = dev_get_platdata(wcd937x->dev);
  1828. if (!pdata) {
  1829. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1830. return -EINVAL;
  1831. }
  1832. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1833. w->name, event);
  1834. switch (event) {
  1835. case SND_SOC_DAPM_PRE_PMU:
  1836. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1837. dev_dbg(component->dev,
  1838. "%s: buck already in enabled state\n",
  1839. __func__);
  1840. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1841. return 0;
  1842. }
  1843. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1844. wcd937x->supplies,
  1845. pdata->regulator,
  1846. pdata->num_supplies,
  1847. "cdc-vdd-buck");
  1848. if (ret == -EINVAL) {
  1849. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1850. __func__);
  1851. return ret;
  1852. }
  1853. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1854. /*
  1855. * 200us sleep is required after LDO15 is enabled as per
  1856. * HW requirement
  1857. */
  1858. usleep_range(200, 250);
  1859. break;
  1860. case SND_SOC_DAPM_POST_PMD:
  1861. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1862. break;
  1863. }
  1864. return 0;
  1865. }
  1866. static const char * const rx_hph_mode_mux_text[] = {
  1867. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1868. "CLS_H_ULP", "CLS_AB_HIFI",
  1869. };
  1870. const char * const tx_master_ch_text[] = {
  1871. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1872. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1873. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1874. "SWRM_PCM_IN",
  1875. };
  1876. const struct soc_enum tx_master_ch_enum =
  1877. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1878. tx_master_ch_text);
  1879. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1880. {
  1881. u8 ch_type = 0;
  1882. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1883. ch_type = ADC1;
  1884. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1885. ch_type = ADC2;
  1886. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1887. ch_type = ADC3;
  1888. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1889. ch_type = DMIC0;
  1890. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1891. ch_type = DMIC1;
  1892. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1893. ch_type = MBHC;
  1894. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1895. ch_type = DMIC2;
  1896. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1897. ch_type = DMIC3;
  1898. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1899. ch_type = DMIC4;
  1900. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1901. ch_type = DMIC5;
  1902. else
  1903. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1904. if (ch_type)
  1905. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1906. else
  1907. *ch_idx = -EINVAL;
  1908. }
  1909. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1910. struct snd_ctl_elem_value *ucontrol)
  1911. {
  1912. struct snd_soc_component *component =
  1913. snd_soc_kcontrol_component(kcontrol);
  1914. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1915. int slave_ch_idx;
  1916. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1917. if (slave_ch_idx != -EINVAL)
  1918. ucontrol->value.integer.value[0] =
  1919. wcd937x_slave_get_master_ch_val(
  1920. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1921. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1922. __func__, ucontrol->value.integer.value[0]);
  1923. return 0;
  1924. }
  1925. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1926. struct snd_ctl_elem_value *ucontrol)
  1927. {
  1928. struct snd_soc_component *component =
  1929. snd_soc_kcontrol_component(kcontrol);
  1930. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1931. int slave_ch_idx;
  1932. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1933. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1934. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1935. __func__, ucontrol->value.enumerated.item[0]);
  1936. if (slave_ch_idx != -EINVAL)
  1937. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1938. wcd937x_slave_get_master_ch(
  1939. ucontrol->value.enumerated.item[0]);
  1940. return 0;
  1941. }
  1942. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1943. "L0", "L1", "L2", "L3",
  1944. };
  1945. static const char * const wcd937x_ear_pa_gain_text[] = {
  1946. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1947. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1948. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1949. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1950. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1951. };
  1952. static const struct soc_enum rx_hph_mode_mux_enum =
  1953. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1954. rx_hph_mode_mux_text);
  1955. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1956. wcd937x_ear_pa_gain_text);
  1957. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1958. wcd937x_tx_ch_pwr_level_text);
  1959. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1960. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1961. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1962. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1963. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1964. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1965. wcd937x_get_compander, wcd937x_set_compander),
  1966. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1967. wcd937x_get_compander, wcd937x_set_compander),
  1968. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1969. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1970. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1971. analog_gain),
  1972. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1973. analog_gain),
  1974. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1975. analog_gain),
  1976. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1977. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1978. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1979. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1980. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1981. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1982. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1983. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1984. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1985. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1986. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1987. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1988. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1989. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1990. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1991. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1992. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1993. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1994. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1995. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1996. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  1997. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1998. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  1999. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2000. };
  2001. static const struct snd_kcontrol_new adc1_switch[] = {
  2002. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2003. };
  2004. static const struct snd_kcontrol_new adc2_switch[] = {
  2005. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2006. };
  2007. static const struct snd_kcontrol_new adc3_switch[] = {
  2008. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2009. };
  2010. static const struct snd_kcontrol_new dmic1_switch[] = {
  2011. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2012. };
  2013. static const struct snd_kcontrol_new dmic2_switch[] = {
  2014. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2015. };
  2016. static const struct snd_kcontrol_new dmic3_switch[] = {
  2017. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2018. };
  2019. static const struct snd_kcontrol_new dmic4_switch[] = {
  2020. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2021. };
  2022. static const struct snd_kcontrol_new dmic5_switch[] = {
  2023. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2024. };
  2025. static const struct snd_kcontrol_new dmic6_switch[] = {
  2026. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2027. };
  2028. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2029. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2030. };
  2031. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2032. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2033. };
  2034. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2035. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2036. };
  2037. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2038. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2039. };
  2040. static const char * const adc2_mux_text[] = {
  2041. "INP2", "INP3"
  2042. };
  2043. static const char * const rdac3_mux_text[] = {
  2044. "RX1", "RX3"
  2045. };
  2046. static const struct soc_enum adc2_enum =
  2047. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2048. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2049. static const struct soc_enum rdac3_enum =
  2050. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2051. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2052. static const struct snd_kcontrol_new tx_adc2_mux =
  2053. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2054. static const struct snd_kcontrol_new rx_rdac3_mux =
  2055. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2056. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2057. /*input widgets*/
  2058. SND_SOC_DAPM_INPUT("AMIC1"),
  2059. SND_SOC_DAPM_INPUT("AMIC2"),
  2060. SND_SOC_DAPM_INPUT("AMIC3"),
  2061. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2062. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2063. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2064. /*
  2065. * These dummy widgets are null connected to WCD937x dapm input and
  2066. * output widgets which are not actual path endpoints. This ensures
  2067. * dapm doesnt set these dapm input and output widgets as endpoints.
  2068. */
  2069. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2070. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2071. /*tx widgets*/
  2072. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2073. wcd937x_codec_enable_adc,
  2074. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2075. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2076. wcd937x_codec_enable_adc,
  2077. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2078. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2079. NULL, 0, wcd937x_enable_req,
  2080. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2081. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2082. NULL, 0, wcd937x_enable_req,
  2083. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2084. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2085. &tx_adc2_mux),
  2086. /*tx mixers*/
  2087. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2088. adc1_switch, ARRAY_SIZE(adc1_switch),
  2089. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2090. SND_SOC_DAPM_POST_PMD),
  2091. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2092. adc2_switch, ARRAY_SIZE(adc2_switch),
  2093. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2094. SND_SOC_DAPM_POST_PMD),
  2095. /* micbias widgets*/
  2096. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2097. wcd937x_codec_enable_micbias,
  2098. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2099. SND_SOC_DAPM_POST_PMD),
  2100. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2101. wcd937x_codec_enable_micbias,
  2102. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2103. SND_SOC_DAPM_POST_PMD),
  2104. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2105. wcd937x_codec_enable_micbias,
  2106. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2107. SND_SOC_DAPM_POST_PMD),
  2108. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2109. wcd937x_codec_enable_vdd_buck,
  2110. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2111. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2112. wcd937x_enable_clsh,
  2113. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2114. /*rx widgets*/
  2115. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2116. wcd937x_codec_enable_ear_pa,
  2117. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2118. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2119. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2120. wcd937x_codec_enable_aux_pa,
  2121. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2122. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2123. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2124. wcd937x_codec_enable_hphl_pa,
  2125. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2126. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2127. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2128. wcd937x_codec_enable_hphr_pa,
  2129. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2130. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2131. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2132. wcd937x_codec_hphl_dac_event,
  2133. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2134. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2135. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2136. wcd937x_codec_hphr_dac_event,
  2137. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2138. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2139. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2140. wcd937x_codec_ear_dac_event,
  2141. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2142. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2143. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2144. wcd937x_codec_aux_dac_event,
  2145. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2146. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2147. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2148. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2149. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2150. SND_SOC_DAPM_POST_PMD),
  2151. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2152. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2153. SND_SOC_DAPM_POST_PMD),
  2154. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2155. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2156. SND_SOC_DAPM_POST_PMD),
  2157. /* rx mixer widgets*/
  2158. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2159. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2160. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2161. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2162. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2163. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2164. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2165. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2166. /*output widgets tx*/
  2167. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2168. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2169. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2170. /*output widgets rx*/
  2171. SND_SOC_DAPM_OUTPUT("EAR"),
  2172. SND_SOC_DAPM_OUTPUT("AUX"),
  2173. SND_SOC_DAPM_OUTPUT("HPHL"),
  2174. SND_SOC_DAPM_OUTPUT("HPHR"),
  2175. /* micbias pull up widgets*/
  2176. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2177. wcd937x_codec_enable_micbias_pullup,
  2178. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2179. SND_SOC_DAPM_POST_PMD),
  2180. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2181. wcd937x_codec_enable_micbias_pullup,
  2182. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2183. SND_SOC_DAPM_POST_PMD),
  2184. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2185. wcd937x_codec_enable_micbias_pullup,
  2186. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2187. SND_SOC_DAPM_POST_PMD),
  2188. };
  2189. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2190. /*input widgets*/
  2191. SND_SOC_DAPM_INPUT("AMIC4"),
  2192. /*tx widgets*/
  2193. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2194. wcd937x_codec_enable_adc,
  2195. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2196. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2197. NULL, 0, wcd937x_enable_req,
  2198. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2199. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2200. wcd937x_codec_enable_dmic,
  2201. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2202. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2203. wcd937x_codec_enable_dmic,
  2204. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2205. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2206. wcd937x_codec_enable_dmic,
  2207. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2208. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2209. wcd937x_codec_enable_dmic,
  2210. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2211. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2212. wcd937x_codec_enable_dmic,
  2213. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2214. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2215. wcd937x_codec_enable_dmic,
  2216. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2217. /*tx mixer widgets*/
  2218. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2219. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2220. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2221. SND_SOC_DAPM_POST_PMD),
  2222. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2223. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2224. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2225. SND_SOC_DAPM_POST_PMD),
  2226. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2227. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2228. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2229. SND_SOC_DAPM_POST_PMD),
  2230. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2231. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2232. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2233. SND_SOC_DAPM_POST_PMD),
  2234. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2235. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2236. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2237. SND_SOC_DAPM_POST_PMD),
  2238. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2239. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2240. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2241. SND_SOC_DAPM_POST_PMD),
  2242. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2243. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2244. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2245. /*output widgets*/
  2246. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2247. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2248. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2249. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2250. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2251. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2252. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2253. };
  2254. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2255. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2256. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2257. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2258. {"ADC1 REQ", NULL, "ADC1"},
  2259. {"ADC1", NULL, "AMIC1"},
  2260. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2261. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2262. {"ADC2 REQ", NULL, "ADC2"},
  2263. {"ADC2", NULL, "ADC2 MUX"},
  2264. {"ADC2 MUX", "INP3", "AMIC3"},
  2265. {"ADC2 MUX", "INP2", "AMIC2"},
  2266. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2267. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2268. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2269. {"RX1", NULL, "IN1_HPHL"},
  2270. {"RDAC1", NULL, "RX1"},
  2271. {"HPHL_RDAC", "Switch", "RDAC1"},
  2272. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2273. {"HPHL", NULL, "HPHL PGA"},
  2274. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2275. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2276. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2277. {"RX2", NULL, "IN2_HPHR"},
  2278. {"RDAC2", NULL, "RX2"},
  2279. {"HPHR_RDAC", "Switch", "RDAC2"},
  2280. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2281. {"HPHR", NULL, "HPHR PGA"},
  2282. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2283. {"IN3_AUX", NULL, "VDD_BUCK"},
  2284. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2285. {"RX3", NULL, "IN3_AUX"},
  2286. {"RDAC4", NULL, "RX3"},
  2287. {"AUX_RDAC", "Switch", "RDAC4"},
  2288. {"AUX PGA", NULL, "AUX_RDAC"},
  2289. {"AUX", NULL, "AUX PGA"},
  2290. {"RDAC3_MUX", "RX3", "RX3"},
  2291. {"RDAC3_MUX", "RX1", "RX1"},
  2292. {"RDAC3", NULL, "RDAC3_MUX"},
  2293. {"EAR_RDAC", "Switch", "RDAC3"},
  2294. {"EAR PGA", NULL, "EAR_RDAC"},
  2295. {"EAR", NULL, "EAR PGA"},
  2296. };
  2297. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2298. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2299. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2300. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2301. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2302. {"ADC3 REQ", NULL, "ADC3"},
  2303. {"ADC3", NULL, "AMIC4"},
  2304. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2305. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2306. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2307. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2308. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2309. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2310. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2311. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2312. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2313. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2314. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2315. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2316. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2317. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2318. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2319. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2320. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2321. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2322. };
  2323. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2324. void *file_private_data,
  2325. struct file *file,
  2326. char __user *buf, size_t count,
  2327. loff_t pos)
  2328. {
  2329. struct wcd937x_priv *priv;
  2330. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2331. int len = 0;
  2332. priv = (struct wcd937x_priv *) entry->private_data;
  2333. if (!priv) {
  2334. pr_err("%s: wcd937x priv is null\n", __func__);
  2335. return -EINVAL;
  2336. }
  2337. switch (priv->version) {
  2338. case WCD937X_VERSION_1_0:
  2339. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2340. break;
  2341. default:
  2342. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2343. }
  2344. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2345. }
  2346. static struct snd_info_entry_ops wcd937x_info_ops = {
  2347. .read = wcd937x_version_read,
  2348. };
  2349. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2350. void *file_private_data,
  2351. struct file *file,
  2352. char __user *buf, size_t count,
  2353. loff_t pos)
  2354. {
  2355. struct wcd937x_priv *priv;
  2356. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2357. int len = 0;
  2358. priv = (struct wcd937x_priv *) entry->private_data;
  2359. if (!priv) {
  2360. pr_err("%s: wcd937x priv is null\n", __func__);
  2361. return -EINVAL;
  2362. }
  2363. switch (priv->variant) {
  2364. case WCD9370_VARIANT:
  2365. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2366. break;
  2367. case WCD9375_VARIANT:
  2368. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2369. break;
  2370. default:
  2371. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2372. }
  2373. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2374. }
  2375. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2376. .read = wcd937x_variant_read,
  2377. };
  2378. /*
  2379. * wcd937x_info_create_codec_entry - creates wcd937x module
  2380. * @codec_root: The parent directory
  2381. * @component: component instance
  2382. *
  2383. * Creates wcd937x module, variant and version entry under the given
  2384. * parent directory.
  2385. *
  2386. * Return: 0 on success or negative error code on failure.
  2387. */
  2388. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2389. struct snd_soc_component *component)
  2390. {
  2391. struct snd_info_entry *version_entry;
  2392. struct snd_info_entry *variant_entry;
  2393. struct wcd937x_priv *priv;
  2394. struct snd_soc_card *card;
  2395. if (!codec_root || !component)
  2396. return -EINVAL;
  2397. priv = snd_soc_component_get_drvdata(component);
  2398. if (priv->entry) {
  2399. dev_dbg(priv->dev,
  2400. "%s:wcd937x module already created\n", __func__);
  2401. return 0;
  2402. }
  2403. card = component->card;
  2404. priv->entry = snd_info_create_module_entry(codec_root->module,
  2405. "wcd937x", codec_root);
  2406. if (!priv->entry) {
  2407. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2408. __func__);
  2409. return -ENOMEM;
  2410. }
  2411. priv->entry->mode = S_IFDIR | 0555;
  2412. if (snd_info_register(priv->entry) < 0) {
  2413. snd_info_free_entry(priv->entry);
  2414. return -ENOMEM;
  2415. }
  2416. version_entry = snd_info_create_card_entry(card->snd_card,
  2417. "version",
  2418. priv->entry);
  2419. if (!version_entry) {
  2420. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2421. __func__);
  2422. snd_info_free_entry(priv->entry);
  2423. return -ENOMEM;
  2424. }
  2425. version_entry->private_data = priv;
  2426. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2427. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2428. version_entry->c.ops = &wcd937x_info_ops;
  2429. if (snd_info_register(version_entry) < 0) {
  2430. snd_info_free_entry(version_entry);
  2431. snd_info_free_entry(priv->entry);
  2432. return -ENOMEM;
  2433. }
  2434. priv->version_entry = version_entry;
  2435. variant_entry = snd_info_create_card_entry(card->snd_card,
  2436. "variant",
  2437. priv->entry);
  2438. if (!variant_entry) {
  2439. dev_dbg(component->dev,
  2440. "%s: failed to create wcd937x variant entry\n",
  2441. __func__);
  2442. snd_info_free_entry(version_entry);
  2443. snd_info_free_entry(priv->entry);
  2444. return -ENOMEM;
  2445. }
  2446. variant_entry->private_data = priv;
  2447. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2448. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2449. variant_entry->c.ops = &wcd937x_variant_ops;
  2450. if (snd_info_register(variant_entry) < 0) {
  2451. snd_info_free_entry(variant_entry);
  2452. snd_info_free_entry(version_entry);
  2453. snd_info_free_entry(priv->entry);
  2454. return -ENOMEM;
  2455. }
  2456. priv->variant_entry = variant_entry;
  2457. return 0;
  2458. }
  2459. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2460. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2461. struct wcd937x_pdata *pdata)
  2462. {
  2463. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2464. int rc = 0;
  2465. if (!pdata) {
  2466. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2467. return -ENODEV;
  2468. }
  2469. /* set micbias voltage */
  2470. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2471. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2472. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2473. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2474. rc = -EINVAL;
  2475. goto done;
  2476. }
  2477. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2478. vout_ctl_1);
  2479. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2480. vout_ctl_2);
  2481. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2482. vout_ctl_3);
  2483. done:
  2484. return rc;
  2485. }
  2486. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2487. {
  2488. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2489. struct snd_soc_dapm_context *dapm =
  2490. snd_soc_component_get_dapm(component);
  2491. int variant;
  2492. int ret = -EINVAL;
  2493. dev_info(component->dev, "%s()\n", __func__);
  2494. wcd937x = snd_soc_component_get_drvdata(component);
  2495. if (!wcd937x)
  2496. return -EINVAL;
  2497. wcd937x->component = component;
  2498. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2499. variant = (snd_soc_component_read(
  2500. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2501. wcd937x->variant = variant;
  2502. wcd937x->fw_data = devm_kzalloc(component->dev,
  2503. sizeof(*(wcd937x->fw_data)),
  2504. GFP_KERNEL);
  2505. if (!wcd937x->fw_data) {
  2506. dev_err(component->dev, "Failed to allocate fw_data\n");
  2507. ret = -ENOMEM;
  2508. goto err;
  2509. }
  2510. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2511. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2512. WCD9XXX_CODEC_HWDEP_NODE, component);
  2513. if (ret < 0) {
  2514. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2515. goto err_hwdep;
  2516. }
  2517. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2518. if (ret) {
  2519. pr_err("%s: mbhc initialization failed\n", __func__);
  2520. goto err_hwdep;
  2521. }
  2522. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2523. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2524. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2525. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2526. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2527. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2528. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2529. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2530. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2531. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2532. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2533. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2534. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2535. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2536. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2537. snd_soc_dapm_sync(dapm);
  2538. wcd_cls_h_init(&wcd937x->clsh_info);
  2539. wcd937x_init_reg(component);
  2540. if (wcd937x->variant == WCD9375_VARIANT) {
  2541. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2542. ARRAY_SIZE(wcd9375_dapm_widgets));
  2543. if (ret < 0) {
  2544. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2545. __func__);
  2546. goto err_hwdep;
  2547. }
  2548. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2549. ARRAY_SIZE(wcd9375_audio_map));
  2550. if (ret < 0) {
  2551. dev_err(component->dev, "%s: Failed to add routes\n",
  2552. __func__);
  2553. goto err_hwdep;
  2554. }
  2555. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2556. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2557. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2558. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2559. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2560. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2561. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2562. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2563. snd_soc_dapm_sync(dapm);
  2564. }
  2565. wcd937x->version = WCD937X_VERSION_1_0;
  2566. /* Register event notifier */
  2567. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2568. if (wcd937x->register_notifier) {
  2569. ret = wcd937x->register_notifier(wcd937x->handle,
  2570. &wcd937x->nblock,
  2571. true);
  2572. if (ret) {
  2573. dev_err(component->dev,
  2574. "%s: Failed to register notifier %d\n",
  2575. __func__, ret);
  2576. return ret;
  2577. }
  2578. }
  2579. return ret;
  2580. err_hwdep:
  2581. wcd937x->fw_data = NULL;
  2582. err:
  2583. return ret;
  2584. }
  2585. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2586. {
  2587. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2588. if (!wcd937x)
  2589. return;
  2590. if (wcd937x->register_notifier)
  2591. wcd937x->register_notifier(wcd937x->handle,
  2592. &wcd937x->nblock,
  2593. false);
  2594. return;
  2595. }
  2596. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2597. .name = WCD937X_DRV_NAME,
  2598. .probe = wcd937x_soc_codec_probe,
  2599. .remove = wcd937x_soc_codec_remove,
  2600. .controls = wcd937x_snd_controls,
  2601. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2602. .dapm_widgets = wcd937x_dapm_widgets,
  2603. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2604. .dapm_routes = wcd937x_audio_map,
  2605. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2606. };
  2607. #ifdef CONFIG_PM_SLEEP
  2608. static int wcd937x_suspend(struct device *dev)
  2609. {
  2610. struct wcd937x_priv *wcd937x = NULL;
  2611. int ret = 0;
  2612. struct wcd937x_pdata *pdata = NULL;
  2613. if (!dev)
  2614. return -ENODEV;
  2615. wcd937x = dev_get_drvdata(dev);
  2616. if (!wcd937x)
  2617. return -EINVAL;
  2618. pdata = dev_get_platdata(wcd937x->dev);
  2619. if (!pdata) {
  2620. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2621. return -EINVAL;
  2622. }
  2623. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2624. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2625. wcd937x->supplies,
  2626. pdata->regulator,
  2627. pdata->num_supplies,
  2628. "cdc-vdd-buck");
  2629. if (ret == -EINVAL) {
  2630. dev_err(dev, "%s: vdd buck is not disabled\n",
  2631. __func__);
  2632. return 0;
  2633. }
  2634. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2635. }
  2636. return 0;
  2637. }
  2638. static int wcd937x_resume(struct device *dev)
  2639. {
  2640. return 0;
  2641. }
  2642. #endif
  2643. static int wcd937x_reset(struct device *dev)
  2644. {
  2645. struct wcd937x_priv *wcd937x = NULL;
  2646. int rc = 0;
  2647. int value = 0;
  2648. if (!dev)
  2649. return -ENODEV;
  2650. wcd937x = dev_get_drvdata(dev);
  2651. if (!wcd937x)
  2652. return -EINVAL;
  2653. if (!wcd937x->rst_np) {
  2654. dev_err(dev, "%s: reset gpio device node not specified\n",
  2655. __func__);
  2656. return -EINVAL;
  2657. }
  2658. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2659. if (value > 0)
  2660. return 0;
  2661. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2662. if (rc) {
  2663. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2664. __func__);
  2665. return rc;
  2666. }
  2667. /* 20ms sleep required after pulling the reset gpio to LOW */
  2668. usleep_range(20, 30);
  2669. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2670. if (rc) {
  2671. dev_err(dev, "%s: wcd active state request fail!\n",
  2672. __func__);
  2673. return rc;
  2674. }
  2675. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2676. usleep_range(20, 30);
  2677. return rc;
  2678. }
  2679. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2680. u32 *val)
  2681. {
  2682. int rc = 0;
  2683. rc = of_property_read_u32(dev->of_node, name, val);
  2684. if (rc)
  2685. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2686. __func__, name, dev->of_node->full_name);
  2687. return rc;
  2688. }
  2689. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2690. struct wcd937x_micbias_setting *mb)
  2691. {
  2692. u32 prop_val = 0;
  2693. int rc = 0;
  2694. /* MB1 */
  2695. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2696. NULL)) {
  2697. rc = wcd937x_read_of_property_u32(dev,
  2698. "qcom,cdc-micbias1-mv",
  2699. &prop_val);
  2700. if (!rc)
  2701. mb->micb1_mv = prop_val;
  2702. } else {
  2703. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2704. __func__);
  2705. }
  2706. /* MB2 */
  2707. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2708. NULL)) {
  2709. rc = wcd937x_read_of_property_u32(dev,
  2710. "qcom,cdc-micbias2-mv",
  2711. &prop_val);
  2712. if (!rc)
  2713. mb->micb2_mv = prop_val;
  2714. } else {
  2715. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2716. __func__);
  2717. }
  2718. /* MB3 */
  2719. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2720. NULL)) {
  2721. rc = wcd937x_read_of_property_u32(dev,
  2722. "qcom,cdc-micbias3-mv",
  2723. &prop_val);
  2724. if (!rc)
  2725. mb->micb3_mv = prop_val;
  2726. } else {
  2727. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2728. __func__);
  2729. }
  2730. }
  2731. static int wcd937x_reset_low(struct device *dev)
  2732. {
  2733. struct wcd937x_priv *wcd937x = NULL;
  2734. int rc = 0;
  2735. if (!dev)
  2736. return -ENODEV;
  2737. wcd937x = dev_get_drvdata(dev);
  2738. if (!wcd937x)
  2739. return -EINVAL;
  2740. if (!wcd937x->rst_np) {
  2741. dev_err(dev, "%s: reset gpio device node not specified\n",
  2742. __func__);
  2743. return -EINVAL;
  2744. }
  2745. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2746. if (rc) {
  2747. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2748. __func__);
  2749. return rc;
  2750. }
  2751. /* 20ms sleep required after pulling the reset gpio to LOW */
  2752. usleep_range(20, 30);
  2753. return rc;
  2754. }
  2755. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2756. {
  2757. struct wcd937x_pdata *pdata = NULL;
  2758. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2759. GFP_KERNEL);
  2760. if (!pdata)
  2761. return NULL;
  2762. pdata->rst_np = of_parse_phandle(dev->of_node,
  2763. "qcom,wcd-rst-gpio-node", 0);
  2764. if (!pdata->rst_np) {
  2765. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2766. __func__, "qcom,wcd-rst-gpio-node",
  2767. dev->of_node->full_name);
  2768. return NULL;
  2769. }
  2770. /* Parse power supplies */
  2771. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2772. &pdata->num_supplies);
  2773. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2774. dev_err(dev, "%s: no power supplies defined for codec\n",
  2775. __func__);
  2776. return NULL;
  2777. }
  2778. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2779. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2780. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2781. return pdata;
  2782. }
  2783. static int wcd937x_wakeup(void *handle, bool enable)
  2784. {
  2785. struct wcd937x_priv *priv;
  2786. if (!handle) {
  2787. pr_err("%s: NULL handle\n", __func__);
  2788. return -EINVAL;
  2789. }
  2790. priv = (struct wcd937x_priv *)handle;
  2791. if (!priv->tx_swr_dev) {
  2792. pr_err("%s: tx swr dev is NULL\n", __func__);
  2793. return -EINVAL;
  2794. }
  2795. if (enable)
  2796. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2797. else
  2798. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2799. }
  2800. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2801. {
  2802. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2803. __func__, irq);
  2804. return IRQ_HANDLED;
  2805. }
  2806. static int wcd937x_bind(struct device *dev)
  2807. {
  2808. int ret = 0, i = 0;
  2809. struct wcd937x_priv *wcd937x = NULL;
  2810. struct wcd937x_pdata *pdata = NULL;
  2811. struct wcd_ctrl_platform_data *plat_data = NULL;
  2812. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2813. if (!wcd937x)
  2814. return -ENOMEM;
  2815. dev_set_drvdata(dev, wcd937x);
  2816. pdata = wcd937x_populate_dt_data(dev);
  2817. if (!pdata) {
  2818. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2819. return -EINVAL;
  2820. }
  2821. wcd937x->dev = dev;
  2822. wcd937x->dev->platform_data = pdata;
  2823. wcd937x->rst_np = pdata->rst_np;
  2824. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2825. pdata->regulator, pdata->num_supplies);
  2826. if (!wcd937x->supplies) {
  2827. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2828. __func__);
  2829. goto err_bind_all;
  2830. }
  2831. plat_data = dev_get_platdata(dev->parent);
  2832. if (!plat_data) {
  2833. dev_err(dev, "%s: platform data from parent is NULL\n",
  2834. __func__);
  2835. ret = -EINVAL;
  2836. goto err_bind_all;
  2837. }
  2838. wcd937x->handle = (void *)plat_data->handle;
  2839. if (!wcd937x->handle) {
  2840. dev_err(dev, "%s: handle is NULL\n", __func__);
  2841. ret = -EINVAL;
  2842. goto err_bind_all;
  2843. }
  2844. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2845. if (!wcd937x->update_wcd_event) {
  2846. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2847. __func__);
  2848. ret = -EINVAL;
  2849. goto err_bind_all;
  2850. }
  2851. wcd937x->register_notifier = plat_data->register_notifier;
  2852. if (!wcd937x->register_notifier) {
  2853. dev_err(dev, "%s: register_notifier api is null!\n",
  2854. __func__);
  2855. ret = -EINVAL;
  2856. goto err_bind_all;
  2857. }
  2858. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2859. pdata->regulator,
  2860. pdata->num_supplies);
  2861. if (ret) {
  2862. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2863. __func__);
  2864. goto err_bind_all;
  2865. }
  2866. wcd937x_reset(dev);
  2867. /*
  2868. * Add 5msec delay to provide sufficient time for
  2869. * soundwire auto enumeration of slave devices as
  2870. * as per HW requirement.
  2871. */
  2872. usleep_range(5000, 5010);
  2873. wcd937x->wakeup = wcd937x_wakeup;
  2874. ret = component_bind_all(dev, wcd937x);
  2875. if (ret) {
  2876. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2877. __func__, ret);
  2878. goto err_bind_all;
  2879. }
  2880. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2881. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2882. if (ret) {
  2883. dev_err(dev, "Failed to read port mapping\n");
  2884. goto err;
  2885. }
  2886. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  2887. CODEC_TX);
  2888. if (ret) {
  2889. dev_err(dev, "Failed to read port params\n");
  2890. goto err;
  2891. }
  2892. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2893. if (!wcd937x->rx_swr_dev) {
  2894. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2895. __func__);
  2896. ret = -ENODEV;
  2897. goto err;
  2898. }
  2899. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2900. if (!wcd937x->tx_swr_dev) {
  2901. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2902. __func__);
  2903. ret = -ENODEV;
  2904. goto err;
  2905. }
  2906. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  2907. wcd937x->swr_tx_port_params);
  2908. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2909. &wcd937x_regmap_config);
  2910. if (!wcd937x->regmap) {
  2911. dev_err(dev, "%s: Regmap init failed\n",
  2912. __func__);
  2913. goto err;
  2914. }
  2915. /* Set all interupts as edge triggered */
  2916. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2917. regmap_write(wcd937x->regmap,
  2918. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2919. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2920. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2921. wcd937x->irq_info.codec_name = "WCD937X";
  2922. wcd937x->irq_info.regmap = wcd937x->regmap;
  2923. wcd937x->irq_info.dev = dev;
  2924. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2925. if (ret) {
  2926. dev_err(dev, "%s: IRQ init failed: %d\n",
  2927. __func__, ret);
  2928. goto err;
  2929. }
  2930. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2931. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2932. if (ret < 0) {
  2933. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2934. goto err_irq;
  2935. }
  2936. /* default L1 power setting */
  2937. wcd937x->tx_ch_pwr[0] = 1;
  2938. wcd937x->tx_ch_pwr[1] = 1;
  2939. mutex_init(&wcd937x->micb_lock);
  2940. mutex_init(&wcd937x->ana_tx_clk_lock);
  2941. /* Request for watchdog interrupt */
  2942. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2943. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2944. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2945. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2946. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2947. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2948. /* Disable watchdog interrupt for HPH and AUX */
  2949. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2950. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2951. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2952. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2953. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2954. if (ret) {
  2955. dev_err(dev, "%s: Codec registration failed\n",
  2956. __func__);
  2957. goto err_irq;
  2958. }
  2959. return ret;
  2960. err_irq:
  2961. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2962. err:
  2963. component_unbind_all(dev, wcd937x);
  2964. err_bind_all:
  2965. dev_set_drvdata(dev, NULL);
  2966. kfree(pdata);
  2967. kfree(wcd937x);
  2968. return ret;
  2969. }
  2970. static void wcd937x_unbind(struct device *dev)
  2971. {
  2972. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2973. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2974. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2975. snd_soc_unregister_component(dev);
  2976. component_unbind_all(dev, wcd937x);
  2977. mutex_destroy(&wcd937x->micb_lock);
  2978. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2979. dev_set_drvdata(dev, NULL);
  2980. kfree(pdata);
  2981. kfree(wcd937x);
  2982. }
  2983. static const struct of_device_id wcd937x_dt_match[] = {
  2984. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2985. {}
  2986. };
  2987. static const struct component_master_ops wcd937x_comp_ops = {
  2988. .bind = wcd937x_bind,
  2989. .unbind = wcd937x_unbind,
  2990. };
  2991. static int wcd937x_compare_of(struct device *dev, void *data)
  2992. {
  2993. return dev->of_node == data;
  2994. }
  2995. static void wcd937x_release_of(struct device *dev, void *data)
  2996. {
  2997. of_node_put(data);
  2998. }
  2999. static int wcd937x_add_slave_components(struct device *dev,
  3000. struct component_match **matchptr)
  3001. {
  3002. struct device_node *np, *rx_node, *tx_node;
  3003. np = dev->of_node;
  3004. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3005. if (!rx_node) {
  3006. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3007. return -ENODEV;
  3008. }
  3009. of_node_get(rx_node);
  3010. component_match_add_release(dev, matchptr,
  3011. wcd937x_release_of,
  3012. wcd937x_compare_of,
  3013. rx_node);
  3014. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3015. if (!tx_node) {
  3016. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3017. return -ENODEV;
  3018. }
  3019. of_node_get(tx_node);
  3020. component_match_add_release(dev, matchptr,
  3021. wcd937x_release_of,
  3022. wcd937x_compare_of,
  3023. tx_node);
  3024. return 0;
  3025. }
  3026. static int wcd937x_probe(struct platform_device *pdev)
  3027. {
  3028. struct component_match *match = NULL;
  3029. int ret;
  3030. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3031. if (ret)
  3032. return ret;
  3033. return component_master_add_with_match(&pdev->dev,
  3034. &wcd937x_comp_ops, match);
  3035. }
  3036. static int wcd937x_remove(struct platform_device *pdev)
  3037. {
  3038. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3039. dev_set_drvdata(&pdev->dev, NULL);
  3040. return 0;
  3041. }
  3042. #ifdef CONFIG_PM_SLEEP
  3043. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3044. SET_SYSTEM_SLEEP_PM_OPS(
  3045. wcd937x_suspend,
  3046. wcd937x_resume
  3047. )
  3048. };
  3049. #endif
  3050. static struct platform_driver wcd937x_codec_driver = {
  3051. .probe = wcd937x_probe,
  3052. .remove = wcd937x_remove,
  3053. .driver = {
  3054. .name = "wcd937x_codec",
  3055. .owner = THIS_MODULE,
  3056. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3057. #ifdef CONFIG_PM_SLEEP
  3058. .pm = &wcd937x_dev_pm_ops,
  3059. #endif
  3060. .suppress_bind_attrs = true,
  3061. },
  3062. };
  3063. module_platform_driver(wcd937x_codec_driver);
  3064. MODULE_DESCRIPTION("WCD937X Codec driver");
  3065. MODULE_LICENSE("GPL v2");