sde_kms.c 117 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705
  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  171. {
  172. int ret;
  173. if (!kms || !crtc)
  174. return -EINVAL;
  175. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  176. ret = sde_crtc_vblank(crtc, true);
  177. SDE_ATRACE_END("sde_kms_enable_vblank");
  178. return ret;
  179. }
  180. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  181. {
  182. if (!kms || !crtc)
  183. return;
  184. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  185. sde_crtc_vblank(crtc, false);
  186. SDE_ATRACE_END("sde_kms_disable_vblank");
  187. }
  188. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  189. struct drm_crtc *crtc)
  190. {
  191. struct drm_encoder *encoder;
  192. struct drm_device *dev;
  193. int ret;
  194. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  195. SDE_ERROR("invalid params\n");
  196. return;
  197. }
  198. if (!crtc->state->enable) {
  199. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  200. return;
  201. }
  202. if (!crtc->state->active) {
  203. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  204. return;
  205. }
  206. dev = crtc->dev;
  207. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  208. if (encoder->crtc != crtc)
  209. continue;
  210. /*
  211. * Video Mode - Wait for VSYNC
  212. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  213. * complete
  214. */
  215. SDE_EVT32_VERBOSE(DRMID(crtc));
  216. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  217. if (ret && ret != -EWOULDBLOCK) {
  218. SDE_ERROR(
  219. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  220. crtc->base.id, encoder->base.id, ret);
  221. break;
  222. }
  223. }
  224. }
  225. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  226. struct drm_crtc *crtc, bool enable)
  227. {
  228. struct drm_device *dev;
  229. struct msm_drm_private *priv;
  230. struct sde_mdss_cfg *sde_cfg;
  231. struct drm_plane *plane;
  232. int i, ret;
  233. dev = sde_kms->dev;
  234. priv = dev->dev_private;
  235. sde_cfg = sde_kms->catalog;
  236. ret = sde_vbif_halt_xin_mask(sde_kms,
  237. sde_cfg->sui_block_xin_mask, enable);
  238. if (ret) {
  239. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  240. return ret;
  241. }
  242. if (enable) {
  243. for (i = 0; i < priv->num_planes; i++) {
  244. plane = priv->planes[i];
  245. sde_plane_secure_ctrl_xin_client(plane, crtc);
  246. }
  247. }
  248. return 0;
  249. }
  250. /**
  251. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  252. * @sde_kms: Pointer to sde_kms struct
  253. * @vimd: switch the stage 2 translation to this VMID
  254. */
  255. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  256. {
  257. struct device dummy = {};
  258. dma_addr_t dma_handle;
  259. uint32_t num_sids;
  260. uint32_t *sec_sid;
  261. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  262. int ret = 0, i;
  263. struct qtee_shm shm;
  264. bool qtee_en = qtee_shmbridge_is_enabled();
  265. phys_addr_t mem_addr;
  266. u64 mem_size;
  267. num_sids = sde_cfg->sec_sid_mask_count;
  268. if (!num_sids) {
  269. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  270. return -EINVAL;
  271. }
  272. if (qtee_en) {
  273. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  274. &shm);
  275. if (ret)
  276. return -ENOMEM;
  277. sec_sid = (uint32_t *) shm.vaddr;
  278. mem_addr = shm.paddr;
  279. /**
  280. * SMMUSecureModeSwitch requires the size to be number of SID's
  281. * but shm allocates size in pages. Modify the args as per
  282. * client requirement.
  283. */
  284. mem_size = sizeof(uint32_t) * num_sids;
  285. } else {
  286. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  287. if (!sec_sid)
  288. return -ENOMEM;
  289. mem_addr = virt_to_phys(sec_sid);
  290. mem_size = sizeof(uint32_t) * num_sids;
  291. }
  292. for (i = 0; i < num_sids; i++) {
  293. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  294. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  295. }
  296. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  297. if (ret) {
  298. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  299. goto map_error;
  300. }
  301. set_dma_ops(&dummy, NULL);
  302. dma_handle = dma_map_single(&dummy, sec_sid,
  303. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  304. if (dma_mapping_error(&dummy, dma_handle)) {
  305. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  306. vmid);
  307. goto map_error;
  308. }
  309. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  310. vmid, num_sids, qtee_en);
  311. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  312. mem_size, vmid);
  313. if (ret)
  314. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  315. vmid, ret);
  316. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  317. vmid, qtee_en, num_sids, ret);
  318. dma_unmap_single(&dummy, dma_handle,
  319. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  320. map_error:
  321. if (qtee_en)
  322. qtee_shmbridge_free_shm(&shm);
  323. else
  324. kfree(sec_sid);
  325. return ret;
  326. }
  327. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  328. {
  329. u32 ret;
  330. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  331. return 0;
  332. /* detach_all_contexts */
  333. ret = sde_kms_mmu_detach(sde_kms, false);
  334. if (ret) {
  335. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  336. goto mmu_error;
  337. }
  338. ret = _sde_kms_scm_call(sde_kms, vmid);
  339. if (ret) {
  340. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  341. goto scm_error;
  342. }
  343. return 0;
  344. scm_error:
  345. sde_kms_mmu_attach(sde_kms, false);
  346. mmu_error:
  347. atomic_dec(&sde_kms->detach_all_cb);
  348. return ret;
  349. }
  350. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  351. u32 old_vmid)
  352. {
  353. u32 ret;
  354. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  355. return 0;
  356. ret = _sde_kms_scm_call(sde_kms, vmid);
  357. if (ret) {
  358. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  359. goto scm_error;
  360. }
  361. /* attach_all_contexts */
  362. ret = sde_kms_mmu_attach(sde_kms, false);
  363. if (ret) {
  364. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  365. goto mmu_error;
  366. }
  367. return 0;
  368. mmu_error:
  369. _sde_kms_scm_call(sde_kms, old_vmid);
  370. scm_error:
  371. atomic_inc(&sde_kms->detach_all_cb);
  372. return ret;
  373. }
  374. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  375. {
  376. u32 ret;
  377. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  378. return 0;
  379. /* detach secure_context */
  380. ret = sde_kms_mmu_detach(sde_kms, true);
  381. if (ret) {
  382. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  383. goto mmu_error;
  384. }
  385. ret = _sde_kms_scm_call(sde_kms, vmid);
  386. if (ret) {
  387. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  388. goto scm_error;
  389. }
  390. return 0;
  391. scm_error:
  392. sde_kms_mmu_attach(sde_kms, true);
  393. mmu_error:
  394. atomic_dec(&sde_kms->detach_sec_cb);
  395. return ret;
  396. }
  397. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  398. u32 old_vmid)
  399. {
  400. u32 ret;
  401. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  402. return 0;
  403. ret = _sde_kms_scm_call(sde_kms, vmid);
  404. if (ret) {
  405. goto scm_error;
  406. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  407. }
  408. ret = sde_kms_mmu_attach(sde_kms, true);
  409. if (ret) {
  410. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  411. goto mmu_error;
  412. }
  413. return 0;
  414. mmu_error:
  415. _sde_kms_scm_call(sde_kms, old_vmid);
  416. scm_error:
  417. atomic_inc(&sde_kms->detach_sec_cb);
  418. return ret;
  419. }
  420. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  421. struct drm_crtc *crtc, bool enable)
  422. {
  423. int ret;
  424. if (enable) {
  425. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  426. if (ret < 0) {
  427. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  428. return ret;
  429. }
  430. sde_crtc_misr_setup(crtc, true, 1);
  431. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  432. if (ret) {
  433. sde_crtc_misr_setup(crtc, false, 0);
  434. pm_runtime_put_sync(sde_kms->dev->dev);
  435. return ret;
  436. }
  437. } else {
  438. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  439. sde_crtc_misr_setup(crtc, false, 0);
  440. pm_runtime_put_sync(sde_kms->dev->dev);
  441. }
  442. return 0;
  443. }
  444. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  445. bool post_commit)
  446. {
  447. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  448. int old_smmu_state = smmu_state->state;
  449. int ret = 0;
  450. u32 vmid;
  451. if (!sde_kms || !crtc) {
  452. SDE_ERROR("invalid argument(s)\n");
  453. return -EINVAL;
  454. }
  455. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  456. post_commit, smmu_state->sui_misr_state,
  457. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  458. if ((!smmu_state->transition_type) ||
  459. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  460. /* Bail out */
  461. return 0;
  462. /* enable sui misr if requested, before the transition */
  463. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  464. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  465. if (ret) {
  466. smmu_state->sui_misr_state = NONE;
  467. goto end;
  468. }
  469. }
  470. mutex_lock(&sde_kms->secure_transition_lock);
  471. switch (smmu_state->state) {
  472. case DETACH_ALL_REQ:
  473. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  474. if (!ret)
  475. smmu_state->state = DETACHED;
  476. break;
  477. case ATTACH_ALL_REQ:
  478. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  479. VMID_CP_SEC_DISPLAY);
  480. if (!ret) {
  481. smmu_state->state = ATTACHED;
  482. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  483. }
  484. break;
  485. case DETACH_SEC_REQ:
  486. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  487. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  488. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  489. if (!ret)
  490. smmu_state->state = DETACHED_SEC;
  491. break;
  492. case ATTACH_SEC_REQ:
  493. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  494. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  495. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  496. if (!ret) {
  497. smmu_state->state = ATTACHED;
  498. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  499. }
  500. break;
  501. default:
  502. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  503. DRMID(crtc), smmu_state->state,
  504. smmu_state->transition_type);
  505. ret = -EINVAL;
  506. break;
  507. }
  508. mutex_unlock(&sde_kms->secure_transition_lock);
  509. /* disable sui misr if requested, after the transition */
  510. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  511. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  512. if (ret)
  513. goto end;
  514. }
  515. end:
  516. smmu_state->transition_error = false;
  517. if (ret) {
  518. smmu_state->transition_error = true;
  519. SDE_ERROR(
  520. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  521. DRMID(crtc), old_smmu_state, smmu_state->state,
  522. smmu_state->secure_level, ret);
  523. smmu_state->state = smmu_state->prev_state;
  524. smmu_state->secure_level = smmu_state->prev_secure_level;
  525. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  526. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  527. }
  528. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  529. DRMID(crtc), old_smmu_state, smmu_state->state,
  530. smmu_state->secure_level, ret);
  531. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  532. smmu_state->transition_type,
  533. smmu_state->transition_error,
  534. smmu_state->secure_level, smmu_state->prev_secure_level,
  535. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  536. smmu_state->sui_misr_state = NONE;
  537. smmu_state->transition_type = NONE;
  538. return ret;
  539. }
  540. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  541. struct drm_atomic_state *state)
  542. {
  543. struct drm_crtc *crtc;
  544. struct drm_crtc_state *old_crtc_state;
  545. struct drm_plane_state *old_plane_state, *new_plane_state;
  546. struct drm_plane *plane;
  547. struct drm_plane_state *plane_state;
  548. struct sde_kms *sde_kms = to_sde_kms(kms);
  549. struct drm_device *dev = sde_kms->dev;
  550. int i, ops = 0, ret = 0;
  551. bool old_valid_fb = false;
  552. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  553. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  554. if (!crtc->state || !crtc->state->active)
  555. continue;
  556. /*
  557. * It is safe to assume only one active crtc,
  558. * and compatible translation modes on the
  559. * planes staged on this crtc.
  560. * otherwise validation would have failed.
  561. * For this CRTC,
  562. */
  563. /*
  564. * 1. Check if old state on the CRTC has planes
  565. * staged with valid fbs
  566. */
  567. for_each_old_plane_in_state(state, plane, plane_state, i) {
  568. if (!plane_state->crtc)
  569. continue;
  570. if (plane_state->fb) {
  571. old_valid_fb = true;
  572. break;
  573. }
  574. }
  575. /*
  576. * 2.Get the operations needed to be performed before
  577. * secure transition can be initiated.
  578. */
  579. ops = sde_crtc_get_secure_transition_ops(crtc,
  580. old_crtc_state, old_valid_fb);
  581. if (ops < 0) {
  582. SDE_ERROR("invalid secure operations %x\n", ops);
  583. return ops;
  584. }
  585. if (!ops) {
  586. smmu_state->transition_error = false;
  587. goto no_ops;
  588. }
  589. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  590. crtc->base.id, ops, crtc->state);
  591. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  592. /* 3. Perform operations needed for secure transition */
  593. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  594. SDE_DEBUG("wait_for_transfer_done\n");
  595. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  596. }
  597. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  598. SDE_DEBUG("cleanup planes\n");
  599. drm_atomic_helper_cleanup_planes(dev, state);
  600. for_each_oldnew_plane_in_state(state, plane,
  601. old_plane_state, new_plane_state, i)
  602. sde_plane_destroy_fb(old_plane_state);
  603. }
  604. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  605. SDE_DEBUG("secure ctrl\n");
  606. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  607. }
  608. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  609. SDE_DEBUG("prepare planes %d",
  610. crtc->state->plane_mask);
  611. drm_atomic_crtc_for_each_plane(plane,
  612. crtc) {
  613. const struct drm_plane_helper_funcs *funcs;
  614. plane_state = plane->state;
  615. funcs = plane->helper_private;
  616. SDE_DEBUG("psde:%d FB[%u]\n",
  617. plane->base.id,
  618. plane->fb->base.id);
  619. if (!funcs)
  620. continue;
  621. if (funcs->prepare_fb(plane, plane_state)) {
  622. ret = funcs->prepare_fb(plane,
  623. plane_state);
  624. if (ret)
  625. return ret;
  626. }
  627. }
  628. }
  629. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  630. SDE_DEBUG("secure operations completed\n");
  631. }
  632. no_ops:
  633. return 0;
  634. }
  635. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  636. unsigned int splash_buffer_size,
  637. unsigned int ramdump_base,
  638. unsigned int ramdump_buffer_size)
  639. {
  640. unsigned long pfn_start, pfn_end, pfn_idx;
  641. int ret = 0;
  642. if (!mem_addr || !splash_buffer_size) {
  643. SDE_ERROR("invalid params\n");
  644. return -EINVAL;
  645. }
  646. /* leave ramdump memory only if base address matches */
  647. if (ramdump_base == mem_addr &&
  648. ramdump_buffer_size <= splash_buffer_size) {
  649. mem_addr += ramdump_buffer_size;
  650. splash_buffer_size -= ramdump_buffer_size;
  651. }
  652. pfn_start = mem_addr >> PAGE_SHIFT;
  653. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  654. ret = memblock_free(mem_addr, splash_buffer_size);
  655. if (ret) {
  656. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  657. return ret;
  658. }
  659. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  660. free_reserved_page(pfn_to_page(pfn_idx));
  661. return ret;
  662. }
  663. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  664. struct sde_splash_mem *splash)
  665. {
  666. struct msm_mmu *mmu = NULL;
  667. int ret = 0;
  668. if (!sde_kms->aspace[0]) {
  669. SDE_ERROR("aspace not found for sde kms node\n");
  670. return -EINVAL;
  671. }
  672. mmu = sde_kms->aspace[0]->mmu;
  673. if (!mmu) {
  674. SDE_ERROR("mmu not found for aspace\n");
  675. return -EINVAL;
  676. }
  677. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  678. SDE_ERROR("invalid input params for map\n");
  679. return -EINVAL;
  680. }
  681. if (!splash->ref_cnt) {
  682. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  683. splash->splash_buf_base,
  684. splash->splash_buf_size,
  685. IOMMU_READ | IOMMU_NOEXEC);
  686. if (ret)
  687. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  688. }
  689. splash->ref_cnt++;
  690. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  691. splash->splash_buf_base,
  692. splash->splash_buf_size,
  693. splash->ref_cnt);
  694. return ret;
  695. }
  696. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  697. {
  698. int i = 0;
  699. int ret = 0;
  700. if (!sde_kms)
  701. return -EINVAL;
  702. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  703. ret = _sde_kms_splash_mem_get(sde_kms,
  704. sde_kms->splash_data.splash_display[i].splash);
  705. if (ret)
  706. return ret;
  707. }
  708. return ret;
  709. }
  710. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  711. struct sde_splash_mem *splash)
  712. {
  713. struct msm_mmu *mmu = NULL;
  714. int rc = 0;
  715. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  716. SDE_ERROR("invalid params\n");
  717. return -EINVAL;
  718. }
  719. mmu = sde_kms->aspace[0]->mmu;
  720. if (!splash || !splash->ref_cnt ||
  721. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  722. return -EINVAL;
  723. splash->ref_cnt--;
  724. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  725. splash->splash_buf_base, splash->ref_cnt);
  726. if (!splash->ref_cnt) {
  727. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  728. splash->splash_buf_size);
  729. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  730. splash->splash_buf_size, splash->ramdump_base,
  731. splash->ramdump_size);
  732. splash->splash_buf_base = 0;
  733. splash->splash_buf_size = 0;
  734. }
  735. return rc;
  736. }
  737. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  738. {
  739. int i = 0;
  740. int ret = 0;
  741. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  742. return -EINVAL;
  743. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  744. ret = _sde_kms_splash_mem_put(sde_kms,
  745. sde_kms->splash_data.splash_display[i].splash);
  746. if (ret)
  747. return ret;
  748. }
  749. return ret;
  750. }
  751. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  752. struct drm_connector_state *conn_state)
  753. {
  754. int lp_mode, blank;
  755. if (crtc_state->active)
  756. lp_mode = sde_connector_get_property(conn_state,
  757. CONNECTOR_PROP_LP);
  758. else
  759. lp_mode = SDE_MODE_DPMS_OFF;
  760. switch (lp_mode) {
  761. case SDE_MODE_DPMS_ON:
  762. blank = DRM_PANEL_BLANK_UNBLANK;
  763. break;
  764. case SDE_MODE_DPMS_LP1:
  765. case SDE_MODE_DPMS_LP2:
  766. blank = DRM_PANEL_BLANK_LP;
  767. break;
  768. case SDE_MODE_DPMS_OFF:
  769. default:
  770. blank = DRM_PANEL_BLANK_POWERDOWN;
  771. break;
  772. }
  773. return blank;
  774. }
  775. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  776. unsigned long event)
  777. {
  778. struct drm_connector *connector;
  779. struct drm_connector_state *old_conn_state;
  780. struct drm_crtc_state *old_crtc_state;
  781. struct drm_crtc *crtc;
  782. int i, old_mode, new_mode, old_fps, new_fps;
  783. for_each_old_connector_in_state(old_state, connector,
  784. old_conn_state, i) {
  785. crtc = connector->state->crtc ? connector->state->crtc :
  786. old_conn_state->crtc;
  787. if (!crtc)
  788. continue;
  789. new_fps = crtc->state->mode.vrefresh;
  790. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  791. if (old_conn_state->crtc) {
  792. old_crtc_state = drm_atomic_get_existing_crtc_state(
  793. old_state, old_conn_state->crtc);
  794. old_fps = old_crtc_state->mode.vrefresh;
  795. old_mode = _sde_kms_get_blank(old_crtc_state,
  796. old_conn_state);
  797. } else {
  798. old_fps = 0;
  799. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  800. }
  801. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  802. struct drm_panel_notifier notifier_data;
  803. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  804. connector->panel, crtc->state->active,
  805. old_conn_state->crtc, event);
  806. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  807. old_mode, new_mode, old_fps, new_fps);
  808. /* If suspend resume and fps change are happening
  809. * at the same time, give preference to power mode
  810. * changes rather than fps change.
  811. */
  812. if ((old_mode == new_mode) && (old_fps != new_fps))
  813. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  814. notifier_data.data = &new_mode;
  815. notifier_data.refresh_rate = new_fps;
  816. notifier_data.id = connector->base.id;
  817. if (connector->panel)
  818. drm_panel_notifier_call_chain(connector->panel,
  819. event, &notifier_data);
  820. }
  821. }
  822. }
  823. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  824. struct drm_atomic_state *state)
  825. {
  826. int i;
  827. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  828. struct drm_crtc *crtc, *vm_crtc = NULL;
  829. struct drm_crtc_state *new_cstate, *old_cstate;
  830. struct sde_crtc_state *vm_cstate;
  831. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  832. if (!new_cstate->active && !old_cstate->active)
  833. continue;
  834. vm_cstate = to_sde_crtc_state(new_cstate);
  835. vm_req = sde_crtc_get_property(vm_cstate,
  836. CRTC_PROP_VM_REQ_STATE);
  837. if (vm_req != VM_REQ_NONE) {
  838. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  839. vm_req, crtc->base.id);
  840. vm_crtc = crtc;
  841. break;
  842. }
  843. }
  844. return vm_crtc;
  845. }
  846. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  847. struct drm_atomic_state *state)
  848. {
  849. struct drm_device *ddev;
  850. struct drm_crtc *crtc;
  851. struct drm_crtc_state *new_cstate;
  852. struct drm_encoder *encoder;
  853. struct drm_connector *connector;
  854. struct sde_vm_ops *vm_ops;
  855. struct sde_crtc_state *cstate;
  856. enum sde_crtc_vm_req vm_req;
  857. int rc = 0;
  858. ddev = sde_kms->dev;
  859. vm_ops = sde_vm_get_ops(sde_kms);
  860. if (!vm_ops)
  861. return -EINVAL;
  862. crtc = sde_kms_vm_get_vm_crtc(state);
  863. if (!crtc)
  864. return 0;
  865. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  866. cstate = to_sde_crtc_state(new_cstate);
  867. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  868. if (vm_req != VM_REQ_ACQUIRE)
  869. return 0;
  870. /* enable MDSS irq line */
  871. sde_irq_update(&sde_kms->base, true);
  872. /* clear the stale IRQ status bits */
  873. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  874. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  875. /* enable the display path IRQ's */
  876. drm_for_each_encoder_mask(encoder, crtc->dev,
  877. crtc->state->encoder_mask) {
  878. if (sde_encoder_in_clone_mode(encoder))
  879. continue;
  880. sde_encoder_irq_control(encoder, true);
  881. }
  882. /* Schedule ESD work */
  883. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  884. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  885. sde_connector_schedule_status_work(connector, true);
  886. /* enable vblank events */
  887. drm_crtc_vblank_on(crtc);
  888. /* handle non-SDE pre_acquire */
  889. if (vm_ops->vm_client_post_acquire)
  890. rc = vm_ops->vm_client_post_acquire(sde_kms);
  891. return rc;
  892. }
  893. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  894. struct drm_atomic_state *state)
  895. {
  896. struct drm_device *ddev;
  897. struct drm_plane *plane;
  898. struct drm_crtc *crtc;
  899. struct drm_crtc_state *new_cstate;
  900. struct sde_crtc_state *cstate;
  901. enum sde_crtc_vm_req vm_req;
  902. ddev = sde_kms->dev;
  903. crtc = sde_kms_vm_get_vm_crtc(state);
  904. if (!crtc)
  905. return 0;
  906. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  907. cstate = to_sde_crtc_state(new_cstate);
  908. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  909. if (vm_req != VM_REQ_ACQUIRE)
  910. return 0;
  911. /* Clear the stale IRQ status bits */
  912. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  913. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  914. /* Program the SID's for the trusted VM */
  915. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  916. sde_plane_set_sid(plane, 1);
  917. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  918. return 0;
  919. }
  920. static void sde_kms_prepare_commit(struct msm_kms *kms,
  921. struct drm_atomic_state *state)
  922. {
  923. struct sde_kms *sde_kms;
  924. struct msm_drm_private *priv;
  925. struct drm_device *dev;
  926. struct drm_encoder *encoder;
  927. struct drm_crtc *crtc;
  928. struct drm_crtc_state *crtc_state;
  929. struct sde_vm_ops *vm_ops;
  930. int i, rc;
  931. if (!kms)
  932. return;
  933. sde_kms = to_sde_kms(kms);
  934. dev = sde_kms->dev;
  935. if (!dev || !dev->dev_private)
  936. return;
  937. priv = dev->dev_private;
  938. SDE_ATRACE_BEGIN("prepare_commit");
  939. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  940. if (rc < 0) {
  941. SDE_ERROR("failed to enable power resources %d\n", rc);
  942. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  943. goto end;
  944. }
  945. if (sde_kms->first_kickoff) {
  946. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  947. sde_kms->first_kickoff = false;
  948. }
  949. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  950. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  951. head) {
  952. if (encoder->crtc != crtc)
  953. continue;
  954. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  955. SDE_ERROR("crtc:%d, initiating hw reset\n",
  956. DRMID(crtc));
  957. sde_encoder_needs_hw_reset(encoder);
  958. sde_crtc_set_needs_hw_reset(crtc);
  959. }
  960. }
  961. }
  962. /*
  963. * NOTE: for secure use cases we want to apply the new HW
  964. * configuration only after completing preparation for secure
  965. * transitions prepare below if any transtions is required.
  966. */
  967. sde_kms_prepare_secure_transition(kms, state);
  968. vm_ops = sde_vm_get_ops(sde_kms);
  969. if (!vm_ops)
  970. goto end_vm;
  971. if (vm_ops->vm_prepare_commit)
  972. vm_ops->vm_prepare_commit(sde_kms, state);
  973. end_vm:
  974. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  975. end:
  976. SDE_ATRACE_END("prepare_commit");
  977. }
  978. static void sde_kms_commit(struct msm_kms *kms,
  979. struct drm_atomic_state *old_state)
  980. {
  981. struct sde_kms *sde_kms;
  982. struct drm_crtc *crtc;
  983. struct drm_crtc_state *old_crtc_state;
  984. int i;
  985. if (!kms || !old_state)
  986. return;
  987. sde_kms = to_sde_kms(kms);
  988. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  989. SDE_ERROR("power resource is not enabled\n");
  990. return;
  991. }
  992. SDE_ATRACE_BEGIN("sde_kms_commit");
  993. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  994. if (crtc->state->active) {
  995. SDE_EVT32(DRMID(crtc), old_state);
  996. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  997. }
  998. }
  999. SDE_ATRACE_END("sde_kms_commit");
  1000. }
  1001. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  1002. struct sde_splash_display *splash_display)
  1003. {
  1004. if (!sde_kms || !splash_display ||
  1005. !sde_kms->splash_data.num_splash_displays)
  1006. return;
  1007. if (sde_kms->splash_data.num_splash_regions)
  1008. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  1009. sde_kms->splash_data.num_splash_displays--;
  1010. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  1011. sde_kms->splash_data.num_splash_displays);
  1012. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1013. }
  1014. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1015. struct drm_crtc *crtc)
  1016. {
  1017. struct msm_drm_private *priv;
  1018. struct sde_splash_display *splash_display;
  1019. int i;
  1020. if (!sde_kms || !crtc)
  1021. return;
  1022. priv = sde_kms->dev->dev_private;
  1023. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1024. return;
  1025. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1026. sde_kms->splash_data.num_splash_displays);
  1027. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1028. splash_display = &sde_kms->splash_data.splash_display[i];
  1029. if (splash_display->encoder &&
  1030. crtc == splash_display->encoder->crtc)
  1031. break;
  1032. }
  1033. if (i >= MAX_DSI_DISPLAYS)
  1034. return;
  1035. if (splash_display->cont_splash_enabled) {
  1036. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1037. splash_display, false);
  1038. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1039. }
  1040. /* remove the votes if all displays are done with splash */
  1041. if (!sde_kms->splash_data.num_splash_displays) {
  1042. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1043. sde_power_data_bus_set_quota(&priv->phandle, i,
  1044. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1045. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1046. pm_runtime_put_sync(sde_kms->dev->dev);
  1047. }
  1048. }
  1049. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1050. struct drm_atomic_state *state)
  1051. {
  1052. struct sde_vm_ops *vm_ops;
  1053. struct drm_device *ddev;
  1054. struct drm_crtc *crtc;
  1055. struct drm_plane *plane;
  1056. struct drm_encoder *encoder;
  1057. struct sde_crtc_state *cstate;
  1058. struct drm_crtc_state *new_cstate;
  1059. enum sde_crtc_vm_req vm_req;
  1060. int rc = 0;
  1061. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1062. return -EINVAL;
  1063. vm_ops = sde_vm_get_ops(sde_kms);
  1064. ddev = sde_kms->dev;
  1065. crtc = sde_kms_vm_get_vm_crtc(state);
  1066. if (!crtc)
  1067. return 0;
  1068. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1069. cstate = to_sde_crtc_state(new_cstate);
  1070. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1071. if (vm_req != VM_REQ_RELEASE)
  1072. return 0;
  1073. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1074. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1075. drm_for_each_encoder_mask(encoder, crtc->dev,
  1076. crtc->state->encoder_mask) {
  1077. if (sde_encoder_in_clone_mode(encoder))
  1078. continue;
  1079. sde_encoder_irq_control(encoder, false);
  1080. }
  1081. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1082. sde_plane_set_sid(plane, 0);
  1083. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1084. sde_vm_lock(sde_kms);
  1085. if (vm_ops->vm_release)
  1086. rc = vm_ops->vm_release(sde_kms);
  1087. sde_vm_unlock(sde_kms);
  1088. return rc;
  1089. }
  1090. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1091. struct drm_atomic_state *state)
  1092. {
  1093. struct drm_device *ddev;
  1094. struct drm_crtc *crtc;
  1095. struct drm_encoder *encoder;
  1096. struct drm_connector *connector;
  1097. int rc = 0;
  1098. ddev = sde_kms->dev;
  1099. crtc = sde_kms_vm_get_vm_crtc(state);
  1100. if (!crtc)
  1101. return 0;
  1102. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1103. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1104. /* disable ESD work */
  1105. list_for_each_entry(connector,
  1106. &ddev->mode_config.connector_list, head) {
  1107. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1108. sde_connector_schedule_status_work(connector, false);
  1109. }
  1110. /* disable SDE irq's */
  1111. drm_for_each_encoder_mask(encoder, crtc->dev,
  1112. crtc->state->encoder_mask) {
  1113. if (sde_encoder_in_clone_mode(encoder))
  1114. continue;
  1115. sde_encoder_irq_control(encoder, false);
  1116. }
  1117. /* disable IRQ line */
  1118. sde_irq_update(&sde_kms->base, false);
  1119. /* disable vblank events */
  1120. drm_crtc_vblank_off(crtc);
  1121. /* reset sw state */
  1122. sde_crtc_reset_sw_state(crtc);
  1123. return rc;
  1124. }
  1125. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1126. struct drm_atomic_state *state)
  1127. {
  1128. struct sde_vm_ops *vm_ops;
  1129. struct sde_crtc_state *cstate;
  1130. struct drm_crtc *crtc;
  1131. struct drm_crtc_state *new_cstate;
  1132. enum sde_crtc_vm_req vm_req;
  1133. int rc = 0;
  1134. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1135. return -EINVAL;
  1136. vm_ops = sde_vm_get_ops(sde_kms);
  1137. crtc = sde_kms_vm_get_vm_crtc(state);
  1138. if (!crtc)
  1139. return 0;
  1140. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1141. cstate = to_sde_crtc_state(new_cstate);
  1142. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1143. if (vm_req != VM_REQ_RELEASE)
  1144. return 0;
  1145. /* handle SDE pre-release */
  1146. rc = sde_kms_vm_pre_release(sde_kms, state);
  1147. if (rc) {
  1148. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1149. goto exit;
  1150. }
  1151. /* properly handoff color processing features */
  1152. sde_cp_crtc_vm_primary_handoff(crtc);
  1153. /* handle non-SDE clients pre-release */
  1154. if (vm_ops->vm_client_pre_release) {
  1155. rc = vm_ops->vm_client_pre_release(sde_kms);
  1156. if (rc) {
  1157. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1158. rc);
  1159. goto exit;
  1160. }
  1161. }
  1162. sde_vm_lock(sde_kms);
  1163. /* release HW */
  1164. if (vm_ops->vm_release) {
  1165. rc = vm_ops->vm_release(sde_kms);
  1166. if (rc)
  1167. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1168. }
  1169. sde_vm_unlock(sde_kms);
  1170. exit:
  1171. return rc;
  1172. }
  1173. static void sde_kms_complete_commit(struct msm_kms *kms,
  1174. struct drm_atomic_state *old_state)
  1175. {
  1176. struct sde_kms *sde_kms;
  1177. struct msm_drm_private *priv;
  1178. struct drm_crtc *crtc;
  1179. struct drm_crtc_state *old_crtc_state;
  1180. struct drm_connector *connector;
  1181. struct drm_connector_state *old_conn_state;
  1182. struct msm_display_conn_params params;
  1183. struct sde_vm_ops *vm_ops;
  1184. int i, rc = 0;
  1185. if (!kms || !old_state)
  1186. return;
  1187. sde_kms = to_sde_kms(kms);
  1188. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1189. return;
  1190. priv = sde_kms->dev->dev_private;
  1191. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1192. SDE_ERROR("power resource is not enabled\n");
  1193. return;
  1194. }
  1195. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1196. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1197. sde_crtc_complete_commit(crtc, old_crtc_state);
  1198. /* complete secure transitions if any */
  1199. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1200. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1201. }
  1202. for_each_old_connector_in_state(old_state, connector,
  1203. old_conn_state, i) {
  1204. struct sde_connector *c_conn;
  1205. c_conn = to_sde_connector(connector);
  1206. if (!c_conn->ops.post_kickoff)
  1207. continue;
  1208. memset(&params, 0, sizeof(params));
  1209. sde_connector_complete_qsync_commit(connector, &params);
  1210. rc = c_conn->ops.post_kickoff(connector, &params);
  1211. if (rc) {
  1212. pr_err("Connector Post kickoff failed rc=%d\n",
  1213. rc);
  1214. }
  1215. }
  1216. vm_ops = sde_vm_get_ops(sde_kms);
  1217. if (vm_ops && vm_ops->vm_post_commit) {
  1218. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1219. if (rc)
  1220. SDE_ERROR("vm post commit failed, rc = %d\n",
  1221. rc);
  1222. }
  1223. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1224. pm_runtime_put_sync(sde_kms->dev->dev);
  1225. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1226. _sde_kms_release_splash_resource(sde_kms, crtc);
  1227. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1228. SDE_ATRACE_END("sde_kms_complete_commit");
  1229. }
  1230. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1231. struct drm_crtc *crtc)
  1232. {
  1233. struct drm_encoder *encoder;
  1234. struct drm_device *dev;
  1235. int ret;
  1236. bool cwb_disabling;
  1237. if (!kms || !crtc || !crtc->state) {
  1238. SDE_ERROR("invalid params\n");
  1239. return;
  1240. }
  1241. dev = crtc->dev;
  1242. if (!crtc->state->enable) {
  1243. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1244. return;
  1245. }
  1246. if (!crtc->state->active) {
  1247. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1248. return;
  1249. }
  1250. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1251. SDE_ERROR("power resource is not enabled\n");
  1252. return;
  1253. }
  1254. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1255. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1256. cwb_disabling = false;
  1257. if (encoder->crtc != crtc) {
  1258. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1259. crtc);
  1260. if (!cwb_disabling)
  1261. continue;
  1262. }
  1263. /*
  1264. * Wait for post-flush if necessary to delay before
  1265. * plane_cleanup. For example, wait for vsync in case of video
  1266. * mode panels. This may be a no-op for command mode panels.
  1267. */
  1268. SDE_EVT32_VERBOSE(DRMID(crtc));
  1269. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1270. if (ret && ret != -EWOULDBLOCK) {
  1271. SDE_ERROR("wait for commit done returned %d\n", ret);
  1272. sde_crtc_request_frame_reset(crtc);
  1273. break;
  1274. }
  1275. sde_crtc_complete_flip(crtc, NULL);
  1276. if (cwb_disabling)
  1277. sde_encoder_virt_reset(encoder);
  1278. }
  1279. sde_crtc_static_cache_read_kickoff(crtc);
  1280. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1281. }
  1282. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1283. struct drm_atomic_state *old_state)
  1284. {
  1285. struct drm_crtc *crtc;
  1286. struct drm_crtc_state *old_crtc_state;
  1287. int i, rc;
  1288. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1289. SDE_ERROR("invalid argument(s)\n");
  1290. return;
  1291. }
  1292. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1293. retry:
  1294. /* attempt to acquire ww mutex for connection */
  1295. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1296. old_state->acquire_ctx);
  1297. if (rc == -EDEADLK) {
  1298. drm_modeset_backoff(old_state->acquire_ctx);
  1299. goto retry;
  1300. }
  1301. /* old_state actually contains updated crtc pointers */
  1302. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1303. if (crtc->state->active || crtc->state->active_changed)
  1304. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1305. }
  1306. SDE_ATRACE_END("sde_kms_prepare_fence");
  1307. }
  1308. /**
  1309. * _sde_kms_get_displays - query for underlying display handles and cache them
  1310. * @sde_kms: Pointer to sde kms structure
  1311. * Returns: Zero on success
  1312. */
  1313. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1314. {
  1315. int rc = -ENOMEM;
  1316. if (!sde_kms) {
  1317. SDE_ERROR("invalid sde kms\n");
  1318. return -EINVAL;
  1319. }
  1320. /* dsi */
  1321. sde_kms->dsi_displays = NULL;
  1322. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1323. if (sde_kms->dsi_display_count) {
  1324. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1325. sizeof(void *),
  1326. GFP_KERNEL);
  1327. if (!sde_kms->dsi_displays) {
  1328. SDE_ERROR("failed to allocate dsi displays\n");
  1329. goto exit_deinit_dsi;
  1330. }
  1331. sde_kms->dsi_display_count =
  1332. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1333. sde_kms->dsi_display_count);
  1334. }
  1335. /* wb */
  1336. sde_kms->wb_displays = NULL;
  1337. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1338. if (sde_kms->wb_display_count) {
  1339. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1340. sizeof(void *),
  1341. GFP_KERNEL);
  1342. if (!sde_kms->wb_displays) {
  1343. SDE_ERROR("failed to allocate wb displays\n");
  1344. goto exit_deinit_wb;
  1345. }
  1346. sde_kms->wb_display_count =
  1347. wb_display_get_displays(sde_kms->wb_displays,
  1348. sde_kms->wb_display_count);
  1349. }
  1350. /* dp */
  1351. sde_kms->dp_displays = NULL;
  1352. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1353. if (sde_kms->dp_display_count) {
  1354. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1355. sizeof(void *), GFP_KERNEL);
  1356. if (!sde_kms->dp_displays) {
  1357. SDE_ERROR("failed to allocate dp displays\n");
  1358. goto exit_deinit_dp;
  1359. }
  1360. sde_kms->dp_display_count =
  1361. dp_display_get_displays(sde_kms->dp_displays,
  1362. sde_kms->dp_display_count);
  1363. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1364. }
  1365. return 0;
  1366. exit_deinit_dp:
  1367. kfree(sde_kms->dp_displays);
  1368. sde_kms->dp_stream_count = 0;
  1369. sde_kms->dp_display_count = 0;
  1370. sde_kms->dp_displays = NULL;
  1371. exit_deinit_wb:
  1372. kfree(sde_kms->wb_displays);
  1373. sde_kms->wb_display_count = 0;
  1374. sde_kms->wb_displays = NULL;
  1375. exit_deinit_dsi:
  1376. kfree(sde_kms->dsi_displays);
  1377. sde_kms->dsi_display_count = 0;
  1378. sde_kms->dsi_displays = NULL;
  1379. return rc;
  1380. }
  1381. /**
  1382. * _sde_kms_release_displays - release cache of underlying display handles
  1383. * @sde_kms: Pointer to sde kms structure
  1384. */
  1385. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1386. {
  1387. if (!sde_kms) {
  1388. SDE_ERROR("invalid sde kms\n");
  1389. return;
  1390. }
  1391. kfree(sde_kms->wb_displays);
  1392. sde_kms->wb_displays = NULL;
  1393. sde_kms->wb_display_count = 0;
  1394. kfree(sde_kms->dsi_displays);
  1395. sde_kms->dsi_displays = NULL;
  1396. sde_kms->dsi_display_count = 0;
  1397. }
  1398. /**
  1399. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1400. * for underlying displays
  1401. * @dev: Pointer to drm device structure
  1402. * @priv: Pointer to private drm device data
  1403. * @sde_kms: Pointer to sde kms structure
  1404. * Returns: Zero on success
  1405. */
  1406. static int _sde_kms_setup_displays(struct drm_device *dev,
  1407. struct msm_drm_private *priv,
  1408. struct sde_kms *sde_kms)
  1409. {
  1410. static const struct sde_connector_ops dsi_ops = {
  1411. .set_info_blob = dsi_conn_set_info_blob,
  1412. .detect = dsi_conn_detect,
  1413. .get_modes = dsi_connector_get_modes,
  1414. .pre_destroy = dsi_connector_put_modes,
  1415. .mode_valid = dsi_conn_mode_valid,
  1416. .get_info = dsi_display_get_info,
  1417. .set_backlight = dsi_display_set_backlight,
  1418. .soft_reset = dsi_display_soft_reset,
  1419. .pre_kickoff = dsi_conn_pre_kickoff,
  1420. .clk_ctrl = dsi_display_clk_ctrl,
  1421. .set_power = dsi_display_set_power,
  1422. .get_mode_info = dsi_conn_get_mode_info,
  1423. .get_dst_format = dsi_display_get_dst_format,
  1424. .post_kickoff = dsi_conn_post_kickoff,
  1425. .check_status = dsi_display_check_status,
  1426. .enable_event = dsi_conn_enable_event,
  1427. .cmd_transfer = dsi_display_cmd_transfer,
  1428. .cont_splash_config = dsi_display_cont_splash_config,
  1429. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1430. .get_panel_vfp = dsi_display_get_panel_vfp,
  1431. .get_default_lms = dsi_display_get_default_lms,
  1432. .cmd_receive = dsi_display_cmd_receive,
  1433. .install_properties = NULL,
  1434. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1435. .get_qsync_min_fps = dsi_display_get_qsync_min_fps,
  1436. };
  1437. static const struct sde_connector_ops wb_ops = {
  1438. .post_init = sde_wb_connector_post_init,
  1439. .set_info_blob = sde_wb_connector_set_info_blob,
  1440. .detect = sde_wb_connector_detect,
  1441. .get_modes = sde_wb_connector_get_modes,
  1442. .set_property = sde_wb_connector_set_property,
  1443. .get_info = sde_wb_get_info,
  1444. .soft_reset = NULL,
  1445. .get_mode_info = sde_wb_get_mode_info,
  1446. .get_dst_format = NULL,
  1447. .check_status = NULL,
  1448. .cmd_transfer = NULL,
  1449. .cont_splash_config = NULL,
  1450. .cont_splash_res_disable = NULL,
  1451. .get_panel_vfp = NULL,
  1452. .cmd_receive = NULL,
  1453. .install_properties = NULL,
  1454. .set_allowed_mode_switch = NULL,
  1455. };
  1456. static const struct sde_connector_ops dp_ops = {
  1457. .post_init = dp_connector_post_init,
  1458. .detect = dp_connector_detect,
  1459. .get_modes = dp_connector_get_modes,
  1460. .atomic_check = dp_connector_atomic_check,
  1461. .mode_valid = dp_connector_mode_valid,
  1462. .get_info = dp_connector_get_info,
  1463. .get_mode_info = dp_connector_get_mode_info,
  1464. .post_open = dp_connector_post_open,
  1465. .check_status = NULL,
  1466. .set_colorspace = dp_connector_set_colorspace,
  1467. .config_hdr = dp_connector_config_hdr,
  1468. .cmd_transfer = NULL,
  1469. .cont_splash_config = NULL,
  1470. .cont_splash_res_disable = NULL,
  1471. .get_panel_vfp = NULL,
  1472. .update_pps = dp_connector_update_pps,
  1473. .cmd_receive = NULL,
  1474. .install_properties = dp_connector_install_properties,
  1475. .set_allowed_mode_switch = NULL,
  1476. };
  1477. struct msm_display_info info;
  1478. struct drm_encoder *encoder;
  1479. void *display, *connector;
  1480. int i, max_encoders;
  1481. int rc = 0;
  1482. u32 dsc_count = 0, mixer_count = 0;
  1483. u32 max_dp_dsc_count, max_dp_mixer_count;
  1484. if (!dev || !priv || !sde_kms) {
  1485. SDE_ERROR("invalid argument(s)\n");
  1486. return -EINVAL;
  1487. }
  1488. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1489. sde_kms->dp_display_count +
  1490. sde_kms->dp_stream_count;
  1491. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1492. max_encoders = ARRAY_SIZE(priv->encoders);
  1493. SDE_ERROR("capping number of displays to %d", max_encoders);
  1494. }
  1495. /* wb */
  1496. for (i = 0; i < sde_kms->wb_display_count &&
  1497. priv->num_encoders < max_encoders; ++i) {
  1498. display = sde_kms->wb_displays[i];
  1499. encoder = NULL;
  1500. memset(&info, 0x0, sizeof(info));
  1501. rc = sde_wb_get_info(NULL, &info, display);
  1502. if (rc) {
  1503. SDE_ERROR("wb get_info %d failed\n", i);
  1504. continue;
  1505. }
  1506. encoder = sde_encoder_init(dev, &info);
  1507. if (IS_ERR_OR_NULL(encoder)) {
  1508. SDE_ERROR("encoder init failed for wb %d\n", i);
  1509. continue;
  1510. }
  1511. rc = sde_wb_drm_init(display, encoder);
  1512. if (rc) {
  1513. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1514. sde_encoder_destroy(encoder);
  1515. continue;
  1516. }
  1517. connector = sde_connector_init(dev,
  1518. encoder,
  1519. 0,
  1520. display,
  1521. &wb_ops,
  1522. DRM_CONNECTOR_POLL_HPD,
  1523. DRM_MODE_CONNECTOR_VIRTUAL);
  1524. if (connector) {
  1525. priv->encoders[priv->num_encoders++] = encoder;
  1526. priv->connectors[priv->num_connectors++] = connector;
  1527. } else {
  1528. SDE_ERROR("wb %d connector init failed\n", i);
  1529. sde_wb_drm_deinit(display);
  1530. sde_encoder_destroy(encoder);
  1531. }
  1532. }
  1533. /* dsi */
  1534. for (i = 0; i < sde_kms->dsi_display_count &&
  1535. priv->num_encoders < max_encoders; ++i) {
  1536. display = sde_kms->dsi_displays[i];
  1537. encoder = NULL;
  1538. memset(&info, 0x0, sizeof(info));
  1539. rc = dsi_display_get_info(NULL, &info, display);
  1540. if (rc) {
  1541. SDE_ERROR("dsi get_info %d failed\n", i);
  1542. continue;
  1543. }
  1544. encoder = sde_encoder_init(dev, &info);
  1545. if (IS_ERR_OR_NULL(encoder)) {
  1546. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1547. continue;
  1548. }
  1549. rc = dsi_display_drm_bridge_init(display, encoder);
  1550. if (rc) {
  1551. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1552. sde_encoder_destroy(encoder);
  1553. continue;
  1554. }
  1555. connector = sde_connector_init(dev,
  1556. encoder,
  1557. dsi_display_get_drm_panel(display),
  1558. display,
  1559. &dsi_ops,
  1560. DRM_CONNECTOR_POLL_HPD,
  1561. DRM_MODE_CONNECTOR_DSI);
  1562. if (connector) {
  1563. priv->encoders[priv->num_encoders++] = encoder;
  1564. priv->connectors[priv->num_connectors++] = connector;
  1565. } else {
  1566. SDE_ERROR("dsi %d connector init failed\n", i);
  1567. dsi_display_drm_bridge_deinit(display);
  1568. sde_encoder_destroy(encoder);
  1569. continue;
  1570. }
  1571. rc = dsi_display_drm_ext_bridge_init(display,
  1572. encoder, connector);
  1573. if (rc) {
  1574. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1575. dsi_display_drm_bridge_deinit(display);
  1576. sde_connector_destroy(connector);
  1577. sde_encoder_destroy(encoder);
  1578. }
  1579. dsc_count += info.dsc_count;
  1580. mixer_count += info.lm_count;
  1581. }
  1582. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1583. sde_kms->catalog->mixer_count - mixer_count : 0;
  1584. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1585. sde_kms->catalog->dsc_count - dsc_count : 0;
  1586. /* dp */
  1587. for (i = 0; i < sde_kms->dp_display_count &&
  1588. priv->num_encoders < max_encoders; ++i) {
  1589. int idx;
  1590. display = sde_kms->dp_displays[i];
  1591. encoder = NULL;
  1592. memset(&info, 0x0, sizeof(info));
  1593. rc = dp_connector_get_info(NULL, &info, display);
  1594. if (rc) {
  1595. SDE_ERROR("dp get_info %d failed\n", i);
  1596. continue;
  1597. }
  1598. encoder = sde_encoder_init(dev, &info);
  1599. if (IS_ERR_OR_NULL(encoder)) {
  1600. SDE_ERROR("dp encoder init failed %d\n", i);
  1601. continue;
  1602. }
  1603. rc = dp_drm_bridge_init(display, encoder,
  1604. max_dp_mixer_count, max_dp_dsc_count);
  1605. if (rc) {
  1606. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1607. sde_encoder_destroy(encoder);
  1608. continue;
  1609. }
  1610. connector = sde_connector_init(dev,
  1611. encoder,
  1612. NULL,
  1613. display,
  1614. &dp_ops,
  1615. DRM_CONNECTOR_POLL_HPD,
  1616. DRM_MODE_CONNECTOR_DisplayPort);
  1617. if (connector) {
  1618. priv->encoders[priv->num_encoders++] = encoder;
  1619. priv->connectors[priv->num_connectors++] = connector;
  1620. } else {
  1621. SDE_ERROR("dp %d connector init failed\n", i);
  1622. dp_drm_bridge_deinit(display);
  1623. sde_encoder_destroy(encoder);
  1624. }
  1625. /* update display cap to MST_MODE for DP MST encoders */
  1626. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1627. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1628. priv->num_encoders < max_encoders; idx++) {
  1629. info.h_tile_instance[0] = idx;
  1630. encoder = sde_encoder_init(dev, &info);
  1631. if (IS_ERR_OR_NULL(encoder)) {
  1632. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1633. continue;
  1634. }
  1635. rc = dp_mst_drm_bridge_init(display, encoder);
  1636. if (rc) {
  1637. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1638. i, rc);
  1639. sde_encoder_destroy(encoder);
  1640. continue;
  1641. }
  1642. priv->encoders[priv->num_encoders++] = encoder;
  1643. }
  1644. }
  1645. return 0;
  1646. }
  1647. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1648. {
  1649. struct msm_drm_private *priv;
  1650. int i;
  1651. if (!sde_kms) {
  1652. SDE_ERROR("invalid sde_kms\n");
  1653. return;
  1654. } else if (!sde_kms->dev) {
  1655. SDE_ERROR("invalid dev\n");
  1656. return;
  1657. } else if (!sde_kms->dev->dev_private) {
  1658. SDE_ERROR("invalid dev_private\n");
  1659. return;
  1660. }
  1661. priv = sde_kms->dev->dev_private;
  1662. for (i = 0; i < priv->num_crtcs; i++)
  1663. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1664. priv->num_crtcs = 0;
  1665. for (i = 0; i < priv->num_planes; i++)
  1666. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1667. priv->num_planes = 0;
  1668. for (i = 0; i < priv->num_connectors; i++)
  1669. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1670. priv->num_connectors = 0;
  1671. for (i = 0; i < priv->num_encoders; i++)
  1672. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1673. priv->num_encoders = 0;
  1674. _sde_kms_release_displays(sde_kms);
  1675. }
  1676. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1677. {
  1678. struct drm_device *dev;
  1679. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1680. struct drm_crtc *crtc;
  1681. struct msm_drm_private *priv;
  1682. struct sde_mdss_cfg *catalog;
  1683. int primary_planes_idx = 0, i, ret;
  1684. int max_crtc_count;
  1685. u32 sspp_id[MAX_PLANES];
  1686. u32 master_plane_id[MAX_PLANES];
  1687. u32 num_virt_planes = 0;
  1688. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1689. SDE_ERROR("invalid sde_kms\n");
  1690. return -EINVAL;
  1691. }
  1692. dev = sde_kms->dev;
  1693. priv = dev->dev_private;
  1694. catalog = sde_kms->catalog;
  1695. ret = sde_core_irq_domain_add(sde_kms);
  1696. if (ret)
  1697. goto fail_irq;
  1698. /*
  1699. * Query for underlying display drivers, and create connectors,
  1700. * bridges and encoders for them.
  1701. */
  1702. if (!_sde_kms_get_displays(sde_kms))
  1703. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1704. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1705. /* Create the planes */
  1706. for (i = 0; i < catalog->sspp_count; i++) {
  1707. bool primary = true;
  1708. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1709. || primary_planes_idx >= max_crtc_count)
  1710. primary = false;
  1711. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1712. (1UL << max_crtc_count) - 1, 0);
  1713. if (IS_ERR(plane)) {
  1714. SDE_ERROR("sde_plane_init failed\n");
  1715. ret = PTR_ERR(plane);
  1716. goto fail;
  1717. }
  1718. priv->planes[priv->num_planes++] = plane;
  1719. if (primary)
  1720. primary_planes[primary_planes_idx++] = plane;
  1721. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1722. sde_is_custom_client()) {
  1723. int priority =
  1724. catalog->sspp[i].sblk->smart_dma_priority;
  1725. sspp_id[priority - 1] = catalog->sspp[i].id;
  1726. master_plane_id[priority - 1] = plane->base.id;
  1727. num_virt_planes++;
  1728. }
  1729. }
  1730. /* Initialize smart DMA virtual planes */
  1731. for (i = 0; i < num_virt_planes; i++) {
  1732. plane = sde_plane_init(dev, sspp_id[i], false,
  1733. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1734. if (IS_ERR(plane)) {
  1735. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1736. ret = PTR_ERR(plane);
  1737. goto fail;
  1738. }
  1739. priv->planes[priv->num_planes++] = plane;
  1740. }
  1741. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1742. /* Create one CRTC per encoder */
  1743. for (i = 0; i < max_crtc_count; i++) {
  1744. crtc = sde_crtc_init(dev, primary_planes[i]);
  1745. if (IS_ERR(crtc)) {
  1746. ret = PTR_ERR(crtc);
  1747. goto fail;
  1748. }
  1749. priv->crtcs[priv->num_crtcs++] = crtc;
  1750. }
  1751. if (sde_is_custom_client()) {
  1752. /* All CRTCs are compatible with all planes */
  1753. for (i = 0; i < priv->num_planes; i++)
  1754. priv->planes[i]->possible_crtcs =
  1755. (1 << priv->num_crtcs) - 1;
  1756. }
  1757. /* All CRTCs are compatible with all encoders */
  1758. for (i = 0; i < priv->num_encoders; i++)
  1759. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1760. return 0;
  1761. fail:
  1762. _sde_kms_drm_obj_destroy(sde_kms);
  1763. fail_irq:
  1764. sde_core_irq_domain_fini(sde_kms);
  1765. return ret;
  1766. }
  1767. /**
  1768. * sde_kms_timeline_status - provides current timeline status
  1769. * This API should be called without mode config lock.
  1770. * @dev: Pointer to drm device
  1771. */
  1772. void sde_kms_timeline_status(struct drm_device *dev)
  1773. {
  1774. struct drm_crtc *crtc;
  1775. struct drm_connector *conn;
  1776. struct drm_connector_list_iter conn_iter;
  1777. if (!dev) {
  1778. SDE_ERROR("invalid drm device node\n");
  1779. return;
  1780. }
  1781. drm_for_each_crtc(crtc, dev)
  1782. sde_crtc_timeline_status(crtc);
  1783. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1784. /*
  1785. *Probably locked from last close dumping status anyway
  1786. */
  1787. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1788. drm_connector_list_iter_begin(dev, &conn_iter);
  1789. drm_for_each_connector_iter(conn, &conn_iter)
  1790. sde_conn_timeline_status(conn);
  1791. drm_connector_list_iter_end(&conn_iter);
  1792. return;
  1793. }
  1794. mutex_lock(&dev->mode_config.mutex);
  1795. drm_connector_list_iter_begin(dev, &conn_iter);
  1796. drm_for_each_connector_iter(conn, &conn_iter)
  1797. sde_conn_timeline_status(conn);
  1798. drm_connector_list_iter_end(&conn_iter);
  1799. mutex_unlock(&dev->mode_config.mutex);
  1800. }
  1801. static int sde_kms_postinit(struct msm_kms *kms)
  1802. {
  1803. struct sde_kms *sde_kms = to_sde_kms(kms);
  1804. struct drm_device *dev;
  1805. struct drm_crtc *crtc;
  1806. int rc;
  1807. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1808. SDE_ERROR("invalid sde_kms\n");
  1809. return -EINVAL;
  1810. }
  1811. dev = sde_kms->dev;
  1812. rc = _sde_debugfs_init(sde_kms);
  1813. if (rc)
  1814. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1815. drm_for_each_crtc(crtc, dev)
  1816. sde_crtc_post_init(dev, crtc);
  1817. return rc;
  1818. }
  1819. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1820. struct drm_encoder *encoder)
  1821. {
  1822. return rate;
  1823. }
  1824. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1825. struct platform_device *pdev)
  1826. {
  1827. struct drm_device *dev;
  1828. struct msm_drm_private *priv;
  1829. struct sde_vm_ops *vm_ops;
  1830. int i;
  1831. if (!sde_kms || !pdev)
  1832. return;
  1833. dev = sde_kms->dev;
  1834. if (!dev)
  1835. return;
  1836. priv = dev->dev_private;
  1837. if (!priv)
  1838. return;
  1839. if (sde_kms->genpd_init) {
  1840. sde_kms->genpd_init = false;
  1841. pm_genpd_remove(&sde_kms->genpd);
  1842. of_genpd_del_provider(pdev->dev.of_node);
  1843. }
  1844. vm_ops = sde_vm_get_ops(sde_kms);
  1845. if (vm_ops && vm_ops->vm_deinit)
  1846. vm_ops->vm_deinit(sde_kms, vm_ops);
  1847. if (sde_kms->hw_intr)
  1848. sde_hw_intr_destroy(sde_kms->hw_intr);
  1849. sde_kms->hw_intr = NULL;
  1850. if (sde_kms->power_event)
  1851. sde_power_handle_unregister_event(
  1852. &priv->phandle, sde_kms->power_event);
  1853. _sde_kms_release_displays(sde_kms);
  1854. _sde_kms_unmap_all_splash_regions(sde_kms);
  1855. if (sde_kms->catalog) {
  1856. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1857. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1858. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1859. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1860. }
  1861. }
  1862. if (sde_kms->rm_init)
  1863. sde_rm_destroy(&sde_kms->rm);
  1864. sde_kms->rm_init = false;
  1865. if (sde_kms->catalog)
  1866. sde_hw_catalog_deinit(sde_kms->catalog);
  1867. sde_kms->catalog = NULL;
  1868. if (sde_kms->sid)
  1869. msm_iounmap(pdev, sde_kms->sid);
  1870. sde_kms->sid = NULL;
  1871. if (sde_kms->reg_dma)
  1872. msm_iounmap(pdev, sde_kms->reg_dma);
  1873. sde_kms->reg_dma = NULL;
  1874. if (sde_kms->vbif[VBIF_NRT])
  1875. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1876. sde_kms->vbif[VBIF_NRT] = NULL;
  1877. if (sde_kms->vbif[VBIF_RT])
  1878. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1879. sde_kms->vbif[VBIF_RT] = NULL;
  1880. if (sde_kms->mmio)
  1881. msm_iounmap(pdev, sde_kms->mmio);
  1882. sde_kms->mmio = NULL;
  1883. sde_reg_dma_deinit();
  1884. _sde_kms_mmu_destroy(sde_kms);
  1885. }
  1886. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1887. {
  1888. int i;
  1889. if (!sde_kms)
  1890. return -EINVAL;
  1891. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1892. struct msm_mmu *mmu;
  1893. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1894. if (!aspace)
  1895. continue;
  1896. mmu = sde_kms->aspace[i]->mmu;
  1897. if (secure_only &&
  1898. !aspace->mmu->funcs->is_domain_secure(mmu))
  1899. continue;
  1900. /* cleanup aspace before detaching */
  1901. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1902. SDE_DEBUG("Detaching domain:%d\n", i);
  1903. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1904. ARRAY_SIZE(iommu_ports));
  1905. aspace->domain_attached = false;
  1906. }
  1907. return 0;
  1908. }
  1909. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1910. {
  1911. int i;
  1912. if (!sde_kms)
  1913. return -EINVAL;
  1914. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1915. struct msm_mmu *mmu;
  1916. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1917. if (!aspace)
  1918. continue;
  1919. mmu = sde_kms->aspace[i]->mmu;
  1920. if (secure_only &&
  1921. !aspace->mmu->funcs->is_domain_secure(mmu))
  1922. continue;
  1923. SDE_DEBUG("Attaching domain:%d\n", i);
  1924. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1925. ARRAY_SIZE(iommu_ports));
  1926. aspace->domain_attached = true;
  1927. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1928. }
  1929. return 0;
  1930. }
  1931. static void sde_kms_destroy(struct msm_kms *kms)
  1932. {
  1933. struct sde_kms *sde_kms;
  1934. struct drm_device *dev;
  1935. if (!kms) {
  1936. SDE_ERROR("invalid kms\n");
  1937. return;
  1938. }
  1939. sde_kms = to_sde_kms(kms);
  1940. dev = sde_kms->dev;
  1941. if (!dev || !dev->dev) {
  1942. SDE_ERROR("invalid device\n");
  1943. return;
  1944. }
  1945. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1946. kfree(sde_kms);
  1947. }
  1948. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1949. struct drm_atomic_state *state)
  1950. {
  1951. struct drm_device *dev = sde_kms->dev;
  1952. struct drm_plane *plane;
  1953. struct drm_plane_state *plane_state;
  1954. struct drm_crtc *crtc;
  1955. struct drm_crtc_state *crtc_state;
  1956. struct drm_connector *conn;
  1957. struct drm_connector_state *conn_state;
  1958. struct drm_connector_list_iter conn_iter;
  1959. int ret = 0;
  1960. drm_for_each_plane(plane, dev) {
  1961. plane_state = drm_atomic_get_plane_state(state, plane);
  1962. if (IS_ERR(plane_state)) {
  1963. ret = PTR_ERR(plane_state);
  1964. SDE_ERROR("error %d getting plane %d state\n",
  1965. ret, DRMID(plane));
  1966. return ret;
  1967. }
  1968. ret = sde_plane_helper_reset_custom_properties(plane,
  1969. plane_state);
  1970. if (ret) {
  1971. SDE_ERROR("error %d resetting plane props %d\n",
  1972. ret, DRMID(plane));
  1973. return ret;
  1974. }
  1975. }
  1976. drm_for_each_crtc(crtc, dev) {
  1977. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1978. if (IS_ERR(crtc_state)) {
  1979. ret = PTR_ERR(crtc_state);
  1980. SDE_ERROR("error %d getting crtc %d state\n",
  1981. ret, DRMID(crtc));
  1982. return ret;
  1983. }
  1984. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1985. if (ret) {
  1986. SDE_ERROR("error %d resetting crtc props %d\n",
  1987. ret, DRMID(crtc));
  1988. return ret;
  1989. }
  1990. }
  1991. drm_connector_list_iter_begin(dev, &conn_iter);
  1992. drm_for_each_connector_iter(conn, &conn_iter) {
  1993. conn_state = drm_atomic_get_connector_state(state, conn);
  1994. if (IS_ERR(conn_state)) {
  1995. ret = PTR_ERR(conn_state);
  1996. SDE_ERROR("error %d getting connector %d state\n",
  1997. ret, DRMID(conn));
  1998. return ret;
  1999. }
  2000. ret = sde_connector_helper_reset_custom_properties(conn,
  2001. conn_state);
  2002. if (ret) {
  2003. SDE_ERROR("error %d resetting connector props %d\n",
  2004. ret, DRMID(conn));
  2005. return ret;
  2006. }
  2007. }
  2008. drm_connector_list_iter_end(&conn_iter);
  2009. return ret;
  2010. }
  2011. static void sde_kms_lastclose(struct msm_kms *kms)
  2012. {
  2013. struct sde_kms *sde_kms;
  2014. struct drm_device *dev;
  2015. struct drm_atomic_state *state;
  2016. struct drm_modeset_acquire_ctx ctx;
  2017. int ret;
  2018. if (!kms) {
  2019. SDE_ERROR("invalid argument\n");
  2020. return;
  2021. }
  2022. sde_kms = to_sde_kms(kms);
  2023. dev = sde_kms->dev;
  2024. drm_modeset_acquire_init(&ctx, 0);
  2025. state = drm_atomic_state_alloc(dev);
  2026. if (!state) {
  2027. ret = -ENOMEM;
  2028. goto out_ctx;
  2029. }
  2030. state->acquire_ctx = &ctx;
  2031. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2032. retry:
  2033. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2034. if (ret)
  2035. goto out_state;
  2036. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2037. if (ret)
  2038. goto out_state;
  2039. ret = drm_atomic_commit(state);
  2040. out_state:
  2041. if (ret == -EDEADLK)
  2042. goto backoff;
  2043. drm_atomic_state_put(state);
  2044. out_ctx:
  2045. drm_modeset_drop_locks(&ctx);
  2046. drm_modeset_acquire_fini(&ctx);
  2047. if (ret)
  2048. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2049. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2050. return;
  2051. backoff:
  2052. drm_atomic_state_clear(state);
  2053. drm_modeset_backoff(&ctx);
  2054. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2055. goto retry;
  2056. }
  2057. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2058. struct drm_atomic_state *state)
  2059. {
  2060. struct sde_kms *sde_kms;
  2061. struct drm_device *dev;
  2062. struct drm_crtc *crtc;
  2063. struct drm_encoder *encoder;
  2064. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2065. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2066. uint32_t crtc_encoder_cnt = 0;
  2067. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2068. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2069. struct sde_vm_ops *vm_ops;
  2070. bool vm_req_active = false;
  2071. enum sde_crtc_idle_pc_state idle_pc_state;
  2072. struct sde_mdss_cfg *catalog;
  2073. int rc = 0;
  2074. struct sde_connector *sde_conn;
  2075. struct dsi_display *dsi_display;
  2076. struct drm_connector *connector;
  2077. struct drm_connector_state *new_connstate;
  2078. if (!kms || !state)
  2079. return -EINVAL;
  2080. sde_kms = to_sde_kms(kms);
  2081. dev = sde_kms->dev;
  2082. catalog = sde_kms->catalog;
  2083. vm_ops = sde_vm_get_ops(sde_kms);
  2084. if (!vm_ops)
  2085. return 0;
  2086. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw ||
  2087. !vm_ops->vm_acquire)
  2088. return -EINVAL;
  2089. sde_vm_lock(sde_kms);
  2090. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2091. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2092. if (!new_cstate->active && !old_cstate->active)
  2093. continue;
  2094. new_state = to_sde_crtc_state(new_cstate);
  2095. new_vm_req = sde_crtc_get_property(new_state,
  2096. CRTC_PROP_VM_REQ_STATE);
  2097. old_state = to_sde_crtc_state(old_cstate);
  2098. old_vm_req = sde_crtc_get_property(old_state,
  2099. CRTC_PROP_VM_REQ_STATE);
  2100. /*
  2101. * No active request if the transition is from
  2102. * VM_REQ_NONE to VM_REQ_NONE
  2103. */
  2104. if (old_vm_req || new_vm_req) {
  2105. rc = vm_ops->vm_request_valid(sde_kms,
  2106. old_vm_req, new_vm_req);
  2107. if (rc) {
  2108. SDE_ERROR(
  2109. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2110. old_vm_req, new_vm_req,
  2111. vm_ops->vm_owns_hw(sde_kms), rc);
  2112. goto end;
  2113. } else if (old_vm_req == VM_REQ_ACQUIRE &&
  2114. new_vm_req == VM_REQ_NONE) {
  2115. SDE_DEBUG(
  2116. "VM transition valid; ignore further checks\n");
  2117. } else {
  2118. vm_req_active = true;
  2119. }
  2120. }
  2121. idle_pc_state = sde_crtc_get_property(new_state,
  2122. CRTC_PROP_IDLE_PC_STATE);
  2123. active_crtc = crtc;
  2124. active_cstate = new_cstate;
  2125. commit_crtc_cnt++;
  2126. }
  2127. /* return early if no active vm request */
  2128. if (!vm_req_active)
  2129. goto end;
  2130. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2131. if (!crtc->state->active)
  2132. continue;
  2133. global_crtc_cnt++;
  2134. global_active_crtc = crtc;
  2135. }
  2136. if (active_crtc) {
  2137. drm_for_each_encoder_mask(encoder, active_crtc->dev,
  2138. active_cstate->encoder_mask)
  2139. crtc_encoder_cnt++;
  2140. }
  2141. SDE_EVT32(old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2142. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d\n", old_vm_req,
  2143. new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2144. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2145. int conn_mask = active_cstate->connector_mask;
  2146. if (drm_connector_mask(connector) & conn_mask) {
  2147. sde_conn = to_sde_connector(connector);
  2148. dsi_display = (struct dsi_display *) sde_conn->display;
  2149. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i,
  2150. dsi_display->type,
  2151. dsi_display->trusted_vm_env);
  2152. SDE_DEBUG(
  2153. "VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d,",
  2154. dsi_display->name, DRMID(connector),
  2155. DRMID(active_crtc), dsi_display->type,
  2156. dsi_display->trusted_vm_env);
  2157. break;
  2158. }
  2159. }
  2160. /* Check for single crtc commits only on valid VM requests */
  2161. if (active_crtc && global_active_crtc &&
  2162. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2163. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2164. active_crtc != global_active_crtc)) {
  2165. SDE_ERROR(
  2166. "VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2167. catalog->max_trusted_vm_displays,
  2168. commit_crtc_cnt, global_crtc_cnt, DRMID(active_crtc),
  2169. DRMID(global_active_crtc));
  2170. rc = -E2BIG;
  2171. goto end;
  2172. } else if ((new_vm_req == VM_REQ_RELEASE) &&
  2173. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2174. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2175. /*
  2176. * disable idle-pc before releasing the HW
  2177. * allow only specified number of encoders on a given crtc
  2178. */
  2179. SDE_ERROR(
  2180. "VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2181. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC,
  2182. crtc_encoder_cnt);
  2183. rc = -EINVAL;
  2184. goto end;
  2185. }
  2186. if ((new_vm_req == VM_REQ_ACQUIRE) && !vm_ops->vm_owns_hw(sde_kms)) {
  2187. rc = vm_ops->vm_acquire(sde_kms);
  2188. if (rc) {
  2189. SDE_ERROR(
  2190. "VM acquire failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2191. old_vm_req, new_vm_req,
  2192. vm_ops->vm_owns_hw(sde_kms), rc);
  2193. goto end;
  2194. }
  2195. if (vm_ops->vm_resource_init)
  2196. rc = vm_ops->vm_resource_init(sde_kms, state);
  2197. }
  2198. end:
  2199. sde_vm_unlock(sde_kms);
  2200. return rc;
  2201. }
  2202. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2203. struct drm_atomic_state *state)
  2204. {
  2205. struct sde_kms *sde_kms;
  2206. struct drm_device *dev;
  2207. struct drm_crtc *crtc;
  2208. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2209. struct drm_crtc_state *crtc_state;
  2210. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2211. bool sec_session = false, global_sec_session = false;
  2212. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2213. int i;
  2214. if (!kms || !state) {
  2215. return -EINVAL;
  2216. SDE_ERROR("invalid arguments\n");
  2217. }
  2218. sde_kms = to_sde_kms(kms);
  2219. dev = sde_kms->dev;
  2220. /* iterate state object for active secure/non-secure crtc */
  2221. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2222. if (!crtc_state->active)
  2223. continue;
  2224. active_crtc_cnt++;
  2225. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2226. &fb_sec, &fb_sec_dir);
  2227. if (fb_sec_dir)
  2228. sec_session = true;
  2229. cur_crtc = crtc;
  2230. }
  2231. /* iterate global list for active and secure/non-secure crtc */
  2232. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2233. if (!crtc->state->active)
  2234. continue;
  2235. global_active_crtc_cnt++;
  2236. /* update only when crtc is not the same as current crtc */
  2237. if (crtc != cur_crtc) {
  2238. fb_ns = fb_sec = fb_sec_dir = 0;
  2239. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2240. &fb_sec, &fb_sec_dir);
  2241. if (fb_sec_dir)
  2242. global_sec_session = true;
  2243. global_crtc = crtc;
  2244. }
  2245. }
  2246. if (!global_sec_session && !sec_session)
  2247. return 0;
  2248. /*
  2249. * - fail crtc commit, if secure-camera/secure-ui session is
  2250. * in-progress in any other display
  2251. * - fail secure-camera/secure-ui crtc commit, if any other display
  2252. * session is in-progress
  2253. */
  2254. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2255. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2256. SDE_ERROR(
  2257. "crtc%d secure check failed global_active:%d active:%d\n",
  2258. cur_crtc ? cur_crtc->base.id : -1,
  2259. global_active_crtc_cnt, active_crtc_cnt);
  2260. return -EPERM;
  2261. /*
  2262. * As only one crtc is allowed during secure session, the crtc
  2263. * in this commit should match with the global crtc
  2264. */
  2265. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2266. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2267. cur_crtc->base.id, sec_session,
  2268. global_crtc->base.id, global_sec_session);
  2269. return -EPERM;
  2270. }
  2271. return 0;
  2272. }
  2273. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2274. struct drm_atomic_state *state)
  2275. {
  2276. struct drm_crtc *crtc;
  2277. struct drm_crtc_state *new_cstate;
  2278. struct sde_crtc_state *cstate;
  2279. struct sde_vm_ops *vm_ops;
  2280. enum sde_crtc_vm_req vm_req;
  2281. struct sde_kms *sde_kms = to_sde_kms(kms);
  2282. vm_ops = sde_vm_get_ops(sde_kms);
  2283. if (!vm_ops)
  2284. return;
  2285. crtc = sde_kms_vm_get_vm_crtc(state);
  2286. if (!crtc)
  2287. return;
  2288. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2289. cstate = to_sde_crtc_state(new_cstate);
  2290. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2291. if (vm_req != VM_REQ_ACQUIRE)
  2292. return;
  2293. sde_vm_lock(sde_kms);
  2294. if (vm_ops->vm_acquire_fail_handler)
  2295. vm_ops->vm_acquire_fail_handler(sde_kms);
  2296. sde_vm_unlock(sde_kms);
  2297. }
  2298. static int sde_kms_atomic_check(struct msm_kms *kms,
  2299. struct drm_atomic_state *state)
  2300. {
  2301. struct sde_kms *sde_kms;
  2302. struct drm_device *dev;
  2303. int ret;
  2304. if (!kms || !state)
  2305. return -EINVAL;
  2306. sde_kms = to_sde_kms(kms);
  2307. dev = sde_kms->dev;
  2308. SDE_ATRACE_BEGIN("atomic_check");
  2309. if (sde_kms_is_suspend_blocked(dev)) {
  2310. SDE_DEBUG("suspended, skip atomic_check\n");
  2311. ret = -EBUSY;
  2312. goto end;
  2313. }
  2314. ret = sde_kms_check_vm_request(kms, state);
  2315. if (ret) {
  2316. SDE_ERROR("vm switch request checks failed\n");
  2317. goto end;
  2318. }
  2319. ret = drm_atomic_helper_check(dev, state);
  2320. if (ret)
  2321. goto vm_clean_up;
  2322. /*
  2323. * Check if any secure transition(moving CRTC between secure and
  2324. * non-secure state and vice-versa) is allowed or not. when moving
  2325. * to secure state, planes with fb_mode set to dir_translated only can
  2326. * be staged on the CRTC, and only one CRTC can be active during
  2327. * Secure state
  2328. */
  2329. ret = sde_kms_check_secure_transition(kms, state);
  2330. if (ret)
  2331. goto vm_clean_up;
  2332. goto end;
  2333. vm_clean_up:
  2334. sde_kms_vm_res_release(kms, state);
  2335. end:
  2336. SDE_ATRACE_END("atomic_check");
  2337. return ret;
  2338. }
  2339. static struct msm_gem_address_space*
  2340. _sde_kms_get_address_space(struct msm_kms *kms,
  2341. unsigned int domain)
  2342. {
  2343. struct sde_kms *sde_kms;
  2344. if (!kms) {
  2345. SDE_ERROR("invalid kms\n");
  2346. return NULL;
  2347. }
  2348. sde_kms = to_sde_kms(kms);
  2349. if (!sde_kms) {
  2350. SDE_ERROR("invalid sde_kms\n");
  2351. return NULL;
  2352. }
  2353. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2354. return NULL;
  2355. return (sde_kms->aspace[domain] &&
  2356. sde_kms->aspace[domain]->domain_attached) ?
  2357. sde_kms->aspace[domain] : NULL;
  2358. }
  2359. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2360. unsigned int domain)
  2361. {
  2362. struct sde_kms *sde_kms;
  2363. struct msm_gem_address_space *aspace;
  2364. if (!kms) {
  2365. SDE_ERROR("invalid kms\n");
  2366. return NULL;
  2367. }
  2368. sde_kms = to_sde_kms(kms);
  2369. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2370. SDE_ERROR("invalid params\n");
  2371. return NULL;
  2372. }
  2373. aspace = _sde_kms_get_address_space(kms, domain);
  2374. return (aspace && aspace->domain_attached) ?
  2375. msm_gem_get_aspace_device(aspace) : NULL;
  2376. }
  2377. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2378. {
  2379. struct drm_device *dev = NULL;
  2380. struct sde_kms *sde_kms = NULL;
  2381. struct drm_connector *connector = NULL;
  2382. struct drm_connector_list_iter conn_iter;
  2383. struct sde_connector *sde_conn = NULL;
  2384. if (!kms) {
  2385. SDE_ERROR("invalid kms\n");
  2386. return;
  2387. }
  2388. sde_kms = to_sde_kms(kms);
  2389. dev = sde_kms->dev;
  2390. if (!dev) {
  2391. SDE_ERROR("invalid device\n");
  2392. return;
  2393. }
  2394. if (!dev->mode_config.poll_enabled)
  2395. return;
  2396. mutex_lock(&dev->mode_config.mutex);
  2397. drm_connector_list_iter_begin(dev, &conn_iter);
  2398. drm_for_each_connector_iter(connector, &conn_iter) {
  2399. /* Only handle HPD capable connectors. */
  2400. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2401. continue;
  2402. sde_conn = to_sde_connector(connector);
  2403. if (sde_conn->ops.post_open)
  2404. sde_conn->ops.post_open(&sde_conn->base,
  2405. sde_conn->display);
  2406. }
  2407. drm_connector_list_iter_end(&conn_iter);
  2408. mutex_unlock(&dev->mode_config.mutex);
  2409. }
  2410. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2411. struct sde_splash_display *splash_display,
  2412. struct drm_crtc *crtc)
  2413. {
  2414. struct msm_drm_private *priv;
  2415. struct drm_plane *plane;
  2416. struct sde_splash_mem *splash;
  2417. enum sde_sspp plane_id;
  2418. bool is_virtual;
  2419. int i, j;
  2420. if (!sde_kms || !splash_display || !crtc) {
  2421. SDE_ERROR("invalid input args\n");
  2422. return -EINVAL;
  2423. }
  2424. priv = sde_kms->dev->dev_private;
  2425. for (i = 0; i < priv->num_planes; i++) {
  2426. plane = priv->planes[i];
  2427. plane_id = sde_plane_pipe(plane);
  2428. is_virtual = is_sde_plane_virtual(plane);
  2429. splash = splash_display->splash;
  2430. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2431. if ((plane_id != splash_display->pipes[j].sspp) ||
  2432. (splash_display->pipes[j].is_virtual
  2433. != is_virtual))
  2434. continue;
  2435. if (splash && sde_plane_validate_src_addr(plane,
  2436. splash->splash_buf_base,
  2437. splash->splash_buf_size)) {
  2438. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2439. plane_id, crtc->base.id);
  2440. }
  2441. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2442. crtc->base.id, plane_id, is_virtual);
  2443. }
  2444. }
  2445. return 0;
  2446. }
  2447. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2448. struct dsi_display *dsi_display)
  2449. {
  2450. void *display;
  2451. struct drm_encoder *encoder = NULL;
  2452. struct msm_display_info info;
  2453. struct drm_device *dev;
  2454. struct sde_kms *sde_kms;
  2455. struct drm_connector_list_iter conn_iter;
  2456. struct drm_connector *connector = NULL;
  2457. struct sde_connector *sde_conn = NULL;
  2458. int rc = 0;
  2459. sde_kms = to_sde_kms(kms);
  2460. dev = sde_kms->dev;
  2461. display = dsi_display;
  2462. if (dsi_display) {
  2463. if (dsi_display->bridge->base.encoder) {
  2464. encoder = dsi_display->bridge->base.encoder;
  2465. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2466. }
  2467. memset(&info, 0x0, sizeof(info));
  2468. rc = dsi_display_get_info(NULL, &info, display);
  2469. if (rc) {
  2470. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2471. rc, __func__);
  2472. encoder = NULL;
  2473. }
  2474. }
  2475. drm_connector_list_iter_begin(dev, &conn_iter);
  2476. drm_for_each_connector_iter(connector, &conn_iter) {
  2477. /**
  2478. * Inform cont_splash is disabled to each interface/connector.
  2479. * This is currently supported for DSI interface.
  2480. */
  2481. sde_conn = to_sde_connector(connector);
  2482. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2483. if (!dsi_display || !encoder) {
  2484. sde_conn->ops.cont_splash_res_disable
  2485. (sde_conn->display);
  2486. } else if (connector->encoder_ids[0]
  2487. == encoder->base.id) {
  2488. /**
  2489. * This handles dual DSI
  2490. * configuration where one DSI
  2491. * interface has cont_splash
  2492. * enabled and the other doesn't.
  2493. */
  2494. sde_conn->ops.cont_splash_res_disable
  2495. (sde_conn->display);
  2496. break;
  2497. }
  2498. }
  2499. }
  2500. drm_connector_list_iter_end(&conn_iter);
  2501. return 0;
  2502. }
  2503. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2504. {
  2505. int i;
  2506. void *display;
  2507. struct dsi_display *dsi_display;
  2508. struct drm_encoder *encoder;
  2509. if (!sde_kms)
  2510. return -EINVAL;
  2511. if (!sde_in_trusted_vm(sde_kms))
  2512. return 0;
  2513. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2514. display = sde_kms->dsi_displays[i];
  2515. dsi_display = (struct dsi_display *)display;
  2516. if (!dsi_display->bridge->base.encoder) {
  2517. SDE_ERROR("no encoder on dsi display:%d", i);
  2518. return -EINVAL;
  2519. }
  2520. encoder = dsi_display->bridge->base.encoder;
  2521. encoder->possible_crtcs = 1 << i;
  2522. SDE_DEBUG(
  2523. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2524. encoder->index, encoder->base.id,
  2525. encoder->name, encoder->possible_crtcs);
  2526. }
  2527. return 0;
  2528. }
  2529. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2530. struct sde_kms *sde_kms, struct drm_connector *connector,
  2531. struct drm_atomic_state *state)
  2532. {
  2533. struct drm_display_mode *mode, *cur_mode = NULL;
  2534. struct drm_crtc *crtc;
  2535. struct drm_crtc_state *new_cstate, *old_cstate;
  2536. u32 i = 0;
  2537. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2538. list_for_each_entry(mode, &connector->modes, head) {
  2539. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2540. cur_mode = mode;
  2541. break;
  2542. }
  2543. }
  2544. } else if (state) {
  2545. /* get the mode from first atomic_check phase for trusted_vm*/
  2546. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2547. new_cstate, i) {
  2548. if (!new_cstate->active && !old_cstate->active)
  2549. continue;
  2550. list_for_each_entry(mode, &connector->modes, head) {
  2551. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2552. cur_mode = mode;
  2553. break;
  2554. }
  2555. }
  2556. }
  2557. }
  2558. return cur_mode;
  2559. }
  2560. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2561. struct drm_atomic_state *state)
  2562. {
  2563. void *display;
  2564. struct dsi_display *dsi_display;
  2565. struct msm_display_info info;
  2566. struct drm_encoder *encoder = NULL;
  2567. struct drm_crtc *crtc = NULL;
  2568. int i, rc = 0;
  2569. struct drm_display_mode *drm_mode = NULL;
  2570. struct drm_device *dev;
  2571. struct msm_drm_private *priv;
  2572. struct sde_kms *sde_kms;
  2573. struct drm_connector_list_iter conn_iter;
  2574. struct drm_connector *connector = NULL;
  2575. struct sde_connector *sde_conn = NULL;
  2576. struct sde_splash_display *splash_display;
  2577. if (!kms) {
  2578. SDE_ERROR("invalid kms\n");
  2579. return -EINVAL;
  2580. }
  2581. sde_kms = to_sde_kms(kms);
  2582. dev = sde_kms->dev;
  2583. if (!dev) {
  2584. SDE_ERROR("invalid device\n");
  2585. return -EINVAL;
  2586. }
  2587. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2588. if (rc) {
  2589. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2590. return -EINVAL;
  2591. }
  2592. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2593. && (!sde_kms->splash_data.num_splash_regions)) ||
  2594. !sde_kms->splash_data.num_splash_displays) {
  2595. DRM_INFO("cont_splash feature not enabled\n");
  2596. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2597. return rc;
  2598. }
  2599. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2600. sde_kms->splash_data.num_splash_displays,
  2601. sde_kms->dsi_display_count);
  2602. /* dsi */
  2603. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2604. display = sde_kms->dsi_displays[i];
  2605. dsi_display = (struct dsi_display *)display;
  2606. splash_display = &sde_kms->splash_data.splash_display[i];
  2607. if (!splash_display->cont_splash_enabled) {
  2608. SDE_DEBUG("display->name = %s splash not enabled\n",
  2609. dsi_display->name);
  2610. sde_kms_inform_cont_splash_res_disable(kms,
  2611. dsi_display);
  2612. continue;
  2613. }
  2614. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2615. if (dsi_display->bridge->base.encoder) {
  2616. encoder = dsi_display->bridge->base.encoder;
  2617. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2618. }
  2619. memset(&info, 0x0, sizeof(info));
  2620. rc = dsi_display_get_info(NULL, &info, display);
  2621. if (rc) {
  2622. SDE_ERROR("dsi get_info %d failed\n", i);
  2623. encoder = NULL;
  2624. continue;
  2625. }
  2626. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2627. ((info.is_connected) ? "true" : "false"),
  2628. info.display_type);
  2629. if (!encoder) {
  2630. SDE_ERROR("encoder not initialized\n");
  2631. return -EINVAL;
  2632. }
  2633. priv = sde_kms->dev->dev_private;
  2634. encoder->crtc = priv->crtcs[i];
  2635. crtc = encoder->crtc;
  2636. splash_display->encoder = encoder;
  2637. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2638. i, crtc->index, crtc->base.id, encoder->index,
  2639. encoder->base.id);
  2640. mutex_lock(&dev->mode_config.mutex);
  2641. drm_connector_list_iter_begin(dev, &conn_iter);
  2642. drm_for_each_connector_iter(connector, &conn_iter) {
  2643. /**
  2644. * SDE_KMS doesn't attach more than one encoder to
  2645. * a DSI connector. So it is safe to check only with
  2646. * the first encoder entry. Revisit this logic if we
  2647. * ever have to support continuous splash for
  2648. * external displays in MST configuration.
  2649. */
  2650. if (connector->encoder_ids[0] == encoder->base.id)
  2651. break;
  2652. }
  2653. drm_connector_list_iter_end(&conn_iter);
  2654. if (!connector) {
  2655. SDE_ERROR("connector not initialized\n");
  2656. mutex_unlock(&dev->mode_config.mutex);
  2657. return -EINVAL;
  2658. }
  2659. mutex_unlock(&dev->mode_config.mutex);
  2660. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2661. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  2662. if (!drm_mode) {
  2663. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  2664. sde_kms->splash_data.type);
  2665. return -EINVAL;
  2666. }
  2667. SDE_DEBUG(
  2668. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  2669. drm_mode->name, drm_mode->type,
  2670. drm_mode->flags, sde_kms->splash_data.type);
  2671. /* Update CRTC drm structure */
  2672. crtc->state->active = true;
  2673. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2674. if (rc) {
  2675. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2676. return rc;
  2677. }
  2678. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2679. drm_mode_copy(&crtc->mode, drm_mode);
  2680. /* Update encoder structure */
  2681. sde_encoder_update_caps_for_cont_splash(encoder,
  2682. splash_display, true);
  2683. sde_crtc_update_cont_splash_settings(crtc);
  2684. sde_conn = to_sde_connector(connector);
  2685. if (sde_conn && sde_conn->ops.cont_splash_config)
  2686. sde_conn->ops.cont_splash_config(sde_conn->display);
  2687. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2688. splash_display, crtc);
  2689. if (rc) {
  2690. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2691. return rc;
  2692. }
  2693. }
  2694. return rc;
  2695. }
  2696. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2697. {
  2698. struct sde_kms *sde_kms;
  2699. if (!kms) {
  2700. SDE_ERROR("invalid kms\n");
  2701. return false;
  2702. }
  2703. sde_kms = to_sde_kms(kms);
  2704. return sde_kms->splash_data.num_splash_displays;
  2705. }
  2706. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2707. const struct drm_display_mode *mode,
  2708. const struct msm_resource_caps_info *res, u32 *num_lm)
  2709. {
  2710. struct sde_kms *sde_kms;
  2711. s64 mode_clock_hz = 0;
  2712. s64 max_mdp_clock_hz = 0;
  2713. s64 max_lm_width = 0;
  2714. s64 hdisplay_fp = 0;
  2715. s64 htotal_fp = 0;
  2716. s64 vtotal_fp = 0;
  2717. s64 vrefresh_fp = 0;
  2718. s64 mdp_fudge_factor = 0;
  2719. s64 num_lm_fp = 0;
  2720. s64 lm_clk_fp = 0;
  2721. s64 lm_width_fp = 0;
  2722. int rc = 0;
  2723. if (!num_lm) {
  2724. SDE_ERROR("invalid num_lm pointer\n");
  2725. return -EINVAL;
  2726. }
  2727. /* default to 1 layer mixer */
  2728. *num_lm = 1;
  2729. if (!kms || !mode || !res) {
  2730. SDE_ERROR("invalid input args\n");
  2731. return -EINVAL;
  2732. }
  2733. sde_kms = to_sde_kms(kms);
  2734. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2735. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2736. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2737. htotal_fp = drm_int2fixp(mode->htotal);
  2738. vtotal_fp = drm_int2fixp(mode->vtotal);
  2739. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2740. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2741. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2742. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2743. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2744. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2745. if (mode_clock_hz > max_mdp_clock_hz ||
  2746. hdisplay_fp > max_lm_width) {
  2747. *num_lm = 0;
  2748. do {
  2749. *num_lm += 2;
  2750. num_lm_fp = drm_int2fixp(*num_lm);
  2751. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2752. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2753. if (*num_lm > 4) {
  2754. rc = -EINVAL;
  2755. goto error;
  2756. }
  2757. } while (lm_clk_fp > max_mdp_clock_hz ||
  2758. lm_width_fp > max_lm_width);
  2759. mode_clock_hz = lm_clk_fp;
  2760. }
  2761. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2762. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2763. *num_lm, drm_fixp2int(mode_clock_hz),
  2764. sde_kms->perf.max_core_clk_rate);
  2765. return 0;
  2766. error:
  2767. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2768. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2769. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2770. *num_lm, drm_fixp2int(mode_clock_hz),
  2771. sde_kms->perf.max_core_clk_rate);
  2772. return rc;
  2773. }
  2774. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2775. u32 hdisplay, u32 *num_dsc)
  2776. {
  2777. struct sde_kms *sde_kms;
  2778. uint32_t max_dsc_width;
  2779. if (!num_dsc) {
  2780. SDE_ERROR("invalid num_dsc pointer\n");
  2781. return -EINVAL;
  2782. }
  2783. *num_dsc = 0;
  2784. if (!kms || !hdisplay) {
  2785. SDE_ERROR("invalid input args\n");
  2786. return -EINVAL;
  2787. }
  2788. sde_kms = to_sde_kms(kms);
  2789. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2790. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2791. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2792. hdisplay, max_dsc_width,
  2793. *num_dsc);
  2794. return 0;
  2795. }
  2796. static void _sde_kms_null_commit(struct drm_device *dev,
  2797. struct drm_encoder *enc)
  2798. {
  2799. struct drm_modeset_acquire_ctx ctx;
  2800. struct drm_connector *conn = NULL;
  2801. struct drm_connector *tmp_conn = NULL;
  2802. struct drm_connector_list_iter conn_iter;
  2803. struct drm_atomic_state *state = NULL;
  2804. struct drm_crtc_state *crtc_state = NULL;
  2805. struct drm_connector_state *conn_state = NULL;
  2806. int retry_cnt = 0;
  2807. int ret = 0;
  2808. drm_modeset_acquire_init(&ctx, 0);
  2809. retry:
  2810. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2811. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2812. drm_modeset_backoff(&ctx);
  2813. retry_cnt++;
  2814. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2815. goto retry;
  2816. } else if (WARN_ON(ret)) {
  2817. goto end;
  2818. }
  2819. state = drm_atomic_state_alloc(dev);
  2820. if (!state) {
  2821. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2822. goto end;
  2823. }
  2824. state->acquire_ctx = &ctx;
  2825. drm_connector_list_iter_begin(dev, &conn_iter);
  2826. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2827. if (enc == tmp_conn->state->best_encoder) {
  2828. conn = tmp_conn;
  2829. break;
  2830. }
  2831. }
  2832. drm_connector_list_iter_end(&conn_iter);
  2833. if (!conn) {
  2834. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2835. goto end;
  2836. }
  2837. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2838. conn_state = drm_atomic_get_connector_state(state, conn);
  2839. if (IS_ERR(conn_state)) {
  2840. SDE_ERROR("error %d getting connector %d state\n",
  2841. ret, DRMID(conn));
  2842. goto end;
  2843. }
  2844. crtc_state->active = true;
  2845. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2846. if (ret)
  2847. SDE_ERROR("error %d setting the crtc\n", ret);
  2848. ret = drm_atomic_commit(state);
  2849. if (ret)
  2850. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2851. end:
  2852. if (state)
  2853. drm_atomic_state_put(state);
  2854. drm_modeset_drop_locks(&ctx);
  2855. drm_modeset_acquire_fini(&ctx);
  2856. }
  2857. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2858. const int32_t connector_id)
  2859. {
  2860. struct drm_connector_list_iter conn_iter;
  2861. struct drm_connector *conn;
  2862. struct drm_encoder *drm_enc;
  2863. drm_connector_list_iter_begin(dev, &conn_iter);
  2864. drm_for_each_connector_iter(conn, &conn_iter) {
  2865. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2866. connector_id != conn->base.id)
  2867. continue;
  2868. if (conn->state && conn->state->best_encoder)
  2869. drm_enc = conn->state->best_encoder;
  2870. else
  2871. drm_enc = conn->encoder;
  2872. if (drm_enc)
  2873. sde_encoder_early_wakeup(drm_enc);
  2874. }
  2875. drm_connector_list_iter_end(&conn_iter);
  2876. }
  2877. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2878. struct device *dev)
  2879. {
  2880. int i, ret, crtc_id = 0;
  2881. struct drm_device *ddev = dev_get_drvdata(dev);
  2882. struct drm_connector *conn;
  2883. struct drm_connector_list_iter conn_iter;
  2884. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2885. drm_connector_list_iter_begin(ddev, &conn_iter);
  2886. drm_for_each_connector_iter(conn, &conn_iter) {
  2887. uint64_t lp;
  2888. lp = sde_connector_get_lp(conn);
  2889. if (lp != SDE_MODE_DPMS_LP2)
  2890. continue;
  2891. if (sde_encoder_in_clone_mode(conn->encoder))
  2892. continue;
  2893. ret = sde_encoder_wait_for_event(conn->encoder,
  2894. MSM_ENC_TX_COMPLETE);
  2895. if (ret && ret != -EWOULDBLOCK) {
  2896. SDE_ERROR(
  2897. "[conn: %d] wait for commit done returned %d\n",
  2898. conn->base.id, ret);
  2899. } else if (!ret) {
  2900. crtc_id = drm_crtc_index(conn->state->crtc);
  2901. if (priv->event_thread[crtc_id].thread)
  2902. kthread_flush_worker(
  2903. &priv->event_thread[crtc_id].worker);
  2904. sde_encoder_idle_request(conn->encoder);
  2905. }
  2906. }
  2907. drm_connector_list_iter_end(&conn_iter);
  2908. for (i = 0; i < priv->num_crtcs; i++) {
  2909. if (priv->disp_thread[i].thread)
  2910. kthread_flush_worker(
  2911. &priv->disp_thread[i].worker);
  2912. if (priv->event_thread[i].thread)
  2913. kthread_flush_worker(
  2914. &priv->event_thread[i].worker);
  2915. }
  2916. kthread_flush_worker(&priv->pp_event_worker);
  2917. }
  2918. static int sde_kms_pm_suspend(struct device *dev)
  2919. {
  2920. struct drm_device *ddev;
  2921. struct drm_modeset_acquire_ctx ctx;
  2922. struct drm_connector *conn;
  2923. struct drm_encoder *enc;
  2924. struct drm_connector_list_iter conn_iter;
  2925. struct drm_atomic_state *state = NULL;
  2926. struct sde_kms *sde_kms;
  2927. int ret = 0, num_crtcs = 0;
  2928. if (!dev)
  2929. return -EINVAL;
  2930. ddev = dev_get_drvdata(dev);
  2931. if (!ddev || !ddev_to_msm_kms(ddev))
  2932. return -EINVAL;
  2933. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2934. SDE_EVT32(0);
  2935. /* disable hot-plug polling */
  2936. drm_kms_helper_poll_disable(ddev);
  2937. /* if a display stuck in CS trigger a null commit to complete handoff */
  2938. drm_for_each_encoder(enc, ddev) {
  2939. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2940. _sde_kms_null_commit(ddev, enc);
  2941. }
  2942. /* acquire modeset lock(s) */
  2943. drm_modeset_acquire_init(&ctx, 0);
  2944. retry:
  2945. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2946. if (ret)
  2947. goto unlock;
  2948. /* save current state for resume */
  2949. if (sde_kms->suspend_state)
  2950. drm_atomic_state_put(sde_kms->suspend_state);
  2951. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2952. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2953. ret = PTR_ERR(sde_kms->suspend_state);
  2954. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2955. sde_kms->suspend_state = NULL;
  2956. goto unlock;
  2957. }
  2958. /* create atomic state to disable all CRTCs */
  2959. state = drm_atomic_state_alloc(ddev);
  2960. if (!state) {
  2961. ret = -ENOMEM;
  2962. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2963. goto unlock;
  2964. }
  2965. state->acquire_ctx = &ctx;
  2966. drm_connector_list_iter_begin(ddev, &conn_iter);
  2967. drm_for_each_connector_iter(conn, &conn_iter) {
  2968. struct drm_crtc_state *crtc_state;
  2969. uint64_t lp;
  2970. if (!conn->state || !conn->state->crtc ||
  2971. conn->dpms != DRM_MODE_DPMS_ON ||
  2972. sde_encoder_in_clone_mode(conn->encoder))
  2973. continue;
  2974. lp = sde_connector_get_lp(conn);
  2975. if (lp == SDE_MODE_DPMS_LP1) {
  2976. /* transition LP1->LP2 on pm suspend */
  2977. ret = sde_connector_set_property_for_commit(conn, state,
  2978. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2979. if (ret) {
  2980. DRM_ERROR("failed to set lp2 for conn %d\n",
  2981. conn->base.id);
  2982. drm_connector_list_iter_end(&conn_iter);
  2983. goto unlock;
  2984. }
  2985. }
  2986. if (lp != SDE_MODE_DPMS_LP2) {
  2987. /* force CRTC to be inactive */
  2988. crtc_state = drm_atomic_get_crtc_state(state,
  2989. conn->state->crtc);
  2990. if (IS_ERR_OR_NULL(crtc_state)) {
  2991. DRM_ERROR("failed to get crtc %d state\n",
  2992. conn->state->crtc->base.id);
  2993. drm_connector_list_iter_end(&conn_iter);
  2994. goto unlock;
  2995. }
  2996. if (lp != SDE_MODE_DPMS_LP1)
  2997. crtc_state->active = false;
  2998. ++num_crtcs;
  2999. }
  3000. }
  3001. drm_connector_list_iter_end(&conn_iter);
  3002. /* check for nothing to do */
  3003. if (num_crtcs == 0) {
  3004. DRM_DEBUG("all crtcs are already in the off state\n");
  3005. sde_kms->suspend_block = true;
  3006. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3007. goto unlock;
  3008. }
  3009. /* commit the "disable all" state */
  3010. ret = drm_atomic_commit(state);
  3011. if (ret < 0) {
  3012. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3013. goto unlock;
  3014. }
  3015. sde_kms->suspend_block = true;
  3016. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3017. unlock:
  3018. if (state) {
  3019. drm_atomic_state_put(state);
  3020. state = NULL;
  3021. }
  3022. if (ret == -EDEADLK) {
  3023. drm_modeset_backoff(&ctx);
  3024. goto retry;
  3025. }
  3026. drm_modeset_drop_locks(&ctx);
  3027. drm_modeset_acquire_fini(&ctx);
  3028. /*
  3029. * pm runtime driver avoids multiple runtime_suspend API call by
  3030. * checking runtime_status. However, this call helps when there is a
  3031. * race condition between pm_suspend call and doze_suspend/power_off
  3032. * commit. It removes the extra vote from suspend and adds it back
  3033. * later to allow power collapse during pm_suspend call
  3034. */
  3035. pm_runtime_put_sync(dev);
  3036. pm_runtime_get_noresume(dev);
  3037. /* dump clock state before entering suspend */
  3038. if (sde_kms->pm_suspend_clk_dump)
  3039. _sde_kms_dump_clks_state(sde_kms);
  3040. return ret;
  3041. }
  3042. static int sde_kms_pm_resume(struct device *dev)
  3043. {
  3044. struct drm_device *ddev;
  3045. struct sde_kms *sde_kms;
  3046. struct drm_modeset_acquire_ctx ctx;
  3047. int ret, i;
  3048. if (!dev)
  3049. return -EINVAL;
  3050. ddev = dev_get_drvdata(dev);
  3051. if (!ddev || !ddev_to_msm_kms(ddev))
  3052. return -EINVAL;
  3053. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3054. SDE_EVT32(sde_kms->suspend_state != NULL);
  3055. drm_mode_config_reset(ddev);
  3056. drm_modeset_acquire_init(&ctx, 0);
  3057. retry:
  3058. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3059. if (ret == -EDEADLK) {
  3060. drm_modeset_backoff(&ctx);
  3061. goto retry;
  3062. } else if (WARN_ON(ret)) {
  3063. goto end;
  3064. }
  3065. sde_kms->suspend_block = false;
  3066. if (sde_kms->suspend_state) {
  3067. sde_kms->suspend_state->acquire_ctx = &ctx;
  3068. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3069. ret = drm_atomic_helper_commit_duplicated_state(
  3070. sde_kms->suspend_state, &ctx);
  3071. if (ret != -EDEADLK)
  3072. break;
  3073. drm_modeset_backoff(&ctx);
  3074. }
  3075. if (ret < 0)
  3076. DRM_ERROR("failed to restore state, %d\n", ret);
  3077. drm_atomic_state_put(sde_kms->suspend_state);
  3078. sde_kms->suspend_state = NULL;
  3079. }
  3080. end:
  3081. drm_modeset_drop_locks(&ctx);
  3082. drm_modeset_acquire_fini(&ctx);
  3083. /* enable hot-plug polling */
  3084. drm_kms_helper_poll_enable(ddev);
  3085. return 0;
  3086. }
  3087. static const struct msm_kms_funcs kms_funcs = {
  3088. .hw_init = sde_kms_hw_init,
  3089. .postinit = sde_kms_postinit,
  3090. .irq_preinstall = sde_irq_preinstall,
  3091. .irq_postinstall = sde_irq_postinstall,
  3092. .irq_uninstall = sde_irq_uninstall,
  3093. .irq = sde_irq,
  3094. .lastclose = sde_kms_lastclose,
  3095. .prepare_fence = sde_kms_prepare_fence,
  3096. .prepare_commit = sde_kms_prepare_commit,
  3097. .commit = sde_kms_commit,
  3098. .complete_commit = sde_kms_complete_commit,
  3099. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3100. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3101. .enable_vblank = sde_kms_enable_vblank,
  3102. .disable_vblank = sde_kms_disable_vblank,
  3103. .check_modified_format = sde_format_check_modified_format,
  3104. .atomic_check = sde_kms_atomic_check,
  3105. .get_format = sde_get_msm_format,
  3106. .round_pixclk = sde_kms_round_pixclk,
  3107. .display_early_wakeup = sde_kms_display_early_wakeup,
  3108. .pm_suspend = sde_kms_pm_suspend,
  3109. .pm_resume = sde_kms_pm_resume,
  3110. .destroy = sde_kms_destroy,
  3111. .debugfs_destroy = sde_kms_debugfs_destroy,
  3112. .cont_splash_config = sde_kms_cont_splash_config,
  3113. .register_events = _sde_kms_register_events,
  3114. .get_address_space = _sde_kms_get_address_space,
  3115. .get_address_space_device = _sde_kms_get_address_space_device,
  3116. .postopen = _sde_kms_post_open,
  3117. .check_for_splash = sde_kms_check_for_splash,
  3118. .get_mixer_count = sde_kms_get_mixer_count,
  3119. .get_dsc_count = sde_kms_get_dsc_count,
  3120. };
  3121. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3122. {
  3123. int i;
  3124. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3125. if (!sde_kms->aspace[i])
  3126. continue;
  3127. msm_gem_address_space_put(sde_kms->aspace[i]);
  3128. sde_kms->aspace[i] = NULL;
  3129. }
  3130. return 0;
  3131. }
  3132. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3133. {
  3134. struct msm_mmu *mmu;
  3135. int i, ret;
  3136. int early_map = 0;
  3137. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3138. return -EINVAL;
  3139. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3140. struct msm_gem_address_space *aspace;
  3141. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3142. if (IS_ERR(mmu)) {
  3143. ret = PTR_ERR(mmu);
  3144. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3145. i, ret);
  3146. continue;
  3147. }
  3148. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3149. mmu, "sde");
  3150. if (IS_ERR(aspace)) {
  3151. ret = PTR_ERR(aspace);
  3152. mmu->funcs->destroy(mmu);
  3153. goto fail;
  3154. }
  3155. sde_kms->aspace[i] = aspace;
  3156. aspace->domain_attached = true;
  3157. /* Mapping splash memory block */
  3158. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3159. sde_kms->splash_data.num_splash_regions) {
  3160. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3161. if (ret) {
  3162. SDE_ERROR("failed to map ret:%d\n", ret);
  3163. goto fail;
  3164. }
  3165. }
  3166. /*
  3167. * disable early-map which would have been enabled during
  3168. * bootup by smmu through the device-tree hint for cont-spash
  3169. */
  3170. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3171. &early_map);
  3172. if (ret) {
  3173. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3174. ret, early_map);
  3175. goto early_map_fail;
  3176. }
  3177. }
  3178. sde_kms->base.aspace = sde_kms->aspace[0];
  3179. return 0;
  3180. early_map_fail:
  3181. _sde_kms_unmap_all_splash_regions(sde_kms);
  3182. fail:
  3183. _sde_kms_mmu_destroy(sde_kms);
  3184. return ret;
  3185. }
  3186. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3187. {
  3188. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3189. return;
  3190. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3191. }
  3192. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3193. {
  3194. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3195. return;
  3196. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3197. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3198. sde_kms->catalog);
  3199. }
  3200. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3201. {
  3202. struct sde_vbif_set_qos_params qos_params;
  3203. struct sde_mdss_cfg *catalog;
  3204. if (!sde_kms->catalog)
  3205. return;
  3206. catalog = sde_kms->catalog;
  3207. memset(&qos_params, 0, sizeof(qos_params));
  3208. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3209. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3210. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3211. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3212. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3213. }
  3214. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3215. {
  3216. struct sde_hw_uidle *uidle;
  3217. if (!sde_kms) {
  3218. SDE_ERROR("invalid kms\n");
  3219. return -EINVAL;
  3220. }
  3221. uidle = sde_kms->hw_uidle;
  3222. if (uidle && uidle->ops.active_override_enable)
  3223. uidle->ops.active_override_enable(uidle, enable);
  3224. return 0;
  3225. }
  3226. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3227. {
  3228. struct device *cpu_dev;
  3229. int cpu = 0;
  3230. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3231. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3232. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3233. return;
  3234. }
  3235. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3236. cpu_dev = get_cpu_device(cpu);
  3237. if (!cpu_dev) {
  3238. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3239. cpu);
  3240. continue;
  3241. }
  3242. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3243. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3244. cpu_irq_latency);
  3245. else
  3246. dev_pm_qos_add_request(cpu_dev,
  3247. &sde_kms->pm_qos_irq_req[cpu],
  3248. DEV_PM_QOS_RESUME_LATENCY,
  3249. cpu_irq_latency);
  3250. }
  3251. }
  3252. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3253. {
  3254. struct device *cpu_dev;
  3255. int cpu = 0;
  3256. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3257. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3258. return;
  3259. }
  3260. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3261. cpu_dev = get_cpu_device(cpu);
  3262. if (!cpu_dev) {
  3263. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3264. cpu);
  3265. continue;
  3266. }
  3267. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3268. dev_pm_qos_remove_request(
  3269. &sde_kms->pm_qos_irq_req[cpu]);
  3270. }
  3271. }
  3272. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3273. {
  3274. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3275. mutex_lock(&priv->phandle.phandle_lock);
  3276. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3277. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3278. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3279. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3280. mutex_unlock(&priv->phandle.phandle_lock);
  3281. }
  3282. static void sde_kms_irq_affinity_notify(
  3283. struct irq_affinity_notify *affinity_notify,
  3284. const cpumask_t *mask)
  3285. {
  3286. struct msm_drm_private *priv;
  3287. struct sde_kms *sde_kms = container_of(affinity_notify,
  3288. struct sde_kms, affinity_notify);
  3289. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3290. return;
  3291. priv = sde_kms->dev->dev_private;
  3292. mutex_lock(&priv->phandle.phandle_lock);
  3293. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3294. // save irq cpu mask
  3295. sde_kms->irq_cpu_mask = *mask;
  3296. // request vote with updated irq cpu mask
  3297. if (atomic_read(&sde_kms->irq_vote_count))
  3298. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3299. mutex_unlock(&priv->phandle.phandle_lock);
  3300. }
  3301. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3302. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3303. {
  3304. struct sde_kms *sde_kms = usr;
  3305. struct msm_kms *msm_kms;
  3306. msm_kms = &sde_kms->base;
  3307. if (!sde_kms)
  3308. return;
  3309. SDE_DEBUG("event_type:%d\n", event_type);
  3310. SDE_EVT32_VERBOSE(event_type);
  3311. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3312. sde_irq_update(msm_kms, true);
  3313. sde_kms->first_kickoff = true;
  3314. /**
  3315. * Rotator sid needs to be programmed since uefi doesn't
  3316. * configure it during continuous splash
  3317. */
  3318. sde_kms_init_rot_sid_hw(sde_kms);
  3319. if (sde_kms->splash_data.num_splash_displays ||
  3320. sde_in_trusted_vm(sde_kms))
  3321. return;
  3322. sde_vbif_init_memtypes(sde_kms);
  3323. sde_kms_init_shared_hw(sde_kms);
  3324. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3325. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3326. sde_irq_update(msm_kms, false);
  3327. sde_kms->first_kickoff = false;
  3328. if (sde_in_trusted_vm(sde_kms))
  3329. return;
  3330. _sde_kms_active_override(sde_kms, true);
  3331. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3332. sde_vbif_axi_halt_request(sde_kms);
  3333. }
  3334. }
  3335. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3336. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3337. {
  3338. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3339. int rc = -EINVAL;
  3340. SDE_DEBUG("\n");
  3341. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3342. if (rc > 0)
  3343. rc = 0;
  3344. SDE_EVT32(rc, genpd->device_count);
  3345. return rc;
  3346. }
  3347. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3348. {
  3349. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3350. SDE_DEBUG("\n");
  3351. pm_runtime_put_sync(sde_kms->dev->dev);
  3352. SDE_EVT32(genpd->device_count);
  3353. return 0;
  3354. }
  3355. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3356. struct sde_splash_data *data)
  3357. {
  3358. int i = 0;
  3359. int ret = 0;
  3360. struct device_node *parent, *node, *node1;
  3361. struct resource r, r1;
  3362. const char *node_name = "splash_region";
  3363. struct sde_splash_mem *mem;
  3364. bool share_splash_mem = false;
  3365. int num_displays, num_regions;
  3366. struct sde_splash_display *splash_display;
  3367. if (!data)
  3368. return -EINVAL;
  3369. memset(data, 0, sizeof(*data));
  3370. parent = of_find_node_by_path("/reserved-memory");
  3371. if (!parent) {
  3372. SDE_ERROR("failed to find reserved-memory node\n");
  3373. return -EINVAL;
  3374. }
  3375. node = of_find_node_by_name(parent, node_name);
  3376. if (!node) {
  3377. SDE_DEBUG("failed to find node %s\n", node_name);
  3378. return -EINVAL;
  3379. }
  3380. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3381. if (!node1)
  3382. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3383. /**
  3384. * Support sharing a single splash memory for all the built in displays
  3385. * and also independent splash region per displays. Incase of
  3386. * independent splash region for each connected display, dtsi node of
  3387. * cont_splash_region should be collection of all memory regions
  3388. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3389. */
  3390. num_displays = dsi_display_get_num_of_displays();
  3391. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3392. data->num_splash_displays = num_displays;
  3393. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3394. if (num_displays > num_regions) {
  3395. share_splash_mem = true;
  3396. pr_info(":%d displays share same splash buf\n", num_displays);
  3397. }
  3398. for (i = 0; i < num_displays; i++) {
  3399. splash_display = &data->splash_display[i];
  3400. if (!i || !share_splash_mem) {
  3401. if (of_address_to_resource(node, i, &r)) {
  3402. SDE_ERROR("invalid data for:%s\n", node_name);
  3403. return -EINVAL;
  3404. }
  3405. mem = &data->splash_mem[i];
  3406. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3407. SDE_DEBUG("failed to find ramdump memory\n");
  3408. mem->ramdump_base = 0;
  3409. mem->ramdump_size = 0;
  3410. } else {
  3411. mem->ramdump_base = (unsigned long)r1.start;
  3412. mem->ramdump_size = (r1.end - r1.start) + 1;
  3413. }
  3414. mem->splash_buf_base = (unsigned long)r.start;
  3415. mem->splash_buf_size = (r.end - r.start) + 1;
  3416. mem->ref_cnt = 0;
  3417. splash_display->splash = mem;
  3418. data->num_splash_regions++;
  3419. } else {
  3420. data->splash_display[i].splash = &data->splash_mem[0];
  3421. }
  3422. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3423. splash_display->splash->splash_buf_base,
  3424. splash_display->splash->splash_buf_size);
  3425. }
  3426. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3427. return ret;
  3428. }
  3429. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3430. struct platform_device *platformdev)
  3431. {
  3432. int rc = -EINVAL;
  3433. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3434. if (IS_ERR(sde_kms->mmio)) {
  3435. rc = PTR_ERR(sde_kms->mmio);
  3436. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3437. sde_kms->mmio = NULL;
  3438. goto error;
  3439. }
  3440. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3441. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3442. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3443. sde_kms->mmio_len);
  3444. if (rc)
  3445. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3446. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3447. "vbif_phys");
  3448. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3449. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3450. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3451. sde_kms->vbif[VBIF_RT] = NULL;
  3452. goto error;
  3453. }
  3454. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3455. "vbif_phys");
  3456. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3457. sde_kms->vbif_len[VBIF_RT]);
  3458. if (rc)
  3459. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3460. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3461. "vbif_nrt_phys");
  3462. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3463. sde_kms->vbif[VBIF_NRT] = NULL;
  3464. SDE_DEBUG("VBIF NRT is not defined");
  3465. } else {
  3466. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3467. "vbif_nrt_phys");
  3468. rc = sde_dbg_reg_register_base("vbif_nrt",
  3469. sde_kms->vbif[VBIF_NRT],
  3470. sde_kms->vbif_len[VBIF_NRT]);
  3471. if (rc)
  3472. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3473. rc);
  3474. }
  3475. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3476. "regdma_phys");
  3477. if (IS_ERR(sde_kms->reg_dma)) {
  3478. sde_kms->reg_dma = NULL;
  3479. SDE_DEBUG("REG_DMA is not defined");
  3480. } else {
  3481. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3482. "regdma_phys");
  3483. rc = sde_dbg_reg_register_base("reg_dma",
  3484. sde_kms->reg_dma,
  3485. sde_kms->reg_dma_len);
  3486. if (rc)
  3487. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3488. rc);
  3489. }
  3490. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3491. "sid_phys");
  3492. if (IS_ERR(sde_kms->sid)) {
  3493. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3494. sde_kms->sid = NULL;
  3495. } else {
  3496. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3497. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3498. sde_kms->sid_len);
  3499. if (rc)
  3500. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3501. }
  3502. error:
  3503. return rc;
  3504. }
  3505. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3506. struct sde_kms *sde_kms)
  3507. {
  3508. int rc = 0;
  3509. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3510. sde_kms->genpd.name = dev->unique;
  3511. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3512. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3513. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3514. if (rc < 0) {
  3515. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3516. sde_kms->genpd.name, rc);
  3517. return rc;
  3518. }
  3519. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3520. &sde_kms->genpd);
  3521. if (rc < 0) {
  3522. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3523. sde_kms->genpd.name, rc);
  3524. pm_genpd_remove(&sde_kms->genpd);
  3525. return rc;
  3526. }
  3527. sde_kms->genpd_init = true;
  3528. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3529. }
  3530. return rc;
  3531. }
  3532. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3533. struct drm_device *dev,
  3534. struct msm_drm_private *priv)
  3535. {
  3536. struct sde_rm *rm = NULL;
  3537. int i, rc = -EINVAL;
  3538. sde_kms->catalog = sde_hw_catalog_init(dev);
  3539. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3540. rc = PTR_ERR(sde_kms->catalog);
  3541. if (!sde_kms->catalog)
  3542. rc = -EINVAL;
  3543. SDE_ERROR("catalog init failed: %d\n", rc);
  3544. sde_kms->catalog = NULL;
  3545. goto power_error;
  3546. }
  3547. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3548. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3549. /* initialize power domain if defined */
  3550. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3551. if (rc) {
  3552. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3553. goto genpd_err;
  3554. }
  3555. rc = _sde_kms_mmu_init(sde_kms);
  3556. if (rc) {
  3557. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3558. goto power_error;
  3559. }
  3560. /* Initialize reg dma block which is a singleton */
  3561. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3562. sde_kms->dev);
  3563. if (rc) {
  3564. SDE_ERROR("failed: reg dma init failed\n");
  3565. goto power_error;
  3566. }
  3567. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3568. rm = &sde_kms->rm;
  3569. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3570. sde_kms->dev);
  3571. if (rc) {
  3572. SDE_ERROR("rm init failed: %d\n", rc);
  3573. goto power_error;
  3574. }
  3575. sde_kms->rm_init = true;
  3576. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3577. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3578. rc = PTR_ERR(sde_kms->hw_intr);
  3579. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3580. sde_kms->hw_intr = NULL;
  3581. goto hw_intr_init_err;
  3582. }
  3583. /*
  3584. * Attempt continuous splash handoff only if reserved
  3585. * splash memory is found & release resources on any error
  3586. * in finding display hw config in splash
  3587. */
  3588. if (sde_kms->splash_data.num_splash_regions) {
  3589. struct sde_splash_display *display;
  3590. int ret, display_count =
  3591. sde_kms->splash_data.num_splash_displays;
  3592. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3593. &sde_kms->splash_data, sde_kms->catalog);
  3594. for (i = 0; i < display_count; i++) {
  3595. display = &sde_kms->splash_data.splash_display[i];
  3596. /*
  3597. * free splash region on resource init failure and
  3598. * cont-splash disabled case
  3599. */
  3600. if (!display->cont_splash_enabled || ret)
  3601. _sde_kms_free_splash_display_data(
  3602. sde_kms, display);
  3603. }
  3604. }
  3605. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3606. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3607. rc = PTR_ERR(sde_kms->hw_mdp);
  3608. if (!sde_kms->hw_mdp)
  3609. rc = -EINVAL;
  3610. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3611. sde_kms->hw_mdp = NULL;
  3612. goto power_error;
  3613. }
  3614. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3615. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3616. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3617. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3618. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3619. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3620. if (!sde_kms->hw_vbif[vbif_idx])
  3621. rc = -EINVAL;
  3622. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3623. sde_kms->hw_vbif[vbif_idx] = NULL;
  3624. goto power_error;
  3625. }
  3626. }
  3627. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3628. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3629. sde_kms->mmio_len, sde_kms->catalog);
  3630. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3631. rc = PTR_ERR(sde_kms->hw_uidle);
  3632. if (!sde_kms->hw_uidle)
  3633. rc = -EINVAL;
  3634. /* uidle is optional, so do not make it a fatal error */
  3635. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3636. sde_kms->hw_uidle = NULL;
  3637. rc = 0;
  3638. }
  3639. } else {
  3640. sde_kms->hw_uidle = NULL;
  3641. }
  3642. if (sde_kms->sid) {
  3643. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3644. sde_kms->sid_len, sde_kms->catalog);
  3645. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3646. rc = PTR_ERR(sde_kms->hw_sid);
  3647. SDE_ERROR("failed to init sid %ld\n", rc);
  3648. sde_kms->hw_sid = NULL;
  3649. goto power_error;
  3650. }
  3651. }
  3652. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3653. &priv->phandle, "core_clk");
  3654. if (rc) {
  3655. SDE_ERROR("failed to init perf %d\n", rc);
  3656. goto perf_err;
  3657. }
  3658. /*
  3659. * _sde_kms_drm_obj_init should create the DRM related objects
  3660. * i.e. CRTCs, planes, encoders, connectors and so forth
  3661. */
  3662. rc = _sde_kms_drm_obj_init(sde_kms);
  3663. if (rc) {
  3664. SDE_ERROR("modeset init failed: %d\n", rc);
  3665. goto drm_obj_init_err;
  3666. }
  3667. return 0;
  3668. genpd_err:
  3669. drm_obj_init_err:
  3670. sde_core_perf_destroy(&sde_kms->perf);
  3671. hw_intr_init_err:
  3672. perf_err:
  3673. power_error:
  3674. return rc;
  3675. }
  3676. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3677. {
  3678. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3679. int rc = 0;
  3680. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3681. if (rc) {
  3682. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3683. return rc;
  3684. }
  3685. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3686. if (rc) {
  3687. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3688. return rc;
  3689. }
  3690. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3691. if (rc) {
  3692. SDE_ERROR("failed to get io irq for KMS");
  3693. return rc;
  3694. }
  3695. return rc;
  3696. }
  3697. static int sde_kms_hw_init(struct msm_kms *kms)
  3698. {
  3699. struct sde_kms *sde_kms;
  3700. struct drm_device *dev;
  3701. struct msm_drm_private *priv;
  3702. struct platform_device *platformdev;
  3703. int i, irq_num, rc = -EINVAL;
  3704. if (!kms) {
  3705. SDE_ERROR("invalid kms\n");
  3706. goto end;
  3707. }
  3708. sde_kms = to_sde_kms(kms);
  3709. dev = sde_kms->dev;
  3710. if (!dev || !dev->dev) {
  3711. SDE_ERROR("invalid device\n");
  3712. goto end;
  3713. }
  3714. platformdev = to_platform_device(dev->dev);
  3715. priv = dev->dev_private;
  3716. if (!priv) {
  3717. SDE_ERROR("invalid private data\n");
  3718. goto end;
  3719. }
  3720. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3721. if (rc)
  3722. goto error;
  3723. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3724. if (rc)
  3725. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3726. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3727. if (rc)
  3728. goto error;
  3729. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3730. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3731. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3732. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3733. mutex_init(&sde_kms->secure_transition_lock);
  3734. atomic_set(&sde_kms->detach_sec_cb, 0);
  3735. atomic_set(&sde_kms->detach_all_cb, 0);
  3736. atomic_set(&sde_kms->irq_vote_count, 0);
  3737. /*
  3738. * Support format modifiers for compression etc.
  3739. */
  3740. dev->mode_config.allow_fb_modifiers = true;
  3741. /*
  3742. * Handle (re)initializations during power enable
  3743. */
  3744. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3745. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3746. SDE_POWER_EVENT_POST_ENABLE |
  3747. SDE_POWER_EVENT_PRE_DISABLE,
  3748. sde_kms_handle_power_event, sde_kms, "kms");
  3749. if (sde_kms->splash_data.num_splash_displays) {
  3750. SDE_DEBUG("Skipping MDP Resources disable\n");
  3751. } else {
  3752. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3753. sde_power_data_bus_set_quota(&priv->phandle, i,
  3754. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3755. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3756. pm_runtime_put_sync(sde_kms->dev->dev);
  3757. }
  3758. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3759. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3760. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3761. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3762. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3763. if (sde_in_trusted_vm(sde_kms))
  3764. rc = sde_vm_trusted_init(sde_kms);
  3765. else
  3766. rc = sde_vm_primary_init(sde_kms);
  3767. if (rc) {
  3768. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3769. goto error;
  3770. }
  3771. return 0;
  3772. error:
  3773. _sde_kms_hw_destroy(sde_kms, platformdev);
  3774. end:
  3775. return rc;
  3776. }
  3777. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3778. {
  3779. struct msm_drm_private *priv;
  3780. struct sde_kms *sde_kms;
  3781. if (!dev || !dev->dev_private) {
  3782. SDE_ERROR("drm device node invalid\n");
  3783. return ERR_PTR(-EINVAL);
  3784. }
  3785. priv = dev->dev_private;
  3786. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3787. if (!sde_kms) {
  3788. SDE_ERROR("failed to allocate sde kms\n");
  3789. return ERR_PTR(-ENOMEM);
  3790. }
  3791. msm_kms_init(&sde_kms->base, &kms_funcs);
  3792. sde_kms->dev = dev;
  3793. return &sde_kms->base;
  3794. }
  3795. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3796. {
  3797. struct dsi_display *display;
  3798. struct sde_splash_display *handoff_display;
  3799. int i;
  3800. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3801. handoff_display = &sde_kms->splash_data.splash_display[i];
  3802. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3803. if (handoff_display->cont_splash_enabled)
  3804. _sde_kms_free_splash_display_data(sde_kms,
  3805. handoff_display);
  3806. dsi_display_set_active_state(display, false);
  3807. }
  3808. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3809. }
  3810. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  3811. struct drm_atomic_state *state)
  3812. {
  3813. struct drm_device *dev;
  3814. struct msm_drm_private *priv;
  3815. struct sde_splash_display *handoff_display;
  3816. struct dsi_display *display;
  3817. int ret, i;
  3818. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3819. SDE_ERROR("invalid params\n");
  3820. return -EINVAL;
  3821. }
  3822. dev = sde_kms->dev;
  3823. priv = dev->dev_private;
  3824. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3825. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3826. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3827. &sde_kms->splash_data, sde_kms->catalog);
  3828. if (ret) {
  3829. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  3830. return -EINVAL;
  3831. }
  3832. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3833. handoff_display = &sde_kms->splash_data.splash_display[i];
  3834. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3835. if (!handoff_display->cont_splash_enabled || ret)
  3836. _sde_kms_free_splash_display_data(sde_kms,
  3837. handoff_display);
  3838. else
  3839. dsi_display_set_active_state(display, true);
  3840. }
  3841. if (sde_kms->splash_data.num_splash_displays != 1) {
  3842. SDE_ERROR("no. of displays not supported:%d\n",
  3843. sde_kms->splash_data.num_splash_displays);
  3844. goto error;
  3845. }
  3846. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  3847. if (ret) {
  3848. SDE_ERROR("error in setting handoff configs\n");
  3849. goto error;
  3850. }
  3851. /**
  3852. * fill-in vote for the continuous splash hanodff path, which will be
  3853. * removed on the successful first commit.
  3854. */
  3855. pm_runtime_get_sync(sde_kms->dev->dev);
  3856. return 0;
  3857. error:
  3858. return ret;
  3859. }
  3860. static int _sde_kms_register_events(struct msm_kms *kms,
  3861. struct drm_mode_object *obj, u32 event, bool en)
  3862. {
  3863. int ret = 0;
  3864. struct drm_crtc *crtc = NULL;
  3865. struct drm_connector *conn = NULL;
  3866. struct sde_kms *sde_kms = NULL;
  3867. struct sde_vm_ops *vm_ops;
  3868. if (!kms || !obj) {
  3869. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3870. return -EINVAL;
  3871. }
  3872. sde_kms = to_sde_kms(kms);
  3873. /* check vm ownership, if event registration requires HW access */
  3874. switch (obj->type) {
  3875. case DRM_MODE_OBJECT_CRTC:
  3876. vm_ops = sde_vm_get_ops(sde_kms);
  3877. sde_vm_lock(sde_kms);
  3878. if (vm_ops && vm_ops->vm_owns_hw
  3879. && !vm_ops->vm_owns_hw(sde_kms)) {
  3880. sde_vm_unlock(sde_kms);
  3881. SDE_DEBUG("HW is owned by other VM\n");
  3882. return -EACCES;
  3883. }
  3884. crtc = obj_to_crtc(obj);
  3885. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3886. sde_vm_unlock(sde_kms);
  3887. break;
  3888. case DRM_MODE_OBJECT_CONNECTOR:
  3889. conn = obj_to_connector(obj);
  3890. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3891. en);
  3892. break;
  3893. }
  3894. return ret;
  3895. }
  3896. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3897. {
  3898. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3899. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3900. }