sde_encoder_phys_vid.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include "sde_encoder_phys.h"
  7. #include "sde_hw_interrupts.h"
  8. #include "sde_core_irq.h"
  9. #include "sde_formats.h"
  10. #include "dsi_display.h"
  11. #include "sde_trace.h"
  12. #define SDE_DEBUG_VIDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
  13. (e) && (e)->base.parent ? \
  14. (e)->base.parent->base.id : -1, \
  15. (e) && (e)->base.hw_intf ? \
  16. (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  17. #define SDE_ERROR_VIDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
  18. (e) && (e)->base.parent ? \
  19. (e)->base.parent->base.id : -1, \
  20. (e) && (e)->base.hw_intf ? \
  21. (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  22. #define to_sde_encoder_phys_vid(x) \
  23. container_of(x, struct sde_encoder_phys_vid, base)
  24. /* Poll time to do recovery during active region */
  25. #define POLL_TIME_USEC_FOR_LN_CNT 500
  26. #define MAX_POLL_CNT 10
  27. static bool sde_encoder_phys_vid_is_master(
  28. struct sde_encoder_phys *phys_enc)
  29. {
  30. bool ret = false;
  31. if (phys_enc->split_role != ENC_ROLE_SLAVE)
  32. ret = true;
  33. return ret;
  34. }
  35. static void drm_mode_to_intf_timing_params(
  36. const struct sde_encoder_phys_vid *vid_enc,
  37. const struct drm_display_mode *mode,
  38. struct intf_timing_params *timing)
  39. {
  40. const struct sde_encoder_phys *phys_enc = &vid_enc->base;
  41. memset(timing, 0, sizeof(*timing));
  42. if ((mode->htotal < mode->hsync_end)
  43. || (mode->hsync_start < mode->hdisplay)
  44. || (mode->vtotal < mode->vsync_end)
  45. || (mode->vsync_start < mode->vdisplay)
  46. || (mode->hsync_end < mode->hsync_start)
  47. || (mode->vsync_end < mode->vsync_start)) {
  48. SDE_ERROR(
  49. "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
  50. mode->hsync_start, mode->hsync_end,
  51. mode->htotal, mode->hdisplay);
  52. SDE_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
  53. mode->vsync_start, mode->vsync_end,
  54. mode->vtotal, mode->vdisplay);
  55. return;
  56. }
  57. /*
  58. * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
  59. * Active Region Front Porch Sync Back Porch
  60. * <-----------------><------------><-----><----------->
  61. * <- [hv]display --->
  62. * <--------- [hv]sync_start ------>
  63. * <----------------- [hv]sync_end ------->
  64. * <---------------------------- [hv]total ------------->
  65. */
  66. timing->poms_align_vsync = phys_enc->poms_align_vsync;
  67. timing->width = mode->hdisplay; /* active width */
  68. timing->height = mode->vdisplay; /* active height */
  69. timing->xres = timing->width;
  70. timing->yres = timing->height;
  71. timing->h_back_porch = mode->htotal - mode->hsync_end;
  72. timing->h_front_porch = mode->hsync_start - mode->hdisplay;
  73. timing->v_back_porch = mode->vtotal - mode->vsync_end;
  74. timing->v_front_porch = mode->vsync_start - mode->vdisplay;
  75. timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
  76. timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
  77. timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
  78. timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
  79. timing->border_clr = 0;
  80. timing->underflow_clr = 0xff;
  81. timing->hsync_skew = mode->hskew;
  82. timing->v_front_porch_fixed = vid_enc->base.vfp_cached;
  83. timing->vrefresh = mode->vrefresh;
  84. if (vid_enc->base.comp_type != MSM_DISPLAY_COMPRESSION_NONE) {
  85. timing->compression_en = true;
  86. timing->dce_bytes_per_line = vid_enc->base.dce_bytes_per_line;
  87. }
  88. /* DSI controller cannot handle active-low sync signals. */
  89. if (phys_enc->hw_intf->cap->type == INTF_DSI) {
  90. timing->hsync_polarity = 0;
  91. timing->vsync_polarity = 0;
  92. }
  93. /* for DP/EDP, Shift timings to align it to bottom right */
  94. if ((phys_enc->hw_intf->cap->type == INTF_DP) ||
  95. (phys_enc->hw_intf->cap->type == INTF_EDP)) {
  96. timing->h_back_porch += timing->h_front_porch;
  97. timing->h_front_porch = 0;
  98. timing->v_back_porch += timing->v_front_porch;
  99. timing->v_front_porch = 0;
  100. }
  101. timing->wide_bus_en = sde_encoder_is_widebus_enabled(phys_enc->parent);
  102. /*
  103. * for DP, divide the horizonal parameters by 2 when
  104. * widebus or compression is enabled, irrespective of
  105. * compression ratio
  106. */
  107. if (phys_enc->hw_intf->cap->type == INTF_DP &&
  108. (timing->wide_bus_en ||
  109. (vid_enc->base.comp_ratio > 1))) {
  110. timing->width = timing->width >> 1;
  111. timing->xres = timing->xres >> 1;
  112. timing->h_back_porch = timing->h_back_porch >> 1;
  113. timing->h_front_porch = timing->h_front_porch >> 1;
  114. timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
  115. if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  116. (vid_enc->base.comp_ratio > 1)) {
  117. timing->extra_dto_cycles =
  118. vid_enc->base.dsc_extra_pclk_cycle_cnt;
  119. timing->width += vid_enc->base.dsc_extra_disp_width;
  120. timing->h_back_porch +=
  121. vid_enc->base.dsc_extra_disp_width;
  122. }
  123. }
  124. /*
  125. * for DSI, if compression is enabled, then divide the horizonal active
  126. * timing parameters by compression ratio.
  127. */
  128. if ((phys_enc->hw_intf->cap->type != INTF_DP) &&
  129. ((vid_enc->base.comp_type ==
  130. MSM_DISPLAY_COMPRESSION_DSC) ||
  131. (vid_enc->base.comp_type ==
  132. MSM_DISPLAY_COMPRESSION_VDC))) {
  133. // adjust active dimensions
  134. timing->width = DIV_ROUND_UP(timing->width,
  135. vid_enc->base.comp_ratio);
  136. timing->xres = DIV_ROUND_UP(timing->xres,
  137. vid_enc->base.comp_ratio);
  138. }
  139. /*
  140. * For edp only:
  141. * DISPLAY_V_START = (VBP * HCYCLE) + HBP
  142. * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
  143. */
  144. /*
  145. * if (vid_enc->hw->cap->type == INTF_EDP) {
  146. * display_v_start += mode->htotal - mode->hsync_start;
  147. * display_v_end -= mode->hsync_start - mode->hdisplay;
  148. * }
  149. */
  150. }
  151. static inline u32 get_horizontal_total(const struct intf_timing_params *timing)
  152. {
  153. u32 active = timing->xres;
  154. u32 inactive =
  155. timing->h_back_porch + timing->h_front_porch +
  156. timing->hsync_pulse_width;
  157. return active + inactive;
  158. }
  159. static inline u32 get_vertical_total(const struct intf_timing_params *timing)
  160. {
  161. u32 active = timing->yres;
  162. u32 inactive = timing->v_back_porch + timing->v_front_porch +
  163. timing->vsync_pulse_width;
  164. return active + inactive;
  165. }
  166. /*
  167. * programmable_fetch_get_num_lines:
  168. * Number of fetch lines in vertical front porch
  169. * @timing: Pointer to the intf timing information for the requested mode
  170. *
  171. * Returns the number of fetch lines in vertical front porch at which mdp
  172. * can start fetching the next frame.
  173. *
  174. * Number of needed prefetch lines is anything that cannot be absorbed in the
  175. * start of frame time (back porch + vsync pulse width).
  176. *
  177. * Some panels have very large VFP, however we only need a total number of
  178. * lines based on the chip worst case latencies.
  179. */
  180. static u32 programmable_fetch_get_num_lines(
  181. struct sde_encoder_phys_vid *vid_enc,
  182. const struct intf_timing_params *timing)
  183. {
  184. struct sde_encoder_phys *phys_enc = &vid_enc->base;
  185. u32 needed_prefill_lines, needed_vfp_lines, actual_vfp_lines;
  186. const u32 fixed_prefill_fps = DEFAULT_FPS;
  187. u32 default_prefill_lines =
  188. phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
  189. u32 start_of_frame_lines =
  190. timing->v_back_porch + timing->vsync_pulse_width;
  191. u32 v_front_porch = timing->v_front_porch;
  192. /* minimum prefill lines are defined based on 60fps */
  193. needed_prefill_lines = (timing->vrefresh > fixed_prefill_fps) ?
  194. ((default_prefill_lines * timing->vrefresh) /
  195. fixed_prefill_fps) : default_prefill_lines;
  196. needed_vfp_lines = needed_prefill_lines - start_of_frame_lines;
  197. /* Fetch must be outside active lines, otherwise undefined. */
  198. if (start_of_frame_lines >= needed_prefill_lines) {
  199. SDE_DEBUG_VIDENC(vid_enc,
  200. "prog fetch is not needed, large vbp+vsw\n");
  201. actual_vfp_lines = 0;
  202. } else if (v_front_porch < needed_vfp_lines) {
  203. /* Warn fetch needed, but not enough porch in panel config */
  204. pr_warn_once
  205. ("low vbp+vfp may lead to perf issues in some cases\n");
  206. SDE_DEBUG_VIDENC(vid_enc,
  207. "less vfp than fetch req, using entire vfp\n");
  208. actual_vfp_lines = v_front_porch;
  209. } else {
  210. SDE_DEBUG_VIDENC(vid_enc, "room in vfp for needed prefetch\n");
  211. actual_vfp_lines = needed_vfp_lines;
  212. }
  213. SDE_DEBUG_VIDENC(vid_enc,
  214. "vrefresh:%u v_front_porch:%u v_back_porch:%u vsync_pulse_width:%u\n",
  215. timing->vrefresh, v_front_porch, timing->v_back_porch,
  216. timing->vsync_pulse_width);
  217. SDE_DEBUG_VIDENC(vid_enc,
  218. "prefill_lines:%u needed_vfp_lines:%u actual_vfp_lines:%u\n",
  219. needed_prefill_lines, needed_vfp_lines, actual_vfp_lines);
  220. return actual_vfp_lines;
  221. }
  222. /*
  223. * programmable_fetch_config: Programs HW to prefetch lines by offsetting
  224. * the start of fetch into the vertical front porch for cases where the
  225. * vsync pulse width and vertical back porch time is insufficient
  226. *
  227. * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
  228. * HW layer requires VSYNC counter of first pixel of tgt VFP line.
  229. *
  230. * @timing: Pointer to the intf timing information for the requested mode
  231. */
  232. static void programmable_fetch_config(struct sde_encoder_phys *phys_enc,
  233. const struct intf_timing_params *timing)
  234. {
  235. struct sde_encoder_phys_vid *vid_enc =
  236. to_sde_encoder_phys_vid(phys_enc);
  237. struct intf_prog_fetch f = { 0 };
  238. u32 vfp_fetch_lines = 0;
  239. u32 horiz_total = 0;
  240. u32 vert_total = 0;
  241. u32 vfp_fetch_start_vsync_counter = 0;
  242. unsigned long lock_flags;
  243. struct sde_mdss_cfg *m;
  244. if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
  245. return;
  246. m = phys_enc->sde_kms->catalog;
  247. vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing);
  248. if (vfp_fetch_lines) {
  249. vert_total = get_vertical_total(timing);
  250. horiz_total = get_horizontal_total(timing);
  251. vfp_fetch_start_vsync_counter =
  252. (vert_total - vfp_fetch_lines) * horiz_total + 1;
  253. /**
  254. * Check if we need to throttle the fetch to start
  255. * from second line after the active region.
  256. */
  257. if (m->delay_prg_fetch_start)
  258. vfp_fetch_start_vsync_counter += horiz_total;
  259. f.enable = 1;
  260. f.fetch_start = vfp_fetch_start_vsync_counter;
  261. }
  262. SDE_DEBUG_VIDENC(vid_enc,
  263. "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
  264. vfp_fetch_lines, vfp_fetch_start_vsync_counter);
  265. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  266. phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
  267. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  268. }
  269. static bool sde_encoder_phys_vid_mode_fixup(
  270. struct sde_encoder_phys *phys_enc,
  271. const struct drm_display_mode *mode,
  272. struct drm_display_mode *adj_mode)
  273. {
  274. if (phys_enc)
  275. SDE_DEBUG_VIDENC(to_sde_encoder_phys_vid(phys_enc), "\n");
  276. /*
  277. * Modifying mode has consequences when the mode comes back to us
  278. */
  279. return true;
  280. }
  281. /* vid_enc timing_params must be configured before calling this function */
  282. static void _sde_encoder_phys_vid_setup_avr(
  283. struct sde_encoder_phys *phys_enc, u32 qsync_min_fps)
  284. {
  285. struct sde_encoder_phys_vid *vid_enc;
  286. struct drm_display_mode mode;
  287. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  288. mode = phys_enc->cached_mode;
  289. if (vid_enc->base.hw_intf->ops.avr_setup) {
  290. struct intf_avr_params avr_params = {0};
  291. u32 default_fps = mode.vrefresh;
  292. int ret;
  293. if (!default_fps) {
  294. SDE_ERROR_VIDENC(vid_enc,
  295. "invalid default fps %d\n",
  296. default_fps);
  297. return;
  298. }
  299. if (qsync_min_fps > default_fps) {
  300. SDE_ERROR_VIDENC(vid_enc,
  301. "qsync fps %d must be less than default %d\n",
  302. qsync_min_fps, default_fps);
  303. return;
  304. }
  305. avr_params.default_fps = default_fps;
  306. avr_params.min_fps = qsync_min_fps;
  307. ret = vid_enc->base.hw_intf->ops.avr_setup(
  308. vid_enc->base.hw_intf,
  309. &vid_enc->timing_params, &avr_params);
  310. if (ret)
  311. SDE_ERROR_VIDENC(vid_enc,
  312. "bad settings, can't configure AVR\n");
  313. SDE_EVT32(DRMID(phys_enc->parent), default_fps,
  314. qsync_min_fps, ret);
  315. }
  316. }
  317. static void _sde_encoder_phys_vid_avr_ctrl(struct sde_encoder_phys *phys_enc)
  318. {
  319. struct intf_avr_params avr_params;
  320. struct sde_encoder_phys_vid *vid_enc =
  321. to_sde_encoder_phys_vid(phys_enc);
  322. avr_params.avr_mode = sde_connector_get_qsync_mode(
  323. phys_enc->connector);
  324. if (vid_enc->base.hw_intf->ops.avr_ctrl) {
  325. vid_enc->base.hw_intf->ops.avr_ctrl(
  326. vid_enc->base.hw_intf,
  327. &avr_params);
  328. }
  329. SDE_EVT32(DRMID(phys_enc->parent),
  330. phys_enc->hw_intf->idx - INTF_0,
  331. avr_params.avr_mode);
  332. }
  333. static void sde_encoder_phys_vid_setup_timing_engine(
  334. struct sde_encoder_phys *phys_enc)
  335. {
  336. struct sde_encoder_phys_vid *vid_enc;
  337. struct drm_display_mode mode;
  338. struct intf_timing_params timing_params = { 0 };
  339. const struct sde_format *fmt = NULL;
  340. u32 fmt_fourcc = DRM_FORMAT_RGB888;
  341. u32 qsync_min_fps = 0;
  342. unsigned long lock_flags;
  343. struct sde_hw_intf_cfg intf_cfg = { 0 };
  344. bool is_split_link = false;
  345. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->hw_ctl ||
  346. !phys_enc->hw_intf) {
  347. SDE_ERROR("invalid encoder %d\n", !phys_enc);
  348. return;
  349. }
  350. mode = phys_enc->cached_mode;
  351. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  352. if (!phys_enc->hw_intf->ops.setup_timing_gen) {
  353. SDE_ERROR("timing engine setup is not supported\n");
  354. return;
  355. }
  356. SDE_DEBUG_VIDENC(vid_enc, "enabling mode:\n");
  357. drm_mode_debug_printmodeline(&mode);
  358. is_split_link = phys_enc->hw_intf->cfg.split_link_en;
  359. if (phys_enc->split_role != ENC_ROLE_SOLO || is_split_link) {
  360. mode.hdisplay >>= 1;
  361. mode.htotal >>= 1;
  362. mode.hsync_start >>= 1;
  363. mode.hsync_end >>= 1;
  364. SDE_DEBUG_VIDENC(vid_enc,
  365. "split_role %d, halve horizontal %d %d %d %d\n",
  366. phys_enc->split_role,
  367. mode.hdisplay, mode.htotal,
  368. mode.hsync_start, mode.hsync_end);
  369. }
  370. if (!phys_enc->vfp_cached) {
  371. phys_enc->vfp_cached =
  372. sde_connector_get_panel_vfp(phys_enc->connector, &mode);
  373. if (phys_enc->vfp_cached <= 0)
  374. phys_enc->vfp_cached = mode.vsync_start - mode.vdisplay;
  375. }
  376. drm_mode_to_intf_timing_params(vid_enc, &mode, &timing_params);
  377. vid_enc->timing_params = timing_params;
  378. if (phys_enc->cont_splash_enabled) {
  379. SDE_DEBUG_VIDENC(vid_enc,
  380. "skipping intf programming since cont splash is enabled\n");
  381. goto exit;
  382. }
  383. fmt = sde_get_sde_format(fmt_fourcc);
  384. SDE_DEBUG_VIDENC(vid_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
  385. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  386. phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
  387. &timing_params, fmt);
  388. if (test_bit(SDE_CTL_ACTIVE_CFG,
  389. &phys_enc->hw_ctl->caps->features)) {
  390. sde_encoder_helper_update_intf_cfg(phys_enc);
  391. } else if (phys_enc->hw_ctl->ops.setup_intf_cfg) {
  392. intf_cfg.intf = phys_enc->hw_intf->idx;
  393. intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  394. intf_cfg.stream_sel = 0; /* Don't care value for video mode */
  395. intf_cfg.mode_3d =
  396. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  397. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  398. &intf_cfg);
  399. }
  400. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  401. if (phys_enc->hw_intf->cap->type == INTF_DSI)
  402. programmable_fetch_config(phys_enc, &timing_params);
  403. exit:
  404. if (phys_enc->parent_ops.get_qsync_fps)
  405. phys_enc->parent_ops.get_qsync_fps(
  406. phys_enc->parent, &qsync_min_fps, mode.vrefresh);
  407. /* only panels which support qsync will have a non-zero min fps */
  408. if (qsync_min_fps) {
  409. _sde_encoder_phys_vid_setup_avr(phys_enc, qsync_min_fps);
  410. _sde_encoder_phys_vid_avr_ctrl(phys_enc);
  411. }
  412. }
  413. static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
  414. {
  415. struct sde_encoder_phys *phys_enc = arg;
  416. struct sde_hw_ctl *hw_ctl;
  417. struct intf_status intf_status = {0};
  418. unsigned long lock_flags;
  419. u32 flush_register = ~0;
  420. u32 reset_status = 0;
  421. int new_cnt = -1, old_cnt = -1;
  422. u32 event = 0;
  423. int pend_ret_fence_cnt = 0;
  424. if (!phys_enc)
  425. return;
  426. hw_ctl = phys_enc->hw_ctl;
  427. if (!hw_ctl)
  428. return;
  429. SDE_ATRACE_BEGIN("vblank_irq");
  430. /*
  431. * only decrement the pending flush count if we've actually flushed
  432. * hardware. due to sw irq latency, vblank may have already happened
  433. * so we need to double-check with hw that it accepted the flush bits
  434. */
  435. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  436. old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt);
  437. if (hw_ctl && hw_ctl->ops.get_flush_register)
  438. flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
  439. if (flush_register)
  440. goto not_flushed;
  441. new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
  442. pend_ret_fence_cnt = atomic_read(&phys_enc->pending_retire_fence_cnt);
  443. /* signal only for master, where there is a pending kickoff */
  444. if (sde_encoder_phys_vid_is_master(phys_enc) &&
  445. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  446. event = SDE_ENCODER_FRAME_EVENT_DONE |
  447. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE |
  448. SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  449. }
  450. not_flushed:
  451. if (hw_ctl && hw_ctl->ops.get_reset)
  452. reset_status = hw_ctl->ops.get_reset(hw_ctl);
  453. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  454. if (event && phys_enc->parent_ops.handle_frame_done)
  455. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  456. phys_enc, event);
  457. if (phys_enc->parent_ops.handle_vblank_virt)
  458. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  459. phys_enc);
  460. if (phys_enc->hw_intf->ops.get_status)
  461. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  462. &intf_status);
  463. SDE_EVT32_IRQ(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
  464. old_cnt, atomic_read(&phys_enc->pending_kickoff_cnt),
  465. reset_status ? SDE_EVTLOG_ERROR : 0,
  466. flush_register, event,
  467. atomic_read(&phys_enc->pending_retire_fence_cnt),
  468. intf_status.frame_count);
  469. /* Signal any waiting atomic commit thread */
  470. wake_up_all(&phys_enc->pending_kickoff_wq);
  471. SDE_ATRACE_END("vblank_irq");
  472. }
  473. static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
  474. {
  475. struct sde_encoder_phys *phys_enc = arg;
  476. if (!phys_enc)
  477. return;
  478. if (phys_enc->parent_ops.handle_underrun_virt)
  479. phys_enc->parent_ops.handle_underrun_virt(phys_enc->parent,
  480. phys_enc);
  481. }
  482. static void _sde_encoder_phys_vid_setup_irq_hw_idx(
  483. struct sde_encoder_phys *phys_enc)
  484. {
  485. struct sde_encoder_irq *irq;
  486. /*
  487. * Initialize irq->hw_idx only when irq is not registered.
  488. * Prevent invalidating irq->irq_idx as modeset may be
  489. * called many times during dfps.
  490. */
  491. irq = &phys_enc->irq[INTR_IDX_VSYNC];
  492. if (irq->irq_idx < 0)
  493. irq->hw_idx = phys_enc->intf_idx;
  494. irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
  495. if (irq->irq_idx < 0)
  496. irq->hw_idx = phys_enc->intf_idx;
  497. }
  498. static void sde_encoder_phys_vid_cont_splash_mode_set(
  499. struct sde_encoder_phys *phys_enc,
  500. struct drm_display_mode *adj_mode)
  501. {
  502. if (!phys_enc || !adj_mode) {
  503. SDE_ERROR("invalid args\n");
  504. return;
  505. }
  506. phys_enc->cached_mode = *adj_mode;
  507. phys_enc->enable_state = SDE_ENC_ENABLED;
  508. _sde_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
  509. }
  510. static void sde_encoder_phys_vid_mode_set(
  511. struct sde_encoder_phys *phys_enc,
  512. struct drm_display_mode *mode,
  513. struct drm_display_mode *adj_mode)
  514. {
  515. struct sde_rm *rm;
  516. struct sde_rm_hw_iter iter;
  517. int i, instance;
  518. struct sde_encoder_phys_vid *vid_enc;
  519. if (!phys_enc || !phys_enc->sde_kms) {
  520. SDE_ERROR("invalid encoder/kms\n");
  521. return;
  522. }
  523. rm = &phys_enc->sde_kms->rm;
  524. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  525. if (adj_mode) {
  526. phys_enc->cached_mode = *adj_mode;
  527. drm_mode_debug_printmodeline(adj_mode);
  528. SDE_DEBUG_VIDENC(vid_enc, "caching mode:\n");
  529. }
  530. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  531. /* Retrieve previously allocated HW Resources. Shouldn't fail */
  532. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  533. for (i = 0; i <= instance; i++) {
  534. if (sde_rm_get_hw(rm, &iter))
  535. phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
  536. }
  537. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  538. SDE_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
  539. PTR_ERR(phys_enc->hw_ctl));
  540. phys_enc->hw_ctl = NULL;
  541. return;
  542. }
  543. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_INTF);
  544. for (i = 0; i <= instance; i++) {
  545. if (sde_rm_get_hw(rm, &iter))
  546. phys_enc->hw_intf = (struct sde_hw_intf *)iter.hw;
  547. }
  548. if (IS_ERR_OR_NULL(phys_enc->hw_intf)) {
  549. SDE_ERROR_VIDENC(vid_enc, "failed to init intf: %ld\n",
  550. PTR_ERR(phys_enc->hw_intf));
  551. phys_enc->hw_intf = NULL;
  552. return;
  553. }
  554. _sde_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
  555. }
  556. static int sde_encoder_phys_vid_control_vblank_irq(
  557. struct sde_encoder_phys *phys_enc,
  558. bool enable)
  559. {
  560. int ret = 0;
  561. struct sde_encoder_phys_vid *vid_enc;
  562. int refcount;
  563. if (!phys_enc) {
  564. SDE_ERROR("invalid encoder\n");
  565. return -EINVAL;
  566. }
  567. mutex_lock(phys_enc->vblank_ctl_lock);
  568. refcount = atomic_read(&phys_enc->vblank_refcount);
  569. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  570. /* Slave encoders don't report vblank */
  571. if (!sde_encoder_phys_vid_is_master(phys_enc))
  572. goto end;
  573. /* protect against negative */
  574. if (!enable && refcount == 0) {
  575. ret = -EINVAL;
  576. goto end;
  577. }
  578. SDE_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
  579. __builtin_return_address(0),
  580. enable, atomic_read(&phys_enc->vblank_refcount));
  581. SDE_EVT32(DRMID(phys_enc->parent), enable,
  582. atomic_read(&phys_enc->vblank_refcount));
  583. if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) {
  584. ret = sde_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
  585. if (ret)
  586. atomic_dec_return(&phys_enc->vblank_refcount);
  587. } else if (!enable &&
  588. atomic_dec_return(&phys_enc->vblank_refcount) == 0) {
  589. ret = sde_encoder_helper_unregister_irq(phys_enc,
  590. INTR_IDX_VSYNC);
  591. if (ret)
  592. atomic_inc_return(&phys_enc->vblank_refcount);
  593. }
  594. end:
  595. if (ret) {
  596. SDE_ERROR_VIDENC(vid_enc,
  597. "control vblank irq error %d, enable %d\n",
  598. ret, enable);
  599. SDE_EVT32(DRMID(phys_enc->parent),
  600. phys_enc->hw_intf->idx - INTF_0,
  601. enable, refcount, SDE_EVTLOG_ERROR);
  602. }
  603. mutex_unlock(phys_enc->vblank_ctl_lock);
  604. return ret;
  605. }
  606. static bool sde_encoder_phys_vid_wait_dma_trigger(
  607. struct sde_encoder_phys *phys_enc)
  608. {
  609. struct sde_encoder_phys_vid *vid_enc;
  610. struct sde_hw_intf *intf;
  611. struct sde_hw_ctl *ctl;
  612. struct intf_status status;
  613. if (!phys_enc) {
  614. SDE_ERROR("invalid encoder\n");
  615. return false;
  616. }
  617. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  618. intf = phys_enc->hw_intf;
  619. ctl = phys_enc->hw_ctl;
  620. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  621. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  622. phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
  623. return false;
  624. }
  625. if (!intf->ops.get_status)
  626. return false;
  627. intf->ops.get_status(intf, &status);
  628. /* if interface is not enabled, return true to wait for dma trigger */
  629. return status.is_en ? false : true;
  630. }
  631. static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
  632. {
  633. struct msm_drm_private *priv;
  634. struct sde_encoder_phys_vid *vid_enc;
  635. struct sde_hw_intf *intf;
  636. struct sde_hw_ctl *ctl;
  637. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
  638. !phys_enc->parent->dev->dev_private ||
  639. !phys_enc->sde_kms) {
  640. SDE_ERROR("invalid encoder/device\n");
  641. return;
  642. }
  643. priv = phys_enc->parent->dev->dev_private;
  644. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  645. intf = phys_enc->hw_intf;
  646. ctl = phys_enc->hw_ctl;
  647. if (!phys_enc->hw_intf || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
  648. SDE_ERROR("invalid hw_intf %d hw_ctl %d hw_pp %d\n",
  649. !phys_enc->hw_intf, !phys_enc->hw_ctl,
  650. !phys_enc->hw_pp);
  651. return;
  652. }
  653. if (!ctl->ops.update_bitmask) {
  654. SDE_ERROR("invalid hw_ctl ops %d\n", ctl->idx);
  655. return;
  656. }
  657. SDE_DEBUG_VIDENC(vid_enc, "\n");
  658. if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
  659. return;
  660. if (!phys_enc->cont_splash_enabled)
  661. sde_encoder_helper_split_config(phys_enc,
  662. phys_enc->hw_intf->idx);
  663. sde_encoder_phys_vid_setup_timing_engine(phys_enc);
  664. /*
  665. * For cases where both the interfaces are connected to same ctl,
  666. * set the flush bit for both master and slave.
  667. * For single flush cases (dual-ctl or pp-split), skip setting the
  668. * flush bit for the slave intf, since both intfs use same ctl
  669. * and HW will only flush the master.
  670. */
  671. if (!test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  672. sde_encoder_phys_needs_single_flush(phys_enc) &&
  673. !sde_encoder_phys_vid_is_master(phys_enc))
  674. goto skip_flush;
  675. /**
  676. * skip flushing intf during cont. splash handoff since bootloader
  677. * has already enabled the hardware and is single buffered.
  678. */
  679. if (phys_enc->cont_splash_enabled) {
  680. SDE_DEBUG_VIDENC(vid_enc,
  681. "skipping intf flush bit set as cont. splash is enabled\n");
  682. goto skip_flush;
  683. }
  684. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_INTF, intf->idx, 1);
  685. if (phys_enc->hw_pp->merge_3d)
  686. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_MERGE_3D,
  687. phys_enc->hw_pp->merge_3d->idx, 1);
  688. if (phys_enc->hw_intf->cap->type == INTF_DP &&
  689. phys_enc->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  690. phys_enc->comp_ratio)
  691. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH, intf->idx, 1);
  692. skip_flush:
  693. SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d intf %d\n",
  694. ctl->idx - CTL_0, intf->idx);
  695. SDE_EVT32(DRMID(phys_enc->parent),
  696. atomic_read(&phys_enc->pending_retire_fence_cnt));
  697. /* ctl_flush & timing engine enable will be triggered by framework */
  698. if (phys_enc->enable_state == SDE_ENC_DISABLED)
  699. phys_enc->enable_state = SDE_ENC_ENABLING;
  700. }
  701. static void sde_encoder_phys_vid_destroy(struct sde_encoder_phys *phys_enc)
  702. {
  703. struct sde_encoder_phys_vid *vid_enc;
  704. if (!phys_enc) {
  705. SDE_ERROR("invalid encoder\n");
  706. return;
  707. }
  708. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  709. SDE_DEBUG_VIDENC(vid_enc, "\n");
  710. kfree(vid_enc);
  711. }
  712. static void sde_encoder_phys_vid_get_hw_resources(
  713. struct sde_encoder_phys *phys_enc,
  714. struct sde_encoder_hw_resources *hw_res,
  715. struct drm_connector_state *conn_state)
  716. {
  717. struct sde_encoder_phys_vid *vid_enc;
  718. if (!phys_enc || !hw_res) {
  719. SDE_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
  720. !phys_enc, !hw_res, !conn_state);
  721. return;
  722. }
  723. if ((phys_enc->intf_idx - INTF_0) >= INTF_MAX) {
  724. SDE_ERROR("invalid intf idx:%d\n", phys_enc->intf_idx);
  725. return;
  726. }
  727. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  728. SDE_DEBUG_VIDENC(vid_enc, "\n");
  729. hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
  730. }
  731. static int _sde_encoder_phys_vid_wait_for_vblank(
  732. struct sde_encoder_phys *phys_enc, bool notify)
  733. {
  734. struct sde_encoder_wait_info wait_info = {0};
  735. int ret = 0;
  736. u32 event = SDE_ENCODER_FRAME_EVENT_ERROR |
  737. SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE |
  738. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  739. struct drm_connector *conn;
  740. if (!phys_enc) {
  741. pr_err("invalid encoder\n");
  742. return -EINVAL;
  743. }
  744. conn = phys_enc->connector;
  745. wait_info.wq = &phys_enc->pending_kickoff_wq;
  746. wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
  747. wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
  748. /* Wait for kickoff to complete */
  749. ret = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
  750. &wait_info);
  751. if (notify && (ret == -ETIMEDOUT) &&
  752. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0) &&
  753. phys_enc->parent_ops.handle_frame_done) {
  754. phys_enc->parent_ops.handle_frame_done(
  755. phys_enc->parent, phys_enc, event);
  756. if (sde_encoder_recovery_events_enabled(phys_enc->parent))
  757. sde_connector_event_notify(conn,
  758. DRM_EVENT_SDE_HW_RECOVERY,
  759. sizeof(uint8_t), SDE_RECOVERY_HARD_RESET);
  760. }
  761. SDE_EVT32(DRMID(phys_enc->parent), event, notify, ret,
  762. ret ? SDE_EVTLOG_FATAL : 0);
  763. return ret;
  764. }
  765. static int sde_encoder_phys_vid_wait_for_vblank(
  766. struct sde_encoder_phys *phys_enc)
  767. {
  768. return _sde_encoder_phys_vid_wait_for_vblank(phys_enc, true);
  769. }
  770. static int sde_encoder_phys_vid_wait_for_vblank_no_notify(
  771. struct sde_encoder_phys *phys_enc)
  772. {
  773. return _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
  774. }
  775. static int sde_encoder_phys_vid_prepare_for_kickoff(
  776. struct sde_encoder_phys *phys_enc,
  777. struct sde_encoder_kickoff_params *params)
  778. {
  779. struct sde_encoder_phys_vid *vid_enc;
  780. struct sde_hw_ctl *ctl;
  781. bool recovery_events;
  782. struct drm_connector *conn;
  783. int rc;
  784. if (!phys_enc || !params || !phys_enc->hw_ctl) {
  785. SDE_ERROR("invalid encoder/parameters\n");
  786. return -EINVAL;
  787. }
  788. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  789. ctl = phys_enc->hw_ctl;
  790. if (!ctl->ops.wait_reset_status)
  791. return 0;
  792. conn = phys_enc->connector;
  793. recovery_events = sde_encoder_recovery_events_enabled(
  794. phys_enc->parent);
  795. /*
  796. * hw supports hardware initiated ctl reset, so before we kickoff a new
  797. * frame, need to check and wait for hw initiated ctl reset completion
  798. */
  799. rc = ctl->ops.wait_reset_status(ctl);
  800. if (rc) {
  801. SDE_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
  802. ctl->idx, rc);
  803. ++vid_enc->error_count;
  804. /* to avoid flooding, only log first time, and "dead" time */
  805. if (vid_enc->error_count == 1) {
  806. SDE_EVT32(DRMID(phys_enc->parent), SDE_EVTLOG_FATAL);
  807. sde_encoder_helper_unregister_irq(
  808. phys_enc, INTR_IDX_VSYNC);
  809. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus");
  810. sde_encoder_helper_register_irq(
  811. phys_enc, INTR_IDX_VSYNC);
  812. }
  813. /*
  814. * if the recovery event is registered by user, don't panic
  815. * trigger panic on first timeout if no listener registered
  816. */
  817. if (recovery_events)
  818. sde_connector_event_notify(conn, DRM_EVENT_SDE_HW_RECOVERY,
  819. sizeof(uint8_t), SDE_RECOVERY_CAPTURE);
  820. else
  821. SDE_DBG_DUMP("panic");
  822. /* request a ctl reset before the next flush */
  823. phys_enc->enable_state = SDE_ENC_ERR_NEEDS_HW_RESET;
  824. } else {
  825. if (recovery_events && vid_enc->error_count)
  826. sde_connector_event_notify(conn,
  827. DRM_EVENT_SDE_HW_RECOVERY,
  828. sizeof(uint8_t),
  829. SDE_RECOVERY_SUCCESS);
  830. vid_enc->error_count = 0;
  831. }
  832. return rc;
  833. }
  834. static void sde_encoder_phys_vid_single_vblank_wait(
  835. struct sde_encoder_phys *phys_enc)
  836. {
  837. int ret;
  838. struct sde_encoder_phys_vid *vid_enc
  839. = to_sde_encoder_phys_vid(phys_enc);
  840. /*
  841. * Wait for a vsync so we know the ENABLE=0 latched before
  842. * the (connector) source of the vsync's gets disabled,
  843. * otherwise we end up in a funny state if we re-enable
  844. * before the disable latches, which results that some of
  845. * the settings changes for the new modeset (like new
  846. * scanout buffer) don't latch properly..
  847. */
  848. ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
  849. if (ret) {
  850. SDE_ERROR_VIDENC(vid_enc,
  851. "failed to enable vblank irq: %d\n",
  852. ret);
  853. SDE_EVT32(DRMID(phys_enc->parent),
  854. phys_enc->hw_intf->idx - INTF_0, ret,
  855. SDE_EVTLOG_FUNC_CASE1,
  856. SDE_EVTLOG_ERROR);
  857. } else {
  858. ret = _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false);
  859. if (ret) {
  860. atomic_set(&phys_enc->pending_kickoff_cnt, 0);
  861. SDE_ERROR_VIDENC(vid_enc,
  862. "failure waiting for disable: %d\n",
  863. ret);
  864. SDE_EVT32(DRMID(phys_enc->parent),
  865. phys_enc->hw_intf->idx - INTF_0, ret,
  866. SDE_EVTLOG_FUNC_CASE2,
  867. SDE_EVTLOG_ERROR);
  868. }
  869. sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
  870. }
  871. }
  872. static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
  873. {
  874. struct msm_drm_private *priv;
  875. struct sde_encoder_phys_vid *vid_enc;
  876. unsigned long lock_flags;
  877. struct intf_status intf_status = {0};
  878. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
  879. !phys_enc->parent->dev->dev_private) {
  880. SDE_ERROR("invalid encoder/device\n");
  881. return;
  882. }
  883. priv = phys_enc->parent->dev->dev_private;
  884. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  885. if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
  886. SDE_ERROR("invalid hw_intf %d hw_ctl %d\n",
  887. !phys_enc->hw_intf, !phys_enc->hw_ctl);
  888. return;
  889. }
  890. SDE_DEBUG_VIDENC(vid_enc, "\n");
  891. if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
  892. return;
  893. else if (!sde_encoder_phys_vid_is_master(phys_enc))
  894. goto exit;
  895. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  896. SDE_ERROR("already disabled\n");
  897. return;
  898. }
  899. if (sde_in_trusted_vm(phys_enc->sde_kms))
  900. goto exit;
  901. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  902. phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
  903. sde_encoder_phys_inc_pending(phys_enc);
  904. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  905. sde_encoder_phys_vid_single_vblank_wait(phys_enc);
  906. if (phys_enc->hw_intf->ops.get_status)
  907. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  908. &intf_status);
  909. if (intf_status.is_en) {
  910. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  911. sde_encoder_phys_inc_pending(phys_enc);
  912. spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
  913. sde_encoder_phys_vid_single_vblank_wait(phys_enc);
  914. }
  915. sde_encoder_helper_phys_disable(phys_enc, NULL);
  916. exit:
  917. SDE_EVT32(DRMID(phys_enc->parent),
  918. atomic_read(&phys_enc->pending_retire_fence_cnt));
  919. phys_enc->vfp_cached = 0;
  920. phys_enc->enable_state = SDE_ENC_DISABLED;
  921. }
  922. static void sde_encoder_phys_vid_handle_post_kickoff(
  923. struct sde_encoder_phys *phys_enc)
  924. {
  925. unsigned long lock_flags;
  926. struct sde_encoder_phys_vid *vid_enc;
  927. u32 avr_mode;
  928. if (!phys_enc) {
  929. SDE_ERROR("invalid encoder\n");
  930. return;
  931. }
  932. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  933. SDE_DEBUG_VIDENC(vid_enc, "enable_state %d\n", phys_enc->enable_state);
  934. /*
  935. * Video mode must flush CTL before enabling timing engine
  936. * Video encoders need to turn on their interfaces now
  937. */
  938. if (phys_enc->enable_state == SDE_ENC_ENABLING) {
  939. if (sde_encoder_phys_vid_is_master(phys_enc)) {
  940. SDE_EVT32(DRMID(phys_enc->parent),
  941. phys_enc->hw_intf->idx - INTF_0);
  942. spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
  943. phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf,
  944. 1);
  945. spin_unlock_irqrestore(phys_enc->enc_spinlock,
  946. lock_flags);
  947. }
  948. phys_enc->enable_state = SDE_ENC_ENABLED;
  949. }
  950. avr_mode = sde_connector_get_qsync_mode(phys_enc->connector);
  951. if (avr_mode && vid_enc->base.hw_intf->ops.avr_trigger) {
  952. vid_enc->base.hw_intf->ops.avr_trigger(vid_enc->base.hw_intf);
  953. SDE_EVT32(DRMID(phys_enc->parent),
  954. phys_enc->hw_intf->idx - INTF_0,
  955. SDE_EVTLOG_FUNC_CASE9);
  956. }
  957. }
  958. static void sde_encoder_phys_vid_prepare_for_commit(
  959. struct sde_encoder_phys *phys_enc)
  960. {
  961. struct drm_crtc *crtc;
  962. if (!phys_enc || !phys_enc->parent) {
  963. SDE_ERROR("invalid encoder parameters\n");
  964. return;
  965. }
  966. crtc = phys_enc->parent->crtc;
  967. if (!crtc || !crtc->state) {
  968. SDE_ERROR("invalid crtc state\n");
  969. return;
  970. }
  971. if (!msm_is_mode_seamless_vrr(&crtc->state->adjusted_mode)
  972. && sde_connector_is_qsync_updated(phys_enc->connector))
  973. _sde_encoder_phys_vid_avr_ctrl(phys_enc);
  974. }
  975. static void sde_encoder_phys_vid_irq_control(struct sde_encoder_phys *phys_enc,
  976. bool enable)
  977. {
  978. struct sde_encoder_phys_vid *vid_enc;
  979. int ret;
  980. if (!phys_enc)
  981. return;
  982. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  983. SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
  984. enable, atomic_read(&phys_enc->vblank_refcount));
  985. if (enable) {
  986. ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
  987. if (ret)
  988. return;
  989. sde_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
  990. } else {
  991. sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
  992. sde_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
  993. }
  994. }
  995. static int sde_encoder_phys_vid_get_line_count(
  996. struct sde_encoder_phys *phys_enc)
  997. {
  998. if (!phys_enc)
  999. return -EINVAL;
  1000. if (!sde_encoder_phys_vid_is_master(phys_enc))
  1001. return -EINVAL;
  1002. if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
  1003. return -EINVAL;
  1004. return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
  1005. }
  1006. static u32 sde_encoder_phys_vid_get_underrun_line_count(
  1007. struct sde_encoder_phys *phys_enc)
  1008. {
  1009. u32 underrun_linecount = 0xebadebad;
  1010. u32 intf_intr_status = 0xebadebad;
  1011. struct intf_status intf_status = {0};
  1012. if (!phys_enc)
  1013. return -EINVAL;
  1014. if (!sde_encoder_phys_vid_is_master(phys_enc) || !phys_enc->hw_intf)
  1015. return -EINVAL;
  1016. if (phys_enc->hw_intf->ops.get_status)
  1017. phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
  1018. &intf_status);
  1019. if (phys_enc->hw_intf->ops.get_underrun_line_count)
  1020. underrun_linecount =
  1021. phys_enc->hw_intf->ops.get_underrun_line_count(
  1022. phys_enc->hw_intf);
  1023. if (phys_enc->hw_intf->ops.get_intr_status)
  1024. intf_intr_status = phys_enc->hw_intf->ops.get_intr_status(
  1025. phys_enc->hw_intf);
  1026. SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount,
  1027. intf_status.frame_count, intf_status.line_count,
  1028. intf_intr_status);
  1029. return underrun_linecount;
  1030. }
  1031. static int sde_encoder_phys_vid_wait_for_active(
  1032. struct sde_encoder_phys *phys_enc)
  1033. {
  1034. struct drm_display_mode mode;
  1035. struct sde_encoder_phys_vid *vid_enc;
  1036. u32 ln_cnt, min_ln_cnt, active_lns_cnt;
  1037. u32 clk_period, time_of_line;
  1038. u32 delay, retry = MAX_POLL_CNT;
  1039. vid_enc = to_sde_encoder_phys_vid(phys_enc);
  1040. if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) {
  1041. SDE_ERROR_VIDENC(vid_enc, "invalid vid_enc params\n");
  1042. return -EINVAL;
  1043. }
  1044. mode = phys_enc->cached_mode;
  1045. /*
  1046. * calculate clk_period as pico second to maintain good
  1047. * accuracy with high pclk rate and this number is in 17 bit
  1048. * range.
  1049. */
  1050. clk_period = DIV_ROUND_UP_ULL(1000000000, mode.clock);
  1051. if (!clk_period) {
  1052. SDE_ERROR_VIDENC(vid_enc, "Unable to calculate clock period\n");
  1053. return -EINVAL;
  1054. }
  1055. min_ln_cnt = (mode.vtotal - mode.vsync_start) +
  1056. (mode.vsync_end - mode.vsync_start);
  1057. active_lns_cnt = mode.vdisplay;
  1058. time_of_line = mode.htotal * clk_period;
  1059. /* delay in micro seconds */
  1060. delay = (time_of_line * (min_ln_cnt +
  1061. (mode.vsync_start - mode.vdisplay))) / 1000000;
  1062. /*
  1063. * Wait for max delay before
  1064. * polling to check active region
  1065. */
  1066. if (delay > POLL_TIME_USEC_FOR_LN_CNT)
  1067. delay = POLL_TIME_USEC_FOR_LN_CNT;
  1068. while (retry) {
  1069. ln_cnt = phys_enc->hw_intf->ops.get_line_count(
  1070. phys_enc->hw_intf);
  1071. if ((ln_cnt >= min_ln_cnt) &&
  1072. (ln_cnt < (active_lns_cnt + min_ln_cnt))) {
  1073. SDE_DEBUG_VIDENC(vid_enc,
  1074. "Needed lines left line_cnt=%d\n",
  1075. ln_cnt);
  1076. return 0;
  1077. }
  1078. SDE_ERROR_VIDENC(vid_enc, "line count is less. line_cnt = %d\n",
  1079. ln_cnt);
  1080. /* Add delay so that line count is in active region */
  1081. udelay(delay);
  1082. retry--;
  1083. }
  1084. return -EINVAL;
  1085. }
  1086. static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops)
  1087. {
  1088. ops->is_master = sde_encoder_phys_vid_is_master;
  1089. ops->mode_set = sde_encoder_phys_vid_mode_set;
  1090. ops->cont_splash_mode_set = sde_encoder_phys_vid_cont_splash_mode_set;
  1091. ops->mode_fixup = sde_encoder_phys_vid_mode_fixup;
  1092. ops->enable = sde_encoder_phys_vid_enable;
  1093. ops->disable = sde_encoder_phys_vid_disable;
  1094. ops->destroy = sde_encoder_phys_vid_destroy;
  1095. ops->get_hw_resources = sde_encoder_phys_vid_get_hw_resources;
  1096. ops->control_vblank_irq = sde_encoder_phys_vid_control_vblank_irq;
  1097. ops->wait_for_commit_done = sde_encoder_phys_vid_wait_for_vblank;
  1098. ops->wait_for_vblank = sde_encoder_phys_vid_wait_for_vblank_no_notify;
  1099. ops->wait_for_tx_complete = sde_encoder_phys_vid_wait_for_vblank;
  1100. ops->irq_control = sde_encoder_phys_vid_irq_control;
  1101. ops->prepare_for_kickoff = sde_encoder_phys_vid_prepare_for_kickoff;
  1102. ops->handle_post_kickoff = sde_encoder_phys_vid_handle_post_kickoff;
  1103. ops->needs_single_flush = sde_encoder_phys_needs_single_flush;
  1104. ops->setup_misr = sde_encoder_helper_setup_misr;
  1105. ops->collect_misr = sde_encoder_helper_collect_misr;
  1106. ops->trigger_flush = sde_encoder_helper_trigger_flush;
  1107. ops->hw_reset = sde_encoder_helper_hw_reset;
  1108. ops->get_line_count = sde_encoder_phys_vid_get_line_count;
  1109. ops->get_wr_line_count = sde_encoder_phys_vid_get_line_count;
  1110. ops->wait_dma_trigger = sde_encoder_phys_vid_wait_dma_trigger;
  1111. ops->wait_for_active = sde_encoder_phys_vid_wait_for_active;
  1112. ops->prepare_commit = sde_encoder_phys_vid_prepare_for_commit;
  1113. ops->get_underrun_line_count =
  1114. sde_encoder_phys_vid_get_underrun_line_count;
  1115. }
  1116. struct sde_encoder_phys *sde_encoder_phys_vid_init(
  1117. struct sde_enc_phys_init_params *p)
  1118. {
  1119. struct sde_encoder_phys *phys_enc = NULL;
  1120. struct sde_encoder_phys_vid *vid_enc = NULL;
  1121. struct sde_hw_mdp *hw_mdp;
  1122. struct sde_encoder_irq *irq;
  1123. int i, ret = 0;
  1124. if (!p) {
  1125. ret = -EINVAL;
  1126. goto fail;
  1127. }
  1128. vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL);
  1129. if (!vid_enc) {
  1130. ret = -ENOMEM;
  1131. goto fail;
  1132. }
  1133. phys_enc = &vid_enc->base;
  1134. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1135. if (IS_ERR_OR_NULL(hw_mdp)) {
  1136. ret = PTR_ERR(hw_mdp);
  1137. SDE_ERROR("failed to get mdptop\n");
  1138. goto fail;
  1139. }
  1140. phys_enc->hw_mdptop = hw_mdp;
  1141. phys_enc->intf_idx = p->intf_idx;
  1142. SDE_DEBUG_VIDENC(vid_enc, "\n");
  1143. sde_encoder_phys_vid_init_ops(&phys_enc->ops);
  1144. phys_enc->parent = p->parent;
  1145. phys_enc->parent_ops = p->parent_ops;
  1146. phys_enc->sde_kms = p->sde_kms;
  1147. phys_enc->split_role = p->split_role;
  1148. phys_enc->intf_mode = INTF_MODE_VIDEO;
  1149. phys_enc->enc_spinlock = p->enc_spinlock;
  1150. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1151. phys_enc->comp_type = p->comp_type;
  1152. for (i = 0; i < INTR_IDX_MAX; i++) {
  1153. irq = &phys_enc->irq[i];
  1154. INIT_LIST_HEAD(&irq->cb.list);
  1155. irq->irq_idx = -EINVAL;
  1156. irq->hw_idx = -EINVAL;
  1157. irq->cb.arg = phys_enc;
  1158. }
  1159. irq = &phys_enc->irq[INTR_IDX_VSYNC];
  1160. irq->name = "vsync_irq";
  1161. irq->intr_type = SDE_IRQ_TYPE_INTF_VSYNC;
  1162. irq->intr_idx = INTR_IDX_VSYNC;
  1163. irq->cb.func = sde_encoder_phys_vid_vblank_irq;
  1164. irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
  1165. irq->name = "underrun";
  1166. irq->intr_type = SDE_IRQ_TYPE_INTF_UNDER_RUN;
  1167. irq->intr_idx = INTR_IDX_UNDERRUN;
  1168. irq->cb.func = sde_encoder_phys_vid_underrun_irq;
  1169. atomic_set(&phys_enc->vblank_refcount, 0);
  1170. atomic_set(&phys_enc->pending_kickoff_cnt, 0);
  1171. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1172. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1173. phys_enc->enable_state = SDE_ENC_DISABLED;
  1174. SDE_DEBUG_VIDENC(vid_enc, "created intf idx:%d\n", p->intf_idx);
  1175. return phys_enc;
  1176. fail:
  1177. SDE_ERROR("failed to create encoder\n");
  1178. if (vid_enc)
  1179. sde_encoder_phys_vid_destroy(phys_enc);
  1180. return ERR_PTR(ret);
  1181. }