2b640ea7f9
To support QCN7605 DBS chip, which has 3 RF chains, chain0 is for 2G, chain1 is for 2G/5G, and chain2 for 5G. So it need 3 bits to indicate RF chainmask for DBS mode. This is to extend the value range for 2g/5g chainmask setting for QCN7605 DBS mode. Change-Id: I43ee3393c121b6e9609223af1db0059158d44078 CRs-Fixed: 2933722
407 строки
10 KiB
C
407 строки
10 KiB
C
/*
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* Copyright (c) 2012-2019, 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* DOC: This file contains centralized definitions of converged configuration.
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*/
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#ifndef __CFG_CHAINMASK_H
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#define __CFG_CHAINMASK_H
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/*
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* <ini>
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* gSetTxChainmask1x1 - Sets Transmit chain mask.
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* @Min: 0
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* @Max: 3
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* @Default: 1
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*
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* This ini Sets Transmit chain mask.
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*
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* If gEnable2x2 is disabled, gSetTxChainmask1x1 and gSetRxChainmask1x1 values
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* are taken into account. If chainmask value exceeds the maximum number of
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* chains supported by target, the max number of chains is used. By default,
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* chain0 is selected for both Tx and Rx.
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* gSetTxChainmask1x1=1 or gSetRxChainmask1x1=1 to select chain0.
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* gSetTxChainmask1x1=2 or gSetRxChainmask1x1=2 to select chain1.
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* gSetTxChainmask1x1=3 or gSetRxChainmask1x1=3 to select both chains.
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*
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* Supported Feature: 11AC
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_VHT_ENABLE_1x1_TX_CHAINMASK CFG_INI_UINT( \
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"gSetTxChainmask1x1", \
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0, \
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3, \
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1, \
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CFG_VALUE_OR_DEFAULT, \
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"1x1 VHT Tx Chainmask")
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/*
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* <ini>
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* gSetRxChainmask1x1 - Sets Receive chain mask.
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* @Min: 0
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* @Max: 3
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* @Default: 1
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*
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* This ini is used to set Receive chain mask.
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*
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* If gEnable2x2 is disabled, gSetTxChainmask1x1 and gSetRxChainmask1x1 values
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* are taken into account. If chainmask value exceeds the maximum number of
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* chains supported by target, the max number of chains is used. By default,
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* chain0 is selected for both Tx and Rx.
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* gSetTxChainmask1x1=1 or gSetRxChainmask1x1=1 to select chain0.
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* gSetTxChainmask1x1=2 or gSetRxChainmask1x1=2 to select chain1.
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* gSetTxChainmask1x1=3 or gSetRxChainmask1x1=3 to select both chains.
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*
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* Supported Feature: 11AC
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_VHT_ENABLE_1x1_RX_CHAINMASK CFG_INI_UINT( \
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"gSetRxChainmask1x1", \
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0, \
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3, \
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1, \
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CFG_VALUE_OR_DEFAULT, \
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"1x1 VHT Rx Chainmask")
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/*
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* <ini>
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* gCckChainMaskEnable - Used to enable/disable Cck ChainMask
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* @Min: 0
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* @Max: 1
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* @Default: 0
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*
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* This ini is used to set default Cck ChainMask
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* 0: disable the cck tx chain mask (default)
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* 1: enable the cck tx chain mask
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*
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* Related: None
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*
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* Supported Feature: STA
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*
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* Usage: Internal/External
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*
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* </ini>
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*/
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#define CFG_TX_CHAIN_MASK_CCK CFG_INI_BOOL( \
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"gCckChainMaskEnable", \
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0, \
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"Set default CCK Tx Chainmask")
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/*
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* <ini>
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* gTxChainMask1ss - Enables/disables tx chain mask1ss, used by Rome
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* @Min: 0
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* @Max: 3
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* @Default: 0
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*
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* This ini is used to set default tx chain mask for 1ss
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*
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* gTxChainMask1ss=0 : 1ss data tx chain mask set to 3 and self gen chain mask
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* set to 3. This is default setting of fw side. For 1x1 case, WIFI will
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* using chain0 to sent 1ss data and selfgen packets. 2x2 case, WIFI will
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* using chain0 and chain1 to sent 1ss data and selfgen packets.
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*
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* gTxChainMask1ss=1 : 1ss data tx chain mask set to 2 and self gen chain mask
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* set to 2. This setting can work only when 2x2 case, WIFI will use chain1
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* to sent 1ss data packets and selfgen packets, this can improve BTC
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* performance a little, but have side affect when chain0 and chain1 RSSI
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* is unbalance or green AP is enabled. So we recommend not using it.
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*
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* gTxChainMask1ss=2 : 1ss data tx chain mask set to 3 and self gen chain mask
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* set to 2. This setting never used before.
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*
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* gTxChainMask1ss=3 : 1ss data tx chain mask set to 2 and self gen chain mask
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* set to 3. This setting never used before.
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*
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* Related: None
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*
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* Supported Feature: STA/SAP
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*
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* Usage: Internal/External
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*
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* </ini>
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*/
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#define CFG_TX_CHAIN_MASK_1SS CFG_INI_UINT( \
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"gTxChainMask1ss", \
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0, \
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3, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"1SS Tx Chainmask")
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/*
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* <ini>
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* g11bNumTxChains - Number of Tx Chanins in 11b mode
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* @Min: 0
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* @Max: 2
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* @Default: 0
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*
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* Number of Tx Chanins in 11b mode
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*
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*
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* Related: None
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*
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* Supported Feature: connection
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_11B_NUM_TX_CHAIN CFG_INI_UINT( \
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"g11bNumTxChains", \
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0, \
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2, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"11b Num Tx chains")
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/*
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* <ini>
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* g11agNumTxChains - Number of Tx Chanins in 11ag mode
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* @Min: 0
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* @Max: 2
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* @Default: 0
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*
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* Number of Tx Chanins in 11ag mode
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*
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*
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* Related: None
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*
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* Supported Feature: connection
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_11AG_NUM_TX_CHAIN CFG_INI_UINT( \
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"g11agNumTxChains", \
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0, \
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2, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"11ag Num Tx chains")
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/*
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* <ini>
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* tx_chain_mask_2g - tx chain mask for 2g
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* @Min: 0
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* @Max: 4
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* @Default: 0
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*
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* This ini will set tx chain mask for 2g. To use the ini, make sure:
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* gSetTxChainmask1x1/gSetRxChainmask1x1 = 0,
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* gDualMacFeatureDisable = 1
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* gEnable2x2 = 0
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*
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* tx_chain_mask_2g=0 : don't care
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* tx_chain_mask_2g=1 : for 2g tx use chain 0
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* tx_chain_mask_2g=2 : for 2g tx use chain 1
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* tx_chain_mask_2g=3 : for 2g tx can use either chain
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*
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* QCN7605 DBS chip has 3 RF chains.
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* Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G.
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* DBS mode need 3 bits to map chainmask and halphy.
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* In HW design, PHYA0 always Connects to shared RF chain1.
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* tx_chain_mask_2g=4 : for 2g tx chain use PHYB and chain 0
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*
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* Related: None
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*
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* Supported Feature: All profiles
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_TX_CHAIN_MASK_2G CFG_INI_UINT( \
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"tx_chain_mask_2g", \
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0, \
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4, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"2.4G Tx Chainmask")
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/*
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* <ini>
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* rx_chain_mask_2g - rx chain mask for 2g
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* @Min: 0
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* @Max: 4
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* @Default: 0
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*
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* This ini will set rx chain mask for 2g. To use the ini, make sure:
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* gSetTxChainmask1x1/gSetRxChainmask1x1 = 0,
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* gDualMacFeatureDisable = 1
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* gEnable2x2 = 0
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*
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* rx_chain_mask_2g=0 : don't care
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* rx_chain_mask_2g=1 : for 2g rx use chain 0
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* rx_chain_mask_2g=2 : for 2g rx use chain 1
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* rx_chain_mask_2g=3 : for 2g rx can use either chain
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*
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* QCN7605 DBS chip has 3 RF chains.
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* Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G.
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* DBS mode need 3 bits to map chainmask and halphy.
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* In HW design, PHYA0 always Connects to shared RF chain1.
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* rx_chain_mask_2g=4 : for 2g rx chain use PHYB and chain 0
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*
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* Related: None
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*
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* Supported Feature: All profiles
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_RX_CHAIN_MASK_2G CFG_INI_UINT( \
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"rx_chain_mask_2g", \
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0, \
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4, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"2.4G Rx Chainmask")
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/*
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* <ini>
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* tx_chain_mask_5g - tx chain mask for 5g
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* @Min: 0
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* @Max: 6
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* @Default: 0
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*
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* This ini will set tx chain mask for 5g. To use the ini, make sure:
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* gSetTxChainmask1x1/gSetRxChainmask1x1 = 0,
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* gDualMacFeatureDisable = 1
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* gEnable2x2 = 0
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*
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* tx_chain_mask_5g=0 : don't care
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* tx_chain_mask_5g=1 : for 5g tx use chain 0, Genoa use chain 1
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* tx_chain_mask_5g=2 : for 5g tx use chain 1, Genoa use chain 2
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* tx_chain_mask_5g=3 : for 5g tx can use either chain
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*
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* QCN7605 DBS chip has 3 RF chains.
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* Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G.
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* DBS mode need 3 bits to map chainmask and halphy.
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* In HW design, PHYA0 always Connects to shared RF chain1.
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* tx_chain_mask_5g=4 : for 5g tx chain use PHYB and chain 2
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* tx_chain_mask_5g=5 : for 5g tx chain use PHYA and chain 1
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* tx_chain_mask_5g=6 : for 5g tx chain use PHYA and chain 2
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*
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* Related: None
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*
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* Supported Feature: All profiles
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_TX_CHAIN_MASK_5G CFG_INI_UINT( \
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"tx_chain_mask_5g", \
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0, \
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6, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"5Ghz Tx Chainmask")
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/*
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* <ini>
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* rx_chain_mask_5g - rx chain mask for 5g
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* @Min: 0
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* @Max: 6
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* @Default: 0
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*
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* This ini will set rx chain mask for 5g. To use the ini, make sure:
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* gSetTxChainmask1x1/gSetRxChainmask1x1 = 0,
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* gDualMacFeatureDisable = 1
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* gEnable2x2 = 0
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*
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* rx_chain_mask_5g=0 : don't care
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* rx_chain_mask_5g=1 : for 5g rx use chain 0, Genoa use chain 1
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* rx_chain_mask_5g=2 : for 5g rx use chain 1, Genoa use chain 2
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* rx_chain_mask_5g=3 : for 5g rx can use either chain
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*
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* QCN7605 DBS chip has 3 RF chains.
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* Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G.
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* DBS mode need 3 bits to map halphy and chain.
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* HW design, PHYA0 always Connects to shared RF chain1.
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* rx_chain_mask_5g=4 : for 5g rx chain use PHYB and chain 2
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* rx_chain_mask_5g=5 : for 5g rx chain use PHYA and chain 1
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* rx_chain_mask_5g=6 : for 5g rx chain use PHYB and chain 2
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*
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* Related: None
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*
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* Supported Feature: All profiles
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_RX_CHAIN_MASK_5G CFG_INI_UINT( \
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"rx_chain_mask_5g", \
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0, \
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6, \
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0, \
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CFG_VALUE_OR_DEFAULT, \
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"5Ghz Rx Chainmask")
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/*
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* <ini>
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* enable_bt_chain_separation - Enables/disables bt /wlan chainmask assignment
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* @Min: 0
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* @Max: 1
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* @Default: 0
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*
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* This ini disables/enables chainmask setting on 2x2, mainly used for ROME
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* BT/WLAN chainmask assignment.
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*
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* 0, Disable
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* 1, Enable
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*
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* Related: NA
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*
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* Supported Feature: 11n/11ac
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_ENABLE_BT_CHAIN_SEPARATION CFG_INI_BOOL( \
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"enableBTChainSeparation", \
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0, \
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"Enable/disable BT chainmask assignment")
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#define CFG_CHAINMASK_ALL \
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CFG(CFG_VHT_ENABLE_1x1_TX_CHAINMASK) \
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CFG(CFG_VHT_ENABLE_1x1_RX_CHAINMASK) \
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CFG(CFG_TX_CHAIN_MASK_CCK) \
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CFG(CFG_TX_CHAIN_MASK_1SS) \
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CFG(CFG_11B_NUM_TX_CHAIN) \
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CFG(CFG_11AG_NUM_TX_CHAIN) \
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CFG(CFG_TX_CHAIN_MASK_2G) \
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CFG(CFG_RX_CHAIN_MASK_2G) \
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CFG(CFG_TX_CHAIN_MASK_5G) \
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CFG(CFG_RX_CHAIN_MASK_5G) \
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CFG(CFG_ENABLE_BT_CHAIN_SEPARATION)
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#endif /* __CFG_CHAINMASK_H */
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