wcd938x.c 137 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <sound/soc.h>
  14. #include <sound/tlv.h>
  15. #include <soc/soundwire.h>
  16. #include <linux/regmap.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <asoc/msm-cdc-supply.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <linux/qti-regmap-debugfs.h>
  24. #include "wcd938x-registers.h"
  25. #include "wcd938x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #define NUM_SWRS_DT_PARAMS 5
  29. #define WCD938X_VARIANT_ENTRY_SIZE 32
  30. #define WCD938X_VERSION_1_0 1
  31. #define WCD938X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. #define ADC_MODE_VAL_HIFI 0x01
  34. #define ADC_MODE_VAL_LO_HIF 0x02
  35. #define ADC_MODE_VAL_NORMAL 0x03
  36. #define ADC_MODE_VAL_LP 0x05
  37. #define ADC_MODE_VAL_ULP1 0x09
  38. #define ADC_MODE_VAL_ULP2 0x0B
  39. #define NUM_ATTEMPTS 5
  40. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  41. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  42. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  43. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  44. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  45. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  46. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  47. SNDRV_PCM_RATE_384000)
  48. /* Fractional Rates */
  49. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  50. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  51. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  52. SNDRV_PCM_FMTBIT_S24_LE |\
  53. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  54. enum {
  55. CODEC_TX = 0,
  56. CODEC_RX,
  57. };
  58. enum {
  59. WCD_ADC1 = 0,
  60. WCD_ADC2,
  61. WCD_ADC3,
  62. WCD_ADC4,
  63. ALLOW_BUCK_DISABLE,
  64. HPH_COMP_DELAY,
  65. HPH_PA_DELAY,
  66. AMIC2_BCS_ENABLE,
  67. WCD_SUPPLIES_LPM_MODE,
  68. WCD_ADC1_MODE,
  69. WCD_ADC2_MODE,
  70. WCD_ADC3_MODE,
  71. WCD_ADC4_MODE,
  72. WCD_HPHL_EN,
  73. WCD_EAR_EN,
  74. };
  75. enum {
  76. ADC_MODE_INVALID = 0,
  77. ADC_MODE_HIFI,
  78. ADC_MODE_LO_HIF,
  79. ADC_MODE_NORMAL,
  80. ADC_MODE_LP,
  81. ADC_MODE_ULP1,
  82. ADC_MODE_ULP2,
  83. };
  84. static u8 tx_mode_bit[] = {
  85. [ADC_MODE_INVALID] = 0x00,
  86. [ADC_MODE_HIFI] = 0x01,
  87. [ADC_MODE_LO_HIF] = 0x02,
  88. [ADC_MODE_NORMAL] = 0x04,
  89. [ADC_MODE_LP] = 0x08,
  90. [ADC_MODE_ULP1] = 0x10,
  91. [ADC_MODE_ULP2] = 0x20,
  92. };
  93. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  94. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  95. static int wcd938x_handle_post_irq(void *data);
  96. static int wcd938x_reset(struct device *dev);
  97. static int wcd938x_reset_low(struct device *dev);
  98. static int wcd938x_get_adc_mode(int val);
  99. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  100. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  115. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  116. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  117. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  118. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  119. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  120. };
  121. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  122. .name = "wcd938x",
  123. .irqs = wcd938x_irqs,
  124. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  125. .num_regs = 3,
  126. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  127. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  128. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  129. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  130. .use_ack = 1,
  131. .runtime_pm = false,
  132. .handle_post_irq = wcd938x_handle_post_irq,
  133. .irq_drv_data = NULL,
  134. };
  135. static int wcd938x_handle_post_irq(void *data)
  136. {
  137. struct wcd938x_priv *wcd938x = data;
  138. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  139. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  140. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  141. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  142. wcd938x->tx_swr_dev->slave_irq_pending =
  143. ((sts1 || sts2 || sts3) ? true : false);
  144. return IRQ_HANDLED;
  145. }
  146. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  147. {
  148. int ret = 0;
  149. int bank = 0;
  150. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  151. if (ret)
  152. return -EINVAL;
  153. return ((bank & 0x40) ? 1: 0);
  154. }
  155. static int wcd938x_get_clk_rate(int mode)
  156. {
  157. int rate;
  158. switch (mode) {
  159. case ADC_MODE_ULP2:
  160. rate = SWR_CLK_RATE_0P6MHZ;
  161. break;
  162. case ADC_MODE_ULP1:
  163. rate = SWR_CLK_RATE_1P2MHZ;
  164. break;
  165. case ADC_MODE_LP:
  166. rate = SWR_CLK_RATE_4P8MHZ;
  167. break;
  168. case ADC_MODE_NORMAL:
  169. case ADC_MODE_LO_HIF:
  170. case ADC_MODE_HIFI:
  171. case ADC_MODE_INVALID:
  172. default:
  173. rate = SWR_CLK_RATE_9P6MHZ;
  174. break;
  175. }
  176. return rate;
  177. }
  178. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  179. int rate, int bank)
  180. {
  181. u8 mask = (bank ? 0xF0 : 0x0F);
  182. u8 val = 0;
  183. switch (rate) {
  184. case SWR_CLK_RATE_0P6MHZ:
  185. val = (bank ? 0x60 : 0x06);
  186. break;
  187. case SWR_CLK_RATE_1P2MHZ:
  188. val = (bank ? 0x50 : 0x05);
  189. break;
  190. case SWR_CLK_RATE_2P4MHZ:
  191. val = (bank ? 0x30 : 0x03);
  192. break;
  193. case SWR_CLK_RATE_4P8MHZ:
  194. val = (bank ? 0x10 : 0x01);
  195. break;
  196. case SWR_CLK_RATE_9P6MHZ:
  197. default:
  198. val = 0x00;
  199. break;
  200. }
  201. snd_soc_component_update_bits(component,
  202. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  203. mask, val);
  204. return 0;
  205. }
  206. static int wcd938x_init_reg(struct snd_soc_component *component)
  207. {
  208. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  209. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  210. /* 1 msec delay as per HW requirement */
  211. usleep_range(1000, 1010);
  212. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  213. /* 1 msec delay as per HW requirement */
  214. usleep_range(1000, 1010);
  215. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  216. 0x10, 0x00);
  217. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  218. 0xF0, 0x80);
  219. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  220. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  221. /* 10 msec delay as per HW requirement */
  222. usleep_range(10000, 10010);
  223. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  224. snd_soc_component_update_bits(component,
  225. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  226. 0xF0, 0x00);
  227. snd_soc_component_update_bits(component,
  228. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  229. 0x1F, 0x15);
  230. snd_soc_component_update_bits(component,
  231. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  232. 0x1F, 0x15);
  233. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  234. 0xC0, 0x80);
  235. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  236. 0x02, 0x02);
  237. snd_soc_component_update_bits(component,
  238. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  239. 0xFF, 0x14);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  242. 0x1F, 0x08);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  253. snd_soc_component_update_bits(component,
  254. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  255. snd_soc_component_update_bits(component,
  256. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  257. snd_soc_component_update_bits(component,
  258. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  259. snd_soc_component_update_bits(component,
  260. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  261. snd_soc_component_update_bits(component,
  262. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  263. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  264. ((snd_soc_component_read(component,
  265. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  266. snd_soc_component_update_bits(component,
  267. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  268. return 0;
  269. }
  270. static int wcd938x_set_port_params(struct snd_soc_component *component,
  271. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  272. u8 *ch_mask, u32 *ch_rate,
  273. u8 *port_type, u8 path)
  274. {
  275. int i, j;
  276. u8 num_ports = 0;
  277. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  278. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  279. switch (path) {
  280. case CODEC_RX:
  281. map = &wcd938x->rx_port_mapping;
  282. num_ports = wcd938x->num_rx_ports;
  283. break;
  284. case CODEC_TX:
  285. map = &wcd938x->tx_port_mapping;
  286. num_ports = wcd938x->num_tx_ports;
  287. break;
  288. default:
  289. dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
  290. __func__, path);
  291. return -EINVAL;
  292. }
  293. for (i = 0; i <= num_ports; i++) {
  294. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  295. if ((*map)[i][j].slave_port_type == slv_prt_type)
  296. goto found;
  297. }
  298. }
  299. found:
  300. if (i > num_ports || j == MAX_CH_PER_PORT) {
  301. dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
  302. __func__, slv_prt_type);
  303. return -EINVAL;
  304. }
  305. *port_id = i;
  306. *num_ch = (*map)[i][j].num_ch;
  307. *ch_mask = (*map)[i][j].ch_mask;
  308. *ch_rate = (*map)[i][j].ch_rate;
  309. *port_type = (*map)[i][j].master_port_type;
  310. return 0;
  311. }
  312. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  313. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  314. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  315. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  316. static int wcd938x_parse_port_params(struct device *dev,
  317. char *prop, u8 path)
  318. {
  319. u32 *dt_array, map_size, max_uc;
  320. int ret = 0;
  321. u32 cnt = 0;
  322. u32 i, j;
  323. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  324. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  325. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  326. switch (path) {
  327. case CODEC_TX:
  328. map = &wcd938x->tx_port_params;
  329. map_uc = &wcd938x->swr_tx_port_params;
  330. break;
  331. default:
  332. ret = -EINVAL;
  333. goto err_port_map;
  334. }
  335. if (!of_find_property(dev->of_node, prop,
  336. &map_size)) {
  337. dev_err(dev, "missing port mapping prop %s\n", prop);
  338. ret = -EINVAL;
  339. goto err_port_map;
  340. }
  341. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  342. if (max_uc != SWR_UC_MAX) {
  343. dev_err(dev, "%s: port params not provided for all usecases\n",
  344. __func__);
  345. ret = -EINVAL;
  346. goto err_port_map;
  347. }
  348. dt_array = kzalloc(map_size, GFP_KERNEL);
  349. if (!dt_array) {
  350. ret = -ENOMEM;
  351. goto err_alloc;
  352. }
  353. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  354. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  355. if (ret) {
  356. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  357. __func__, prop);
  358. goto err_pdata_fail;
  359. }
  360. for (i = 0; i < max_uc; i++) {
  361. for (j = 0; j < SWR_NUM_PORTS; j++) {
  362. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  363. (*map)[i][j].offset1 = dt_array[cnt];
  364. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  365. }
  366. (*map_uc)[i].pp = &(*map)[i][0];
  367. }
  368. kfree(dt_array);
  369. return 0;
  370. err_pdata_fail:
  371. kfree(dt_array);
  372. err_alloc:
  373. err_port_map:
  374. return ret;
  375. }
  376. static int wcd938x_parse_port_mapping(struct device *dev,
  377. char *prop, u8 path)
  378. {
  379. u32 *dt_array, map_size, map_length;
  380. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  381. u32 slave_port_type, master_port_type;
  382. u32 i, ch_iter = 0;
  383. int ret = 0;
  384. u8 *num_ports = NULL;
  385. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  386. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  387. switch (path) {
  388. case CODEC_RX:
  389. map = &wcd938x->rx_port_mapping;
  390. num_ports = &wcd938x->num_rx_ports;
  391. break;
  392. case CODEC_TX:
  393. map = &wcd938x->tx_port_mapping;
  394. num_ports = &wcd938x->num_tx_ports;
  395. break;
  396. default:
  397. dev_err(dev, "%s Invalid path selected %u\n",
  398. __func__, path);
  399. return -EINVAL;
  400. }
  401. if (!of_find_property(dev->of_node, prop,
  402. &map_size)) {
  403. dev_err(dev, "missing port mapping prop %s\n", prop);
  404. ret = -EINVAL;
  405. goto err_port_map;
  406. }
  407. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  408. dt_array = kzalloc(map_size, GFP_KERNEL);
  409. if (!dt_array) {
  410. ret = -ENOMEM;
  411. goto err_alloc;
  412. }
  413. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  414. NUM_SWRS_DT_PARAMS * map_length);
  415. if (ret) {
  416. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  417. __func__, prop);
  418. goto err_pdata_fail;
  419. }
  420. for (i = 0; i < map_length; i++) {
  421. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  422. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  423. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  424. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  425. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  426. if (port_num != old_port_num)
  427. ch_iter = 0;
  428. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  429. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  430. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  431. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  432. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  433. old_port_num = port_num;
  434. }
  435. *num_ports = port_num;
  436. kfree(dt_array);
  437. return 0;
  438. err_pdata_fail:
  439. kfree(dt_array);
  440. err_alloc:
  441. err_port_map:
  442. return ret;
  443. }
  444. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  445. u8 slv_port_type, int clk_rate,
  446. u8 enable)
  447. {
  448. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  449. u8 port_id, num_ch, ch_mask;
  450. u8 ch_type = 0;
  451. u32 ch_rate;
  452. int slave_ch_idx;
  453. u8 num_port = 1;
  454. int ret = 0;
  455. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  456. &num_ch, &ch_mask, &ch_rate,
  457. &ch_type, CODEC_TX);
  458. if (ret)
  459. return ret;
  460. if (clk_rate)
  461. ch_rate = clk_rate;
  462. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  463. if (slave_ch_idx != -EINVAL)
  464. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  465. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  466. __func__, slave_ch_idx, ch_type);
  467. if (enable)
  468. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  469. num_port, &ch_mask, &ch_rate,
  470. &num_ch, &ch_type);
  471. else
  472. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  473. num_port, &ch_mask, &ch_type);
  474. return ret;
  475. }
  476. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  477. u8 slv_port_type, u8 enable)
  478. {
  479. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  480. u8 port_id, num_ch, ch_mask, port_type;
  481. u32 ch_rate;
  482. u8 num_port = 1;
  483. int ret = 0;
  484. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  485. &num_ch, &ch_mask, &ch_rate,
  486. &port_type, CODEC_RX);
  487. if (ret)
  488. return ret;
  489. if (enable)
  490. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  491. num_port, &ch_mask, &ch_rate,
  492. &num_ch, &port_type);
  493. else
  494. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  495. num_port, &ch_mask, &port_type);
  496. return ret;
  497. }
  498. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  499. {
  500. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  501. if (wcd938x->rx_clk_cnt == 0) {
  502. snd_soc_component_update_bits(component,
  503. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  508. snd_soc_component_update_bits(component,
  509. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  510. snd_soc_component_update_bits(component,
  511. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  512. snd_soc_component_update_bits(component,
  513. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  514. snd_soc_component_update_bits(component,
  515. WCD938X_AUX_AUXPA, 0x10, 0x10);
  516. }
  517. wcd938x->rx_clk_cnt++;
  518. return 0;
  519. }
  520. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  521. {
  522. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  523. wcd938x->rx_clk_cnt--;
  524. if (wcd938x->rx_clk_cnt == 0) {
  525. snd_soc_component_update_bits(component,
  526. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  527. snd_soc_component_update_bits(component,
  528. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  529. snd_soc_component_update_bits(component,
  530. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  531. snd_soc_component_update_bits(component,
  532. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  533. snd_soc_component_update_bits(component,
  534. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  535. }
  536. return 0;
  537. }
  538. /*
  539. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  540. * @component: handle to snd_soc_component *
  541. *
  542. * return wcd938x_mbhc handle or error code in case of failure
  543. */
  544. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  545. {
  546. struct wcd938x_priv *wcd938x;
  547. if (!component) {
  548. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  549. return NULL;
  550. }
  551. wcd938x = snd_soc_component_get_drvdata(component);
  552. if (!wcd938x) {
  553. pr_err_ratelimited("%s: wcd938x is NULL\n", __func__);
  554. return NULL;
  555. }
  556. return wcd938x->mbhc;
  557. }
  558. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  559. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  560. struct snd_kcontrol *kcontrol,
  561. int event)
  562. {
  563. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  564. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  565. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  566. w->name, event);
  567. switch (event) {
  568. case SND_SOC_DAPM_PRE_PMU:
  569. wcd938x_rx_clk_enable(component);
  570. snd_soc_component_update_bits(component,
  571. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  572. snd_soc_component_update_bits(component,
  573. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  574. snd_soc_component_update_bits(component,
  575. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  576. break;
  577. case SND_SOC_DAPM_POST_PMU:
  578. snd_soc_component_update_bits(component,
  579. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  580. if (wcd938x->comp1_enable) {
  581. snd_soc_component_update_bits(component,
  582. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  583. /* 5msec compander delay as per HW requirement */
  584. if (!wcd938x->comp2_enable ||
  585. (snd_soc_component_read(component,
  586. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  587. usleep_range(5000, 5010);
  588. snd_soc_component_update_bits(component,
  589. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  590. } else {
  591. snd_soc_component_update_bits(component,
  592. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  593. 0x02, 0x00);
  594. snd_soc_component_update_bits(component,
  595. WCD938X_HPH_L_EN, 0x20, 0x20);
  596. }
  597. break;
  598. case SND_SOC_DAPM_POST_PMD:
  599. snd_soc_component_update_bits(component,
  600. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  601. 0x0F, 0x01);
  602. break;
  603. }
  604. return 0;
  605. }
  606. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  607. struct snd_kcontrol *kcontrol,
  608. int event)
  609. {
  610. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  611. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  612. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  613. w->name, event);
  614. switch (event) {
  615. case SND_SOC_DAPM_PRE_PMU:
  616. wcd938x_rx_clk_enable(component);
  617. snd_soc_component_update_bits(component,
  618. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  619. snd_soc_component_update_bits(component,
  620. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  621. snd_soc_component_update_bits(component,
  622. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  623. break;
  624. case SND_SOC_DAPM_POST_PMU:
  625. snd_soc_component_update_bits(component,
  626. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  627. if (wcd938x->comp2_enable) {
  628. snd_soc_component_update_bits(component,
  629. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  630. /* 5msec compander delay as per HW requirement */
  631. if (!wcd938x->comp1_enable ||
  632. (snd_soc_component_read(component,
  633. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  634. usleep_range(5000, 5010);
  635. snd_soc_component_update_bits(component,
  636. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  637. } else {
  638. snd_soc_component_update_bits(component,
  639. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  640. 0x01, 0x00);
  641. snd_soc_component_update_bits(component,
  642. WCD938X_HPH_R_EN, 0x20, 0x20);
  643. }
  644. break;
  645. case SND_SOC_DAPM_POST_PMD:
  646. snd_soc_component_update_bits(component,
  647. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  648. 0x0F, 0x01);
  649. break;
  650. }
  651. return 0;
  652. }
  653. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  654. struct snd_kcontrol *kcontrol,
  655. int event)
  656. {
  657. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  658. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  659. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  660. w->name, event);
  661. switch (event) {
  662. case SND_SOC_DAPM_PRE_PMU:
  663. wcd938x_rx_clk_enable(component);
  664. wcd938x->ear_rx_path =
  665. snd_soc_component_read(
  666. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  667. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  668. snd_soc_component_update_bits(component,
  669. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  670. snd_soc_component_update_bits(component,
  671. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  672. snd_soc_component_update_bits(component,
  673. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  674. snd_soc_component_update_bits(component,
  675. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  676. } else {
  677. snd_soc_component_update_bits(component,
  678. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  679. snd_soc_component_update_bits(component,
  680. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  681. if (wcd938x->comp1_enable)
  682. snd_soc_component_update_bits(component,
  683. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  684. 0x02, 0x02);
  685. }
  686. /* 5 msec delay as per HW requirement */
  687. usleep_range(5000, 5010);
  688. if (wcd938x->flyback_cur_det_disable == 0)
  689. snd_soc_component_update_bits(component,
  690. WCD938X_FLYBACK_EN,
  691. 0x04, 0x00);
  692. wcd938x->flyback_cur_det_disable++;
  693. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  694. WCD_CLSH_EVENT_PRE_DAC,
  695. WCD_CLSH_STATE_EAR,
  696. wcd938x->hph_mode);
  697. break;
  698. case SND_SOC_DAPM_POST_PMD:
  699. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  700. snd_soc_component_update_bits(component,
  701. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  702. snd_soc_component_update_bits(component,
  703. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  704. } else {
  705. if (!(test_bit(WCD_HPHL_EN, &wcd938x->status_mask))) {
  706. snd_soc_component_update_bits(component,
  707. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  708. snd_soc_component_update_bits(component,
  709. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  710. 0x01, 0x00);
  711. }
  712. if (wcd938x->comp1_enable)
  713. snd_soc_component_update_bits(component,
  714. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  715. 0x02, 0x00);
  716. }
  717. snd_soc_component_update_bits(component,
  718. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  719. snd_soc_component_update_bits(component,
  720. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  721. break;
  722. };
  723. return 0;
  724. }
  725. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  726. struct snd_kcontrol *kcontrol,
  727. int event)
  728. {
  729. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  730. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  731. int ret = 0;
  732. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  733. w->name, event);
  734. switch (event) {
  735. case SND_SOC_DAPM_PRE_PMU:
  736. wcd938x_rx_clk_enable(component);
  737. snd_soc_component_update_bits(component,
  738. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  739. snd_soc_component_update_bits(component,
  740. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  741. snd_soc_component_update_bits(component,
  742. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  743. if (wcd938x->flyback_cur_det_disable == 0)
  744. snd_soc_component_update_bits(component,
  745. WCD938X_FLYBACK_EN,
  746. 0x04, 0x00);
  747. wcd938x->flyback_cur_det_disable++;
  748. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  749. WCD_CLSH_EVENT_PRE_DAC,
  750. WCD_CLSH_STATE_AUX,
  751. wcd938x->hph_mode);
  752. break;
  753. case SND_SOC_DAPM_POST_PMD:
  754. snd_soc_component_update_bits(component,
  755. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  756. break;
  757. };
  758. return ret;
  759. }
  760. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  761. struct snd_kcontrol *kcontrol,
  762. int event)
  763. {
  764. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  765. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  766. int ret = 0;
  767. int hph_mode = wcd938x->hph_mode;
  768. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  769. w->name, event);
  770. switch (event) {
  771. case SND_SOC_DAPM_PRE_PMU:
  772. if (wcd938x->ldoh)
  773. snd_soc_component_update_bits(component,
  774. WCD938X_LDOH_MODE,
  775. 0x80, 0x80);
  776. if (wcd938x->update_wcd_event)
  777. wcd938x->update_wcd_event(wcd938x->handle,
  778. SLV_BOLERO_EVT_RX_MUTE,
  779. (WCD_RX2 << 0x10 | 0x1));
  780. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  781. wcd938x->rx_swr_dev->dev_num,
  782. true);
  783. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  784. WCD_CLSH_EVENT_PRE_DAC,
  785. WCD_CLSH_STATE_HPHR,
  786. hph_mode);
  787. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  788. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  789. hph_mode == CLS_H_ULP) {
  790. snd_soc_component_update_bits(component,
  791. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  792. }
  793. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  794. 0x10, 0x10);
  795. wcd_clsh_set_hph_mode(component, hph_mode);
  796. /* 100 usec delay as per HW requirement */
  797. usleep_range(100, 110);
  798. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  799. snd_soc_component_update_bits(component,
  800. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  801. break;
  802. case SND_SOC_DAPM_POST_PMU:
  803. /*
  804. * 7ms sleep is required if compander is enabled as per
  805. * HW requirement. If compander is disabled, then
  806. * 20ms delay is required.
  807. */
  808. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  809. if (!wcd938x->comp2_enable)
  810. usleep_range(20000, 20100);
  811. else
  812. usleep_range(7000, 7100);
  813. if (hph_mode == CLS_H_LP ||
  814. hph_mode == CLS_H_LOHIFI ||
  815. hph_mode == CLS_H_ULP)
  816. snd_soc_component_update_bits(component,
  817. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  818. 0x00);
  819. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  820. }
  821. snd_soc_component_update_bits(component,
  822. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  823. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  824. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  825. snd_soc_component_update_bits(component,
  826. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  827. if (wcd938x->update_wcd_event)
  828. wcd938x->update_wcd_event(wcd938x->handle,
  829. SLV_BOLERO_EVT_RX_MUTE,
  830. (WCD_RX2 << 0x10));
  831. wcd_enable_irq(&wcd938x->irq_info,
  832. WCD938X_IRQ_HPHR_PDM_WD_INT);
  833. break;
  834. case SND_SOC_DAPM_PRE_PMD:
  835. if (wcd938x->update_wcd_event)
  836. wcd938x->update_wcd_event(wcd938x->handle,
  837. SLV_BOLERO_EVT_RX_MUTE,
  838. (WCD_RX2 << 0x10 | 0x1));
  839. wcd_disable_irq(&wcd938x->irq_info,
  840. WCD938X_IRQ_HPHR_PDM_WD_INT);
  841. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  842. wcd938x->update_wcd_event(wcd938x->handle,
  843. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  844. (WCD_RX2 << 0x10));
  845. /*
  846. * 7ms sleep is required if compander is enabled as per
  847. * HW requirement. If compander is disabled, then
  848. * 20ms delay is required.
  849. */
  850. if (!wcd938x->comp2_enable)
  851. usleep_range(20000, 20100);
  852. else
  853. usleep_range(7000, 7100);
  854. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  855. 0x40, 0x00);
  856. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  857. WCD_EVENT_PRE_HPHR_PA_OFF,
  858. &wcd938x->mbhc->wcd_mbhc);
  859. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  860. break;
  861. case SND_SOC_DAPM_POST_PMD:
  862. /*
  863. * 7ms sleep is required if compander is enabled as per
  864. * HW requirement. If compander is disabled, then
  865. * 20ms delay is required.
  866. */
  867. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  868. if (!wcd938x->comp2_enable)
  869. usleep_range(20000, 20100);
  870. else
  871. usleep_range(7000, 7100);
  872. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  873. }
  874. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  875. WCD_EVENT_POST_HPHR_PA_OFF,
  876. &wcd938x->mbhc->wcd_mbhc);
  877. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  878. 0x10, 0x00);
  879. snd_soc_component_update_bits(component,
  880. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  881. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  882. WCD_CLSH_EVENT_POST_PA,
  883. WCD_CLSH_STATE_HPHR,
  884. hph_mode);
  885. if (wcd938x->ldoh)
  886. snd_soc_component_update_bits(component,
  887. WCD938X_LDOH_MODE,
  888. 0x80, 0x00);
  889. break;
  890. };
  891. return ret;
  892. }
  893. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  894. struct snd_kcontrol *kcontrol,
  895. int event)
  896. {
  897. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  898. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  899. int ret = 0;
  900. int hph_mode = wcd938x->hph_mode;
  901. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  902. w->name, event);
  903. switch (event) {
  904. case SND_SOC_DAPM_PRE_PMU:
  905. if (wcd938x->ldoh)
  906. snd_soc_component_update_bits(component,
  907. WCD938X_LDOH_MODE,
  908. 0x80, 0x80);
  909. if (wcd938x->update_wcd_event)
  910. wcd938x->update_wcd_event(wcd938x->handle,
  911. SLV_BOLERO_EVT_RX_MUTE,
  912. (WCD_RX1 << 0x10 | 0x01));
  913. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  914. wcd938x->rx_swr_dev->dev_num,
  915. true);
  916. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  917. WCD_CLSH_EVENT_PRE_DAC,
  918. WCD_CLSH_STATE_HPHL,
  919. hph_mode);
  920. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  921. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  922. hph_mode == CLS_H_ULP) {
  923. snd_soc_component_update_bits(component,
  924. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  925. }
  926. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  927. 0x20, 0x20);
  928. wcd_clsh_set_hph_mode(component, hph_mode);
  929. /* 100 usec delay as per HW requirement */
  930. usleep_range(100, 110);
  931. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  932. snd_soc_component_update_bits(component,
  933. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  934. set_bit(WCD_HPHL_EN, &wcd938x->status_mask);
  935. break;
  936. case SND_SOC_DAPM_POST_PMU:
  937. /*
  938. * 7ms sleep is required if compander is enabled as per
  939. * HW requirement. If compander is disabled, then
  940. * 20ms delay is required.
  941. */
  942. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  943. if (!wcd938x->comp1_enable)
  944. usleep_range(20000, 20100);
  945. else
  946. usleep_range(7000, 7100);
  947. if (hph_mode == CLS_H_LP ||
  948. hph_mode == CLS_H_LOHIFI ||
  949. hph_mode == CLS_H_ULP)
  950. snd_soc_component_update_bits(component,
  951. WCD938X_HPH_REFBUFF_LP_CTL,
  952. 0x01, 0x00);
  953. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  954. }
  955. snd_soc_component_update_bits(component,
  956. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  957. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  958. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  959. snd_soc_component_update_bits(component,
  960. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  961. if (wcd938x->update_wcd_event)
  962. wcd938x->update_wcd_event(wcd938x->handle,
  963. SLV_BOLERO_EVT_RX_MUTE,
  964. (WCD_RX1 << 0x10));
  965. wcd_enable_irq(&wcd938x->irq_info,
  966. WCD938X_IRQ_HPHL_PDM_WD_INT);
  967. break;
  968. case SND_SOC_DAPM_PRE_PMD:
  969. if (!test_bit(WCD_EAR_EN, &wcd938x->status_mask)) {
  970. if (wcd938x->update_wcd_event)
  971. wcd938x->update_wcd_event(wcd938x->handle,
  972. SLV_BOLERO_EVT_RX_MUTE,
  973. (WCD_RX1 << 0x10 | 0x1));
  974. wcd_disable_irq(&wcd938x->irq_info,
  975. WCD938X_IRQ_HPHL_PDM_WD_INT);
  976. }
  977. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  978. wcd938x->update_wcd_event(wcd938x->handle,
  979. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  980. (WCD_RX1 << 0x10));
  981. /*
  982. * 7ms sleep is required if compander is enabled as per
  983. * HW requirement. If compander is disabled, then
  984. * 20ms delay is required.
  985. */
  986. if (!wcd938x->comp1_enable)
  987. usleep_range(20000, 20100);
  988. else
  989. usleep_range(7000, 7100);
  990. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  991. 0x80, 0x00);
  992. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  993. WCD_EVENT_PRE_HPHL_PA_OFF,
  994. &wcd938x->mbhc->wcd_mbhc);
  995. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  996. break;
  997. case SND_SOC_DAPM_POST_PMD:
  998. /*
  999. * 7ms sleep is required if compander is enabled as per
  1000. * HW requirement. If compander is disabled, then
  1001. * 20ms delay is required.
  1002. */
  1003. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  1004. if (!wcd938x->comp1_enable)
  1005. usleep_range(21000, 21100);
  1006. else
  1007. usleep_range(7000, 7100);
  1008. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  1009. }
  1010. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1011. WCD_EVENT_POST_HPHL_PA_OFF,
  1012. &wcd938x->mbhc->wcd_mbhc);
  1013. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1014. 0x20, 0x00);
  1015. snd_soc_component_update_bits(component,
  1016. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  1017. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1018. WCD_CLSH_EVENT_POST_PA,
  1019. WCD_CLSH_STATE_HPHL,
  1020. hph_mode);
  1021. if (wcd938x->ldoh)
  1022. snd_soc_component_update_bits(component,
  1023. WCD938X_LDOH_MODE,
  1024. 0x80, 0x00);
  1025. clear_bit(WCD_HPHL_EN, &wcd938x->status_mask);
  1026. break;
  1027. };
  1028. return ret;
  1029. }
  1030. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1031. struct snd_kcontrol *kcontrol,
  1032. int event)
  1033. {
  1034. struct snd_soc_component *component =
  1035. snd_soc_dapm_to_component(w->dapm);
  1036. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1037. int hph_mode = wcd938x->hph_mode;
  1038. int ret = 0;
  1039. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1040. w->name, event);
  1041. switch (event) {
  1042. case SND_SOC_DAPM_PRE_PMU:
  1043. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1044. wcd938x->rx_swr_dev->dev_num,
  1045. true);
  1046. snd_soc_component_update_bits(component,
  1047. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  1048. break;
  1049. case SND_SOC_DAPM_POST_PMU:
  1050. /* 1 msec delay as per HW requirement */
  1051. usleep_range(1000, 1010);
  1052. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1053. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1054. snd_soc_component_update_bits(component,
  1055. WCD938X_ANA_RX_SUPPLIES,
  1056. 0x02, 0x02);
  1057. if (wcd938x->update_wcd_event)
  1058. wcd938x->update_wcd_event(wcd938x->handle,
  1059. SLV_BOLERO_EVT_RX_MUTE,
  1060. (WCD_RX3 << 0x10));
  1061. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  1062. break;
  1063. case SND_SOC_DAPM_PRE_PMD:
  1064. wcd_disable_irq(&wcd938x->irq_info,
  1065. WCD938X_IRQ_AUX_PDM_WD_INT);
  1066. if (wcd938x->update_wcd_event)
  1067. wcd938x->update_wcd_event(wcd938x->handle,
  1068. SLV_BOLERO_EVT_RX_MUTE,
  1069. (WCD_RX3 << 0x10 | 0x1));
  1070. break;
  1071. case SND_SOC_DAPM_POST_PMD:
  1072. /* 1 msec delay as per HW requirement */
  1073. usleep_range(1000, 1010);
  1074. snd_soc_component_update_bits(component,
  1075. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1076. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1077. WCD_CLSH_EVENT_POST_PA,
  1078. WCD_CLSH_STATE_AUX,
  1079. hph_mode);
  1080. wcd938x->flyback_cur_det_disable--;
  1081. if (wcd938x->flyback_cur_det_disable == 0)
  1082. snd_soc_component_update_bits(component,
  1083. WCD938X_FLYBACK_EN,
  1084. 0x04, 0x04);
  1085. break;
  1086. };
  1087. return ret;
  1088. }
  1089. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1090. struct snd_kcontrol *kcontrol,
  1091. int event)
  1092. {
  1093. struct snd_soc_component *component =
  1094. snd_soc_dapm_to_component(w->dapm);
  1095. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1096. int hph_mode = wcd938x->hph_mode;
  1097. int ret = 0;
  1098. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1099. w->name, event);
  1100. switch (event) {
  1101. case SND_SOC_DAPM_PRE_PMU:
  1102. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1103. wcd938x->rx_swr_dev->dev_num,
  1104. true);
  1105. /*
  1106. * Enable watchdog interrupt for HPHL or AUX
  1107. * depending on mux value
  1108. */
  1109. wcd938x->ear_rx_path =
  1110. snd_soc_component_read(
  1111. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1112. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1113. snd_soc_component_update_bits(component,
  1114. WCD938X_DIGITAL_PDM_WD_CTL2,
  1115. 0x01, 0x01);
  1116. else {
  1117. snd_soc_component_update_bits(component,
  1118. WCD938X_DIGITAL_PDM_WD_CTL0,
  1119. 0x07, 0x03);
  1120. set_bit(WCD_EAR_EN, &wcd938x->status_mask);
  1121. }
  1122. if (!wcd938x->comp1_enable)
  1123. snd_soc_component_update_bits(component,
  1124. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1125. break;
  1126. case SND_SOC_DAPM_POST_PMU:
  1127. /* 6 msec delay as per HW requirement */
  1128. usleep_range(6000, 6010);
  1129. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1130. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1131. snd_soc_component_update_bits(component,
  1132. WCD938X_ANA_RX_SUPPLIES,
  1133. 0x02, 0x02);
  1134. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1135. if (wcd938x->update_wcd_event)
  1136. wcd938x->update_wcd_event(wcd938x->handle,
  1137. SLV_BOLERO_EVT_RX_MUTE,
  1138. (WCD_RX3 << 0x10));
  1139. wcd_enable_irq(&wcd938x->irq_info,
  1140. WCD938X_IRQ_AUX_PDM_WD_INT);
  1141. } else {
  1142. if (wcd938x->update_wcd_event)
  1143. wcd938x->update_wcd_event(wcd938x->handle,
  1144. SLV_BOLERO_EVT_RX_MUTE,
  1145. (WCD_RX1 << 0x10));
  1146. wcd_enable_irq(&wcd938x->irq_info,
  1147. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1148. }
  1149. break;
  1150. case SND_SOC_DAPM_PRE_PMD:
  1151. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1152. wcd_disable_irq(&wcd938x->irq_info,
  1153. WCD938X_IRQ_AUX_PDM_WD_INT);
  1154. if (wcd938x->update_wcd_event)
  1155. wcd938x->update_wcd_event(wcd938x->handle,
  1156. SLV_BOLERO_EVT_RX_MUTE,
  1157. (WCD_RX3 << 0x10 | 0x1));
  1158. } else {
  1159. if(!test_bit(WCD_HPHL_EN, &wcd938x->status_mask)) {
  1160. wcd_disable_irq(&wcd938x->irq_info,
  1161. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1162. if (wcd938x->update_wcd_event)
  1163. wcd938x->update_wcd_event(wcd938x->handle,
  1164. SLV_BOLERO_EVT_RX_MUTE,
  1165. (WCD_RX1 << 0x10 | 0x1));
  1166. }
  1167. }
  1168. break;
  1169. case SND_SOC_DAPM_POST_PMD:
  1170. if (!wcd938x->comp1_enable)
  1171. snd_soc_component_update_bits(component,
  1172. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1173. /* 7 msec delay as per HW requirement */
  1174. usleep_range(7000, 7010);
  1175. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1176. snd_soc_component_update_bits(component,
  1177. WCD938X_DIGITAL_PDM_WD_CTL2,
  1178. 0x01, 0x00);
  1179. else {
  1180. snd_soc_component_update_bits(component,
  1181. WCD938X_DIGITAL_PDM_WD_CTL0,
  1182. 0x07, 0x00);
  1183. clear_bit(WCD_EAR_EN, &wcd938x->status_mask);
  1184. }
  1185. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1186. WCD_CLSH_EVENT_POST_PA,
  1187. WCD_CLSH_STATE_EAR,
  1188. hph_mode);
  1189. wcd938x->flyback_cur_det_disable--;
  1190. if (wcd938x->flyback_cur_det_disable == 0)
  1191. snd_soc_component_update_bits(component,
  1192. WCD938X_FLYBACK_EN,
  1193. 0x04, 0x04);
  1194. break;
  1195. };
  1196. return ret;
  1197. }
  1198. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1199. struct snd_kcontrol *kcontrol,
  1200. int event)
  1201. {
  1202. struct snd_soc_component *component =
  1203. snd_soc_dapm_to_component(w->dapm);
  1204. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1205. int mode = wcd938x->hph_mode;
  1206. int ret = 0;
  1207. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1208. w->name, event);
  1209. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1210. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1211. wcd938x_rx_connect_port(component, CLSH,
  1212. SND_SOC_DAPM_EVENT_ON(event));
  1213. }
  1214. if (SND_SOC_DAPM_EVENT_OFF(event))
  1215. ret = swr_slvdev_datapath_control(
  1216. wcd938x->rx_swr_dev,
  1217. wcd938x->rx_swr_dev->dev_num,
  1218. false);
  1219. return ret;
  1220. }
  1221. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1222. struct snd_kcontrol *kcontrol,
  1223. int event)
  1224. {
  1225. struct snd_soc_component *component =
  1226. snd_soc_dapm_to_component(w->dapm);
  1227. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1228. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1229. w->name, event);
  1230. switch (event) {
  1231. case SND_SOC_DAPM_PRE_PMU:
  1232. wcd938x_rx_connect_port(component, HPH_L, true);
  1233. if (wcd938x->comp1_enable)
  1234. wcd938x_rx_connect_port(component, COMP_L, true);
  1235. break;
  1236. case SND_SOC_DAPM_POST_PMD:
  1237. if (!test_bit(WCD_HPHL_EN, &wcd938x->status_mask) &&
  1238. !test_bit(WCD_EAR_EN, &wcd938x->status_mask)) {
  1239. wcd938x_rx_connect_port(component, HPH_L, false);
  1240. if (wcd938x->comp1_enable)
  1241. wcd938x_rx_connect_port(component, COMP_L, false);
  1242. wcd938x_rx_clk_disable(component);
  1243. snd_soc_component_update_bits(component,
  1244. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1245. 0x01, 0x00);
  1246. }
  1247. break;
  1248. };
  1249. return 0;
  1250. }
  1251. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1252. struct snd_kcontrol *kcontrol, int event)
  1253. {
  1254. struct snd_soc_component *component =
  1255. snd_soc_dapm_to_component(w->dapm);
  1256. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1257. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1258. w->name, event);
  1259. switch (event) {
  1260. case SND_SOC_DAPM_PRE_PMU:
  1261. wcd938x_rx_connect_port(component, HPH_R, true);
  1262. if (wcd938x->comp2_enable)
  1263. wcd938x_rx_connect_port(component, COMP_R, true);
  1264. break;
  1265. case SND_SOC_DAPM_POST_PMD:
  1266. wcd938x_rx_connect_port(component, HPH_R, false);
  1267. if (wcd938x->comp2_enable)
  1268. wcd938x_rx_connect_port(component, COMP_R, false);
  1269. wcd938x_rx_clk_disable(component);
  1270. snd_soc_component_update_bits(component,
  1271. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1272. 0x02, 0x00);
  1273. break;
  1274. };
  1275. return 0;
  1276. }
  1277. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1278. struct snd_kcontrol *kcontrol,
  1279. int event)
  1280. {
  1281. struct snd_soc_component *component =
  1282. snd_soc_dapm_to_component(w->dapm);
  1283. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1284. w->name, event);
  1285. switch (event) {
  1286. case SND_SOC_DAPM_PRE_PMU:
  1287. wcd938x_rx_connect_port(component, LO, true);
  1288. break;
  1289. case SND_SOC_DAPM_POST_PMD:
  1290. wcd938x_rx_connect_port(component, LO, false);
  1291. /* 6 msec delay as per HW requirement */
  1292. usleep_range(6000, 6010);
  1293. wcd938x_rx_clk_disable(component);
  1294. snd_soc_component_update_bits(component,
  1295. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1296. break;
  1297. }
  1298. return 0;
  1299. }
  1300. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1301. struct snd_kcontrol *kcontrol,
  1302. int event)
  1303. {
  1304. struct snd_soc_component *component =
  1305. snd_soc_dapm_to_component(w->dapm);
  1306. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1307. u16 dmic_clk_reg, dmic_clk_en_reg;
  1308. s32 *dmic_clk_cnt;
  1309. u8 dmic_ctl_shift = 0;
  1310. u8 dmic_clk_shift = 0;
  1311. u8 dmic_clk_mask = 0;
  1312. u16 dmic2_left_en = 0;
  1313. int ret = 0;
  1314. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1315. w->name, event);
  1316. switch (w->shift) {
  1317. case 0:
  1318. case 1:
  1319. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1320. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1321. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1322. dmic_clk_mask = 0x0F;
  1323. dmic_clk_shift = 0x00;
  1324. dmic_ctl_shift = 0x00;
  1325. break;
  1326. case 2:
  1327. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1328. case 3:
  1329. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1330. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1331. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1332. dmic_clk_mask = 0xF0;
  1333. dmic_clk_shift = 0x04;
  1334. dmic_ctl_shift = 0x01;
  1335. break;
  1336. case 4:
  1337. case 5:
  1338. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1339. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1340. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1341. dmic_clk_mask = 0x0F;
  1342. dmic_clk_shift = 0x00;
  1343. dmic_ctl_shift = 0x02;
  1344. break;
  1345. case 6:
  1346. case 7:
  1347. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1348. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1349. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1350. dmic_clk_mask = 0xF0;
  1351. dmic_clk_shift = 0x04;
  1352. dmic_ctl_shift = 0x03;
  1353. break;
  1354. default:
  1355. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  1356. __func__);
  1357. return -EINVAL;
  1358. };
  1359. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1360. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1361. switch (event) {
  1362. case SND_SOC_DAPM_PRE_PMU:
  1363. snd_soc_component_update_bits(component,
  1364. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1365. (0x01 << dmic_ctl_shift), 0x00);
  1366. /* 250us sleep as per HW requirement */
  1367. usleep_range(250, 260);
  1368. if (dmic2_left_en)
  1369. snd_soc_component_update_bits(component,
  1370. dmic2_left_en, 0x80, 0x80);
  1371. /* Setting DMIC clock rate to 2.4MHz */
  1372. snd_soc_component_update_bits(component,
  1373. dmic_clk_reg, dmic_clk_mask,
  1374. (0x03 << dmic_clk_shift));
  1375. snd_soc_component_update_bits(component,
  1376. dmic_clk_en_reg, 0x08, 0x08);
  1377. /* enable clock scaling */
  1378. snd_soc_component_update_bits(component,
  1379. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1380. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1381. wcd938x->tx_swr_dev->dev_num,
  1382. true);
  1383. break;
  1384. case SND_SOC_DAPM_POST_PMD:
  1385. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1386. false);
  1387. snd_soc_component_update_bits(component,
  1388. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1389. (0x01 << dmic_ctl_shift),
  1390. (0x01 << dmic_ctl_shift));
  1391. if (dmic2_left_en)
  1392. snd_soc_component_update_bits(component,
  1393. dmic2_left_en, 0x80, 0x00);
  1394. snd_soc_component_update_bits(component,
  1395. dmic_clk_en_reg, 0x08, 0x00);
  1396. break;
  1397. };
  1398. return ret;
  1399. }
  1400. /*
  1401. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1402. * @micb_mv: micbias in mv
  1403. *
  1404. * return register value converted
  1405. */
  1406. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1407. {
  1408. /* min micbias voltage is 1V and maximum is 2.85V */
  1409. if (micb_mv < 1000 || micb_mv > 2850) {
  1410. pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
  1411. return -EINVAL;
  1412. }
  1413. return (micb_mv - 1000) / 50;
  1414. }
  1415. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1416. /*
  1417. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1418. * @component: handle to snd_soc_component *
  1419. * @req_volt: micbias voltage to be set
  1420. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1421. *
  1422. * return 0 if adjustment is success or error code in case of failure
  1423. */
  1424. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1425. int req_volt, int micb_num)
  1426. {
  1427. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1428. int cur_vout_ctl, req_vout_ctl;
  1429. int micb_reg, micb_val, micb_en;
  1430. int ret = 0;
  1431. switch (micb_num) {
  1432. case MIC_BIAS_1:
  1433. micb_reg = WCD938X_ANA_MICB1;
  1434. break;
  1435. case MIC_BIAS_2:
  1436. micb_reg = WCD938X_ANA_MICB2;
  1437. break;
  1438. case MIC_BIAS_3:
  1439. micb_reg = WCD938X_ANA_MICB3;
  1440. break;
  1441. case MIC_BIAS_4:
  1442. micb_reg = WCD938X_ANA_MICB4;
  1443. break;
  1444. default:
  1445. return -EINVAL;
  1446. }
  1447. mutex_lock(&wcd938x->micb_lock);
  1448. /*
  1449. * If requested micbias voltage is same as current micbias
  1450. * voltage, then just return. Otherwise, adjust voltage as
  1451. * per requested value. If micbias is already enabled, then
  1452. * to avoid slow micbias ramp-up or down enable pull-up
  1453. * momentarily, change the micbias value and then re-enable
  1454. * micbias.
  1455. */
  1456. micb_val = snd_soc_component_read(component, micb_reg);
  1457. micb_en = (micb_val & 0xC0) >> 6;
  1458. cur_vout_ctl = micb_val & 0x3F;
  1459. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1460. if (req_vout_ctl < 0) {
  1461. ret = -EINVAL;
  1462. goto exit;
  1463. }
  1464. if (cur_vout_ctl == req_vout_ctl) {
  1465. ret = 0;
  1466. goto exit;
  1467. }
  1468. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1469. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1470. req_volt, micb_en);
  1471. if (micb_en == 0x1)
  1472. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1473. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1474. if (micb_en == 0x1) {
  1475. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1476. /*
  1477. * Add 2ms delay as per HW requirement after enabling
  1478. * micbias
  1479. */
  1480. usleep_range(2000, 2100);
  1481. }
  1482. exit:
  1483. mutex_unlock(&wcd938x->micb_lock);
  1484. return ret;
  1485. }
  1486. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1487. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1488. struct snd_kcontrol *kcontrol,
  1489. int event)
  1490. {
  1491. struct snd_soc_component *component =
  1492. snd_soc_dapm_to_component(w->dapm);
  1493. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1494. int ret = 0;
  1495. int bank = 0;
  1496. u8 mode = 0;
  1497. int i = 0;
  1498. int rate = 0;
  1499. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1500. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1501. /* power mode is applicable only to analog mics */
  1502. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1503. /* Get channel rate */
  1504. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1505. }
  1506. switch (event) {
  1507. case SND_SOC_DAPM_PRE_PMU:
  1508. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1509. if (w->shift == ADC2 && !(snd_soc_component_read(component,
  1510. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1511. if (!wcd938x->bcs_dis) {
  1512. wcd938x_tx_connect_port(component, MBHC,
  1513. SWR_CLK_RATE_4P8MHZ, true);
  1514. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1515. }
  1516. }
  1517. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1518. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1519. wcd938x_tx_connect_port(component, w->shift, rate,
  1520. true);
  1521. } else {
  1522. wcd938x_tx_connect_port(component, w->shift,
  1523. SWR_CLK_RATE_2P4MHZ, true);
  1524. }
  1525. break;
  1526. case SND_SOC_DAPM_POST_PMD:
  1527. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1528. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1529. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1530. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1531. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1532. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1533. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1534. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1535. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1536. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1537. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1538. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1539. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1540. }
  1541. }
  1542. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1543. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1544. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1545. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1546. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1547. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1548. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1549. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1550. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1551. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1552. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1553. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1554. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1555. if (mode != 0) {
  1556. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1557. if (mode & (1 << i)) {
  1558. i++;
  1559. break;
  1560. }
  1561. }
  1562. }
  1563. rate = wcd938x_get_clk_rate(i);
  1564. if (wcd938x->adc_count) {
  1565. rate = (wcd938x->adc_count * rate);
  1566. if (rate > SWR_CLK_RATE_9P6MHZ)
  1567. rate = SWR_CLK_RATE_9P6MHZ;
  1568. }
  1569. wcd938x_set_swr_clk_rate(component, rate, bank);
  1570. }
  1571. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1572. wcd938x->tx_swr_dev->dev_num,
  1573. false);
  1574. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1575. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1576. break;
  1577. };
  1578. return ret;
  1579. }
  1580. static int wcd938x_get_adc_mode(int val)
  1581. {
  1582. int ret = 0;
  1583. switch (val) {
  1584. case ADC_MODE_INVALID:
  1585. ret = ADC_MODE_VAL_NORMAL;
  1586. break;
  1587. case ADC_MODE_HIFI:
  1588. ret = ADC_MODE_VAL_HIFI;
  1589. break;
  1590. case ADC_MODE_LO_HIF:
  1591. ret = ADC_MODE_VAL_LO_HIF;
  1592. break;
  1593. case ADC_MODE_NORMAL:
  1594. ret = ADC_MODE_VAL_NORMAL;
  1595. break;
  1596. case ADC_MODE_LP:
  1597. ret = ADC_MODE_VAL_LP;
  1598. break;
  1599. case ADC_MODE_ULP1:
  1600. ret = ADC_MODE_VAL_ULP1;
  1601. break;
  1602. case ADC_MODE_ULP2:
  1603. ret = ADC_MODE_VAL_ULP2;
  1604. break;
  1605. default:
  1606. ret = -EINVAL;
  1607. pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
  1608. break;
  1609. }
  1610. return ret;
  1611. }
  1612. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1613. int channel, int mode)
  1614. {
  1615. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1616. int ret = 0;
  1617. switch (channel) {
  1618. case 0:
  1619. reg = WCD938X_ANA_TX_CH2;
  1620. mask = 0x40;
  1621. break;
  1622. case 1:
  1623. reg = WCD938X_ANA_TX_CH2;
  1624. mask = 0x20;
  1625. break;
  1626. case 2:
  1627. reg = WCD938X_ANA_TX_CH4;
  1628. mask = 0x40;
  1629. break;
  1630. case 3:
  1631. reg = WCD938X_ANA_TX_CH4;
  1632. mask = 0x20;
  1633. break;
  1634. default:
  1635. pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
  1636. ret = -EINVAL;
  1637. break;
  1638. }
  1639. if (!mode)
  1640. val = 0x00;
  1641. else
  1642. val = mask;
  1643. if (!ret)
  1644. snd_soc_component_update_bits(component, reg, mask, val);
  1645. return ret;
  1646. }
  1647. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1648. struct snd_kcontrol *kcontrol,
  1649. int event){
  1650. struct snd_soc_component *component =
  1651. snd_soc_dapm_to_component(w->dapm);
  1652. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1653. int clk_rate = 0, ret = 0;
  1654. int mode = 0, i = 0, bank = 0;
  1655. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1656. w->name, event);
  1657. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1658. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1659. switch (event) {
  1660. case SND_SOC_DAPM_PRE_PMU:
  1661. wcd938x->adc_count++;
  1662. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1663. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1664. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1665. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1666. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1667. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1668. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1669. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1670. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1671. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1672. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1673. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1674. if (mode != 0) {
  1675. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1676. if (mode & (1 << i)) {
  1677. i++;
  1678. break;
  1679. }
  1680. }
  1681. }
  1682. clk_rate = wcd938x_get_clk_rate(i);
  1683. /* clk_rate depends on number of paths getting enabled */
  1684. clk_rate = (wcd938x->adc_count * clk_rate);
  1685. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1686. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1687. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1688. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1689. wcd938x->tx_swr_dev->dev_num,
  1690. true);
  1691. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1692. break;
  1693. case SND_SOC_DAPM_POST_PMD:
  1694. wcd938x->adc_count--;
  1695. if (wcd938x->adc_count < 0)
  1696. wcd938x->adc_count = 0;
  1697. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1698. if (w->shift + ADC1 == ADC2 &&
  1699. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1700. wcd938x_tx_connect_port(component, MBHC, 0,
  1701. false);
  1702. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1703. }
  1704. break;
  1705. };
  1706. return ret;
  1707. }
  1708. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1709. bool bcs_disable)
  1710. {
  1711. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1712. if (wcd938x->update_wcd_event) {
  1713. if (bcs_disable)
  1714. wcd938x->update_wcd_event(wcd938x->handle,
  1715. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1716. else
  1717. wcd938x->update_wcd_event(wcd938x->handle,
  1718. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1719. }
  1720. }
  1721. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1722. struct snd_kcontrol *kcontrol, int event)
  1723. {
  1724. struct snd_soc_component *component =
  1725. snd_soc_dapm_to_component(w->dapm);
  1726. struct wcd938x_priv *wcd938x =
  1727. snd_soc_component_get_drvdata(component);
  1728. int ret = 0;
  1729. u8 mode = 0;
  1730. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1731. w->name, event);
  1732. switch (event) {
  1733. case SND_SOC_DAPM_PRE_PMU:
  1734. snd_soc_component_update_bits(component,
  1735. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1736. snd_soc_component_update_bits(component,
  1737. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1738. snd_soc_component_update_bits(component,
  1739. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1740. snd_soc_component_update_bits(component,
  1741. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1742. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1743. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1744. if (mode < 0) {
  1745. dev_info_ratelimited(component->dev,
  1746. "%s: invalid mode, setting to normal mode\n",
  1747. __func__);
  1748. mode = ADC_MODE_VAL_NORMAL;
  1749. }
  1750. switch (w->shift) {
  1751. case 0:
  1752. snd_soc_component_update_bits(component,
  1753. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1754. mode);
  1755. snd_soc_component_update_bits(component,
  1756. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1757. break;
  1758. case 1:
  1759. snd_soc_component_update_bits(component,
  1760. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1761. mode << 4);
  1762. snd_soc_component_update_bits(component,
  1763. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1764. break;
  1765. case 2:
  1766. snd_soc_component_update_bits(component,
  1767. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1768. mode);
  1769. snd_soc_component_update_bits(component,
  1770. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1771. break;
  1772. case 3:
  1773. snd_soc_component_update_bits(component,
  1774. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1775. mode << 4);
  1776. snd_soc_component_update_bits(component,
  1777. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1778. break;
  1779. default:
  1780. break;
  1781. }
  1782. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1783. break;
  1784. case SND_SOC_DAPM_POST_PMD:
  1785. switch (w->shift) {
  1786. case 0:
  1787. snd_soc_component_update_bits(component,
  1788. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1789. 0x00);
  1790. snd_soc_component_update_bits(component,
  1791. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1792. break;
  1793. case 1:
  1794. snd_soc_component_update_bits(component,
  1795. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1796. 0x00);
  1797. snd_soc_component_update_bits(component,
  1798. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1799. break;
  1800. case 2:
  1801. snd_soc_component_update_bits(component,
  1802. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1803. 0x00);
  1804. snd_soc_component_update_bits(component,
  1805. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1806. break;
  1807. case 3:
  1808. snd_soc_component_update_bits(component,
  1809. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1810. 0x00);
  1811. snd_soc_component_update_bits(component,
  1812. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1813. break;
  1814. default:
  1815. break;
  1816. }
  1817. if (wcd938x->adc_count == 0) {
  1818. snd_soc_component_update_bits(component,
  1819. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1820. snd_soc_component_update_bits(component,
  1821. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1822. }
  1823. break;
  1824. };
  1825. return ret;
  1826. }
  1827. int wcd938x_micbias_control(struct snd_soc_component *component,
  1828. int micb_num, int req, bool is_dapm)
  1829. {
  1830. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1831. int micb_index = micb_num - 1;
  1832. u16 micb_reg;
  1833. int pre_off_event = 0, post_off_event = 0;
  1834. int post_on_event = 0, post_dapm_off = 0;
  1835. int post_dapm_on = 0;
  1836. int ret = 0;
  1837. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1838. dev_err_ratelimited(component->dev,
  1839. "%s: Invalid micbias index, micb_ind:%d\n",
  1840. __func__, micb_index);
  1841. return -EINVAL;
  1842. }
  1843. if (NULL == wcd938x) {
  1844. dev_err_ratelimited(component->dev,
  1845. "%s: wcd938x private data is NULL\n", __func__);
  1846. return -EINVAL;
  1847. }
  1848. switch (micb_num) {
  1849. case MIC_BIAS_1:
  1850. micb_reg = WCD938X_ANA_MICB1;
  1851. break;
  1852. case MIC_BIAS_2:
  1853. micb_reg = WCD938X_ANA_MICB2;
  1854. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1855. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1856. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1857. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1858. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1859. break;
  1860. case MIC_BIAS_3:
  1861. micb_reg = WCD938X_ANA_MICB3;
  1862. break;
  1863. case MIC_BIAS_4:
  1864. micb_reg = WCD938X_ANA_MICB4;
  1865. break;
  1866. default:
  1867. dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
  1868. __func__, micb_num);
  1869. return -EINVAL;
  1870. };
  1871. mutex_lock(&wcd938x->micb_lock);
  1872. switch (req) {
  1873. case MICB_PULLUP_ENABLE:
  1874. if (!wcd938x->dev_up) {
  1875. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1876. __func__, req);
  1877. ret = -ENODEV;
  1878. goto done;
  1879. }
  1880. wcd938x->pullup_ref[micb_index]++;
  1881. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1882. (wcd938x->micb_ref[micb_index] == 0))
  1883. snd_soc_component_update_bits(component, micb_reg,
  1884. 0xC0, 0x80);
  1885. break;
  1886. case MICB_PULLUP_DISABLE:
  1887. if (wcd938x->pullup_ref[micb_index] > 0)
  1888. wcd938x->pullup_ref[micb_index]--;
  1889. if (!wcd938x->dev_up) {
  1890. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1891. __func__, req);
  1892. ret = -ENODEV;
  1893. goto done;
  1894. }
  1895. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1896. (wcd938x->micb_ref[micb_index] == 0))
  1897. snd_soc_component_update_bits(component, micb_reg,
  1898. 0xC0, 0x00);
  1899. break;
  1900. case MICB_ENABLE:
  1901. if (!wcd938x->dev_up) {
  1902. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1903. __func__, req);
  1904. ret = -ENODEV;
  1905. goto done;
  1906. }
  1907. wcd938x->micb_ref[micb_index]++;
  1908. if (wcd938x->micb_ref[micb_index] == 1) {
  1909. snd_soc_component_update_bits(component,
  1910. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1911. snd_soc_component_update_bits(component,
  1912. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1913. snd_soc_component_update_bits(component,
  1914. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1915. snd_soc_component_update_bits(component,
  1916. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1917. snd_soc_component_update_bits(component,
  1918. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1919. snd_soc_component_update_bits(component,
  1920. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1921. snd_soc_component_update_bits(component,
  1922. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1923. snd_soc_component_update_bits(component,
  1924. micb_reg, 0xC0, 0x40);
  1925. if (post_on_event)
  1926. blocking_notifier_call_chain(
  1927. &wcd938x->mbhc->notifier,
  1928. post_on_event,
  1929. &wcd938x->mbhc->wcd_mbhc);
  1930. }
  1931. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1932. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1933. post_dapm_on,
  1934. &wcd938x->mbhc->wcd_mbhc);
  1935. break;
  1936. case MICB_DISABLE:
  1937. if (wcd938x->micb_ref[micb_index] > 0)
  1938. wcd938x->micb_ref[micb_index]--;
  1939. if (!wcd938x->dev_up) {
  1940. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1941. __func__, req);
  1942. ret = -ENODEV;
  1943. goto done;
  1944. }
  1945. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1946. (wcd938x->pullup_ref[micb_index] > 0))
  1947. snd_soc_component_update_bits(component, micb_reg,
  1948. 0xC0, 0x80);
  1949. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1950. (wcd938x->pullup_ref[micb_index] == 0)) {
  1951. if (pre_off_event && wcd938x->mbhc)
  1952. blocking_notifier_call_chain(
  1953. &wcd938x->mbhc->notifier,
  1954. pre_off_event,
  1955. &wcd938x->mbhc->wcd_mbhc);
  1956. snd_soc_component_update_bits(component, micb_reg,
  1957. 0xC0, 0x00);
  1958. if (post_off_event && wcd938x->mbhc)
  1959. blocking_notifier_call_chain(
  1960. &wcd938x->mbhc->notifier,
  1961. post_off_event,
  1962. &wcd938x->mbhc->wcd_mbhc);
  1963. }
  1964. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1965. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1966. post_dapm_off,
  1967. &wcd938x->mbhc->wcd_mbhc);
  1968. break;
  1969. };
  1970. dev_dbg(component->dev,
  1971. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1972. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1973. wcd938x->pullup_ref[micb_index]);
  1974. done:
  1975. mutex_unlock(&wcd938x->micb_lock);
  1976. return ret;
  1977. }
  1978. EXPORT_SYMBOL(wcd938x_micbias_control);
  1979. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1980. {
  1981. int ret = 0;
  1982. uint8_t devnum = 0;
  1983. int num_retry = NUM_ATTEMPTS;
  1984. do {
  1985. /* retry after 1ms */
  1986. usleep_range(1000, 1010);
  1987. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1988. } while (ret && --num_retry);
  1989. if (ret)
  1990. dev_err_ratelimited(&swr_dev->dev,
  1991. "%s get devnum %d for dev addr %llx failed\n",
  1992. __func__, devnum, swr_dev->addr);
  1993. swr_dev->dev_num = devnum;
  1994. return 0;
  1995. }
  1996. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1997. struct wcd_mbhc_config *mbhc_cfg)
  1998. {
  1999. if (mbhc_cfg->enable_usbc_analog) {
  2000. if (!(snd_soc_component_read(component, WCD938X_ANA_MBHC_MECH)
  2001. & 0x20))
  2002. return true;
  2003. }
  2004. return false;
  2005. }
  2006. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  2007. struct notifier_block *nblock,
  2008. bool enable)
  2009. {
  2010. struct wcd938x_priv *wcd938x_priv;
  2011. if(NULL == component) {
  2012. pr_err_ratelimited("%s: wcd938x component is NULL\n", __func__);
  2013. return -EINVAL;
  2014. }
  2015. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2016. wcd938x_priv->notify_swr_dmic = enable;
  2017. if (enable)
  2018. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  2019. nblock);
  2020. else
  2021. return blocking_notifier_chain_unregister(
  2022. &wcd938x_priv->notifier, nblock);
  2023. }
  2024. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  2025. static int wcd938x_event_notify(struct notifier_block *block,
  2026. unsigned long val,
  2027. void *data)
  2028. {
  2029. u16 event = (val & 0xffff);
  2030. int ret = 0;
  2031. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  2032. struct snd_soc_component *component = wcd938x->component;
  2033. struct wcd_mbhc *mbhc;
  2034. switch (event) {
  2035. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2036. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  2037. snd_soc_component_update_bits(component,
  2038. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  2039. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  2040. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  2041. }
  2042. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  2043. snd_soc_component_update_bits(component,
  2044. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  2045. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  2046. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  2047. }
  2048. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  2049. snd_soc_component_update_bits(component,
  2050. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  2051. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  2052. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  2053. }
  2054. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  2055. snd_soc_component_update_bits(component,
  2056. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  2057. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  2058. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  2059. }
  2060. break;
  2061. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2062. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  2063. 0xC0, 0x00);
  2064. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  2065. 0x80, 0x00);
  2066. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  2067. 0x80, 0x00);
  2068. break;
  2069. case BOLERO_SLV_EVT_SSR_DOWN:
  2070. wcd938x->dev_up = false;
  2071. if(wcd938x->notify_swr_dmic)
  2072. blocking_notifier_call_chain(&wcd938x->notifier,
  2073. WCD938X_EVT_SSR_DOWN,
  2074. NULL);
  2075. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2076. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2077. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  2078. mbhc->mbhc_cfg);
  2079. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  2080. wcd938x_reset_low(wcd938x->dev);
  2081. break;
  2082. case BOLERO_SLV_EVT_SSR_UP:
  2083. wcd938x_reset(wcd938x->dev);
  2084. /* allow reset to take effect */
  2085. usleep_range(10000, 10010);
  2086. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2087. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2088. wcd938x_init_reg(component);
  2089. regcache_mark_dirty(wcd938x->regmap);
  2090. regcache_sync(wcd938x->regmap);
  2091. /* Initialize MBHC module */
  2092. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2093. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2094. if (ret) {
  2095. dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
  2096. __func__);
  2097. } else {
  2098. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2099. }
  2100. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2101. wcd938x->dev_up = true;
  2102. if(wcd938x->notify_swr_dmic)
  2103. blocking_notifier_call_chain(&wcd938x->notifier,
  2104. WCD938X_EVT_SSR_UP,
  2105. NULL);
  2106. if (wcd938x->usbc_hs_status)
  2107. mdelay(500);
  2108. break;
  2109. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2110. snd_soc_component_update_bits(component,
  2111. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2112. ((val >> 0x10) << 0x01));
  2113. break;
  2114. default:
  2115. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2116. break;
  2117. }
  2118. return 0;
  2119. }
  2120. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2121. int event)
  2122. {
  2123. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2124. int micb_num;
  2125. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2126. __func__, w->name, event);
  2127. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2128. micb_num = MIC_BIAS_1;
  2129. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2130. micb_num = MIC_BIAS_2;
  2131. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2132. micb_num = MIC_BIAS_3;
  2133. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2134. micb_num = MIC_BIAS_4;
  2135. else
  2136. return -EINVAL;
  2137. switch (event) {
  2138. case SND_SOC_DAPM_PRE_PMU:
  2139. wcd938x_micbias_control(component, micb_num,
  2140. MICB_ENABLE, true);
  2141. break;
  2142. case SND_SOC_DAPM_POST_PMU:
  2143. /* 1 msec delay as per HW requirement */
  2144. usleep_range(1000, 1100);
  2145. break;
  2146. case SND_SOC_DAPM_POST_PMD:
  2147. wcd938x_micbias_control(component, micb_num,
  2148. MICB_DISABLE, true);
  2149. break;
  2150. };
  2151. return 0;
  2152. }
  2153. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2154. struct snd_kcontrol *kcontrol,
  2155. int event)
  2156. {
  2157. return __wcd938x_codec_enable_micbias(w, event);
  2158. }
  2159. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2160. int event)
  2161. {
  2162. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2163. int micb_num;
  2164. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2165. __func__, w->name, event);
  2166. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2167. micb_num = MIC_BIAS_1;
  2168. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2169. micb_num = MIC_BIAS_2;
  2170. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2171. micb_num = MIC_BIAS_3;
  2172. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2173. micb_num = MIC_BIAS_4;
  2174. else
  2175. return -EINVAL;
  2176. switch (event) {
  2177. case SND_SOC_DAPM_PRE_PMU:
  2178. wcd938x_micbias_control(component, micb_num,
  2179. MICB_PULLUP_ENABLE, true);
  2180. break;
  2181. case SND_SOC_DAPM_POST_PMU:
  2182. /* 1 msec delay as per HW requirement */
  2183. usleep_range(1000, 1100);
  2184. break;
  2185. case SND_SOC_DAPM_POST_PMD:
  2186. wcd938x_micbias_control(component, micb_num,
  2187. MICB_PULLUP_DISABLE, true);
  2188. break;
  2189. };
  2190. return 0;
  2191. }
  2192. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2193. struct snd_kcontrol *kcontrol,
  2194. int event)
  2195. {
  2196. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2197. }
  2198. static int wcd938x_wakeup(void *handle, bool enable)
  2199. {
  2200. struct wcd938x_priv *priv;
  2201. int ret = 0;
  2202. if (!handle) {
  2203. pr_err_ratelimited("%s: NULL handle\n", __func__);
  2204. return -EINVAL;
  2205. }
  2206. priv = (struct wcd938x_priv *)handle;
  2207. if (!priv->tx_swr_dev) {
  2208. pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
  2209. return -EINVAL;
  2210. }
  2211. mutex_lock(&priv->wakeup_lock);
  2212. if (enable)
  2213. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2214. else
  2215. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2216. mutex_unlock(&priv->wakeup_lock);
  2217. return ret;
  2218. }
  2219. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2220. struct snd_kcontrol *kcontrol,
  2221. int event)
  2222. {
  2223. int ret = 0;
  2224. struct snd_soc_component *component =
  2225. snd_soc_dapm_to_component(w->dapm);
  2226. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2227. switch (event) {
  2228. case SND_SOC_DAPM_PRE_PMU:
  2229. wcd938x_wakeup(wcd938x, true);
  2230. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2231. wcd938x_wakeup(wcd938x, false);
  2232. break;
  2233. case SND_SOC_DAPM_POST_PMD:
  2234. wcd938x_wakeup(wcd938x, true);
  2235. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2236. wcd938x_wakeup(wcd938x, false);
  2237. break;
  2238. }
  2239. return ret;
  2240. }
  2241. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2242. int micb_num, int req)
  2243. {
  2244. int micb_index = micb_num - 1;
  2245. u16 micb_reg;
  2246. if (NULL == wcd938x) {
  2247. pr_err_ratelimited("%s: wcd938x private data is NULL\n", __func__);
  2248. return -EINVAL;
  2249. }
  2250. switch (micb_num) {
  2251. case MIC_BIAS_1:
  2252. micb_reg = WCD938X_ANA_MICB1;
  2253. break;
  2254. case MIC_BIAS_2:
  2255. micb_reg = WCD938X_ANA_MICB2;
  2256. break;
  2257. case MIC_BIAS_3:
  2258. micb_reg = WCD938X_ANA_MICB3;
  2259. break;
  2260. case MIC_BIAS_4:
  2261. micb_reg = WCD938X_ANA_MICB4;
  2262. break;
  2263. default:
  2264. pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2265. return -EINVAL;
  2266. };
  2267. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2268. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2269. wcd938x->pullup_ref[micb_index]);
  2270. mutex_lock(&wcd938x->micb_lock);
  2271. switch (req) {
  2272. case MICB_ENABLE:
  2273. wcd938x->micb_ref[micb_index]++;
  2274. if (wcd938x->micb_ref[micb_index] == 1) {
  2275. regmap_update_bits(wcd938x->regmap,
  2276. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2277. regmap_update_bits(wcd938x->regmap,
  2278. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2279. regmap_update_bits(wcd938x->regmap,
  2280. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2281. regmap_update_bits(wcd938x->regmap,
  2282. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2283. regmap_update_bits(wcd938x->regmap,
  2284. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2285. regmap_update_bits(wcd938x->regmap,
  2286. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2287. regmap_update_bits(wcd938x->regmap,
  2288. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2289. regmap_update_bits(wcd938x->regmap,
  2290. micb_reg, 0xC0, 0x40);
  2291. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2292. }
  2293. break;
  2294. case MICB_PULLUP_ENABLE:
  2295. wcd938x->pullup_ref[micb_index]++;
  2296. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2297. (wcd938x->micb_ref[micb_index] == 0))
  2298. regmap_update_bits(wcd938x->regmap, micb_reg,
  2299. 0xC0, 0x80);
  2300. break;
  2301. case MICB_PULLUP_DISABLE:
  2302. if (wcd938x->pullup_ref[micb_index] > 0)
  2303. wcd938x->pullup_ref[micb_index]--;
  2304. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2305. (wcd938x->micb_ref[micb_index] == 0))
  2306. regmap_update_bits(wcd938x->regmap, micb_reg,
  2307. 0xC0, 0x00);
  2308. break;
  2309. case MICB_DISABLE:
  2310. if (wcd938x->micb_ref[micb_index] > 0)
  2311. wcd938x->micb_ref[micb_index]--;
  2312. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2313. (wcd938x->pullup_ref[micb_index] > 0))
  2314. regmap_update_bits(wcd938x->regmap, micb_reg,
  2315. 0xC0, 0x80);
  2316. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2317. (wcd938x->pullup_ref[micb_index] == 0))
  2318. regmap_update_bits(wcd938x->regmap, micb_reg,
  2319. 0xC0, 0x00);
  2320. break;
  2321. };
  2322. mutex_unlock(&wcd938x->micb_lock);
  2323. return 0;
  2324. }
  2325. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2326. int event, int micb_num)
  2327. {
  2328. struct wcd938x_priv *wcd938x_priv = NULL;
  2329. int ret = 0;
  2330. int micb_index = micb_num - 1;
  2331. if(NULL == component) {
  2332. pr_err_ratelimited("%s: wcd938x component is NULL\n", __func__);
  2333. return -EINVAL;
  2334. }
  2335. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2336. pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
  2337. return -EINVAL;
  2338. }
  2339. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2340. pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2341. return -EINVAL;
  2342. }
  2343. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2344. if (!wcd938x_priv->dev_up) {
  2345. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2346. (event == SND_SOC_DAPM_POST_PMD)) {
  2347. wcd938x_priv->pullup_ref[micb_index]--;
  2348. ret = -ENODEV;
  2349. goto done;
  2350. }
  2351. }
  2352. switch (event) {
  2353. case SND_SOC_DAPM_PRE_PMU:
  2354. wcd938x_wakeup(wcd938x_priv, true);
  2355. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2356. wcd938x_wakeup(wcd938x_priv, false);
  2357. break;
  2358. case SND_SOC_DAPM_POST_PMD:
  2359. wcd938x_wakeup(wcd938x_priv, true);
  2360. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2361. wcd938x_wakeup(wcd938x_priv, false);
  2362. break;
  2363. }
  2364. done:
  2365. return ret;
  2366. }
  2367. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2368. static inline int wcd938x_tx_path_get(const char *wname,
  2369. unsigned int *path_num)
  2370. {
  2371. int ret = 0;
  2372. char *widget_name = NULL;
  2373. char *w_name = NULL;
  2374. char *path_num_char = NULL;
  2375. char *path_name = NULL;
  2376. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2377. if (!widget_name)
  2378. return -EINVAL;
  2379. w_name = widget_name;
  2380. path_name = strsep(&widget_name, " ");
  2381. if (!path_name) {
  2382. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  2383. __func__, widget_name);
  2384. ret = -EINVAL;
  2385. goto err;
  2386. }
  2387. path_num_char = strpbrk(path_name, "0123");
  2388. if (!path_num_char) {
  2389. pr_err_ratelimited("%s: tx path index not found\n",
  2390. __func__);
  2391. ret = -EINVAL;
  2392. goto err;
  2393. }
  2394. ret = kstrtouint(path_num_char, 10, path_num);
  2395. if (ret < 0)
  2396. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  2397. __func__, w_name);
  2398. err:
  2399. kfree(w_name);
  2400. return ret;
  2401. }
  2402. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2403. struct snd_ctl_elem_value *ucontrol)
  2404. {
  2405. struct snd_soc_component *component =
  2406. snd_soc_kcontrol_component(kcontrol);
  2407. struct wcd938x_priv *wcd938x = NULL;
  2408. int ret = 0;
  2409. unsigned int path = 0;
  2410. if (!component)
  2411. return -EINVAL;
  2412. wcd938x = snd_soc_component_get_drvdata(component);
  2413. if (!wcd938x)
  2414. return -EINVAL;
  2415. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2416. if (ret < 0)
  2417. return ret;
  2418. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2419. return 0;
  2420. }
  2421. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2422. struct snd_ctl_elem_value *ucontrol)
  2423. {
  2424. struct snd_soc_component *component =
  2425. snd_soc_kcontrol_component(kcontrol);
  2426. struct wcd938x_priv *wcd938x = NULL;
  2427. u32 mode_val;
  2428. unsigned int path = 0;
  2429. int ret = 0;
  2430. if (!component)
  2431. return -EINVAL;
  2432. wcd938x = snd_soc_component_get_drvdata(component);
  2433. if (!wcd938x)
  2434. return -EINVAL;
  2435. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2436. if (ret)
  2437. return ret;
  2438. mode_val = ucontrol->value.enumerated.item[0];
  2439. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2440. wcd938x->tx_mode[path] = mode_val;
  2441. return 0;
  2442. }
  2443. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2444. struct snd_ctl_elem_value *ucontrol)
  2445. {
  2446. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2447. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2448. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2449. return 0;
  2450. }
  2451. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2452. struct snd_ctl_elem_value *ucontrol)
  2453. {
  2454. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2455. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2456. u32 mode_val;
  2457. mode_val = ucontrol->value.enumerated.item[0];
  2458. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2459. if (wcd938x->variant == WCD9380) {
  2460. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2461. dev_info_ratelimited(component->dev,
  2462. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2463. __func__);
  2464. mode_val = CLS_H_ULP;
  2465. }
  2466. }
  2467. if (mode_val == CLS_H_NORMAL) {
  2468. dev_info_ratelimited(component->dev,
  2469. "%s:Invalid HPH Mode, default to class_AB\n",
  2470. __func__);
  2471. mode_val = CLS_H_ULP;
  2472. }
  2473. wcd938x->hph_mode = mode_val;
  2474. return 0;
  2475. }
  2476. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2477. struct snd_ctl_elem_value *ucontrol)
  2478. {
  2479. u8 ear_pa_gain = 0;
  2480. struct snd_soc_component *component =
  2481. snd_soc_kcontrol_component(kcontrol);
  2482. ear_pa_gain = snd_soc_component_read(component,
  2483. WCD938X_ANA_EAR_COMPANDER_CTL);
  2484. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2485. ucontrol->value.integer.value[0] = ear_pa_gain;
  2486. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2487. ear_pa_gain);
  2488. return 0;
  2489. }
  2490. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2491. struct snd_ctl_elem_value *ucontrol)
  2492. {
  2493. u8 ear_pa_gain = 0;
  2494. struct snd_soc_component *component =
  2495. snd_soc_kcontrol_component(kcontrol);
  2496. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2497. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2498. __func__, ucontrol->value.integer.value[0]);
  2499. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2500. if (!wcd938x->comp1_enable) {
  2501. snd_soc_component_update_bits(component,
  2502. WCD938X_ANA_EAR_COMPANDER_CTL,
  2503. 0x7C, ear_pa_gain);
  2504. }
  2505. return 0;
  2506. }
  2507. /* wcd938x_codec_get_dev_num - returns swr device number
  2508. * @component: Codec instance
  2509. *
  2510. * Return: swr device number on success or negative error
  2511. * code on failure.
  2512. */
  2513. int wcd938x_codec_get_dev_num(struct snd_soc_component *component)
  2514. {
  2515. struct wcd938x_priv *wcd938x;
  2516. if (!component)
  2517. return -EINVAL;
  2518. wcd938x = snd_soc_component_get_drvdata(component);
  2519. if (!wcd938x || !wcd938x->rx_swr_dev) {
  2520. pr_err_ratelimited("%s: wcd938x component is NULL\n", __func__);
  2521. return -EINVAL;
  2522. }
  2523. return wcd938x->rx_swr_dev->dev_num;
  2524. }
  2525. EXPORT_SYMBOL(wcd938x_codec_get_dev_num);
  2526. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2527. struct snd_ctl_elem_value *ucontrol)
  2528. {
  2529. struct snd_soc_component *component =
  2530. snd_soc_kcontrol_component(kcontrol);
  2531. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2532. bool hphr;
  2533. struct soc_multi_mixer_control *mc;
  2534. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2535. hphr = mc->shift;
  2536. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2537. wcd938x->comp1_enable;
  2538. return 0;
  2539. }
  2540. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2541. struct snd_ctl_elem_value *ucontrol)
  2542. {
  2543. struct snd_soc_component *component =
  2544. snd_soc_kcontrol_component(kcontrol);
  2545. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2546. int value = ucontrol->value.integer.value[0];
  2547. bool hphr;
  2548. struct soc_multi_mixer_control *mc;
  2549. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2550. hphr = mc->shift;
  2551. if (hphr)
  2552. wcd938x->comp2_enable = value;
  2553. else
  2554. wcd938x->comp1_enable = value;
  2555. return 0;
  2556. }
  2557. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2558. struct snd_kcontrol *kcontrol,
  2559. int event)
  2560. {
  2561. struct snd_soc_component *component =
  2562. snd_soc_dapm_to_component(w->dapm);
  2563. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2564. struct wcd938x_pdata *pdata = NULL;
  2565. int ret = 0;
  2566. pdata = dev_get_platdata(wcd938x->dev);
  2567. if (!pdata) {
  2568. dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
  2569. return -EINVAL;
  2570. }
  2571. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2572. wcd938x->supplies,
  2573. pdata->regulator,
  2574. pdata->num_supplies,
  2575. "cdc-vdd-buck"))
  2576. return 0;
  2577. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2578. w->name, event);
  2579. switch (event) {
  2580. case SND_SOC_DAPM_PRE_PMU:
  2581. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2582. dev_dbg(component->dev,
  2583. "%s: buck already in enabled state\n",
  2584. __func__);
  2585. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2586. return 0;
  2587. }
  2588. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2589. wcd938x->supplies,
  2590. pdata->regulator,
  2591. pdata->num_supplies,
  2592. "cdc-vdd-buck");
  2593. if (ret == -EINVAL) {
  2594. dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
  2595. __func__);
  2596. return ret;
  2597. }
  2598. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2599. /*
  2600. * 200us sleep is required after LDO is enabled as per
  2601. * HW requirement
  2602. */
  2603. usleep_range(200, 250);
  2604. break;
  2605. case SND_SOC_DAPM_POST_PMD:
  2606. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2607. break;
  2608. }
  2609. return 0;
  2610. }
  2611. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2612. struct snd_ctl_elem_value *ucontrol)
  2613. {
  2614. struct snd_soc_component *component =
  2615. snd_soc_kcontrol_component(kcontrol);
  2616. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2617. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2618. return 0;
  2619. }
  2620. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2621. struct snd_ctl_elem_value *ucontrol)
  2622. {
  2623. struct snd_soc_component *component =
  2624. snd_soc_kcontrol_component(kcontrol);
  2625. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2626. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2627. return 0;
  2628. }
  2629. const char * const tx_master_ch_text[] = {
  2630. "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
  2631. "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
  2632. "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
  2633. "SWRM_TX3_CH4", "SWRM_PCM_IN",
  2634. };
  2635. const struct soc_enum tx_master_ch_enum =
  2636. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2637. tx_master_ch_text);
  2638. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2639. {
  2640. u8 ch_type = 0;
  2641. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2642. ch_type = ADC1;
  2643. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2644. ch_type = ADC2;
  2645. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2646. ch_type = ADC3;
  2647. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2648. ch_type = ADC4;
  2649. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2650. ch_type = DMIC0;
  2651. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2652. ch_type = DMIC1;
  2653. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2654. ch_type = MBHC;
  2655. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2656. ch_type = DMIC2;
  2657. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2658. ch_type = DMIC3;
  2659. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2660. ch_type = DMIC4;
  2661. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2662. ch_type = DMIC5;
  2663. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2664. ch_type = DMIC6;
  2665. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2666. ch_type = DMIC7;
  2667. else
  2668. pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
  2669. if (ch_type)
  2670. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2671. else
  2672. *ch_idx = -EINVAL;
  2673. }
  2674. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2675. struct snd_ctl_elem_value *ucontrol)
  2676. {
  2677. struct snd_soc_component *component =
  2678. snd_soc_kcontrol_component(kcontrol);
  2679. struct wcd938x_priv *wcd938x = NULL;
  2680. int slave_ch_idx = -EINVAL;
  2681. if (component == NULL)
  2682. return -EINVAL;
  2683. wcd938x = snd_soc_component_get_drvdata(component);
  2684. if (wcd938x == NULL)
  2685. return -EINVAL;
  2686. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2687. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2688. return -EINVAL;
  2689. ucontrol->value.integer.value[0] = wcd938x_slave_get_master_ch_val(
  2690. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2691. return 0;
  2692. }
  2693. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2694. struct snd_ctl_elem_value *ucontrol)
  2695. {
  2696. struct snd_soc_component *component =
  2697. snd_soc_kcontrol_component(kcontrol);
  2698. struct wcd938x_priv *wcd938x = NULL;
  2699. int slave_ch_idx = -EINVAL, idx = 0;
  2700. if (component == NULL)
  2701. return -EINVAL;
  2702. wcd938x = snd_soc_component_get_drvdata(component);
  2703. if (wcd938x == NULL)
  2704. return -EINVAL;
  2705. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2706. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2707. return -EINVAL;
  2708. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2709. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2710. __func__, ucontrol->value.enumerated.item[0]);
  2711. idx = ucontrol->value.enumerated.item[0];
  2712. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  2713. return -EINVAL;
  2714. wcd938x->tx_master_ch_map[slave_ch_idx] = wcd938x_slave_get_master_ch(idx);
  2715. return 0;
  2716. }
  2717. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2718. struct snd_ctl_elem_value *ucontrol)
  2719. {
  2720. struct snd_soc_component *component =
  2721. snd_soc_kcontrol_component(kcontrol);
  2722. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2723. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2724. return 0;
  2725. }
  2726. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2727. struct snd_ctl_elem_value *ucontrol)
  2728. {
  2729. struct snd_soc_component *component =
  2730. snd_soc_kcontrol_component(kcontrol);
  2731. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2732. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2733. return 0;
  2734. }
  2735. static const char * const tx_mode_mux_text_wcd9380[] = {
  2736. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2737. };
  2738. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2739. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2740. tx_mode_mux_text_wcd9380);
  2741. static const char * const tx_mode_mux_text[] = {
  2742. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2743. "ADC_ULP1", "ADC_ULP2",
  2744. };
  2745. static const struct soc_enum tx_mode_mux_enum =
  2746. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2747. tx_mode_mux_text);
  2748. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2749. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2750. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2751. "CLS_AB_LOHIFI",
  2752. };
  2753. static const char * const wcd938x_ear_pa_gain_text[] = {
  2754. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2755. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2756. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2757. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2758. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2759. };
  2760. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2761. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2762. rx_hph_mode_mux_text_wcd9380);
  2763. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2764. wcd938x_ear_pa_gain_text);
  2765. static const char * const rx_hph_mode_mux_text[] = {
  2766. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2767. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2768. };
  2769. static const struct soc_enum rx_hph_mode_mux_enum =
  2770. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2771. rx_hph_mode_mux_text);
  2772. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2773. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2774. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2775. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2776. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2777. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2778. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2779. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2780. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2781. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2782. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2783. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2784. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2785. };
  2786. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2787. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2788. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2789. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2790. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2791. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2792. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2793. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2794. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2795. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2796. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2797. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2798. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2799. };
  2800. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2801. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2802. wcd938x_get_compander, wcd938x_set_compander),
  2803. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2804. wcd938x_get_compander, wcd938x_set_compander),
  2805. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2806. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2807. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2808. wcd938x_bcs_get, wcd938x_bcs_put),
  2809. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2810. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2811. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2812. analog_gain),
  2813. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2814. analog_gain),
  2815. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2816. analog_gain),
  2817. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2818. analog_gain),
  2819. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2820. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2821. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2822. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2823. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2824. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2825. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2826. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2827. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2828. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2829. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2830. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2831. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2832. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2833. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2834. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2835. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2836. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2837. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2838. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2839. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2840. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2841. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2842. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2843. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2844. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2845. };
  2846. static const struct snd_kcontrol_new adc1_switch[] = {
  2847. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2848. };
  2849. static const struct snd_kcontrol_new adc2_switch[] = {
  2850. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2851. };
  2852. static const struct snd_kcontrol_new adc3_switch[] = {
  2853. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2854. };
  2855. static const struct snd_kcontrol_new adc4_switch[] = {
  2856. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2857. };
  2858. static const struct snd_kcontrol_new amic1_switch[] = {
  2859. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2860. };
  2861. static const struct snd_kcontrol_new amic2_switch[] = {
  2862. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2863. };
  2864. static const struct snd_kcontrol_new amic3_switch[] = {
  2865. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2866. };
  2867. static const struct snd_kcontrol_new amic4_switch[] = {
  2868. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2869. };
  2870. static const struct snd_kcontrol_new amic5_switch[] = {
  2871. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2872. };
  2873. static const struct snd_kcontrol_new amic6_switch[] = {
  2874. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2875. };
  2876. static const struct snd_kcontrol_new amic7_switch[] = {
  2877. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2878. };
  2879. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2880. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2881. };
  2882. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2883. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2884. };
  2885. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2886. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2887. };
  2888. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2890. };
  2891. static const struct snd_kcontrol_new va_amic5_switch[] = {
  2892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2893. };
  2894. static const struct snd_kcontrol_new va_amic6_switch[] = {
  2895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2896. };
  2897. static const struct snd_kcontrol_new va_amic7_switch[] = {
  2898. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2899. };
  2900. static const struct snd_kcontrol_new dmic1_switch[] = {
  2901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2902. };
  2903. static const struct snd_kcontrol_new dmic2_switch[] = {
  2904. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2905. };
  2906. static const struct snd_kcontrol_new dmic3_switch[] = {
  2907. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2908. };
  2909. static const struct snd_kcontrol_new dmic4_switch[] = {
  2910. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2911. };
  2912. static const struct snd_kcontrol_new dmic5_switch[] = {
  2913. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2914. };
  2915. static const struct snd_kcontrol_new dmic6_switch[] = {
  2916. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2917. };
  2918. static const struct snd_kcontrol_new dmic7_switch[] = {
  2919. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2920. };
  2921. static const struct snd_kcontrol_new dmic8_switch[] = {
  2922. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2923. };
  2924. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2925. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2926. };
  2927. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2928. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2929. };
  2930. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2931. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2932. };
  2933. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2934. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2935. };
  2936. static const char * const adc2_mux_text[] = {
  2937. "INP2", "INP3"
  2938. };
  2939. static const struct soc_enum adc2_enum =
  2940. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2941. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2942. static const struct snd_kcontrol_new tx_adc2_mux =
  2943. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2944. static const char * const adc3_mux_text[] = {
  2945. "INP4", "INP6"
  2946. };
  2947. static const struct soc_enum adc3_enum =
  2948. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2949. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2950. static const struct snd_kcontrol_new tx_adc3_mux =
  2951. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2952. static const char * const adc4_mux_text[] = {
  2953. "INP5", "INP7"
  2954. };
  2955. static const struct soc_enum adc4_enum =
  2956. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2957. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2958. static const struct snd_kcontrol_new tx_adc4_mux =
  2959. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2960. static const char * const rdac3_mux_text[] = {
  2961. "RX1", "RX3"
  2962. };
  2963. static const char * const hdr12_mux_text[] = {
  2964. "NO_HDR12", "HDR12"
  2965. };
  2966. static const struct soc_enum hdr12_enum =
  2967. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2968. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2969. static const struct snd_kcontrol_new tx_hdr12_mux =
  2970. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2971. static const char * const hdr34_mux_text[] = {
  2972. "NO_HDR34", "HDR34"
  2973. };
  2974. static const struct soc_enum hdr34_enum =
  2975. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2976. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2977. static const struct snd_kcontrol_new tx_hdr34_mux =
  2978. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2979. static const struct soc_enum rdac3_enum =
  2980. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2981. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2982. static const struct snd_kcontrol_new rx_rdac3_mux =
  2983. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2984. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2985. /*input widgets*/
  2986. SND_SOC_DAPM_INPUT("AMIC1"),
  2987. SND_SOC_DAPM_INPUT("AMIC2"),
  2988. SND_SOC_DAPM_INPUT("AMIC3"),
  2989. SND_SOC_DAPM_INPUT("AMIC4"),
  2990. SND_SOC_DAPM_INPUT("AMIC5"),
  2991. SND_SOC_DAPM_INPUT("AMIC6"),
  2992. SND_SOC_DAPM_INPUT("AMIC7"),
  2993. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2994. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2995. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2996. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2997. SND_SOC_DAPM_INPUT("VA AMIC5"),
  2998. SND_SOC_DAPM_INPUT("VA AMIC6"),
  2999. SND_SOC_DAPM_INPUT("VA AMIC7"),
  3000. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  3001. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  3002. SND_SOC_DAPM_INPUT("IN3_AUX"),
  3003. /*
  3004. * These dummy widgets are null connected to WCD938x dapm input and
  3005. * output widgets which are not actual path endpoints. This ensures
  3006. * dapm doesnt set these dapm input and output widgets as endpoints.
  3007. */
  3008. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  3009. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  3010. /*tx widgets*/
  3011. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  3012. wcd938x_codec_enable_adc,
  3013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3014. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  3015. wcd938x_codec_enable_adc,
  3016. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3017. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  3018. wcd938x_codec_enable_adc,
  3019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3020. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3021. wcd938x_codec_enable_adc,
  3022. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3023. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3024. wcd938x_codec_enable_dmic,
  3025. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3026. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3027. wcd938x_codec_enable_dmic,
  3028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3029. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3030. wcd938x_codec_enable_dmic,
  3031. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3032. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3033. wcd938x_codec_enable_dmic,
  3034. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3035. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3036. wcd938x_codec_enable_dmic,
  3037. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3038. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3039. wcd938x_codec_enable_dmic,
  3040. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3041. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3042. wcd938x_codec_enable_dmic,
  3043. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3044. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3045. wcd938x_codec_enable_dmic,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3047. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3048. NULL, 0, wcd938x_enable_req,
  3049. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3050. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3051. NULL, 0, wcd938x_enable_req,
  3052. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3053. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3054. NULL, 0, wcd938x_enable_req,
  3055. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3056. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3057. NULL, 0, wcd938x_enable_req,
  3058. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3059. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3060. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3061. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3062. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3063. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3064. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3065. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3066. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3067. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3068. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3069. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3070. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3071. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3072. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3074. SND_SOC_DAPM_MIXER_E("AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3075. amic6_switch, ARRAY_SIZE(amic6_switch), NULL,
  3076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3077. SND_SOC_DAPM_MIXER_E("AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3078. amic7_switch, ARRAY_SIZE(amic7_switch), NULL,
  3079. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3080. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3081. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3082. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3083. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3084. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3085. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3086. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3087. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3088. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3089. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3090. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3091. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3092. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3093. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3094. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3095. SND_SOC_DAPM_MIXER_E("VA_AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3096. va_amic6_switch, ARRAY_SIZE(va_amic6_switch), NULL,
  3097. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3098. SND_SOC_DAPM_MIXER_E("VA_AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3099. va_amic7_switch, ARRAY_SIZE(va_amic7_switch), NULL,
  3100. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3101. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3102. &tx_adc2_mux),
  3103. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3104. &tx_adc3_mux),
  3105. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3106. &tx_adc4_mux),
  3107. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  3108. &tx_hdr12_mux),
  3109. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  3110. &tx_hdr34_mux),
  3111. /*tx mixers*/
  3112. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3113. adc1_switch, ARRAY_SIZE(adc1_switch),
  3114. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3115. SND_SOC_DAPM_POST_PMD),
  3116. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3117. adc2_switch, ARRAY_SIZE(adc2_switch),
  3118. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3119. SND_SOC_DAPM_POST_PMD),
  3120. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3121. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  3122. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3123. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3124. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  3125. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3126. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3127. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3128. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3129. SND_SOC_DAPM_POST_PMD),
  3130. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3131. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3132. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3133. SND_SOC_DAPM_POST_PMD),
  3134. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3135. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3136. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3137. SND_SOC_DAPM_POST_PMD),
  3138. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3139. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3140. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3141. SND_SOC_DAPM_POST_PMD),
  3142. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3143. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3144. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3145. SND_SOC_DAPM_POST_PMD),
  3146. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3147. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3148. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3149. SND_SOC_DAPM_POST_PMD),
  3150. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3151. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3152. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3153. SND_SOC_DAPM_POST_PMD),
  3154. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3155. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3156. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3157. SND_SOC_DAPM_POST_PMD),
  3158. /* micbias widgets*/
  3159. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3160. wcd938x_codec_enable_micbias,
  3161. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3162. SND_SOC_DAPM_POST_PMD),
  3163. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3164. wcd938x_codec_enable_micbias,
  3165. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3166. SND_SOC_DAPM_POST_PMD),
  3167. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3168. wcd938x_codec_enable_micbias,
  3169. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3170. SND_SOC_DAPM_POST_PMD),
  3171. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3172. wcd938x_codec_enable_micbias,
  3173. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3174. SND_SOC_DAPM_POST_PMD),
  3175. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3176. wcd938x_codec_force_enable_micbias,
  3177. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3178. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3179. wcd938x_codec_force_enable_micbias,
  3180. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3181. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3182. wcd938x_codec_force_enable_micbias,
  3183. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3184. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3185. wcd938x_codec_force_enable_micbias,
  3186. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3187. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3188. wcd938x_codec_enable_vdd_buck,
  3189. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3190. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3191. wcd938x_enable_clsh,
  3192. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3193. /*rx widgets*/
  3194. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  3195. wcd938x_codec_enable_ear_pa,
  3196. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3197. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3198. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  3199. wcd938x_codec_enable_aux_pa,
  3200. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3201. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3202. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  3203. wcd938x_codec_enable_hphl_pa,
  3204. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3205. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3206. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  3207. wcd938x_codec_enable_hphr_pa,
  3208. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3209. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3210. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3211. wcd938x_codec_hphl_dac_event,
  3212. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3213. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3214. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3215. wcd938x_codec_hphr_dac_event,
  3216. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3217. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3218. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3219. wcd938x_codec_ear_dac_event,
  3220. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3221. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3222. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3223. wcd938x_codec_aux_dac_event,
  3224. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3225. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3226. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3227. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3228. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3229. SND_SOC_DAPM_POST_PMD),
  3230. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3231. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3232. SND_SOC_DAPM_POST_PMD),
  3233. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3234. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3235. SND_SOC_DAPM_POST_PMD),
  3236. /* rx mixer widgets*/
  3237. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3238. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3239. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3240. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3241. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3242. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3243. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3244. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3245. /*output widgets tx*/
  3246. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3247. /*output widgets rx*/
  3248. SND_SOC_DAPM_OUTPUT("EAR"),
  3249. SND_SOC_DAPM_OUTPUT("AUX"),
  3250. SND_SOC_DAPM_OUTPUT("HPHL"),
  3251. SND_SOC_DAPM_OUTPUT("HPHR"),
  3252. /* micbias pull up widgets*/
  3253. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3254. wcd938x_codec_enable_micbias_pullup,
  3255. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3256. SND_SOC_DAPM_POST_PMD),
  3257. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3258. wcd938x_codec_enable_micbias_pullup,
  3259. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3260. SND_SOC_DAPM_POST_PMD),
  3261. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3262. wcd938x_codec_enable_micbias_pullup,
  3263. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3264. SND_SOC_DAPM_POST_PMD),
  3265. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3266. wcd938x_codec_enable_micbias_pullup,
  3267. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3268. SND_SOC_DAPM_POST_PMD),
  3269. };
  3270. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3271. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3272. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3273. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3274. {"ADC1 REQ", NULL, "ADC1"},
  3275. {"ADC1", NULL, "AMIC1_MIXER"},
  3276. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3277. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3278. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3279. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3280. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3281. {"ADC2 REQ", NULL, "ADC2"},
  3282. {"ADC2", NULL, "HDR12 MUX"},
  3283. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3284. {"HDR12 MUX", "HDR12", "AMIC1_MIXER"},
  3285. {"ADC2 MUX", "INP3", "AMIC3_MIXER"},
  3286. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3287. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3288. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3289. {"ADC2 MUX", "INP2", "AMIC2_MIXER"},
  3290. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3291. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3292. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3293. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3294. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3295. {"ADC3 REQ", NULL, "ADC3"},
  3296. {"ADC3", NULL, "HDR34 MUX"},
  3297. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3298. {"HDR34 MUX", "HDR34", "AMIC5_MIXER"},
  3299. {"ADC3 MUX", "INP4", "AMIC4_MIXER"},
  3300. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3301. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3302. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3303. {"ADC3 MUX", "INP6", "AMIC6_MIXER"},
  3304. {"AMIC6_MIXER", "Switch", "AMIC6"},
  3305. {"AMIC6_MIXER", NULL, "VA_AMIC6_MIXER"},
  3306. {"VA_AMIC6_MIXER", "Switch", "VA AMIC6"},
  3307. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3308. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3309. {"ADC4 REQ", NULL, "ADC4"},
  3310. {"ADC4", NULL, "ADC4 MUX"},
  3311. {"ADC4 MUX", "INP5", "AMIC5_MIXER"},
  3312. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3313. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3314. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3315. {"ADC4 MUX", "INP7", "AMIC7_MIXER"},
  3316. {"AMIC7_MIXER", "Switch", "AMIC7"},
  3317. {"AMIC7_MIXER", NULL, "VA_AMIC7_MIXER"},
  3318. {"VA_AMIC7_MIXER", "Switch", "VA AMIC7"},
  3319. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3320. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3321. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3322. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3323. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3324. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3325. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3326. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3327. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3328. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3329. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3330. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3331. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3332. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3333. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3334. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3335. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3336. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3337. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3338. {"RX1", NULL, "IN1_HPHL"},
  3339. {"RDAC1", NULL, "RX1"},
  3340. {"HPHL_RDAC", "Switch", "RDAC1"},
  3341. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3342. {"HPHL", NULL, "HPHL PGA"},
  3343. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3344. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3345. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3346. {"RX2", NULL, "IN2_HPHR"},
  3347. {"RDAC2", NULL, "RX2"},
  3348. {"HPHR_RDAC", "Switch", "RDAC2"},
  3349. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3350. {"HPHR", NULL, "HPHR PGA"},
  3351. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3352. {"IN3_AUX", NULL, "VDD_BUCK"},
  3353. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3354. {"RX3", NULL, "IN3_AUX"},
  3355. {"RDAC4", NULL, "RX3"},
  3356. {"AUX_RDAC", "Switch", "RDAC4"},
  3357. {"AUX PGA", NULL, "AUX_RDAC"},
  3358. {"AUX", NULL, "AUX PGA"},
  3359. {"RDAC3_MUX", "RX3", "RX3"},
  3360. {"RDAC3_MUX", "RX1", "RX1"},
  3361. {"RDAC3", NULL, "RDAC3_MUX"},
  3362. {"EAR_RDAC", "Switch", "RDAC3"},
  3363. {"EAR PGA", NULL, "EAR_RDAC"},
  3364. {"EAR", NULL, "EAR PGA"},
  3365. };
  3366. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3367. void *file_private_data,
  3368. struct file *file,
  3369. char __user *buf, size_t count,
  3370. loff_t pos)
  3371. {
  3372. struct wcd938x_priv *priv;
  3373. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3374. int len = 0;
  3375. priv = (struct wcd938x_priv *) entry->private_data;
  3376. if (!priv) {
  3377. pr_err_ratelimited("%s: wcd938x priv is null\n", __func__);
  3378. return -EINVAL;
  3379. }
  3380. switch (priv->version) {
  3381. case WCD938X_VERSION_1_0:
  3382. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3383. break;
  3384. default:
  3385. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3386. }
  3387. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3388. }
  3389. static struct snd_info_entry_ops wcd938x_info_ops = {
  3390. .read = wcd938x_version_read,
  3391. };
  3392. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3393. void *file_private_data,
  3394. struct file *file,
  3395. char __user *buf, size_t count,
  3396. loff_t pos)
  3397. {
  3398. struct wcd938x_priv *priv;
  3399. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3400. int len = 0;
  3401. priv = (struct wcd938x_priv *) entry->private_data;
  3402. if (!priv) {
  3403. pr_err_ratelimited("%s: wcd938x priv is null\n", __func__);
  3404. return -EINVAL;
  3405. }
  3406. switch (priv->variant) {
  3407. case WCD9380:
  3408. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3409. break;
  3410. case WCD9385:
  3411. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3412. break;
  3413. default:
  3414. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3415. }
  3416. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3417. }
  3418. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3419. .read = wcd938x_variant_read,
  3420. };
  3421. /*
  3422. * wcd938x_get_codec_variant
  3423. * @component: component instance
  3424. *
  3425. * Return: codec variant or -EINVAL in error.
  3426. */
  3427. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3428. {
  3429. struct wcd938x_priv *priv = NULL;
  3430. if (!component)
  3431. return -EINVAL;
  3432. priv = snd_soc_component_get_drvdata(component);
  3433. if (!priv) {
  3434. dev_err(component->dev,
  3435. "%s:wcd938x not probed\n", __func__);
  3436. return 0;
  3437. }
  3438. return priv->variant;
  3439. }
  3440. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3441. /*
  3442. * wcd938x_info_create_codec_entry - creates wcd938x module
  3443. * @codec_root: The parent directory
  3444. * @component: component instance
  3445. *
  3446. * Creates wcd938x module, variant and version entry under the given
  3447. * parent directory.
  3448. *
  3449. * Return: 0 on success or negative error code on failure.
  3450. */
  3451. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3452. struct snd_soc_component *component)
  3453. {
  3454. struct snd_info_entry *version_entry;
  3455. struct snd_info_entry *variant_entry;
  3456. struct wcd938x_priv *priv;
  3457. struct snd_soc_card *card;
  3458. if (!codec_root || !component)
  3459. return -EINVAL;
  3460. priv = snd_soc_component_get_drvdata(component);
  3461. if (priv->entry) {
  3462. dev_dbg(priv->dev,
  3463. "%s:wcd938x module already created\n", __func__);
  3464. return 0;
  3465. }
  3466. card = component->card;
  3467. priv->entry = snd_info_create_module_entry(codec_root->module,
  3468. "wcd938x", codec_root);
  3469. if (!priv->entry) {
  3470. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3471. __func__);
  3472. return -ENOMEM;
  3473. }
  3474. priv->entry->mode = S_IFDIR | 0555;
  3475. if (snd_info_register(priv->entry) < 0) {
  3476. snd_info_free_entry(priv->entry);
  3477. return -ENOMEM;
  3478. }
  3479. version_entry = snd_info_create_card_entry(card->snd_card,
  3480. "version",
  3481. priv->entry);
  3482. if (!version_entry) {
  3483. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3484. __func__);
  3485. snd_info_free_entry(priv->entry);
  3486. return -ENOMEM;
  3487. }
  3488. version_entry->private_data = priv;
  3489. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3490. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3491. version_entry->c.ops = &wcd938x_info_ops;
  3492. if (snd_info_register(version_entry) < 0) {
  3493. snd_info_free_entry(version_entry);
  3494. snd_info_free_entry(priv->entry);
  3495. return -ENOMEM;
  3496. }
  3497. priv->version_entry = version_entry;
  3498. variant_entry = snd_info_create_card_entry(card->snd_card,
  3499. "variant",
  3500. priv->entry);
  3501. if (!variant_entry) {
  3502. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3503. __func__);
  3504. snd_info_free_entry(version_entry);
  3505. snd_info_free_entry(priv->entry);
  3506. return -ENOMEM;
  3507. }
  3508. variant_entry->private_data = priv;
  3509. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3510. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3511. variant_entry->c.ops = &wcd938x_variant_ops;
  3512. if (snd_info_register(variant_entry) < 0) {
  3513. snd_info_free_entry(variant_entry);
  3514. snd_info_free_entry(version_entry);
  3515. snd_info_free_entry(priv->entry);
  3516. return -ENOMEM;
  3517. }
  3518. priv->variant_entry = variant_entry;
  3519. return 0;
  3520. }
  3521. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3522. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3523. struct wcd938x_pdata *pdata)
  3524. {
  3525. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3526. int rc = 0;
  3527. if (!pdata) {
  3528. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3529. return -ENODEV;
  3530. }
  3531. /* set micbias voltage */
  3532. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3533. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3534. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3535. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3536. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3537. vout_ctl_4 < 0) {
  3538. rc = -EINVAL;
  3539. goto done;
  3540. }
  3541. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3542. vout_ctl_1);
  3543. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3544. vout_ctl_2);
  3545. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3546. vout_ctl_3);
  3547. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3548. vout_ctl_4);
  3549. done:
  3550. return rc;
  3551. }
  3552. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3553. {
  3554. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3555. struct snd_soc_dapm_context *dapm =
  3556. snd_soc_component_get_dapm(component);
  3557. int variant;
  3558. int ret = -EINVAL;
  3559. dev_info(component->dev, "%s()\n", __func__);
  3560. wcd938x = snd_soc_component_get_drvdata(component);
  3561. if (!wcd938x)
  3562. return -EINVAL;
  3563. wcd938x->component = component;
  3564. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3565. devm_regmap_qti_debugfs_register(&wcd938x->tx_swr_dev->dev, wcd938x->regmap);
  3566. variant = (snd_soc_component_read(component,
  3567. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3568. wcd938x->variant = variant;
  3569. wcd938x->fw_data = devm_kzalloc(component->dev,
  3570. sizeof(*(wcd938x->fw_data)),
  3571. GFP_KERNEL);
  3572. if (!wcd938x->fw_data) {
  3573. dev_err(component->dev, "Failed to allocate fw_data\n");
  3574. ret = -ENOMEM;
  3575. goto err;
  3576. }
  3577. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3578. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3579. WCD9XXX_CODEC_HWDEP_NODE, component);
  3580. if (ret < 0) {
  3581. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3582. goto err_hwdep;
  3583. }
  3584. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3585. if (ret) {
  3586. pr_err("%s: mbhc initialization failed\n", __func__);
  3587. goto err_hwdep;
  3588. }
  3589. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3590. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3591. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3592. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3593. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3594. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3595. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3596. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3597. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3598. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3599. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3600. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3601. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3602. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3603. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC6");
  3604. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC7");
  3605. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3606. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3607. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3608. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3609. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3610. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3611. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3612. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3613. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3614. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3615. snd_soc_dapm_sync(dapm);
  3616. wcd_cls_h_init(&wcd938x->clsh_info);
  3617. wcd938x_init_reg(component);
  3618. if (wcd938x->variant == WCD9380) {
  3619. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3620. ARRAY_SIZE(wcd9380_snd_controls));
  3621. if (ret < 0) {
  3622. dev_err(component->dev,
  3623. "%s: Failed to add snd ctrls for variant: %d\n",
  3624. __func__, wcd938x->variant);
  3625. goto err_hwdep;
  3626. }
  3627. }
  3628. if (wcd938x->variant == WCD9385) {
  3629. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3630. ARRAY_SIZE(wcd9385_snd_controls));
  3631. if (ret < 0) {
  3632. dev_err(component->dev,
  3633. "%s: Failed to add snd ctrls for variant: %d\n",
  3634. __func__, wcd938x->variant);
  3635. goto err_hwdep;
  3636. }
  3637. }
  3638. wcd938x->version = WCD938X_VERSION_1_0;
  3639. /* Register event notifier */
  3640. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3641. if (wcd938x->register_notifier) {
  3642. ret = wcd938x->register_notifier(wcd938x->handle,
  3643. &wcd938x->nblock,
  3644. true);
  3645. if (ret) {
  3646. dev_err(component->dev,
  3647. "%s: Failed to register notifier %d\n",
  3648. __func__, ret);
  3649. return ret;
  3650. }
  3651. }
  3652. return ret;
  3653. err_hwdep:
  3654. wcd938x->fw_data = NULL;
  3655. err:
  3656. return ret;
  3657. }
  3658. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3659. {
  3660. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3661. if (!wcd938x) {
  3662. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3663. __func__);
  3664. return;
  3665. }
  3666. if (wcd938x->register_notifier)
  3667. wcd938x->register_notifier(wcd938x->handle,
  3668. &wcd938x->nblock,
  3669. false);
  3670. }
  3671. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3672. {
  3673. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3674. if (!wcd938x)
  3675. return 0;
  3676. wcd938x->dapm_bias_off = true;
  3677. return 0;
  3678. }
  3679. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3680. {
  3681. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3682. if (!wcd938x)
  3683. return 0;
  3684. wcd938x->dapm_bias_off = false;
  3685. return 0;
  3686. }
  3687. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3688. .name = WCD938X_DRV_NAME,
  3689. .probe = wcd938x_soc_codec_probe,
  3690. .remove = wcd938x_soc_codec_remove,
  3691. .controls = wcd938x_snd_controls,
  3692. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3693. .dapm_widgets = wcd938x_dapm_widgets,
  3694. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3695. .dapm_routes = wcd938x_audio_map,
  3696. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3697. .suspend = wcd938x_soc_codec_suspend,
  3698. .resume = wcd938x_soc_codec_resume,
  3699. };
  3700. static int wcd938x_reset(struct device *dev)
  3701. {
  3702. struct wcd938x_priv *wcd938x = NULL;
  3703. int rc = 0;
  3704. int value = 0;
  3705. if (!dev)
  3706. return -ENODEV;
  3707. wcd938x = dev_get_drvdata(dev);
  3708. if (!wcd938x)
  3709. return -EINVAL;
  3710. if (!wcd938x->rst_np) {
  3711. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  3712. __func__);
  3713. return -EINVAL;
  3714. }
  3715. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3716. if (value > 0)
  3717. return 0;
  3718. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3719. if (rc) {
  3720. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  3721. __func__);
  3722. return rc;
  3723. }
  3724. /* 20us sleep required after pulling the reset gpio to LOW */
  3725. usleep_range(20, 30);
  3726. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3727. if (rc) {
  3728. dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
  3729. __func__);
  3730. return rc;
  3731. }
  3732. /* 20us sleep required after pulling the reset gpio to HIGH */
  3733. usleep_range(20, 30);
  3734. return rc;
  3735. }
  3736. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3737. u32 *val)
  3738. {
  3739. int rc = 0;
  3740. rc = of_property_read_u32(dev->of_node, name, val);
  3741. if (rc)
  3742. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3743. __func__, name, dev->of_node->full_name);
  3744. return rc;
  3745. }
  3746. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3747. struct wcd938x_micbias_setting *mb)
  3748. {
  3749. u32 prop_val = 0;
  3750. int rc = 0;
  3751. /* MB1 */
  3752. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3753. NULL)) {
  3754. rc = wcd938x_read_of_property_u32(dev,
  3755. "qcom,cdc-micbias1-mv",
  3756. &prop_val);
  3757. if (!rc)
  3758. mb->micb1_mv = prop_val;
  3759. } else {
  3760. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3761. __func__);
  3762. }
  3763. /* MB2 */
  3764. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3765. NULL)) {
  3766. rc = wcd938x_read_of_property_u32(dev,
  3767. "qcom,cdc-micbias2-mv",
  3768. &prop_val);
  3769. if (!rc)
  3770. mb->micb2_mv = prop_val;
  3771. } else {
  3772. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3773. __func__);
  3774. }
  3775. /* MB3 */
  3776. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3777. NULL)) {
  3778. rc = wcd938x_read_of_property_u32(dev,
  3779. "qcom,cdc-micbias3-mv",
  3780. &prop_val);
  3781. if (!rc)
  3782. mb->micb3_mv = prop_val;
  3783. } else {
  3784. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3785. __func__);
  3786. }
  3787. /* MB4 */
  3788. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3789. NULL)) {
  3790. rc = wcd938x_read_of_property_u32(dev,
  3791. "qcom,cdc-micbias4-mv",
  3792. &prop_val);
  3793. if (!rc)
  3794. mb->micb4_mv = prop_val;
  3795. } else {
  3796. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3797. __func__);
  3798. }
  3799. }
  3800. static int wcd938x_reset_low(struct device *dev)
  3801. {
  3802. struct wcd938x_priv *wcd938x = NULL;
  3803. int rc = 0;
  3804. if (!dev)
  3805. return -ENODEV;
  3806. wcd938x = dev_get_drvdata(dev);
  3807. if (!wcd938x)
  3808. return -EINVAL;
  3809. if (!wcd938x->rst_np) {
  3810. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  3811. __func__);
  3812. return -EINVAL;
  3813. }
  3814. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3815. if (rc) {
  3816. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  3817. __func__);
  3818. return rc;
  3819. }
  3820. /* 20us sleep required after pulling the reset gpio to LOW */
  3821. usleep_range(20, 30);
  3822. return rc;
  3823. }
  3824. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3825. {
  3826. struct wcd938x_pdata *pdata = NULL;
  3827. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3828. GFP_KERNEL);
  3829. if (!pdata)
  3830. return NULL;
  3831. pdata->rst_np = of_parse_phandle(dev->of_node,
  3832. "qcom,wcd-rst-gpio-node", 0);
  3833. if (!pdata->rst_np) {
  3834. dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
  3835. __func__, "qcom,wcd-rst-gpio-node",
  3836. dev->of_node->full_name);
  3837. return NULL;
  3838. }
  3839. /* Parse power supplies */
  3840. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3841. &pdata->num_supplies);
  3842. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3843. dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
  3844. __func__);
  3845. return NULL;
  3846. }
  3847. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3848. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3849. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3850. return pdata;
  3851. }
  3852. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3853. {
  3854. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3855. __func__, irq);
  3856. return IRQ_HANDLED;
  3857. }
  3858. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3859. {
  3860. .name = "wcd938x_cdc",
  3861. .playback = {
  3862. .stream_name = "WCD938X_AIF Playback",
  3863. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3864. .formats = WCD938X_FORMATS,
  3865. .rate_max = 384000,
  3866. .rate_min = 8000,
  3867. .channels_min = 1,
  3868. .channels_max = 4,
  3869. },
  3870. .capture = {
  3871. .stream_name = "WCD938X_AIF Capture",
  3872. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3873. .formats = WCD938X_FORMATS,
  3874. .rate_max = 384000,
  3875. .rate_min = 8000,
  3876. .channels_min = 1,
  3877. .channels_max = 4,
  3878. },
  3879. },
  3880. };
  3881. static int wcd938x_bind(struct device *dev)
  3882. {
  3883. int ret = 0, i = 0;
  3884. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3885. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3886. /*
  3887. * Add 5msec delay to provide sufficient time for
  3888. * soundwire auto enumeration of slave devices as
  3889. * as per HW requirement.
  3890. */
  3891. usleep_range(5000, 5010);
  3892. ret = component_bind_all(dev, wcd938x);
  3893. if (ret) {
  3894. dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
  3895. __func__, ret);
  3896. return ret;
  3897. }
  3898. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3899. if (!wcd938x->rx_swr_dev) {
  3900. dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
  3901. __func__);
  3902. ret = -ENODEV;
  3903. goto err;
  3904. }
  3905. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3906. if (!wcd938x->tx_swr_dev) {
  3907. dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
  3908. __func__);
  3909. ret = -ENODEV;
  3910. goto err;
  3911. }
  3912. swr_init_port_params(wcd938x->tx_swr_dev, SWR_NUM_PORTS,
  3913. wcd938x->swr_tx_port_params);
  3914. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3915. &wcd938x_regmap_config);
  3916. if (!wcd938x->regmap) {
  3917. dev_err_ratelimited(dev, "%s: Regmap init failed\n",
  3918. __func__);
  3919. goto err;
  3920. }
  3921. /* Set all interupts as edge triggered */
  3922. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3923. regmap_write(wcd938x->regmap,
  3924. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3925. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3926. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3927. wcd938x->irq_info.codec_name = "WCD938X";
  3928. wcd938x->irq_info.regmap = wcd938x->regmap;
  3929. wcd938x->irq_info.dev = dev;
  3930. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3931. if (ret) {
  3932. dev_err_ratelimited(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3933. __func__, ret);
  3934. goto err;
  3935. }
  3936. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3937. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3938. if (ret < 0) {
  3939. dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
  3940. goto err_irq;
  3941. }
  3942. /* Request for watchdog interrupt */
  3943. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3944. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3945. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3946. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3947. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3948. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3949. /* Disable watchdog interrupt for HPH and AUX */
  3950. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3951. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3952. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3953. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3954. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3955. if (ret) {
  3956. dev_err_ratelimited(dev, "%s: Codec registration failed\n",
  3957. __func__);
  3958. goto err_irq;
  3959. }
  3960. wcd938x->dev_up = true;
  3961. return ret;
  3962. err_irq:
  3963. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3964. err:
  3965. component_unbind_all(dev, wcd938x);
  3966. return ret;
  3967. }
  3968. static void wcd938x_unbind(struct device *dev)
  3969. {
  3970. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3971. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3972. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3973. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3974. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3975. snd_soc_unregister_component(dev);
  3976. component_unbind_all(dev, wcd938x);
  3977. }
  3978. static const struct of_device_id wcd938x_dt_match[] = {
  3979. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3980. {}
  3981. };
  3982. static const struct component_master_ops wcd938x_comp_ops = {
  3983. .bind = wcd938x_bind,
  3984. .unbind = wcd938x_unbind,
  3985. };
  3986. static int wcd938x_compare_of(struct device *dev, void *data)
  3987. {
  3988. return dev->of_node == data;
  3989. }
  3990. static void wcd938x_release_of(struct device *dev, void *data)
  3991. {
  3992. of_node_put(data);
  3993. }
  3994. static int wcd938x_add_slave_components(struct device *dev,
  3995. struct component_match **matchptr)
  3996. {
  3997. struct device_node *np, *rx_node, *tx_node;
  3998. np = dev->of_node;
  3999. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  4000. if (!rx_node) {
  4001. dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
  4002. return -ENODEV;
  4003. }
  4004. of_node_get(rx_node);
  4005. component_match_add_release(dev, matchptr,
  4006. wcd938x_release_of,
  4007. wcd938x_compare_of,
  4008. rx_node);
  4009. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  4010. if (!tx_node) {
  4011. dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
  4012. return -ENODEV;
  4013. }
  4014. of_node_get(tx_node);
  4015. component_match_add_release(dev, matchptr,
  4016. wcd938x_release_of,
  4017. wcd938x_compare_of,
  4018. tx_node);
  4019. return 0;
  4020. }
  4021. static int wcd938x_probe(struct platform_device *pdev)
  4022. {
  4023. struct component_match *match = NULL;
  4024. struct wcd938x_priv *wcd938x = NULL;
  4025. struct wcd938x_pdata *pdata = NULL;
  4026. struct wcd_ctrl_platform_data *plat_data = NULL;
  4027. struct device *dev = &pdev->dev;
  4028. int ret;
  4029. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  4030. GFP_KERNEL);
  4031. if (!wcd938x)
  4032. return -ENOMEM;
  4033. dev_set_drvdata(dev, wcd938x);
  4034. wcd938x->dev = dev;
  4035. pdata = wcd938x_populate_dt_data(dev);
  4036. if (!pdata) {
  4037. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4038. return -EINVAL;
  4039. }
  4040. dev->platform_data = pdata;
  4041. wcd938x->rst_np = pdata->rst_np;
  4042. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  4043. pdata->regulator, pdata->num_supplies);
  4044. if (!wcd938x->supplies) {
  4045. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4046. __func__);
  4047. return ret;
  4048. }
  4049. plat_data = dev_get_platdata(dev->parent);
  4050. if (!plat_data) {
  4051. dev_err(dev, "%s: platform data from parent is NULL\n",
  4052. __func__);
  4053. return -EINVAL;
  4054. }
  4055. wcd938x->handle = (void *)plat_data->handle;
  4056. if (!wcd938x->handle) {
  4057. dev_err(dev, "%s: handle is NULL\n", __func__);
  4058. return -EINVAL;
  4059. }
  4060. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  4061. if (!wcd938x->update_wcd_event) {
  4062. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4063. __func__);
  4064. return -EINVAL;
  4065. }
  4066. wcd938x->register_notifier = plat_data->register_notifier;
  4067. if (!wcd938x->register_notifier) {
  4068. dev_err(dev, "%s: register_notifier api is null!\n",
  4069. __func__);
  4070. return -EINVAL;
  4071. }
  4072. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  4073. pdata->regulator,
  4074. pdata->num_supplies);
  4075. if (ret) {
  4076. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4077. __func__);
  4078. return ret;
  4079. }
  4080. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4081. CODEC_RX);
  4082. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4083. CODEC_TX);
  4084. if (ret) {
  4085. dev_err(dev, "Failed to read port mapping\n");
  4086. goto err;
  4087. }
  4088. ret = wcd938x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4089. CODEC_TX);
  4090. if (ret) {
  4091. dev_err(dev, "Failed to read port params\n");
  4092. goto err;
  4093. }
  4094. mutex_init(&wcd938x->wakeup_lock);
  4095. mutex_init(&wcd938x->micb_lock);
  4096. ret = wcd938x_add_slave_components(dev, &match);
  4097. if (ret)
  4098. goto err_lock_init;
  4099. wcd938x_reset(dev);
  4100. wcd938x->wakeup = wcd938x_wakeup;
  4101. return component_master_add_with_match(dev,
  4102. &wcd938x_comp_ops, match);
  4103. err_lock_init:
  4104. mutex_destroy(&wcd938x->micb_lock);
  4105. mutex_destroy(&wcd938x->wakeup_lock);
  4106. err:
  4107. return ret;
  4108. }
  4109. static int wcd938x_remove(struct platform_device *pdev)
  4110. {
  4111. struct wcd938x_priv *wcd938x = NULL;
  4112. wcd938x = platform_get_drvdata(pdev);
  4113. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  4114. mutex_destroy(&wcd938x->micb_lock);
  4115. mutex_destroy(&wcd938x->wakeup_lock);
  4116. dev_set_drvdata(&pdev->dev, NULL);
  4117. return 0;
  4118. }
  4119. #ifdef CONFIG_PM_SLEEP
  4120. static int wcd938x_suspend(struct device *dev)
  4121. {
  4122. struct wcd938x_priv *wcd938x = NULL;
  4123. int ret = 0;
  4124. struct wcd938x_pdata *pdata = NULL;
  4125. if (!dev)
  4126. return -ENODEV;
  4127. wcd938x = dev_get_drvdata(dev);
  4128. if (!wcd938x)
  4129. return -EINVAL;
  4130. pdata = dev_get_platdata(wcd938x->dev);
  4131. if (!pdata) {
  4132. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4133. return -EINVAL;
  4134. }
  4135. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  4136. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  4137. wcd938x->supplies,
  4138. pdata->regulator,
  4139. pdata->num_supplies,
  4140. "cdc-vdd-buck");
  4141. if (ret == -EINVAL) {
  4142. dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
  4143. __func__);
  4144. return 0;
  4145. }
  4146. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  4147. }
  4148. if (wcd938x->dapm_bias_off ||
  4149. (snd_soc_component_get_bias_level(wcd938x->component) ==
  4150. SND_SOC_BIAS_OFF)) {
  4151. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4152. wcd938x->supplies,
  4153. pdata->regulator,
  4154. pdata->num_supplies,
  4155. true);
  4156. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4157. }
  4158. return 0;
  4159. }
  4160. static int wcd938x_resume(struct device *dev)
  4161. {
  4162. struct wcd938x_priv *wcd938x = NULL;
  4163. struct wcd938x_pdata *pdata = NULL;
  4164. if (!dev)
  4165. return -ENODEV;
  4166. wcd938x = dev_get_drvdata(dev);
  4167. if (!wcd938x)
  4168. return -EINVAL;
  4169. pdata = dev_get_platdata(wcd938x->dev);
  4170. if (!pdata) {
  4171. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4172. return -EINVAL;
  4173. }
  4174. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  4175. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4176. wcd938x->supplies,
  4177. pdata->regulator,
  4178. pdata->num_supplies,
  4179. false);
  4180. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4181. }
  4182. return 0;
  4183. }
  4184. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  4185. .suspend_late = wcd938x_suspend,
  4186. .resume_early = wcd938x_resume,
  4187. };
  4188. #endif
  4189. static struct platform_driver wcd938x_codec_driver = {
  4190. .probe = wcd938x_probe,
  4191. .remove = wcd938x_remove,
  4192. .driver = {
  4193. .name = "wcd938x_codec",
  4194. .owner = THIS_MODULE,
  4195. .of_match_table = of_match_ptr(wcd938x_dt_match),
  4196. #ifdef CONFIG_PM_SLEEP
  4197. .pm = &wcd938x_dev_pm_ops,
  4198. #endif
  4199. .suppress_bind_attrs = true,
  4200. },
  4201. };
  4202. module_platform_driver(wcd938x_codec_driver);
  4203. MODULE_DESCRIPTION("WCD938X Codec driver");
  4204. MODULE_LICENSE("GPL v2");