dp_tx.c 153 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  115. /**
  116. * dp_update_tx_desc_stats - Update the increase or decrease in
  117. * outstanding tx desc count
  118. * values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  125. {
  126. int32_t tx_descs_cnt =
  127. qdf_atomic_read(&pdev->num_tx_outstanding);
  128. if (pdev->tx_descs_max < tx_descs_cnt)
  129. pdev->tx_descs_max = tx_descs_cnt;
  130. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  131. pdev->tx_descs_max);
  132. }
  133. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  134. static inline void
  135. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  136. {
  137. }
  138. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  139. #ifdef QCA_TX_LIMIT_CHECK
  140. /**
  141. * dp_tx_limit_check - Check if allocated tx descriptors reached
  142. * soc max limit and pdev max limit
  143. * @vdev: DP vdev handle
  144. *
  145. * Return: true if allocated tx descriptors reached max configured value, else
  146. * false
  147. */
  148. static inline bool
  149. dp_tx_limit_check(struct dp_vdev *vdev)
  150. {
  151. struct dp_pdev *pdev = vdev->pdev;
  152. struct dp_soc *soc = pdev->soc;
  153. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  154. soc->num_tx_allowed) {
  155. dp_tx_info("queued packets are more than max tx, drop the frame");
  156. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  157. return true;
  158. }
  159. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  160. pdev->num_tx_allowed) {
  161. dp_tx_info("queued packets are more than max tx, drop the frame");
  162. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  163. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  164. return true;
  165. }
  166. return false;
  167. }
  168. /**
  169. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  170. * reached soc max limit
  171. * @vdev: DP vdev handle
  172. *
  173. * Return: true if allocated tx descriptors reached max configured value, else
  174. * false
  175. */
  176. static inline bool
  177. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  178. {
  179. struct dp_pdev *pdev = vdev->pdev;
  180. struct dp_soc *soc = pdev->soc;
  181. if (qdf_atomic_read(&soc->num_tx_exception) >=
  182. soc->num_msdu_exception_desc) {
  183. dp_info("exc packets are more than max drop the exc pkt");
  184. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  185. return true;
  186. }
  187. return false;
  188. }
  189. /**
  190. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  191. * @vdev: DP pdev handle
  192. *
  193. * Return: void
  194. */
  195. static inline void
  196. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  197. {
  198. struct dp_soc *soc = pdev->soc;
  199. qdf_atomic_inc(&pdev->num_tx_outstanding);
  200. qdf_atomic_inc(&soc->num_tx_outstanding);
  201. dp_update_tx_desc_stats(pdev);
  202. }
  203. /**
  204. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  205. * @vdev: DP pdev handle
  206. *
  207. * Return: void
  208. */
  209. static inline void
  210. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  211. {
  212. struct dp_soc *soc = pdev->soc;
  213. qdf_atomic_dec(&pdev->num_tx_outstanding);
  214. qdf_atomic_dec(&soc->num_tx_outstanding);
  215. dp_update_tx_desc_stats(pdev);
  216. }
  217. #else //QCA_TX_LIMIT_CHECK
  218. static inline bool
  219. dp_tx_limit_check(struct dp_vdev *vdev)
  220. {
  221. return false;
  222. }
  223. static inline bool
  224. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  225. {
  226. return false;
  227. }
  228. static inline void
  229. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  230. {
  231. qdf_atomic_inc(&pdev->num_tx_outstanding);
  232. dp_update_tx_desc_stats(pdev);
  233. }
  234. static inline void
  235. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  236. {
  237. qdf_atomic_dec(&pdev->num_tx_outstanding);
  238. dp_update_tx_desc_stats(pdev);
  239. }
  240. #endif //QCA_TX_LIMIT_CHECK
  241. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  242. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  243. {
  244. enum dp_tx_event_type type;
  245. if (flags & DP_TX_DESC_FLAG_FLUSH)
  246. type = DP_TX_DESC_FLUSH;
  247. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  248. type = DP_TX_COMP_UNMAP_ERR;
  249. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  250. type = DP_TX_COMP_UNMAP;
  251. else
  252. type = DP_TX_DESC_UNMAP;
  253. return type;
  254. }
  255. static inline void
  256. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  257. qdf_nbuf_t skb, uint32_t sw_cookie,
  258. enum dp_tx_event_type type)
  259. {
  260. struct dp_tx_desc_event *entry;
  261. uint32_t idx;
  262. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  263. return;
  264. switch (type) {
  265. case DP_TX_COMP_UNMAP:
  266. case DP_TX_COMP_UNMAP_ERR:
  267. case DP_TX_COMP_MSDU_EXT:
  268. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  269. DP_TX_COMP_HISTORY_SIZE);
  270. entry = &soc->tx_comp_history->entry[idx];
  271. break;
  272. case DP_TX_DESC_MAP:
  273. case DP_TX_DESC_UNMAP:
  274. case DP_TX_DESC_COOKIE:
  275. case DP_TX_DESC_FLUSH:
  276. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  277. DP_TX_TCL_HISTORY_SIZE);
  278. entry = &soc->tx_tcl_history->entry[idx];
  279. break;
  280. default:
  281. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  282. return;
  283. }
  284. entry->skb = skb;
  285. entry->paddr = paddr;
  286. entry->sw_cookie = sw_cookie;
  287. entry->type = type;
  288. entry->ts = qdf_get_log_timestamp();
  289. }
  290. static inline void
  291. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  292. struct qdf_tso_seg_elem_t *tso_seg,
  293. qdf_nbuf_t skb, uint32_t sw_cookie,
  294. enum dp_tx_event_type type)
  295. {
  296. int i;
  297. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  298. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  299. skb, sw_cookie, type);
  300. }
  301. if (!tso_seg->next)
  302. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  303. skb, 0xFFFFFFFF, type);
  304. }
  305. static inline void
  306. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  307. qdf_nbuf_t skb, uint32_t sw_cookie,
  308. enum dp_tx_event_type type)
  309. {
  310. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  311. uint32_t num_segs = tso_info.num_segs;
  312. while (num_segs) {
  313. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  314. curr_seg = curr_seg->next;
  315. num_segs--;
  316. }
  317. }
  318. #else
  319. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  320. {
  321. return DP_TX_DESC_INVAL_EVT;
  322. }
  323. static inline void
  324. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  325. qdf_nbuf_t skb, uint32_t sw_cookie,
  326. enum dp_tx_event_type type)
  327. {
  328. }
  329. static inline void
  330. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  331. struct qdf_tso_seg_elem_t *tso_seg,
  332. qdf_nbuf_t skb, uint32_t sw_cookie,
  333. enum dp_tx_event_type type)
  334. {
  335. }
  336. static inline void
  337. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  338. qdf_nbuf_t skb, uint32_t sw_cookie,
  339. enum dp_tx_event_type type)
  340. {
  341. }
  342. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  343. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  344. /**
  345. * dp_is_tput_high() - Check if throughput is high
  346. *
  347. * @soc - core txrx main context
  348. *
  349. * The current function is based of the RTPM tput policy variable where RTPM is
  350. * avoided based on throughput.
  351. */
  352. static inline int dp_is_tput_high(struct dp_soc *soc)
  353. {
  354. return dp_get_rtpm_tput_policy_requirement(soc);
  355. }
  356. #if defined(FEATURE_TSO)
  357. /**
  358. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  359. *
  360. * @soc - core txrx main context
  361. * @seg_desc - tso segment descriptor
  362. * @num_seg_desc - tso number segment descriptor
  363. */
  364. static void dp_tx_tso_unmap_segment(
  365. struct dp_soc *soc,
  366. struct qdf_tso_seg_elem_t *seg_desc,
  367. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  368. {
  369. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  370. if (qdf_unlikely(!seg_desc)) {
  371. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  372. __func__, __LINE__);
  373. qdf_assert(0);
  374. } else if (qdf_unlikely(!num_seg_desc)) {
  375. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  376. __func__, __LINE__);
  377. qdf_assert(0);
  378. } else {
  379. bool is_last_seg;
  380. /* no tso segment left to do dma unmap */
  381. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  382. return;
  383. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  384. true : false;
  385. qdf_nbuf_unmap_tso_segment(soc->osdev,
  386. seg_desc, is_last_seg);
  387. num_seg_desc->num_seg.tso_cmn_num_seg--;
  388. }
  389. }
  390. /**
  391. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  392. * back to the freelist
  393. *
  394. * @soc - soc device handle
  395. * @tx_desc - Tx software descriptor
  396. */
  397. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  398. struct dp_tx_desc_s *tx_desc)
  399. {
  400. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  401. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  402. dp_tx_err("SO desc is NULL!");
  403. qdf_assert(0);
  404. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  405. dp_tx_err("TSO num desc is NULL!");
  406. qdf_assert(0);
  407. } else {
  408. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  409. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  410. msdu_ext_desc->tso_num_desc;
  411. /* Add the tso num segment into the free list */
  412. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  413. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  414. tx_desc->msdu_ext_desc->
  415. tso_num_desc);
  416. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  417. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  418. }
  419. /* Add the tso segment into the free list*/
  420. dp_tx_tso_desc_free(soc,
  421. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  422. tso_desc);
  423. tx_desc->msdu_ext_desc->tso_desc = NULL;
  424. }
  425. }
  426. #else
  427. static void dp_tx_tso_unmap_segment(
  428. struct dp_soc *soc,
  429. struct qdf_tso_seg_elem_t *seg_desc,
  430. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  431. {
  432. }
  433. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  434. struct dp_tx_desc_s *tx_desc)
  435. {
  436. }
  437. #endif
  438. /**
  439. * dp_tx_desc_release() - Release Tx Descriptor
  440. * @tx_desc : Tx Descriptor
  441. * @desc_pool_id: Descriptor Pool ID
  442. *
  443. * Deallocate all resources attached to Tx descriptor and free the Tx
  444. * descriptor.
  445. *
  446. * Return:
  447. */
  448. void
  449. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  450. {
  451. struct dp_pdev *pdev = tx_desc->pdev;
  452. struct dp_soc *soc;
  453. uint8_t comp_status = 0;
  454. qdf_assert(pdev);
  455. soc = pdev->soc;
  456. dp_tx_outstanding_dec(pdev);
  457. if (tx_desc->msdu_ext_desc) {
  458. if (tx_desc->frm_type == dp_tx_frm_tso)
  459. dp_tx_tso_desc_release(soc, tx_desc);
  460. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  461. dp_tx_me_free_buf(tx_desc->pdev,
  462. tx_desc->msdu_ext_desc->me_buffer);
  463. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  464. }
  465. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  466. qdf_atomic_dec(&soc->num_tx_exception);
  467. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  468. tx_desc->buffer_src)
  469. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  470. soc->hal_soc);
  471. else
  472. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  473. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  474. tx_desc->id, comp_status,
  475. qdf_atomic_read(&pdev->num_tx_outstanding));
  476. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  477. return;
  478. }
  479. /**
  480. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  481. * @vdev: DP vdev Handle
  482. * @nbuf: skb
  483. * @msdu_info: msdu_info required to create HTT metadata
  484. *
  485. * Prepares and fills HTT metadata in the frame pre-header for special frames
  486. * that should be transmitted using varying transmit parameters.
  487. * There are 2 VDEV modes that currently needs this special metadata -
  488. * 1) Mesh Mode
  489. * 2) DSRC Mode
  490. *
  491. * Return: HTT metadata size
  492. *
  493. */
  494. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  495. struct dp_tx_msdu_info_s *msdu_info)
  496. {
  497. uint32_t *meta_data = msdu_info->meta_data;
  498. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  499. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  500. uint8_t htt_desc_size;
  501. /* Size rounded of multiple of 8 bytes */
  502. uint8_t htt_desc_size_aligned;
  503. uint8_t *hdr = NULL;
  504. /*
  505. * Metadata - HTT MSDU Extension header
  506. */
  507. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  508. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  509. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  510. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  511. meta_data[0])) {
  512. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  513. htt_desc_size_aligned)) {
  514. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  515. htt_desc_size_aligned);
  516. if (!nbuf) {
  517. /*
  518. * qdf_nbuf_realloc_headroom won't do skb_clone
  519. * as skb_realloc_headroom does. so, no free is
  520. * needed here.
  521. */
  522. DP_STATS_INC(vdev,
  523. tx_i.dropped.headroom_insufficient,
  524. 1);
  525. qdf_print(" %s[%d] skb_realloc_headroom failed",
  526. __func__, __LINE__);
  527. return 0;
  528. }
  529. }
  530. /* Fill and add HTT metaheader */
  531. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  532. if (!hdr) {
  533. dp_tx_err("Error in filling HTT metadata");
  534. return 0;
  535. }
  536. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  537. } else if (vdev->opmode == wlan_op_mode_ocb) {
  538. /* Todo - Add support for DSRC */
  539. }
  540. return htt_desc_size_aligned;
  541. }
  542. /**
  543. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  544. * @tso_seg: TSO segment to process
  545. * @ext_desc: Pointer to MSDU extension descriptor
  546. *
  547. * Return: void
  548. */
  549. #if defined(FEATURE_TSO)
  550. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  551. void *ext_desc)
  552. {
  553. uint8_t num_frag;
  554. uint32_t tso_flags;
  555. /*
  556. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  557. * tcp_flag_mask
  558. *
  559. * Checksum enable flags are set in TCL descriptor and not in Extension
  560. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  561. */
  562. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  563. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  564. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  565. tso_seg->tso_flags.ip_len);
  566. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  567. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  568. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  569. uint32_t lo = 0;
  570. uint32_t hi = 0;
  571. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  572. (tso_seg->tso_frags[num_frag].length));
  573. qdf_dmaaddr_to_32s(
  574. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  575. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  576. tso_seg->tso_frags[num_frag].length);
  577. }
  578. return;
  579. }
  580. #else
  581. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  582. void *ext_desc)
  583. {
  584. return;
  585. }
  586. #endif
  587. #if defined(FEATURE_TSO)
  588. /**
  589. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  590. * allocated and free them
  591. *
  592. * @soc: soc handle
  593. * @free_seg: list of tso segments
  594. * @msdu_info: msdu descriptor
  595. *
  596. * Return - void
  597. */
  598. static void dp_tx_free_tso_seg_list(
  599. struct dp_soc *soc,
  600. struct qdf_tso_seg_elem_t *free_seg,
  601. struct dp_tx_msdu_info_s *msdu_info)
  602. {
  603. struct qdf_tso_seg_elem_t *next_seg;
  604. while (free_seg) {
  605. next_seg = free_seg->next;
  606. dp_tx_tso_desc_free(soc,
  607. msdu_info->tx_queue.desc_pool_id,
  608. free_seg);
  609. free_seg = next_seg;
  610. }
  611. }
  612. /**
  613. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  614. * allocated and free them
  615. *
  616. * @soc: soc handle
  617. * @free_num_seg: list of tso number segments
  618. * @msdu_info: msdu descriptor
  619. * Return - void
  620. */
  621. static void dp_tx_free_tso_num_seg_list(
  622. struct dp_soc *soc,
  623. struct qdf_tso_num_seg_elem_t *free_num_seg,
  624. struct dp_tx_msdu_info_s *msdu_info)
  625. {
  626. struct qdf_tso_num_seg_elem_t *next_num_seg;
  627. while (free_num_seg) {
  628. next_num_seg = free_num_seg->next;
  629. dp_tso_num_seg_free(soc,
  630. msdu_info->tx_queue.desc_pool_id,
  631. free_num_seg);
  632. free_num_seg = next_num_seg;
  633. }
  634. }
  635. /**
  636. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  637. * do dma unmap for each segment
  638. *
  639. * @soc: soc handle
  640. * @free_seg: list of tso segments
  641. * @num_seg_desc: tso number segment descriptor
  642. *
  643. * Return - void
  644. */
  645. static void dp_tx_unmap_tso_seg_list(
  646. struct dp_soc *soc,
  647. struct qdf_tso_seg_elem_t *free_seg,
  648. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  649. {
  650. struct qdf_tso_seg_elem_t *next_seg;
  651. if (qdf_unlikely(!num_seg_desc)) {
  652. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  653. return;
  654. }
  655. while (free_seg) {
  656. next_seg = free_seg->next;
  657. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  658. free_seg = next_seg;
  659. }
  660. }
  661. #ifdef FEATURE_TSO_STATS
  662. /**
  663. * dp_tso_get_stats_idx: Retrieve the tso packet id
  664. * @pdev - pdev handle
  665. *
  666. * Return: id
  667. */
  668. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  669. {
  670. uint32_t stats_idx;
  671. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  672. % CDP_MAX_TSO_PACKETS);
  673. return stats_idx;
  674. }
  675. #else
  676. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  677. {
  678. return 0;
  679. }
  680. #endif /* FEATURE_TSO_STATS */
  681. /**
  682. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  683. * free the tso segments descriptor and
  684. * tso num segments descriptor
  685. *
  686. * @soc: soc handle
  687. * @msdu_info: msdu descriptor
  688. * @tso_seg_unmap: flag to show if dma unmap is necessary
  689. *
  690. * Return - void
  691. */
  692. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  693. struct dp_tx_msdu_info_s *msdu_info,
  694. bool tso_seg_unmap)
  695. {
  696. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  697. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  698. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  699. tso_info->tso_num_seg_list;
  700. /* do dma unmap for each segment */
  701. if (tso_seg_unmap)
  702. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  703. /* free all tso number segment descriptor though looks only have 1 */
  704. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  705. /* free all tso segment descriptor */
  706. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  707. }
  708. /**
  709. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  710. * @vdev: virtual device handle
  711. * @msdu: network buffer
  712. * @msdu_info: meta data associated with the msdu
  713. *
  714. * Return: QDF_STATUS_SUCCESS success
  715. */
  716. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  717. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  718. {
  719. struct qdf_tso_seg_elem_t *tso_seg;
  720. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  721. struct dp_soc *soc = vdev->pdev->soc;
  722. struct dp_pdev *pdev = vdev->pdev;
  723. struct qdf_tso_info_t *tso_info;
  724. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  725. tso_info = &msdu_info->u.tso_info;
  726. tso_info->curr_seg = NULL;
  727. tso_info->tso_seg_list = NULL;
  728. tso_info->num_segs = num_seg;
  729. msdu_info->frm_type = dp_tx_frm_tso;
  730. tso_info->tso_num_seg_list = NULL;
  731. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  732. while (num_seg) {
  733. tso_seg = dp_tx_tso_desc_alloc(
  734. soc, msdu_info->tx_queue.desc_pool_id);
  735. if (tso_seg) {
  736. tso_seg->next = tso_info->tso_seg_list;
  737. tso_info->tso_seg_list = tso_seg;
  738. num_seg--;
  739. } else {
  740. dp_err_rl("Failed to alloc tso seg desc");
  741. DP_STATS_INC_PKT(vdev->pdev,
  742. tso_stats.tso_no_mem_dropped, 1,
  743. qdf_nbuf_len(msdu));
  744. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  745. return QDF_STATUS_E_NOMEM;
  746. }
  747. }
  748. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  749. tso_num_seg = dp_tso_num_seg_alloc(soc,
  750. msdu_info->tx_queue.desc_pool_id);
  751. if (tso_num_seg) {
  752. tso_num_seg->next = tso_info->tso_num_seg_list;
  753. tso_info->tso_num_seg_list = tso_num_seg;
  754. } else {
  755. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  756. __func__);
  757. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  758. return QDF_STATUS_E_NOMEM;
  759. }
  760. msdu_info->num_seg =
  761. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  762. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  763. msdu_info->num_seg);
  764. if (!(msdu_info->num_seg)) {
  765. /*
  766. * Free allocated TSO seg desc and number seg desc,
  767. * do unmap for segments if dma map has done.
  768. */
  769. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  770. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  771. return QDF_STATUS_E_INVAL;
  772. }
  773. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  774. msdu, 0, DP_TX_DESC_MAP);
  775. tso_info->curr_seg = tso_info->tso_seg_list;
  776. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  777. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  778. msdu, msdu_info->num_seg);
  779. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  780. tso_info->msdu_stats_idx);
  781. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  782. return QDF_STATUS_SUCCESS;
  783. }
  784. #else
  785. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  786. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  787. {
  788. return QDF_STATUS_E_NOMEM;
  789. }
  790. #endif
  791. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  792. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  793. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  794. /**
  795. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  796. * @vdev: DP Vdev handle
  797. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  798. * @desc_pool_id: Descriptor Pool ID
  799. *
  800. * Return:
  801. */
  802. static
  803. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  804. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  805. {
  806. uint8_t i;
  807. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  808. struct dp_tx_seg_info_s *seg_info;
  809. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  810. struct dp_soc *soc = vdev->pdev->soc;
  811. /* Allocate an extension descriptor */
  812. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  813. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  814. if (!msdu_ext_desc) {
  815. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  816. return NULL;
  817. }
  818. if (msdu_info->exception_fw &&
  819. qdf_unlikely(vdev->mesh_vdev)) {
  820. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  821. &msdu_info->meta_data[0],
  822. sizeof(struct htt_tx_msdu_desc_ext2_t));
  823. qdf_atomic_inc(&soc->num_tx_exception);
  824. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  825. }
  826. switch (msdu_info->frm_type) {
  827. case dp_tx_frm_sg:
  828. case dp_tx_frm_me:
  829. case dp_tx_frm_raw:
  830. seg_info = msdu_info->u.sg_info.curr_seg;
  831. /* Update the buffer pointers in MSDU Extension Descriptor */
  832. for (i = 0; i < seg_info->frag_cnt; i++) {
  833. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  834. seg_info->frags[i].paddr_lo,
  835. seg_info->frags[i].paddr_hi,
  836. seg_info->frags[i].len);
  837. }
  838. break;
  839. case dp_tx_frm_tso:
  840. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  841. &cached_ext_desc[0]);
  842. break;
  843. default:
  844. break;
  845. }
  846. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  847. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  848. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  849. msdu_ext_desc->vaddr);
  850. return msdu_ext_desc;
  851. }
  852. /**
  853. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  854. *
  855. * @skb: skb to be traced
  856. * @msdu_id: msdu_id of the packet
  857. * @vdev_id: vdev_id of the packet
  858. *
  859. * Return: None
  860. */
  861. #ifdef DP_DISABLE_TX_PKT_TRACE
  862. static void dp_tx_trace_pkt(struct dp_soc *soc,
  863. qdf_nbuf_t skb, uint16_t msdu_id,
  864. uint8_t vdev_id)
  865. {
  866. }
  867. #else
  868. static void dp_tx_trace_pkt(struct dp_soc *soc,
  869. qdf_nbuf_t skb, uint16_t msdu_id,
  870. uint8_t vdev_id)
  871. {
  872. if (dp_is_tput_high(soc))
  873. return;
  874. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  875. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  876. DPTRACE(qdf_dp_trace_ptr(skb,
  877. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  878. QDF_TRACE_DEFAULT_PDEV_ID,
  879. qdf_nbuf_data_addr(skb),
  880. sizeof(qdf_nbuf_data(skb)),
  881. msdu_id, vdev_id, 0));
  882. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  883. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  884. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  885. msdu_id, QDF_TX));
  886. }
  887. #endif
  888. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  889. /**
  890. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  891. * exception by the upper layer (OS_IF)
  892. * @soc: DP soc handle
  893. * @nbuf: packet to be transmitted
  894. *
  895. * Returns: 1 if the packet is marked as exception,
  896. * 0, if the packet is not marked as exception.
  897. */
  898. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  899. qdf_nbuf_t nbuf)
  900. {
  901. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  902. }
  903. #else
  904. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  905. qdf_nbuf_t nbuf)
  906. {
  907. return 0;
  908. }
  909. #endif
  910. /**
  911. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  912. * @vdev: DP vdev handle
  913. * @nbuf: skb
  914. * @desc_pool_id: Descriptor pool ID
  915. * @meta_data: Metadata to the fw
  916. * @tx_exc_metadata: Handle that holds exception path metadata
  917. * Allocate and prepare Tx descriptor with msdu information.
  918. *
  919. * Return: Pointer to Tx Descriptor on success,
  920. * NULL on failure
  921. */
  922. static
  923. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  924. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  925. struct dp_tx_msdu_info_s *msdu_info,
  926. struct cdp_tx_exception_metadata *tx_exc_metadata)
  927. {
  928. uint8_t align_pad;
  929. uint8_t is_exception = 0;
  930. uint8_t htt_hdr_size;
  931. struct dp_tx_desc_s *tx_desc;
  932. struct dp_pdev *pdev = vdev->pdev;
  933. struct dp_soc *soc = pdev->soc;
  934. if (dp_tx_limit_check(vdev))
  935. return NULL;
  936. /* Allocate software Tx descriptor */
  937. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  938. if (qdf_unlikely(!tx_desc)) {
  939. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  940. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  941. return NULL;
  942. }
  943. dp_tx_outstanding_inc(pdev);
  944. /* Initialize the SW tx descriptor */
  945. tx_desc->nbuf = nbuf;
  946. tx_desc->frm_type = dp_tx_frm_std;
  947. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  948. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  949. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  950. tx_desc->vdev_id = vdev->vdev_id;
  951. tx_desc->pdev = pdev;
  952. tx_desc->msdu_ext_desc = NULL;
  953. tx_desc->pkt_offset = 0;
  954. tx_desc->length = qdf_nbuf_headlen(nbuf);
  955. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  956. if (qdf_unlikely(vdev->multipass_en)) {
  957. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  958. goto failure;
  959. }
  960. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  961. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  962. is_exception = 1;
  963. /*
  964. * For special modes (vdev_type == ocb or mesh), data frames should be
  965. * transmitted using varying transmit parameters (tx spec) which include
  966. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  967. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  968. * These frames are sent as exception packets to firmware.
  969. *
  970. * HW requirement is that metadata should always point to a
  971. * 8-byte aligned address. So we add alignment pad to start of buffer.
  972. * HTT Metadata should be ensured to be multiple of 8-bytes,
  973. * to get 8-byte aligned start address along with align_pad added
  974. *
  975. * |-----------------------------|
  976. * | |
  977. * |-----------------------------| <-----Buffer Pointer Address given
  978. * | | ^ in HW descriptor (aligned)
  979. * | HTT Metadata | |
  980. * | | |
  981. * | | | Packet Offset given in descriptor
  982. * | | |
  983. * |-----------------------------| |
  984. * | Alignment Pad | v
  985. * |-----------------------------| <----- Actual buffer start address
  986. * | SKB Data | (Unaligned)
  987. * | |
  988. * | |
  989. * | |
  990. * | |
  991. * | |
  992. * |-----------------------------|
  993. */
  994. if (qdf_unlikely((msdu_info->exception_fw)) ||
  995. (vdev->opmode == wlan_op_mode_ocb) ||
  996. (tx_exc_metadata &&
  997. tx_exc_metadata->is_tx_sniffer)) {
  998. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  999. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1000. DP_STATS_INC(vdev,
  1001. tx_i.dropped.headroom_insufficient, 1);
  1002. goto failure;
  1003. }
  1004. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1005. dp_tx_err("qdf_nbuf_push_head failed");
  1006. goto failure;
  1007. }
  1008. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1009. msdu_info);
  1010. if (htt_hdr_size == 0)
  1011. goto failure;
  1012. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1013. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1014. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1015. is_exception = 1;
  1016. tx_desc->length -= tx_desc->pkt_offset;
  1017. }
  1018. #if !TQM_BYPASS_WAR
  1019. if (is_exception || tx_exc_metadata)
  1020. #endif
  1021. {
  1022. /* Temporary WAR due to TQM VP issues */
  1023. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1024. qdf_atomic_inc(&soc->num_tx_exception);
  1025. }
  1026. return tx_desc;
  1027. failure:
  1028. dp_tx_desc_release(tx_desc, desc_pool_id);
  1029. return NULL;
  1030. }
  1031. /**
  1032. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1033. * @vdev: DP vdev handle
  1034. * @nbuf: skb
  1035. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1036. * @desc_pool_id : Descriptor Pool ID
  1037. *
  1038. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1039. * information. For frames wth fragments, allocate and prepare
  1040. * an MSDU extension descriptor
  1041. *
  1042. * Return: Pointer to Tx Descriptor on success,
  1043. * NULL on failure
  1044. */
  1045. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1046. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1047. uint8_t desc_pool_id)
  1048. {
  1049. struct dp_tx_desc_s *tx_desc;
  1050. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1051. struct dp_pdev *pdev = vdev->pdev;
  1052. struct dp_soc *soc = pdev->soc;
  1053. if (dp_tx_limit_check(vdev))
  1054. return NULL;
  1055. /* Allocate software Tx descriptor */
  1056. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1057. if (!tx_desc) {
  1058. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1059. return NULL;
  1060. }
  1061. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1062. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1063. dp_tx_outstanding_inc(pdev);
  1064. /* Initialize the SW tx descriptor */
  1065. tx_desc->nbuf = nbuf;
  1066. tx_desc->frm_type = msdu_info->frm_type;
  1067. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1068. tx_desc->vdev_id = vdev->vdev_id;
  1069. tx_desc->pdev = pdev;
  1070. tx_desc->pkt_offset = 0;
  1071. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1072. /* Handle scattered frames - TSO/SG/ME */
  1073. /* Allocate and prepare an extension descriptor for scattered frames */
  1074. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1075. if (!msdu_ext_desc) {
  1076. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1077. goto failure;
  1078. }
  1079. #if TQM_BYPASS_WAR
  1080. /* Temporary WAR due to TQM VP issues */
  1081. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1082. qdf_atomic_inc(&soc->num_tx_exception);
  1083. #endif
  1084. if (qdf_unlikely(msdu_info->exception_fw))
  1085. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1086. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1087. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1088. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1089. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1090. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1091. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1092. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1093. else
  1094. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1095. return tx_desc;
  1096. failure:
  1097. dp_tx_desc_release(tx_desc, desc_pool_id);
  1098. return NULL;
  1099. }
  1100. /**
  1101. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1102. * @vdev: DP vdev handle
  1103. * @nbuf: buffer pointer
  1104. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1105. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1106. * descriptor
  1107. *
  1108. * Return:
  1109. */
  1110. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1111. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1112. {
  1113. qdf_nbuf_t curr_nbuf = NULL;
  1114. uint16_t total_len = 0;
  1115. qdf_dma_addr_t paddr;
  1116. int32_t i;
  1117. int32_t mapped_buf_num = 0;
  1118. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1119. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1120. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1121. /* Continue only if frames are of DATA type */
  1122. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1123. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1124. dp_tx_debug("Pkt. recd is of not data type");
  1125. goto error;
  1126. }
  1127. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1128. if (vdev->raw_mode_war &&
  1129. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1130. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1131. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1132. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1133. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1134. /*
  1135. * Number of nbuf's must not exceed the size of the frags
  1136. * array in seg_info.
  1137. */
  1138. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1139. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1140. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1141. goto error;
  1142. }
  1143. if (QDF_STATUS_SUCCESS !=
  1144. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1145. curr_nbuf,
  1146. QDF_DMA_TO_DEVICE,
  1147. curr_nbuf->len)) {
  1148. dp_tx_err("%s dma map error ", __func__);
  1149. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1150. goto error;
  1151. }
  1152. /* Update the count of mapped nbuf's */
  1153. mapped_buf_num++;
  1154. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1155. seg_info->frags[i].paddr_lo = paddr;
  1156. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1157. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1158. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1159. total_len += qdf_nbuf_len(curr_nbuf);
  1160. }
  1161. seg_info->frag_cnt = i;
  1162. seg_info->total_len = total_len;
  1163. seg_info->next = NULL;
  1164. sg_info->curr_seg = seg_info;
  1165. msdu_info->frm_type = dp_tx_frm_raw;
  1166. msdu_info->num_seg = 1;
  1167. return nbuf;
  1168. error:
  1169. i = 0;
  1170. while (nbuf) {
  1171. curr_nbuf = nbuf;
  1172. if (i < mapped_buf_num) {
  1173. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1174. QDF_DMA_TO_DEVICE,
  1175. curr_nbuf->len);
  1176. i++;
  1177. }
  1178. nbuf = qdf_nbuf_next(nbuf);
  1179. qdf_nbuf_free(curr_nbuf);
  1180. }
  1181. return NULL;
  1182. }
  1183. /**
  1184. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1185. * @soc: DP soc handle
  1186. * @nbuf: Buffer pointer
  1187. *
  1188. * unmap the chain of nbufs that belong to this RAW frame.
  1189. *
  1190. * Return: None
  1191. */
  1192. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1193. qdf_nbuf_t nbuf)
  1194. {
  1195. qdf_nbuf_t cur_nbuf = nbuf;
  1196. do {
  1197. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1198. QDF_DMA_TO_DEVICE,
  1199. cur_nbuf->len);
  1200. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1201. } while (cur_nbuf);
  1202. }
  1203. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1204. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1205. qdf_nbuf_t nbuf)
  1206. {
  1207. qdf_nbuf_t nbuf_local;
  1208. struct dp_vdev *vdev_local = vdev_hdl;
  1209. do {
  1210. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1211. break;
  1212. nbuf_local = nbuf;
  1213. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1214. htt_cmn_pkt_type_raw))
  1215. break;
  1216. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1217. break;
  1218. else if (qdf_nbuf_is_tso((nbuf_local)))
  1219. break;
  1220. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1221. (nbuf_local),
  1222. NULL, 1, 0);
  1223. } while (0);
  1224. }
  1225. #endif
  1226. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1227. /**
  1228. * dp_tx_update_stats() - Update soc level tx stats
  1229. * @soc: DP soc handle
  1230. * @nbuf: packet being transmitted
  1231. *
  1232. * Returns: none
  1233. */
  1234. void dp_tx_update_stats(struct dp_soc *soc,
  1235. qdf_nbuf_t nbuf)
  1236. {
  1237. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1238. }
  1239. int
  1240. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1241. struct dp_tx_desc_s *tx_desc,
  1242. uint8_t tid,
  1243. struct dp_tx_msdu_info_s *msdu_info)
  1244. {
  1245. struct dp_swlm *swlm = &soc->swlm;
  1246. union swlm_data swlm_query_data;
  1247. struct dp_swlm_tcl_data tcl_data;
  1248. QDF_STATUS status;
  1249. int ret;
  1250. if (!swlm->is_enabled)
  1251. return msdu_info->skip_hp_update;
  1252. tcl_data.nbuf = tx_desc->nbuf;
  1253. tcl_data.tid = tid;
  1254. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1255. swlm_query_data.tcl_data = &tcl_data;
  1256. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1257. if (QDF_IS_STATUS_ERROR(status)) {
  1258. dp_swlm_tcl_reset_session_data(soc);
  1259. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1260. return 0;
  1261. }
  1262. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1263. if (ret) {
  1264. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1265. } else {
  1266. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1267. }
  1268. return ret;
  1269. }
  1270. void
  1271. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1272. int coalesce)
  1273. {
  1274. if (coalesce)
  1275. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1276. else
  1277. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1278. }
  1279. static inline void
  1280. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1281. {
  1282. if (((i + 1) < msdu_info->num_seg))
  1283. msdu_info->skip_hp_update = 1;
  1284. else
  1285. msdu_info->skip_hp_update = 0;
  1286. }
  1287. static inline void
  1288. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1289. {
  1290. hal_ring_handle_t hal_ring_hdl =
  1291. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1292. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1293. dp_err("Fillmore: SRNG access start failed");
  1294. return;
  1295. }
  1296. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1297. }
  1298. static inline void
  1299. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1300. QDF_STATUS status,
  1301. struct dp_tx_msdu_info_s *msdu_info)
  1302. {
  1303. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1304. dp_flush_tcp_hp(soc,
  1305. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1306. }
  1307. }
  1308. #else
  1309. static inline void
  1310. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1311. {
  1312. }
  1313. static inline void
  1314. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1315. QDF_STATUS status,
  1316. struct dp_tx_msdu_info_s *msdu_info)
  1317. {
  1318. }
  1319. #endif
  1320. #ifdef FEATURE_RUNTIME_PM
  1321. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1322. {
  1323. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1324. }
  1325. /**
  1326. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1327. * @soc: Datapath soc handle
  1328. * @hal_ring_hdl: HAL ring handle
  1329. * @coalesce: Coalesce the current write or not
  1330. *
  1331. * Wrapper for HAL ring access end for data transmission for
  1332. * FEATURE_RUNTIME_PM
  1333. *
  1334. * Returns: none
  1335. */
  1336. void
  1337. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1338. hal_ring_handle_t hal_ring_hdl,
  1339. int coalesce)
  1340. {
  1341. int ret;
  1342. /*
  1343. * Avoid runtime get and put APIs under high throughput scenarios.
  1344. */
  1345. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1346. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1347. return;
  1348. }
  1349. ret = hif_pm_runtime_get(soc->hif_handle,
  1350. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1351. switch (ret) {
  1352. case 0:
  1353. if (hif_system_pm_state_check(soc->hif_handle)) {
  1354. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1355. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1356. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1357. } else {
  1358. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1359. }
  1360. hif_pm_runtime_put(soc->hif_handle,
  1361. RTPM_ID_DW_TX_HW_ENQUEUE);
  1362. break;
  1363. /*
  1364. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1365. * take the dp runtime refcount using dp_runtime_get,
  1366. * check link state,if up, write TX ring HP, else just set flush event.
  1367. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1368. * zero or time out, then flush pending tx.
  1369. */
  1370. case -EBUSY:
  1371. case -EINPROGRESS:
  1372. dp_runtime_get(soc);
  1373. if (hif_pm_get_link_state(soc->hif_handle) ==
  1374. HIF_PM_LINK_STATE_UP) {
  1375. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1376. } else {
  1377. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1378. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1379. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1380. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1381. }
  1382. dp_runtime_put(soc);
  1383. break;
  1384. default:
  1385. dp_runtime_get(soc);
  1386. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1387. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1388. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1389. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1390. dp_runtime_put(soc);
  1391. }
  1392. }
  1393. #else
  1394. #ifdef DP_POWER_SAVE
  1395. void
  1396. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1397. hal_ring_handle_t hal_ring_hdl,
  1398. int coalesce)
  1399. {
  1400. if (hif_system_pm_state_check(soc->hif_handle)) {
  1401. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1402. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1403. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1404. } else {
  1405. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1406. }
  1407. }
  1408. #endif
  1409. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1410. {
  1411. return 0;
  1412. }
  1413. #endif
  1414. /**
  1415. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1416. * @vdev: DP vdev handle
  1417. * @nbuf: skb
  1418. *
  1419. * Extract the DSCP or PCP information from frame and map into TID value.
  1420. *
  1421. * Return: void
  1422. */
  1423. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1424. struct dp_tx_msdu_info_s *msdu_info)
  1425. {
  1426. uint8_t tos = 0, dscp_tid_override = 0;
  1427. uint8_t *hdr_ptr, *L3datap;
  1428. uint8_t is_mcast = 0;
  1429. qdf_ether_header_t *eh = NULL;
  1430. qdf_ethervlan_header_t *evh = NULL;
  1431. uint16_t ether_type;
  1432. qdf_llc_t *llcHdr;
  1433. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1434. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1435. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1436. eh = (qdf_ether_header_t *)nbuf->data;
  1437. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1438. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1439. } else {
  1440. qdf_dot3_qosframe_t *qos_wh =
  1441. (qdf_dot3_qosframe_t *) nbuf->data;
  1442. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1443. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1444. return;
  1445. }
  1446. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1447. ether_type = eh->ether_type;
  1448. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1449. /*
  1450. * Check if packet is dot3 or eth2 type.
  1451. */
  1452. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1453. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1454. sizeof(*llcHdr));
  1455. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1456. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1457. sizeof(*llcHdr);
  1458. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1459. + sizeof(*llcHdr) +
  1460. sizeof(qdf_net_vlanhdr_t));
  1461. } else {
  1462. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1463. sizeof(*llcHdr);
  1464. }
  1465. } else {
  1466. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1467. evh = (qdf_ethervlan_header_t *) eh;
  1468. ether_type = evh->ether_type;
  1469. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1470. }
  1471. }
  1472. /*
  1473. * Find priority from IP TOS DSCP field
  1474. */
  1475. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1476. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1477. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1478. /* Only for unicast frames */
  1479. if (!is_mcast) {
  1480. /* send it on VO queue */
  1481. msdu_info->tid = DP_VO_TID;
  1482. }
  1483. } else {
  1484. /*
  1485. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1486. * from TOS byte.
  1487. */
  1488. tos = ip->ip_tos;
  1489. dscp_tid_override = 1;
  1490. }
  1491. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1492. /* TODO
  1493. * use flowlabel
  1494. *igmpmld cases to be handled in phase 2
  1495. */
  1496. unsigned long ver_pri_flowlabel;
  1497. unsigned long pri;
  1498. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1499. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1500. DP_IPV6_PRIORITY_SHIFT;
  1501. tos = pri;
  1502. dscp_tid_override = 1;
  1503. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1504. msdu_info->tid = DP_VO_TID;
  1505. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1506. /* Only for unicast frames */
  1507. if (!is_mcast) {
  1508. /* send ucast arp on VO queue */
  1509. msdu_info->tid = DP_VO_TID;
  1510. }
  1511. }
  1512. /*
  1513. * Assign all MCAST packets to BE
  1514. */
  1515. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1516. if (is_mcast) {
  1517. tos = 0;
  1518. dscp_tid_override = 1;
  1519. }
  1520. }
  1521. if (dscp_tid_override == 1) {
  1522. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1523. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1524. }
  1525. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1526. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1527. return;
  1528. }
  1529. /**
  1530. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1531. * @vdev: DP vdev handle
  1532. * @nbuf: skb
  1533. *
  1534. * Software based TID classification is required when more than 2 DSCP-TID
  1535. * mapping tables are needed.
  1536. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1537. *
  1538. * Return: void
  1539. */
  1540. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1541. struct dp_tx_msdu_info_s *msdu_info)
  1542. {
  1543. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1544. /*
  1545. * skip_sw_tid_classification flag will set in below cases-
  1546. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1547. * 2. hlos_tid_override enabled for vdev
  1548. * 3. mesh mode enabled for vdev
  1549. */
  1550. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1551. /* Update tid in msdu_info from skb priority */
  1552. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1553. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1554. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1555. if (tid == DP_TX_INVALID_QOS_TAG)
  1556. return;
  1557. msdu_info->tid = tid;
  1558. return;
  1559. }
  1560. return;
  1561. }
  1562. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1563. }
  1564. #ifdef FEATURE_WLAN_TDLS
  1565. /**
  1566. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1567. * @soc: datapath SOC
  1568. * @vdev: datapath vdev
  1569. * @tx_desc: TX descriptor
  1570. *
  1571. * Return: None
  1572. */
  1573. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1574. struct dp_vdev *vdev,
  1575. struct dp_tx_desc_s *tx_desc)
  1576. {
  1577. if (vdev) {
  1578. if (vdev->is_tdls_frame) {
  1579. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1580. vdev->is_tdls_frame = false;
  1581. }
  1582. }
  1583. }
  1584. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1585. {
  1586. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1587. switch (soc->arch_id) {
  1588. case CDP_ARCH_TYPE_LI:
  1589. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1590. break;
  1591. case CDP_ARCH_TYPE_BE:
  1592. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1593. break;
  1594. default:
  1595. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1596. QDF_BUG(0);
  1597. }
  1598. return tx_status;
  1599. }
  1600. /**
  1601. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1602. * @soc: dp_soc handle
  1603. * @tx_desc: TX descriptor
  1604. * @vdev: datapath vdev handle
  1605. *
  1606. * Return: None
  1607. */
  1608. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1609. struct dp_tx_desc_s *tx_desc)
  1610. {
  1611. uint8_t tx_status = 0;
  1612. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1613. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1614. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1615. DP_MOD_ID_TDLS);
  1616. if (qdf_unlikely(!vdev)) {
  1617. dp_err_rl("vdev is null!");
  1618. goto error;
  1619. }
  1620. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1621. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1622. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1623. if (vdev->tx_non_std_data_callback.func) {
  1624. qdf_nbuf_set_next(nbuf, NULL);
  1625. vdev->tx_non_std_data_callback.func(
  1626. vdev->tx_non_std_data_callback.ctxt,
  1627. nbuf, tx_status);
  1628. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1629. return;
  1630. } else {
  1631. dp_err_rl("callback func is null");
  1632. }
  1633. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1634. error:
  1635. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1636. qdf_nbuf_free(nbuf);
  1637. }
  1638. /**
  1639. * dp_tx_msdu_single_map() - do nbuf map
  1640. * @vdev: DP vdev handle
  1641. * @tx_desc: DP TX descriptor pointer
  1642. * @nbuf: skb pointer
  1643. *
  1644. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1645. * operation done in other component.
  1646. *
  1647. * Return: QDF_STATUS
  1648. */
  1649. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1650. struct dp_tx_desc_s *tx_desc,
  1651. qdf_nbuf_t nbuf)
  1652. {
  1653. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1654. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1655. nbuf,
  1656. QDF_DMA_TO_DEVICE,
  1657. nbuf->len);
  1658. else
  1659. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1660. QDF_DMA_TO_DEVICE);
  1661. }
  1662. #else
  1663. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1664. struct dp_vdev *vdev,
  1665. struct dp_tx_desc_s *tx_desc)
  1666. {
  1667. }
  1668. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1669. struct dp_tx_desc_s *tx_desc)
  1670. {
  1671. }
  1672. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1673. struct dp_tx_desc_s *tx_desc,
  1674. qdf_nbuf_t nbuf)
  1675. {
  1676. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1677. nbuf,
  1678. QDF_DMA_TO_DEVICE,
  1679. nbuf->len);
  1680. }
  1681. #endif
  1682. static inline
  1683. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1684. struct dp_tx_desc_s *tx_desc,
  1685. qdf_nbuf_t nbuf)
  1686. {
  1687. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1688. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1689. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1690. return 0;
  1691. return qdf_nbuf_mapped_paddr_get(nbuf);
  1692. }
  1693. static inline
  1694. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1695. {
  1696. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1697. desc->nbuf,
  1698. desc->dma_addr,
  1699. QDF_DMA_TO_DEVICE,
  1700. desc->length);
  1701. }
  1702. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1703. static inline
  1704. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1705. struct dp_tx_desc_s *tx_desc,
  1706. qdf_nbuf_t nbuf)
  1707. {
  1708. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1709. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1710. (void *)(nbuf->data + nbuf->len));
  1711. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1712. } else {
  1713. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1714. }
  1715. }
  1716. static inline
  1717. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1718. struct dp_tx_desc_s *desc)
  1719. {
  1720. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1721. return dp_tx_nbuf_unmap_regular(soc, desc);
  1722. }
  1723. #else
  1724. static inline
  1725. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1726. struct dp_tx_desc_s *tx_desc,
  1727. qdf_nbuf_t nbuf)
  1728. {
  1729. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1730. }
  1731. static inline
  1732. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1733. struct dp_tx_desc_s *desc)
  1734. {
  1735. return dp_tx_nbuf_unmap_regular(soc, desc);
  1736. }
  1737. #endif
  1738. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1739. static inline
  1740. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1741. {
  1742. dp_tx_nbuf_unmap(soc, desc);
  1743. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1744. }
  1745. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1746. {
  1747. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1748. dp_tx_nbuf_unmap(soc, desc);
  1749. }
  1750. #else
  1751. static inline
  1752. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1753. {
  1754. }
  1755. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1756. {
  1757. dp_tx_nbuf_unmap(soc, desc);
  1758. }
  1759. #endif
  1760. #ifdef MESH_MODE_SUPPORT
  1761. /**
  1762. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1763. * @soc: datapath SOC
  1764. * @vdev: datapath vdev
  1765. * @tx_desc: TX descriptor
  1766. *
  1767. * Return: None
  1768. */
  1769. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1770. struct dp_vdev *vdev,
  1771. struct dp_tx_desc_s *tx_desc)
  1772. {
  1773. if (qdf_unlikely(vdev->mesh_vdev))
  1774. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1775. }
  1776. /**
  1777. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1778. * @soc: dp_soc handle
  1779. * @tx_desc: TX descriptor
  1780. * @vdev: datapath vdev handle
  1781. *
  1782. * Return: None
  1783. */
  1784. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1785. struct dp_tx_desc_s *tx_desc)
  1786. {
  1787. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1788. struct dp_vdev *vdev = NULL;
  1789. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1790. qdf_nbuf_free(nbuf);
  1791. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1792. } else {
  1793. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1794. DP_MOD_ID_MESH);
  1795. if (vdev && vdev->osif_tx_free_ext)
  1796. vdev->osif_tx_free_ext((nbuf));
  1797. else
  1798. qdf_nbuf_free(nbuf);
  1799. if (vdev)
  1800. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1801. }
  1802. }
  1803. #else
  1804. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1805. struct dp_vdev *vdev,
  1806. struct dp_tx_desc_s *tx_desc)
  1807. {
  1808. }
  1809. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1810. struct dp_tx_desc_s *tx_desc)
  1811. {
  1812. }
  1813. #endif
  1814. /**
  1815. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1816. * @vdev: DP vdev handle
  1817. * @nbuf: skb
  1818. *
  1819. * Return: 1 if frame needs to be dropped else 0
  1820. */
  1821. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1822. {
  1823. struct dp_pdev *pdev = NULL;
  1824. struct dp_ast_entry *src_ast_entry = NULL;
  1825. struct dp_ast_entry *dst_ast_entry = NULL;
  1826. struct dp_soc *soc = NULL;
  1827. qdf_assert(vdev);
  1828. pdev = vdev->pdev;
  1829. qdf_assert(pdev);
  1830. soc = pdev->soc;
  1831. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1832. (soc, dstmac, vdev->pdev->pdev_id);
  1833. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1834. (soc, srcmac, vdev->pdev->pdev_id);
  1835. if (dst_ast_entry && src_ast_entry) {
  1836. if (dst_ast_entry->peer_id ==
  1837. src_ast_entry->peer_id)
  1838. return 1;
  1839. }
  1840. return 0;
  1841. }
  1842. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1843. defined(WLAN_MCAST_MLO)
  1844. /* MLO peer id for reinject*/
  1845. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1846. /* MLO vdev id inc offset */
  1847. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1848. static inline void
  1849. dp_tx_update_mcast_param(uint16_t peer_id,
  1850. uint16_t *htt_tcl_metadata,
  1851. struct dp_vdev *vdev,
  1852. struct dp_tx_msdu_info_s *msdu_info)
  1853. {
  1854. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1855. *htt_tcl_metadata = 0;
  1856. DP_TX_TCL_METADATA_TYPE_SET(
  1857. *htt_tcl_metadata,
  1858. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1859. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1860. msdu_info->gsn);
  1861. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1862. } else {
  1863. msdu_info->vdev_id = vdev->vdev_id;
  1864. }
  1865. }
  1866. #else
  1867. static inline void
  1868. dp_tx_update_mcast_param(uint16_t peer_id,
  1869. uint16_t *htt_tcl_metadata,
  1870. struct dp_vdev *vdev,
  1871. struct dp_tx_msdu_info_s *msdu_info)
  1872. {
  1873. }
  1874. #endif
  1875. /**
  1876. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1877. * @vdev: DP vdev handle
  1878. * @nbuf: skb
  1879. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1880. * @meta_data: Metadata to the fw
  1881. * @tx_q: Tx queue to be used for this Tx frame
  1882. * @peer_id: peer_id of the peer in case of NAWDS frames
  1883. * @tx_exc_metadata: Handle that holds exception path metadata
  1884. *
  1885. * Return: NULL on success,
  1886. * nbuf when it fails to send
  1887. */
  1888. qdf_nbuf_t
  1889. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1890. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1891. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1892. {
  1893. struct dp_pdev *pdev = vdev->pdev;
  1894. struct dp_soc *soc = pdev->soc;
  1895. struct dp_tx_desc_s *tx_desc;
  1896. QDF_STATUS status;
  1897. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1898. uint16_t htt_tcl_metadata = 0;
  1899. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1900. uint8_t tid = msdu_info->tid;
  1901. struct cdp_tid_tx_stats *tid_stats = NULL;
  1902. qdf_dma_addr_t paddr;
  1903. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1904. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1905. msdu_info, tx_exc_metadata);
  1906. if (!tx_desc) {
  1907. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1908. vdev, tx_q->desc_pool_id);
  1909. drop_code = TX_DESC_ERR;
  1910. goto fail_return;
  1911. }
  1912. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1913. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1914. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1915. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1916. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1917. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1918. DP_TCL_METADATA_TYPE_PEER_BASED);
  1919. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1920. peer_id);
  1921. } else
  1922. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1923. if (msdu_info->exception_fw)
  1924. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1925. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1926. !pdev->enhanced_stats_en);
  1927. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1928. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  1929. if (!paddr) {
  1930. /* Handle failure */
  1931. dp_err("qdf_nbuf_map failed");
  1932. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1933. drop_code = TX_DMA_MAP_ERR;
  1934. goto release_desc;
  1935. }
  1936. tx_desc->dma_addr = paddr;
  1937. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1938. tx_desc->id, DP_TX_DESC_MAP);
  1939. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  1940. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1941. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1942. htt_tcl_metadata,
  1943. tx_exc_metadata, msdu_info);
  1944. if (status != QDF_STATUS_SUCCESS) {
  1945. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1946. tx_desc, tx_q->ring_id);
  1947. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1948. tx_desc->id, DP_TX_DESC_UNMAP);
  1949. dp_tx_nbuf_unmap(soc, tx_desc);
  1950. drop_code = TX_HW_ENQUEUE;
  1951. goto release_desc;
  1952. }
  1953. return NULL;
  1954. release_desc:
  1955. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1956. fail_return:
  1957. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1958. tid_stats = &pdev->stats.tid_stats.
  1959. tid_tx_stats[tx_q->ring_id][tid];
  1960. tid_stats->swdrop_cnt[drop_code]++;
  1961. return nbuf;
  1962. }
  1963. /**
  1964. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1965. * @soc: Soc handle
  1966. * @desc: software Tx descriptor to be processed
  1967. *
  1968. * Return: none
  1969. */
  1970. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1971. {
  1972. qdf_nbuf_t nbuf = desc->nbuf;
  1973. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1974. /* nbuf already freed in vdev detach path */
  1975. if (!nbuf)
  1976. return;
  1977. /* If it is TDLS mgmt, don't unmap or free the frame */
  1978. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1979. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  1980. /* 0 : MSDU buffer, 1 : MLE */
  1981. if (desc->msdu_ext_desc) {
  1982. /* TSO free */
  1983. if (hal_tx_ext_desc_get_tso_enable(
  1984. desc->msdu_ext_desc->vaddr)) {
  1985. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1986. desc->id, DP_TX_COMP_MSDU_EXT);
  1987. dp_tx_tso_seg_history_add(soc,
  1988. desc->msdu_ext_desc->tso_desc,
  1989. desc->nbuf, desc->id, type);
  1990. /* unmap eash TSO seg before free the nbuf */
  1991. dp_tx_tso_unmap_segment(soc,
  1992. desc->msdu_ext_desc->tso_desc,
  1993. desc->msdu_ext_desc->
  1994. tso_num_desc);
  1995. qdf_nbuf_free(nbuf);
  1996. return;
  1997. }
  1998. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  1999. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2000. qdf_dma_addr_t iova;
  2001. uint32_t frag_len;
  2002. uint32_t i;
  2003. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2004. QDF_DMA_TO_DEVICE,
  2005. qdf_nbuf_headlen(nbuf));
  2006. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2007. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2008. &iova,
  2009. &frag_len);
  2010. if (!iova || !frag_len)
  2011. break;
  2012. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2013. QDF_DMA_TO_DEVICE);
  2014. }
  2015. qdf_nbuf_free(nbuf);
  2016. return;
  2017. }
  2018. }
  2019. /* If it's ME frame, dont unmap the cloned nbuf's */
  2020. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2021. goto nbuf_free;
  2022. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2023. dp_tx_unmap(soc, desc);
  2024. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2025. return dp_mesh_tx_comp_free_buff(soc, desc);
  2026. nbuf_free:
  2027. qdf_nbuf_free(nbuf);
  2028. }
  2029. /**
  2030. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2031. * @soc: DP soc handle
  2032. * @nbuf: skb
  2033. * @msdu_info: MSDU info
  2034. *
  2035. * Return: None
  2036. */
  2037. static inline void
  2038. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2039. struct dp_tx_msdu_info_s *msdu_info)
  2040. {
  2041. uint32_t cur_idx;
  2042. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2043. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2044. qdf_nbuf_headlen(nbuf));
  2045. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2046. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2047. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2048. seg->frags[cur_idx].paddr_hi) << 32),
  2049. seg->frags[cur_idx].len,
  2050. QDF_DMA_TO_DEVICE);
  2051. }
  2052. /**
  2053. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2054. * @vdev: DP vdev handle
  2055. * @nbuf: skb
  2056. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2057. *
  2058. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2059. *
  2060. * Return: NULL on success,
  2061. * nbuf when it fails to send
  2062. */
  2063. #if QDF_LOCK_STATS
  2064. noinline
  2065. #else
  2066. #endif
  2067. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2068. struct dp_tx_msdu_info_s *msdu_info)
  2069. {
  2070. uint32_t i;
  2071. struct dp_pdev *pdev = vdev->pdev;
  2072. struct dp_soc *soc = pdev->soc;
  2073. struct dp_tx_desc_s *tx_desc;
  2074. bool is_cce_classified = false;
  2075. QDF_STATUS status;
  2076. uint16_t htt_tcl_metadata = 0;
  2077. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2078. struct cdp_tid_tx_stats *tid_stats = NULL;
  2079. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2080. if (msdu_info->frm_type == dp_tx_frm_me)
  2081. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2082. i = 0;
  2083. /* Print statement to track i and num_seg */
  2084. /*
  2085. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2086. * descriptors using information in msdu_info
  2087. */
  2088. while (i < msdu_info->num_seg) {
  2089. /*
  2090. * Setup Tx descriptor for an MSDU, and MSDU extension
  2091. * descriptor
  2092. */
  2093. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2094. tx_q->desc_pool_id);
  2095. if (!tx_desc) {
  2096. if (msdu_info->frm_type == dp_tx_frm_me) {
  2097. prep_desc_fail++;
  2098. dp_tx_me_free_buf(pdev,
  2099. (void *)(msdu_info->u.sg_info
  2100. .curr_seg->frags[0].vaddr));
  2101. if (prep_desc_fail == msdu_info->num_seg) {
  2102. /*
  2103. * Unmap is needed only if descriptor
  2104. * preparation failed for all segments.
  2105. */
  2106. qdf_nbuf_unmap(soc->osdev,
  2107. msdu_info->u.sg_info.
  2108. curr_seg->nbuf,
  2109. QDF_DMA_TO_DEVICE);
  2110. }
  2111. /*
  2112. * Free the nbuf for the current segment
  2113. * and make it point to the next in the list.
  2114. * For me, there are as many segments as there
  2115. * are no of clients.
  2116. */
  2117. qdf_nbuf_free(msdu_info->u.sg_info
  2118. .curr_seg->nbuf);
  2119. if (msdu_info->u.sg_info.curr_seg->next) {
  2120. msdu_info->u.sg_info.curr_seg =
  2121. msdu_info->u.sg_info
  2122. .curr_seg->next;
  2123. nbuf = msdu_info->u.sg_info
  2124. .curr_seg->nbuf;
  2125. }
  2126. i++;
  2127. continue;
  2128. }
  2129. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2130. dp_tx_tso_seg_history_add(
  2131. soc,
  2132. msdu_info->u.tso_info.curr_seg,
  2133. nbuf, 0, DP_TX_DESC_UNMAP);
  2134. dp_tx_tso_unmap_segment(soc,
  2135. msdu_info->u.tso_info.
  2136. curr_seg,
  2137. msdu_info->u.tso_info.
  2138. tso_num_seg_list);
  2139. if (msdu_info->u.tso_info.curr_seg->next) {
  2140. msdu_info->u.tso_info.curr_seg =
  2141. msdu_info->u.tso_info.curr_seg->next;
  2142. i++;
  2143. continue;
  2144. }
  2145. }
  2146. if (msdu_info->frm_type == dp_tx_frm_sg)
  2147. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2148. goto done;
  2149. }
  2150. if (msdu_info->frm_type == dp_tx_frm_me) {
  2151. tx_desc->msdu_ext_desc->me_buffer =
  2152. (struct dp_tx_me_buf_t *)msdu_info->
  2153. u.sg_info.curr_seg->frags[0].vaddr;
  2154. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2155. }
  2156. if (is_cce_classified)
  2157. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2158. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2159. if (msdu_info->exception_fw) {
  2160. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2161. }
  2162. dp_tx_is_hp_update_required(i, msdu_info);
  2163. /*
  2164. * For frames with multiple segments (TSO, ME), jump to next
  2165. * segment.
  2166. */
  2167. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2168. if (msdu_info->u.tso_info.curr_seg->next) {
  2169. msdu_info->u.tso_info.curr_seg =
  2170. msdu_info->u.tso_info.curr_seg->next;
  2171. /*
  2172. * If this is a jumbo nbuf, then increment the
  2173. * number of nbuf users for each additional
  2174. * segment of the msdu. This will ensure that
  2175. * the skb is freed only after receiving tx
  2176. * completion for all segments of an nbuf
  2177. */
  2178. qdf_nbuf_inc_users(nbuf);
  2179. /* Check with MCL if this is needed */
  2180. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2181. */
  2182. }
  2183. }
  2184. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2185. &htt_tcl_metadata,
  2186. vdev,
  2187. msdu_info);
  2188. /*
  2189. * Enqueue the Tx MSDU descriptor to HW for transmit
  2190. */
  2191. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2192. htt_tcl_metadata,
  2193. NULL, msdu_info);
  2194. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2195. if (status != QDF_STATUS_SUCCESS) {
  2196. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2197. tx_desc, tx_q->ring_id);
  2198. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2199. tid_stats = &pdev->stats.tid_stats.
  2200. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2201. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2202. if (msdu_info->frm_type == dp_tx_frm_me) {
  2203. hw_enq_fail++;
  2204. if (hw_enq_fail == msdu_info->num_seg) {
  2205. /*
  2206. * Unmap is needed only if enqueue
  2207. * failed for all segments.
  2208. */
  2209. qdf_nbuf_unmap(soc->osdev,
  2210. msdu_info->u.sg_info.
  2211. curr_seg->nbuf,
  2212. QDF_DMA_TO_DEVICE);
  2213. }
  2214. /*
  2215. * Free the nbuf for the current segment
  2216. * and make it point to the next in the list.
  2217. * For me, there are as many segments as there
  2218. * are no of clients.
  2219. */
  2220. qdf_nbuf_free(msdu_info->u.sg_info
  2221. .curr_seg->nbuf);
  2222. if (msdu_info->u.sg_info.curr_seg->next) {
  2223. msdu_info->u.sg_info.curr_seg =
  2224. msdu_info->u.sg_info
  2225. .curr_seg->next;
  2226. nbuf = msdu_info->u.sg_info
  2227. .curr_seg->nbuf;
  2228. } else
  2229. break;
  2230. i++;
  2231. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2232. continue;
  2233. }
  2234. /*
  2235. * For TSO frames, the nbuf users increment done for
  2236. * the current segment has to be reverted, since the
  2237. * hw enqueue for this segment failed
  2238. */
  2239. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2240. msdu_info->u.tso_info.curr_seg) {
  2241. /*
  2242. * unmap and free current,
  2243. * retransmit remaining segments
  2244. */
  2245. dp_tx_comp_free_buf(soc, tx_desc);
  2246. i++;
  2247. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2248. continue;
  2249. }
  2250. if (msdu_info->frm_type == dp_tx_frm_sg)
  2251. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2252. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2253. goto done;
  2254. }
  2255. /*
  2256. * TODO
  2257. * if tso_info structure can be modified to have curr_seg
  2258. * as first element, following 2 blocks of code (for TSO and SG)
  2259. * can be combined into 1
  2260. */
  2261. /*
  2262. * For Multicast-Unicast converted packets,
  2263. * each converted frame (for a client) is represented as
  2264. * 1 segment
  2265. */
  2266. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2267. (msdu_info->frm_type == dp_tx_frm_me)) {
  2268. if (msdu_info->u.sg_info.curr_seg->next) {
  2269. msdu_info->u.sg_info.curr_seg =
  2270. msdu_info->u.sg_info.curr_seg->next;
  2271. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2272. } else
  2273. break;
  2274. }
  2275. i++;
  2276. }
  2277. nbuf = NULL;
  2278. done:
  2279. return nbuf;
  2280. }
  2281. /**
  2282. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2283. * for SG frames
  2284. * @vdev: DP vdev handle
  2285. * @nbuf: skb
  2286. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2287. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2288. *
  2289. * Return: NULL on success,
  2290. * nbuf when it fails to send
  2291. */
  2292. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2293. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2294. {
  2295. uint32_t cur_frag, nr_frags, i;
  2296. qdf_dma_addr_t paddr;
  2297. struct dp_tx_sg_info_s *sg_info;
  2298. sg_info = &msdu_info->u.sg_info;
  2299. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2300. if (QDF_STATUS_SUCCESS !=
  2301. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2302. QDF_DMA_TO_DEVICE,
  2303. qdf_nbuf_headlen(nbuf))) {
  2304. dp_tx_err("dma map error");
  2305. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2306. qdf_nbuf_free(nbuf);
  2307. return NULL;
  2308. }
  2309. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2310. seg_info->frags[0].paddr_lo = paddr;
  2311. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2312. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2313. seg_info->frags[0].vaddr = (void *) nbuf;
  2314. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2315. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2316. nbuf, 0,
  2317. QDF_DMA_TO_DEVICE,
  2318. cur_frag)) {
  2319. dp_tx_err("frag dma map error");
  2320. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2321. goto map_err;
  2322. }
  2323. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2324. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2325. seg_info->frags[cur_frag + 1].paddr_hi =
  2326. ((uint64_t) paddr) >> 32;
  2327. seg_info->frags[cur_frag + 1].len =
  2328. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2329. }
  2330. seg_info->frag_cnt = (cur_frag + 1);
  2331. seg_info->total_len = qdf_nbuf_len(nbuf);
  2332. seg_info->next = NULL;
  2333. sg_info->curr_seg = seg_info;
  2334. msdu_info->frm_type = dp_tx_frm_sg;
  2335. msdu_info->num_seg = 1;
  2336. return nbuf;
  2337. map_err:
  2338. /* restore paddr into nbuf before calling unmap */
  2339. qdf_nbuf_mapped_paddr_set(nbuf,
  2340. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2341. ((uint64_t)
  2342. seg_info->frags[0].paddr_hi) << 32));
  2343. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2344. QDF_DMA_TO_DEVICE,
  2345. seg_info->frags[0].len);
  2346. for (i = 1; i <= cur_frag; i++) {
  2347. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2348. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2349. seg_info->frags[i].paddr_hi) << 32),
  2350. seg_info->frags[i].len,
  2351. QDF_DMA_TO_DEVICE);
  2352. }
  2353. qdf_nbuf_free(nbuf);
  2354. return NULL;
  2355. }
  2356. /**
  2357. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2358. * @vdev: DP vdev handle
  2359. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2360. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2361. *
  2362. * Return: NULL on failure,
  2363. * nbuf when extracted successfully
  2364. */
  2365. static
  2366. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2367. struct dp_tx_msdu_info_s *msdu_info,
  2368. uint16_t ppdu_cookie)
  2369. {
  2370. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2371. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2372. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2373. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2374. (msdu_info->meta_data[5], 1);
  2375. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2376. (msdu_info->meta_data[5], 1);
  2377. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2378. (msdu_info->meta_data[6], ppdu_cookie);
  2379. msdu_info->exception_fw = 1;
  2380. msdu_info->is_tx_sniffer = 1;
  2381. }
  2382. #ifdef MESH_MODE_SUPPORT
  2383. /**
  2384. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2385. and prepare msdu_info for mesh frames.
  2386. * @vdev: DP vdev handle
  2387. * @nbuf: skb
  2388. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2389. *
  2390. * Return: NULL on failure,
  2391. * nbuf when extracted successfully
  2392. */
  2393. static
  2394. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2395. struct dp_tx_msdu_info_s *msdu_info)
  2396. {
  2397. struct meta_hdr_s *mhdr;
  2398. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2399. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2400. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2401. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2402. msdu_info->exception_fw = 0;
  2403. goto remove_meta_hdr;
  2404. }
  2405. msdu_info->exception_fw = 1;
  2406. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2407. meta_data->host_tx_desc_pool = 1;
  2408. meta_data->update_peer_cache = 1;
  2409. meta_data->learning_frame = 1;
  2410. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2411. meta_data->power = mhdr->power;
  2412. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2413. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2414. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2415. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2416. meta_data->dyn_bw = 1;
  2417. meta_data->valid_pwr = 1;
  2418. meta_data->valid_mcs_mask = 1;
  2419. meta_data->valid_nss_mask = 1;
  2420. meta_data->valid_preamble_type = 1;
  2421. meta_data->valid_retries = 1;
  2422. meta_data->valid_bw_info = 1;
  2423. }
  2424. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2425. meta_data->encrypt_type = 0;
  2426. meta_data->valid_encrypt_type = 1;
  2427. meta_data->learning_frame = 0;
  2428. }
  2429. meta_data->valid_key_flags = 1;
  2430. meta_data->key_flags = (mhdr->keyix & 0x3);
  2431. remove_meta_hdr:
  2432. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2433. dp_tx_err("qdf_nbuf_pull_head failed");
  2434. qdf_nbuf_free(nbuf);
  2435. return NULL;
  2436. }
  2437. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2438. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2439. " tid %d to_fw %d",
  2440. msdu_info->meta_data[0],
  2441. msdu_info->meta_data[1],
  2442. msdu_info->meta_data[2],
  2443. msdu_info->meta_data[3],
  2444. msdu_info->meta_data[4],
  2445. msdu_info->meta_data[5],
  2446. msdu_info->tid, msdu_info->exception_fw);
  2447. return nbuf;
  2448. }
  2449. #else
  2450. static
  2451. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2452. struct dp_tx_msdu_info_s *msdu_info)
  2453. {
  2454. return nbuf;
  2455. }
  2456. #endif
  2457. /**
  2458. * dp_check_exc_metadata() - Checks if parameters are valid
  2459. * @tx_exc - holds all exception path parameters
  2460. *
  2461. * Returns true when all the parameters are valid else false
  2462. *
  2463. */
  2464. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2465. {
  2466. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2467. HTT_INVALID_TID);
  2468. bool invalid_encap_type =
  2469. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2470. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2471. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2472. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2473. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2474. tx_exc->ppdu_cookie == 0);
  2475. if (tx_exc->is_intrabss_fwd)
  2476. return true;
  2477. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2478. invalid_cookie) {
  2479. return false;
  2480. }
  2481. return true;
  2482. }
  2483. #ifdef ATH_SUPPORT_IQUE
  2484. /**
  2485. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2486. * @vdev: vdev handle
  2487. * @nbuf: skb
  2488. *
  2489. * Return: true on success,
  2490. * false on failure
  2491. */
  2492. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2493. {
  2494. qdf_ether_header_t *eh;
  2495. /* Mcast to Ucast Conversion*/
  2496. if (qdf_likely(!vdev->mcast_enhancement_en))
  2497. return true;
  2498. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2499. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2500. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2501. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2502. qdf_nbuf_set_next(nbuf, NULL);
  2503. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2504. qdf_nbuf_len(nbuf));
  2505. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2506. QDF_STATUS_SUCCESS) {
  2507. return false;
  2508. }
  2509. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2510. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2511. QDF_STATUS_SUCCESS) {
  2512. return false;
  2513. }
  2514. }
  2515. }
  2516. return true;
  2517. }
  2518. #else
  2519. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2520. {
  2521. return true;
  2522. }
  2523. #endif
  2524. /**
  2525. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2526. * @nbuf: qdf_nbuf_t
  2527. * @vdev: struct dp_vdev *
  2528. *
  2529. * Allow packet for processing only if it is for peer client which is
  2530. * connected with same vap. Drop packet if client is connected to
  2531. * different vap.
  2532. *
  2533. * Return: QDF_STATUS
  2534. */
  2535. static inline QDF_STATUS
  2536. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2537. {
  2538. struct dp_ast_entry *dst_ast_entry = NULL;
  2539. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2540. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2541. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2542. return QDF_STATUS_SUCCESS;
  2543. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2544. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2545. eh->ether_dhost,
  2546. vdev->vdev_id);
  2547. /* If there is no ast entry, return failure */
  2548. if (qdf_unlikely(!dst_ast_entry)) {
  2549. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2550. return QDF_STATUS_E_FAILURE;
  2551. }
  2552. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2553. return QDF_STATUS_SUCCESS;
  2554. }
  2555. /**
  2556. * dp_tx_nawds_handler() - NAWDS handler
  2557. *
  2558. * @soc: DP soc handle
  2559. * @vdev_id: id of DP vdev handle
  2560. * @msdu_info: msdu_info required to create HTT metadata
  2561. * @nbuf: skb
  2562. *
  2563. * This API transfers the multicast frames with the peer id
  2564. * on NAWDS enabled peer.
  2565. * Return: none
  2566. */
  2567. static inline
  2568. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2569. struct dp_tx_msdu_info_s *msdu_info,
  2570. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2571. {
  2572. struct dp_peer *peer = NULL;
  2573. qdf_nbuf_t nbuf_clone = NULL;
  2574. uint16_t peer_id = DP_INVALID_PEER;
  2575. struct dp_txrx_peer *txrx_peer;
  2576. /* This check avoids pkt forwarding which is entered
  2577. * in the ast table but still doesn't have valid peerid.
  2578. */
  2579. if (sa_peer_id == HTT_INVALID_PEER)
  2580. return;
  2581. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2582. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2583. txrx_peer = dp_get_txrx_peer(peer);
  2584. if (!txrx_peer)
  2585. continue;
  2586. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2587. peer_id = peer->peer_id;
  2588. if (!dp_peer_is_primary_link_peer(peer))
  2589. continue;
  2590. /* Multicast packets needs to be
  2591. * dropped in case of intra bss forwarding
  2592. */
  2593. if (sa_peer_id == peer->peer_id) {
  2594. dp_tx_debug("multicast packet");
  2595. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2596. tx.nawds_mcast_drop,
  2597. 1);
  2598. continue;
  2599. }
  2600. nbuf_clone = qdf_nbuf_clone(nbuf);
  2601. if (!nbuf_clone) {
  2602. QDF_TRACE(QDF_MODULE_ID_DP,
  2603. QDF_TRACE_LEVEL_ERROR,
  2604. FL("nbuf clone failed"));
  2605. break;
  2606. }
  2607. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2608. msdu_info, peer_id,
  2609. NULL);
  2610. if (nbuf_clone) {
  2611. dp_tx_debug("pkt send failed");
  2612. qdf_nbuf_free(nbuf_clone);
  2613. } else {
  2614. if (peer_id != DP_INVALID_PEER)
  2615. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2616. tx.nawds_mcast,
  2617. 1, qdf_nbuf_len(nbuf));
  2618. }
  2619. }
  2620. }
  2621. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2622. }
  2623. /**
  2624. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2625. * @soc: DP soc handle
  2626. * @vdev_id: id of DP vdev handle
  2627. * @nbuf: skb
  2628. * @tx_exc_metadata: Handle that holds exception path meta data
  2629. *
  2630. * Entry point for Core Tx layer (DP_TX) invoked from
  2631. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2632. *
  2633. * Return: NULL on success,
  2634. * nbuf when it fails to send
  2635. */
  2636. qdf_nbuf_t
  2637. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2638. qdf_nbuf_t nbuf,
  2639. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2640. {
  2641. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2642. qdf_ether_header_t *eh = NULL;
  2643. struct dp_tx_msdu_info_s msdu_info;
  2644. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2645. DP_MOD_ID_TX_EXCEPTION);
  2646. if (qdf_unlikely(!vdev))
  2647. goto fail;
  2648. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2649. if (!tx_exc_metadata)
  2650. goto fail;
  2651. msdu_info.tid = tx_exc_metadata->tid;
  2652. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2653. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2654. QDF_MAC_ADDR_REF(nbuf->data));
  2655. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2656. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2657. dp_tx_err("Invalid parameters in exception path");
  2658. goto fail;
  2659. }
  2660. /* Basic sanity checks for unsupported packets */
  2661. /* MESH mode */
  2662. if (qdf_unlikely(vdev->mesh_vdev)) {
  2663. dp_tx_err("Mesh mode is not supported in exception path");
  2664. goto fail;
  2665. }
  2666. /*
  2667. * Classify the frame and call corresponding
  2668. * "prepare" function which extracts the segment (TSO)
  2669. * and fragmentation information (for TSO , SG, ME, or Raw)
  2670. * into MSDU_INFO structure which is later used to fill
  2671. * SW and HW descriptors.
  2672. */
  2673. if (qdf_nbuf_is_tso(nbuf)) {
  2674. dp_verbose_debug("TSO frame %pK", vdev);
  2675. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2676. qdf_nbuf_len(nbuf));
  2677. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2678. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2679. qdf_nbuf_len(nbuf));
  2680. goto fail;
  2681. }
  2682. goto send_multiple;
  2683. }
  2684. /* SG */
  2685. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2686. struct dp_tx_seg_info_s seg_info = {0};
  2687. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2688. if (!nbuf)
  2689. goto fail;
  2690. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2691. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2692. qdf_nbuf_len(nbuf));
  2693. goto send_multiple;
  2694. }
  2695. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2696. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2697. qdf_nbuf_len(nbuf));
  2698. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2699. tx_exc_metadata->ppdu_cookie);
  2700. }
  2701. /*
  2702. * Get HW Queue to use for this frame.
  2703. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2704. * dedicated for data and 1 for command.
  2705. * "queue_id" maps to one hardware ring.
  2706. * With each ring, we also associate a unique Tx descriptor pool
  2707. * to minimize lock contention for these resources.
  2708. */
  2709. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2710. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2711. if (qdf_unlikely(vdev->nawds_enabled)) {
  2712. /*
  2713. * This is a multicast packet
  2714. */
  2715. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2716. tx_exc_metadata->peer_id);
  2717. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2718. 1, qdf_nbuf_len(nbuf));
  2719. }
  2720. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2721. DP_INVALID_PEER, NULL);
  2722. } else {
  2723. /*
  2724. * Check exception descriptors
  2725. */
  2726. if (dp_tx_exception_limit_check(vdev))
  2727. goto fail;
  2728. /* Single linear frame */
  2729. /*
  2730. * If nbuf is a simple linear frame, use send_single function to
  2731. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2732. * SRNG. There is no need to setup a MSDU extension descriptor.
  2733. */
  2734. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2735. tx_exc_metadata->peer_id,
  2736. tx_exc_metadata);
  2737. }
  2738. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2739. return nbuf;
  2740. send_multiple:
  2741. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2742. fail:
  2743. if (vdev)
  2744. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2745. dp_verbose_debug("pkt send failed");
  2746. return nbuf;
  2747. }
  2748. /**
  2749. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2750. * in exception path in special case to avoid regular exception path chk.
  2751. * @soc: DP soc handle
  2752. * @vdev_id: id of DP vdev handle
  2753. * @nbuf: skb
  2754. * @tx_exc_metadata: Handle that holds exception path meta data
  2755. *
  2756. * Entry point for Core Tx layer (DP_TX) invoked from
  2757. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2758. *
  2759. * Return: NULL on success,
  2760. * nbuf when it fails to send
  2761. */
  2762. qdf_nbuf_t
  2763. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2764. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2765. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2766. {
  2767. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2768. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2769. DP_MOD_ID_TX_EXCEPTION);
  2770. if (qdf_unlikely(!vdev))
  2771. goto fail;
  2772. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2773. == QDF_STATUS_E_FAILURE)) {
  2774. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2775. goto fail;
  2776. }
  2777. /* Unref count as it will agin be taken inside dp_tx_exception */
  2778. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2779. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2780. fail:
  2781. if (vdev)
  2782. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2783. dp_verbose_debug("pkt send failed");
  2784. return nbuf;
  2785. }
  2786. /**
  2787. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2788. * @soc: DP soc handle
  2789. * @vdev_id: DP vdev handle
  2790. * @nbuf: skb
  2791. *
  2792. * Entry point for Core Tx layer (DP_TX) invoked from
  2793. * hard_start_xmit in OSIF/HDD
  2794. *
  2795. * Return: NULL on success,
  2796. * nbuf when it fails to send
  2797. */
  2798. #ifdef MESH_MODE_SUPPORT
  2799. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2800. qdf_nbuf_t nbuf)
  2801. {
  2802. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2803. struct meta_hdr_s *mhdr;
  2804. qdf_nbuf_t nbuf_mesh = NULL;
  2805. qdf_nbuf_t nbuf_clone = NULL;
  2806. struct dp_vdev *vdev;
  2807. uint8_t no_enc_frame = 0;
  2808. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2809. if (!nbuf_mesh) {
  2810. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2811. "qdf_nbuf_unshare failed");
  2812. return nbuf;
  2813. }
  2814. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2815. if (!vdev) {
  2816. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2817. "vdev is NULL for vdev_id %d", vdev_id);
  2818. return nbuf;
  2819. }
  2820. nbuf = nbuf_mesh;
  2821. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2822. if ((vdev->sec_type != cdp_sec_type_none) &&
  2823. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2824. no_enc_frame = 1;
  2825. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2826. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2827. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2828. !no_enc_frame) {
  2829. nbuf_clone = qdf_nbuf_clone(nbuf);
  2830. if (!nbuf_clone) {
  2831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2832. "qdf_nbuf_clone failed");
  2833. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2834. return nbuf;
  2835. }
  2836. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2837. }
  2838. if (nbuf_clone) {
  2839. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2840. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2841. } else {
  2842. qdf_nbuf_free(nbuf_clone);
  2843. }
  2844. }
  2845. if (no_enc_frame)
  2846. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2847. else
  2848. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2849. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2850. if ((!nbuf) && no_enc_frame) {
  2851. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2852. }
  2853. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2854. return nbuf;
  2855. }
  2856. #else
  2857. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2858. qdf_nbuf_t nbuf)
  2859. {
  2860. return dp_tx_send(soc, vdev_id, nbuf);
  2861. }
  2862. #endif
  2863. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2864. static inline
  2865. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2866. {
  2867. if (nbuf) {
  2868. qdf_prefetch(&nbuf->len);
  2869. qdf_prefetch(&nbuf->data);
  2870. }
  2871. }
  2872. #else
  2873. static inline
  2874. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2875. {
  2876. }
  2877. #endif
  2878. /**
  2879. * dp_tx_send() - Transmit a frame on a given VAP
  2880. * @soc: DP soc handle
  2881. * @vdev_id: id of DP vdev handle
  2882. * @nbuf: skb
  2883. *
  2884. * Entry point for Core Tx layer (DP_TX) invoked from
  2885. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2886. * cases
  2887. *
  2888. * Return: NULL on success,
  2889. * nbuf when it fails to send
  2890. */
  2891. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2892. qdf_nbuf_t nbuf)
  2893. {
  2894. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2895. uint16_t peer_id = HTT_INVALID_PEER;
  2896. /*
  2897. * doing a memzero is causing additional function call overhead
  2898. * so doing static stack clearing
  2899. */
  2900. struct dp_tx_msdu_info_s msdu_info = {0};
  2901. struct dp_vdev *vdev = NULL;
  2902. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2903. return nbuf;
  2904. /*
  2905. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2906. * this in per packet path.
  2907. *
  2908. * As in this path vdev memory is already protected with netdev
  2909. * tx lock
  2910. */
  2911. vdev = soc->vdev_id_map[vdev_id];
  2912. if (qdf_unlikely(!vdev))
  2913. return nbuf;
  2914. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2915. QDF_MAC_ADDR_REF(nbuf->data));
  2916. /*
  2917. * Set Default Host TID value to invalid TID
  2918. * (TID override disabled)
  2919. */
  2920. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2921. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2922. if (qdf_unlikely(vdev->mesh_vdev)) {
  2923. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2924. &msdu_info);
  2925. if (!nbuf_mesh) {
  2926. dp_verbose_debug("Extracting mesh metadata failed");
  2927. return nbuf;
  2928. }
  2929. nbuf = nbuf_mesh;
  2930. }
  2931. /*
  2932. * Get HW Queue to use for this frame.
  2933. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2934. * dedicated for data and 1 for command.
  2935. * "queue_id" maps to one hardware ring.
  2936. * With each ring, we also associate a unique Tx descriptor pool
  2937. * to minimize lock contention for these resources.
  2938. */
  2939. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2940. /*
  2941. * TCL H/W supports 2 DSCP-TID mapping tables.
  2942. * Table 1 - Default DSCP-TID mapping table
  2943. * Table 2 - 1 DSCP-TID override table
  2944. *
  2945. * If we need a different DSCP-TID mapping for this vap,
  2946. * call tid_classify to extract DSCP/ToS from frame and
  2947. * map to a TID and store in msdu_info. This is later used
  2948. * to fill in TCL Input descriptor (per-packet TID override).
  2949. */
  2950. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2951. /*
  2952. * Classify the frame and call corresponding
  2953. * "prepare" function which extracts the segment (TSO)
  2954. * and fragmentation information (for TSO , SG, ME, or Raw)
  2955. * into MSDU_INFO structure which is later used to fill
  2956. * SW and HW descriptors.
  2957. */
  2958. if (qdf_nbuf_is_tso(nbuf)) {
  2959. dp_verbose_debug("TSO frame %pK", vdev);
  2960. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2961. qdf_nbuf_len(nbuf));
  2962. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2963. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2964. qdf_nbuf_len(nbuf));
  2965. return nbuf;
  2966. }
  2967. goto send_multiple;
  2968. }
  2969. /* SG */
  2970. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2971. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  2972. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  2973. return nbuf;
  2974. } else {
  2975. struct dp_tx_seg_info_s seg_info = {0};
  2976. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  2977. &msdu_info);
  2978. if (!nbuf)
  2979. return NULL;
  2980. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2981. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2982. qdf_nbuf_len(nbuf));
  2983. goto send_multiple;
  2984. }
  2985. }
  2986. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2987. return NULL;
  2988. /* RAW */
  2989. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2990. struct dp_tx_seg_info_s seg_info = {0};
  2991. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2992. if (!nbuf)
  2993. return NULL;
  2994. dp_verbose_debug("Raw frame %pK", vdev);
  2995. goto send_multiple;
  2996. }
  2997. if (qdf_unlikely(vdev->nawds_enabled)) {
  2998. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2999. qdf_nbuf_data(nbuf);
  3000. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3001. uint16_t sa_peer_id = DP_INVALID_PEER;
  3002. if (!soc->ast_offload_support) {
  3003. struct dp_ast_entry *ast_entry = NULL;
  3004. qdf_spin_lock_bh(&soc->ast_lock);
  3005. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3006. (soc,
  3007. (uint8_t *)(eh->ether_shost),
  3008. vdev->pdev->pdev_id);
  3009. if (ast_entry)
  3010. sa_peer_id = ast_entry->peer_id;
  3011. qdf_spin_unlock_bh(&soc->ast_lock);
  3012. }
  3013. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3014. sa_peer_id);
  3015. }
  3016. peer_id = DP_INVALID_PEER;
  3017. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3018. 1, qdf_nbuf_len(nbuf));
  3019. }
  3020. /* Single linear frame */
  3021. /*
  3022. * If nbuf is a simple linear frame, use send_single function to
  3023. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3024. * SRNG. There is no need to setup a MSDU extension descriptor.
  3025. */
  3026. dp_tx_prefetch_nbuf_data(nbuf);
  3027. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  3028. return nbuf;
  3029. send_multiple:
  3030. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3031. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3032. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3033. return nbuf;
  3034. }
  3035. /**
  3036. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3037. * case to vaoid check in perpkt path.
  3038. * @soc: DP soc handle
  3039. * @vdev_id: id of DP vdev handle
  3040. * @nbuf: skb
  3041. *
  3042. * Entry point for Core Tx layer (DP_TX) invoked from
  3043. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3044. * with special condition to avoid per pkt check in dp_tx_send
  3045. *
  3046. * Return: NULL on success,
  3047. * nbuf when it fails to send
  3048. */
  3049. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3050. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3051. {
  3052. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3053. struct dp_vdev *vdev = NULL;
  3054. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3055. return nbuf;
  3056. /*
  3057. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3058. * this in per packet path.
  3059. *
  3060. * As in this path vdev memory is already protected with netdev
  3061. * tx lock
  3062. */
  3063. vdev = soc->vdev_id_map[vdev_id];
  3064. if (qdf_unlikely(!vdev))
  3065. return nbuf;
  3066. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3067. == QDF_STATUS_E_FAILURE)) {
  3068. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3069. return nbuf;
  3070. }
  3071. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3072. }
  3073. #ifdef UMAC_SUPPORT_PROXY_ARP
  3074. /**
  3075. * dp_tx_proxy_arp() - Tx proxy arp handler
  3076. * @vdev: datapath vdev handle
  3077. * @buf: sk buffer
  3078. *
  3079. * Return: status
  3080. */
  3081. static inline
  3082. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3083. {
  3084. if (vdev->osif_proxy_arp)
  3085. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3086. /*
  3087. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3088. * osif_proxy_arp has a valid function pointer assigned
  3089. * to it
  3090. */
  3091. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3092. return QDF_STATUS_NOT_INITIALIZED;
  3093. }
  3094. #else
  3095. /**
  3096. * dp_tx_proxy_arp() - Tx proxy arp handler
  3097. * @vdev: datapath vdev handle
  3098. * @buf: sk buffer
  3099. *
  3100. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3101. * is not defined.
  3102. *
  3103. * Return: status
  3104. */
  3105. static inline
  3106. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3107. {
  3108. return QDF_STATUS_SUCCESS;
  3109. }
  3110. #endif
  3111. /**
  3112. * dp_tx_reinject_handler() - Tx Reinject Handler
  3113. * @soc: datapath soc handle
  3114. * @vdev: datapath vdev handle
  3115. * @tx_desc: software descriptor head pointer
  3116. * @status : Tx completion status from HTT descriptor
  3117. * @reinject_reason : reinject reason from HTT descriptor
  3118. *
  3119. * This function reinjects frames back to Target.
  3120. * Todo - Host queue needs to be added
  3121. *
  3122. * Return: none
  3123. */
  3124. void dp_tx_reinject_handler(struct dp_soc *soc,
  3125. struct dp_vdev *vdev,
  3126. struct dp_tx_desc_s *tx_desc,
  3127. uint8_t *status,
  3128. uint8_t reinject_reason)
  3129. {
  3130. struct dp_peer *peer = NULL;
  3131. uint32_t peer_id = HTT_INVALID_PEER;
  3132. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3133. qdf_nbuf_t nbuf_copy = NULL;
  3134. struct dp_tx_msdu_info_s msdu_info;
  3135. #ifdef WDS_VENDOR_EXTENSION
  3136. int is_mcast = 0, is_ucast = 0;
  3137. int num_peers_3addr = 0;
  3138. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3139. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3140. #endif
  3141. struct dp_txrx_peer *txrx_peer;
  3142. qdf_assert(vdev);
  3143. dp_tx_debug("Tx reinject path");
  3144. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3145. qdf_nbuf_len(tx_desc->nbuf));
  3146. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3147. #ifdef WLAN_MCAST_MLO
  3148. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3149. if (soc->arch_ops.dp_tx_mcast_handler)
  3150. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3151. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3152. return;
  3153. }
  3154. #endif
  3155. #endif
  3156. #ifdef WDS_VENDOR_EXTENSION
  3157. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3158. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3159. } else {
  3160. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3161. }
  3162. is_ucast = !is_mcast;
  3163. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3164. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3165. txrx_peer = dp_get_txrx_peer(peer);
  3166. if (!txrx_peer || txrx_peer->bss_peer)
  3167. continue;
  3168. /* Detect wds peers that use 3-addr framing for mcast.
  3169. * if there are any, the bss_peer is used to send the
  3170. * the mcast frame using 3-addr format. all wds enabled
  3171. * peers that use 4-addr framing for mcast frames will
  3172. * be duplicated and sent as 4-addr frames below.
  3173. */
  3174. if (!txrx_peer->wds_enabled ||
  3175. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3176. num_peers_3addr = 1;
  3177. break;
  3178. }
  3179. }
  3180. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3181. #endif
  3182. if (qdf_unlikely(vdev->mesh_vdev)) {
  3183. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3184. } else {
  3185. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3186. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3187. txrx_peer = dp_get_txrx_peer(peer);
  3188. if (!txrx_peer)
  3189. continue;
  3190. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3191. #ifdef WDS_VENDOR_EXTENSION
  3192. /*
  3193. * . if 3-addr STA, then send on BSS Peer
  3194. * . if Peer WDS enabled and accept 4-addr mcast,
  3195. * send mcast on that peer only
  3196. * . if Peer WDS enabled and accept 4-addr ucast,
  3197. * send ucast on that peer only
  3198. */
  3199. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3200. (txrx_peer->wds_enabled &&
  3201. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3202. (is_ucast &&
  3203. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3204. #else
  3205. (txrx_peer->bss_peer &&
  3206. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3207. #endif
  3208. peer_id = DP_INVALID_PEER;
  3209. nbuf_copy = qdf_nbuf_copy(nbuf);
  3210. if (!nbuf_copy) {
  3211. dp_tx_debug("nbuf copy failed");
  3212. break;
  3213. }
  3214. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3215. dp_tx_get_queue(vdev, nbuf,
  3216. &msdu_info.tx_queue);
  3217. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3218. nbuf_copy,
  3219. &msdu_info,
  3220. peer_id,
  3221. NULL);
  3222. if (nbuf_copy) {
  3223. dp_tx_debug("pkt send failed");
  3224. qdf_nbuf_free(nbuf_copy);
  3225. }
  3226. }
  3227. }
  3228. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3229. }
  3230. qdf_nbuf_free(nbuf);
  3231. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3232. }
  3233. /**
  3234. * dp_tx_inspect_handler() - Tx Inspect Handler
  3235. * @soc: datapath soc handle
  3236. * @vdev: datapath vdev handle
  3237. * @tx_desc: software descriptor head pointer
  3238. * @status : Tx completion status from HTT descriptor
  3239. *
  3240. * Handles Tx frames sent back to Host for inspection
  3241. * (ProxyARP)
  3242. *
  3243. * Return: none
  3244. */
  3245. void dp_tx_inspect_handler(struct dp_soc *soc,
  3246. struct dp_vdev *vdev,
  3247. struct dp_tx_desc_s *tx_desc,
  3248. uint8_t *status)
  3249. {
  3250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3251. "%s Tx inspect path",
  3252. __func__);
  3253. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3254. qdf_nbuf_len(tx_desc->nbuf));
  3255. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3256. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3257. }
  3258. #ifdef MESH_MODE_SUPPORT
  3259. /**
  3260. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3261. * in mesh meta header
  3262. * @tx_desc: software descriptor head pointer
  3263. * @ts: pointer to tx completion stats
  3264. * Return: none
  3265. */
  3266. static
  3267. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3268. struct hal_tx_completion_status *ts)
  3269. {
  3270. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3271. if (!tx_desc->msdu_ext_desc) {
  3272. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3273. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3274. "netbuf %pK offset %d",
  3275. netbuf, tx_desc->pkt_offset);
  3276. return;
  3277. }
  3278. }
  3279. }
  3280. #else
  3281. static
  3282. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3283. struct hal_tx_completion_status *ts)
  3284. {
  3285. }
  3286. #endif
  3287. #ifdef CONFIG_SAWF
  3288. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3289. struct dp_vdev *vdev,
  3290. struct dp_txrx_peer *txrx_peer,
  3291. struct dp_tx_desc_s *tx_desc,
  3292. struct hal_tx_completion_status *ts,
  3293. uint8_t tid)
  3294. {
  3295. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3296. ts, tid);
  3297. }
  3298. #else
  3299. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3300. struct dp_vdev *vdev,
  3301. struct dp_txrx_peer *txrx_peer,
  3302. struct dp_tx_desc_s *tx_desc,
  3303. struct hal_tx_completion_status *ts,
  3304. uint8_t tid)
  3305. {
  3306. }
  3307. #endif
  3308. #ifdef QCA_PEER_EXT_STATS
  3309. /*
  3310. * dp_tx_compute_tid_delay() - Compute per TID delay
  3311. * @stats: Per TID delay stats
  3312. * @tx_desc: Software Tx descriptor
  3313. *
  3314. * Compute the software enqueue and hw enqueue delays and
  3315. * update the respective histograms
  3316. *
  3317. * Return: void
  3318. */
  3319. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3320. struct dp_tx_desc_s *tx_desc)
  3321. {
  3322. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3323. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3324. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3325. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3326. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3327. timestamp_hw_enqueue = tx_desc->timestamp;
  3328. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3329. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3330. timestamp_hw_enqueue);
  3331. /*
  3332. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3333. */
  3334. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3335. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3336. }
  3337. /*
  3338. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3339. * @txrx_peer: DP peer context
  3340. * @tx_desc: Tx software descriptor
  3341. * @tid: Transmission ID
  3342. * @ring_id: Rx CPU context ID/CPU_ID
  3343. *
  3344. * Update the peer extended stats. These are enhanced other
  3345. * delay stats per msdu level.
  3346. *
  3347. * Return: void
  3348. */
  3349. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3350. struct dp_tx_desc_s *tx_desc,
  3351. uint8_t tid, uint8_t ring_id)
  3352. {
  3353. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3354. struct dp_soc *soc = NULL;
  3355. struct dp_peer_delay_stats *delay_stats = NULL;
  3356. soc = pdev->soc;
  3357. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3358. return;
  3359. delay_stats = txrx_peer->delay_stats;
  3360. qdf_assert(delay_stats);
  3361. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3362. /*
  3363. * For non-TID packets use the TID 9
  3364. */
  3365. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3366. tid = CDP_MAX_DATA_TIDS - 1;
  3367. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3368. tx_desc);
  3369. }
  3370. #else
  3371. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3372. struct dp_tx_desc_s *tx_desc,
  3373. uint8_t tid, uint8_t ring_id)
  3374. {
  3375. }
  3376. #endif
  3377. /**
  3378. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3379. * to pass in correct fields
  3380. *
  3381. * @vdev: pdev handle
  3382. * @tx_desc: tx descriptor
  3383. * @tid: tid value
  3384. * @ring_id: TCL or WBM ring number for transmit path
  3385. * Return: none
  3386. */
  3387. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3388. uint8_t tid, uint8_t ring_id)
  3389. {
  3390. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3391. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3392. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3393. return;
  3394. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3395. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3396. timestamp_hw_enqueue = tx_desc->timestamp;
  3397. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3398. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3399. timestamp_hw_enqueue);
  3400. interframe_delay = (uint32_t)(timestamp_ingress -
  3401. vdev->prev_tx_enq_tstamp);
  3402. /*
  3403. * Delay in software enqueue
  3404. */
  3405. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3406. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3407. /*
  3408. * Delay between packet enqueued to HW and Tx completion
  3409. */
  3410. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3411. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3412. /*
  3413. * Update interframe delay stats calculated at hardstart receive point.
  3414. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3415. * interframe delay will not be calculate correctly for 1st frame.
  3416. * On the other side, this will help in avoiding extra per packet check
  3417. * of !vdev->prev_tx_enq_tstamp.
  3418. */
  3419. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3420. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3421. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3422. }
  3423. #ifdef DISABLE_DP_STATS
  3424. static
  3425. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3426. struct dp_txrx_peer *txrx_peer)
  3427. {
  3428. }
  3429. #else
  3430. static inline void
  3431. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3432. {
  3433. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3434. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3435. if (subtype != QDF_PROTO_INVALID)
  3436. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3437. 1);
  3438. }
  3439. #endif
  3440. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3441. /**
  3442. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3443. *
  3444. * @ts: Tx compltion status
  3445. * @txrx_peer: datapath txrx_peer handle
  3446. *
  3447. * Return: void
  3448. */
  3449. static inline void
  3450. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3451. struct dp_txrx_peer *txrx_peer)
  3452. {
  3453. uint8_t mcs, pkt_type;
  3454. mcs = ts->mcs;
  3455. pkt_type = ts->pkt_type;
  3456. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3457. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3458. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3459. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3460. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3461. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3462. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3463. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3464. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3465. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3466. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3467. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3468. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3469. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3470. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3471. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3472. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3473. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3474. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3475. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3476. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3477. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3478. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3479. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3480. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3481. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3482. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3483. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3484. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3485. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3486. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3487. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3488. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3489. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3490. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3491. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3492. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3493. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3494. if (ts->first_msdu) {
  3495. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3496. ts->transmit_cnt > 1);
  3497. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3498. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3499. ts->transmit_cnt > DP_RETRY_COUNT);
  3500. }
  3501. }
  3502. #else
  3503. static inline void
  3504. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3505. struct dp_txrx_peer *txrx_peer)
  3506. {
  3507. }
  3508. #endif
  3509. /**
  3510. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3511. * per wbm ring
  3512. *
  3513. * @tx_desc: software descriptor head pointer
  3514. * @ts: Tx completion status
  3515. * @peer: peer handle
  3516. * @ring_id: ring number
  3517. *
  3518. * Return: None
  3519. */
  3520. static inline void
  3521. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3522. struct hal_tx_completion_status *ts,
  3523. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3524. {
  3525. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3526. uint8_t tid = ts->tid;
  3527. uint32_t length;
  3528. struct cdp_tid_tx_stats *tid_stats;
  3529. if (!pdev)
  3530. return;
  3531. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3532. tid = CDP_MAX_DATA_TIDS - 1;
  3533. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3534. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3535. dp_err("Release source is not from TQM");
  3536. return;
  3537. }
  3538. length = qdf_nbuf_len(tx_desc->nbuf);
  3539. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3540. if (qdf_unlikely(pdev->delay_stats_flag))
  3541. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3542. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3543. tid_stats->tqm_status_cnt[ts->status]++;
  3544. }
  3545. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3546. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3547. ts->transmit_cnt > 1);
  3548. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3549. 1, ts->transmit_cnt > 2);
  3550. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3551. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3552. ts->msdu_part_of_amsdu);
  3553. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3554. !ts->msdu_part_of_amsdu);
  3555. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3556. qdf_system_ticks();
  3557. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3558. return;
  3559. }
  3560. /*
  3561. * tx_failed is ideally supposed to be updated from HTT ppdu
  3562. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3563. * hw limitation there are no completions for failed cases.
  3564. * Hence updating tx_failed from data path. Please note that
  3565. * if tx_failed is fixed to be from ppdu, then this has to be
  3566. * removed
  3567. */
  3568. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3569. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3570. ts->transmit_cnt > DP_RETRY_COUNT);
  3571. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3572. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3573. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3574. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3575. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3576. length);
  3577. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3578. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3579. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3580. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3581. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3582. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3583. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3584. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3585. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3586. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3587. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3588. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3589. tx.dropped.fw_rem_queue_disable, 1);
  3590. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3591. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3592. tx.dropped.fw_rem_no_match, 1);
  3593. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3594. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3595. tx.dropped.drop_threshold, 1);
  3596. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3597. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3598. tx.dropped.drop_link_desc_na, 1);
  3599. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3600. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3601. tx.dropped.invalid_drop, 1);
  3602. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3603. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3604. tx.dropped.mcast_vdev_drop, 1);
  3605. } else {
  3606. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3607. }
  3608. }
  3609. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3610. /**
  3611. * dp_tx_flow_pool_lock() - take flow pool lock
  3612. * @soc: core txrx main context
  3613. * @tx_desc: tx desc
  3614. *
  3615. * Return: None
  3616. */
  3617. static inline
  3618. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3619. struct dp_tx_desc_s *tx_desc)
  3620. {
  3621. struct dp_tx_desc_pool_s *pool;
  3622. uint8_t desc_pool_id;
  3623. desc_pool_id = tx_desc->pool_id;
  3624. pool = &soc->tx_desc[desc_pool_id];
  3625. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3626. }
  3627. /**
  3628. * dp_tx_flow_pool_unlock() - release flow pool lock
  3629. * @soc: core txrx main context
  3630. * @tx_desc: tx desc
  3631. *
  3632. * Return: None
  3633. */
  3634. static inline
  3635. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3636. struct dp_tx_desc_s *tx_desc)
  3637. {
  3638. struct dp_tx_desc_pool_s *pool;
  3639. uint8_t desc_pool_id;
  3640. desc_pool_id = tx_desc->pool_id;
  3641. pool = &soc->tx_desc[desc_pool_id];
  3642. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3643. }
  3644. #else
  3645. static inline
  3646. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3647. {
  3648. }
  3649. static inline
  3650. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3651. {
  3652. }
  3653. #endif
  3654. /**
  3655. * dp_tx_notify_completion() - Notify tx completion for this desc
  3656. * @soc: core txrx main context
  3657. * @vdev: datapath vdev handle
  3658. * @tx_desc: tx desc
  3659. * @netbuf: buffer
  3660. * @status: tx status
  3661. *
  3662. * Return: none
  3663. */
  3664. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3665. struct dp_vdev *vdev,
  3666. struct dp_tx_desc_s *tx_desc,
  3667. qdf_nbuf_t netbuf,
  3668. uint8_t status)
  3669. {
  3670. void *osif_dev;
  3671. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3672. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3673. qdf_assert(tx_desc);
  3674. dp_tx_flow_pool_lock(soc, tx_desc);
  3675. if (!vdev ||
  3676. !vdev->osif_vdev) {
  3677. dp_tx_flow_pool_unlock(soc, tx_desc);
  3678. return;
  3679. }
  3680. osif_dev = vdev->osif_vdev;
  3681. tx_compl_cbk = vdev->tx_comp;
  3682. dp_tx_flow_pool_unlock(soc, tx_desc);
  3683. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3684. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3685. if (tx_compl_cbk)
  3686. tx_compl_cbk(netbuf, osif_dev, flag);
  3687. }
  3688. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3689. * @pdev: pdev handle
  3690. * @tid: tid value
  3691. * @txdesc_ts: timestamp from txdesc
  3692. * @ppdu_id: ppdu id
  3693. *
  3694. * Return: none
  3695. */
  3696. #ifdef FEATURE_PERPKT_INFO
  3697. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3698. struct dp_txrx_peer *txrx_peer,
  3699. uint8_t tid,
  3700. uint64_t txdesc_ts,
  3701. uint32_t ppdu_id)
  3702. {
  3703. uint64_t delta_ms;
  3704. struct cdp_tx_sojourn_stats *sojourn_stats;
  3705. struct dp_peer *primary_link_peer = NULL;
  3706. struct dp_soc *link_peer_soc = NULL;
  3707. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3708. return;
  3709. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3710. tid >= CDP_DATA_TID_MAX))
  3711. return;
  3712. if (qdf_unlikely(!pdev->sojourn_buf))
  3713. return;
  3714. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3715. txrx_peer->peer_id,
  3716. DP_MOD_ID_TX_COMP);
  3717. if (qdf_unlikely(!primary_link_peer))
  3718. return;
  3719. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3720. qdf_nbuf_data(pdev->sojourn_buf);
  3721. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3722. sojourn_stats->cookie = (void *)
  3723. dp_monitor_peer_get_rdkstats_ctx(link_peer_soc,
  3724. primary_link_peer);
  3725. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3726. txdesc_ts;
  3727. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3728. delta_ms);
  3729. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3730. sojourn_stats->num_msdus[tid] = 1;
  3731. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3732. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3733. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3734. pdev->sojourn_buf, HTT_INVALID_PEER,
  3735. WDI_NO_VAL, pdev->pdev_id);
  3736. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3737. sojourn_stats->num_msdus[tid] = 0;
  3738. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3739. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3740. }
  3741. #else
  3742. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3743. struct dp_txrx_peer *txrx_peer,
  3744. uint8_t tid,
  3745. uint64_t txdesc_ts,
  3746. uint32_t ppdu_id)
  3747. {
  3748. }
  3749. #endif
  3750. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3751. /**
  3752. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3753. * @soc: dp_soc handle
  3754. * @desc: Tx Descriptor
  3755. * @ts: HAL Tx completion descriptor contents
  3756. *
  3757. * This function is used to send tx completion to packet capture
  3758. */
  3759. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3760. struct dp_tx_desc_s *desc,
  3761. struct hal_tx_completion_status *ts)
  3762. {
  3763. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3764. desc, ts->peer_id,
  3765. WDI_NO_VAL, desc->pdev->pdev_id);
  3766. }
  3767. #endif
  3768. /**
  3769. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3770. * @soc: DP Soc handle
  3771. * @tx_desc: software Tx descriptor
  3772. * @ts : Tx completion status from HAL/HTT descriptor
  3773. *
  3774. * Return: none
  3775. */
  3776. void
  3777. dp_tx_comp_process_desc(struct dp_soc *soc,
  3778. struct dp_tx_desc_s *desc,
  3779. struct hal_tx_completion_status *ts,
  3780. struct dp_txrx_peer *txrx_peer)
  3781. {
  3782. uint64_t time_latency = 0;
  3783. uint16_t peer_id = DP_INVALID_PEER_ID;
  3784. /*
  3785. * m_copy/tx_capture modes are not supported for
  3786. * scatter gather packets
  3787. */
  3788. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3789. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3790. desc->timestamp);
  3791. }
  3792. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3793. if (dp_tx_pkt_tracepoints_enabled())
  3794. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3795. desc->msdu_ext_desc ?
  3796. desc->msdu_ext_desc->tso_desc : NULL,
  3797. desc->timestamp);
  3798. if (!(desc->msdu_ext_desc)) {
  3799. dp_tx_enh_unmap(soc, desc);
  3800. if (txrx_peer)
  3801. peer_id = txrx_peer->peer_id;
  3802. if (QDF_STATUS_SUCCESS ==
  3803. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  3804. return;
  3805. }
  3806. if (QDF_STATUS_SUCCESS ==
  3807. dp_get_completion_indication_for_stack(soc,
  3808. desc->pdev,
  3809. txrx_peer, ts,
  3810. desc->nbuf,
  3811. time_latency)) {
  3812. dp_send_completion_to_stack(soc,
  3813. desc->pdev,
  3814. ts->peer_id,
  3815. ts->ppdu_id,
  3816. desc->nbuf);
  3817. return;
  3818. }
  3819. }
  3820. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3821. dp_tx_comp_free_buf(soc, desc);
  3822. }
  3823. #ifdef DISABLE_DP_STATS
  3824. /**
  3825. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3826. * @soc: core txrx main context
  3827. * @tx_desc: tx desc
  3828. * @status: tx status
  3829. *
  3830. * Return: none
  3831. */
  3832. static inline
  3833. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3834. struct dp_vdev *vdev,
  3835. struct dp_tx_desc_s *tx_desc,
  3836. uint8_t status)
  3837. {
  3838. }
  3839. #else
  3840. static inline
  3841. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3842. struct dp_vdev *vdev,
  3843. struct dp_tx_desc_s *tx_desc,
  3844. uint8_t status)
  3845. {
  3846. void *osif_dev;
  3847. ol_txrx_stats_rx_fp stats_cbk;
  3848. uint8_t pkt_type;
  3849. qdf_assert(tx_desc);
  3850. if (!vdev ||
  3851. !vdev->osif_vdev ||
  3852. !vdev->stats_cb)
  3853. return;
  3854. osif_dev = vdev->osif_vdev;
  3855. stats_cbk = vdev->stats_cb;
  3856. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3857. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3858. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3859. &pkt_type);
  3860. }
  3861. #endif
  3862. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF)
  3863. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3864. uint32_t delta_tsf)
  3865. {
  3866. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3867. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3868. DP_MOD_ID_CDP);
  3869. if (!vdev) {
  3870. dp_err_rl("vdev %d does not exist", vdev_id);
  3871. return;
  3872. }
  3873. vdev->delta_tsf = delta_tsf;
  3874. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3875. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3876. }
  3877. #endif
  3878. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3879. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3880. uint8_t vdev_id, bool enable)
  3881. {
  3882. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3883. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3884. DP_MOD_ID_CDP);
  3885. if (!vdev) {
  3886. dp_err_rl("vdev %d does not exist", vdev_id);
  3887. return QDF_STATUS_E_FAILURE;
  3888. }
  3889. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3890. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3891. return QDF_STATUS_SUCCESS;
  3892. }
  3893. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3894. uint32_t *val)
  3895. {
  3896. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3897. struct dp_vdev *vdev;
  3898. uint32_t delay_accum;
  3899. uint32_t pkts_accum;
  3900. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3901. if (!vdev) {
  3902. dp_err_rl("vdev %d does not exist", vdev_id);
  3903. return QDF_STATUS_E_FAILURE;
  3904. }
  3905. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3906. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3907. return QDF_STATUS_E_FAILURE;
  3908. }
  3909. /* Average uplink delay based on current accumulated values */
  3910. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3911. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3912. *val = delay_accum / pkts_accum;
  3913. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3914. delay_accum, pkts_accum);
  3915. /* Reset accumulated values to 0 */
  3916. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3917. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3919. return QDF_STATUS_SUCCESS;
  3920. }
  3921. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3922. struct hal_tx_completion_status *ts)
  3923. {
  3924. uint32_t buffer_ts;
  3925. uint32_t delta_tsf;
  3926. uint32_t ul_delay;
  3927. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3928. if (!ts->valid)
  3929. return;
  3930. if (qdf_unlikely(!vdev)) {
  3931. dp_info_rl("vdev is null or delete in progrss");
  3932. return;
  3933. }
  3934. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3935. return;
  3936. delta_tsf = vdev->delta_tsf;
  3937. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3938. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3939. * valid up to 29 bits.
  3940. */
  3941. buffer_ts = ts->buffer_timestamp << 10;
  3942. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3943. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3944. if (ul_delay > 0x1000000) {
  3945. dp_info_rl("----------------------\n"
  3946. "Tx completion status:\n"
  3947. "----------------------\n"
  3948. "release_src = %d\n"
  3949. "ppdu_id = 0x%x\n"
  3950. "release_reason = %d\n"
  3951. "tsf = %u (0x%x)\n"
  3952. "buffer_timestamp = %u (0x%x)\n"
  3953. "delta_tsf = %u (0x%x)\n",
  3954. ts->release_src, ts->ppdu_id, ts->status,
  3955. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3956. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3957. return;
  3958. }
  3959. ul_delay /= 1000; /* in unit of ms */
  3960. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3961. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3962. }
  3963. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3964. static inline
  3965. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3966. struct hal_tx_completion_status *ts)
  3967. {
  3968. }
  3969. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3970. /**
  3971. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3972. * @soc: DP soc handle
  3973. * @tx_desc: software descriptor head pointer
  3974. * @ts: Tx completion status
  3975. * @txrx_peer: txrx peer handle
  3976. * @ring_id: ring number
  3977. *
  3978. * Return: none
  3979. */
  3980. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3981. struct dp_tx_desc_s *tx_desc,
  3982. struct hal_tx_completion_status *ts,
  3983. struct dp_txrx_peer *txrx_peer,
  3984. uint8_t ring_id)
  3985. {
  3986. uint32_t length;
  3987. qdf_ether_header_t *eh;
  3988. struct dp_vdev *vdev = NULL;
  3989. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3990. enum qdf_dp_tx_rx_status dp_status;
  3991. if (!nbuf) {
  3992. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3993. goto out;
  3994. }
  3995. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3996. length = qdf_nbuf_len(nbuf);
  3997. dp_status = dp_tx_hw_to_qdf(ts->status);
  3998. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3999. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4000. QDF_TRACE_DEFAULT_PDEV_ID,
  4001. qdf_nbuf_data_addr(nbuf),
  4002. sizeof(qdf_nbuf_data(nbuf)),
  4003. tx_desc->id, ts->status, dp_status));
  4004. dp_tx_comp_debug("-------------------- \n"
  4005. "Tx Completion Stats: \n"
  4006. "-------------------- \n"
  4007. "ack_frame_rssi = %d \n"
  4008. "first_msdu = %d \n"
  4009. "last_msdu = %d \n"
  4010. "msdu_part_of_amsdu = %d \n"
  4011. "rate_stats valid = %d \n"
  4012. "bw = %d \n"
  4013. "pkt_type = %d \n"
  4014. "stbc = %d \n"
  4015. "ldpc = %d \n"
  4016. "sgi = %d \n"
  4017. "mcs = %d \n"
  4018. "ofdma = %d \n"
  4019. "tones_in_ru = %d \n"
  4020. "tsf = %d \n"
  4021. "ppdu_id = %d \n"
  4022. "transmit_cnt = %d \n"
  4023. "tid = %d \n"
  4024. "peer_id = %d\n"
  4025. "tx_status = %d\n",
  4026. ts->ack_frame_rssi, ts->first_msdu,
  4027. ts->last_msdu, ts->msdu_part_of_amsdu,
  4028. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4029. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4030. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4031. ts->transmit_cnt, ts->tid, ts->peer_id,
  4032. ts->status);
  4033. /* Update SoC level stats */
  4034. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4035. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4036. if (!txrx_peer) {
  4037. dp_info_rl("peer is null or deletion in progress");
  4038. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4039. goto out;
  4040. }
  4041. vdev = txrx_peer->vdev;
  4042. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4043. dp_tx_update_uplink_delay(soc, vdev, ts);
  4044. /* Update per-packet stats for mesh mode */
  4045. if (qdf_unlikely(vdev->mesh_vdev) &&
  4046. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4047. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4048. /* Update peer level stats */
  4049. if (qdf_unlikely(txrx_peer->bss_peer &&
  4050. vdev->opmode == wlan_op_mode_ap)) {
  4051. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4052. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4053. length);
  4054. if (txrx_peer->vdev->tx_encap_type ==
  4055. htt_cmn_pkt_type_ethernet &&
  4056. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4057. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4058. tx.bcast, 1,
  4059. length);
  4060. }
  4061. }
  4062. } else {
  4063. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4064. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4065. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4066. 1, length);
  4067. if (qdf_unlikely(txrx_peer->in_twt)) {
  4068. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4069. tx.tx_success_twt,
  4070. 1, length);
  4071. }
  4072. }
  4073. }
  4074. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4075. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4076. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4077. ts, ts->tid);
  4078. #ifdef QCA_SUPPORT_RDK_STATS
  4079. if (soc->rdkstats_enabled)
  4080. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4081. tx_desc->timestamp,
  4082. ts->ppdu_id);
  4083. #endif
  4084. out:
  4085. return;
  4086. }
  4087. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4088. defined(QCA_ENHANCED_STATS_SUPPORT)
  4089. /*
  4090. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4091. * @txrx_peer: Datapath txrx_peer handle
  4092. * @length: Length of the packet
  4093. * @tx_status: Tx status from TQM/FW
  4094. * @update: enhanced flag value present in dp_pdev
  4095. *
  4096. * Return: none
  4097. */
  4098. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4099. uint32_t length, uint8_t tx_status,
  4100. bool update)
  4101. {
  4102. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  4103. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4104. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4105. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4106. }
  4107. }
  4108. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4109. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4110. uint32_t length, uint8_t tx_status,
  4111. bool update)
  4112. {
  4113. if (!peer->hw_txrx_stats_en) {
  4114. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4115. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4116. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4117. }
  4118. }
  4119. #else
  4120. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4121. uint32_t length, uint8_t tx_status,
  4122. bool update)
  4123. {
  4124. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4125. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4126. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4127. }
  4128. #endif
  4129. /*
  4130. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4131. * @nbuf: skb buffer
  4132. *
  4133. * Return: none
  4134. */
  4135. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4136. static inline
  4137. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4138. {
  4139. qdf_nbuf_t nbuf = NULL;
  4140. if (next)
  4141. nbuf = next->nbuf;
  4142. if (nbuf) {
  4143. /* prefetch skb->next and first few bytes of skb->cb */
  4144. qdf_prefetch(nbuf);
  4145. /* prefetch skb fields present in different cachelines */
  4146. qdf_prefetch(&nbuf->len);
  4147. qdf_prefetch(&nbuf->users);
  4148. }
  4149. }
  4150. #else
  4151. static inline
  4152. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4153. {
  4154. }
  4155. #endif
  4156. /**
  4157. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4158. * @soc: core txrx main context
  4159. * @comp_head: software descriptor head pointer
  4160. * @ring_id: ring number
  4161. *
  4162. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4163. * and release the software descriptors after processing is complete
  4164. *
  4165. * Return: none
  4166. */
  4167. static void
  4168. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4169. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4170. {
  4171. struct dp_tx_desc_s *desc;
  4172. struct dp_tx_desc_s *next;
  4173. struct hal_tx_completion_status ts;
  4174. struct dp_txrx_peer *txrx_peer = NULL;
  4175. uint16_t peer_id = DP_INVALID_PEER;
  4176. qdf_nbuf_t netbuf;
  4177. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4178. desc = comp_head;
  4179. while (desc) {
  4180. next = desc->next;
  4181. dp_tx_prefetch_next_nbuf_data(next);
  4182. if (peer_id != desc->peer_id) {
  4183. if (txrx_peer)
  4184. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4185. DP_MOD_ID_TX_COMP);
  4186. peer_id = desc->peer_id;
  4187. txrx_peer =
  4188. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4189. &txrx_ref_handle,
  4190. DP_MOD_ID_TX_COMP);
  4191. }
  4192. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4193. struct dp_pdev *pdev = desc->pdev;
  4194. if (qdf_likely(txrx_peer))
  4195. dp_tx_update_peer_basic_stats(txrx_peer,
  4196. desc->length,
  4197. desc->tx_status,
  4198. false);
  4199. qdf_assert(pdev);
  4200. dp_tx_outstanding_dec(pdev);
  4201. /*
  4202. * Calling a QDF WRAPPER here is creating signifcant
  4203. * performance impact so avoided the wrapper call here
  4204. */
  4205. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4206. desc->id, DP_TX_COMP_UNMAP);
  4207. dp_tx_nbuf_unmap(soc, desc);
  4208. qdf_nbuf_free(desc->nbuf);
  4209. dp_tx_desc_free(soc, desc, desc->pool_id);
  4210. desc = next;
  4211. continue;
  4212. }
  4213. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4214. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4215. ring_id);
  4216. netbuf = desc->nbuf;
  4217. /* check tx complete notification */
  4218. if (txrx_peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  4219. dp_tx_notify_completion(soc, txrx_peer->vdev, desc,
  4220. netbuf, ts.status);
  4221. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4222. dp_tx_desc_release(desc, desc->pool_id);
  4223. desc = next;
  4224. }
  4225. if (txrx_peer)
  4226. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4227. }
  4228. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4229. static inline
  4230. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4231. int max_reap_limit)
  4232. {
  4233. bool limit_hit = false;
  4234. limit_hit =
  4235. (num_reaped >= max_reap_limit) ? true : false;
  4236. if (limit_hit)
  4237. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4238. return limit_hit;
  4239. }
  4240. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4241. {
  4242. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4243. }
  4244. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4245. {
  4246. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4247. return cfg->tx_comp_loop_pkt_limit;
  4248. }
  4249. #else
  4250. static inline
  4251. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4252. int max_reap_limit)
  4253. {
  4254. return false;
  4255. }
  4256. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4257. {
  4258. return false;
  4259. }
  4260. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4261. {
  4262. return 0;
  4263. }
  4264. #endif
  4265. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4266. static inline int
  4267. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4268. int *max_reap_limit)
  4269. {
  4270. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4271. max_reap_limit);
  4272. }
  4273. #else
  4274. static inline int
  4275. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4276. int *max_reap_limit)
  4277. {
  4278. return 0;
  4279. }
  4280. #endif
  4281. #ifdef DP_TX_TRACKING
  4282. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4283. {
  4284. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4285. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4286. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4287. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4288. }
  4289. }
  4290. #endif
  4291. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4292. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4293. uint32_t quota)
  4294. {
  4295. void *tx_comp_hal_desc;
  4296. void *last_prefetched_hw_desc = NULL;
  4297. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4298. hal_soc_handle_t hal_soc;
  4299. uint8_t buffer_src;
  4300. struct dp_tx_desc_s *tx_desc = NULL;
  4301. struct dp_tx_desc_s *head_desc = NULL;
  4302. struct dp_tx_desc_s *tail_desc = NULL;
  4303. uint32_t num_processed = 0;
  4304. uint32_t count;
  4305. uint32_t num_avail_for_reap = 0;
  4306. bool force_break = false;
  4307. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4308. int max_reap_limit, ring_near_full;
  4309. DP_HIST_INIT();
  4310. more_data:
  4311. hal_soc = soc->hal_soc;
  4312. /* Re-initialize local variables to be re-used */
  4313. head_desc = NULL;
  4314. tail_desc = NULL;
  4315. count = 0;
  4316. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4317. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4318. &max_reap_limit);
  4319. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4320. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4321. return 0;
  4322. }
  4323. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4324. if (num_avail_for_reap >= quota)
  4325. num_avail_for_reap = quota;
  4326. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4327. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4328. num_avail_for_reap);
  4329. /* Find head descriptor from completion ring */
  4330. while (qdf_likely(num_avail_for_reap--)) {
  4331. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4332. if (qdf_unlikely(!tx_comp_hal_desc))
  4333. break;
  4334. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4335. tx_comp_hal_desc);
  4336. /* If this buffer was not released by TQM or FW, then it is not
  4337. * Tx completion indication, assert */
  4338. if (qdf_unlikely(buffer_src !=
  4339. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4340. (qdf_unlikely(buffer_src !=
  4341. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4342. uint8_t wbm_internal_error;
  4343. dp_err_rl(
  4344. "Tx comp release_src != TQM | FW but from %d",
  4345. buffer_src);
  4346. hal_dump_comp_desc(tx_comp_hal_desc);
  4347. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4348. /* When WBM sees NULL buffer_addr_info in any of
  4349. * ingress rings it sends an error indication,
  4350. * with wbm_internal_error=1, to a specific ring.
  4351. * The WBM2SW ring used to indicate these errors is
  4352. * fixed in HW, and that ring is being used as Tx
  4353. * completion ring. These errors are not related to
  4354. * Tx completions, and should just be ignored
  4355. */
  4356. wbm_internal_error = hal_get_wbm_internal_error(
  4357. hal_soc,
  4358. tx_comp_hal_desc);
  4359. if (wbm_internal_error) {
  4360. dp_err_rl("Tx comp wbm_internal_error!!");
  4361. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4362. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4363. buffer_src)
  4364. dp_handle_wbm_internal_error(
  4365. soc,
  4366. tx_comp_hal_desc,
  4367. hal_tx_comp_get_buffer_type(
  4368. tx_comp_hal_desc));
  4369. } else {
  4370. dp_err_rl("Tx comp wbm_internal_error false");
  4371. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4372. }
  4373. continue;
  4374. }
  4375. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4376. tx_comp_hal_desc,
  4377. &tx_desc);
  4378. if (!tx_desc) {
  4379. dp_err("unable to retrieve tx_desc!");
  4380. QDF_BUG(0);
  4381. continue;
  4382. }
  4383. tx_desc->buffer_src = buffer_src;
  4384. /*
  4385. * If the release source is FW, process the HTT status
  4386. */
  4387. if (qdf_unlikely(buffer_src ==
  4388. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4389. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4390. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4391. htt_tx_status);
  4392. /* Collect hw completion contents */
  4393. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4394. &tx_desc->comp, 1);
  4395. soc->arch_ops.dp_tx_process_htt_completion(
  4396. soc,
  4397. tx_desc,
  4398. htt_tx_status,
  4399. ring_id);
  4400. } else {
  4401. tx_desc->tx_status =
  4402. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4403. tx_desc->buffer_src = buffer_src;
  4404. /*
  4405. * If the fast completion mode is enabled extended
  4406. * metadata from descriptor is not copied
  4407. */
  4408. if (qdf_likely(tx_desc->flags &
  4409. DP_TX_DESC_FLAG_SIMPLE))
  4410. goto add_to_pool;
  4411. /*
  4412. * If the descriptor is already freed in vdev_detach,
  4413. * continue to next descriptor
  4414. */
  4415. if (qdf_unlikely
  4416. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4417. !tx_desc->flags)) {
  4418. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4419. tx_desc->id);
  4420. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4421. dp_tx_desc_check_corruption(tx_desc);
  4422. continue;
  4423. }
  4424. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4425. dp_tx_comp_info_rl("pdev in down state %d",
  4426. tx_desc->id);
  4427. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4428. dp_tx_comp_free_buf(soc, tx_desc);
  4429. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4430. goto next_desc;
  4431. }
  4432. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4433. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4434. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4435. tx_desc->flags, tx_desc->id);
  4436. qdf_assert_always(0);
  4437. }
  4438. /* Collect hw completion contents */
  4439. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4440. &tx_desc->comp, 1);
  4441. add_to_pool:
  4442. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4443. /* First ring descriptor on the cycle */
  4444. if (!head_desc) {
  4445. head_desc = tx_desc;
  4446. tail_desc = tx_desc;
  4447. }
  4448. tail_desc->next = tx_desc;
  4449. tx_desc->next = NULL;
  4450. tail_desc = tx_desc;
  4451. }
  4452. next_desc:
  4453. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4454. /*
  4455. * Processed packet count is more than given quota
  4456. * stop to processing
  4457. */
  4458. count++;
  4459. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4460. num_avail_for_reap,
  4461. hal_ring_hdl,
  4462. &last_prefetched_hw_desc,
  4463. &last_prefetched_sw_desc);
  4464. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4465. break;
  4466. }
  4467. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4468. /* Process the reaped descriptors */
  4469. if (head_desc)
  4470. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4471. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4472. /*
  4473. * If we are processing in near-full condition, there are 3 scenario
  4474. * 1) Ring entries has reached critical state
  4475. * 2) Ring entries are still near high threshold
  4476. * 3) Ring entries are below the safe level
  4477. *
  4478. * One more loop will move te state to normal processing and yield
  4479. */
  4480. if (ring_near_full)
  4481. goto more_data;
  4482. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4483. if (num_processed >= quota)
  4484. force_break = true;
  4485. if (!force_break &&
  4486. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4487. hal_ring_hdl)) {
  4488. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4489. if (!hif_exec_should_yield(soc->hif_handle,
  4490. int_ctx->dp_intr_id))
  4491. goto more_data;
  4492. }
  4493. }
  4494. DP_TX_HIST_STATS_PER_PDEV();
  4495. return num_processed;
  4496. }
  4497. #ifdef FEATURE_WLAN_TDLS
  4498. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4499. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4500. {
  4501. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4502. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4503. DP_MOD_ID_TDLS);
  4504. if (!vdev) {
  4505. dp_err("vdev handle for id %d is NULL", vdev_id);
  4506. return NULL;
  4507. }
  4508. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4509. vdev->is_tdls_frame = true;
  4510. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4511. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4512. }
  4513. #endif
  4514. /**
  4515. * dp_tx_vdev_attach() - attach vdev to dp tx
  4516. * @vdev: virtual device instance
  4517. *
  4518. * Return: QDF_STATUS_SUCCESS: success
  4519. * QDF_STATUS_E_RESOURCES: Error return
  4520. */
  4521. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4522. {
  4523. int pdev_id;
  4524. /*
  4525. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4526. */
  4527. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4528. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4529. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4530. vdev->vdev_id);
  4531. pdev_id =
  4532. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4533. vdev->pdev->pdev_id);
  4534. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4535. /*
  4536. * Set HTT Extension Valid bit to 0 by default
  4537. */
  4538. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4539. dp_tx_vdev_update_search_flags(vdev);
  4540. return QDF_STATUS_SUCCESS;
  4541. }
  4542. #ifndef FEATURE_WDS
  4543. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4544. {
  4545. return false;
  4546. }
  4547. #endif
  4548. /**
  4549. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4550. * @vdev: virtual device instance
  4551. *
  4552. * Return: void
  4553. *
  4554. */
  4555. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4556. {
  4557. struct dp_soc *soc = vdev->pdev->soc;
  4558. /*
  4559. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4560. * for TDLS link
  4561. *
  4562. * Enable AddrY (SA based search) only for non-WDS STA and
  4563. * ProxySTA VAP (in HKv1) modes.
  4564. *
  4565. * In all other VAP modes, only DA based search should be
  4566. * enabled
  4567. */
  4568. if (vdev->opmode == wlan_op_mode_sta &&
  4569. vdev->tdls_link_connected)
  4570. vdev->hal_desc_addr_search_flags =
  4571. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4572. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4573. !dp_tx_da_search_override(vdev))
  4574. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4575. else
  4576. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4577. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4578. vdev->search_type = soc->sta_mode_search_policy;
  4579. else
  4580. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4581. }
  4582. static inline bool
  4583. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4584. struct dp_vdev *vdev,
  4585. struct dp_tx_desc_s *tx_desc)
  4586. {
  4587. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4588. return false;
  4589. /*
  4590. * if vdev is given, then only check whether desc
  4591. * vdev match. if vdev is NULL, then check whether
  4592. * desc pdev match.
  4593. */
  4594. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4595. (tx_desc->pdev == pdev);
  4596. }
  4597. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4598. /**
  4599. * dp_tx_desc_flush() - release resources associated
  4600. * to TX Desc
  4601. *
  4602. * @dp_pdev: Handle to DP pdev structure
  4603. * @vdev: virtual device instance
  4604. * NULL: no specific Vdev is required and check all allcated TX desc
  4605. * on this pdev.
  4606. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4607. *
  4608. * @force_free:
  4609. * true: flush the TX desc.
  4610. * false: only reset the Vdev in each allocated TX desc
  4611. * that associated to current Vdev.
  4612. *
  4613. * This function will go through the TX desc pool to flush
  4614. * the outstanding TX data or reset Vdev to NULL in associated TX
  4615. * Desc.
  4616. */
  4617. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4618. bool force_free)
  4619. {
  4620. uint8_t i;
  4621. uint32_t j;
  4622. uint32_t num_desc, page_id, offset;
  4623. uint16_t num_desc_per_page;
  4624. struct dp_soc *soc = pdev->soc;
  4625. struct dp_tx_desc_s *tx_desc = NULL;
  4626. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4627. if (!vdev && !force_free) {
  4628. dp_err("Reset TX desc vdev, Vdev param is required!");
  4629. return;
  4630. }
  4631. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4632. tx_desc_pool = &soc->tx_desc[i];
  4633. if (!(tx_desc_pool->pool_size) ||
  4634. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4635. !(tx_desc_pool->desc_pages.cacheable_pages))
  4636. continue;
  4637. /*
  4638. * Add flow pool lock protection in case pool is freed
  4639. * due to all tx_desc is recycled when handle TX completion.
  4640. * this is not necessary when do force flush as:
  4641. * a. double lock will happen if dp_tx_desc_release is
  4642. * also trying to acquire it.
  4643. * b. dp interrupt has been disabled before do force TX desc
  4644. * flush in dp_pdev_deinit().
  4645. */
  4646. if (!force_free)
  4647. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4648. num_desc = tx_desc_pool->pool_size;
  4649. num_desc_per_page =
  4650. tx_desc_pool->desc_pages.num_element_per_page;
  4651. for (j = 0; j < num_desc; j++) {
  4652. page_id = j / num_desc_per_page;
  4653. offset = j % num_desc_per_page;
  4654. if (qdf_unlikely(!(tx_desc_pool->
  4655. desc_pages.cacheable_pages)))
  4656. break;
  4657. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4658. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4659. /*
  4660. * Free TX desc if force free is
  4661. * required, otherwise only reset vdev
  4662. * in this TX desc.
  4663. */
  4664. if (force_free) {
  4665. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4666. dp_tx_comp_free_buf(soc, tx_desc);
  4667. dp_tx_desc_release(tx_desc, i);
  4668. } else {
  4669. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4670. }
  4671. }
  4672. }
  4673. if (!force_free)
  4674. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4675. }
  4676. }
  4677. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4678. /**
  4679. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4680. *
  4681. * @soc: Handle to DP soc structure
  4682. * @tx_desc: pointer of one TX desc
  4683. * @desc_pool_id: TX Desc pool id
  4684. */
  4685. static inline void
  4686. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4687. uint8_t desc_pool_id)
  4688. {
  4689. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4690. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4691. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4692. }
  4693. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4694. bool force_free)
  4695. {
  4696. uint8_t i, num_pool;
  4697. uint32_t j;
  4698. uint32_t num_desc, page_id, offset;
  4699. uint16_t num_desc_per_page;
  4700. struct dp_soc *soc = pdev->soc;
  4701. struct dp_tx_desc_s *tx_desc = NULL;
  4702. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4703. if (!vdev && !force_free) {
  4704. dp_err("Reset TX desc vdev, Vdev param is required!");
  4705. return;
  4706. }
  4707. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4708. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4709. for (i = 0; i < num_pool; i++) {
  4710. tx_desc_pool = &soc->tx_desc[i];
  4711. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4712. continue;
  4713. num_desc_per_page =
  4714. tx_desc_pool->desc_pages.num_element_per_page;
  4715. for (j = 0; j < num_desc; j++) {
  4716. page_id = j / num_desc_per_page;
  4717. offset = j % num_desc_per_page;
  4718. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4719. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4720. if (force_free) {
  4721. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4722. dp_tx_comp_free_buf(soc, tx_desc);
  4723. dp_tx_desc_release(tx_desc, i);
  4724. } else {
  4725. dp_tx_desc_reset_vdev(soc, tx_desc,
  4726. i);
  4727. }
  4728. }
  4729. }
  4730. }
  4731. }
  4732. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4733. /**
  4734. * dp_tx_vdev_detach() - detach vdev from dp tx
  4735. * @vdev: virtual device instance
  4736. *
  4737. * Return: QDF_STATUS_SUCCESS: success
  4738. * QDF_STATUS_E_RESOURCES: Error return
  4739. */
  4740. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4741. {
  4742. struct dp_pdev *pdev = vdev->pdev;
  4743. /* Reset TX desc associated to this Vdev as NULL */
  4744. dp_tx_desc_flush(pdev, vdev, false);
  4745. return QDF_STATUS_SUCCESS;
  4746. }
  4747. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4748. /* Pools will be allocated dynamically */
  4749. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4750. int num_desc)
  4751. {
  4752. uint8_t i;
  4753. for (i = 0; i < num_pool; i++) {
  4754. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4755. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4756. }
  4757. return QDF_STATUS_SUCCESS;
  4758. }
  4759. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4760. uint32_t num_desc)
  4761. {
  4762. return QDF_STATUS_SUCCESS;
  4763. }
  4764. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4765. {
  4766. }
  4767. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4768. {
  4769. uint8_t i;
  4770. for (i = 0; i < num_pool; i++)
  4771. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4772. }
  4773. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4774. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4775. uint32_t num_desc)
  4776. {
  4777. uint8_t i, count;
  4778. /* Allocate software Tx descriptor pools */
  4779. for (i = 0; i < num_pool; i++) {
  4780. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4781. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4782. FL("Tx Desc Pool alloc %d failed %pK"),
  4783. i, soc);
  4784. goto fail;
  4785. }
  4786. }
  4787. return QDF_STATUS_SUCCESS;
  4788. fail:
  4789. for (count = 0; count < i; count++)
  4790. dp_tx_desc_pool_free(soc, count);
  4791. return QDF_STATUS_E_NOMEM;
  4792. }
  4793. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4794. uint32_t num_desc)
  4795. {
  4796. uint8_t i;
  4797. for (i = 0; i < num_pool; i++) {
  4798. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4799. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4800. FL("Tx Desc Pool init %d failed %pK"),
  4801. i, soc);
  4802. return QDF_STATUS_E_NOMEM;
  4803. }
  4804. }
  4805. return QDF_STATUS_SUCCESS;
  4806. }
  4807. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4808. {
  4809. uint8_t i;
  4810. for (i = 0; i < num_pool; i++)
  4811. dp_tx_desc_pool_deinit(soc, i);
  4812. }
  4813. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4814. {
  4815. uint8_t i;
  4816. for (i = 0; i < num_pool; i++)
  4817. dp_tx_desc_pool_free(soc, i);
  4818. }
  4819. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4820. /**
  4821. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4822. * @soc: core txrx main context
  4823. * @num_pool: number of pools
  4824. *
  4825. */
  4826. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4827. {
  4828. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4829. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4830. }
  4831. /**
  4832. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4833. * @soc: core txrx main context
  4834. * @num_pool: number of pools
  4835. *
  4836. */
  4837. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4838. {
  4839. dp_tx_tso_desc_pool_free(soc, num_pool);
  4840. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4841. }
  4842. /**
  4843. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4844. * @soc: core txrx main context
  4845. *
  4846. * This function frees all tx related descriptors as below
  4847. * 1. Regular TX descriptors (static pools)
  4848. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4849. * 3. TSO descriptors
  4850. *
  4851. */
  4852. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4853. {
  4854. uint8_t num_pool;
  4855. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4856. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4857. dp_tx_ext_desc_pool_free(soc, num_pool);
  4858. dp_tx_delete_static_pools(soc, num_pool);
  4859. }
  4860. /**
  4861. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4862. * @soc: core txrx main context
  4863. *
  4864. * This function de-initializes all tx related descriptors as below
  4865. * 1. Regular TX descriptors (static pools)
  4866. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4867. * 3. TSO descriptors
  4868. *
  4869. */
  4870. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4871. {
  4872. uint8_t num_pool;
  4873. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4874. dp_tx_flow_control_deinit(soc);
  4875. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4876. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4877. dp_tx_deinit_static_pools(soc, num_pool);
  4878. }
  4879. /**
  4880. * dp_tso_attach() - TSO attach handler
  4881. * @txrx_soc: Opaque Dp handle
  4882. *
  4883. * Reserve TSO descriptor buffers
  4884. *
  4885. * Return: QDF_STATUS_E_FAILURE on failure or
  4886. * QDF_STATUS_SUCCESS on success
  4887. */
  4888. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4889. uint8_t num_pool,
  4890. uint32_t num_desc)
  4891. {
  4892. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4893. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4894. return QDF_STATUS_E_FAILURE;
  4895. }
  4896. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4897. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4898. num_pool, soc);
  4899. return QDF_STATUS_E_FAILURE;
  4900. }
  4901. return QDF_STATUS_SUCCESS;
  4902. }
  4903. /**
  4904. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4905. * @soc: DP soc handle
  4906. * @num_pool: Number of pools
  4907. * @num_desc: Number of descriptors
  4908. *
  4909. * Initialize TSO descriptor pools
  4910. *
  4911. * Return: QDF_STATUS_E_FAILURE on failure or
  4912. * QDF_STATUS_SUCCESS on success
  4913. */
  4914. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4915. uint8_t num_pool,
  4916. uint32_t num_desc)
  4917. {
  4918. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4919. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4920. return QDF_STATUS_E_FAILURE;
  4921. }
  4922. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4923. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4924. num_pool, soc);
  4925. return QDF_STATUS_E_FAILURE;
  4926. }
  4927. return QDF_STATUS_SUCCESS;
  4928. }
  4929. /**
  4930. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4931. * @soc: core txrx main context
  4932. *
  4933. * This function allocates memory for following descriptor pools
  4934. * 1. regular sw tx descriptor pools (static pools)
  4935. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4936. * 3. TSO descriptor pools
  4937. *
  4938. * Return: QDF_STATUS_SUCCESS: success
  4939. * QDF_STATUS_E_RESOURCES: Error return
  4940. */
  4941. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4942. {
  4943. uint8_t num_pool;
  4944. uint32_t num_desc;
  4945. uint32_t num_ext_desc;
  4946. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4947. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4948. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4949. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4950. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4951. __func__, num_pool, num_desc);
  4952. if ((num_pool > MAX_TXDESC_POOLS) ||
  4953. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4954. goto fail1;
  4955. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4956. goto fail1;
  4957. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4958. goto fail2;
  4959. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4960. return QDF_STATUS_SUCCESS;
  4961. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4962. goto fail3;
  4963. return QDF_STATUS_SUCCESS;
  4964. fail3:
  4965. dp_tx_ext_desc_pool_free(soc, num_pool);
  4966. fail2:
  4967. dp_tx_delete_static_pools(soc, num_pool);
  4968. fail1:
  4969. return QDF_STATUS_E_RESOURCES;
  4970. }
  4971. /**
  4972. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4973. * @soc: core txrx main context
  4974. *
  4975. * This function initializes the following TX descriptor pools
  4976. * 1. regular sw tx descriptor pools (static pools)
  4977. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4978. * 3. TSO descriptor pools
  4979. *
  4980. * Return: QDF_STATUS_SUCCESS: success
  4981. * QDF_STATUS_E_RESOURCES: Error return
  4982. */
  4983. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4984. {
  4985. uint8_t num_pool;
  4986. uint32_t num_desc;
  4987. uint32_t num_ext_desc;
  4988. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4989. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4990. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4991. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4992. goto fail1;
  4993. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4994. goto fail2;
  4995. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4996. return QDF_STATUS_SUCCESS;
  4997. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4998. goto fail3;
  4999. dp_tx_flow_control_init(soc);
  5000. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5001. return QDF_STATUS_SUCCESS;
  5002. fail3:
  5003. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5004. fail2:
  5005. dp_tx_deinit_static_pools(soc, num_pool);
  5006. fail1:
  5007. return QDF_STATUS_E_RESOURCES;
  5008. }
  5009. /**
  5010. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5011. * @txrx_soc: dp soc handle
  5012. *
  5013. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5014. * QDF_STATUS_E_FAILURE
  5015. */
  5016. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5017. {
  5018. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5019. uint8_t num_pool;
  5020. uint32_t num_desc;
  5021. uint32_t num_ext_desc;
  5022. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5023. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5024. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5025. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5026. return QDF_STATUS_E_FAILURE;
  5027. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5028. return QDF_STATUS_E_FAILURE;
  5029. return QDF_STATUS_SUCCESS;
  5030. }
  5031. /**
  5032. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5033. * @txrx_soc: dp soc handle
  5034. *
  5035. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5036. */
  5037. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5038. {
  5039. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5040. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5041. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5042. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5043. return QDF_STATUS_SUCCESS;
  5044. }