main.c 114 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "cnss_utils.h"
  28. #include "main.h"
  29. #include "bus.h"
  30. #include "debug.h"
  31. #include "genl.h"
  32. #include "reg.h"
  33. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  34. #include "smcinvoke.h"
  35. #include "smcinvoke_object.h"
  36. #include "IClientEnv.h"
  37. #define HW_STATE_UID 0x108
  38. #define HW_OP_GET_STATE 1
  39. #define HW_WIFI_UID 0x508
  40. #define FEATURE_NOT_SUPPORTED 12
  41. #define PERIPHERAL_NOT_FOUND 10
  42. #endif
  43. #define CNSS_DUMP_FORMAT_VER 0x11
  44. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  45. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  46. #define CNSS_DUMP_NAME "CNSS_WLAN"
  47. #define CNSS_DUMP_DESC_SIZE 0x1000
  48. #define CNSS_DUMP_SEG_VER 0x1
  49. #define FILE_SYSTEM_READY 1
  50. #define FW_READY_TIMEOUT 20000
  51. #define FW_ASSERT_TIMEOUT 5000
  52. #define CNSS_EVENT_PENDING 2989
  53. #define POWER_RESET_MIN_DELAY_MS 100
  54. #define CNSS_QUIRKS_DEFAULT 0
  55. #ifdef CONFIG_CNSS_EMULATION
  56. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  57. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  58. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  59. #else
  60. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  61. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  62. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  63. #endif
  64. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  65. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  66. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  67. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  68. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  69. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  70. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  71. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  72. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  73. enum cnss_cal_db_op {
  74. CNSS_CAL_DB_UPLOAD,
  75. CNSS_CAL_DB_DOWNLOAD,
  76. CNSS_CAL_DB_INVALID_OP,
  77. };
  78. enum cnss_recovery_type {
  79. CNSS_WLAN_RECOVERY = 0x1,
  80. CNSS_PCSS_RECOVERY = 0x2,
  81. };
  82. static struct cnss_plat_data *plat_env;
  83. static bool cnss_allow_driver_loading;
  84. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  85. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  86. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  87. };
  88. static struct cnss_fw_files FW_FILES_DEFAULT = {
  89. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  90. "utfbd.bin", "epping.bin", "evicted.bin"
  91. };
  92. struct cnss_driver_event {
  93. struct list_head list;
  94. enum cnss_driver_event_type type;
  95. bool sync;
  96. struct completion complete;
  97. int ret;
  98. void *data;
  99. };
  100. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  101. struct cnss_plat_data *plat_priv)
  102. {
  103. plat_env = plat_priv;
  104. }
  105. bool cnss_check_driver_loading_allowed(void)
  106. {
  107. return cnss_allow_driver_loading;
  108. }
  109. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  110. {
  111. return plat_env;
  112. }
  113. /**
  114. * cnss_get_mem_seg_count - Get segment count of memory
  115. * @type: memory type
  116. * @seg: segment count
  117. *
  118. * Return: 0 on success, negative value on failure
  119. */
  120. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  121. {
  122. struct cnss_plat_data *plat_priv;
  123. plat_priv = cnss_get_plat_priv(NULL);
  124. if (!plat_priv)
  125. return -ENODEV;
  126. switch (type) {
  127. case CNSS_REMOTE_MEM_TYPE_FW:
  128. *seg = plat_priv->fw_mem_seg_len;
  129. break;
  130. case CNSS_REMOTE_MEM_TYPE_QDSS:
  131. *seg = plat_priv->qdss_mem_seg_len;
  132. break;
  133. default:
  134. return -EINVAL;
  135. }
  136. return 0;
  137. }
  138. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  139. /**
  140. * cnss_get_wifi_kobject -return wifi kobject
  141. * Return: Null, to maintain driver comnpatibilty
  142. */
  143. struct kobject *cnss_get_wifi_kobj(struct device *dev)
  144. {
  145. struct cnss_plat_data *plat_priv;
  146. plat_priv = cnss_get_plat_priv(NULL);
  147. if (!plat_priv)
  148. return NULL;
  149. return plat_priv->wifi_kobj;
  150. }
  151. EXPORT_SYMBOL(cnss_get_wifi_kobj);
  152. /**
  153. * cnss_get_mem_segment_info - Get memory info of different type
  154. * @type: memory type
  155. * @segment: array to save the segment info
  156. * @seg: segment count
  157. *
  158. * Return: 0 on success, negative value on failure
  159. */
  160. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  161. struct cnss_mem_segment segment[],
  162. u32 segment_count)
  163. {
  164. struct cnss_plat_data *plat_priv;
  165. u32 i;
  166. plat_priv = cnss_get_plat_priv(NULL);
  167. if (!plat_priv)
  168. return -ENODEV;
  169. switch (type) {
  170. case CNSS_REMOTE_MEM_TYPE_FW:
  171. if (segment_count > plat_priv->fw_mem_seg_len)
  172. segment_count = plat_priv->fw_mem_seg_len;
  173. for (i = 0; i < segment_count; i++) {
  174. segment[i].size = plat_priv->fw_mem[i].size;
  175. segment[i].va = plat_priv->fw_mem[i].va;
  176. segment[i].pa = plat_priv->fw_mem[i].pa;
  177. }
  178. break;
  179. case CNSS_REMOTE_MEM_TYPE_QDSS:
  180. if (segment_count > plat_priv->qdss_mem_seg_len)
  181. segment_count = plat_priv->qdss_mem_seg_len;
  182. for (i = 0; i < segment_count; i++) {
  183. segment[i].size = plat_priv->qdss_mem[i].size;
  184. segment[i].va = plat_priv->qdss_mem[i].va;
  185. segment[i].pa = plat_priv->qdss_mem[i].pa;
  186. }
  187. break;
  188. default:
  189. return -EINVAL;
  190. }
  191. return 0;
  192. }
  193. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  194. static int cnss_get_audio_iommu_domain(struct cnss_plat_data *plat_priv)
  195. {
  196. struct device_node *audio_ion_node;
  197. struct platform_device *audio_ion_pdev;
  198. audio_ion_node = of_find_compatible_node(NULL, NULL,
  199. "qcom,msm-audio-ion");
  200. if (!audio_ion_node) {
  201. cnss_pr_err("Unable to get Audio ion node");
  202. return -EINVAL;
  203. }
  204. audio_ion_pdev = of_find_device_by_node(audio_ion_node);
  205. of_node_put(audio_ion_node);
  206. if (!audio_ion_pdev) {
  207. cnss_pr_err("Unable to get Audio ion platform device");
  208. return -EINVAL;
  209. }
  210. plat_priv->audio_iommu_domain =
  211. iommu_get_domain_for_dev(&audio_ion_pdev->dev);
  212. put_device(&audio_ion_pdev->dev);
  213. if (!plat_priv->audio_iommu_domain) {
  214. cnss_pr_err("Unable to get Audio ion iommu domain");
  215. return -EINVAL;
  216. }
  217. return 0;
  218. }
  219. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  220. enum cnss_feature_v01 feature)
  221. {
  222. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  223. return -EINVAL;
  224. plat_priv->feature_list |= 1 << feature;
  225. return 0;
  226. }
  227. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  228. enum cnss_feature_v01 feature)
  229. {
  230. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  231. return -EINVAL;
  232. plat_priv->feature_list &= ~(1 << feature);
  233. return 0;
  234. }
  235. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  236. u64 *feature_list)
  237. {
  238. if (unlikely(!plat_priv))
  239. return -EINVAL;
  240. *feature_list = plat_priv->feature_list;
  241. return 0;
  242. }
  243. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  244. {
  245. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  246. return;
  247. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  248. plat_priv->driver_state,
  249. atomic_read(&plat_priv->pm_count));
  250. pm_stay_awake(&plat_priv->plat_dev->dev);
  251. }
  252. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  253. {
  254. int r = atomic_dec_return(&plat_priv->pm_count);
  255. WARN_ON(r < 0);
  256. if (r != 0)
  257. return;
  258. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  259. plat_priv->driver_state,
  260. atomic_read(&plat_priv->pm_count));
  261. pm_relax(&plat_priv->plat_dev->dev);
  262. }
  263. int cnss_get_fw_files_for_target(struct device *dev,
  264. struct cnss_fw_files *pfw_files,
  265. u32 target_type, u32 target_version)
  266. {
  267. if (!pfw_files)
  268. return -ENODEV;
  269. switch (target_version) {
  270. case QCA6174_REV3_VERSION:
  271. case QCA6174_REV3_2_VERSION:
  272. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  273. break;
  274. default:
  275. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  276. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  277. target_type, target_version);
  278. break;
  279. }
  280. return 0;
  281. }
  282. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  283. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  284. {
  285. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  286. if (!plat_priv)
  287. return -ENODEV;
  288. if (!cap)
  289. return -EINVAL;
  290. *cap = plat_priv->cap;
  291. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  292. return 0;
  293. }
  294. EXPORT_SYMBOL(cnss_get_platform_cap);
  295. /**
  296. * cnss_get_fw_cap - Check whether FW supports specific capability or not
  297. * @dev: Device
  298. * @fw_cap: FW Capability which needs to be checked
  299. *
  300. * Return: TRUE if supported, FALSE on failure or if not supported
  301. */
  302. bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap)
  303. {
  304. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  305. bool is_supported = false;
  306. if (!plat_priv)
  307. return is_supported;
  308. if (!plat_priv->fw_caps)
  309. return is_supported;
  310. switch (fw_cap) {
  311. case CNSS_FW_CAP_DIRECT_LINK_SUPPORT:
  312. is_supported = !!(plat_priv->fw_caps &
  313. QMI_WLFW_DIRECT_LINK_SUPPORT_V01);
  314. if (is_supported && cnss_get_audio_iommu_domain(plat_priv))
  315. is_supported = false;
  316. break;
  317. default:
  318. cnss_pr_err("Invalid FW Capability: 0x%x\n", fw_cap);
  319. }
  320. cnss_pr_dbg("FW Capability 0x%x is %s\n", fw_cap,
  321. is_supported ? "supported" : "not supported");
  322. return is_supported;
  323. }
  324. EXPORT_SYMBOL(cnss_get_fw_cap);
  325. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  326. {
  327. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  328. if (!plat_priv)
  329. return;
  330. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  331. }
  332. EXPORT_SYMBOL(cnss_request_pm_qos);
  333. void cnss_remove_pm_qos(struct device *dev)
  334. {
  335. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  336. if (!plat_priv)
  337. return;
  338. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  339. }
  340. EXPORT_SYMBOL(cnss_remove_pm_qos);
  341. int cnss_wlan_enable(struct device *dev,
  342. struct cnss_wlan_enable_cfg *config,
  343. enum cnss_driver_mode mode,
  344. const char *host_version)
  345. {
  346. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  347. int ret = 0;
  348. if (!plat_priv)
  349. return -ENODEV;
  350. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  351. return 0;
  352. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  353. return 0;
  354. if (!config || !host_version) {
  355. cnss_pr_err("Invalid config or host_version pointer\n");
  356. return -EINVAL;
  357. }
  358. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  359. mode, config, host_version);
  360. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  361. goto skip_cfg;
  362. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  363. if (ret)
  364. goto out;
  365. skip_cfg:
  366. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  367. out:
  368. return ret;
  369. }
  370. EXPORT_SYMBOL(cnss_wlan_enable);
  371. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  372. {
  373. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  374. int ret = 0;
  375. if (!plat_priv)
  376. return -ENODEV;
  377. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  378. return 0;
  379. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  380. return 0;
  381. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  382. cnss_bus_free_qdss_mem(plat_priv);
  383. return ret;
  384. }
  385. EXPORT_SYMBOL(cnss_wlan_disable);
  386. int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
  387. dma_addr_t iova, size_t size)
  388. {
  389. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  390. uint32_t page_offset;
  391. if (!plat_priv)
  392. return -ENODEV;
  393. if (!plat_priv->audio_iommu_domain)
  394. return -EINVAL;
  395. page_offset = iova & (PAGE_SIZE - 1);
  396. if (page_offset + size > PAGE_SIZE)
  397. size += PAGE_SIZE;
  398. iova -= page_offset;
  399. paddr -= page_offset;
  400. return iommu_map(plat_priv->audio_iommu_domain, iova, paddr,
  401. roundup(size, PAGE_SIZE), IOMMU_READ | IOMMU_WRITE);
  402. }
  403. EXPORT_SYMBOL(cnss_audio_smmu_map);
  404. void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
  405. {
  406. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  407. uint32_t page_offset;
  408. if (!plat_priv)
  409. return;
  410. if (!plat_priv->audio_iommu_domain)
  411. return;
  412. page_offset = iova & (PAGE_SIZE - 1);
  413. if (page_offset + size > PAGE_SIZE)
  414. size += PAGE_SIZE;
  415. iova -= page_offset;
  416. iommu_unmap(plat_priv->audio_iommu_domain, iova,
  417. roundup(size, PAGE_SIZE));
  418. }
  419. EXPORT_SYMBOL(cnss_audio_smmu_unmap);
  420. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  421. u32 data_len, u8 *output)
  422. {
  423. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  424. int ret = 0;
  425. if (!plat_priv) {
  426. cnss_pr_err("plat_priv is NULL!\n");
  427. return -EINVAL;
  428. }
  429. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  430. return 0;
  431. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  432. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  433. plat_priv->driver_state);
  434. ret = -EINVAL;
  435. goto out;
  436. }
  437. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  438. data_len, output);
  439. out:
  440. return ret;
  441. }
  442. EXPORT_SYMBOL(cnss_athdiag_read);
  443. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  444. u32 data_len, u8 *input)
  445. {
  446. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  447. int ret = 0;
  448. if (!plat_priv) {
  449. cnss_pr_err("plat_priv is NULL!\n");
  450. return -EINVAL;
  451. }
  452. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  453. return 0;
  454. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  455. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  456. plat_priv->driver_state);
  457. ret = -EINVAL;
  458. goto out;
  459. }
  460. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  461. data_len, input);
  462. out:
  463. return ret;
  464. }
  465. EXPORT_SYMBOL(cnss_athdiag_write);
  466. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  467. {
  468. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  469. if (!plat_priv)
  470. return -ENODEV;
  471. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  472. return 0;
  473. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  474. }
  475. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  476. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  477. {
  478. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  479. if (!plat_priv)
  480. return -EINVAL;
  481. if (!plat_priv->fw_pcie_gen_switch) {
  482. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  483. return -EOPNOTSUPP;
  484. }
  485. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  486. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  487. return -EINVAL;
  488. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  489. plat_priv->pcie_gen_speed = pcie_gen_speed;
  490. return 0;
  491. }
  492. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  493. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  494. {
  495. int ret = 0;
  496. if (!plat_priv)
  497. return -ENODEV;
  498. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  499. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  500. if (ret)
  501. goto out;
  502. if (plat_priv->hds_enabled)
  503. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  504. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  505. cnss_wlfw_ini_file_send_sync(plat_priv, WLFW_CONN_ROAM_INI_V01);
  506. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  507. plat_priv->ctrl_params.bdf_type);
  508. if (ret)
  509. goto out;
  510. ret = cnss_bus_load_m3(plat_priv);
  511. if (ret)
  512. goto out;
  513. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  514. if (ret)
  515. goto out;
  516. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  517. return 0;
  518. out:
  519. return ret;
  520. }
  521. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  522. {
  523. int ret = 0;
  524. if (!plat_priv->antenna) {
  525. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  526. if (ret)
  527. goto out;
  528. }
  529. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  530. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  531. if (ret)
  532. goto out;
  533. }
  534. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  535. if (ret)
  536. goto out;
  537. return 0;
  538. out:
  539. return ret;
  540. }
  541. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  542. {
  543. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  544. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  545. }
  546. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  547. {
  548. u32 i;
  549. int ret = 0;
  550. struct cnss_plat_ipc_daemon_config *cfg;
  551. ret = cnss_qmi_get_dms_mac(plat_priv);
  552. if (ret == 0 && plat_priv->dms.mac_valid)
  553. goto qmi_send;
  554. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  555. * Thus assert on failure to get MAC from DMS even after retries
  556. */
  557. if (plat_priv->use_nv_mac) {
  558. /* Check if Daemon says platform support DMS MAC provisioning */
  559. cfg = cnss_plat_ipc_qmi_daemon_config();
  560. if (cfg) {
  561. if (!cfg->dms_mac_addr_supported) {
  562. cnss_pr_err("DMS MAC address not supported\n");
  563. CNSS_ASSERT(0);
  564. return -EINVAL;
  565. }
  566. }
  567. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  568. if (plat_priv->dms.mac_valid)
  569. break;
  570. ret = cnss_qmi_get_dms_mac(plat_priv);
  571. if (ret == 0)
  572. break;
  573. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  574. }
  575. if (!plat_priv->dms.mac_valid) {
  576. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  577. CNSS_ASSERT(0);
  578. return -EINVAL;
  579. }
  580. }
  581. qmi_send:
  582. if (plat_priv->dms.mac_valid)
  583. ret =
  584. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  585. ARRAY_SIZE(plat_priv->dms.mac));
  586. return ret;
  587. }
  588. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  589. enum cnss_cal_db_op op, u32 *size)
  590. {
  591. int ret = 0;
  592. u32 timeout = cnss_get_timeout(plat_priv,
  593. CNSS_TIMEOUT_DAEMON_CONNECTION);
  594. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  595. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  596. if (op >= CNSS_CAL_DB_INVALID_OP)
  597. return -EINVAL;
  598. if (!plat_priv->cbc_file_download) {
  599. cnss_pr_info("CAL DB file not required as per BDF\n");
  600. return 0;
  601. }
  602. if (*size == 0) {
  603. cnss_pr_err("Invalid cal file size\n");
  604. return -EINVAL;
  605. }
  606. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  607. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  608. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  609. msecs_to_jiffies(timeout));
  610. if (!ret) {
  611. cnss_pr_err("Daemon not yet connected\n");
  612. CNSS_ASSERT(0);
  613. return ret;
  614. }
  615. }
  616. if (!plat_priv->cal_mem->va) {
  617. cnss_pr_err("CAL DB Memory not setup for FW\n");
  618. return -EINVAL;
  619. }
  620. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  621. if (op == CNSS_CAL_DB_DOWNLOAD) {
  622. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  623. ret = cnss_plat_ipc_qmi_file_download(client_id,
  624. CNSS_CAL_DB_FILE_NAME,
  625. plat_priv->cal_mem->va,
  626. size);
  627. } else {
  628. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  629. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  630. CNSS_CAL_DB_FILE_NAME,
  631. plat_priv->cal_mem->va,
  632. *size);
  633. }
  634. if (ret)
  635. cnss_pr_err("Cal DB file %s %s failure\n",
  636. CNSS_CAL_DB_FILE_NAME,
  637. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  638. else
  639. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  640. CNSS_CAL_DB_FILE_NAME,
  641. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  642. *size);
  643. return ret;
  644. }
  645. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  646. {
  647. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  648. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  649. return -EINVAL;
  650. }
  651. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  652. &plat_priv->cal_file_size);
  653. }
  654. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  655. u32 *cal_file_size)
  656. {
  657. /* To download pass the total size of cal DB mem allocated.
  658. * After cal file is download to mem, its size is updated in
  659. * return pointer
  660. */
  661. *cal_file_size = plat_priv->cal_mem->size;
  662. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  663. cal_file_size);
  664. }
  665. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  666. {
  667. int ret = 0;
  668. u32 cal_file_size = 0;
  669. if (!plat_priv)
  670. return -ENODEV;
  671. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  672. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  673. return -EINVAL;
  674. }
  675. cnss_pr_dbg("Processing FW Init Done..\n");
  676. del_timer(&plat_priv->fw_boot_timer);
  677. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  678. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  679. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  680. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  681. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  682. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  683. }
  684. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  685. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  686. CNSS_WALTEST);
  687. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  688. cnss_request_antenna_sharing(plat_priv);
  689. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  690. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  691. plat_priv->cal_time = jiffies;
  692. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  693. CNSS_CALIBRATION);
  694. } else {
  695. ret = cnss_setup_dms_mac(plat_priv);
  696. ret = cnss_bus_call_driver_probe(plat_priv);
  697. }
  698. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  699. goto out;
  700. else if (ret)
  701. goto shutdown;
  702. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  703. return 0;
  704. shutdown:
  705. cnss_bus_dev_shutdown(plat_priv);
  706. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  707. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  708. out:
  709. return ret;
  710. }
  711. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  712. {
  713. switch (type) {
  714. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  715. return "SERVER_ARRIVE";
  716. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  717. return "SERVER_EXIT";
  718. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  719. return "REQUEST_MEM";
  720. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  721. return "FW_MEM_READY";
  722. case CNSS_DRIVER_EVENT_FW_READY:
  723. return "FW_READY";
  724. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  725. return "COLD_BOOT_CAL_START";
  726. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  727. return "COLD_BOOT_CAL_DONE";
  728. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  729. return "REGISTER_DRIVER";
  730. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  731. return "UNREGISTER_DRIVER";
  732. case CNSS_DRIVER_EVENT_RECOVERY:
  733. return "RECOVERY";
  734. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  735. return "FORCE_FW_ASSERT";
  736. case CNSS_DRIVER_EVENT_POWER_UP:
  737. return "POWER_UP";
  738. case CNSS_DRIVER_EVENT_POWER_DOWN:
  739. return "POWER_DOWN";
  740. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  741. return "IDLE_RESTART";
  742. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  743. return "IDLE_SHUTDOWN";
  744. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  745. return "IMS_WFC_CALL_IND";
  746. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  747. return "WLFW_TWC_CFG_IND";
  748. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  749. return "QDSS_TRACE_REQ_MEM";
  750. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  751. return "FW_MEM_FILE_SAVE";
  752. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  753. return "QDSS_TRACE_FREE";
  754. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  755. return "QDSS_TRACE_REQ_DATA";
  756. case CNSS_DRIVER_EVENT_MAX:
  757. return "EVENT_MAX";
  758. }
  759. return "UNKNOWN";
  760. };
  761. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  762. enum cnss_driver_event_type type,
  763. u32 flags, void *data)
  764. {
  765. struct cnss_driver_event *event;
  766. unsigned long irq_flags;
  767. int gfp = GFP_KERNEL;
  768. int ret = 0;
  769. if (!plat_priv)
  770. return -ENODEV;
  771. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  772. cnss_driver_event_to_str(type), type,
  773. flags ? "-sync" : "", plat_priv->driver_state, flags);
  774. if (type >= CNSS_DRIVER_EVENT_MAX) {
  775. cnss_pr_err("Invalid Event type: %d, can't post", type);
  776. return -EINVAL;
  777. }
  778. if (in_interrupt() || irqs_disabled())
  779. gfp = GFP_ATOMIC;
  780. event = kzalloc(sizeof(*event), gfp);
  781. if (!event)
  782. return -ENOMEM;
  783. cnss_pm_stay_awake(plat_priv);
  784. event->type = type;
  785. event->data = data;
  786. init_completion(&event->complete);
  787. event->ret = CNSS_EVENT_PENDING;
  788. event->sync = !!(flags & CNSS_EVENT_SYNC);
  789. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  790. list_add_tail(&event->list, &plat_priv->event_list);
  791. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  792. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  793. if (!(flags & CNSS_EVENT_SYNC))
  794. goto out;
  795. if (flags & CNSS_EVENT_UNKILLABLE)
  796. wait_for_completion(&event->complete);
  797. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  798. ret = wait_for_completion_killable(&event->complete);
  799. else
  800. ret = wait_for_completion_interruptible(&event->complete);
  801. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  802. cnss_driver_event_to_str(type), type,
  803. plat_priv->driver_state, ret, event->ret);
  804. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  805. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  806. event->sync = false;
  807. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  808. ret = -EINTR;
  809. goto out;
  810. }
  811. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  812. ret = event->ret;
  813. kfree(event);
  814. out:
  815. cnss_pm_relax(plat_priv);
  816. return ret;
  817. }
  818. /**
  819. * cnss_get_timeout - Get timeout for corresponding type.
  820. * @plat_priv: Pointer to platform driver context.
  821. * @cnss_timeout_type: Timeout type.
  822. *
  823. * Return: Timeout in milliseconds.
  824. */
  825. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  826. enum cnss_timeout_type timeout_type)
  827. {
  828. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  829. switch (timeout_type) {
  830. case CNSS_TIMEOUT_QMI:
  831. return qmi_timeout;
  832. case CNSS_TIMEOUT_POWER_UP:
  833. return (qmi_timeout << 2);
  834. case CNSS_TIMEOUT_IDLE_RESTART:
  835. /* In idle restart power up sequence, we have fw_boot_timer to
  836. * handle FW initialization failure.
  837. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  838. * account for FW dump collection and FW re-initialization on
  839. * retry.
  840. */
  841. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  842. case CNSS_TIMEOUT_CALIBRATION:
  843. /* Similar to mission mode, in CBC if FW init fails
  844. * fw recovery is tried. Thus return 2x the CBC timeout.
  845. */
  846. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  847. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  848. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  849. case CNSS_TIMEOUT_RDDM:
  850. return CNSS_RDDM_TIMEOUT_MS;
  851. case CNSS_TIMEOUT_RECOVERY:
  852. return RECOVERY_TIMEOUT;
  853. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  854. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  855. default:
  856. return qmi_timeout;
  857. }
  858. }
  859. unsigned int cnss_get_boot_timeout(struct device *dev)
  860. {
  861. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  862. if (!plat_priv) {
  863. cnss_pr_err("plat_priv is NULL\n");
  864. return 0;
  865. }
  866. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  867. }
  868. EXPORT_SYMBOL(cnss_get_boot_timeout);
  869. int cnss_power_up(struct device *dev)
  870. {
  871. int ret = 0;
  872. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  873. unsigned int timeout;
  874. if (!plat_priv) {
  875. cnss_pr_err("plat_priv is NULL\n");
  876. return -ENODEV;
  877. }
  878. cnss_pr_dbg("Powering up device\n");
  879. ret = cnss_driver_event_post(plat_priv,
  880. CNSS_DRIVER_EVENT_POWER_UP,
  881. CNSS_EVENT_SYNC, NULL);
  882. if (ret)
  883. goto out;
  884. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  885. goto out;
  886. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  887. reinit_completion(&plat_priv->power_up_complete);
  888. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  889. msecs_to_jiffies(timeout));
  890. if (!ret) {
  891. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  892. timeout);
  893. ret = -EAGAIN;
  894. goto out;
  895. }
  896. return 0;
  897. out:
  898. return ret;
  899. }
  900. EXPORT_SYMBOL(cnss_power_up);
  901. int cnss_power_down(struct device *dev)
  902. {
  903. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  904. if (!plat_priv) {
  905. cnss_pr_err("plat_priv is NULL\n");
  906. return -ENODEV;
  907. }
  908. cnss_pr_dbg("Powering down device\n");
  909. return cnss_driver_event_post(plat_priv,
  910. CNSS_DRIVER_EVENT_POWER_DOWN,
  911. CNSS_EVENT_SYNC, NULL);
  912. }
  913. EXPORT_SYMBOL(cnss_power_down);
  914. int cnss_idle_restart(struct device *dev)
  915. {
  916. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  917. unsigned int timeout;
  918. int ret = 0;
  919. if (!plat_priv) {
  920. cnss_pr_err("plat_priv is NULL\n");
  921. return -ENODEV;
  922. }
  923. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  924. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  925. return -EBUSY;
  926. }
  927. cnss_pr_dbg("Doing idle restart\n");
  928. reinit_completion(&plat_priv->power_up_complete);
  929. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  930. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  931. ret = -EINVAL;
  932. goto out;
  933. }
  934. ret = cnss_driver_event_post(plat_priv,
  935. CNSS_DRIVER_EVENT_IDLE_RESTART,
  936. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  937. if (ret)
  938. goto out;
  939. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  940. ret = cnss_bus_call_driver_probe(plat_priv);
  941. goto out;
  942. }
  943. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  944. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  945. msecs_to_jiffies(timeout));
  946. if (plat_priv->power_up_error) {
  947. ret = plat_priv->power_up_error;
  948. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  949. cnss_pr_dbg("Power up error:%d, exiting\n",
  950. plat_priv->power_up_error);
  951. goto out;
  952. }
  953. if (!ret) {
  954. /* This exception occurs after attempting retry of FW recovery.
  955. * Thus we can safely power off the device.
  956. */
  957. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  958. timeout);
  959. ret = -ETIMEDOUT;
  960. cnss_power_down(dev);
  961. CNSS_ASSERT(0);
  962. goto out;
  963. }
  964. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  965. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  966. del_timer(&plat_priv->fw_boot_timer);
  967. ret = -EINVAL;
  968. goto out;
  969. }
  970. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  971. * non-DRV is supported only once after device reboots and before wifi
  972. * is turned on. We do not allow switching back to DRV.
  973. * To bring device back into DRV, user needs to reboot device.
  974. */
  975. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  976. cnss_pr_dbg("DRV is disabled\n");
  977. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  978. }
  979. mutex_unlock(&plat_priv->driver_ops_lock);
  980. return 0;
  981. out:
  982. mutex_unlock(&plat_priv->driver_ops_lock);
  983. return ret;
  984. }
  985. EXPORT_SYMBOL(cnss_idle_restart);
  986. int cnss_idle_shutdown(struct device *dev)
  987. {
  988. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  989. unsigned int timeout;
  990. int ret;
  991. if (!plat_priv) {
  992. cnss_pr_err("plat_priv is NULL\n");
  993. return -ENODEV;
  994. }
  995. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  996. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  997. return -EAGAIN;
  998. }
  999. cnss_pr_dbg("Doing idle shutdown\n");
  1000. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  1001. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1002. goto skip_wait;
  1003. reinit_completion(&plat_priv->recovery_complete);
  1004. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  1005. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  1006. msecs_to_jiffies(timeout));
  1007. if (!ret) {
  1008. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  1009. timeout);
  1010. CNSS_ASSERT(0);
  1011. }
  1012. skip_wait:
  1013. return cnss_driver_event_post(plat_priv,
  1014. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  1015. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1016. }
  1017. EXPORT_SYMBOL(cnss_idle_shutdown);
  1018. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  1019. {
  1020. int ret = 0;
  1021. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1022. if (ret) {
  1023. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  1024. goto out;
  1025. }
  1026. ret = cnss_get_clk(plat_priv);
  1027. if (ret) {
  1028. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  1029. goto put_vreg;
  1030. }
  1031. ret = cnss_get_pinctrl(plat_priv);
  1032. if (ret) {
  1033. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  1034. goto put_clk;
  1035. }
  1036. return 0;
  1037. put_clk:
  1038. cnss_put_clk(plat_priv);
  1039. put_vreg:
  1040. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1041. out:
  1042. return ret;
  1043. }
  1044. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  1045. {
  1046. cnss_put_clk(plat_priv);
  1047. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1048. }
  1049. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1050. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  1051. unsigned long code,
  1052. void *ss_handle)
  1053. {
  1054. struct cnss_plat_data *plat_priv =
  1055. container_of(nb, struct cnss_plat_data, modem_nb);
  1056. struct cnss_esoc_info *esoc_info;
  1057. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  1058. if (!plat_priv)
  1059. return NOTIFY_DONE;
  1060. esoc_info = &plat_priv->esoc_info;
  1061. if (code == SUBSYS_AFTER_POWERUP)
  1062. esoc_info->modem_current_status = 1;
  1063. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  1064. esoc_info->modem_current_status = 0;
  1065. else
  1066. return NOTIFY_DONE;
  1067. if (!cnss_bus_call_driver_modem_status(plat_priv,
  1068. esoc_info->modem_current_status))
  1069. return NOTIFY_DONE;
  1070. return NOTIFY_OK;
  1071. }
  1072. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1073. {
  1074. int ret = 0;
  1075. struct device *dev;
  1076. struct cnss_esoc_info *esoc_info;
  1077. struct esoc_desc *esoc_desc;
  1078. const char *client_desc;
  1079. dev = &plat_priv->plat_dev->dev;
  1080. esoc_info = &plat_priv->esoc_info;
  1081. esoc_info->notify_modem_status =
  1082. of_property_read_bool(dev->of_node,
  1083. "qcom,notify-modem-status");
  1084. if (!esoc_info->notify_modem_status)
  1085. goto out;
  1086. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1087. &client_desc);
  1088. if (ret) {
  1089. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1090. } else {
  1091. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1092. if (IS_ERR_OR_NULL(esoc_desc)) {
  1093. ret = PTR_RET(esoc_desc);
  1094. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1095. ret);
  1096. goto out;
  1097. }
  1098. esoc_info->esoc_desc = esoc_desc;
  1099. }
  1100. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1101. esoc_info->modem_current_status = 0;
  1102. esoc_info->modem_notify_handler =
  1103. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1104. esoc_info->esoc_desc->name :
  1105. "modem", &plat_priv->modem_nb);
  1106. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1107. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1108. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1109. ret);
  1110. goto unreg_esoc;
  1111. }
  1112. return 0;
  1113. unreg_esoc:
  1114. if (esoc_info->esoc_desc)
  1115. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1116. out:
  1117. return ret;
  1118. }
  1119. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1120. {
  1121. struct device *dev;
  1122. struct cnss_esoc_info *esoc_info;
  1123. dev = &plat_priv->plat_dev->dev;
  1124. esoc_info = &plat_priv->esoc_info;
  1125. if (esoc_info->notify_modem_status)
  1126. subsys_notif_unregister_notifier
  1127. (esoc_info->modem_notify_handler,
  1128. &plat_priv->modem_nb);
  1129. if (esoc_info->esoc_desc)
  1130. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1131. }
  1132. #else
  1133. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1134. {
  1135. return 0;
  1136. }
  1137. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1138. #endif
  1139. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1140. {
  1141. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1142. int ret = 0;
  1143. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1144. return 0;
  1145. enable_irq(sol_gpio->dev_sol_irq);
  1146. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1147. if (ret)
  1148. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1149. ret);
  1150. return ret;
  1151. }
  1152. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1153. {
  1154. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1155. int ret = 0;
  1156. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1157. return 0;
  1158. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1159. if (ret)
  1160. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1161. ret);
  1162. disable_irq(sol_gpio->dev_sol_irq);
  1163. return ret;
  1164. }
  1165. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1166. {
  1167. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1168. if (sol_gpio->dev_sol_gpio < 0)
  1169. return -EINVAL;
  1170. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1171. }
  1172. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1173. {
  1174. struct cnss_plat_data *plat_priv = data;
  1175. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1176. sol_gpio->dev_sol_counter++;
  1177. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1178. irq, sol_gpio->dev_sol_counter);
  1179. /* Make sure abort current suspend */
  1180. cnss_pm_stay_awake(plat_priv);
  1181. cnss_pm_relax(plat_priv);
  1182. pm_system_wakeup();
  1183. cnss_bus_handle_dev_sol_irq(plat_priv);
  1184. return IRQ_HANDLED;
  1185. }
  1186. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1187. {
  1188. struct device *dev = &plat_priv->plat_dev->dev;
  1189. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1190. int ret = 0;
  1191. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1192. "wlan-dev-sol-gpio", 0);
  1193. if (sol_gpio->dev_sol_gpio < 0)
  1194. goto out;
  1195. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1196. sol_gpio->dev_sol_gpio);
  1197. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1198. if (ret) {
  1199. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1200. ret);
  1201. goto out;
  1202. }
  1203. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1204. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1205. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1206. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1207. if (ret) {
  1208. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1209. goto free_gpio;
  1210. }
  1211. return 0;
  1212. free_gpio:
  1213. gpio_free(sol_gpio->dev_sol_gpio);
  1214. out:
  1215. return ret;
  1216. }
  1217. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1218. {
  1219. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1220. if (sol_gpio->dev_sol_gpio < 0)
  1221. return;
  1222. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1223. gpio_free(sol_gpio->dev_sol_gpio);
  1224. }
  1225. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1226. {
  1227. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1228. if (sol_gpio->host_sol_gpio < 0)
  1229. return -EINVAL;
  1230. if (value)
  1231. cnss_pr_dbg("Assert host SOL GPIO\n");
  1232. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1233. return 0;
  1234. }
  1235. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1236. {
  1237. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1238. if (sol_gpio->host_sol_gpio < 0)
  1239. return -EINVAL;
  1240. return gpio_get_value(sol_gpio->host_sol_gpio);
  1241. }
  1242. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1243. {
  1244. struct device *dev = &plat_priv->plat_dev->dev;
  1245. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1246. int ret = 0;
  1247. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1248. "wlan-host-sol-gpio", 0);
  1249. if (sol_gpio->host_sol_gpio < 0)
  1250. goto out;
  1251. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1252. sol_gpio->host_sol_gpio);
  1253. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1254. if (ret) {
  1255. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1256. ret);
  1257. goto out;
  1258. }
  1259. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1260. return 0;
  1261. out:
  1262. return ret;
  1263. }
  1264. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1265. {
  1266. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1267. if (sol_gpio->host_sol_gpio < 0)
  1268. return;
  1269. gpio_free(sol_gpio->host_sol_gpio);
  1270. }
  1271. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1272. {
  1273. int ret;
  1274. ret = cnss_init_dev_sol_gpio(plat_priv);
  1275. if (ret)
  1276. goto out;
  1277. ret = cnss_init_host_sol_gpio(plat_priv);
  1278. if (ret)
  1279. goto deinit_dev_sol;
  1280. return 0;
  1281. deinit_dev_sol:
  1282. cnss_deinit_dev_sol_gpio(plat_priv);
  1283. out:
  1284. return ret;
  1285. }
  1286. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1287. {
  1288. cnss_deinit_host_sol_gpio(plat_priv);
  1289. cnss_deinit_dev_sol_gpio(plat_priv);
  1290. }
  1291. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1292. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1293. {
  1294. struct cnss_plat_data *plat_priv;
  1295. int ret = 0;
  1296. if (!subsys_desc->dev) {
  1297. cnss_pr_err("dev from subsys_desc is NULL\n");
  1298. return -ENODEV;
  1299. }
  1300. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1301. if (!plat_priv) {
  1302. cnss_pr_err("plat_priv is NULL\n");
  1303. return -ENODEV;
  1304. }
  1305. if (!plat_priv->driver_state) {
  1306. cnss_pr_dbg("subsys powerup is ignored\n");
  1307. return 0;
  1308. }
  1309. ret = cnss_bus_dev_powerup(plat_priv);
  1310. if (ret)
  1311. __pm_relax(plat_priv->recovery_ws);
  1312. return ret;
  1313. }
  1314. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1315. bool force_stop)
  1316. {
  1317. struct cnss_plat_data *plat_priv;
  1318. if (!subsys_desc->dev) {
  1319. cnss_pr_err("dev from subsys_desc is NULL\n");
  1320. return -ENODEV;
  1321. }
  1322. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1323. if (!plat_priv) {
  1324. cnss_pr_err("plat_priv is NULL\n");
  1325. return -ENODEV;
  1326. }
  1327. if (!plat_priv->driver_state) {
  1328. cnss_pr_dbg("subsys shutdown is ignored\n");
  1329. return 0;
  1330. }
  1331. return cnss_bus_dev_shutdown(plat_priv);
  1332. }
  1333. void cnss_device_crashed(struct device *dev)
  1334. {
  1335. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1336. struct cnss_subsys_info *subsys_info;
  1337. if (!plat_priv)
  1338. return;
  1339. subsys_info = &plat_priv->subsys_info;
  1340. if (subsys_info->subsys_device) {
  1341. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1342. subsys_set_crash_status(subsys_info->subsys_device, true);
  1343. subsystem_restart_dev(subsys_info->subsys_device);
  1344. }
  1345. }
  1346. EXPORT_SYMBOL(cnss_device_crashed);
  1347. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1348. {
  1349. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1350. if (!plat_priv) {
  1351. cnss_pr_err("plat_priv is NULL\n");
  1352. return;
  1353. }
  1354. cnss_bus_dev_crash_shutdown(plat_priv);
  1355. }
  1356. static int cnss_subsys_ramdump(int enable,
  1357. const struct subsys_desc *subsys_desc)
  1358. {
  1359. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1360. if (!plat_priv) {
  1361. cnss_pr_err("plat_priv is NULL\n");
  1362. return -ENODEV;
  1363. }
  1364. if (!enable)
  1365. return 0;
  1366. return cnss_bus_dev_ramdump(plat_priv);
  1367. }
  1368. static void cnss_recovery_work_handler(struct work_struct *work)
  1369. {
  1370. }
  1371. #else
  1372. static void cnss_recovery_work_handler(struct work_struct *work)
  1373. {
  1374. int ret;
  1375. struct cnss_plat_data *plat_priv =
  1376. container_of(work, struct cnss_plat_data, recovery_work);
  1377. if (!plat_priv->recovery_enabled)
  1378. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1379. cnss_bus_dev_shutdown(plat_priv);
  1380. cnss_bus_dev_ramdump(plat_priv);
  1381. msleep(POWER_RESET_MIN_DELAY_MS);
  1382. ret = cnss_bus_dev_powerup(plat_priv);
  1383. if (ret)
  1384. __pm_relax(plat_priv->recovery_ws);
  1385. return;
  1386. }
  1387. void cnss_device_crashed(struct device *dev)
  1388. {
  1389. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1390. if (!plat_priv)
  1391. return;
  1392. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1393. schedule_work(&plat_priv->recovery_work);
  1394. }
  1395. EXPORT_SYMBOL(cnss_device_crashed);
  1396. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1397. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1398. {
  1399. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1400. struct cnss_ramdump_info *ramdump_info;
  1401. if (!plat_priv)
  1402. return NULL;
  1403. ramdump_info = &plat_priv->ramdump_info;
  1404. *size = ramdump_info->ramdump_size;
  1405. return ramdump_info->ramdump_va;
  1406. }
  1407. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1408. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1409. {
  1410. switch (reason) {
  1411. case CNSS_REASON_DEFAULT:
  1412. return "DEFAULT";
  1413. case CNSS_REASON_LINK_DOWN:
  1414. return "LINK_DOWN";
  1415. case CNSS_REASON_RDDM:
  1416. return "RDDM";
  1417. case CNSS_REASON_TIMEOUT:
  1418. return "TIMEOUT";
  1419. }
  1420. return "UNKNOWN";
  1421. };
  1422. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1423. enum cnss_recovery_reason reason)
  1424. {
  1425. plat_priv->recovery_count++;
  1426. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1427. goto self_recovery;
  1428. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1429. cnss_pr_dbg("Skip device recovery\n");
  1430. return 0;
  1431. }
  1432. /* FW recovery sequence has multiple steps and firmware load requires
  1433. * linux PM in awake state. Thus hold the cnss wake source until
  1434. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1435. * time taken in this process.
  1436. */
  1437. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1438. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1439. true);
  1440. switch (reason) {
  1441. case CNSS_REASON_LINK_DOWN:
  1442. if (!cnss_bus_check_link_status(plat_priv)) {
  1443. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1444. return 0;
  1445. }
  1446. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1447. &plat_priv->ctrl_params.quirks))
  1448. goto self_recovery;
  1449. if (!cnss_bus_recover_link_down(plat_priv)) {
  1450. /* clear recovery bit here to avoid skipping
  1451. * the recovery work for RDDM later
  1452. */
  1453. clear_bit(CNSS_DRIVER_RECOVERY,
  1454. &plat_priv->driver_state);
  1455. return 0;
  1456. }
  1457. break;
  1458. case CNSS_REASON_RDDM:
  1459. cnss_bus_collect_dump_info(plat_priv, false);
  1460. break;
  1461. case CNSS_REASON_DEFAULT:
  1462. case CNSS_REASON_TIMEOUT:
  1463. break;
  1464. default:
  1465. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1466. cnss_recovery_reason_to_str(reason), reason);
  1467. break;
  1468. }
  1469. cnss_bus_device_crashed(plat_priv);
  1470. return 0;
  1471. self_recovery:
  1472. cnss_pr_dbg("Going for self recovery\n");
  1473. cnss_bus_dev_shutdown(plat_priv);
  1474. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1475. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1476. &plat_priv->ctrl_params.quirks);
  1477. cnss_bus_dev_powerup(plat_priv);
  1478. return 0;
  1479. }
  1480. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1481. void *data)
  1482. {
  1483. struct cnss_recovery_data *recovery_data = data;
  1484. int ret = 0;
  1485. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1486. cnss_recovery_reason_to_str(recovery_data->reason),
  1487. recovery_data->reason);
  1488. if (!plat_priv->driver_state) {
  1489. cnss_pr_err("Improper driver state, ignore recovery\n");
  1490. ret = -EINVAL;
  1491. goto out;
  1492. }
  1493. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1494. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1495. ret = -EINVAL;
  1496. goto out;
  1497. }
  1498. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1499. cnss_pr_err("Recovery is already in progress\n");
  1500. CNSS_ASSERT(0);
  1501. ret = -EINVAL;
  1502. goto out;
  1503. }
  1504. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1505. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1506. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1507. ret = -EINVAL;
  1508. goto out;
  1509. }
  1510. switch (plat_priv->device_id) {
  1511. case QCA6174_DEVICE_ID:
  1512. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1513. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1514. &plat_priv->driver_state)) {
  1515. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1516. ret = -EINVAL;
  1517. goto out;
  1518. }
  1519. break;
  1520. default:
  1521. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1522. set_bit(CNSS_FW_BOOT_RECOVERY,
  1523. &plat_priv->driver_state);
  1524. }
  1525. break;
  1526. }
  1527. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1528. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1529. out:
  1530. kfree(data);
  1531. return ret;
  1532. }
  1533. int cnss_self_recovery(struct device *dev,
  1534. enum cnss_recovery_reason reason)
  1535. {
  1536. cnss_schedule_recovery(dev, reason);
  1537. return 0;
  1538. }
  1539. EXPORT_SYMBOL(cnss_self_recovery);
  1540. void cnss_schedule_recovery(struct device *dev,
  1541. enum cnss_recovery_reason reason)
  1542. {
  1543. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1544. struct cnss_recovery_data *data;
  1545. int gfp = GFP_KERNEL;
  1546. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1547. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1548. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1549. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1550. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1551. return;
  1552. }
  1553. if (in_interrupt() || irqs_disabled())
  1554. gfp = GFP_ATOMIC;
  1555. data = kzalloc(sizeof(*data), gfp);
  1556. if (!data)
  1557. return;
  1558. data->reason = reason;
  1559. cnss_driver_event_post(plat_priv,
  1560. CNSS_DRIVER_EVENT_RECOVERY,
  1561. 0, data);
  1562. }
  1563. EXPORT_SYMBOL(cnss_schedule_recovery);
  1564. int cnss_force_fw_assert(struct device *dev)
  1565. {
  1566. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1567. if (!plat_priv) {
  1568. cnss_pr_err("plat_priv is NULL\n");
  1569. return -ENODEV;
  1570. }
  1571. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1572. cnss_pr_info("Forced FW assert is not supported\n");
  1573. return -EOPNOTSUPP;
  1574. }
  1575. if (cnss_bus_is_device_down(plat_priv)) {
  1576. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1577. return 0;
  1578. }
  1579. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1580. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1581. return 0;
  1582. }
  1583. if (in_interrupt() || irqs_disabled())
  1584. cnss_driver_event_post(plat_priv,
  1585. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1586. 0, NULL);
  1587. else
  1588. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1589. return 0;
  1590. }
  1591. EXPORT_SYMBOL(cnss_force_fw_assert);
  1592. int cnss_force_collect_rddm(struct device *dev)
  1593. {
  1594. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1595. unsigned int timeout;
  1596. int ret = 0;
  1597. if (!plat_priv) {
  1598. cnss_pr_err("plat_priv is NULL\n");
  1599. return -ENODEV;
  1600. }
  1601. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1602. cnss_pr_info("Force collect rddm is not supported\n");
  1603. return -EOPNOTSUPP;
  1604. }
  1605. if (cnss_bus_is_device_down(plat_priv)) {
  1606. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1607. goto wait_rddm;
  1608. }
  1609. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1610. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1611. goto wait_rddm;
  1612. }
  1613. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1614. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1615. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1616. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1617. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1618. return 0;
  1619. }
  1620. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1621. if (ret)
  1622. return ret;
  1623. wait_rddm:
  1624. reinit_completion(&plat_priv->rddm_complete);
  1625. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1626. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1627. msecs_to_jiffies(timeout));
  1628. if (!ret) {
  1629. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1630. timeout);
  1631. ret = -ETIMEDOUT;
  1632. } else if (ret > 0) {
  1633. ret = 0;
  1634. }
  1635. return ret;
  1636. }
  1637. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1638. int cnss_qmi_send_get(struct device *dev)
  1639. {
  1640. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1641. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1642. return 0;
  1643. return cnss_bus_qmi_send_get(plat_priv);
  1644. }
  1645. EXPORT_SYMBOL(cnss_qmi_send_get);
  1646. int cnss_qmi_send_put(struct device *dev)
  1647. {
  1648. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1649. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1650. return 0;
  1651. return cnss_bus_qmi_send_put(plat_priv);
  1652. }
  1653. EXPORT_SYMBOL(cnss_qmi_send_put);
  1654. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1655. int cmd_len, void *cb_ctx,
  1656. int (*cb)(void *ctx, void *event, int event_len))
  1657. {
  1658. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1659. int ret;
  1660. if (!plat_priv)
  1661. return -ENODEV;
  1662. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1663. return -EINVAL;
  1664. plat_priv->get_info_cb = cb;
  1665. plat_priv->get_info_cb_ctx = cb_ctx;
  1666. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1667. if (ret) {
  1668. plat_priv->get_info_cb = NULL;
  1669. plat_priv->get_info_cb_ctx = NULL;
  1670. }
  1671. return ret;
  1672. }
  1673. EXPORT_SYMBOL(cnss_qmi_send);
  1674. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1675. {
  1676. int ret = 0;
  1677. u32 retry = 0, timeout;
  1678. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1679. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1680. goto out;
  1681. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1682. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1683. goto out;
  1684. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  1685. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  1686. goto out;
  1687. }
  1688. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1689. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1690. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1691. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1692. CNSS_ASSERT(0);
  1693. return -EINVAL;
  1694. }
  1695. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1696. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1697. break;
  1698. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1699. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1700. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1701. CNSS_ASSERT(0);
  1702. ret = -EINVAL;
  1703. goto mark_cal_fail;
  1704. }
  1705. }
  1706. switch (plat_priv->device_id) {
  1707. case QCA6290_DEVICE_ID:
  1708. case QCA6390_DEVICE_ID:
  1709. case QCA6490_DEVICE_ID:
  1710. case KIWI_DEVICE_ID:
  1711. case MANGO_DEVICE_ID:
  1712. break;
  1713. default:
  1714. cnss_pr_err("Not supported for device ID 0x%lx\n",
  1715. plat_priv->device_id);
  1716. ret = -EINVAL;
  1717. goto mark_cal_fail;
  1718. }
  1719. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1720. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1721. timeout = cnss_get_timeout(plat_priv,
  1722. CNSS_TIMEOUT_CALIBRATION);
  1723. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1724. timeout / 1000);
  1725. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1726. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1727. msecs_to_jiffies(timeout));
  1728. }
  1729. reinit_completion(&plat_priv->cal_complete);
  1730. ret = cnss_bus_dev_powerup(plat_priv);
  1731. mark_cal_fail:
  1732. if (ret) {
  1733. complete(&plat_priv->cal_complete);
  1734. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1735. /* Set CBC done in driver state to mark attempt and note error
  1736. * since calibration cannot be retried at boot.
  1737. */
  1738. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1739. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1740. }
  1741. out:
  1742. return ret;
  1743. }
  1744. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1745. void *data)
  1746. {
  1747. struct cnss_cal_info *cal_info = data;
  1748. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1749. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1750. goto out;
  1751. switch (cal_info->cal_status) {
  1752. case CNSS_CAL_DONE:
  1753. cnss_pr_dbg("Calibration completed successfully\n");
  1754. plat_priv->cal_done = true;
  1755. break;
  1756. case CNSS_CAL_TIMEOUT:
  1757. case CNSS_CAL_FAILURE:
  1758. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1759. cal_info->cal_status);
  1760. break;
  1761. default:
  1762. cnss_pr_err("Unknown calibration status: %u\n",
  1763. cal_info->cal_status);
  1764. break;
  1765. }
  1766. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1767. cnss_bus_free_qdss_mem(plat_priv);
  1768. cnss_release_antenna_sharing(plat_priv);
  1769. cnss_bus_dev_shutdown(plat_priv);
  1770. msleep(POWER_RESET_MIN_DELAY_MS);
  1771. complete(&plat_priv->cal_complete);
  1772. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1773. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1774. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1775. cnss_cal_mem_upload_to_file(plat_priv);
  1776. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1777. goto out;
  1778. cnss_pr_dbg("Schedule WLAN driver load\n");
  1779. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1780. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1781. 0);
  1782. }
  1783. out:
  1784. kfree(data);
  1785. return 0;
  1786. }
  1787. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1788. {
  1789. int ret;
  1790. ret = cnss_bus_dev_powerup(plat_priv);
  1791. if (ret)
  1792. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1793. return ret;
  1794. }
  1795. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1796. {
  1797. cnss_bus_dev_shutdown(plat_priv);
  1798. return 0;
  1799. }
  1800. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1801. {
  1802. int ret = 0;
  1803. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1804. if (ret < 0)
  1805. return ret;
  1806. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1807. }
  1808. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1809. u32 mem_seg_len, u64 pa, u32 size)
  1810. {
  1811. int i = 0;
  1812. u64 offset = 0;
  1813. void *va = NULL;
  1814. u64 local_pa;
  1815. u32 local_size;
  1816. for (i = 0; i < mem_seg_len; i++) {
  1817. local_pa = (u64)fw_mem[i].pa;
  1818. local_size = (u32)fw_mem[i].size;
  1819. if (pa == local_pa && size <= local_size) {
  1820. va = fw_mem[i].va;
  1821. break;
  1822. }
  1823. if (pa > local_pa &&
  1824. pa < local_pa + local_size &&
  1825. pa + size <= local_pa + local_size) {
  1826. offset = pa - local_pa;
  1827. va = fw_mem[i].va + offset;
  1828. break;
  1829. }
  1830. }
  1831. return va;
  1832. }
  1833. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1834. void *data)
  1835. {
  1836. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1837. struct cnss_fw_mem *fw_mem_seg;
  1838. int ret = 0L;
  1839. void *va = NULL;
  1840. u32 i, fw_mem_seg_len;
  1841. switch (event_data->mem_type) {
  1842. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1843. if (!plat_priv->fw_mem_seg_len)
  1844. goto invalid_mem_save;
  1845. fw_mem_seg = plat_priv->fw_mem;
  1846. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1847. break;
  1848. case QMI_WLFW_MEM_QDSS_V01:
  1849. if (!plat_priv->qdss_mem_seg_len)
  1850. goto invalid_mem_save;
  1851. fw_mem_seg = plat_priv->qdss_mem;
  1852. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1853. break;
  1854. default:
  1855. goto invalid_mem_save;
  1856. }
  1857. for (i = 0; i < event_data->mem_seg_len; i++) {
  1858. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1859. event_data->mem_seg[i].addr,
  1860. event_data->mem_seg[i].size);
  1861. if (!va) {
  1862. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1863. &event_data->mem_seg[i].addr,
  1864. event_data->mem_type);
  1865. ret = -EINVAL;
  1866. break;
  1867. }
  1868. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1869. event_data->file_name,
  1870. event_data->mem_seg[i].size);
  1871. if (ret < 0) {
  1872. cnss_pr_err("Fail to save fw mem data: %d\n",
  1873. ret);
  1874. break;
  1875. }
  1876. }
  1877. kfree(data);
  1878. return ret;
  1879. invalid_mem_save:
  1880. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1881. event_data->mem_type);
  1882. kfree(data);
  1883. return -EINVAL;
  1884. }
  1885. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1886. {
  1887. cnss_bus_free_qdss_mem(plat_priv);
  1888. return 0;
  1889. }
  1890. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1891. void *data)
  1892. {
  1893. int ret = 0;
  1894. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1895. if (!plat_priv)
  1896. return -ENODEV;
  1897. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1898. event_data->total_size);
  1899. kfree(data);
  1900. return ret;
  1901. }
  1902. static void cnss_driver_event_work(struct work_struct *work)
  1903. {
  1904. struct cnss_plat_data *plat_priv =
  1905. container_of(work, struct cnss_plat_data, event_work);
  1906. struct cnss_driver_event *event;
  1907. unsigned long flags;
  1908. int ret = 0;
  1909. if (!plat_priv) {
  1910. cnss_pr_err("plat_priv is NULL!\n");
  1911. return;
  1912. }
  1913. cnss_pm_stay_awake(plat_priv);
  1914. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1915. while (!list_empty(&plat_priv->event_list)) {
  1916. event = list_first_entry(&plat_priv->event_list,
  1917. struct cnss_driver_event, list);
  1918. list_del(&event->list);
  1919. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1920. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1921. cnss_driver_event_to_str(event->type),
  1922. event->sync ? "-sync" : "", event->type,
  1923. plat_priv->driver_state);
  1924. switch (event->type) {
  1925. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1926. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1927. break;
  1928. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1929. ret = cnss_wlfw_server_exit(plat_priv);
  1930. break;
  1931. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1932. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1933. if (ret)
  1934. break;
  1935. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1936. break;
  1937. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1938. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1939. break;
  1940. case CNSS_DRIVER_EVENT_FW_READY:
  1941. ret = cnss_fw_ready_hdlr(plat_priv);
  1942. break;
  1943. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1944. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1945. break;
  1946. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1947. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1948. event->data);
  1949. break;
  1950. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1951. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1952. event->data);
  1953. break;
  1954. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1955. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1956. break;
  1957. case CNSS_DRIVER_EVENT_RECOVERY:
  1958. ret = cnss_driver_recovery_hdlr(plat_priv,
  1959. event->data);
  1960. break;
  1961. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1962. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1963. break;
  1964. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1965. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1966. &plat_priv->driver_state);
  1967. fallthrough;
  1968. case CNSS_DRIVER_EVENT_POWER_UP:
  1969. ret = cnss_power_up_hdlr(plat_priv);
  1970. break;
  1971. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1972. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1973. &plat_priv->driver_state);
  1974. fallthrough;
  1975. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1976. ret = cnss_power_down_hdlr(plat_priv);
  1977. break;
  1978. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1979. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1980. event->data);
  1981. break;
  1982. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1983. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1984. event->data);
  1985. break;
  1986. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1987. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1988. break;
  1989. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1990. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1991. event->data);
  1992. break;
  1993. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1994. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1995. break;
  1996. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1997. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1998. event->data);
  1999. break;
  2000. default:
  2001. cnss_pr_err("Invalid driver event type: %d",
  2002. event->type);
  2003. kfree(event);
  2004. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2005. continue;
  2006. }
  2007. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2008. if (event->sync) {
  2009. event->ret = ret;
  2010. complete(&event->complete);
  2011. continue;
  2012. }
  2013. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2014. kfree(event);
  2015. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2016. }
  2017. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2018. cnss_pm_relax(plat_priv);
  2019. }
  2020. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  2021. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2022. {
  2023. int ret = 0;
  2024. struct cnss_subsys_info *subsys_info;
  2025. subsys_info = &plat_priv->subsys_info;
  2026. subsys_info->subsys_desc.name = "wlan";
  2027. subsys_info->subsys_desc.owner = THIS_MODULE;
  2028. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  2029. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  2030. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  2031. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  2032. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  2033. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  2034. if (IS_ERR(subsys_info->subsys_device)) {
  2035. ret = PTR_ERR(subsys_info->subsys_device);
  2036. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  2037. goto out;
  2038. }
  2039. subsys_info->subsys_handle =
  2040. subsystem_get(subsys_info->subsys_desc.name);
  2041. if (!subsys_info->subsys_handle) {
  2042. cnss_pr_err("Failed to get subsys_handle!\n");
  2043. ret = -EINVAL;
  2044. goto unregister_subsys;
  2045. } else if (IS_ERR(subsys_info->subsys_handle)) {
  2046. ret = PTR_ERR(subsys_info->subsys_handle);
  2047. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  2048. goto unregister_subsys;
  2049. }
  2050. return 0;
  2051. unregister_subsys:
  2052. subsys_unregister(subsys_info->subsys_device);
  2053. out:
  2054. return ret;
  2055. }
  2056. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2057. {
  2058. struct cnss_subsys_info *subsys_info;
  2059. subsys_info = &plat_priv->subsys_info;
  2060. subsystem_put(subsys_info->subsys_handle);
  2061. subsys_unregister(subsys_info->subsys_device);
  2062. }
  2063. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2064. {
  2065. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  2066. return create_ramdump_device(subsys_info->subsys_desc.name,
  2067. subsys_info->subsys_desc.dev);
  2068. }
  2069. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2070. void *ramdump_dev)
  2071. {
  2072. destroy_ramdump_device(ramdump_dev);
  2073. }
  2074. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2075. {
  2076. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2077. struct ramdump_segment segment;
  2078. memset(&segment, 0, sizeof(segment));
  2079. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  2080. segment.size = ramdump_info->ramdump_size;
  2081. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  2082. }
  2083. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2084. {
  2085. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2086. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2087. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2088. struct ramdump_segment *ramdump_segs, *s;
  2089. struct cnss_dump_meta_info meta_info = {0};
  2090. int i, ret = 0;
  2091. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2092. sizeof(*ramdump_segs),
  2093. GFP_KERNEL);
  2094. if (!ramdump_segs)
  2095. return -ENOMEM;
  2096. s = ramdump_segs + 1;
  2097. for (i = 0; i < dump_data->nentries; i++) {
  2098. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2099. cnss_pr_err("Unsupported dump type: %d",
  2100. dump_seg->type);
  2101. continue;
  2102. }
  2103. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2104. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2105. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2106. }
  2107. meta_info.entry[dump_seg->type].entry_num++;
  2108. s->address = dump_seg->address;
  2109. s->v_address = (void __iomem *)dump_seg->v_address;
  2110. s->size = dump_seg->size;
  2111. s++;
  2112. dump_seg++;
  2113. }
  2114. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2115. meta_info.version = CNSS_RAMDUMP_VERSION;
  2116. meta_info.chipset = plat_priv->device_id;
  2117. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2118. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2119. ramdump_segs->size = sizeof(meta_info);
  2120. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2121. dump_data->nentries + 1);
  2122. kfree(ramdump_segs);
  2123. return ret;
  2124. }
  2125. #else
  2126. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2127. void *data)
  2128. {
  2129. struct cnss_plat_data *plat_priv =
  2130. container_of(nb, struct cnss_plat_data, panic_nb);
  2131. cnss_bus_dev_crash_shutdown(plat_priv);
  2132. return NOTIFY_DONE;
  2133. }
  2134. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2135. {
  2136. int ret;
  2137. if (!plat_priv)
  2138. return -ENODEV;
  2139. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2140. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2141. &plat_priv->panic_nb);
  2142. if (ret) {
  2143. cnss_pr_err("Failed to register panic handler\n");
  2144. return -EINVAL;
  2145. }
  2146. return 0;
  2147. }
  2148. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2149. {
  2150. int ret;
  2151. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2152. &plat_priv->panic_nb);
  2153. if (ret)
  2154. cnss_pr_err("Failed to unregister panic handler\n");
  2155. }
  2156. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2157. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2158. {
  2159. return &plat_priv->plat_dev->dev;
  2160. }
  2161. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2162. void *ramdump_dev)
  2163. {
  2164. }
  2165. #endif
  2166. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2167. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2168. {
  2169. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2170. struct qcom_dump_segment segment;
  2171. struct list_head head;
  2172. INIT_LIST_HEAD(&head);
  2173. memset(&segment, 0, sizeof(segment));
  2174. segment.va = ramdump_info->ramdump_va;
  2175. segment.size = ramdump_info->ramdump_size;
  2176. list_add(&segment.node, &head);
  2177. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2178. }
  2179. #else
  2180. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2181. {
  2182. return 0;
  2183. }
  2184. /* Using completion event inside dynamically allocated ramdump_desc
  2185. * may result a race between freeing the event after setting it to
  2186. * complete inside dev coredump free callback and the thread that is
  2187. * waiting for completion.
  2188. */
  2189. DECLARE_COMPLETION(dump_done);
  2190. #define TIMEOUT_SAVE_DUMP_MS 30000
  2191. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2192. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2193. { \
  2194. if (class == ELFCLASS32) \
  2195. return sizeof(struct elf32_##__xhdr); \
  2196. else \
  2197. return sizeof(struct elf64_##__xhdr); \
  2198. }
  2199. SIZEOF_ELF_STRUCT(phdr)
  2200. SIZEOF_ELF_STRUCT(hdr)
  2201. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2202. do { \
  2203. if (class == ELFCLASS32) \
  2204. ((struct elf32_##__xhdr *)arg)->member = value; \
  2205. else \
  2206. ((struct elf64_##__xhdr *)arg)->member = value; \
  2207. } while (0)
  2208. #define set_ehdr_property(arg, class, member, value) \
  2209. set_xhdr_property(hdr, arg, class, member, value)
  2210. #define set_phdr_property(arg, class, member, value) \
  2211. set_xhdr_property(phdr, arg, class, member, value)
  2212. /* These replace qcom_ramdump driver APIs called from common API
  2213. * cnss_do_elf_dump() by the ones defined here.
  2214. */
  2215. #define qcom_dump_segment cnss_qcom_dump_segment
  2216. #define qcom_elf_dump cnss_qcom_elf_dump
  2217. #define dump_enabled cnss_dump_enabled
  2218. struct cnss_qcom_dump_segment {
  2219. struct list_head node;
  2220. dma_addr_t da;
  2221. void *va;
  2222. size_t size;
  2223. };
  2224. struct cnss_qcom_ramdump_desc {
  2225. void *data;
  2226. struct completion dump_done;
  2227. };
  2228. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2229. void *data, size_t datalen)
  2230. {
  2231. struct cnss_qcom_ramdump_desc *desc = data;
  2232. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2233. datalen);
  2234. }
  2235. static void cnss_qcom_devcd_freev(void *data)
  2236. {
  2237. struct cnss_qcom_ramdump_desc *desc = data;
  2238. cnss_pr_dbg("Free dump data for dev coredump\n");
  2239. complete(&dump_done);
  2240. vfree(desc->data);
  2241. kfree(desc);
  2242. }
  2243. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2244. gfp_t gfp)
  2245. {
  2246. struct cnss_qcom_ramdump_desc *desc;
  2247. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2248. int ret;
  2249. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2250. if (!desc)
  2251. return -ENOMEM;
  2252. desc->data = data;
  2253. reinit_completion(&dump_done);
  2254. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2255. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2256. ret = wait_for_completion_timeout(&dump_done,
  2257. msecs_to_jiffies(timeout));
  2258. if (!ret)
  2259. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2260. timeout);
  2261. return ret ? 0 : -ETIMEDOUT;
  2262. }
  2263. /* Since the elf32 and elf64 identification is identical apart from
  2264. * the class, use elf32 by default.
  2265. */
  2266. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2267. {
  2268. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2269. ehdr->e_ident[EI_CLASS] = class;
  2270. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2271. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2272. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2273. }
  2274. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2275. unsigned char class)
  2276. {
  2277. struct cnss_qcom_dump_segment *segment;
  2278. void *phdr, *ehdr;
  2279. size_t data_size, offset;
  2280. int phnum = 0;
  2281. void *data;
  2282. void __iomem *ptr;
  2283. if (!segs || list_empty(segs))
  2284. return -EINVAL;
  2285. data_size = sizeof_elf_hdr(class);
  2286. list_for_each_entry(segment, segs, node) {
  2287. data_size += sizeof_elf_phdr(class) + segment->size;
  2288. phnum++;
  2289. }
  2290. data = vmalloc(data_size);
  2291. if (!data)
  2292. return -ENOMEM;
  2293. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2294. ehdr = data;
  2295. memset(ehdr, 0, sizeof_elf_hdr(class));
  2296. init_elf_identification(ehdr, class);
  2297. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2298. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2299. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2300. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2301. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2302. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2303. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2304. phdr = data + sizeof_elf_hdr(class);
  2305. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2306. list_for_each_entry(segment, segs, node) {
  2307. memset(phdr, 0, sizeof_elf_phdr(class));
  2308. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2309. set_phdr_property(phdr, class, p_offset, offset);
  2310. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2311. set_phdr_property(phdr, class, p_paddr, segment->da);
  2312. set_phdr_property(phdr, class, p_filesz, segment->size);
  2313. set_phdr_property(phdr, class, p_memsz, segment->size);
  2314. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2315. set_phdr_property(phdr, class, p_align, 0);
  2316. if (segment->va) {
  2317. memcpy(data + offset, segment->va, segment->size);
  2318. } else {
  2319. ptr = devm_ioremap(dev, segment->da, segment->size);
  2320. if (!ptr) {
  2321. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2322. &segment->da, segment->size);
  2323. memset(data + offset, 0xff, segment->size);
  2324. } else {
  2325. memcpy_fromio(data + offset, ptr,
  2326. segment->size);
  2327. }
  2328. }
  2329. offset += segment->size;
  2330. phdr += sizeof_elf_phdr(class);
  2331. }
  2332. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2333. }
  2334. /* Saving dump to file system is always needed in this case. */
  2335. static bool cnss_dump_enabled(void)
  2336. {
  2337. return true;
  2338. }
  2339. #endif /* CONFIG_QCOM_RAMDUMP */
  2340. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2341. {
  2342. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2343. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2344. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2345. struct qcom_dump_segment *seg;
  2346. struct cnss_dump_meta_info meta_info = {0};
  2347. struct list_head head;
  2348. int i, ret = 0;
  2349. if (!dump_enabled()) {
  2350. cnss_pr_info("Dump collection is not enabled\n");
  2351. return ret;
  2352. }
  2353. INIT_LIST_HEAD(&head);
  2354. for (i = 0; i < dump_data->nentries; i++) {
  2355. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2356. cnss_pr_err("Unsupported dump type: %d",
  2357. dump_seg->type);
  2358. continue;
  2359. }
  2360. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2361. if (!seg)
  2362. continue;
  2363. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2364. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2365. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2366. }
  2367. meta_info.entry[dump_seg->type].entry_num++;
  2368. seg->da = dump_seg->address;
  2369. seg->va = dump_seg->v_address;
  2370. seg->size = dump_seg->size;
  2371. list_add_tail(&seg->node, &head);
  2372. dump_seg++;
  2373. }
  2374. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2375. if (!seg)
  2376. goto do_elf_dump;
  2377. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2378. meta_info.version = CNSS_RAMDUMP_VERSION;
  2379. meta_info.chipset = plat_priv->device_id;
  2380. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2381. seg->va = &meta_info;
  2382. seg->size = sizeof(meta_info);
  2383. list_add(&seg->node, &head);
  2384. do_elf_dump:
  2385. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2386. while (!list_empty(&head)) {
  2387. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2388. list_del(&seg->node);
  2389. kfree(seg);
  2390. }
  2391. return ret;
  2392. }
  2393. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2394. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2395. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2396. {
  2397. struct cnss_ramdump_info *ramdump_info;
  2398. struct msm_dump_entry dump_entry;
  2399. ramdump_info = &plat_priv->ramdump_info;
  2400. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2401. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2402. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2403. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2404. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2405. sizeof(ramdump_info->dump_data.name));
  2406. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2407. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2408. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2409. &dump_entry);
  2410. }
  2411. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2412. {
  2413. int ret = 0;
  2414. struct device *dev;
  2415. struct cnss_ramdump_info *ramdump_info;
  2416. u32 ramdump_size = 0;
  2417. dev = &plat_priv->plat_dev->dev;
  2418. ramdump_info = &plat_priv->ramdump_info;
  2419. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2420. /* dt type: legacy or converged */
  2421. ret = of_property_read_u32(dev->of_node,
  2422. "qcom,wlan-ramdump-dynamic",
  2423. &ramdump_size);
  2424. } else {
  2425. ret = of_property_read_u32(plat_priv->dev_node,
  2426. "qcom,wlan-ramdump-dynamic",
  2427. &ramdump_size);
  2428. }
  2429. if (ret == 0) {
  2430. ramdump_info->ramdump_va =
  2431. dma_alloc_coherent(dev, ramdump_size,
  2432. &ramdump_info->ramdump_pa,
  2433. GFP_KERNEL);
  2434. if (ramdump_info->ramdump_va)
  2435. ramdump_info->ramdump_size = ramdump_size;
  2436. }
  2437. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2438. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2439. if (ramdump_info->ramdump_size == 0) {
  2440. cnss_pr_info("Ramdump will not be collected");
  2441. goto out;
  2442. }
  2443. ret = cnss_init_dump_entry(plat_priv);
  2444. if (ret) {
  2445. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2446. goto free_ramdump;
  2447. }
  2448. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2449. if (!ramdump_info->ramdump_dev) {
  2450. cnss_pr_err("Failed to create ramdump device!");
  2451. ret = -ENOMEM;
  2452. goto free_ramdump;
  2453. }
  2454. return 0;
  2455. free_ramdump:
  2456. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2457. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2458. out:
  2459. return ret;
  2460. }
  2461. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2462. {
  2463. struct device *dev;
  2464. struct cnss_ramdump_info *ramdump_info;
  2465. dev = &plat_priv->plat_dev->dev;
  2466. ramdump_info = &plat_priv->ramdump_info;
  2467. if (ramdump_info->ramdump_dev)
  2468. cnss_destroy_ramdump_device(plat_priv,
  2469. ramdump_info->ramdump_dev);
  2470. if (ramdump_info->ramdump_va)
  2471. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2472. ramdump_info->ramdump_va,
  2473. ramdump_info->ramdump_pa);
  2474. }
  2475. /**
  2476. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2477. * @ret: Error returned by msm_dump_data_register_nominidump
  2478. *
  2479. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2480. * ignore failure.
  2481. *
  2482. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2483. */
  2484. static int cnss_ignore_dump_data_reg_fail(int ret)
  2485. {
  2486. return ret;
  2487. }
  2488. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2489. {
  2490. int ret = 0;
  2491. struct cnss_ramdump_info_v2 *info_v2;
  2492. struct cnss_dump_data *dump_data;
  2493. struct msm_dump_entry dump_entry;
  2494. struct device *dev = &plat_priv->plat_dev->dev;
  2495. u32 ramdump_size = 0;
  2496. info_v2 = &plat_priv->ramdump_info_v2;
  2497. dump_data = &info_v2->dump_data;
  2498. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2499. /* dt type: legacy or converged */
  2500. ret = of_property_read_u32(dev->of_node,
  2501. "qcom,wlan-ramdump-dynamic",
  2502. &ramdump_size);
  2503. } else {
  2504. ret = of_property_read_u32(plat_priv->dev_node,
  2505. "qcom,wlan-ramdump-dynamic",
  2506. &ramdump_size);
  2507. }
  2508. if (ret == 0)
  2509. info_v2->ramdump_size = ramdump_size;
  2510. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2511. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2512. if (!info_v2->dump_data_vaddr)
  2513. return -ENOMEM;
  2514. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2515. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2516. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2517. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2518. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2519. sizeof(dump_data->name));
  2520. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2521. dump_entry.addr = virt_to_phys(dump_data);
  2522. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2523. &dump_entry);
  2524. if (ret) {
  2525. ret = cnss_ignore_dump_data_reg_fail(ret);
  2526. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2527. ret ? "Error" : "Ignoring", ret);
  2528. goto free_ramdump;
  2529. }
  2530. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2531. if (!info_v2->ramdump_dev) {
  2532. cnss_pr_err("Failed to create ramdump device!\n");
  2533. ret = -ENOMEM;
  2534. goto free_ramdump;
  2535. }
  2536. return 0;
  2537. free_ramdump:
  2538. kfree(info_v2->dump_data_vaddr);
  2539. info_v2->dump_data_vaddr = NULL;
  2540. return ret;
  2541. }
  2542. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2543. {
  2544. struct cnss_ramdump_info_v2 *info_v2;
  2545. info_v2 = &plat_priv->ramdump_info_v2;
  2546. if (info_v2->ramdump_dev)
  2547. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2548. kfree(info_v2->dump_data_vaddr);
  2549. info_v2->dump_data_vaddr = NULL;
  2550. info_v2->dump_data_valid = false;
  2551. }
  2552. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2553. {
  2554. int ret = 0;
  2555. switch (plat_priv->device_id) {
  2556. case QCA6174_DEVICE_ID:
  2557. ret = cnss_register_ramdump_v1(plat_priv);
  2558. break;
  2559. case QCA6290_DEVICE_ID:
  2560. case QCA6390_DEVICE_ID:
  2561. case QCA6490_DEVICE_ID:
  2562. case KIWI_DEVICE_ID:
  2563. case MANGO_DEVICE_ID:
  2564. ret = cnss_register_ramdump_v2(plat_priv);
  2565. break;
  2566. default:
  2567. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2568. ret = -ENODEV;
  2569. break;
  2570. }
  2571. return ret;
  2572. }
  2573. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2574. {
  2575. switch (plat_priv->device_id) {
  2576. case QCA6174_DEVICE_ID:
  2577. cnss_unregister_ramdump_v1(plat_priv);
  2578. break;
  2579. case QCA6290_DEVICE_ID:
  2580. case QCA6390_DEVICE_ID:
  2581. case QCA6490_DEVICE_ID:
  2582. case KIWI_DEVICE_ID:
  2583. case MANGO_DEVICE_ID:
  2584. cnss_unregister_ramdump_v2(plat_priv);
  2585. break;
  2586. default:
  2587. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2588. break;
  2589. }
  2590. }
  2591. #else
  2592. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2593. {
  2594. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2595. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2596. struct device *dev = &plat_priv->plat_dev->dev;
  2597. u32 ramdump_size = 0;
  2598. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2599. &ramdump_size) == 0)
  2600. info_v2->ramdump_size = ramdump_size;
  2601. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2602. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2603. if (!info_v2->dump_data_vaddr)
  2604. return -ENOMEM;
  2605. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2606. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2607. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2608. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2609. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2610. sizeof(dump_data->name));
  2611. info_v2->ramdump_dev = dev;
  2612. return 0;
  2613. }
  2614. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2615. {
  2616. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2617. info_v2->ramdump_dev = NULL;
  2618. kfree(info_v2->dump_data_vaddr);
  2619. info_v2->dump_data_vaddr = NULL;
  2620. info_v2->dump_data_valid = false;
  2621. }
  2622. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2623. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2624. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2625. phys_addr_t *pa, unsigned long attrs)
  2626. {
  2627. struct sg_table sgt;
  2628. int ret;
  2629. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2630. if (ret) {
  2631. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2632. va, &dma, size, attrs);
  2633. return -EINVAL;
  2634. }
  2635. *pa = page_to_phys(sg_page(sgt.sgl));
  2636. sg_free_table(&sgt);
  2637. return 0;
  2638. }
  2639. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2640. enum cnss_fw_dump_type type, int seg_no,
  2641. void *va, phys_addr_t pa, size_t size)
  2642. {
  2643. struct md_region md_entry;
  2644. int ret;
  2645. switch (type) {
  2646. case CNSS_FW_IMAGE:
  2647. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2648. seg_no);
  2649. break;
  2650. case CNSS_FW_RDDM:
  2651. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2652. seg_no);
  2653. break;
  2654. case CNSS_FW_REMOTE_HEAP:
  2655. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2656. seg_no);
  2657. break;
  2658. default:
  2659. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2660. return -EINVAL;
  2661. }
  2662. md_entry.phys_addr = pa;
  2663. md_entry.virt_addr = (uintptr_t)va;
  2664. md_entry.size = size;
  2665. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2666. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2667. md_entry.name, va, &pa, size);
  2668. ret = msm_minidump_add_region(&md_entry);
  2669. if (ret < 0)
  2670. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2671. return ret;
  2672. }
  2673. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2674. enum cnss_fw_dump_type type, int seg_no,
  2675. void *va, phys_addr_t pa, size_t size)
  2676. {
  2677. struct md_region md_entry;
  2678. int ret;
  2679. switch (type) {
  2680. case CNSS_FW_IMAGE:
  2681. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2682. seg_no);
  2683. break;
  2684. case CNSS_FW_RDDM:
  2685. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2686. seg_no);
  2687. break;
  2688. case CNSS_FW_REMOTE_HEAP:
  2689. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2690. seg_no);
  2691. break;
  2692. default:
  2693. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2694. return -EINVAL;
  2695. }
  2696. md_entry.phys_addr = pa;
  2697. md_entry.virt_addr = (uintptr_t)va;
  2698. md_entry.size = size;
  2699. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2700. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2701. md_entry.name, va, &pa, size);
  2702. ret = msm_minidump_remove_region(&md_entry);
  2703. if (ret)
  2704. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2705. ret);
  2706. return ret;
  2707. }
  2708. #else
  2709. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2710. phys_addr_t *pa, unsigned long attrs)
  2711. {
  2712. return 0;
  2713. }
  2714. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2715. enum cnss_fw_dump_type type, int seg_no,
  2716. void *va, phys_addr_t pa, size_t size)
  2717. {
  2718. return 0;
  2719. }
  2720. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2721. enum cnss_fw_dump_type type, int seg_no,
  2722. void *va, phys_addr_t pa, size_t size)
  2723. {
  2724. return 0;
  2725. }
  2726. #endif /* CONFIG_QCOM_MINIDUMP */
  2727. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2728. const struct firmware **fw_entry,
  2729. const char *filename)
  2730. {
  2731. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2732. return request_firmware_direct(fw_entry, filename,
  2733. &plat_priv->plat_dev->dev);
  2734. else
  2735. return firmware_request_nowarn(fw_entry, filename,
  2736. &plat_priv->plat_dev->dev);
  2737. }
  2738. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2739. /**
  2740. * cnss_register_bus_scale() - Setup interconnect voting data
  2741. * @plat_priv: Platform data structure
  2742. *
  2743. * For different interconnect path configured in device tree setup voting data
  2744. * for list of bandwidth requirements.
  2745. *
  2746. * Result: 0 for success. -EINVAL if not configured
  2747. */
  2748. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2749. {
  2750. int ret = -EINVAL;
  2751. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2752. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2753. struct device *dev = &plat_priv->plat_dev->dev;
  2754. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2755. ret = of_property_read_u32(dev->of_node,
  2756. "qcom,icc-path-count",
  2757. &plat_priv->icc.path_count);
  2758. if (ret) {
  2759. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2760. return 0;
  2761. }
  2762. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2763. "qcom,bus-bw-cfg-count",
  2764. &plat_priv->icc.bus_bw_cfg_count);
  2765. if (ret) {
  2766. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2767. goto cleanup;
  2768. }
  2769. cfg_arr_size = plat_priv->icc.path_count *
  2770. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2771. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2772. if (!cfg_arr) {
  2773. cnss_pr_err("Failed to alloc cfg table mem\n");
  2774. ret = -ENOMEM;
  2775. goto cleanup;
  2776. }
  2777. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2778. "qcom,bus-bw-cfg", cfg_arr,
  2779. cfg_arr_size);
  2780. if (ret) {
  2781. cnss_pr_err("Invalid Bus BW Config Table\n");
  2782. goto cleanup;
  2783. }
  2784. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2785. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2786. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2787. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2788. GFP_KERNEL);
  2789. if (!bus_bw_info) {
  2790. ret = -ENOMEM;
  2791. goto out;
  2792. }
  2793. ret = of_property_read_string_index(dev->of_node,
  2794. "interconnect-names", idx,
  2795. &bus_bw_info->icc_name);
  2796. if (ret)
  2797. goto out;
  2798. bus_bw_info->icc_path =
  2799. of_icc_get(&plat_priv->plat_dev->dev,
  2800. bus_bw_info->icc_name);
  2801. if (IS_ERR(bus_bw_info->icc_path)) {
  2802. ret = PTR_ERR(bus_bw_info->icc_path);
  2803. if (ret != -EPROBE_DEFER) {
  2804. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2805. bus_bw_info->icc_name, ret);
  2806. goto out;
  2807. }
  2808. }
  2809. bus_bw_info->cfg_table =
  2810. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2811. sizeof(*bus_bw_info->cfg_table),
  2812. GFP_KERNEL);
  2813. if (!bus_bw_info->cfg_table) {
  2814. ret = -ENOMEM;
  2815. goto out;
  2816. }
  2817. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2818. bus_bw_info->icc_name);
  2819. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2820. CNSS_ICC_VOTE_MAX);
  2821. i < plat_priv->icc.bus_bw_cfg_count;
  2822. i++, j += 2) {
  2823. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2824. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2825. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2826. i, bus_bw_info->cfg_table[i].avg_bw,
  2827. bus_bw_info->cfg_table[i].peak_bw);
  2828. }
  2829. list_add_tail(&bus_bw_info->list,
  2830. &plat_priv->icc.list_head);
  2831. }
  2832. kfree(cfg_arr);
  2833. return 0;
  2834. out:
  2835. list_for_each_entry_safe(bus_bw_info, tmp,
  2836. &plat_priv->icc.list_head, list) {
  2837. list_del(&bus_bw_info->list);
  2838. }
  2839. cleanup:
  2840. kfree(cfg_arr);
  2841. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2842. return ret;
  2843. }
  2844. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2845. {
  2846. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2847. list_for_each_entry_safe(bus_bw_info, tmp,
  2848. &plat_priv->icc.list_head, list) {
  2849. list_del(&bus_bw_info->list);
  2850. if (bus_bw_info->icc_path)
  2851. icc_put(bus_bw_info->icc_path);
  2852. }
  2853. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2854. }
  2855. #else
  2856. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2857. {
  2858. return 0;
  2859. }
  2860. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2861. #endif /* CONFIG_INTERCONNECT */
  2862. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2863. {
  2864. struct cnss_plat_data *plat_priv = cb_ctx;
  2865. if (!plat_priv) {
  2866. cnss_pr_err("%s: Invalid context\n", __func__);
  2867. return;
  2868. }
  2869. if (status) {
  2870. cnss_pr_info("CNSS Daemon connected\n");
  2871. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2872. complete(&plat_priv->daemon_connected);
  2873. } else {
  2874. cnss_pr_info("CNSS Daemon disconnected\n");
  2875. reinit_completion(&plat_priv->daemon_connected);
  2876. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2877. }
  2878. }
  2879. static ssize_t enable_hds_store(struct device *dev,
  2880. struct device_attribute *attr,
  2881. const char *buf, size_t count)
  2882. {
  2883. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2884. unsigned int enable_hds = 0;
  2885. if (!plat_priv)
  2886. return -ENODEV;
  2887. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2888. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2889. return -EINVAL;
  2890. }
  2891. if (enable_hds)
  2892. plat_priv->hds_enabled = true;
  2893. else
  2894. plat_priv->hds_enabled = false;
  2895. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2896. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2897. return count;
  2898. }
  2899. static ssize_t recovery_show(struct device *dev,
  2900. struct device_attribute *attr,
  2901. char *buf)
  2902. {
  2903. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2904. u32 buf_size = PAGE_SIZE;
  2905. u32 curr_len = 0;
  2906. u32 buf_written = 0;
  2907. if (!plat_priv)
  2908. return -ENODEV;
  2909. buf_written = scnprintf(buf, buf_size,
  2910. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  2911. "BIT0 -- wlan fw recovery\n"
  2912. "BIT1 -- wlan pcss recovery\n"
  2913. "---------------------------------\n");
  2914. curr_len += buf_written;
  2915. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2916. "WLAN recovery %s[%d]\n",
  2917. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  2918. plat_priv->recovery_enabled);
  2919. curr_len += buf_written;
  2920. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2921. "WLAN PCSS recovery %s[%d]\n",
  2922. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  2923. plat_priv->recovery_pcss_enabled);
  2924. curr_len += buf_written;
  2925. /*
  2926. * Now size of curr_len is not over page size for sure,
  2927. * later if new item or none-fixed size item added, need
  2928. * add check to make sure curr_len is not over page size.
  2929. */
  2930. return curr_len;
  2931. }
  2932. static ssize_t time_sync_period_show(struct device *dev,
  2933. struct device_attribute *attr,
  2934. char *buf)
  2935. {
  2936. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2937. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  2938. plat_priv->ctrl_params.time_sync_period);
  2939. }
  2940. static ssize_t time_sync_period_store(struct device *dev,
  2941. struct device_attribute *attr,
  2942. const char *buf, size_t count)
  2943. {
  2944. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2945. unsigned int time_sync_period = 0;
  2946. if (!plat_priv)
  2947. return -ENODEV;
  2948. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  2949. cnss_pr_err("Invalid time sync sysfs command\n");
  2950. return -EINVAL;
  2951. }
  2952. if (time_sync_period >= CNSS_MIN_TIME_SYNC_PERIOD)
  2953. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  2954. return count;
  2955. }
  2956. static ssize_t recovery_store(struct device *dev,
  2957. struct device_attribute *attr,
  2958. const char *buf, size_t count)
  2959. {
  2960. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2961. unsigned int recovery = 0;
  2962. int ret;
  2963. if (!plat_priv)
  2964. return -ENODEV;
  2965. if (sscanf(buf, "%du", &recovery) != 1) {
  2966. cnss_pr_err("Invalid recovery sysfs command\n");
  2967. return -EINVAL;
  2968. }
  2969. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  2970. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  2971. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2972. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2973. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  2974. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  2975. ret = cnss_send_subsys_restart_level_msg(plat_priv);
  2976. if (ret < 0) {
  2977. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  2978. plat_priv->recovery_pcss_enabled = false;
  2979. return -EINVAL;
  2980. }
  2981. return count;
  2982. }
  2983. static ssize_t shutdown_store(struct device *dev,
  2984. struct device_attribute *attr,
  2985. const char *buf, size_t count)
  2986. {
  2987. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2988. if (plat_priv) {
  2989. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2990. del_timer(&plat_priv->fw_boot_timer);
  2991. complete_all(&plat_priv->power_up_complete);
  2992. complete_all(&plat_priv->cal_complete);
  2993. }
  2994. cnss_pr_dbg("Received shutdown notification\n");
  2995. return count;
  2996. }
  2997. static ssize_t fs_ready_store(struct device *dev,
  2998. struct device_attribute *attr,
  2999. const char *buf, size_t count)
  3000. {
  3001. int fs_ready = 0;
  3002. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3003. if (sscanf(buf, "%du", &fs_ready) != 1)
  3004. return -EINVAL;
  3005. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  3006. fs_ready, count);
  3007. if (!plat_priv) {
  3008. cnss_pr_err("plat_priv is NULL\n");
  3009. return count;
  3010. }
  3011. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  3012. cnss_pr_dbg("QMI is bypassed\n");
  3013. return count;
  3014. }
  3015. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  3016. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  3017. cnss_driver_event_post(plat_priv,
  3018. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3019. 0, NULL);
  3020. }
  3021. return count;
  3022. }
  3023. static ssize_t qdss_trace_start_store(struct device *dev,
  3024. struct device_attribute *attr,
  3025. const char *buf, size_t count)
  3026. {
  3027. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3028. wlfw_qdss_trace_start(plat_priv);
  3029. cnss_pr_dbg("Received QDSS start command\n");
  3030. return count;
  3031. }
  3032. static ssize_t qdss_trace_stop_store(struct device *dev,
  3033. struct device_attribute *attr,
  3034. const char *buf, size_t count)
  3035. {
  3036. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3037. u32 option = 0;
  3038. if (sscanf(buf, "%du", &option) != 1)
  3039. return -EINVAL;
  3040. wlfw_qdss_trace_stop(plat_priv, option);
  3041. cnss_pr_dbg("Received QDSS stop command\n");
  3042. return count;
  3043. }
  3044. static ssize_t qdss_conf_download_store(struct device *dev,
  3045. struct device_attribute *attr,
  3046. const char *buf, size_t count)
  3047. {
  3048. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3049. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  3050. cnss_pr_dbg("Received QDSS download config command\n");
  3051. return count;
  3052. }
  3053. static ssize_t hw_trace_override_store(struct device *dev,
  3054. struct device_attribute *attr,
  3055. const char *buf, size_t count)
  3056. {
  3057. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3058. int tmp = 0;
  3059. if (sscanf(buf, "%du", &tmp) != 1)
  3060. return -EINVAL;
  3061. plat_priv->hw_trc_override = tmp;
  3062. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  3063. return count;
  3064. }
  3065. static ssize_t charger_mode_store(struct device *dev,
  3066. struct device_attribute *attr,
  3067. const char *buf, size_t count)
  3068. {
  3069. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3070. int tmp = 0;
  3071. if (sscanf(buf, "%du", &tmp) != 1)
  3072. return -EINVAL;
  3073. plat_priv->charger_mode = tmp;
  3074. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  3075. return count;
  3076. }
  3077. static DEVICE_ATTR_WO(fs_ready);
  3078. static DEVICE_ATTR_WO(shutdown);
  3079. static DEVICE_ATTR_RW(recovery);
  3080. static DEVICE_ATTR_WO(enable_hds);
  3081. static DEVICE_ATTR_WO(qdss_trace_start);
  3082. static DEVICE_ATTR_WO(qdss_trace_stop);
  3083. static DEVICE_ATTR_WO(qdss_conf_download);
  3084. static DEVICE_ATTR_WO(hw_trace_override);
  3085. static DEVICE_ATTR_WO(charger_mode);
  3086. static DEVICE_ATTR_RW(time_sync_period);
  3087. static struct attribute *cnss_attrs[] = {
  3088. &dev_attr_fs_ready.attr,
  3089. &dev_attr_shutdown.attr,
  3090. &dev_attr_recovery.attr,
  3091. &dev_attr_enable_hds.attr,
  3092. &dev_attr_qdss_trace_start.attr,
  3093. &dev_attr_qdss_trace_stop.attr,
  3094. &dev_attr_qdss_conf_download.attr,
  3095. &dev_attr_hw_trace_override.attr,
  3096. &dev_attr_charger_mode.attr,
  3097. &dev_attr_time_sync_period.attr,
  3098. NULL,
  3099. };
  3100. static struct attribute_group cnss_attr_group = {
  3101. .attrs = cnss_attrs,
  3102. };
  3103. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3104. {
  3105. struct device *dev = &plat_priv->plat_dev->dev;
  3106. int ret;
  3107. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  3108. if (ret) {
  3109. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3110. ret);
  3111. goto out;
  3112. }
  3113. /* This is only for backward compatibility. */
  3114. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  3115. if (ret) {
  3116. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3117. ret);
  3118. goto rm_cnss_link;
  3119. }
  3120. return 0;
  3121. rm_cnss_link:
  3122. sysfs_remove_link(kernel_kobj, "cnss");
  3123. out:
  3124. return ret;
  3125. }
  3126. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3127. {
  3128. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  3129. sysfs_remove_link(kernel_kobj, "cnss");
  3130. }
  3131. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3132. {
  3133. int ret = 0;
  3134. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3135. &cnss_attr_group);
  3136. if (ret) {
  3137. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3138. ret);
  3139. goto out;
  3140. }
  3141. cnss_create_sysfs_link(plat_priv);
  3142. return 0;
  3143. out:
  3144. return ret;
  3145. }
  3146. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3147. {
  3148. cnss_remove_sysfs_link(plat_priv);
  3149. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  3150. }
  3151. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3152. {
  3153. spin_lock_init(&plat_priv->event_lock);
  3154. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3155. WQ_UNBOUND, 1);
  3156. if (!plat_priv->event_wq) {
  3157. cnss_pr_err("Failed to create event workqueue!\n");
  3158. return -EFAULT;
  3159. }
  3160. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3161. INIT_LIST_HEAD(&plat_priv->event_list);
  3162. return 0;
  3163. }
  3164. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3165. {
  3166. destroy_workqueue(plat_priv->event_wq);
  3167. }
  3168. static int cnss_reboot_notifier(struct notifier_block *nb,
  3169. unsigned long action,
  3170. void *data)
  3171. {
  3172. struct cnss_plat_data *plat_priv =
  3173. container_of(nb, struct cnss_plat_data, reboot_nb);
  3174. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3175. del_timer(&plat_priv->fw_boot_timer);
  3176. complete_all(&plat_priv->power_up_complete);
  3177. complete_all(&plat_priv->cal_complete);
  3178. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3179. return NOTIFY_DONE;
  3180. }
  3181. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  3182. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3183. {
  3184. struct Object client_env;
  3185. struct Object app_object;
  3186. u32 wifi_uid = HW_WIFI_UID;
  3187. union ObjectArg obj_arg[2] = {{{0, 0}}};
  3188. int ret;
  3189. u8 state = 0;
  3190. /* Once this flag is set, secure peripheral feature
  3191. * will not be supported till next reboot
  3192. */
  3193. if (plat_priv->sec_peri_feature_disable)
  3194. return 0;
  3195. /* get rootObj */
  3196. ret = get_client_env_object(&client_env);
  3197. if (ret) {
  3198. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  3199. goto end;
  3200. }
  3201. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  3202. if (ret) {
  3203. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  3204. if (ret == FEATURE_NOT_SUPPORTED) {
  3205. ret = 0; /* Do not Assert */
  3206. plat_priv->sec_peri_feature_disable = true;
  3207. cnss_pr_dbg("Secure HW feature not supported\n");
  3208. }
  3209. goto exit_release_clientenv;
  3210. }
  3211. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  3212. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  3213. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  3214. ObjectCounts_pack(1, 1, 0, 0));
  3215. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  3216. if (ret) {
  3217. if (ret == PERIPHERAL_NOT_FOUND) {
  3218. ret = 0; /* Do not Assert */
  3219. plat_priv->sec_peri_feature_disable = true;
  3220. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  3221. }
  3222. goto exit_release_app_obj;
  3223. }
  3224. if (state == 1)
  3225. set_bit(CNSS_WLAN_HW_DISABLED,
  3226. &plat_priv->driver_state);
  3227. else
  3228. clear_bit(CNSS_WLAN_HW_DISABLED,
  3229. &plat_priv->driver_state);
  3230. exit_release_app_obj:
  3231. Object_release(app_object);
  3232. exit_release_clientenv:
  3233. Object_release(client_env);
  3234. end:
  3235. if (ret) {
  3236. cnss_pr_err("Unable to get HW disable status\n");
  3237. CNSS_ASSERT(0);
  3238. }
  3239. return ret;
  3240. }
  3241. #else
  3242. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3243. {
  3244. return 0;
  3245. }
  3246. #endif
  3247. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  3248. {
  3249. int ret;
  3250. ret = cnss_init_sol_gpio(plat_priv);
  3251. if (ret)
  3252. return ret;
  3253. timer_setup(&plat_priv->fw_boot_timer,
  3254. cnss_bus_fw_boot_timeout_hdlr, 0);
  3255. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  3256. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  3257. if (ret)
  3258. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  3259. ret);
  3260. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  3261. if (ret)
  3262. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  3263. ret);
  3264. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  3265. init_completion(&plat_priv->power_up_complete);
  3266. init_completion(&plat_priv->cal_complete);
  3267. init_completion(&plat_priv->rddm_complete);
  3268. init_completion(&plat_priv->recovery_complete);
  3269. init_completion(&plat_priv->daemon_connected);
  3270. mutex_init(&plat_priv->dev_lock);
  3271. mutex_init(&plat_priv->driver_ops_lock);
  3272. plat_priv->recovery_ws =
  3273. wakeup_source_register(&plat_priv->plat_dev->dev,
  3274. "CNSS_FW_RECOVERY");
  3275. if (!plat_priv->recovery_ws)
  3276. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3277. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3278. cnss_daemon_connection_update_cb,
  3279. plat_priv);
  3280. if (ret)
  3281. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3282. ret);
  3283. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  3284. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  3285. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  3286. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3287. "qcom,rc-ep-short-channel"))
  3288. cnss_set_feature_list(plat_priv, CNSS_RC_EP_ULTRASHORT_CHANNEL_V01);
  3289. return 0;
  3290. }
  3291. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3292. {
  3293. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3294. plat_priv);
  3295. complete_all(&plat_priv->recovery_complete);
  3296. complete_all(&plat_priv->rddm_complete);
  3297. complete_all(&plat_priv->cal_complete);
  3298. complete_all(&plat_priv->power_up_complete);
  3299. complete_all(&plat_priv->daemon_connected);
  3300. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3301. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3302. del_timer(&plat_priv->fw_boot_timer);
  3303. wakeup_source_unregister(plat_priv->recovery_ws);
  3304. cnss_deinit_sol_gpio(plat_priv);
  3305. kfree(plat_priv->sram_dump);
  3306. }
  3307. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3308. {
  3309. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3310. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3311. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3312. "qcom,wlan-cbc-enabled");
  3313. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3314. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3315. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3316. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3317. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3318. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3319. * enabled by default
  3320. */
  3321. plat_priv->adsp_pc_enabled = true;
  3322. }
  3323. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3324. {
  3325. struct device *dev = &plat_priv->plat_dev->dev;
  3326. plat_priv->use_pm_domain =
  3327. of_property_read_bool(dev->of_node, "use-pm-domain");
  3328. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3329. }
  3330. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3331. {
  3332. struct device *dev = &plat_priv->plat_dev->dev;
  3333. plat_priv->set_wlaon_pwr_ctrl =
  3334. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3335. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3336. plat_priv->set_wlaon_pwr_ctrl);
  3337. }
  3338. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3339. {
  3340. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3341. "qcom,converged-dt") ||
  3342. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3343. "qcom,same-dt-multi-dev") ||
  3344. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3345. "qcom,multi-wlan-exchg"));
  3346. }
  3347. static const struct platform_device_id cnss_platform_id_table[] = {
  3348. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3349. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3350. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3351. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3352. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3353. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  3354. { .name = "qcaconv", .driver_data = 0, },
  3355. { },
  3356. };
  3357. static const struct of_device_id cnss_of_match_table[] = {
  3358. {
  3359. .compatible = "qcom,cnss",
  3360. .data = (void *)&cnss_platform_id_table[0]},
  3361. {
  3362. .compatible = "qcom,cnss-qca6290",
  3363. .data = (void *)&cnss_platform_id_table[1]},
  3364. {
  3365. .compatible = "qcom,cnss-qca6390",
  3366. .data = (void *)&cnss_platform_id_table[2]},
  3367. {
  3368. .compatible = "qcom,cnss-qca6490",
  3369. .data = (void *)&cnss_platform_id_table[3]},
  3370. {
  3371. .compatible = "qcom,cnss-kiwi",
  3372. .data = (void *)&cnss_platform_id_table[4]},
  3373. {
  3374. .compatible = "qcom,cnss-mango",
  3375. .data = (void *)&cnss_platform_id_table[5]},
  3376. {
  3377. .compatible = "qcom,cnss-qca-converged",
  3378. .data = (void *)&cnss_platform_id_table[6]},
  3379. { },
  3380. };
  3381. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3382. static inline bool
  3383. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3384. {
  3385. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3386. "use-nv-mac");
  3387. }
  3388. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3389. {
  3390. struct device_node *child;
  3391. u32 id, i;
  3392. int id_n, device_identifier_gpio, ret;
  3393. u8 gpio_value;
  3394. if (plat_priv->dt_type != CNSS_DTT_CONVERGED)
  3395. return 0;
  3396. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  3397. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  3398. if (ret) {
  3399. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  3400. return ret;
  3401. }
  3402. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3403. gpio_value = gpio_get_value(device_identifier_gpio);
  3404. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  3405. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3406. child) {
  3407. if (strcmp(child->name, "chip_cfg"))
  3408. continue;
  3409. id_n = of_property_count_u32_elems(child, "supported-ids");
  3410. if (id_n <= 0) {
  3411. cnss_pr_err("Device id is NOT set\n");
  3412. return -EINVAL;
  3413. }
  3414. for (i = 0; i < id_n; i++) {
  3415. ret = of_property_read_u32_index(child,
  3416. "supported-ids",
  3417. i, &id);
  3418. if (ret) {
  3419. cnss_pr_err("Failed to read supported ids\n");
  3420. return -EINVAL;
  3421. }
  3422. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3423. plat_priv->plat_dev->dev.of_node = child;
  3424. plat_priv->device_id = QCA6490_DEVICE_ID;
  3425. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3426. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3427. child->name, i, id);
  3428. return 0;
  3429. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3430. plat_priv->plat_dev->dev.of_node = child;
  3431. plat_priv->device_id = KIWI_DEVICE_ID;
  3432. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3433. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3434. child->name, i, id);
  3435. return 0;
  3436. }
  3437. }
  3438. }
  3439. return -EINVAL;
  3440. }
  3441. static inline u32
  3442. cnss_dt_type(struct cnss_plat_data *plat_priv)
  3443. {
  3444. bool is_converged_dt = of_property_read_bool(
  3445. plat_priv->plat_dev->dev.of_node, "qcom,converged-dt");
  3446. bool is_multi_wlan_xchg;
  3447. if (is_converged_dt)
  3448. return CNSS_DTT_CONVERGED;
  3449. is_multi_wlan_xchg = of_property_read_bool(
  3450. plat_priv->plat_dev->dev.of_node, "qcom,multi-wlan-exchg");
  3451. if (is_multi_wlan_xchg)
  3452. return CNSS_DTT_MULTIEXCHG;
  3453. return CNSS_DTT_LEGACY;
  3454. }
  3455. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  3456. {
  3457. int ret = 0;
  3458. int retry = 0;
  3459. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3460. return 0;
  3461. retry:
  3462. ret = cnss_power_on_device(plat_priv);
  3463. if (ret)
  3464. goto end;
  3465. ret = cnss_bus_init(plat_priv);
  3466. if (ret) {
  3467. if ((ret != -EPROBE_DEFER) &&
  3468. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3469. cnss_power_off_device(plat_priv);
  3470. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3471. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3472. goto retry;
  3473. }
  3474. goto power_off;
  3475. }
  3476. return 0;
  3477. power_off:
  3478. cnss_power_off_device(plat_priv);
  3479. end:
  3480. return ret;
  3481. }
  3482. int cnss_wlan_hw_enable(void)
  3483. {
  3484. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3485. int ret = 0;
  3486. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  3487. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  3488. goto register_driver;
  3489. ret = cnss_wlan_device_init(plat_priv);
  3490. if (ret) {
  3491. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state))
  3492. CNSS_ASSERT(0);
  3493. return ret;
  3494. }
  3495. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  3496. cnss_driver_event_post(plat_priv,
  3497. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3498. 0, NULL);
  3499. register_driver:
  3500. if (plat_priv->driver_ops)
  3501. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  3502. return ret;
  3503. }
  3504. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  3505. int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg)
  3506. {
  3507. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3508. int ret = 0;
  3509. if (!plat_priv)
  3510. return -ENODEV;
  3511. /* If IMS server is connected, return success without QMI send */
  3512. if (test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  3513. cnss_pr_dbg("Ignore host request as IMS server is connected");
  3514. return ret;
  3515. }
  3516. ret = cnss_wlfw_send_host_wfc_call_status(plat_priv, cfg);
  3517. return ret;
  3518. }
  3519. EXPORT_SYMBOL(cnss_set_wfc_mode);
  3520. static int cnss_probe(struct platform_device *plat_dev)
  3521. {
  3522. int ret = 0;
  3523. struct cnss_plat_data *plat_priv;
  3524. const struct of_device_id *of_id;
  3525. const struct platform_device_id *device_id;
  3526. if (cnss_get_plat_priv(plat_dev)) {
  3527. cnss_pr_err("Driver is already initialized!\n");
  3528. ret = -EEXIST;
  3529. goto out;
  3530. }
  3531. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3532. if (!of_id || !of_id->data) {
  3533. cnss_pr_err("Failed to find of match device!\n");
  3534. ret = -ENODEV;
  3535. goto out;
  3536. }
  3537. device_id = of_id->data;
  3538. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3539. GFP_KERNEL);
  3540. if (!plat_priv) {
  3541. ret = -ENOMEM;
  3542. goto out;
  3543. }
  3544. plat_priv->plat_dev = plat_dev;
  3545. plat_priv->dev_node = NULL;
  3546. plat_priv->device_id = device_id->driver_data;
  3547. plat_priv->dt_type = cnss_dt_type(plat_priv);
  3548. cnss_pr_dbg("Probing platform driver from dt type: %d\n",
  3549. plat_priv->dt_type);
  3550. plat_priv->use_fw_path_with_prefix =
  3551. cnss_use_fw_path_with_prefix(plat_priv);
  3552. ret = cnss_get_dev_cfg_node(plat_priv);
  3553. if (ret) {
  3554. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  3555. goto reset_plat_dev;
  3556. }
  3557. plat_priv->bus_type = cnss_get_bus_type(plat_priv);
  3558. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3559. plat_priv->driver_mode = CNSS_DRIVER_MODE_MAX;
  3560. cnss_set_plat_priv(plat_dev, plat_priv);
  3561. platform_set_drvdata(plat_dev, plat_priv);
  3562. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3563. INIT_LIST_HEAD(&plat_priv->clk_list);
  3564. cnss_get_pm_domain_info(plat_priv);
  3565. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3566. cnss_power_misc_params_init(plat_priv);
  3567. cnss_get_tcs_info(plat_priv);
  3568. cnss_get_cpr_info(plat_priv);
  3569. cnss_aop_mbox_init(plat_priv);
  3570. cnss_init_control_params(plat_priv);
  3571. ret = cnss_get_resources(plat_priv);
  3572. if (ret)
  3573. goto reset_ctx;
  3574. ret = cnss_register_esoc(plat_priv);
  3575. if (ret)
  3576. goto free_res;
  3577. ret = cnss_register_bus_scale(plat_priv);
  3578. if (ret)
  3579. goto unreg_esoc;
  3580. ret = cnss_create_sysfs(plat_priv);
  3581. if (ret)
  3582. goto unreg_bus_scale;
  3583. ret = cnss_event_work_init(plat_priv);
  3584. if (ret)
  3585. goto remove_sysfs;
  3586. ret = cnss_qmi_init(plat_priv);
  3587. if (ret)
  3588. goto deinit_event_work;
  3589. ret = cnss_dms_init(plat_priv);
  3590. if (ret)
  3591. goto deinit_qmi;
  3592. ret = cnss_debugfs_create(plat_priv);
  3593. if (ret)
  3594. goto deinit_dms;
  3595. ret = cnss_misc_init(plat_priv);
  3596. if (ret)
  3597. goto destroy_debugfs;
  3598. ret = cnss_wlan_hw_disable_check(plat_priv);
  3599. if (ret)
  3600. goto deinit_misc;
  3601. /* Make sure all platform related init are done before
  3602. * device power on and bus init.
  3603. */
  3604. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  3605. ret = cnss_wlan_device_init(plat_priv);
  3606. if (ret)
  3607. goto deinit_misc;
  3608. } else {
  3609. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  3610. }
  3611. cnss_register_coex_service(plat_priv);
  3612. cnss_register_ims_service(plat_priv);
  3613. ret = cnss_genl_init();
  3614. if (ret < 0)
  3615. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3616. cnss_pr_info("Platform driver probed successfully.\n");
  3617. return 0;
  3618. deinit_misc:
  3619. cnss_misc_deinit(plat_priv);
  3620. destroy_debugfs:
  3621. cnss_debugfs_destroy(plat_priv);
  3622. deinit_dms:
  3623. cnss_dms_deinit(plat_priv);
  3624. deinit_qmi:
  3625. cnss_qmi_deinit(plat_priv);
  3626. deinit_event_work:
  3627. cnss_event_work_deinit(plat_priv);
  3628. remove_sysfs:
  3629. cnss_remove_sysfs(plat_priv);
  3630. unreg_bus_scale:
  3631. cnss_unregister_bus_scale(plat_priv);
  3632. unreg_esoc:
  3633. cnss_unregister_esoc(plat_priv);
  3634. free_res:
  3635. cnss_put_resources(plat_priv);
  3636. reset_ctx:
  3637. platform_set_drvdata(plat_dev, NULL);
  3638. reset_plat_dev:
  3639. cnss_set_plat_priv(plat_dev, NULL);
  3640. out:
  3641. return ret;
  3642. }
  3643. static int cnss_remove(struct platform_device *plat_dev)
  3644. {
  3645. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3646. plat_priv->audio_iommu_domain = NULL;
  3647. cnss_genl_exit();
  3648. cnss_unregister_ims_service(plat_priv);
  3649. cnss_unregister_coex_service(plat_priv);
  3650. cnss_bus_deinit(plat_priv);
  3651. cnss_misc_deinit(plat_priv);
  3652. cnss_debugfs_destroy(plat_priv);
  3653. cnss_dms_deinit(plat_priv);
  3654. cnss_qmi_deinit(plat_priv);
  3655. cnss_event_work_deinit(plat_priv);
  3656. cnss_cancel_dms_work();
  3657. cnss_remove_sysfs(plat_priv);
  3658. cnss_unregister_bus_scale(plat_priv);
  3659. cnss_unregister_esoc(plat_priv);
  3660. cnss_put_resources(plat_priv);
  3661. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3662. mbox_free_channel(plat_priv->mbox_chan);
  3663. platform_set_drvdata(plat_dev, NULL);
  3664. plat_env = NULL;
  3665. return 0;
  3666. }
  3667. static struct platform_driver cnss_platform_driver = {
  3668. .probe = cnss_probe,
  3669. .remove = cnss_remove,
  3670. .driver = {
  3671. .name = "cnss2",
  3672. .of_match_table = cnss_of_match_table,
  3673. #ifdef CONFIG_CNSS_ASYNC
  3674. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3675. #endif
  3676. },
  3677. };
  3678. static bool cnss_check_compatible_node(void)
  3679. {
  3680. struct device_node *dn = NULL;
  3681. for_each_matching_node(dn, cnss_of_match_table) {
  3682. if (of_device_is_available(dn)) {
  3683. cnss_allow_driver_loading = true;
  3684. return true;
  3685. }
  3686. }
  3687. return false;
  3688. }
  3689. /**
  3690. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3691. *
  3692. * Valid device tree node means a node with "compatible" property from the
  3693. * device match table and "status" property is not disabled.
  3694. *
  3695. * Return: true if valid device tree node found, false if not found
  3696. */
  3697. static bool cnss_is_valid_dt_node_found(void)
  3698. {
  3699. struct device_node *dn = NULL;
  3700. for_each_matching_node(dn, cnss_of_match_table) {
  3701. if (of_device_is_available(dn))
  3702. break;
  3703. }
  3704. if (dn)
  3705. return true;
  3706. return false;
  3707. }
  3708. static int __init cnss_initialize(void)
  3709. {
  3710. int ret = 0;
  3711. if (!cnss_is_valid_dt_node_found())
  3712. return -ENODEV;
  3713. if (!cnss_check_compatible_node())
  3714. return ret;
  3715. cnss_debug_init();
  3716. ret = platform_driver_register(&cnss_platform_driver);
  3717. if (ret)
  3718. cnss_debug_deinit();
  3719. return ret;
  3720. }
  3721. static void __exit cnss_exit(void)
  3722. {
  3723. platform_driver_unregister(&cnss_platform_driver);
  3724. cnss_debug_deinit();
  3725. }
  3726. module_init(cnss_initialize);
  3727. module_exit(cnss_exit);
  3728. MODULE_LICENSE("GPL v2");
  3729. MODULE_DESCRIPTION("CNSS2 Platform Driver");