Aravind Venkateswaran 664040053b disp: pll: fix divider clock flags for DSI PLL clocks ...

The divider clocks in the DSI PLL are 1-based and can accept
a value of 0. Set the flags accordingly in the PLL driver.

CRs-Fixed: 2433864
Change-Id: I82361ae3e2119f9e1922153bd5aba6354e8c5442
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>

2019-05-01 12:53:51 -07:00

config

makefile: remove make export <all variables> instances

2019-04-29 13:25:09 -07:00

msm

Merge "disp: msm: sde: handle cont-splash & check only rm reserve"

2019-04-30 16:37:22 -07:00

pll

disp: pll: fix divider clock flags for DSI PLL clocks

2019-05-01 12:53:51 -07:00

rotator

disp: add shmbridge support in sde and rotator

2019-04-19 14:45:55 -07:00

Makefile

makefile: remove make export <all variables> instances

2019-04-29 13:25:09 -07:00

NOTICE

Display drivers kernel project initial snapshot

2019-04-14 22:20:59 -07:00

説明

説明が提供されていません

226 MiB

言語

C 98.7%

C++ 0.9%

Makefile 0.3%

Starlark 0.1%