wcd938x.c 77 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. enum {
  29. WCD9380 = 0,
  30. WCD9385,
  31. WCD9385FX,
  32. };
  33. enum {
  34. CODEC_TX = 0,
  35. CODEC_RX,
  36. };
  37. enum {
  38. ALLOW_BUCK_DISABLE,
  39. HPH_COMP_DELAY,
  40. HPH_PA_DELAY,
  41. };
  42. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  43. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  44. static int wcd938x_handle_post_irq(void *data);
  45. static int wcd938x_reset(struct device *dev);
  46. static int wcd938x_reset_low(struct device *dev);
  47. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  48. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  49. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  50. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  51. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  52. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  53. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  54. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  55. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  56. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  57. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  58. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  59. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  60. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  61. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  62. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  63. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  64. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  65. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  66. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  68. };
  69. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  70. .name = "wcd938x",
  71. .irqs = wcd938x_irqs,
  72. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  73. .num_regs = 3,
  74. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  75. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  76. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  77. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  78. .use_ack = 1,
  79. .runtime_pm = true,
  80. .handle_post_irq = wcd938x_handle_post_irq,
  81. .irq_drv_data = NULL,
  82. };
  83. static int wcd938x_handle_post_irq(void *data)
  84. {
  85. struct wcd938x_priv *wcd938x = data;
  86. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  87. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  88. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  89. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  90. wcd938x->tx_swr_dev->slave_irq_pending =
  91. ((sts1 || sts2 || sts3) ? true : false);
  92. return IRQ_HANDLED;
  93. }
  94. static int wcd938x_init_reg(struct snd_soc_component *component)
  95. {
  96. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  97. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  98. /* 1 msec delay as per HW requirement */
  99. usleep_range(1000, 1010);
  100. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  101. /* 1 msec delay as per HW requirement */
  102. usleep_range(1000, 1010);
  103. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  104. 0x10, 0x00);
  105. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  106. 0xF0, 0x80);
  107. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  108. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  109. /* 10 msec delay as per HW requirement */
  110. usleep_range(10000, 10010);
  111. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  112. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  113. 0xFF, 0x3A);
  114. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  115. 0x0F, 0x02);
  116. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  117. 0x01, 0x01);
  118. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  119. 0x01, 0x01);
  120. return 0;
  121. }
  122. static int wcd938x_set_port_params(struct snd_soc_component *component,
  123. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  124. u8 *ch_mask, u32 *ch_rate,
  125. u8 *port_type, u8 path)
  126. {
  127. int i, j;
  128. u8 num_ports;
  129. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  130. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  131. switch (path) {
  132. case CODEC_RX:
  133. map = &wcd938x->rx_port_mapping;
  134. num_ports = wcd938x->num_rx_ports;
  135. break;
  136. case CODEC_TX:
  137. map = &wcd938x->tx_port_mapping;
  138. num_ports = wcd938x->num_tx_ports;
  139. break;
  140. }
  141. for (i = 0; i <= num_ports; i++) {
  142. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  143. if ((*map)[i][j].slave_port_type == slv_prt_type)
  144. goto found;
  145. }
  146. }
  147. found:
  148. if (i > num_ports || j == MAX_CH_PER_PORT) {
  149. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  150. __func__, slv_prt_type);
  151. return -EINVAL;
  152. }
  153. *port_id = i;
  154. *num_ch = (*map)[i][j].num_ch;
  155. *ch_mask = (*map)[i][j].ch_mask;
  156. *ch_rate = (*map)[i][j].ch_rate;
  157. *port_type = (*map)[i][j].master_port_type;
  158. return 0;
  159. }
  160. static int wcd938x_parse_port_mapping(struct device *dev,
  161. char *prop, u8 path)
  162. {
  163. u32 *dt_array, map_size, map_length;
  164. u32 port_num, ch_mask, ch_rate, old_port_num = 0;
  165. u32 slave_port_type, master_port_type;
  166. u32 i, ch_iter = 0;
  167. int ret = 0;
  168. u8 *num_ports;
  169. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  170. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  171. switch (path) {
  172. case CODEC_RX:
  173. map = &wcd938x->rx_port_mapping;
  174. num_ports = &wcd938x->num_rx_ports;
  175. break;
  176. case CODEC_TX:
  177. map = &wcd938x->tx_port_mapping;
  178. num_ports = &wcd938x->num_tx_ports;
  179. break;
  180. }
  181. if (!of_find_property(dev->of_node, prop,
  182. &map_size)) {
  183. dev_err(dev, "missing port mapping prop %s\n", prop);
  184. ret = -EINVAL;
  185. goto err_port_map;
  186. }
  187. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  188. dt_array = kzalloc(map_size, GFP_KERNEL);
  189. if (!dt_array) {
  190. ret = -ENOMEM;
  191. goto err_alloc;
  192. }
  193. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  194. NUM_SWRS_DT_PARAMS * map_length);
  195. if (ret) {
  196. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  197. __func__, prop);
  198. goto err_pdata_fail;
  199. }
  200. for (i = 0; i < map_length; i++) {
  201. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  202. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  203. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  204. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  205. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  206. if (port_num != old_port_num)
  207. ch_iter = 0;
  208. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  209. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  210. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  211. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  212. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  213. old_port_num = port_num;
  214. }
  215. *num_ports = port_num;
  216. kfree(dt_array);
  217. return 0;
  218. err_pdata_fail:
  219. kfree(dt_array);
  220. err_alloc:
  221. err_port_map:
  222. return ret;
  223. }
  224. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  225. u8 slv_port_type, u8 enable)
  226. {
  227. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  228. u8 port_id, num_ch, ch_mask, port_type;
  229. u32 ch_rate;
  230. u8 num_port = 1;
  231. int ret = 0;
  232. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  233. &num_ch, &ch_mask, &ch_rate,
  234. &port_type, CODEC_TX);
  235. if (ret)
  236. return ret;
  237. if (enable)
  238. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  239. num_port, &ch_mask, &ch_rate,
  240. &num_ch, &port_type);
  241. else
  242. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  243. num_port, &ch_mask, &port_type);
  244. return ret;
  245. }
  246. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  247. u8 slv_port_type, u8 enable)
  248. {
  249. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  250. u8 port_id, num_ch, ch_mask, port_type;
  251. u32 ch_rate;
  252. u8 num_port = 1;
  253. int ret = 0;
  254. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  255. &num_ch, &ch_mask, &ch_rate,
  256. &port_type, CODEC_RX);
  257. if (ret)
  258. return ret;
  259. if (enable)
  260. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  261. num_port, &ch_mask, &ch_rate,
  262. &num_ch, &port_type);
  263. else
  264. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  265. num_port, &ch_mask, &port_type);
  266. return ret;
  267. }
  268. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  269. {
  270. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  271. if (wcd938x->rx_clk_cnt == 0) {
  272. snd_soc_component_update_bits(component,
  273. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  274. snd_soc_component_update_bits(component,
  275. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  276. snd_soc_component_update_bits(component,
  277. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  278. snd_soc_component_update_bits(component,
  279. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  280. snd_soc_component_update_bits(component,
  281. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  282. snd_soc_component_update_bits(component,
  283. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  284. snd_soc_component_update_bits(component,
  285. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  286. }
  287. wcd938x->rx_clk_cnt++;
  288. return 0;
  289. }
  290. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  291. {
  292. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  293. wcd938x->rx_clk_cnt--;
  294. if (wcd938x->rx_clk_cnt == 0) {
  295. snd_soc_component_update_bits(component,
  296. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  297. snd_soc_component_update_bits(component,
  298. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  299. snd_soc_component_update_bits(component,
  300. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  301. snd_soc_component_update_bits(component,
  302. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  303. snd_soc_component_update_bits(component,
  304. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  305. }
  306. return 0;
  307. }
  308. /*
  309. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  310. * @component: handle to snd_soc_component *
  311. *
  312. * return wcd938x_mbhc handle or error code in case of failure
  313. */
  314. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  315. {
  316. struct wcd938x_priv *wcd938x;
  317. if (!component) {
  318. pr_err("%s: Invalid params, NULL component\n", __func__);
  319. return NULL;
  320. }
  321. wcd938x = snd_soc_component_get_drvdata(component);
  322. if (!wcd938x) {
  323. pr_err("%s: wcd938x is NULL\n", __func__);
  324. return NULL;
  325. }
  326. return wcd938x->mbhc;
  327. }
  328. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  329. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  330. struct snd_kcontrol *kcontrol,
  331. int event)
  332. {
  333. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  334. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  335. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  336. w->name, event);
  337. switch (event) {
  338. case SND_SOC_DAPM_PRE_PMU:
  339. wcd938x_rx_clk_enable(component);
  340. snd_soc_component_update_bits(component,
  341. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  342. snd_soc_component_update_bits(component,
  343. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  344. snd_soc_component_update_bits(component,
  345. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  346. break;
  347. case SND_SOC_DAPM_POST_PMU:
  348. snd_soc_component_update_bits(component,
  349. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  350. if (wcd938x->comp1_enable) {
  351. snd_soc_component_update_bits(component,
  352. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  353. /* 5msec compander delay as per HW requirement */
  354. if (!wcd938x->comp2_enable ||
  355. (snd_soc_component_read32(component,
  356. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  357. usleep_range(5000, 5010);
  358. snd_soc_component_update_bits(component,
  359. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  360. } else {
  361. snd_soc_component_update_bits(component,
  362. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  363. 0x02, 0x00);
  364. snd_soc_component_update_bits(component,
  365. WCD938X_HPH_L_EN, 0x20, 0x20);
  366. }
  367. break;
  368. case SND_SOC_DAPM_POST_PMD:
  369. snd_soc_component_update_bits(component,
  370. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  371. 0x0F, 0x01);
  372. break;
  373. }
  374. return 0;
  375. }
  376. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  377. struct snd_kcontrol *kcontrol,
  378. int event)
  379. {
  380. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  381. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  382. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  383. w->name, event);
  384. switch (event) {
  385. case SND_SOC_DAPM_PRE_PMU:
  386. wcd938x_rx_clk_enable(component);
  387. snd_soc_component_update_bits(component,
  388. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  389. snd_soc_component_update_bits(component,
  390. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  391. snd_soc_component_update_bits(component,
  392. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  393. break;
  394. case SND_SOC_DAPM_POST_PMU:
  395. snd_soc_component_update_bits(component,
  396. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  397. if (wcd938x->comp2_enable) {
  398. snd_soc_component_update_bits(component,
  399. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  400. /* 5msec compander delay as per HW requirement */
  401. if (!wcd938x->comp1_enable ||
  402. (snd_soc_component_read32(component,
  403. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  404. usleep_range(5000, 5010);
  405. snd_soc_component_update_bits(component,
  406. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  407. } else {
  408. snd_soc_component_update_bits(component,
  409. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  410. 0x01, 0x00);
  411. snd_soc_component_update_bits(component,
  412. WCD938X_HPH_R_EN, 0x20, 0x20);
  413. }
  414. break;
  415. case SND_SOC_DAPM_POST_PMD:
  416. snd_soc_component_update_bits(component,
  417. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  418. 0x0F, 0x01);
  419. break;
  420. }
  421. return 0;
  422. }
  423. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  424. struct snd_kcontrol *kcontrol,
  425. int event)
  426. {
  427. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  428. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  429. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  430. w->name, event);
  431. switch (event) {
  432. case SND_SOC_DAPM_PRE_PMU:
  433. wcd938x_rx_clk_enable(component);
  434. snd_soc_component_update_bits(component,
  435. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  436. snd_soc_component_update_bits(component,
  437. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  440. /* 5 msec delay as per HW requirement */
  441. usleep_range(5000, 5010);
  442. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  443. WCD_CLSH_EVENT_PRE_DAC,
  444. WCD_CLSH_STATE_EAR,
  445. wcd938x->hph_mode);
  446. break;
  447. case SND_SOC_DAPM_POST_PMD:
  448. break;
  449. };
  450. return 0;
  451. }
  452. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  453. struct snd_kcontrol *kcontrol,
  454. int event)
  455. {
  456. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  457. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  458. int ret = 0;
  459. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  460. w->name, event);
  461. switch (event) {
  462. case SND_SOC_DAPM_PRE_PMU:
  463. wcd938x_rx_clk_enable(component);
  464. snd_soc_component_update_bits(component,
  465. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  466. snd_soc_component_update_bits(component,
  467. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  468. snd_soc_component_update_bits(component,
  469. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  470. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  471. WCD_CLSH_EVENT_PRE_DAC,
  472. WCD_CLSH_STATE_AUX,
  473. wcd938x->hph_mode);
  474. break;
  475. case SND_SOC_DAPM_POST_PMD:
  476. wcd938x_rx_clk_disable(component);
  477. snd_soc_component_update_bits(component,
  478. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  479. break;
  480. };
  481. return ret;
  482. }
  483. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  484. struct snd_kcontrol *kcontrol,
  485. int event)
  486. {
  487. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  488. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  489. int ret = 0;
  490. int hph_mode = wcd938x->hph_mode;
  491. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  492. w->name, event);
  493. switch (event) {
  494. case SND_SOC_DAPM_PRE_PMU:
  495. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  496. wcd938x->rx_swr_dev->dev_num,
  497. true);
  498. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  499. WCD_CLSH_EVENT_PRE_DAC,
  500. WCD_CLSH_STATE_HPHR,
  501. hph_mode);
  502. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  503. 0x10, 0x10);
  504. /* 100 usec delay as per HW requirement */
  505. usleep_range(100, 110);
  506. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  507. break;
  508. case SND_SOC_DAPM_POST_PMU:
  509. /*
  510. * 7ms sleep is required if compander is enabled as per
  511. * HW requirement. If compander is disabled, then
  512. * 20ms delay is required.
  513. */
  514. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  515. if (!wcd938x->comp2_enable)
  516. usleep_range(20000, 20100);
  517. else
  518. usleep_range(7000, 7100);
  519. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  520. }
  521. snd_soc_component_update_bits(component,
  522. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  523. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  524. snd_soc_component_update_bits(component,
  525. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  526. if (wcd938x->update_wcd_event)
  527. wcd938x->update_wcd_event(wcd938x->handle,
  528. WCD_BOLERO_EVT_RX_MUTE,
  529. (WCD_RX2 << 0x10));
  530. break;
  531. case SND_SOC_DAPM_PRE_PMD:
  532. if (wcd938x->update_wcd_event)
  533. wcd938x->update_wcd_event(wcd938x->handle,
  534. WCD_BOLERO_EVT_RX_MUTE,
  535. (WCD_RX2 << 0x10 | 0x1));
  536. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  537. WCD_EVENT_PRE_HPHR_PA_OFF,
  538. &wcd938x->mbhc->wcd_mbhc);
  539. break;
  540. case SND_SOC_DAPM_POST_PMD:
  541. /* 7 msec delay as per HW requirement */
  542. usleep_range(7000, 7010);
  543. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  544. WCD_EVENT_POST_HPHR_PA_OFF,
  545. &wcd938x->mbhc->wcd_mbhc);
  546. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  547. 0x10, 0x00);
  548. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  549. WCD_CLSH_EVENT_POST_PA,
  550. WCD_CLSH_STATE_HPHR,
  551. hph_mode);
  552. break;
  553. };
  554. return ret;
  555. }
  556. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  557. struct snd_kcontrol *kcontrol,
  558. int event)
  559. {
  560. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  561. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  562. int ret = 0;
  563. int hph_mode = wcd938x->hph_mode;
  564. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  565. w->name, event);
  566. switch (event) {
  567. case SND_SOC_DAPM_PRE_PMU:
  568. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  569. wcd938x->rx_swr_dev->dev_num,
  570. true);
  571. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  572. WCD_CLSH_EVENT_PRE_DAC,
  573. WCD_CLSH_STATE_HPHL,
  574. hph_mode);
  575. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  576. 0x20, 0x20);
  577. /* 100 usec delay as per HW requirement */
  578. usleep_range(100, 110);
  579. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  580. break;
  581. case SND_SOC_DAPM_POST_PMU:
  582. /*
  583. * 7ms sleep is required if compander is enabled as per
  584. * HW requirement. If compander is disabled, then
  585. * 20ms delay is required.
  586. */
  587. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  588. if (!wcd938x->comp1_enable)
  589. usleep_range(20000, 20100);
  590. else
  591. usleep_range(7000, 7100);
  592. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  593. }
  594. snd_soc_component_update_bits(component,
  595. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  596. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  597. snd_soc_component_update_bits(component,
  598. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  599. if (wcd938x->update_wcd_event)
  600. wcd938x->update_wcd_event(wcd938x->handle,
  601. WCD_BOLERO_EVT_RX_MUTE,
  602. (WCD_RX1 << 0x10));
  603. break;
  604. case SND_SOC_DAPM_PRE_PMD:
  605. if (wcd938x->update_wcd_event)
  606. wcd938x->update_wcd_event(wcd938x->handle,
  607. WCD_BOLERO_EVT_RX_MUTE,
  608. (WCD_RX1 << 0x10 | 0x1));
  609. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  610. WCD_EVENT_PRE_HPHL_PA_OFF,
  611. &wcd938x->mbhc->wcd_mbhc);
  612. break;
  613. case SND_SOC_DAPM_POST_PMD:
  614. /* 7 msec delay as per HW requirement */
  615. usleep_range(7000, 7010);
  616. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  617. WCD_EVENT_POST_HPHL_PA_OFF,
  618. &wcd938x->mbhc->wcd_mbhc);
  619. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  620. 0x20, 0x00);
  621. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  622. WCD_CLSH_EVENT_POST_PA,
  623. WCD_CLSH_STATE_HPHL,
  624. hph_mode);
  625. break;
  626. };
  627. return ret;
  628. }
  629. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  630. struct snd_kcontrol *kcontrol,
  631. int event)
  632. {
  633. struct snd_soc_component *component =
  634. snd_soc_dapm_to_component(w->dapm);
  635. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  636. int hph_mode = wcd938x->hph_mode;
  637. int ret = 0;
  638. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  639. w->name, event);
  640. switch (event) {
  641. case SND_SOC_DAPM_PRE_PMU:
  642. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  643. wcd938x->rx_swr_dev->dev_num,
  644. true);
  645. break;
  646. case SND_SOC_DAPM_POST_PMU:
  647. /* 1 msec delay as per HW requirement */
  648. usleep_range(1000, 1010);
  649. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  650. snd_soc_component_update_bits(component,
  651. WCD938X_ANA_RX_SUPPLIES,
  652. 0x20, 0x20);
  653. if (wcd938x->update_wcd_event)
  654. wcd938x->update_wcd_event(wcd938x->handle,
  655. WCD_BOLERO_EVT_RX_MUTE,
  656. (WCD_RX3 << 0x10));
  657. break;
  658. case SND_SOC_DAPM_PRE_PMD:
  659. if (wcd938x->update_wcd_event)
  660. wcd938x->update_wcd_event(wcd938x->handle,
  661. WCD_BOLERO_EVT_RX_MUTE,
  662. (WCD_RX3 << 0x10 | 0x1));
  663. break;
  664. case SND_SOC_DAPM_POST_PMD:
  665. /* 1 msec delay as per HW requirement */
  666. usleep_range(1000, 1010);
  667. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  668. WCD_CLSH_EVENT_POST_PA,
  669. WCD_CLSH_STATE_AUX,
  670. hph_mode);
  671. break;
  672. };
  673. return ret;
  674. }
  675. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  676. struct snd_kcontrol *kcontrol,
  677. int event)
  678. {
  679. struct snd_soc_component *component =
  680. snd_soc_dapm_to_component(w->dapm);
  681. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  682. int hph_mode = wcd938x->hph_mode;
  683. int ret = 0;
  684. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  685. w->name, event);
  686. switch (event) {
  687. case SND_SOC_DAPM_PRE_PMU:
  688. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  689. wcd938x->rx_swr_dev->dev_num,
  690. true);
  691. break;
  692. case SND_SOC_DAPM_POST_PMU:
  693. /* 6 msec delay as per HW requirement */
  694. usleep_range(6000, 6010);
  695. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  696. snd_soc_component_update_bits(component,
  697. WCD938X_ANA_RX_SUPPLIES,
  698. 0x02, 0x02);
  699. if (wcd938x->update_wcd_event)
  700. wcd938x->update_wcd_event(wcd938x->handle,
  701. WCD_BOLERO_EVT_RX_MUTE,
  702. (WCD_RX1 << 0x10));
  703. break;
  704. case SND_SOC_DAPM_PRE_PMD:
  705. if (wcd938x->update_wcd_event)
  706. wcd938x->update_wcd_event(wcd938x->handle,
  707. WCD_BOLERO_EVT_RX_MUTE,
  708. (WCD_RX1 << 0x10 | 0x1));
  709. break;
  710. case SND_SOC_DAPM_POST_PMD:
  711. /* 7 msec delay as per HW requirement */
  712. usleep_range(7000, 7010);
  713. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  714. WCD_CLSH_EVENT_POST_PA,
  715. WCD_CLSH_STATE_EAR,
  716. hph_mode);
  717. break;
  718. };
  719. return ret;
  720. }
  721. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  722. struct snd_kcontrol *kcontrol,
  723. int event)
  724. {
  725. struct snd_soc_component *component =
  726. snd_soc_dapm_to_component(w->dapm);
  727. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  728. int mode = wcd938x->hph_mode;
  729. int ret = 0;
  730. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  731. w->name, event);
  732. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  733. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  734. wcd938x_rx_connect_port(component, CLSH,
  735. SND_SOC_DAPM_EVENT_ON(event));
  736. }
  737. if (SND_SOC_DAPM_EVENT_OFF(event))
  738. ret = swr_slvdev_datapath_control(
  739. wcd938x->rx_swr_dev,
  740. wcd938x->rx_swr_dev->dev_num,
  741. false);
  742. return ret;
  743. }
  744. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  745. struct snd_kcontrol *kcontrol,
  746. int event)
  747. {
  748. struct snd_soc_component *component =
  749. snd_soc_dapm_to_component(w->dapm);
  750. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  751. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  752. w->name, event);
  753. switch (event) {
  754. case SND_SOC_DAPM_PRE_PMU:
  755. wcd938x_rx_connect_port(component, HPH_L, true);
  756. if (wcd938x->comp1_enable)
  757. wcd938x_rx_connect_port(component, COMP_L, true);
  758. break;
  759. case SND_SOC_DAPM_POST_PMD:
  760. wcd938x_rx_connect_port(component, HPH_L, false);
  761. if (wcd938x->comp1_enable)
  762. wcd938x_rx_connect_port(component, COMP_L, false);
  763. wcd938x_rx_clk_disable(component);
  764. snd_soc_component_update_bits(component,
  765. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  766. 0x01, 0x00);
  767. break;
  768. };
  769. return 0;
  770. }
  771. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  772. struct snd_kcontrol *kcontrol, int event)
  773. {
  774. struct snd_soc_component *component =
  775. snd_soc_dapm_to_component(w->dapm);
  776. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  777. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  778. w->name, event);
  779. switch (event) {
  780. case SND_SOC_DAPM_PRE_PMU:
  781. wcd938x_rx_connect_port(component, HPH_R, true);
  782. if (wcd938x->comp2_enable)
  783. wcd938x_rx_connect_port(component, COMP_R, true);
  784. break;
  785. case SND_SOC_DAPM_POST_PMD:
  786. wcd938x_rx_connect_port(component, HPH_R, false);
  787. if (wcd938x->comp2_enable)
  788. wcd938x_rx_connect_port(component, COMP_R, false);
  789. wcd938x_rx_clk_disable(component);
  790. snd_soc_component_update_bits(component,
  791. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  792. 0x02, 0x00);
  793. break;
  794. };
  795. return 0;
  796. }
  797. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  798. struct snd_kcontrol *kcontrol,
  799. int event)
  800. {
  801. struct snd_soc_component *component =
  802. snd_soc_dapm_to_component(w->dapm);
  803. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  804. w->name, event);
  805. switch (event) {
  806. case SND_SOC_DAPM_PRE_PMU:
  807. wcd938x_rx_connect_port(component, LO, true);
  808. break;
  809. case SND_SOC_DAPM_POST_PMD:
  810. wcd938x_rx_connect_port(component, LO, false);
  811. /* 6 msec delay as per HW requirement */
  812. usleep_range(6000, 6010);
  813. wcd938x_rx_clk_disable(component);
  814. snd_soc_component_update_bits(component,
  815. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  816. break;
  817. }
  818. return 0;
  819. }
  820. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  821. struct snd_kcontrol *kcontrol,
  822. int event)
  823. {
  824. struct snd_soc_component *component =
  825. snd_soc_dapm_to_component(w->dapm);
  826. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  827. u16 dmic_clk_reg;
  828. s32 *dmic_clk_cnt;
  829. unsigned int dmic;
  830. char *wname;
  831. int ret = 0;
  832. wname = strpbrk(w->name, "012345");
  833. if (!wname) {
  834. dev_err(component->dev, "%s: widget not found\n", __func__);
  835. return -EINVAL;
  836. }
  837. ret = kstrtouint(wname, 10, &dmic);
  838. if (ret < 0) {
  839. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  840. __func__);
  841. return -EINVAL;
  842. }
  843. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  844. w->name, event);
  845. switch (dmic) {
  846. case 0:
  847. case 1:
  848. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  849. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_CTL;
  850. break;
  851. case 2:
  852. case 3:
  853. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  854. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  855. break;
  856. case 4:
  857. case 5:
  858. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  859. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  860. break;
  861. default:
  862. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  863. __func__);
  864. return -EINVAL;
  865. };
  866. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  867. __func__, event, dmic, *dmic_clk_cnt);
  868. switch (event) {
  869. case SND_SOC_DAPM_PRE_PMU:
  870. snd_soc_component_update_bits(component,
  871. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  872. snd_soc_component_update_bits(component,
  873. dmic_clk_reg, 0x07, 0x02);
  874. snd_soc_component_update_bits(component,
  875. dmic_clk_reg, 0x08, 0x08);
  876. snd_soc_component_update_bits(component,
  877. dmic_clk_reg, 0x70, 0x20);
  878. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  879. break;
  880. case SND_SOC_DAPM_POST_PMD:
  881. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  882. break;
  883. };
  884. return 0;
  885. }
  886. /*
  887. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  888. * @micb_mv: micbias in mv
  889. *
  890. * return register value converted
  891. */
  892. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  893. {
  894. /* min micbias voltage is 1V and maximum is 2.85V */
  895. if (micb_mv < 1000 || micb_mv > 2850) {
  896. pr_err("%s: unsupported micbias voltage\n", __func__);
  897. return -EINVAL;
  898. }
  899. return (micb_mv - 1000) / 50;
  900. }
  901. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  902. /*
  903. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  904. * @component: handle to snd_soc_component *
  905. * @req_volt: micbias voltage to be set
  906. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  907. *
  908. * return 0 if adjustment is success or error code in case of failure
  909. */
  910. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  911. int req_volt, int micb_num)
  912. {
  913. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  914. int cur_vout_ctl, req_vout_ctl;
  915. int micb_reg, micb_val, micb_en;
  916. int ret = 0;
  917. switch (micb_num) {
  918. case MIC_BIAS_1:
  919. micb_reg = WCD938X_ANA_MICB1;
  920. break;
  921. case MIC_BIAS_2:
  922. micb_reg = WCD938X_ANA_MICB2;
  923. break;
  924. case MIC_BIAS_3:
  925. micb_reg = WCD938X_ANA_MICB3;
  926. break;
  927. case MIC_BIAS_4:
  928. micb_reg = WCD938X_ANA_MICB4;
  929. break;
  930. default:
  931. return -EINVAL;
  932. }
  933. mutex_lock(&wcd938x->micb_lock);
  934. /*
  935. * If requested micbias voltage is same as current micbias
  936. * voltage, then just return. Otherwise, adjust voltage as
  937. * per requested value. If micbias is already enabled, then
  938. * to avoid slow micbias ramp-up or down enable pull-up
  939. * momentarily, change the micbias value and then re-enable
  940. * micbias.
  941. */
  942. micb_val = snd_soc_component_read32(component, micb_reg);
  943. micb_en = (micb_val & 0xC0) >> 6;
  944. cur_vout_ctl = micb_val & 0x3F;
  945. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  946. if (req_vout_ctl < 0) {
  947. ret = -EINVAL;
  948. goto exit;
  949. }
  950. if (cur_vout_ctl == req_vout_ctl) {
  951. ret = 0;
  952. goto exit;
  953. }
  954. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  955. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  956. req_volt, micb_en);
  957. if (micb_en == 0x1)
  958. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  959. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  960. if (micb_en == 0x1) {
  961. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  962. /*
  963. * Add 2ms delay as per HW requirement after enabling
  964. * micbias
  965. */
  966. usleep_range(2000, 2100);
  967. }
  968. exit:
  969. mutex_unlock(&wcd938x->micb_lock);
  970. return ret;
  971. }
  972. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  973. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  974. struct snd_kcontrol *kcontrol,
  975. int event)
  976. {
  977. struct snd_soc_component *component =
  978. snd_soc_dapm_to_component(w->dapm);
  979. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  980. int ret = 0;
  981. switch (event) {
  982. case SND_SOC_DAPM_PRE_PMU:
  983. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  984. wcd938x->tx_swr_dev->dev_num,
  985. true);
  986. break;
  987. case SND_SOC_DAPM_POST_PMD:
  988. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  989. wcd938x->tx_swr_dev->dev_num,
  990. false);
  991. break;
  992. };
  993. return ret;
  994. }
  995. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  996. struct snd_kcontrol *kcontrol,
  997. int event){
  998. struct snd_soc_component *component =
  999. snd_soc_dapm_to_component(w->dapm);
  1000. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1001. w->name, event);
  1002. switch (event) {
  1003. case SND_SOC_DAPM_PRE_PMU:
  1004. snd_soc_component_update_bits(component,
  1005. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1006. snd_soc_component_update_bits(component,
  1007. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1008. snd_soc_component_update_bits(component,
  1009. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1010. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1011. break;
  1012. case SND_SOC_DAPM_POST_PMD:
  1013. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1014. snd_soc_component_update_bits(component,
  1015. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1016. break;
  1017. };
  1018. return 0;
  1019. }
  1020. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1021. struct snd_kcontrol *kcontrol, int event)
  1022. {
  1023. struct snd_soc_component *component =
  1024. snd_soc_dapm_to_component(w->dapm);
  1025. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1026. w->name, event);
  1027. switch (event) {
  1028. case SND_SOC_DAPM_PRE_PMU:
  1029. snd_soc_component_update_bits(component,
  1030. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1031. snd_soc_component_update_bits(component,
  1032. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1033. snd_soc_component_update_bits(component,
  1034. WCD938X_ANA_TX_CH2, 0x40, 0x40);
  1035. snd_soc_component_update_bits(component,
  1036. WCD938X_ANA_TX_CH2, 0x20, 0x20);
  1037. snd_soc_component_update_bits(component,
  1038. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1039. snd_soc_component_update_bits(component,
  1040. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1041. snd_soc_component_update_bits(component,
  1042. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1043. snd_soc_component_update_bits(component,
  1044. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1045. snd_soc_component_update_bits(component,
  1046. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1047. break;
  1048. case SND_SOC_DAPM_POST_PMD:
  1049. snd_soc_component_update_bits(component,
  1050. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1051. snd_soc_component_update_bits(component,
  1052. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1053. snd_soc_component_update_bits(component,
  1054. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1055. snd_soc_component_update_bits(component,
  1056. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1057. snd_soc_component_update_bits(component,
  1058. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1059. break;
  1060. };
  1061. return 0;
  1062. }
  1063. int wcd938x_micbias_control(struct snd_soc_component *component,
  1064. int micb_num, int req, bool is_dapm)
  1065. {
  1066. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1067. int micb_index = micb_num - 1;
  1068. u16 micb_reg;
  1069. int pre_off_event = 0, post_off_event = 0;
  1070. int post_on_event = 0, post_dapm_off = 0;
  1071. int post_dapm_on = 0;
  1072. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1073. dev_err(component->dev,
  1074. "%s: Invalid micbias index, micb_ind:%d\n",
  1075. __func__, micb_index);
  1076. return -EINVAL;
  1077. }
  1078. switch (micb_num) {
  1079. case MIC_BIAS_1:
  1080. micb_reg = WCD938X_ANA_MICB1;
  1081. break;
  1082. case MIC_BIAS_2:
  1083. micb_reg = WCD938X_ANA_MICB2;
  1084. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1085. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1086. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1087. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1088. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1089. break;
  1090. case MIC_BIAS_3:
  1091. micb_reg = WCD938X_ANA_MICB3;
  1092. break;
  1093. case MIC_BIAS_4:
  1094. micb_reg = WCD938X_ANA_MICB4;
  1095. break;
  1096. default:
  1097. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1098. __func__, micb_num);
  1099. return -EINVAL;
  1100. };
  1101. mutex_lock(&wcd938x->micb_lock);
  1102. switch (req) {
  1103. case MICB_PULLUP_ENABLE:
  1104. wcd938x->pullup_ref[micb_index]++;
  1105. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1106. (wcd938x->micb_ref[micb_index] == 0))
  1107. snd_soc_component_update_bits(component, micb_reg,
  1108. 0xC0, 0x80);
  1109. break;
  1110. case MICB_PULLUP_DISABLE:
  1111. if (wcd938x->pullup_ref[micb_index] > 0)
  1112. wcd938x->pullup_ref[micb_index]--;
  1113. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1114. (wcd938x->micb_ref[micb_index] == 0))
  1115. snd_soc_component_update_bits(component, micb_reg,
  1116. 0xC0, 0x00);
  1117. break;
  1118. case MICB_ENABLE:
  1119. wcd938x->micb_ref[micb_index]++;
  1120. if (wcd938x->micb_ref[micb_index] == 1) {
  1121. snd_soc_component_update_bits(component,
  1122. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1123. snd_soc_component_update_bits(component,
  1124. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1125. snd_soc_component_update_bits(component,
  1126. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1127. snd_soc_component_update_bits(component,
  1128. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1129. snd_soc_component_update_bits(component,
  1130. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1131. snd_soc_component_update_bits(component,
  1132. micb_reg, 0xC0, 0x40);
  1133. if (post_on_event)
  1134. blocking_notifier_call_chain(
  1135. &wcd938x->mbhc->notifier,
  1136. post_on_event,
  1137. &wcd938x->mbhc->wcd_mbhc);
  1138. }
  1139. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1140. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1141. post_dapm_on,
  1142. &wcd938x->mbhc->wcd_mbhc);
  1143. break;
  1144. case MICB_DISABLE:
  1145. if (wcd938x->micb_ref[micb_index] > 0)
  1146. wcd938x->micb_ref[micb_index]--;
  1147. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1148. (wcd938x->pullup_ref[micb_index] > 0))
  1149. snd_soc_component_update_bits(component, micb_reg,
  1150. 0xC0, 0x80);
  1151. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1152. (wcd938x->pullup_ref[micb_index] == 0)) {
  1153. if (pre_off_event && wcd938x->mbhc)
  1154. blocking_notifier_call_chain(
  1155. &wcd938x->mbhc->notifier,
  1156. pre_off_event,
  1157. &wcd938x->mbhc->wcd_mbhc);
  1158. snd_soc_component_update_bits(component, micb_reg,
  1159. 0xC0, 0x00);
  1160. if (post_off_event && wcd938x->mbhc)
  1161. blocking_notifier_call_chain(
  1162. &wcd938x->mbhc->notifier,
  1163. post_off_event,
  1164. &wcd938x->mbhc->wcd_mbhc);
  1165. }
  1166. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1167. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1168. post_dapm_off,
  1169. &wcd938x->mbhc->wcd_mbhc);
  1170. break;
  1171. };
  1172. dev_dbg(component->dev,
  1173. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1174. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1175. wcd938x->pullup_ref[micb_index]);
  1176. mutex_unlock(&wcd938x->micb_lock);
  1177. return 0;
  1178. }
  1179. EXPORT_SYMBOL(wcd938x_micbias_control);
  1180. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1181. {
  1182. int ret = 0;
  1183. uint8_t devnum = 0;
  1184. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1185. if (ret) {
  1186. dev_err(&swr_dev->dev,
  1187. "%s get devnum %d for dev addr %lx failed\n",
  1188. __func__, devnum, swr_dev->addr);
  1189. swr_remove_device(swr_dev);
  1190. return ret;
  1191. }
  1192. swr_dev->dev_num = devnum;
  1193. return 0;
  1194. }
  1195. static int wcd938x_event_notify(struct notifier_block *block,
  1196. unsigned long val,
  1197. void *data)
  1198. {
  1199. u16 event = (val & 0xffff);
  1200. u16 amic;
  1201. u16 mask = 0x40, reg = 0x0;
  1202. int ret = 0;
  1203. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1204. struct snd_soc_component *component = wcd938x->component;
  1205. struct wcd_mbhc *mbhc;
  1206. switch (event) {
  1207. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1208. amic = (val >> 0x10);
  1209. if (amic == 0x1 || amic == 0x2)
  1210. reg = WCD938X_ANA_TX_CH2;
  1211. else if (amic == 0x3)
  1212. reg = WCD938X_ANA_TX_CH4;
  1213. else
  1214. return 0;
  1215. if (amic == 0x2)
  1216. mask = 0x20;
  1217. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1218. break;
  1219. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1220. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1221. 0xC0, 0x00);
  1222. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1223. 0x80, 0x00);
  1224. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1225. 0x80, 0x00);
  1226. break;
  1227. case BOLERO_WCD_EVT_SSR_DOWN:
  1228. wcd938x_reset_low(wcd938x->dev);
  1229. break;
  1230. case BOLERO_WCD_EVT_SSR_UP:
  1231. wcd938x_reset(wcd938x->dev);
  1232. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1233. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1234. regcache_mark_dirty(wcd938x->regmap);
  1235. regcache_sync(wcd938x->regmap);
  1236. /* Initialize MBHC module */
  1237. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1238. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1239. if (ret) {
  1240. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1241. __func__);
  1242. } else {
  1243. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1244. }
  1245. break;
  1246. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1247. snd_soc_component_update_bits(component,
  1248. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1249. ((val >> 0x10) << 0x01));
  1250. break;
  1251. default:
  1252. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1253. break;
  1254. }
  1255. return 0;
  1256. }
  1257. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1258. int event)
  1259. {
  1260. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1261. int micb_num;
  1262. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1263. __func__, w->name, event);
  1264. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1265. micb_num = MIC_BIAS_1;
  1266. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1267. micb_num = MIC_BIAS_2;
  1268. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1269. micb_num = MIC_BIAS_3;
  1270. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1271. micb_num = MIC_BIAS_4;
  1272. else
  1273. return -EINVAL;
  1274. switch (event) {
  1275. case SND_SOC_DAPM_PRE_PMU:
  1276. wcd938x_micbias_control(component, micb_num,
  1277. MICB_ENABLE, true);
  1278. break;
  1279. case SND_SOC_DAPM_POST_PMU:
  1280. /* 1 msec delay as per HW requirement */
  1281. usleep_range(1000, 1100);
  1282. break;
  1283. case SND_SOC_DAPM_POST_PMD:
  1284. wcd938x_micbias_control(component, micb_num,
  1285. MICB_DISABLE, true);
  1286. break;
  1287. };
  1288. return 0;
  1289. }
  1290. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1291. struct snd_kcontrol *kcontrol,
  1292. int event)
  1293. {
  1294. return __wcd938x_codec_enable_micbias(w, event);
  1295. }
  1296. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1297. struct snd_ctl_elem_value *ucontrol)
  1298. {
  1299. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1300. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1301. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1302. return 0;
  1303. }
  1304. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1305. struct snd_ctl_elem_value *ucontrol)
  1306. {
  1307. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1308. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1309. u32 mode_val;
  1310. mode_val = ucontrol->value.enumerated.item[0];
  1311. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1312. if (mode_val == 0) {
  1313. dev_info(component->dev,
  1314. "%s:Invalid HPH Mode, default to class_AB\n",
  1315. __func__);
  1316. mode_val = 3; /* enum will be updated later */
  1317. }
  1318. wcd938x->hph_mode = mode_val;
  1319. return 0;
  1320. }
  1321. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. struct snd_soc_component *component =
  1325. snd_soc_kcontrol_component(kcontrol);
  1326. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1327. bool hphr;
  1328. struct soc_multi_mixer_control *mc;
  1329. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1330. hphr = mc->shift;
  1331. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1332. wcd938x->comp1_enable;
  1333. return 0;
  1334. }
  1335. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1336. struct snd_ctl_elem_value *ucontrol)
  1337. {
  1338. struct snd_soc_component *component =
  1339. snd_soc_kcontrol_component(kcontrol);
  1340. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1341. int value = ucontrol->value.integer.value[0];
  1342. bool hphr;
  1343. struct soc_multi_mixer_control *mc;
  1344. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1345. hphr = mc->shift;
  1346. if (hphr)
  1347. wcd938x->comp2_enable = value;
  1348. else
  1349. wcd938x->comp1_enable = value;
  1350. return 0;
  1351. }
  1352. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1353. struct snd_kcontrol *kcontrol,
  1354. int event)
  1355. {
  1356. struct snd_soc_component *component =
  1357. snd_soc_dapm_to_component(w->dapm);
  1358. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1359. struct wcd938x_pdata *pdata = NULL;
  1360. int ret = 0;
  1361. pdata = dev_get_platdata(wcd938x->dev);
  1362. if (!pdata) {
  1363. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1364. return -EINVAL;
  1365. }
  1366. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1367. w->name, event);
  1368. switch (event) {
  1369. case SND_SOC_DAPM_PRE_PMU:
  1370. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  1371. wcd938x->supplies,
  1372. pdata->regulator,
  1373. pdata->num_supplies,
  1374. "cdc-vdd-buck");
  1375. if (ret == -EINVAL) {
  1376. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1377. __func__);
  1378. return ret;
  1379. }
  1380. /*
  1381. * 200us sleep is required after LDO15 is enabled as per
  1382. * HW requirement
  1383. */
  1384. usleep_range(200, 250);
  1385. break;
  1386. case SND_SOC_DAPM_POST_PMD:
  1387. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  1388. wcd938x->supplies,
  1389. pdata->regulator,
  1390. pdata->num_supplies,
  1391. "cdc-vdd-buck");
  1392. if (ret == -EINVAL) {
  1393. dev_err(component->dev, "%s: vdd buck is not disabled\n",
  1394. __func__);
  1395. return 0;
  1396. }
  1397. break;
  1398. }
  1399. return 0;
  1400. }
  1401. static int wcd938x_tx_hdr_get(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_value *ucontrol)
  1403. {
  1404. struct snd_soc_component *component =
  1405. snd_soc_kcontrol_component(kcontrol);
  1406. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1407. int hdr = ((struct soc_multi_mixer_control *)
  1408. kcontrol->private_value)->shift;
  1409. ucontrol->value.integer.value[0] = wcd938x->hdr_en[hdr];
  1410. return 0;
  1411. }
  1412. static int wcd938x_tx_hdr_put(struct snd_kcontrol *kcontrol,
  1413. struct snd_ctl_elem_value *ucontrol)
  1414. {
  1415. struct snd_soc_component *component =
  1416. snd_soc_kcontrol_component(kcontrol);
  1417. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1418. int hdr = ((struct soc_multi_mixer_control *)
  1419. kcontrol->private_value)->shift;
  1420. int val = ucontrol->value.integer.value[0];
  1421. u8 mask = 0;
  1422. wcd938x->hdr_en[hdr] = val;
  1423. switch(val) {
  1424. case TX_HDR12:
  1425. mask = (1 << 4);
  1426. val = (val << 4);
  1427. break;
  1428. case TX_HDR34:
  1429. mask = (1 << 3);
  1430. val = (val << 3);
  1431. break;
  1432. default:
  1433. dev_err(component->dev, "%s: unknown HDR input: %d\n",
  1434. __func__, hdr);
  1435. break;
  1436. }
  1437. if (mask)
  1438. snd_soc_component_update_bits(component,
  1439. WCD938X_TX_NEW_AMIC_MUX_CFG, mask, val);
  1440. return 0;
  1441. }
  1442. static const char * const rx_hph_mode_mux_text[] = {
  1443. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1444. "CLS_H_ULP", "CLS_AB_HIFI",
  1445. };
  1446. static const struct soc_enum rx_hph_mode_mux_enum =
  1447. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1448. rx_hph_mode_mux_text);
  1449. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1450. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1451. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1452. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1453. wcd938x_get_compander, wcd938x_set_compander),
  1454. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1455. wcd938x_get_compander, wcd938x_set_compander),
  1456. SOC_SINGLE_EXT("TX HDR12", SND_SOC_NOPM, TX_HDR12, 1, 0,
  1457. wcd938x_tx_hdr_get, wcd938x_tx_hdr_put),
  1458. SOC_SINGLE_EXT("TX HDR34", SND_SOC_NOPM, TX_HDR34, 1, 0,
  1459. wcd938x_tx_hdr_get, wcd938x_tx_hdr_put),
  1460. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1461. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1462. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1463. analog_gain),
  1464. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1465. analog_gain),
  1466. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1467. analog_gain),
  1468. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1469. analog_gain),
  1470. };
  1471. static const struct snd_kcontrol_new adc1_switch[] = {
  1472. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1473. };
  1474. static const struct snd_kcontrol_new adc2_switch[] = {
  1475. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1476. };
  1477. static const struct snd_kcontrol_new adc3_switch[] = {
  1478. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1479. };
  1480. static const struct snd_kcontrol_new adc4_switch[] = {
  1481. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1482. };
  1483. static const struct snd_kcontrol_new dmic1_switch[] = {
  1484. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1485. };
  1486. static const struct snd_kcontrol_new dmic2_switch[] = {
  1487. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1488. };
  1489. static const struct snd_kcontrol_new dmic3_switch[] = {
  1490. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1491. };
  1492. static const struct snd_kcontrol_new dmic4_switch[] = {
  1493. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1494. };
  1495. static const struct snd_kcontrol_new dmic5_switch[] = {
  1496. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1497. };
  1498. static const struct snd_kcontrol_new dmic6_switch[] = {
  1499. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1500. };
  1501. static const struct snd_kcontrol_new dmic7_switch[] = {
  1502. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1503. };
  1504. static const struct snd_kcontrol_new dmic8_switch[] = {
  1505. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1506. };
  1507. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1508. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1509. };
  1510. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1511. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1512. };
  1513. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1514. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1515. };
  1516. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1517. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1518. };
  1519. static const char * const adc2_mux_text[] = {
  1520. "INP2", "INP3"
  1521. };
  1522. static const struct soc_enum adc2_enum =
  1523. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1524. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1525. static const struct snd_kcontrol_new tx_adc2_mux =
  1526. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1527. static const char * const adc3_mux_text[] = {
  1528. "INP4", "INP6"
  1529. };
  1530. static const struct soc_enum adc3_enum =
  1531. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1532. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1533. static const struct snd_kcontrol_new tx_adc3_mux =
  1534. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1535. static const char * const adc4_mux_text[] = {
  1536. "INP5", "INP7"
  1537. };
  1538. static const struct soc_enum adc4_enum =
  1539. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1540. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1541. static const struct snd_kcontrol_new tx_adc4_mux =
  1542. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1543. static const char * const rdac3_mux_text[] = {
  1544. "RX1", "RX3"
  1545. };
  1546. static const struct soc_enum rdac3_enum =
  1547. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1548. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1549. static const struct snd_kcontrol_new rx_rdac3_mux =
  1550. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1551. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1552. /*input widgets*/
  1553. SND_SOC_DAPM_INPUT("AMIC1"),
  1554. SND_SOC_DAPM_INPUT("AMIC2"),
  1555. SND_SOC_DAPM_INPUT("AMIC3"),
  1556. SND_SOC_DAPM_INPUT("AMIC4"),
  1557. SND_SOC_DAPM_INPUT("AMIC5"),
  1558. SND_SOC_DAPM_INPUT("AMIC6"),
  1559. SND_SOC_DAPM_INPUT("AMIC7"),
  1560. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1561. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1562. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1563. /*tx widgets*/
  1564. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1565. wcd938x_codec_enable_adc,
  1566. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1567. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 0, 1,
  1568. wcd938x_codec_enable_adc,
  1569. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1570. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 0, 2,
  1571. wcd938x_codec_enable_adc,
  1572. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1573. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 0, 3,
  1574. wcd938x_codec_enable_adc,
  1575. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1576. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1577. wcd938x_codec_enable_dmic,
  1578. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1579. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 1,
  1580. wcd938x_codec_enable_dmic,
  1581. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1582. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 2,
  1583. wcd938x_codec_enable_dmic,
  1584. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1585. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 3,
  1586. wcd938x_codec_enable_dmic,
  1587. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1588. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 4,
  1589. wcd938x_codec_enable_dmic,
  1590. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1591. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 0, 5,
  1592. wcd938x_codec_enable_dmic,
  1593. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1594. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 0, 6,
  1595. wcd938x_codec_enable_dmic,
  1596. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1597. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 0, 7,
  1598. wcd938x_codec_enable_dmic,
  1599. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1600. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1601. NULL, 0, wcd938x_enable_req,
  1602. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1603. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1604. NULL, 0, wcd938x_enable_req,
  1605. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1606. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1607. NULL, 0, wcd938x_enable_req,
  1608. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1609. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 0, 0,
  1610. NULL, 0, wcd938x_enable_req,
  1611. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1612. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1613. &tx_adc2_mux),
  1614. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1615. &tx_adc3_mux),
  1616. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1617. &tx_adc4_mux),
  1618. /*tx mixers*/
  1619. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1620. adc1_switch, ARRAY_SIZE(adc1_switch),
  1621. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1622. SND_SOC_DAPM_POST_PMD),
  1623. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1624. adc2_switch, ARRAY_SIZE(adc2_switch),
  1625. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1626. SND_SOC_DAPM_POST_PMD),
  1627. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1628. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1629. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1630. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1631. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1632. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1633. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1634. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1635. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1636. SND_SOC_DAPM_POST_PMD),
  1637. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1638. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1639. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1640. SND_SOC_DAPM_POST_PMD),
  1641. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1642. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1643. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1644. SND_SOC_DAPM_POST_PMD),
  1645. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1646. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1647. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1648. SND_SOC_DAPM_POST_PMD),
  1649. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1650. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1651. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1652. SND_SOC_DAPM_POST_PMD),
  1653. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1654. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1655. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1656. SND_SOC_DAPM_POST_PMD),
  1657. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1658. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1659. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1660. SND_SOC_DAPM_POST_PMD),
  1661. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1662. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1663. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1664. SND_SOC_DAPM_POST_PMD),
  1665. /* micbias widgets*/
  1666. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1667. wcd938x_codec_enable_micbias,
  1668. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1669. SND_SOC_DAPM_POST_PMD),
  1670. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1671. wcd938x_codec_enable_micbias,
  1672. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1673. SND_SOC_DAPM_POST_PMD),
  1674. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1675. wcd938x_codec_enable_micbias,
  1676. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1677. SND_SOC_DAPM_POST_PMD),
  1678. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1679. wcd938x_codec_enable_micbias,
  1680. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1681. SND_SOC_DAPM_POST_PMD),
  1682. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1683. wcd938x_codec_enable_vdd_buck,
  1684. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1685. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1686. wcd938x_enable_clsh,
  1687. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1688. /*rx widgets*/
  1689. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1690. wcd938x_codec_enable_ear_pa,
  1691. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1692. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1693. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1694. wcd938x_codec_enable_aux_pa,
  1695. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1696. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1697. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1698. wcd938x_codec_enable_hphl_pa,
  1699. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1700. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1701. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1702. wcd938x_codec_enable_hphr_pa,
  1703. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1704. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1705. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1706. wcd938x_codec_hphl_dac_event,
  1707. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1708. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1709. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1710. wcd938x_codec_hphr_dac_event,
  1711. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1712. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1713. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1714. wcd938x_codec_ear_dac_event,
  1715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1716. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1717. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1718. wcd938x_codec_aux_dac_event,
  1719. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1720. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1721. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1722. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1723. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1724. SND_SOC_DAPM_POST_PMD),
  1725. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1726. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1727. SND_SOC_DAPM_POST_PMD),
  1728. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1729. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1730. SND_SOC_DAPM_POST_PMD),
  1731. /* rx mixer widgets*/
  1732. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1733. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1734. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1735. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1736. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1737. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1738. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1739. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1740. /*output widgets tx*/
  1741. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1742. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1743. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1744. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  1745. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1746. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1747. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1748. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1749. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1750. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1751. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  1752. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  1753. /*output widgets rx*/
  1754. SND_SOC_DAPM_OUTPUT("EAR"),
  1755. SND_SOC_DAPM_OUTPUT("AUX"),
  1756. SND_SOC_DAPM_OUTPUT("HPHL"),
  1757. SND_SOC_DAPM_OUTPUT("HPHR"),
  1758. };
  1759. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  1760. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1761. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1762. {"ADC1 REQ", NULL, "ADC1"},
  1763. {"ADC1", NULL, "AMIC1"},
  1764. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1765. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1766. {"ADC2 REQ", NULL, "ADC2"},
  1767. {"ADC2", NULL, "ADC2 MUX"},
  1768. {"ADC2 MUX", "INP3", "AMIC3"},
  1769. {"ADC2 MUX", "INP2", "AMIC2"},
  1770. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1771. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1772. {"ADC3 REQ", NULL, "ADC3"},
  1773. {"ADC3", NULL, "ADC3 MUX"},
  1774. {"ADC3 MUX", "INP4", "AMIC4"},
  1775. {"ADC3 MUX", "INP6", "AMIC6"},
  1776. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  1777. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  1778. {"ADC4 REQ", NULL, "ADC4"},
  1779. {"ADC4", NULL, "ADC4 MUX"},
  1780. {"ADC4 MUX", "INP5", "AMIC5"},
  1781. {"ADC4 MUX", "INP7", "AMIC7"},
  1782. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1783. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1784. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1785. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1786. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1787. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1788. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1789. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1790. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1791. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1792. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1793. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1794. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  1795. {"DMIC7_MIXER", "Switch", "DMIC7"},
  1796. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  1797. {"DMIC8_MIXER", "Switch", "DMIC8"},
  1798. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1799. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1800. {"RX1", NULL, "IN1_HPHL"},
  1801. {"RDAC1", NULL, "RX1"},
  1802. {"HPHL_RDAC", "Switch", "RDAC1"},
  1803. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1804. {"HPHL", NULL, "HPHL PGA"},
  1805. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1806. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1807. {"RX2", NULL, "IN2_HPHR"},
  1808. {"RDAC2", NULL, "RX2"},
  1809. {"HPHR_RDAC", "Switch", "RDAC2"},
  1810. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1811. {"HPHR", NULL, "HPHR PGA"},
  1812. {"IN3_AUX", NULL, "VDD_BUCK"},
  1813. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1814. {"RX3", NULL, "IN3_AUX"},
  1815. {"RDAC4", NULL, "RX3"},
  1816. {"AUX_RDAC", "Switch", "RDAC4"},
  1817. {"AUX PGA", NULL, "AUX_RDAC"},
  1818. {"AUX", NULL, "AUX PGA"},
  1819. {"RDAC3_MUX", "RX3", "RX3"},
  1820. {"RDAC3_MUX", "RX1", "RX1"},
  1821. {"RDAC3", NULL, "RDAC3_MUX"},
  1822. {"EAR_RDAC", "Switch", "RDAC3"},
  1823. {"EAR PGA", NULL, "EAR_RDAC"},
  1824. {"EAR", NULL, "EAR PGA"},
  1825. };
  1826. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  1827. void *file_private_data,
  1828. struct file *file,
  1829. char __user *buf, size_t count,
  1830. loff_t pos)
  1831. {
  1832. struct wcd938x_priv *priv;
  1833. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  1834. int len = 0;
  1835. priv = (struct wcd938x_priv *) entry->private_data;
  1836. if (!priv) {
  1837. pr_err("%s: wcd938x priv is null\n", __func__);
  1838. return -EINVAL;
  1839. }
  1840. switch (priv->version) {
  1841. case WCD938X_VERSION_1_0:
  1842. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  1843. break;
  1844. default:
  1845. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1846. }
  1847. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1848. }
  1849. static struct snd_info_entry_ops wcd938x_info_ops = {
  1850. .read = wcd938x_version_read,
  1851. };
  1852. /*
  1853. * wcd938x_info_create_codec_entry - creates wcd938x module
  1854. * @codec_root: The parent directory
  1855. * @component: component instance
  1856. *
  1857. * Creates wcd938x module and version entry under the given
  1858. * parent directory.
  1859. *
  1860. * Return: 0 on success or negative error code on failure.
  1861. */
  1862. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  1863. struct snd_soc_component *component)
  1864. {
  1865. struct snd_info_entry *version_entry;
  1866. struct wcd938x_priv *priv;
  1867. struct snd_soc_card *card;
  1868. if (!codec_root || !component)
  1869. return -EINVAL;
  1870. priv = snd_soc_component_get_drvdata(component);
  1871. if (priv->entry) {
  1872. dev_dbg(priv->dev,
  1873. "%s:wcd938x module already created\n", __func__);
  1874. return 0;
  1875. }
  1876. card = component->card;
  1877. priv->entry = snd_info_create_subdir(codec_root->module,
  1878. "wcd938x", codec_root);
  1879. if (!priv->entry) {
  1880. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  1881. __func__);
  1882. return -ENOMEM;
  1883. }
  1884. version_entry = snd_info_create_card_entry(card->snd_card,
  1885. "version",
  1886. priv->entry);
  1887. if (!version_entry) {
  1888. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  1889. __func__);
  1890. return -ENOMEM;
  1891. }
  1892. version_entry->private_data = priv;
  1893. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  1894. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  1895. version_entry->c.ops = &wcd938x_info_ops;
  1896. if (snd_info_register(version_entry) < 0) {
  1897. snd_info_free_entry(version_entry);
  1898. return -ENOMEM;
  1899. }
  1900. priv->version_entry = version_entry;
  1901. return 0;
  1902. }
  1903. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  1904. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  1905. {
  1906. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1907. struct snd_soc_dapm_context *dapm =
  1908. snd_soc_component_get_dapm(component);
  1909. int variant;
  1910. int ret = -EINVAL;
  1911. dev_info(component->dev, "%s()\n", __func__);
  1912. wcd938x = snd_soc_component_get_drvdata(component);
  1913. if (!wcd938x)
  1914. return -EINVAL;
  1915. wcd938x->component = component;
  1916. snd_soc_component_init_regmap(component, wcd938x->regmap);
  1917. variant = (snd_soc_component_read32(component,
  1918. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  1919. wcd938x->variant = variant;
  1920. wcd938x->fw_data = devm_kzalloc(component->dev,
  1921. sizeof(*(wcd938x->fw_data)),
  1922. GFP_KERNEL);
  1923. if (!wcd938x->fw_data) {
  1924. dev_err(component->dev, "Failed to allocate fw_data\n");
  1925. ret = -ENOMEM;
  1926. goto err;
  1927. }
  1928. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  1929. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  1930. WCD9XXX_CODEC_HWDEP_NODE, component);
  1931. if (ret < 0) {
  1932. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  1933. goto err_hwdep;
  1934. }
  1935. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  1936. if (ret) {
  1937. pr_err("%s: mbhc initialization failed\n", __func__);
  1938. goto err_hwdep;
  1939. }
  1940. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  1941. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  1942. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  1943. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  1944. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  1945. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  1946. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  1947. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  1948. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  1949. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  1950. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  1951. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  1952. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  1953. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  1954. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  1955. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  1956. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  1957. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  1958. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  1959. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  1960. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  1961. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  1962. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  1963. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  1964. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  1965. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  1966. snd_soc_dapm_sync(dapm);
  1967. wcd_cls_h_init(&wcd938x->clsh_info);
  1968. wcd938x_init_reg(component);
  1969. wcd938x->version = WCD938X_VERSION_1_0;
  1970. /* Register event notifier */
  1971. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  1972. if (wcd938x->register_notifier) {
  1973. ret = wcd938x->register_notifier(wcd938x->handle,
  1974. &wcd938x->nblock,
  1975. true);
  1976. if (ret) {
  1977. dev_err(component->dev,
  1978. "%s: Failed to register notifier %d\n",
  1979. __func__, ret);
  1980. return ret;
  1981. }
  1982. }
  1983. return ret;
  1984. err_hwdep:
  1985. wcd938x->fw_data = NULL;
  1986. err:
  1987. return ret;
  1988. }
  1989. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  1990. {
  1991. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1992. if (!wcd938x) {
  1993. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  1994. __func__);
  1995. return;
  1996. }
  1997. if (wcd938x->register_notifier)
  1998. wcd938x->register_notifier(wcd938x->handle,
  1999. &wcd938x->nblock,
  2000. false);
  2001. }
  2002. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2003. .name = WCD938X_DRV_NAME,
  2004. .probe = wcd938x_soc_codec_probe,
  2005. .remove = wcd938x_soc_codec_remove,
  2006. .controls = wcd938x_snd_controls,
  2007. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2008. .dapm_widgets = wcd938x_dapm_widgets,
  2009. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2010. .dapm_routes = wcd938x_audio_map,
  2011. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2012. };
  2013. static int wcd938x_reset(struct device *dev)
  2014. {
  2015. struct wcd938x_priv *wcd938x = NULL;
  2016. int rc = 0;
  2017. int value = 0;
  2018. if (!dev)
  2019. return -ENODEV;
  2020. wcd938x = dev_get_drvdata(dev);
  2021. if (!wcd938x)
  2022. return -EINVAL;
  2023. if (!wcd938x->rst_np) {
  2024. dev_err(dev, "%s: reset gpio device node not specified\n",
  2025. __func__);
  2026. return -EINVAL;
  2027. }
  2028. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2029. if (value > 0)
  2030. return 0;
  2031. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2032. if (rc) {
  2033. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2034. __func__);
  2035. return rc;
  2036. }
  2037. /* 20us sleep required after pulling the reset gpio to LOW */
  2038. usleep_range(20, 30);
  2039. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2040. if (rc) {
  2041. dev_err(dev, "%s: wcd active state request fail!\n",
  2042. __func__);
  2043. return rc;
  2044. }
  2045. /* 20us sleep required after pulling the reset gpio to HIGH */
  2046. usleep_range(20, 30);
  2047. return rc;
  2048. }
  2049. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2050. u32 *val)
  2051. {
  2052. int rc = 0;
  2053. rc = of_property_read_u32(dev->of_node, name, val);
  2054. if (rc)
  2055. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2056. __func__, name, dev->of_node->full_name);
  2057. return rc;
  2058. }
  2059. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2060. struct wcd938x_micbias_setting *mb)
  2061. {
  2062. u32 prop_val = 0;
  2063. int rc = 0;
  2064. /* MB1 */
  2065. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2066. NULL)) {
  2067. rc = wcd938x_read_of_property_u32(dev,
  2068. "qcom,cdc-micbias1-mv",
  2069. &prop_val);
  2070. if (!rc)
  2071. mb->micb1_mv = prop_val;
  2072. } else {
  2073. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2074. __func__);
  2075. }
  2076. /* MB2 */
  2077. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2078. NULL)) {
  2079. rc = wcd938x_read_of_property_u32(dev,
  2080. "qcom,cdc-micbias2-mv",
  2081. &prop_val);
  2082. if (!rc)
  2083. mb->micb2_mv = prop_val;
  2084. } else {
  2085. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2086. __func__);
  2087. }
  2088. /* MB3 */
  2089. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2090. NULL)) {
  2091. rc = wcd938x_read_of_property_u32(dev,
  2092. "qcom,cdc-micbias3-mv",
  2093. &prop_val);
  2094. if (!rc)
  2095. mb->micb3_mv = prop_val;
  2096. } else {
  2097. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2098. __func__);
  2099. }
  2100. }
  2101. static int wcd938x_reset_low(struct device *dev)
  2102. {
  2103. struct wcd938x_priv *wcd938x = NULL;
  2104. int rc = 0;
  2105. if (!dev)
  2106. return -ENODEV;
  2107. wcd938x = dev_get_drvdata(dev);
  2108. if (!wcd938x)
  2109. return -EINVAL;
  2110. if (!wcd938x->rst_np) {
  2111. dev_err(dev, "%s: reset gpio device node not specified\n",
  2112. __func__);
  2113. return -EINVAL;
  2114. }
  2115. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2116. if (rc) {
  2117. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2118. __func__);
  2119. return rc;
  2120. }
  2121. /* 20us sleep required after pulling the reset gpio to LOW */
  2122. usleep_range(20, 30);
  2123. return rc;
  2124. }
  2125. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2126. {
  2127. struct wcd938x_pdata *pdata = NULL;
  2128. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2129. GFP_KERNEL);
  2130. if (!pdata)
  2131. return NULL;
  2132. pdata->rst_np = of_parse_phandle(dev->of_node,
  2133. "qcom,wcd-rst-gpio-node", 0);
  2134. if (!pdata->rst_np) {
  2135. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2136. __func__, "qcom,wcd-rst-gpio-node",
  2137. dev->of_node->full_name);
  2138. return NULL;
  2139. }
  2140. /* Parse power supplies */
  2141. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2142. &pdata->num_supplies);
  2143. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2144. dev_err(dev, "%s: no power supplies defined for codec\n",
  2145. __func__);
  2146. return NULL;
  2147. }
  2148. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-swr-slave", 0);
  2149. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-swr-slave", 0);
  2150. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2151. return pdata;
  2152. }
  2153. static int wcd938x_bind(struct device *dev)
  2154. {
  2155. int ret = 0, i = 0;
  2156. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2157. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2158. /*
  2159. * Add 5msec delay to provide sufficient time for
  2160. * soundwire auto enumeration of slave devices as
  2161. * as per HW requirement.
  2162. */
  2163. usleep_range(5000, 5010);
  2164. ret = component_bind_all(dev, wcd938x);
  2165. if (ret) {
  2166. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2167. __func__, ret);
  2168. return ret;
  2169. }
  2170. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2171. if (!wcd938x->rx_swr_dev) {
  2172. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2173. __func__);
  2174. ret = -ENODEV;
  2175. goto err;
  2176. }
  2177. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2178. if (!wcd938x->tx_swr_dev) {
  2179. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2180. __func__);
  2181. ret = -ENODEV;
  2182. goto err;
  2183. }
  2184. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2185. &wcd938x_regmap_config);
  2186. if (!wcd938x->regmap) {
  2187. dev_err(dev, "%s: Regmap init failed\n",
  2188. __func__);
  2189. goto err;
  2190. }
  2191. /* Set all interupts as edge triggered */
  2192. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2193. regmap_write(wcd938x->regmap,
  2194. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2195. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2196. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2197. wcd938x->irq_info.codec_name = "WCD938X";
  2198. wcd938x->irq_info.regmap = wcd938x->regmap;
  2199. wcd938x->irq_info.dev = dev;
  2200. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2201. if (ret) {
  2202. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2203. __func__, ret);
  2204. goto err;
  2205. }
  2206. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2207. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2208. NULL, 0);
  2209. if (ret) {
  2210. dev_err(dev, "%s: Codec registration failed\n",
  2211. __func__);
  2212. goto err_irq;
  2213. }
  2214. return ret;
  2215. err_irq:
  2216. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2217. err:
  2218. component_unbind_all(dev, wcd938x);
  2219. return ret;
  2220. }
  2221. static void wcd938x_unbind(struct device *dev)
  2222. {
  2223. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2224. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2225. snd_soc_unregister_component(dev);
  2226. component_unbind_all(dev, wcd938x);
  2227. }
  2228. static const struct of_device_id wcd938x_dt_match[] = {
  2229. { .compatible = "qcom,wcd938x-codec" },
  2230. {}
  2231. };
  2232. static const struct component_master_ops wcd938x_comp_ops = {
  2233. .bind = wcd938x_bind,
  2234. .unbind = wcd938x_unbind,
  2235. };
  2236. static int wcd938x_compare_of(struct device *dev, void *data)
  2237. {
  2238. return dev->of_node == data;
  2239. }
  2240. static void wcd938x_release_of(struct device *dev, void *data)
  2241. {
  2242. of_node_put(data);
  2243. }
  2244. static int wcd938x_add_slave_components(struct device *dev,
  2245. struct component_match **matchptr)
  2246. {
  2247. struct device_node *np, *rx_node, *tx_node;
  2248. np = dev->of_node;
  2249. rx_node = of_parse_phandle(np, "qcom,rx-swr-slave", 0);
  2250. if (!rx_node) {
  2251. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2252. return -ENODEV;
  2253. }
  2254. of_node_get(rx_node);
  2255. component_match_add_release(dev, matchptr,
  2256. wcd938x_release_of,
  2257. wcd938x_compare_of,
  2258. rx_node);
  2259. tx_node = of_parse_phandle(np, "qcom,tx-swr-slave", 0);
  2260. if (!tx_node) {
  2261. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2262. return -ENODEV;
  2263. }
  2264. of_node_get(tx_node);
  2265. component_match_add_release(dev, matchptr,
  2266. wcd938x_release_of,
  2267. wcd938x_compare_of,
  2268. tx_node);
  2269. return 0;
  2270. }
  2271. static int wcd938x_wakeup(void *handle, bool enable)
  2272. {
  2273. struct wcd938x_priv *priv;
  2274. if (!handle) {
  2275. pr_err("%s: NULL handle\n", __func__);
  2276. return -EINVAL;
  2277. }
  2278. priv = (struct wcd938x_priv *)handle;
  2279. if (!priv->tx_swr_dev) {
  2280. pr_err("%s: tx swr dev is NULL\n", __func__);
  2281. return -EINVAL;
  2282. }
  2283. if (enable)
  2284. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2285. else
  2286. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2287. }
  2288. static int wcd938x_probe(struct platform_device *pdev)
  2289. {
  2290. struct component_match *match = NULL;
  2291. struct wcd938x_priv *wcd938x = NULL;
  2292. struct wcd938x_pdata *pdata = NULL;
  2293. struct wcd_ctrl_platform_data *plat_data = NULL;
  2294. struct device *dev = &pdev->dev;
  2295. int ret;
  2296. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2297. GFP_KERNEL);
  2298. if (!wcd938x)
  2299. return -ENOMEM;
  2300. dev_set_drvdata(dev, wcd938x);
  2301. pdata = wcd938x_populate_dt_data(dev);
  2302. if (!pdata) {
  2303. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2304. return -EINVAL;
  2305. }
  2306. dev->platform_data = pdata;
  2307. wcd938x->rst_np = pdata->rst_np;
  2308. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2309. pdata->regulator, pdata->num_supplies);
  2310. if (!wcd938x->supplies) {
  2311. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2312. __func__);
  2313. return ret;
  2314. }
  2315. plat_data = dev_get_platdata(dev->parent);
  2316. if (!plat_data) {
  2317. dev_err(dev, "%s: platform data from parent is NULL\n",
  2318. __func__);
  2319. return -EINVAL;
  2320. }
  2321. wcd938x->handle = (void *)plat_data->handle;
  2322. if (!wcd938x->handle) {
  2323. dev_err(dev, "%s: handle is NULL\n", __func__);
  2324. return -EINVAL;
  2325. }
  2326. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2327. if (!wcd938x->update_wcd_event) {
  2328. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2329. __func__);
  2330. return -EINVAL;
  2331. }
  2332. wcd938x->register_notifier = plat_data->register_notifier;
  2333. if (!wcd938x->register_notifier) {
  2334. dev_err(dev, "%s: register_notifier api is null!\n",
  2335. __func__);
  2336. return -EINVAL;
  2337. }
  2338. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2339. pdata->regulator,
  2340. pdata->num_supplies);
  2341. if (ret) {
  2342. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2343. __func__);
  2344. return ret;
  2345. }
  2346. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2347. CODEC_RX);
  2348. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2349. CODEC_TX);
  2350. if (ret) {
  2351. dev_err(dev, "Failed to read port mapping\n");
  2352. goto err;
  2353. }
  2354. ret = wcd938x_add_slave_components(dev, &match);
  2355. if (ret)
  2356. goto err;
  2357. wcd938x_reset(dev);
  2358. wcd938x->wakeup = wcd938x_wakeup;
  2359. return component_master_add_with_match(dev,
  2360. &wcd938x_comp_ops, match);
  2361. err:
  2362. return ret;
  2363. }
  2364. static int wcd938x_remove(struct platform_device *pdev)
  2365. {
  2366. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2367. dev_set_drvdata(&pdev->dev, NULL);
  2368. return 0;
  2369. }
  2370. #ifdef CONFIG_PM_SLEEP
  2371. static int wcd938x_suspend(struct device *dev)
  2372. {
  2373. return 0;
  2374. }
  2375. static int wcd938x_resume(struct device *dev)
  2376. {
  2377. return 0;
  2378. }
  2379. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2380. SET_SYSTEM_SLEEP_PM_OPS(
  2381. wcd938x_suspend,
  2382. wcd938x_resume
  2383. )
  2384. };
  2385. #endif
  2386. static struct platform_driver wcd938x_codec_driver = {
  2387. .probe = wcd938x_probe,
  2388. .remove = wcd938x_remove,
  2389. .driver = {
  2390. .name = "wcd938x_codec",
  2391. .owner = THIS_MODULE,
  2392. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2393. #ifdef CONFIG_PM_SLEEP
  2394. .pm = &wcd938x_dev_pm_ops,
  2395. #endif
  2396. },
  2397. };
  2398. module_platform_driver(wcd938x_codec_driver);
  2399. MODULE_DESCRIPTION("WCD938X Codec driver");
  2400. MODULE_LICENSE("GPL v2");