sde_plane.c 142 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include "msm_prop.h"
  26. #include "msm_drv.h"
  27. #include "sde_kms.h"
  28. #include "sde_fence.h"
  29. #include "sde_formats.h"
  30. #include "sde_hw_sspp.h"
  31. #include "sde_hw_catalog_format.h"
  32. #include "sde_trace.h"
  33. #include "sde_crtc.h"
  34. #include "sde_vbif.h"
  35. #include "sde_plane.h"
  36. #include "sde_color_processing.h"
  37. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  40. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  42. #define PHASE_STEP_SHIFT 21
  43. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  44. #define PHASE_RESIDUAL 15
  45. #define SHARP_STRENGTH_DEFAULT 32
  46. #define SHARP_EDGE_THR_DEFAULT 112
  47. #define SHARP_SMOOTH_THR_DEFAULT 8
  48. #define SHARP_NOISE_THR_DEFAULT 2
  49. #define SDE_NAME_SIZE 12
  50. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  51. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  52. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  53. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  54. /**
  55. * enum sde_plane_qos - Different qos configurations for each pipe
  56. *
  57. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  58. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  59. * this configuration is mutually exclusive from VBLANK_CTRL.
  60. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  61. */
  62. enum sde_plane_qos {
  63. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  64. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  65. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  66. };
  67. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  68. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  69. {
  70. struct msm_drm_private *priv;
  71. if (!plane || !plane->dev)
  72. return NULL;
  73. priv = plane->dev->dev_private;
  74. if (!priv)
  75. return NULL;
  76. return to_sde_kms(priv->kms);
  77. }
  78. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  79. {
  80. struct drm_plane_state *pstate = NULL;
  81. struct drm_crtc *drm_crtc = NULL;
  82. struct sde_crtc *sde_crtc = NULL;
  83. struct sde_crtc_mixer *mixer = NULL;
  84. struct sde_hw_ctl *ctl = NULL;
  85. if (!plane) {
  86. DRM_ERROR("Invalid plane %pK\n", plane);
  87. return NULL;
  88. }
  89. pstate = plane->state;
  90. if (!pstate) {
  91. DRM_ERROR("Invalid plane state %pK\n", pstate);
  92. return NULL;
  93. }
  94. drm_crtc = pstate->crtc;
  95. if (!drm_crtc) {
  96. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  97. return NULL;
  98. }
  99. sde_crtc = to_sde_crtc(drm_crtc);
  100. if (!sde_crtc) {
  101. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  102. return NULL;
  103. }
  104. /* it will always return the first mixer and single CTL */
  105. mixer = sde_crtc->mixers;
  106. if (!mixer) {
  107. DRM_ERROR("invalid mixer %pK\n", mixer);
  108. return NULL;
  109. }
  110. ctl = mixer->hw_ctl;
  111. if (!mixer) {
  112. DRM_ERROR("invalid ctl %pK\n", ctl);
  113. return NULL;
  114. }
  115. return ctl;
  116. }
  117. static void _sde_plane_setup_panel_stacking(struct sde_plane *psde,
  118. struct sde_plane_state *pstate)
  119. {
  120. struct sde_hw_pipe_line_insertion_cfg *cfg;
  121. struct sde_crtc_state *cstate;
  122. u32 h_start = 0, h_total = 0, y_start = 0;
  123. struct drm_plane_state *dpstate = NULL;
  124. struct drm_crtc *drm_crtc = NULL;
  125. if (!psde || !psde->base.state || !psde->base.state->crtc) {
  126. SDE_ERROR("Invalid plane psde %p or drm plane state or drm crtc\n", psde);
  127. return;
  128. }
  129. dpstate = psde->base.state;
  130. drm_crtc = dpstate->crtc;
  131. cstate = to_sde_crtc_state(drm_crtc->state);
  132. pstate->lineinsertion_feature = cstate->line_insertion.panel_line_insertion_enable;
  133. if ((!test_bit(SDE_SSPP_LINE_INSERTION, (unsigned long *)&psde->features)) ||
  134. !cstate->line_insertion.panel_line_insertion_enable)
  135. return;
  136. cfg = &pstate->line_insertion_cfg;
  137. memset(cfg, 0, sizeof(*cfg));
  138. if (!cstate->line_insertion.padding_height)
  139. return;
  140. sde_crtc_calc_vpadding_param(psde->base.state->crtc->state,
  141. pstate->base.crtc_y, pstate->base.crtc_h,
  142. &y_start, &h_start, &h_total);
  143. cfg->enable = true;
  144. cfg->dummy_lines = cstate->line_insertion.padding_dummy;
  145. cfg->active_lines = cstate->line_insertion.padding_active;
  146. cfg->first_active_lines = h_start;
  147. cfg->dst_h = h_total;
  148. psde->pipe_cfg.dst_rect.y += y_start - pstate->base.crtc_y;
  149. }
  150. static bool sde_plane_enabled(const struct drm_plane_state *state)
  151. {
  152. return state && state->fb && state->crtc;
  153. }
  154. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  155. {
  156. struct sde_plane *psde;
  157. if (!plane)
  158. return false;
  159. psde = to_sde_plane(plane);
  160. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  161. }
  162. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  163. enum sde_sspp_multirect_index rect_mode, bool enable)
  164. {
  165. struct sde_plane *psde;
  166. if (!plane)
  167. return;
  168. psde = to_sde_plane(plane);
  169. if (psde->pipe_hw->ops.set_src_split_order)
  170. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  171. rect_mode, enable);
  172. }
  173. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  174. {
  175. struct sde_plane *psde;
  176. struct sde_kms *sde_kms;
  177. struct msm_drm_private *priv;
  178. if (!plane || !plane->dev) {
  179. SDE_ERROR("invalid plane\n");
  180. return;
  181. }
  182. priv = plane->dev->dev_private;
  183. if (!priv || !priv->kms) {
  184. SDE_ERROR("invalid KMS reference\n");
  185. return;
  186. }
  187. sde_kms = to_sde_kms(priv->kms);
  188. psde = to_sde_plane(plane);
  189. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  190. }
  191. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  192. struct drm_crtc *crtc,
  193. struct drm_framebuffer *fb)
  194. {
  195. struct sde_plane *psde;
  196. const struct sde_format *fmt = NULL;
  197. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  198. struct sde_perf_cfg *perf;
  199. struct sde_plane_state *pstate;
  200. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  201. bool inline_rot = false, landscape = false;
  202. struct drm_display_mode *mode;
  203. u32 fl_require0 = 0;
  204. if (!plane || !fb) {
  205. SDE_ERROR("invalid arguments\n");
  206. return;
  207. }
  208. psde = to_sde_plane(plane);
  209. pstate = to_sde_plane_state(plane->state);
  210. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  211. SDE_ERROR("invalid arguments\n");
  212. return;
  213. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  214. return;
  215. }
  216. mode = &crtc->state->adjusted_mode;
  217. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  218. frame_rate = drm_mode_vrefresh(&crtc->mode);
  219. perf = &psde->catalog->perf;
  220. qos_count = perf->qos_refresh_count;
  221. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  222. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  223. (fps_index == qos_count - 1))
  224. break;
  225. fps_index++;
  226. }
  227. if (psde->is_rt_pipe) {
  228. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  229. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  230. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  231. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  232. else if (inline_rot)
  233. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  234. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  235. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  236. else
  237. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  238. } else {
  239. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  240. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  241. }
  242. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  243. if (psde->scaler3_cfg.enable)
  244. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  245. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  246. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  247. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  248. if (landscape) {
  249. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  250. fl_require0 = psde->catalog->qos_target_time_ns /
  251. (sde_crtc->line_time_in_ns * 2);
  252. if (!fl_require0 || fl_require0 < 4.5)
  253. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  254. }
  255. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  256. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  257. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  258. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  259. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  260. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  261. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  262. plane->base.id, psde->pipe - SSPP_VIG0,
  263. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  264. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  265. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  266. psde->is_rt_pipe, psde->wb_usage_type);
  267. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  268. }
  269. /**
  270. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  271. * @plane: Pointer to drm plane
  272. * @enable: true to enable QoS control
  273. * @flags: QoS control mode (enum sde_plane_qos)
  274. */
  275. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  276. bool enable, u32 flags)
  277. {
  278. struct sde_plane *psde;
  279. if (!plane) {
  280. SDE_ERROR("invalid arguments\n");
  281. return;
  282. }
  283. psde = to_sde_plane(plane);
  284. if (!psde->pipe_hw || !psde->pipe_sblk) {
  285. SDE_ERROR("invalid arguments\n");
  286. return;
  287. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  288. return;
  289. }
  290. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  291. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  292. psde->pipe_qos_cfg.danger_vblank =
  293. psde->pipe_sblk->danger_vblank;
  294. psde->pipe_qos_cfg.vblank_en = enable;
  295. }
  296. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  297. /* this feature overrules previous VBLANK_CTRL */
  298. psde->pipe_qos_cfg.vblank_en = false;
  299. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  300. psde->pipe_qos_cfg.danger_vblank = 0;
  301. }
  302. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  303. psde->pipe_qos_cfg.danger_safe_en = enable;
  304. if (!psde->is_rt_pipe) {
  305. psde->pipe_qos_cfg.vblank_en = false;
  306. psde->pipe_qos_cfg.danger_safe_en = false;
  307. }
  308. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  309. plane->base.id,
  310. psde->pipe - SSPP_VIG0,
  311. psde->pipe_qos_cfg.danger_safe_en,
  312. psde->pipe_qos_cfg.vblank_en,
  313. psde->pipe_qos_cfg.creq_vblank,
  314. psde->pipe_qos_cfg.danger_vblank,
  315. psde->is_rt_pipe);
  316. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  317. &psde->pipe_qos_cfg);
  318. }
  319. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  320. {
  321. struct sde_plane *psde;
  322. if (!plane)
  323. return;
  324. psde = to_sde_plane(plane);
  325. psde->revalidate = enable;
  326. }
  327. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  328. {
  329. struct sde_plane *psde;
  330. int rc;
  331. if (!plane) {
  332. SDE_ERROR("invalid arguments\n");
  333. return -EINVAL;
  334. }
  335. psde = to_sde_plane(plane);
  336. if (!psde->is_rt_pipe)
  337. goto end;
  338. rc = pm_runtime_resume_and_get(plane->dev->dev);
  339. if (rc < 0) {
  340. SDE_ERROR("failed to enable power resource %d\n", rc);
  341. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  342. return rc;
  343. }
  344. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  345. pm_runtime_put_sync(plane->dev->dev);
  346. end:
  347. return 0;
  348. }
  349. /**
  350. * _sde_plane_set_ot_limit - set OT limit for the given plane
  351. * @plane: Pointer to drm plane
  352. * @crtc: Pointer to drm crtc
  353. */
  354. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  355. struct drm_crtc *crtc)
  356. {
  357. struct sde_plane *psde;
  358. struct sde_vbif_set_ot_params ot_params;
  359. struct msm_drm_private *priv;
  360. struct sde_kms *sde_kms;
  361. if (!plane || !plane->dev || !crtc) {
  362. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  363. !plane, !crtc);
  364. return;
  365. }
  366. priv = plane->dev->dev_private;
  367. if (!priv || !priv->kms) {
  368. SDE_ERROR("invalid KMS reference\n");
  369. return;
  370. }
  371. sde_kms = to_sde_kms(priv->kms);
  372. psde = to_sde_plane(plane);
  373. if (!psde->pipe_hw) {
  374. SDE_ERROR("invalid pipe reference\n");
  375. return;
  376. }
  377. memset(&ot_params, 0, sizeof(ot_params));
  378. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  379. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  380. ot_params.width = psde->pipe_cfg.src_rect.w;
  381. ot_params.height = psde->pipe_cfg.src_rect.h;
  382. ot_params.is_wfd = ((psde->is_rt_pipe)
  383. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  384. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  385. ot_params.vbif_idx = VBIF_RT;
  386. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  387. ot_params.rd = true;
  388. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  389. }
  390. /**
  391. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  392. * @plane: Pointer to drm plane
  393. */
  394. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  395. {
  396. struct sde_plane *psde;
  397. struct sde_vbif_set_qos_params qos_params;
  398. struct msm_drm_private *priv;
  399. struct sde_kms *sde_kms;
  400. if (!plane || !plane->dev) {
  401. SDE_ERROR("invalid arguments\n");
  402. return;
  403. }
  404. priv = plane->dev->dev_private;
  405. if (!priv || !priv->kms) {
  406. SDE_ERROR("invalid KMS reference\n");
  407. return;
  408. }
  409. sde_kms = to_sde_kms(priv->kms);
  410. psde = to_sde_plane(plane);
  411. if (!psde->pipe_hw) {
  412. SDE_ERROR("invalid pipe reference\n");
  413. return;
  414. }
  415. memset(&qos_params, 0, sizeof(qos_params));
  416. qos_params.vbif_idx = VBIF_RT;
  417. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  418. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  419. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  420. if (psde->is_rt_pipe)
  421. qos_params.client_type = VBIF_RT_CLIENT;
  422. else
  423. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  424. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  425. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  426. plane->base.id, qos_params.num,
  427. qos_params.vbif_idx,
  428. qos_params.xin_id, qos_params.client_type,
  429. qos_params.clk_ctrl);
  430. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  431. }
  432. /**
  433. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  434. * @plane: Pointer to drm plane
  435. * @pstate: Pointer to sde plane state
  436. */
  437. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  438. struct sde_plane_state *pstate)
  439. {
  440. struct sde_plane *psde;
  441. struct sde_hw_pipe_ts_cfg cfg;
  442. struct msm_drm_private *priv;
  443. struct sde_kms *sde_kms;
  444. if (!plane || !plane->dev) {
  445. SDE_ERROR("invalid arguments");
  446. return;
  447. }
  448. priv = plane->dev->dev_private;
  449. if (!priv || !priv->kms) {
  450. SDE_ERROR("invalid KMS reference\n");
  451. return;
  452. }
  453. sde_kms = to_sde_kms(priv->kms);
  454. psde = to_sde_plane(plane);
  455. if (!psde->pipe_hw) {
  456. SDE_ERROR("invalid pipe reference\n");
  457. return;
  458. }
  459. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  460. return;
  461. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  462. memset(&cfg, 0, sizeof(cfg));
  463. cfg.size = sde_plane_get_property(pstate,
  464. PLANE_PROP_PREFILL_SIZE);
  465. cfg.time = sde_plane_get_property(pstate,
  466. PLANE_PROP_PREFILL_TIME);
  467. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  468. plane->base.id, cfg.size, cfg.time);
  469. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  470. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  471. pstate->multirect_index);
  472. }
  473. /* helper to update a state's input fence pointer from the property */
  474. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  475. struct sde_plane_state *pstate, uint64_t fd)
  476. {
  477. if (!psde || !pstate) {
  478. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  479. !psde, !pstate);
  480. return;
  481. }
  482. /* clear previous reference */
  483. if (pstate->input_fence)
  484. sde_sync_put(pstate->input_fence);
  485. /* get fence pointer for later */
  486. if (fd == 0)
  487. pstate->input_fence = NULL;
  488. else
  489. pstate->input_fence = sde_sync_get(fd);
  490. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  491. }
  492. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  493. {
  494. struct sde_plane *psde;
  495. struct sde_plane_state *pstate;
  496. uint32_t prefix;
  497. void *input_fence;
  498. int ret = -EINVAL;
  499. signed long rc;
  500. if (!plane) {
  501. SDE_ERROR("invalid plane\n");
  502. } else if (!plane->state) {
  503. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  504. } else {
  505. psde = to_sde_plane(plane);
  506. pstate = to_sde_plane_state(plane->state);
  507. input_fence = pstate->input_fence;
  508. if (input_fence) {
  509. prefix = sde_sync_get_name_prefix(input_fence);
  510. rc = sde_sync_wait(input_fence, wait_ms);
  511. switch (rc) {
  512. case 0:
  513. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  514. wait_ms, prefix, sde_plane_get_property(pstate,
  515. PLANE_PROP_INPUT_FENCE));
  516. psde->is_error = true;
  517. sde_kms_timeline_status(plane->dev);
  518. ret = -ETIMEDOUT;
  519. break;
  520. case -ERESTARTSYS:
  521. SDE_ERROR_PLANE(psde,
  522. "%ums wait interrupted on %08X\n",
  523. wait_ms, prefix);
  524. psde->is_error = true;
  525. ret = -ERESTARTSYS;
  526. break;
  527. case -EINVAL:
  528. SDE_ERROR_PLANE(psde,
  529. "invalid fence param for %08X\n",
  530. prefix);
  531. psde->is_error = true;
  532. ret = -EINVAL;
  533. break;
  534. case -EBADF:
  535. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  536. plane->base.id,
  537. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  538. psde->is_error = true;
  539. ret = 0;
  540. break;
  541. default:
  542. SDE_DEBUG_PLANE(psde, "signaled\n");
  543. ret = 0;
  544. break;
  545. }
  546. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  547. } else {
  548. ret = 0;
  549. }
  550. }
  551. return ret;
  552. }
  553. /**
  554. * _sde_plane_get_aspace: gets the address space based on the
  555. * fb_translation mode property
  556. */
  557. static int _sde_plane_get_aspace(
  558. struct sde_plane *psde,
  559. struct sde_plane_state *pstate,
  560. struct msm_gem_address_space **aspace)
  561. {
  562. struct sde_kms *kms;
  563. int mode;
  564. if (!psde || !pstate || !aspace) {
  565. SDE_ERROR("invalid parameters\n");
  566. return -EINVAL;
  567. }
  568. kms = _sde_plane_get_kms(&psde->base);
  569. if (!kms) {
  570. SDE_ERROR("invalid kms\n");
  571. return -EINVAL;
  572. }
  573. mode = sde_plane_get_property(pstate,
  574. PLANE_PROP_FB_TRANSLATION_MODE);
  575. switch (mode) {
  576. case SDE_DRM_FB_NON_SEC:
  577. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  578. if (!aspace)
  579. return -EINVAL;
  580. break;
  581. case SDE_DRM_FB_SEC:
  582. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  583. if (!aspace)
  584. return -EINVAL;
  585. break;
  586. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  587. case SDE_DRM_FB_SEC_DIR_TRANS:
  588. *aspace = NULL;
  589. break;
  590. default:
  591. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  592. return -EFAULT;
  593. }
  594. return 0;
  595. }
  596. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  597. struct sde_plane_state *pstate,
  598. struct sde_hw_pipe_cfg *pipe_cfg,
  599. struct drm_framebuffer *fb)
  600. {
  601. struct sde_plane *psde;
  602. struct msm_gem_address_space *aspace = NULL;
  603. int ret, mode;
  604. bool secure = false;
  605. if (!plane || !pstate || !pipe_cfg || !fb) {
  606. SDE_ERROR(
  607. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  608. !plane, !pstate, !pipe_cfg, !fb);
  609. return;
  610. }
  611. psde = to_sde_plane(plane);
  612. if (!psde->pipe_hw) {
  613. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  614. return;
  615. }
  616. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  617. if (ret) {
  618. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  619. return;
  620. }
  621. /*
  622. * framebuffer prepare is deferred for prepare_fb calls that
  623. * happen during the transition from secure to non-secure.
  624. * Handle the prepare at this point for such cases. This can be
  625. * expected for one or two frames during the transition.
  626. */
  627. if (aspace && pstate->defer_prepare_fb) {
  628. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  629. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  630. if (ret) {
  631. SDE_ERROR_PLANE(psde,
  632. "failed to prepare framebuffer %d\n", ret);
  633. return;
  634. }
  635. pstate->defer_prepare_fb = false;
  636. }
  637. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  638. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  639. secure = true;
  640. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  641. if (ret == -EAGAIN)
  642. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  643. else if (ret) {
  644. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  645. /*
  646. * Force solid fill color on error. This is to prevent
  647. * smmu faults during secure session transition.
  648. */
  649. psde->is_error = true;
  650. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  651. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  652. pipe_cfg->layout.width,
  653. pipe_cfg->layout.height,
  654. pipe_cfg->layout.plane_addr[0],
  655. pipe_cfg->layout.plane_size[0],
  656. pipe_cfg->layout.plane_addr[1],
  657. pipe_cfg->layout.plane_size[1],
  658. pipe_cfg->layout.plane_addr[2],
  659. pipe_cfg->layout.plane_size[2],
  660. pipe_cfg->layout.plane_addr[3],
  661. pipe_cfg->layout.plane_size[3],
  662. pstate->multirect_index,
  663. secure);
  664. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  665. pstate->multirect_index);
  666. }
  667. }
  668. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  669. struct sde_plane_state *pstate)
  670. {
  671. struct sde_hw_scaler3_cfg *cfg;
  672. int ret = 0;
  673. if (!psde || !pstate) {
  674. SDE_ERROR("invalid args\n");
  675. return -EINVAL;
  676. }
  677. cfg = &psde->scaler3_cfg;
  678. cfg->dir_lut = msm_property_get_blob(
  679. &psde->property_info,
  680. &pstate->property_state, &cfg->dir_len,
  681. PLANE_PROP_SCALER_LUT_ED);
  682. cfg->cir_lut = msm_property_get_blob(
  683. &psde->property_info,
  684. &pstate->property_state, &cfg->cir_len,
  685. PLANE_PROP_SCALER_LUT_CIR);
  686. cfg->sep_lut = msm_property_get_blob(
  687. &psde->property_info,
  688. &pstate->property_state, &cfg->sep_len,
  689. PLANE_PROP_SCALER_LUT_SEP);
  690. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  691. ret = -ENODATA;
  692. return ret;
  693. }
  694. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  695. struct sde_plane_state *pstate)
  696. {
  697. struct sde_hw_scaler3_cfg *cfg;
  698. cfg = &psde->scaler3_cfg;
  699. cfg->sep_lut = msm_property_get_blob(
  700. &psde->property_info,
  701. &pstate->property_state, &cfg->sep_len,
  702. PLANE_PROP_SCALER_LUT_SEP);
  703. return cfg->sep_lut ? 0 : -ENODATA;
  704. }
  705. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  706. struct sde_plane_state *pstate, const struct sde_format *fmt,
  707. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  708. {
  709. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  710. struct sde_hw_scaler3_cfg *scale_cfg;
  711. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  712. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  713. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  714. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  715. chroma_subsmpl_h, chroma_subsmpl_v);
  716. return;
  717. }
  718. scale_cfg = &psde->scaler3_cfg;
  719. src_w = psde->pipe_cfg.src_rect.w;
  720. src_h = psde->pipe_cfg.src_rect.h;
  721. dst_w = psde->pipe_cfg.dst_rect.w;
  722. dst_h = psde->pipe_cfg.dst_rect.h;
  723. memset(scale_cfg, 0, sizeof(*scale_cfg));
  724. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  725. /*
  726. * For inline rotation cases, scaler config is post-rotation,
  727. * so swap the dimensions here. However, pixel extension will
  728. * need pre-rotation settings, this will be corrected below
  729. * when calculating pixel extension settings.
  730. */
  731. if (inline_rotation)
  732. swap(src_w, src_h);
  733. decimated = DECIMATED_DIMENSION(src_w,
  734. psde->pipe_cfg.horz_decimation);
  735. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  736. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  737. decimated = DECIMATED_DIMENSION(src_h,
  738. psde->pipe_cfg.vert_decimation);
  739. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  740. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  741. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  742. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  743. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  744. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  745. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  746. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  747. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  748. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  749. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  751. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  753. for (i = 0; i < SDE_MAX_PLANES; i++) {
  754. /*
  755. * For inline rotation cases with pre-downscaling enabled
  756. * set x pre-downscale value if required. Only x direction
  757. * is currently supported. Use src_h as values have been swapped
  758. * and x direction corresponds to height value.
  759. */
  760. src_h_pre_down = src_h;
  761. if (pre_down_supported && inline_rotation) {
  762. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  763. src_h_pre_down = src_h / 2;
  764. }
  765. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  766. psde->pipe_cfg.horz_decimation);
  767. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  768. psde->pipe_cfg.vert_decimation);
  769. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  770. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  771. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  772. }
  773. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  774. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  775. /* For pixel extension we need the pre-rotated orientation */
  776. if (inline_rotation) {
  777. psde->pixel_ext.num_ext_pxls_top[i] =
  778. scale_cfg->src_width[i];
  779. psde->pixel_ext.num_ext_pxls_left[i] =
  780. scale_cfg->src_height[i];
  781. } else {
  782. psde->pixel_ext.num_ext_pxls_top[i] =
  783. scale_cfg->src_height[i];
  784. psde->pixel_ext.num_ext_pxls_left[i] =
  785. scale_cfg->src_width[i];
  786. }
  787. }
  788. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  789. && (src_w == dst_w) && !inline_rotation) ||
  790. pstate->multirect_mode)
  791. return;
  792. SDE_DEBUG_PLANE(psde,
  793. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  794. src_w, src_h, dst_w, dst_h,
  795. chroma_subsmpl_v, chroma_subsmpl_h,
  796. fmt->base.pixel_format);
  797. scale_cfg->dst_width = dst_w;
  798. scale_cfg->dst_height = dst_h;
  799. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  800. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  801. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  802. scale_cfg->lut_flag = 0;
  803. scale_cfg->blend_cfg = 1;
  804. scale_cfg->enable = 1;
  805. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  806. }
  807. /**
  808. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  809. * @psde: Pointer to SDE plane object
  810. * @src: Source size
  811. * @dst: Destination size
  812. * @phase_steps: Pointer to output array for phase steps
  813. * @filter: Pointer to output array for filter type
  814. * @fmt: Pointer to format definition
  815. * @chroma_subsampling: Subsampling amount for chroma channel
  816. *
  817. * Returns: 0 on success
  818. */
  819. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  820. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  821. enum sde_hw_filter *filter, const struct sde_format *fmt,
  822. uint32_t chroma_subsampling)
  823. {
  824. if (!psde || !phase_steps || !filter || !fmt) {
  825. SDE_ERROR(
  826. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  827. !psde, !phase_steps, !filter, !fmt);
  828. return -EINVAL;
  829. }
  830. /* calculate phase steps, leave init phase as zero */
  831. phase_steps[SDE_SSPP_COMP_0] =
  832. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  833. phase_steps[SDE_SSPP_COMP_1_2] =
  834. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  835. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  836. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  837. /* calculate scaler config, if necessary */
  838. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  839. filter[SDE_SSPP_COMP_3] =
  840. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  841. SDE_SCALE_FILTER_PCMN;
  842. if (SDE_FORMAT_IS_YUV(fmt)) {
  843. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  844. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  845. } else {
  846. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  847. filter[SDE_SSPP_COMP_1_2] =
  848. SDE_SCALE_FILTER_NEAREST;
  849. }
  850. } else {
  851. /* disable scaler */
  852. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  853. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  854. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  855. }
  856. return 0;
  857. }
  858. /**
  859. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  860. * @psde: Pointer to SDE plane object
  861. * @src: Source size
  862. * @dst: Destination size
  863. * @decimated_src: Source size after decimation, if any
  864. * @phase_steps: Pointer to output array for phase steps
  865. * @out_src: Output array for pixel extension values
  866. * @out_edge1: Output array for pixel extension first edge
  867. * @out_edge2: Output array for pixel extension second edge
  868. * @filter: Pointer to array for filter type
  869. * @fmt: Pointer to format definition
  870. * @chroma_subsampling: Subsampling amount for chroma channel
  871. * @post_compare: Whether to chroma subsampled source size for comparisions
  872. */
  873. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  874. uint32_t src, uint32_t dst, uint32_t decimated_src,
  875. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  876. int *out_edge2, enum sde_hw_filter *filter,
  877. const struct sde_format *fmt, uint32_t chroma_subsampling,
  878. bool post_compare)
  879. {
  880. int64_t edge1, edge2, caf;
  881. uint32_t src_work;
  882. int i, tmp;
  883. if (psde && phase_steps && out_src && out_edge1 &&
  884. out_edge2 && filter && fmt) {
  885. /* handle CAF for YUV formats */
  886. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  887. caf = PHASE_STEP_UNIT_SCALE;
  888. else
  889. caf = 0;
  890. for (i = 0; i < SDE_MAX_PLANES; i++) {
  891. src_work = decimated_src;
  892. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  893. src_work /= chroma_subsampling;
  894. if (post_compare)
  895. src = src_work;
  896. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  897. /* unity */
  898. edge1 = 0;
  899. edge2 = 0;
  900. } else if (dst >= src) {
  901. /* upscale */
  902. edge1 = (1 << PHASE_RESIDUAL);
  903. edge1 -= caf;
  904. edge2 = (1 << PHASE_RESIDUAL);
  905. edge2 += (dst - 1) * *(phase_steps + i);
  906. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  907. edge2 += caf;
  908. edge2 = -(edge2);
  909. } else {
  910. /* downscale */
  911. edge1 = 0;
  912. edge2 = (dst - 1) * *(phase_steps + i);
  913. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  914. edge2 += *(phase_steps + i);
  915. edge2 = -(edge2);
  916. }
  917. /* only enable CAF for luma plane */
  918. caf = 0;
  919. /* populate output arrays */
  920. *(out_src + i) = src_work;
  921. /* edge updates taken from __pxl_extn_helper */
  922. if (edge1 >= 0) {
  923. tmp = (uint32_t)edge1;
  924. tmp >>= PHASE_STEP_SHIFT;
  925. *(out_edge1 + i) = -tmp;
  926. } else {
  927. tmp = (uint32_t)(-edge1);
  928. *(out_edge1 + i) =
  929. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  930. PHASE_STEP_SHIFT;
  931. }
  932. if (edge2 >= 0) {
  933. tmp = (uint32_t)edge2;
  934. tmp >>= PHASE_STEP_SHIFT;
  935. *(out_edge2 + i) = -tmp;
  936. } else {
  937. tmp = (uint32_t)(-edge2);
  938. *(out_edge2 + i) =
  939. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  940. PHASE_STEP_SHIFT;
  941. }
  942. }
  943. }
  944. }
  945. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  946. {
  947. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  948. {
  949. /* S15.16 format */
  950. 0x00012A00, 0x00000000, 0x00019880,
  951. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  952. 0x00012A00, 0x00020480, 0x00000000,
  953. },
  954. /* signed bias */
  955. { 0xfff0, 0xff80, 0xff80,},
  956. { 0x0, 0x0, 0x0,},
  957. /* unsigned clamp */
  958. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  959. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  960. };
  961. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  962. {
  963. /* S15.16 format */
  964. 0x00012A00, 0x00000000, 0x00019880,
  965. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  966. 0x00012A00, 0x00020480, 0x00000000,
  967. },
  968. /* signed bias */
  969. { 0xffc0, 0xfe00, 0xfe00,},
  970. { 0x0, 0x0, 0x0,},
  971. /* unsigned clamp */
  972. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  973. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  974. };
  975. if (!psde) {
  976. SDE_ERROR("invalid plane\n");
  977. return;
  978. }
  979. /* revert to kernel default if override not available */
  980. if (psde->csc_usr_ptr)
  981. psde->csc_ptr = psde->csc_usr_ptr;
  982. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  983. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  984. else
  985. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  986. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  987. psde->csc_ptr->csc_mv[0],
  988. psde->csc_ptr->csc_mv[1],
  989. psde->csc_ptr->csc_mv[2]);
  990. }
  991. static void sde_color_process_plane_setup(struct drm_plane *plane)
  992. {
  993. struct sde_plane *psde;
  994. struct sde_plane_state *pstate;
  995. uint32_t hue, saturation, value, contrast;
  996. struct drm_msm_memcol *memcol = NULL;
  997. struct drm_msm_3d_gamut *vig_gamut = NULL;
  998. struct drm_msm_igc_lut *igc = NULL;
  999. struct drm_msm_pgc_lut *gc = NULL;
  1000. size_t memcol_sz = 0, size = 0;
  1001. struct sde_hw_cp_cfg hw_cfg = {};
  1002. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1003. bool fp16_igc, fp16_unmult;
  1004. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1005. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1006. psde = to_sde_plane(plane);
  1007. pstate = to_sde_plane_state(plane->state);
  1008. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1009. if (psde->pipe_hw->ops.setup_pa_hue)
  1010. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1011. saturation = (uint32_t) sde_plane_get_property(pstate,
  1012. PLANE_PROP_SATURATION_ADJUST);
  1013. if (psde->pipe_hw->ops.setup_pa_sat)
  1014. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1015. value = (uint32_t) sde_plane_get_property(pstate,
  1016. PLANE_PROP_VALUE_ADJUST);
  1017. if (psde->pipe_hw->ops.setup_pa_val)
  1018. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1019. contrast = (uint32_t) sde_plane_get_property(pstate,
  1020. PLANE_PROP_CONTRAST_ADJUST);
  1021. if (psde->pipe_hw->ops.setup_pa_cont)
  1022. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1023. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1024. /* Skin memory color setup */
  1025. memcol = msm_property_get_blob(&psde->property_info,
  1026. &pstate->property_state,
  1027. &memcol_sz,
  1028. PLANE_PROP_SKIN_COLOR);
  1029. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1030. MEMCOLOR_SKIN, memcol);
  1031. /* Sky memory color setup */
  1032. memcol = msm_property_get_blob(&psde->property_info,
  1033. &pstate->property_state,
  1034. &memcol_sz,
  1035. PLANE_PROP_SKY_COLOR);
  1036. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1037. MEMCOLOR_SKY, memcol);
  1038. /* Foliage memory color setup */
  1039. memcol = msm_property_get_blob(&psde->property_info,
  1040. &pstate->property_state,
  1041. &memcol_sz,
  1042. PLANE_PROP_FOLIAGE_COLOR);
  1043. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1044. MEMCOLOR_FOLIAGE, memcol);
  1045. }
  1046. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1047. psde->pipe_hw->ops.setup_vig_gamut) {
  1048. vig_gamut = msm_property_get_blob(&psde->property_info,
  1049. &pstate->property_state,
  1050. &size,
  1051. PLANE_PROP_VIG_GAMUT);
  1052. hw_cfg.last_feature = 0;
  1053. hw_cfg.ctl = ctl;
  1054. hw_cfg.len = size;
  1055. hw_cfg.payload = vig_gamut;
  1056. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1057. }
  1058. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1059. psde->pipe_hw->ops.setup_vig_igc) {
  1060. igc = msm_property_get_blob(&psde->property_info,
  1061. &pstate->property_state,
  1062. &size,
  1063. PLANE_PROP_VIG_IGC);
  1064. hw_cfg.last_feature = 0;
  1065. hw_cfg.ctl = ctl;
  1066. hw_cfg.len = size;
  1067. hw_cfg.payload = igc;
  1068. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1069. }
  1070. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1071. psde->pipe_hw->ops.setup_dma_igc) {
  1072. igc = msm_property_get_blob(&psde->property_info,
  1073. &pstate->property_state,
  1074. &size,
  1075. PLANE_PROP_DMA_IGC);
  1076. hw_cfg.last_feature = 0;
  1077. hw_cfg.ctl = ctl;
  1078. hw_cfg.len = size;
  1079. hw_cfg.payload = igc;
  1080. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1081. pstate->multirect_index);
  1082. }
  1083. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1084. psde->pipe_hw->ops.setup_dma_gc) {
  1085. gc = msm_property_get_blob(&psde->property_info,
  1086. &pstate->property_state,
  1087. &size,
  1088. PLANE_PROP_DMA_GC);
  1089. hw_cfg.last_feature = 0;
  1090. hw_cfg.ctl = ctl;
  1091. hw_cfg.len = size;
  1092. hw_cfg.payload = gc;
  1093. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1094. pstate->multirect_index);
  1095. }
  1096. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1097. psde->pipe_hw->ops.setup_fp16_igc) {
  1098. fp16_igc = !!sde_plane_get_property(pstate,
  1099. PLANE_PROP_FP16_IGC);
  1100. hw_cfg.last_feature = 0;
  1101. hw_cfg.ctl = ctl;
  1102. hw_cfg.len = sizeof(bool);
  1103. hw_cfg.payload = &fp16_igc;
  1104. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1105. pstate->multirect_index, &hw_cfg);
  1106. }
  1107. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1108. psde->pipe_hw->ops.setup_fp16_gc) {
  1109. fp16_gc = msm_property_get_blob(&psde->property_info,
  1110. &pstate->property_state,
  1111. &size,
  1112. PLANE_PROP_FP16_GC);
  1113. hw_cfg.last_feature = 0;
  1114. hw_cfg.ctl = ctl;
  1115. hw_cfg.len = size;
  1116. hw_cfg.payload = fp16_gc;
  1117. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1118. pstate->multirect_index, &hw_cfg);
  1119. }
  1120. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1121. psde->pipe_hw->ops.setup_fp16_csc) {
  1122. fp16_csc = msm_property_get_blob(&psde->property_info,
  1123. &pstate->property_state,
  1124. &size,
  1125. PLANE_PROP_FP16_CSC);
  1126. hw_cfg.last_feature = 0;
  1127. hw_cfg.ctl = ctl;
  1128. hw_cfg.len = size;
  1129. hw_cfg.payload = fp16_csc;
  1130. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1131. pstate->multirect_index, &hw_cfg);
  1132. }
  1133. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1134. psde->pipe_hw->ops.setup_fp16_unmult) {
  1135. fp16_unmult = !!sde_plane_get_property(pstate,
  1136. PLANE_PROP_FP16_UNMULT);
  1137. hw_cfg.last_feature = 0;
  1138. hw_cfg.ctl = ctl;
  1139. hw_cfg.len = sizeof(bool);
  1140. hw_cfg.payload = &fp16_unmult;
  1141. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1142. pstate->multirect_index, &hw_cfg);
  1143. }
  1144. }
  1145. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1146. struct sde_plane_state *pstate,
  1147. const struct sde_format *fmt, bool color_fill)
  1148. {
  1149. struct sde_hw_pixel_ext *pe;
  1150. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1151. const struct drm_format_info *info = NULL;
  1152. if (!psde || !fmt || !pstate) {
  1153. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1154. !psde, !fmt, !pstate);
  1155. return;
  1156. }
  1157. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1158. sizeof(psde->scaler3_cfg));
  1159. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1160. sizeof(psde->pixel_ext));
  1161. info = drm_format_info(fmt->base.pixel_format);
  1162. pe = &psde->pixel_ext;
  1163. psde->pipe_cfg.horz_decimation =
  1164. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1165. psde->pipe_cfg.vert_decimation =
  1166. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1167. /* don't chroma subsample if decimating */
  1168. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1169. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1170. /* update scaler */
  1171. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1172. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1173. int rc = -EINVAL;
  1174. if (!color_fill && !psde->debugfs_default_scale)
  1175. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1176. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1177. _sde_plane_setup_scaler3_lut(psde, pstate);
  1178. if (rc || pstate->scaler_check_state !=
  1179. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1180. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1181. pstate->scaler_check_state,
  1182. psde->debugfs_default_scale, rc,
  1183. psde->pipe_cfg.src_rect.w,
  1184. psde->pipe_cfg.src_rect.h,
  1185. psde->pipe_cfg.dst_rect.w,
  1186. psde->pipe_cfg.dst_rect.h,
  1187. pstate->multirect_mode);
  1188. /* calculate default config for QSEED3 */
  1189. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1190. chroma_subsmpl_h, chroma_subsmpl_v);
  1191. }
  1192. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1193. color_fill || psde->debugfs_default_scale) {
  1194. uint32_t deci_dim, i;
  1195. /* calculate default configuration for QSEED2 */
  1196. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1197. SDE_DEBUG_PLANE(psde, "default config\n");
  1198. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1199. psde->pipe_cfg.horz_decimation);
  1200. _sde_plane_setup_scaler2(psde,
  1201. deci_dim,
  1202. psde->pipe_cfg.dst_rect.w,
  1203. pe->phase_step_x,
  1204. pe->horz_filter, fmt, chroma_subsmpl_h);
  1205. if (SDE_FORMAT_IS_YUV(fmt))
  1206. deci_dim &= ~0x1;
  1207. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1208. psde->pipe_cfg.dst_rect.w, deci_dim,
  1209. pe->phase_step_x,
  1210. pe->roi_w,
  1211. pe->num_ext_pxls_left,
  1212. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1213. chroma_subsmpl_h, 0);
  1214. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1215. psde->pipe_cfg.vert_decimation);
  1216. _sde_plane_setup_scaler2(psde,
  1217. deci_dim,
  1218. psde->pipe_cfg.dst_rect.h,
  1219. pe->phase_step_y,
  1220. pe->vert_filter, fmt, chroma_subsmpl_v);
  1221. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1222. psde->pipe_cfg.dst_rect.h, deci_dim,
  1223. pe->phase_step_y,
  1224. pe->roi_h,
  1225. pe->num_ext_pxls_top,
  1226. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1227. chroma_subsmpl_v, 1);
  1228. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1229. if (pe->num_ext_pxls_left[i] >= 0)
  1230. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1231. else
  1232. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1233. if (pe->num_ext_pxls_right[i] >= 0)
  1234. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1235. else
  1236. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1237. if (pe->num_ext_pxls_top[i] >= 0)
  1238. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1239. else
  1240. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1241. if (pe->num_ext_pxls_btm[i] >= 0)
  1242. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1243. else
  1244. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1245. }
  1246. }
  1247. if (psde->pipe_hw->ops.setup_pre_downscale)
  1248. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1249. &pstate->pre_down);
  1250. }
  1251. /**
  1252. * _sde_plane_color_fill - enables color fill on plane
  1253. * @psde: Pointer to SDE plane object
  1254. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1255. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1256. * Returns: 0 on success
  1257. */
  1258. static int _sde_plane_color_fill(struct sde_plane *psde,
  1259. uint32_t color, uint32_t alpha)
  1260. {
  1261. const struct sde_format *fmt;
  1262. const struct drm_plane *plane;
  1263. struct sde_plane_state *pstate;
  1264. bool blend_enable = true;
  1265. if (!psde || !psde->base.state) {
  1266. SDE_ERROR("invalid plane\n");
  1267. return -EINVAL;
  1268. }
  1269. if (!psde->pipe_hw) {
  1270. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1271. return -EINVAL;
  1272. }
  1273. plane = &psde->base;
  1274. pstate = to_sde_plane_state(plane->state);
  1275. SDE_DEBUG_PLANE(psde, "\n");
  1276. /*
  1277. * select fill format to match user property expectation,
  1278. * h/w only supports RGB variants
  1279. */
  1280. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1281. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1282. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1283. /* update sspp */
  1284. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1285. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1286. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1287. pstate->multirect_index);
  1288. /* override scaler/decimation if solid fill */
  1289. psde->pipe_cfg.src_rect.x = 0;
  1290. psde->pipe_cfg.src_rect.y = 0;
  1291. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1292. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1293. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1294. if (psde->pipe_hw->ops.setup_format)
  1295. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1296. fmt, blend_enable,
  1297. SDE_SSPP_SOLID_FILL,
  1298. pstate->multirect_index);
  1299. if (psde->pipe_hw->ops.setup_rects)
  1300. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1301. &psde->pipe_cfg,
  1302. pstate->multirect_index);
  1303. if (psde->pipe_hw->ops.setup_pe)
  1304. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1305. &psde->pixel_ext);
  1306. if (psde->pipe_hw->ops.setup_scaler &&
  1307. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1308. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1309. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1310. &psde->pipe_cfg, &psde->pixel_ext,
  1311. &psde->scaler3_cfg);
  1312. }
  1313. }
  1314. return 0;
  1315. }
  1316. /**
  1317. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1318. * @plane: Pointer to drm plane
  1319. * @state: Pointer to drm plane state to be validated
  1320. * return: 0 if success; error code otherwise
  1321. */
  1322. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1323. struct drm_plane_state *state)
  1324. {
  1325. struct sde_plane *psde;
  1326. struct sde_plane_state *pstate, *old_pstate;
  1327. int ret = 0;
  1328. u32 rotation;
  1329. if (!plane || !state) {
  1330. SDE_ERROR("invalid plane/state\n");
  1331. return -EINVAL;
  1332. }
  1333. psde = to_sde_plane(plane);
  1334. pstate = to_sde_plane_state(state);
  1335. old_pstate = to_sde_plane_state(plane->state);
  1336. /* check inline rotation and simplify the transform */
  1337. rotation = drm_rotation_simplify(
  1338. state->rotation,
  1339. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1340. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1341. if ((rotation & DRM_MODE_ROTATE_180) ||
  1342. (rotation & DRM_MODE_ROTATE_270)) {
  1343. SDE_ERROR_PLANE(psde,
  1344. "invalid rotation transform must be simplified 0x%x\n",
  1345. rotation);
  1346. ret = -EINVAL;
  1347. goto exit;
  1348. }
  1349. if (rotation & DRM_MODE_ROTATE_90) {
  1350. struct msm_drm_private *priv = plane->dev->dev_private;
  1351. struct sde_kms *sde_kms;
  1352. const struct msm_format *msm_fmt;
  1353. const struct sde_format *fmt;
  1354. struct sde_rect src;
  1355. bool q16_data = true;
  1356. POPULATE_RECT(&src, state->src_x, state->src_y,
  1357. state->src_w, state->src_h, q16_data);
  1358. /*
  1359. * DRM framework expects rotation flag in counter-clockwise
  1360. * direction and the HW expects in clockwise direction.
  1361. * Flip the flags to match with HW.
  1362. */
  1363. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1364. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1365. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1366. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1367. !psde->pipe_sblk->in_rot_maxheight ||
  1368. !psde->pipe_sblk->in_rot_format_list ||
  1369. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1370. SDE_ERROR_PLANE(psde,
  1371. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1372. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1373. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1374. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1375. !psde->pipe_sblk->in_rot_format_list,
  1376. !psde->pipe_sblk->in_rot_maxheight,
  1377. psde->features);
  1378. ret = -EINVAL;
  1379. goto exit;
  1380. }
  1381. /* check for valid height */
  1382. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1383. SDE_ERROR_PLANE(psde,
  1384. "invalid height for inline rot:%d max:%d\n",
  1385. src.h, psde->pipe_sblk->in_rot_maxheight);
  1386. ret = -EINVAL;
  1387. goto exit;
  1388. }
  1389. if (!sde_plane_enabled(state))
  1390. goto exit;
  1391. /* check for valid formats supported by inline rot */
  1392. sde_kms = to_sde_kms(priv->kms);
  1393. msm_fmt = msm_framebuffer_format(state->fb);
  1394. fmt = to_sde_format(msm_fmt);
  1395. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1396. psde->pipe_sblk->in_rot_format_list);
  1397. }
  1398. exit:
  1399. pstate->rotation = rotation;
  1400. return ret;
  1401. }
  1402. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1403. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1404. {
  1405. struct sde_plane *psde;
  1406. struct msm_drm_private *priv;
  1407. struct sde_vbif_set_xin_halt_params halt_params;
  1408. if (!plane || !plane->dev) {
  1409. SDE_ERROR("invalid arguments\n");
  1410. return false;
  1411. }
  1412. psde = to_sde_plane(plane);
  1413. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1414. SDE_ERROR("invalid pipe reference\n");
  1415. return false;
  1416. }
  1417. priv = plane->dev->dev_private;
  1418. if (!priv || !priv->kms) {
  1419. SDE_ERROR("invalid KMS reference\n");
  1420. return false;
  1421. }
  1422. memset(&halt_params, 0, sizeof(halt_params));
  1423. halt_params.vbif_idx = VBIF_RT;
  1424. halt_params.xin_id = xin_id;
  1425. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1426. halt_params.forced_on = halt_forced_clk;
  1427. halt_params.enable = enable;
  1428. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1429. }
  1430. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1431. {
  1432. struct sde_plane *psde;
  1433. if (!plane) {
  1434. SDE_ERROR("invalid plane\n");
  1435. return;
  1436. }
  1437. psde = to_sde_plane(plane);
  1438. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1439. SDE_ERROR("invalid pipe reference\n");
  1440. return;
  1441. }
  1442. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1443. psde->xin_halt_forced_clk =
  1444. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1445. psde->xin_halt_forced_clk, enable);
  1446. }
  1447. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1448. struct drm_crtc *crtc)
  1449. {
  1450. struct sde_plane *psde;
  1451. if (!plane || !crtc) {
  1452. SDE_ERROR("invalid plane/crtc\n");
  1453. return;
  1454. }
  1455. psde = to_sde_plane(plane);
  1456. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1457. return;
  1458. /* do all VBIF programming for the sec-ui allowed SSPP */
  1459. _sde_plane_set_qos_remap(plane);
  1460. _sde_plane_set_ot_limit(plane, crtc);
  1461. }
  1462. /**
  1463. * sde_plane_rot_install_properties - install plane rotator properties
  1464. * @plane: Pointer to drm plane
  1465. * @catalog: Pointer to mdss configuration
  1466. * return: none
  1467. */
  1468. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1469. struct sde_mdss_cfg *catalog)
  1470. {
  1471. struct sde_plane *psde = to_sde_plane(plane);
  1472. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1473. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1474. int ret = 0;
  1475. if (!plane || !psde) {
  1476. SDE_ERROR("invalid plane\n");
  1477. return;
  1478. } else if (!catalog) {
  1479. SDE_ERROR("invalid catalog\n");
  1480. return;
  1481. }
  1482. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1483. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1484. ret = drm_plane_create_rotation_property(plane,
  1485. DRM_MODE_ROTATE_0, supported_rotations);
  1486. if (ret) {
  1487. DRM_ERROR("create rotation property failed: %d\n", ret);
  1488. return;
  1489. }
  1490. }
  1491. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1492. {
  1493. struct sde_plane_state *pstate;
  1494. if (!drm_state)
  1495. return;
  1496. pstate = to_sde_plane_state(drm_state);
  1497. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1498. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1499. }
  1500. /**
  1501. * multi_rect validate API allows to validate only R0 and R1 RECT
  1502. * passing for each plane. Client of this API must not pass multiple
  1503. * plane which are not sharing same XIN client. Such calls will fail
  1504. * even though kernel client is passing valid multirect configuration.
  1505. */
  1506. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1507. {
  1508. struct sde_plane_state *pstate[R_MAX];
  1509. const struct drm_plane_state *drm_state[R_MAX];
  1510. struct sde_rect src[R_MAX], dst[R_MAX];
  1511. struct sde_plane *sde_plane[R_MAX];
  1512. const struct sde_format *fmt[R_MAX];
  1513. int xin_id[R_MAX];
  1514. bool q16_data = true;
  1515. int i, j, buffer_lines, width_threshold[R_MAX];
  1516. unsigned int max_tile_height = 1;
  1517. bool parallel_fetch_qualified = true;
  1518. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1519. const struct msm_format *msm_fmt;
  1520. bool const_alpha_enable = true;
  1521. for (i = 0; i < R_MAX; i++) {
  1522. drm_state[i] = i ? plane->r1 : plane->r0;
  1523. if (!drm_state[i]) {
  1524. SDE_ERROR("drm plane state is NULL\n");
  1525. return -EINVAL;
  1526. }
  1527. pstate[i] = to_sde_plane_state(drm_state[i]);
  1528. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1529. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1530. for (j = 0; j < i; j++) {
  1531. if (xin_id[i] != xin_id[j]) {
  1532. SDE_ERROR_PLANE(sde_plane[i],
  1533. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1534. j, xin_id[j], i, xin_id[i]);
  1535. return -EINVAL;
  1536. }
  1537. }
  1538. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1539. if (!msm_fmt) {
  1540. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1541. return -EINVAL;
  1542. }
  1543. fmt[i] = to_sde_format(msm_fmt);
  1544. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1545. (fmt[i]->tile_height > max_tile_height))
  1546. max_tile_height = fmt[i]->tile_height;
  1547. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1548. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1549. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1550. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1551. drm_state[i]->crtc_h, !q16_data);
  1552. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1553. SDE_ERROR_PLANE(sde_plane[i],
  1554. "scaling is not supported in multirect mode\n");
  1555. return -EINVAL;
  1556. }
  1557. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1558. SDE_ERROR_PLANE(sde_plane[i],
  1559. "inline rotation is not supported in mulirect mode\n");
  1560. return -EINVAL;
  1561. }
  1562. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1563. SDE_ERROR_PLANE(sde_plane[i],
  1564. "Unsupported format for multirect mode\n");
  1565. return -EINVAL;
  1566. }
  1567. /**
  1568. * SSPP PD_MEM is split half - one for each RECT.
  1569. * Tiled formats need 5 lines of buffering while fetching
  1570. * whereas linear formats need only 2 lines.
  1571. * So we cannot support more than half of the supported SSPP
  1572. * width for tiled formats.
  1573. */
  1574. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1575. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1576. width_threshold[i] /= 2;
  1577. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1578. parallel_fetch_qualified = false;
  1579. if (sde_plane[i]->is_virtual)
  1580. mode = sde_plane_get_property(pstate[i],
  1581. PLANE_PROP_MULTIRECT_MODE);
  1582. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1583. const_alpha_enable = false;
  1584. }
  1585. buffer_lines = 2 * max_tile_height;
  1586. /**
  1587. * fallback to driver mode selection logic if client is using
  1588. * multirect plane without setting property.
  1589. *
  1590. * validate multirect mode configuration based on rectangle
  1591. */
  1592. switch (mode) {
  1593. case SDE_SSPP_MULTIRECT_NONE:
  1594. if (parallel_fetch_qualified)
  1595. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1596. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1597. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1598. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1599. else
  1600. SDE_ERROR(
  1601. "planes(%d - %d) multirect mode selection fail\n",
  1602. drm_state[R0]->plane->base.id,
  1603. drm_state[R1]->plane->base.id);
  1604. break;
  1605. case SDE_SSPP_MULTIRECT_PARALLEL:
  1606. if (!parallel_fetch_qualified) {
  1607. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1608. drm_state[R0]->plane->base.id,
  1609. width_threshold[R0], src[R0].w);
  1610. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1611. drm_state[R1]->plane->base.id,
  1612. width_threshold[R1], src[R1].w);
  1613. SDE_ERROR("parallel fetch not qualified\n");
  1614. mode = SDE_SSPP_MULTIRECT_NONE;
  1615. }
  1616. break;
  1617. case SDE_SSPP_MULTIRECT_TIME_MX:
  1618. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1619. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1620. SDE_ERROR(
  1621. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1622. buffer_lines, drm_state[R0]->plane->base.id,
  1623. dst[R0].y, dst[R0].h);
  1624. SDE_ERROR(
  1625. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1626. buffer_lines, drm_state[R1]->plane->base.id,
  1627. dst[R1].y, dst[R1].h);
  1628. SDE_ERROR("time multiplexed fetch not qualified\n");
  1629. mode = SDE_SSPP_MULTIRECT_NONE;
  1630. }
  1631. break;
  1632. default:
  1633. SDE_ERROR("bad mode:%d selection\n", mode);
  1634. mode = SDE_SSPP_MULTIRECT_NONE;
  1635. break;
  1636. }
  1637. for (i = 0; i < R_MAX; i++) {
  1638. pstate[i]->multirect_mode = mode;
  1639. pstate[i]->const_alpha_en = const_alpha_enable;
  1640. }
  1641. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1642. return -EINVAL;
  1643. if (sde_plane[R0]->is_virtual) {
  1644. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1645. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1646. } else {
  1647. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1648. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1649. }
  1650. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1651. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1652. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1653. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1654. return 0;
  1655. }
  1656. /**
  1657. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1658. * @plane: Pointer to drm plane structure
  1659. * @ctl: Pointer to hardware control driver
  1660. * @set: set if true else clear
  1661. */
  1662. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1663. bool set)
  1664. {
  1665. if (!plane || !ctl) {
  1666. SDE_ERROR("invalid parameters\n");
  1667. return;
  1668. }
  1669. if (!ctl->ops.update_bitmask_sspp) {
  1670. SDE_ERROR("invalid ops\n");
  1671. return;
  1672. }
  1673. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1674. }
  1675. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1676. struct drm_plane_state *new_state)
  1677. {
  1678. struct drm_framebuffer *fb = new_state->fb;
  1679. struct sde_plane *psde = to_sde_plane(plane);
  1680. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1681. struct sde_hw_fmt_layout layout;
  1682. struct msm_gem_address_space *aspace;
  1683. int ret;
  1684. if (!fb)
  1685. return 0;
  1686. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1687. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1688. if (ret) {
  1689. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1690. return ret;
  1691. }
  1692. /* cache aspace */
  1693. pstate->aspace = aspace;
  1694. /*
  1695. * when transitioning from secure to non-secure,
  1696. * plane->prepare_fb happens before the commit. In such case,
  1697. * defer the prepare_fb and handled it late, during the commit
  1698. * after attaching the domains as part of the transition
  1699. */
  1700. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1701. true : false;
  1702. if (pstate->defer_prepare_fb) {
  1703. SDE_EVT32(DRMID(plane), psde->pipe);
  1704. SDE_DEBUG_PLANE(psde,
  1705. "domain not attached, prepare_fb handled later\n");
  1706. return 0;
  1707. }
  1708. if (pstate->aspace && fb) {
  1709. ret = msm_framebuffer_prepare(fb,
  1710. pstate->aspace);
  1711. if (ret) {
  1712. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1713. fb->base.id, plane->base.id, psde->pipe, ret);
  1714. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1715. return ret;
  1716. }
  1717. }
  1718. /* validate framebuffer layout before commit */
  1719. ret = sde_format_populate_layout(pstate->aspace,
  1720. fb, &layout);
  1721. if (ret) {
  1722. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1723. return ret;
  1724. }
  1725. return 0;
  1726. }
  1727. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1728. struct drm_plane_state *old_state)
  1729. {
  1730. struct sde_plane *psde = to_sde_plane(plane);
  1731. struct sde_plane_state *old_pstate;
  1732. if (!old_state || !old_state->fb || !plane)
  1733. return;
  1734. old_pstate = to_sde_plane_state(old_state);
  1735. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1736. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1737. }
  1738. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1739. struct drm_plane_state *state,
  1740. struct drm_plane_state *old_state)
  1741. {
  1742. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1743. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1744. struct drm_framebuffer *fb, *old_fb;
  1745. /* no need to check it again */
  1746. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1747. return;
  1748. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1749. || psde->is_error) {
  1750. SDE_DEBUG_PLANE(psde,
  1751. "enabling/disabling full modeset required\n");
  1752. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1753. } else if (to_sde_plane_state(old_state)->pending) {
  1754. SDE_DEBUG_PLANE(psde, "still pending\n");
  1755. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1756. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1757. pstate->multirect_mode != old_pstate->multirect_mode) {
  1758. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1759. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1760. } else if (state->src_w != old_state->src_w ||
  1761. state->src_h != old_state->src_h ||
  1762. state->src_x != old_state->src_x ||
  1763. state->src_y != old_state->src_y) {
  1764. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1765. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1766. } else if (state->crtc_w != old_state->crtc_w ||
  1767. state->crtc_h != old_state->crtc_h ||
  1768. state->crtc_x != old_state->crtc_x ||
  1769. state->crtc_y != old_state->crtc_y) {
  1770. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1771. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1772. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1773. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1774. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1775. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1776. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1777. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1778. } else if (pstate->rotation != old_pstate->rotation) {
  1779. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1780. pstate->rotation, old_pstate->rotation);
  1781. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1782. }
  1783. fb = state->fb;
  1784. old_fb = old_state->fb;
  1785. if (!fb || !old_fb) {
  1786. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1787. } else if ((fb->format->format != old_fb->format->format) ||
  1788. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1789. SDE_DEBUG_PLANE(psde, "format change\n");
  1790. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1791. } else {
  1792. uint64_t new_mod = fb->modifier;
  1793. uint64_t old_mod = old_fb->modifier;
  1794. uint32_t *new_pitches = fb->pitches;
  1795. uint32_t *old_pitches = old_fb->pitches;
  1796. uint32_t *new_offset = fb->offsets;
  1797. uint32_t *old_offset = old_fb->offsets;
  1798. int i;
  1799. if (new_mod != old_mod) {
  1800. SDE_DEBUG_PLANE(psde,
  1801. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1802. new_mod, old_mod);
  1803. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1804. SDE_PLANE_DIRTY_RECTS;
  1805. }
  1806. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1807. if (new_pitches[i] != old_pitches[i]) {
  1808. SDE_DEBUG_PLANE(psde,
  1809. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1810. i, old_pitches[i], new_pitches[i]);
  1811. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1812. break;
  1813. }
  1814. }
  1815. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1816. if (new_offset[i] != old_offset[i]) {
  1817. SDE_DEBUG_PLANE(psde,
  1818. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1819. i, old_offset[i], new_offset[i]);
  1820. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1821. SDE_PLANE_DIRTY_RECTS;
  1822. break;
  1823. }
  1824. }
  1825. }
  1826. }
  1827. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1828. unsigned long base_addr, u32 size)
  1829. {
  1830. int ret = -EINVAL;
  1831. u32 addr;
  1832. struct sde_plane *psde = to_sde_plane(plane);
  1833. if (!psde || !base_addr || !size) {
  1834. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1835. return ret;
  1836. }
  1837. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1838. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1839. is_sde_plane_virtual(plane));
  1840. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1841. ret = 0;
  1842. }
  1843. return ret;
  1844. }
  1845. static inline bool _sde_plane_is_pre_downscale_enabled(
  1846. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1847. {
  1848. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1849. }
  1850. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1851. struct sde_plane_state *pstate,
  1852. const struct sde_format *fmt,
  1853. uint32_t img_w, uint32_t img_h,
  1854. uint32_t src_w, uint32_t src_h,
  1855. uint32_t deci_w, uint32_t deci_h)
  1856. {
  1857. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1858. bool pre_down_en;
  1859. int i;
  1860. if (!psde || !pstate || !fmt) {
  1861. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1862. return -EINVAL;
  1863. }
  1864. if (psde->debugfs_default_scale ||
  1865. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1866. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1867. return 0;
  1868. pd_cfg = &pstate->pre_down;
  1869. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1870. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1871. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1872. uint32_t hor_req_pixels, hor_fetch_pixels;
  1873. uint32_t vert_req_pixels, vert_fetch_pixels;
  1874. uint32_t src_w_tmp, src_h_tmp;
  1875. uint32_t scaler_w, scaler_h;
  1876. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1877. bool rot;
  1878. /* re-use color plane 1's config for plane 2 */
  1879. if (i == 2)
  1880. continue;
  1881. if (pre_down_en) {
  1882. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1883. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1884. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1885. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1886. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1887. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1888. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1889. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1890. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1891. i, pre_down_ratio_x, pre_down_ratio_y);
  1892. }
  1893. src_w_tmp = src_w;
  1894. src_h_tmp = src_h;
  1895. /*
  1896. * For chroma plane, width is half for the following sub sampled
  1897. * formats. Except in case of decimation, where hardware avoids
  1898. * 1 line of decimation instead of downsampling.
  1899. */
  1900. if (i == 1) {
  1901. if (!deci_w &&
  1902. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1903. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1904. src_w_tmp >>= 1;
  1905. if (!deci_h &&
  1906. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1907. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1908. src_h_tmp >>= 1;
  1909. }
  1910. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1911. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1912. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1913. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1914. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1915. deci_w);
  1916. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1917. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1918. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1919. deci_h);
  1920. if ((hor_req_pixels != hor_fetch_pixels) ||
  1921. (hor_fetch_pixels > img_w) ||
  1922. (vert_req_pixels != vert_fetch_pixels) ||
  1923. (vert_fetch_pixels > img_h)) {
  1924. SDE_ERROR_PLANE(psde,
  1925. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1926. hor_req_pixels, vert_req_pixels,
  1927. hor_fetch_pixels, vert_fetch_pixels,
  1928. img_w, img_h);
  1929. return -EINVAL;
  1930. }
  1931. /*
  1932. * swap the scaler src width & height for inline-rotation 90
  1933. * comparison with Pixel-Extension, as PE is based on
  1934. * pre-rotation and QSEED is based on post-rotation
  1935. */
  1936. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1937. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1938. : pstate->scaler3_cfg.src_width[i];
  1939. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1940. : pstate->scaler3_cfg.src_height[i];
  1941. /*
  1942. * Alpha plane can only be scaled using bilinear or pixel
  1943. * repeat/drop, src_width and src_height are only specified
  1944. * for Y and UV plane
  1945. */
  1946. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1947. vert_req_pixels / pre_down_ratio_y !=
  1948. scaler_h)) {
  1949. SDE_ERROR_PLANE(psde,
  1950. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1951. i, pstate->pixel_ext.roi_w[i],
  1952. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1953. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1954. return -EINVAL;
  1955. }
  1956. /*
  1957. * SSPP fetch , unpack output and QSEED3 input lines need
  1958. * to match for Y plane
  1959. */
  1960. if (i == 0 &&
  1961. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1962. BIT(SDE_DRM_DEINTERLACE)) &&
  1963. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1964. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1965. SDE_ERROR_PLANE(psde,
  1966. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1967. i, pstate->pixel_ext.roi_w[i],
  1968. pstate->pixel_ext.roi_h[i],
  1969. pstate->scaler3_cfg.src_width[i],
  1970. pstate->scaler3_cfg.src_height[i],
  1971. src_w, src_h);
  1972. return -EINVAL;
  1973. }
  1974. }
  1975. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1976. return 0;
  1977. }
  1978. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1979. {
  1980. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1981. }
  1982. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1983. struct sde_plane_state *pstate, struct sde_rect *dst,
  1984. u32 src_w, u32 src_h)
  1985. {
  1986. int ret = 0;
  1987. u32 min_ratio_numer, min_ratio_denom;
  1988. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1989. bool pd_x;
  1990. bool pd_y;
  1991. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1992. return ret;
  1993. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1994. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1995. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1996. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1997. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1998. SDE_ERROR_PLANE(psde,
  1999. "hw does not support pre-downscale X: 0x%x\n",
  2000. psde->features);
  2001. ret = -EINVAL;
  2002. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2003. SDE_ERROR_PLANE(psde,
  2004. "hw does not support pre-downscale Y: 0x%x\n",
  2005. psde->features);
  2006. ret = -EINVAL;
  2007. } else if (!min_ratio_numer || !min_ratio_denom) {
  2008. SDE_ERROR_PLANE(psde,
  2009. "min downscale ratio not set! %u / %u\n",
  2010. min_ratio_numer, min_ratio_denom);
  2011. ret = -EINVAL;
  2012. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2013. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2014. min_ratio_denom))) {
  2015. SDE_ERROR_PLANE(psde,
  2016. "failed min downscale-x check %u->%u, %u/%u\n",
  2017. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2018. ret = -EINVAL;
  2019. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2020. min_ratio_denom))) {
  2021. SDE_ERROR_PLANE(psde,
  2022. "failed min downscale-y check %u->%u, %u/%u\n",
  2023. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2024. ret = -EINVAL;
  2025. }
  2026. return ret;
  2027. }
  2028. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2029. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2030. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2031. u32 *max_numer_h, u32 *max_denom_h)
  2032. {
  2033. bool rotated, has_predown, default_scale;
  2034. const struct sde_sspp_sub_blks *sblk;
  2035. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2036. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2037. sblk = psde->pipe_sblk;
  2038. *max_numer_w = sblk->maxdwnscale;
  2039. *max_denom_w = 1;
  2040. *max_numer_h = sblk->maxdwnscale;
  2041. *max_denom_h = 1;
  2042. has_predown = _sde_plane_has_pre_downscale(psde);
  2043. if (has_predown)
  2044. pd = &pstate->pre_down;
  2045. default_scale = psde->debugfs_default_scale ||
  2046. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2047. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2048. /**
  2049. * Inline rotation has different max vertical downscaling limits since
  2050. * the source-width becomes the scaler's pre-downscaled source-height.
  2051. **/
  2052. if (rotated) {
  2053. if (pd != NULL && rt_client && has_predown) {
  2054. if (default_scale)
  2055. pd->pre_downscale_x_0 = (src_h >
  2056. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2057. *max_numer_h = pd->pre_downscale_x_0 ?
  2058. sblk->in_rot_maxdwnscale_rt_num :
  2059. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2060. *max_denom_h = pd->pre_downscale_x_0 ?
  2061. sblk->in_rot_maxdwnscale_rt_denom :
  2062. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2063. } else if (rt_client) {
  2064. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2065. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2066. } else {
  2067. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2068. }
  2069. }
  2070. }
  2071. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2072. struct sde_plane *psde, const struct sde_format *fmt,
  2073. struct sde_plane_state *pstate, struct sde_rect *src,
  2074. struct sde_rect *dst, u32 width, u32 height)
  2075. {
  2076. int ret = 0;
  2077. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2078. uint32_t scaler_src_w, scaler_src_h;
  2079. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2080. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2081. uint32_t max_upscale, max_linewidth;
  2082. bool inline_rotation, rt_client;
  2083. struct drm_crtc *crtc;
  2084. struct drm_crtc_state *new_cstate;
  2085. const struct sde_sspp_sub_blks *sblk;
  2086. if (!state || !state->state || !state->crtc) {
  2087. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2088. return -EINVAL;
  2089. }
  2090. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2091. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2092. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2093. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2094. /* with inline rotator, the source of the scaler is post-rotated */
  2095. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2096. if (inline_rotation) {
  2097. scaler_src_w = src_deci_h;
  2098. scaler_src_h = src_deci_w;
  2099. } else {
  2100. scaler_src_w = src_deci_w;
  2101. scaler_src_h = src_deci_h;
  2102. }
  2103. sblk = psde->pipe_sblk;
  2104. max_upscale = sblk->maxupscale;
  2105. if (inline_rotation)
  2106. max_linewidth = sblk->in_rot_maxheight;
  2107. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2108. max_linewidth = sblk->scaling_linewidth;
  2109. else
  2110. max_linewidth = sblk->maxlinewidth;
  2111. crtc = state->crtc;
  2112. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2113. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2114. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2115. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2116. &max_downscale_num_h, &max_downscale_denom_h);
  2117. /* decimation validation */
  2118. if ((deci_w || deci_h)
  2119. && ((deci_w > sblk->maxhdeciexp)
  2120. || (deci_h > sblk->maxvdeciexp))) {
  2121. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2122. ret = -EINVAL;
  2123. } else if ((deci_w || deci_h)
  2124. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2125. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2126. ret = -EINVAL;
  2127. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2128. ((src->w != dst->w) || (src->h != dst->h))) {
  2129. SDE_ERROR_PLANE(psde,
  2130. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2131. src->w, src->h, dst->w, dst->h);
  2132. ret = -EINVAL;
  2133. /* check scaler source width */
  2134. } else if (scaler_src_w > max_linewidth) {
  2135. SDE_ERROR_PLANE(psde,
  2136. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2137. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2138. ret = -E2BIG;
  2139. /* check max scaler capability */
  2140. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2141. ((scaler_src_h * max_upscale) < dst->h) ||
  2142. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2143. < scaler_src_w) ||
  2144. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2145. < scaler_src_h)) {
  2146. SDE_ERROR_PLANE(psde,
  2147. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2148. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2149. inline_rotation, max_downscale_num_w,
  2150. max_downscale_denom_w, max_downscale_num_h,
  2151. max_downscale_denom_h);
  2152. ret = -E2BIG;
  2153. /* check inline pre-downscale support */
  2154. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2155. pstate, dst, src_deci_w, src_deci_h)) {
  2156. ret = -EINVAL;
  2157. /* QSEED validation */
  2158. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2159. width, height, src->w, src->h,
  2160. deci_w, deci_h)) {
  2161. ret = -EINVAL;
  2162. }
  2163. return ret;
  2164. }
  2165. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2166. struct sde_plane_state *pstate, struct sde_rect *src,
  2167. const struct sde_format *fmt, int ret)
  2168. {
  2169. /* check excl rect configs */
  2170. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2171. struct sde_rect intersect;
  2172. /*
  2173. * Check exclusion rect against src rect.
  2174. * it must intersect with source rect.
  2175. */
  2176. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2177. if (intersect.w != pstate->excl_rect.w ||
  2178. intersect.h != pstate->excl_rect.h ||
  2179. SDE_FORMAT_IS_YUV(fmt)) {
  2180. SDE_ERROR_PLANE(psde,
  2181. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2182. pstate->excl_rect.x, pstate->excl_rect.y,
  2183. pstate->excl_rect.w, pstate->excl_rect.h,
  2184. src->x, src->y, src->w, src->h,
  2185. (char *)&fmt->base.pixel_format);
  2186. ret = -EINVAL;
  2187. }
  2188. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2189. pstate->excl_rect.x, pstate->excl_rect.y,
  2190. pstate->excl_rect.w, pstate->excl_rect.h);
  2191. }
  2192. return ret;
  2193. }
  2194. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2195. struct drm_plane_state *state)
  2196. {
  2197. struct sde_kms *sde_kms;
  2198. struct sde_splash_display *splash_display;
  2199. int i;
  2200. sde_kms = _sde_plane_get_kms(&psde->base);
  2201. if (!sde_kms || !state->crtc)
  2202. return 0;
  2203. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2204. splash_display = &sde_kms->splash_data.splash_display[i];
  2205. if (splash_display && splash_display->cont_splash_enabled &&
  2206. splash_display->encoder &&
  2207. state->crtc != splash_display->encoder->crtc) {
  2208. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2209. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2210. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2211. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2212. psde->pipe,
  2213. splash_display->encoder->crtc->base.id);
  2214. return -EINVAL;
  2215. }
  2216. }
  2217. }
  2218. return 0;
  2219. }
  2220. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2221. const struct sde_format *fmt,
  2222. struct sde_rect src, struct sde_rect dst,
  2223. u32 width, u32 height)
  2224. {
  2225. int ret = 0;
  2226. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2227. if (SDE_FORMAT_IS_YUV(fmt) &&
  2228. (!(psde->features & SDE_SSPP_SCALER) ||
  2229. !(psde->features & (BIT(SDE_SSPP_CSC)
  2230. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2231. SDE_ERROR_PLANE(psde,
  2232. "plane doesn't have scaler/csc for yuv\n");
  2233. ret = -EINVAL;
  2234. /* check src bounds */
  2235. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2236. src.w < min_src_size || src.h < min_src_size ||
  2237. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2238. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2239. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2240. src.x, src.y, src.w, src.h);
  2241. ret = -E2BIG;
  2242. /* valid yuv image */
  2243. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2244. (src.w & 0x1) || (src.h & 0x1))) {
  2245. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2246. src.x, src.y, src.w, src.h);
  2247. ret = -EINVAL;
  2248. /* min dst support */
  2249. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2250. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2251. dst.x, dst.y, dst.w, dst.h);
  2252. ret = -EINVAL;
  2253. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2254. !psde->catalog->ubwc_rev) {
  2255. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2256. ret = -EINVAL;
  2257. }
  2258. return ret;
  2259. }
  2260. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2261. struct drm_plane_state *state)
  2262. {
  2263. int ret = 0;
  2264. struct sde_plane *psde;
  2265. struct sde_plane_state *pstate;
  2266. const struct msm_format *msm_fmt;
  2267. const struct sde_format *fmt;
  2268. struct sde_rect src, dst;
  2269. bool q16_data = true;
  2270. struct drm_framebuffer *fb;
  2271. u32 width;
  2272. u32 height;
  2273. psde = to_sde_plane(plane);
  2274. pstate = to_sde_plane_state(state);
  2275. if (!psde->pipe_sblk) {
  2276. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2277. return -EINVAL;
  2278. }
  2279. /* src values are in Q16 fixed point, convert to integer */
  2280. POPULATE_RECT(&src, state->src_x, state->src_y,
  2281. state->src_w, state->src_h, q16_data);
  2282. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2283. state->crtc_h, !q16_data);
  2284. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2285. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2286. if (!sde_plane_enabled(state))
  2287. goto modeset_update;
  2288. fb = state->fb;
  2289. width = fb ? state->fb->width : 0x0;
  2290. height = fb ? state->fb->height : 0x0;
  2291. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2292. plane->base.id,
  2293. pstate->rotation,
  2294. width, height,
  2295. fb ? (char *) &state->fb->format->format : 0x0,
  2296. fb ? state->fb->modifier : 0x0);
  2297. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2298. state->src_w >> 16, state->src_h >> 16,
  2299. state->src_x >> 16, state->src_y >> 16,
  2300. state->crtc_w, state->crtc_h,
  2301. state->crtc_x, state->crtc_y);
  2302. msm_fmt = msm_framebuffer_format(fb);
  2303. fmt = to_sde_format(msm_fmt);
  2304. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2305. height);
  2306. if (ret)
  2307. return ret;
  2308. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2309. &src, &dst, width, height);
  2310. if (ret)
  2311. return ret;
  2312. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2313. &src, fmt, ret);
  2314. if (ret)
  2315. return ret;
  2316. ret = _sde_plane_validate_shared_crtc(psde, state);
  2317. if (ret)
  2318. return ret;
  2319. pstate->const_alpha_en = fmt->alpha_enable &&
  2320. (SDE_DRM_BLEND_OP_OPAQUE !=
  2321. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2322. (pstate->stage != SDE_STAGE_0);
  2323. modeset_update:
  2324. if (!ret)
  2325. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2326. state, plane->state);
  2327. return ret;
  2328. }
  2329. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2330. struct drm_plane_state *state)
  2331. {
  2332. int ret = 0;
  2333. struct sde_plane *psde;
  2334. struct sde_plane_state *pstate;
  2335. psde = to_sde_plane(plane);
  2336. pstate = to_sde_plane_state(state);
  2337. SDE_DEBUG_PLANE(psde, "\n");
  2338. ret = sde_plane_rot_atomic_check(plane, state);
  2339. if (ret)
  2340. goto exit;
  2341. ret = sde_plane_sspp_atomic_check(plane, state);
  2342. exit:
  2343. return ret;
  2344. }
  2345. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2346. static int sde_plane_atomic_check(struct drm_plane *plane,
  2347. struct drm_atomic_state *atomic_state)
  2348. {
  2349. struct drm_plane_state *state = NULL;
  2350. if (!plane || !atomic_state) {
  2351. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2352. !plane, !atomic_state);
  2353. return -EINVAL;
  2354. }
  2355. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2356. return _sde_plane_atomic_check(plane, state);
  2357. }
  2358. #else
  2359. static int sde_plane_atomic_check(struct drm_plane *plane,
  2360. struct drm_plane_state *state)
  2361. {
  2362. if (!plane || !state) {
  2363. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2364. !plane, !state);
  2365. return -EINVAL;
  2366. }
  2367. return _sde_plane_atomic_check(plane, state);
  2368. }
  2369. #endif
  2370. void sde_plane_flush(struct drm_plane *plane)
  2371. {
  2372. struct sde_plane *psde;
  2373. struct sde_plane_state *pstate;
  2374. if (!plane || !plane->state) {
  2375. SDE_ERROR("invalid plane\n");
  2376. return;
  2377. }
  2378. psde = to_sde_plane(plane);
  2379. pstate = to_sde_plane_state(plane->state);
  2380. /*
  2381. * These updates have to be done immediately before the plane flush
  2382. * timing, and may not be moved to the atomic_update/mode_set functions.
  2383. */
  2384. if (psde->is_error)
  2385. /* force white frame with 100% alpha pipe output on error */
  2386. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2387. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2388. /* force 100% alpha */
  2389. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2390. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2391. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2392. /* flag h/w flush complete */
  2393. if (plane->state)
  2394. pstate->pending = false;
  2395. }
  2396. /**
  2397. * sde_plane_set_error: enable/disable error condition
  2398. * @plane: pointer to drm_plane structure
  2399. */
  2400. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2401. {
  2402. struct sde_plane *psde;
  2403. if (!plane)
  2404. return;
  2405. psde = to_sde_plane(plane);
  2406. psde->is_error = error;
  2407. }
  2408. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2409. struct sde_plane_state *pstate)
  2410. {
  2411. struct drm_plane_state *state = psde->base.state;
  2412. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2413. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2414. bool prev_rd_en = cfg->rd_en;
  2415. u32 cache_flag, cache_rd_type, cache_wr_type;
  2416. enum sde_sys_cache_state cache_state;
  2417. if (!state->fb) {
  2418. SDE_ERROR("invalid fb on plane %d\n", DRMID(&psde->base));
  2419. return;
  2420. }
  2421. cache_state = pstate->static_cache_state;
  2422. msm_framebuffer_get_cache_hint(state->fb, &cache_flag, &cache_rd_type, &cache_wr_type);
  2423. cfg->rd_en = false;
  2424. cfg->rd_scid = 0x0;
  2425. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2426. /*
  2427. * if condition handles static display legacy path, where internal state machine is
  2428. * transitioning the "cache_state" variable to program the LLCC cache through
  2429. * SSPP hardware using SDE_SYS_CACHE_DISP SCID.
  2430. * else condition handles static display and IWE path, were the frame is programmed to
  2431. * LLCC cache through WB/CWB path and read back by SSPP hardware. The FB cache hints are
  2432. * used to pass information on which SCID to use during read path and LLCC cache to
  2433. * keep active.
  2434. */
  2435. if (test_bit(SDE_SYS_CACHE_DISP, psde->catalog->sde_sys_cache_type_map)
  2436. && ((cache_state == CACHE_STATE_FRAME_WRITE)
  2437. || (cache_state == CACHE_STATE_FRAME_READ))) {
  2438. cfg->type = pstate->static_cache_type;
  2439. cfg->rd_en = true;
  2440. cfg->rd_scid = sc_cfg[cfg->type].llcc_scid;
  2441. if (test_bit(SDE_FEATURE_SYS_CACHE_NSE, psde->catalog->features)) {
  2442. cfg->rd_noallocate = false;
  2443. pstate->static_cache_state = CACHE_STATE_NORMAL;
  2444. } else {
  2445. cfg->rd_noallocate = (cache_state == CACHE_STATE_FRAME_READ);
  2446. }
  2447. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2448. } else if (test_bit(cache_rd_type, psde->catalog->sde_sys_cache_type_map) && cache_flag) {
  2449. cfg->rd_en = true;
  2450. cfg->type = cache_rd_type;
  2451. cfg->rd_scid = sc_cfg[cache_rd_type].llcc_scid;
  2452. cfg->rd_noallocate = false;
  2453. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2454. cache_flag = MSM_FB_CACHE_READ_EN;
  2455. msm_framebuffer_set_cache_hint(state->fb, cache_flag, cache_rd_type, cache_wr_type);
  2456. }
  2457. if (!cfg->rd_en && !prev_rd_en)
  2458. return;
  2459. SDE_EVT32(DRMID(&psde->base), cfg->type, cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate,
  2460. cfg->flags, cache_state, cache_flag, cache_rd_type, cache_wr_type,
  2461. state->fb->base.id);
  2462. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2463. }
  2464. void sde_plane_static_img_control(struct drm_plane *plane,
  2465. enum sde_sys_cache_state state, enum sde_sys_cache_type type)
  2466. {
  2467. struct sde_plane *psde;
  2468. struct sde_plane_state *pstate;
  2469. if (!plane || !plane->state) {
  2470. SDE_ERROR("invalid plane\n");
  2471. return;
  2472. }
  2473. psde = to_sde_plane(plane);
  2474. pstate = to_sde_plane_state(plane->state);
  2475. pstate->static_cache_state = state;
  2476. pstate->static_cache_type = type;
  2477. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2478. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2479. }
  2480. static void _sde_plane_map_prop_to_dirty_bits(void)
  2481. {
  2482. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2483. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2484. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2485. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2486. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2487. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2488. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2489. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2490. plane_prop_array[PLANE_PROP_ZPOS] =
  2491. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2492. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2493. SDE_PLANE_DIRTY_RECTS;
  2494. plane_prop_array[PLANE_PROP_CSC_V1] =
  2495. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2496. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2497. SDE_PLANE_DIRTY_FORMAT;
  2498. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2499. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2500. SDE_PLANE_DIRTY_ALL;
  2501. /* no special action required */
  2502. plane_prop_array[PLANE_PROP_INFO] =
  2503. plane_prop_array[PLANE_PROP_ALPHA] =
  2504. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2505. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2506. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2507. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2508. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2509. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2510. SDE_PLANE_DIRTY_PERF;
  2511. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2512. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2513. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2514. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2515. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2516. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2517. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2518. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2519. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2520. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2521. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2522. SDE_PLANE_DIRTY_ALL;
  2523. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2524. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2525. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2526. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2527. }
  2528. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2529. struct sde_rect *src, struct sde_rect *dst)
  2530. {
  2531. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2532. u32 downscale = (src->h * 1000)/dst->h;
  2533. return (downscale > max_downscale) ? false : true;
  2534. }
  2535. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2536. struct sde_plane *psde, struct sde_plane_state *pstate,
  2537. struct sde_rect *src, struct sde_rect *dst)
  2538. {
  2539. struct sde_hw_pipe_uidle_cfg cfg;
  2540. u32 line_time = sde_crtc_get_line_time(crtc);
  2541. u32 fal1_target_idle_time_ns =
  2542. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2543. u32 fal10_target_idle_time_ns =
  2544. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2545. u32 fal10_threshold =
  2546. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2547. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2548. fal1_target_idle_time_ns) {
  2549. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2550. cfg.fal10_threshold = fal10_threshold;
  2551. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2552. cfg.fal1_threshold = min(1 +
  2553. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2554. psde->catalog->uidle_cfg.fal1_max_threshold);
  2555. cfg.fal_allowed_threshold = fal10_threshold +
  2556. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2557. cfg.fill_level_scale = 0;
  2558. /*
  2559. * if uidle fill scale is supported, determing the scale value
  2560. * and adjust fal10 thresholds to their scaled values.
  2561. * fal1 thresholds and fal_allowed are not scaled.
  2562. */
  2563. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2564. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2565. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2566. u32 fl_scale = fl_require / fal10_threshold;
  2567. u32 fal10_threshold_noscale;
  2568. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2569. if (cfg.fill_level_scale) {
  2570. fal10_threshold_noscale = fal10_threshold *
  2571. 32/cfg.fill_level_scale;
  2572. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2573. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2574. }
  2575. }
  2576. } else {
  2577. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2578. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2579. fal1_target_idle_time_ns);
  2580. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2581. }
  2582. SDE_DEBUG_PLANE(psde,
  2583. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2584. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2585. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2586. cfg.fill_level_scale);
  2587. SDE_DEBUG_PLANE(psde,
  2588. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2589. line_time, fal1_target_idle_time_ns,
  2590. fal10_target_idle_time_ns,
  2591. psde->catalog->uidle_cfg.max_dwnscale);
  2592. SDE_EVT32_VERBOSE(cfg.enable,
  2593. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2594. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2595. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2596. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2597. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2598. psde->pipe_hw->ops.setup_uidle(
  2599. psde->pipe_hw, &cfg,
  2600. pstate->multirect_index);
  2601. }
  2602. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2603. struct sde_plane_state *pstate)
  2604. {
  2605. bool enable = false;
  2606. int mode = sde_plane_get_property(pstate,
  2607. PLANE_PROP_FB_TRANSLATION_MODE);
  2608. if ((mode == SDE_DRM_FB_SEC) ||
  2609. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2610. enable = true;
  2611. /* update secure session flag */
  2612. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2613. pstate->multirect_index,
  2614. enable);
  2615. }
  2616. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2617. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2618. {
  2619. const struct sde_format *fmt;
  2620. const struct msm_format *msm_fmt;
  2621. struct sde_plane *psde;
  2622. struct drm_plane_state *state;
  2623. struct sde_plane_state *pstate;
  2624. struct sde_rect src, dst;
  2625. const struct sde_rect *crtc_roi;
  2626. bool q16_data = true;
  2627. int idx;
  2628. psde = to_sde_plane(plane);
  2629. state = plane->state;
  2630. pstate = to_sde_plane_state(state);
  2631. msm_fmt = msm_framebuffer_format(fb);
  2632. if (!msm_fmt) {
  2633. SDE_ERROR("crtc%d plane%d: null format\n",
  2634. DRMID(crtc), DRMID(plane));
  2635. return;
  2636. }
  2637. fmt = to_sde_format(msm_fmt);
  2638. POPULATE_RECT(&src, state->src_x, state->src_y,
  2639. state->src_w, state->src_h, q16_data);
  2640. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2641. state->crtc_w, state->crtc_h, !q16_data);
  2642. SDE_DEBUG_PLANE(psde,
  2643. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2644. fb->base.id, src.x, src.y, src.w, src.h,
  2645. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2646. (char *)&fmt->base.pixel_format,
  2647. SDE_FORMAT_IS_UBWC(fmt));
  2648. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2649. BIT(SDE_DRM_DEINTERLACE)) {
  2650. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2651. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2652. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2653. src.h /= 2;
  2654. src.y = DIV_ROUND_UP(src.y, 2);
  2655. src.y &= ~0x1;
  2656. }
  2657. /*
  2658. * adjust layer mixer position of the sspp in the presence
  2659. * of a partial update to the active lm origin
  2660. */
  2661. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2662. dst.x -= crtc_roi->x;
  2663. dst.y -= crtc_roi->y;
  2664. /* check for UIDLE */
  2665. if (psde->pipe_hw->ops.setup_uidle)
  2666. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2667. psde->pipe_cfg.src_rect = src;
  2668. psde->pipe_cfg.dst_rect = dst;
  2669. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2670. _sde_plane_setup_panel_stacking(psde, pstate);
  2671. /* check for color fill */
  2672. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2673. PLANE_PROP_COLOR_FILL);
  2674. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2675. /* skip remaining processing on color fill */
  2676. pstate->dirty = 0x0;
  2677. } else if (psde->pipe_hw->ops.setup_rects) {
  2678. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2679. &psde->pipe_cfg,
  2680. pstate->multirect_index);
  2681. }
  2682. if (psde->pipe_hw->ops.setup_pe &&
  2683. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2684. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2685. &psde->pixel_ext);
  2686. /**
  2687. * when programmed in multirect mode, scalar block will be
  2688. * bypassed. Still we need to update alpha and bitwidth
  2689. * ONLY for RECT0
  2690. */
  2691. if (psde->pipe_hw->ops.setup_scaler &&
  2692. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2693. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2694. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2695. &psde->pipe_cfg, &psde->pixel_ext,
  2696. &psde->scaler3_cfg);
  2697. }
  2698. /* update excl rect */
  2699. if (psde->pipe_hw->ops.setup_excl_rect)
  2700. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2701. &pstate->excl_rect,
  2702. pstate->multirect_index);
  2703. /* enable multirect config of corresponding rect */
  2704. if (psde->pipe_hw->ops.update_multirect)
  2705. psde->pipe_hw->ops.update_multirect(
  2706. psde->pipe_hw,
  2707. true,
  2708. pstate->multirect_index,
  2709. pstate->multirect_mode);
  2710. /* update line insertion */
  2711. if (pstate->lineinsertion_feature && psde->pipe_hw->ops.setup_line_insertion)
  2712. psde->pipe_hw->ops.setup_line_insertion(psde->pipe_hw,
  2713. pstate->multirect_index,
  2714. &pstate->line_insertion_cfg);
  2715. }
  2716. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2717. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2718. {
  2719. uint32_t src_flags = 0;
  2720. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2721. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2722. src_flags |= SDE_SSPP_FLIP_LR;
  2723. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2724. src_flags |= SDE_SSPP_FLIP_UD;
  2725. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2726. src_flags |= SDE_SSPP_ROT_90;
  2727. /* update format */
  2728. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2729. pstate->const_alpha_en, src_flags,
  2730. pstate->multirect_index);
  2731. if (psde->pipe_hw->ops.setup_cdp) {
  2732. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2733. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2734. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2735. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2736. cdp_cfg->ubwc_meta_enable =
  2737. SDE_FORMAT_IS_UBWC(fmt);
  2738. cdp_cfg->tile_amortize_enable =
  2739. SDE_FORMAT_IS_UBWC(fmt) ||
  2740. SDE_FORMAT_IS_TILE(fmt);
  2741. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2742. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2743. pstate->multirect_index);
  2744. }
  2745. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2746. /* update csc */
  2747. if (SDE_FORMAT_IS_YUV(fmt))
  2748. _sde_plane_setup_csc(psde);
  2749. else
  2750. psde->csc_ptr = 0;
  2751. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2752. uint32_t pma_mode = 0;
  2753. if (fmt->alpha_enable)
  2754. pma_mode = (uint32_t) sde_plane_get_property(
  2755. pstate, PLANE_PROP_INVERSE_PMA);
  2756. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2757. pstate->multirect_index, pma_mode);
  2758. }
  2759. if (psde->pipe_hw->ops.setup_dgm_csc)
  2760. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2761. pstate->multirect_index, psde->csc_usr_ptr);
  2762. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2763. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2764. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2765. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2766. else
  2767. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2768. pstate->multirect_index, NULL);
  2769. }
  2770. }
  2771. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2772. {
  2773. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2774. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2775. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2776. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2777. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2778. &psde->sharp_cfg);
  2779. }
  2780. static void _sde_plane_update_properties(struct drm_plane *plane,
  2781. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2782. {
  2783. uint32_t nplanes;
  2784. const struct msm_format *msm_fmt;
  2785. const struct sde_format *fmt;
  2786. struct sde_plane *psde;
  2787. struct drm_plane_state *state;
  2788. struct sde_plane_state *pstate;
  2789. psde = to_sde_plane(plane);
  2790. state = plane->state;
  2791. pstate = to_sde_plane_state(state);
  2792. if (!pstate) {
  2793. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2794. return;
  2795. }
  2796. msm_fmt = msm_framebuffer_format(fb);
  2797. if (!msm_fmt) {
  2798. SDE_ERROR("crtc%d plane%d: null format\n",
  2799. DRMID(crtc), DRMID(plane));
  2800. return;
  2801. }
  2802. fmt = to_sde_format(msm_fmt);
  2803. nplanes = fmt->num_planes;
  2804. /* update secure session flag */
  2805. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2806. _sde_plane_update_secure_session(psde, pstate);
  2807. /* update roi config */
  2808. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2809. _sde_plane_update_roi_config(plane, crtc, fb);
  2810. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2811. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2812. psde->pipe_hw->ops.setup_format)
  2813. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2814. sde_color_process_plane_setup(plane);
  2815. /* update sharpening */
  2816. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2817. psde->pipe_hw->ops.setup_sharpening)
  2818. _sde_plane_update_sharpening(psde);
  2819. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2820. SDE_PLANE_DIRTY_FORMAT))
  2821. _sde_plane_set_qos_lut(plane, crtc, fb);
  2822. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2823. _sde_plane_set_ot_limit(plane, crtc);
  2824. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2825. _sde_plane_set_ts_prefill(plane, pstate);
  2826. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2827. _sde_plane_set_qos_remap(plane);
  2828. /* clear dirty */
  2829. pstate->dirty = 0x0;
  2830. }
  2831. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2832. struct sde_plane_state *pstate)
  2833. {
  2834. /**
  2835. * Valid configuration if scaler is not enabled or
  2836. * lut flag is set
  2837. */
  2838. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2839. return;
  2840. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2841. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2842. }
  2843. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2844. struct drm_plane_state *old_state)
  2845. {
  2846. struct sde_plane *psde;
  2847. struct drm_plane_state *state;
  2848. struct sde_plane_state *pstate;
  2849. struct sde_plane_state *old_pstate;
  2850. struct drm_crtc *crtc;
  2851. struct drm_framebuffer *fb;
  2852. int idx;
  2853. int dirty_prop_flag;
  2854. bool is_rt;
  2855. if (!plane) {
  2856. SDE_ERROR("invalid plane\n");
  2857. return -EINVAL;
  2858. } else if (!plane->state) {
  2859. SDE_ERROR("invalid plane state\n");
  2860. return -EINVAL;
  2861. } else if (!old_state) {
  2862. SDE_ERROR("invalid old state\n");
  2863. return -EINVAL;
  2864. }
  2865. psde = to_sde_plane(plane);
  2866. state = plane->state;
  2867. pstate = to_sde_plane_state(state);
  2868. old_pstate = to_sde_plane_state(old_state);
  2869. crtc = state->crtc;
  2870. fb = state->fb;
  2871. if (!crtc || !fb) {
  2872. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2873. !crtc, !fb);
  2874. return -EINVAL;
  2875. }
  2876. SDE_DEBUG(
  2877. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2878. plane->base.id,
  2879. state->fb->width, state->fb->height,
  2880. (char *) &state->fb->format->format,
  2881. state->fb->modifier,
  2882. state->src_w >> 16, state->src_h >> 16,
  2883. state->src_x >> 16, state->src_y >> 16,
  2884. pstate->rotation,
  2885. state->crtc_w, state->crtc_h,
  2886. state->crtc_x, state->crtc_y);
  2887. /* Caching the valid lut flag in sde plane */
  2888. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  2889. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  2890. /* force reprogramming of all the parameters, if the flag is set */
  2891. if (psde->revalidate) {
  2892. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2893. plane->base.id);
  2894. _sde_plane_check_lut_dirty(psde, pstate);
  2895. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2896. psde->revalidate = false;
  2897. }
  2898. /* determine what needs to be refreshed */
  2899. mutex_lock(&psde->property_info.property_lock);
  2900. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2901. &pstate->property_state)) >= 0) {
  2902. dirty_prop_flag = plane_prop_array[idx];
  2903. pstate->dirty |= dirty_prop_flag;
  2904. }
  2905. mutex_unlock(&psde->property_info.property_lock);
  2906. /**
  2907. * since plane_atomic_check is invoked before crtc_atomic_check
  2908. * in the commit sequence, all the parameters for updating the
  2909. * plane dirty flag will not be available during
  2910. * plane_atomic_check as some features params are updated
  2911. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2912. * before sspp update.
  2913. */
  2914. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2915. old_state);
  2916. /* re-program the output rects always if partial update roi changed */
  2917. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2918. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2919. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2920. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2921. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2922. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2923. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2924. psde->is_rt_pipe = is_rt;
  2925. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  2926. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2927. }
  2928. /* early out if nothing dirty */
  2929. if (!pstate->dirty)
  2930. return 0;
  2931. pstate->pending = true;
  2932. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2933. _sde_plane_update_properties(plane, crtc, fb);
  2934. return 0;
  2935. }
  2936. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2937. struct drm_plane_state *old_state)
  2938. {
  2939. struct sde_plane *psde;
  2940. struct drm_plane_state *state;
  2941. struct sde_plane_state *pstate;
  2942. u32 multirect_index = SDE_SSPP_RECT_0;
  2943. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2944. u32 blend_type;
  2945. if (!plane) {
  2946. SDE_ERROR("invalid plane\n");
  2947. return;
  2948. } else if (!plane->state) {
  2949. SDE_ERROR("invalid plane state\n");
  2950. return;
  2951. } else if (!old_state) {
  2952. SDE_ERROR("invalid old state\n");
  2953. return;
  2954. }
  2955. psde = to_sde_plane(plane);
  2956. state = plane->state;
  2957. pstate = to_sde_plane_state(state);
  2958. blend_type = sde_plane_get_property(pstate,
  2959. PLANE_PROP_BLEND_OP);
  2960. /* some of the color features are dependent on plane with skip blend.
  2961. * if skip blend plane is being disabled, we need to disable color properties.
  2962. */
  2963. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2964. skip_blend_plane.valid_plane = false;
  2965. skip_blend_plane.plane = SSPP_NONE;
  2966. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2967. sde_crtc_disable_cp_features(old_state->crtc);
  2968. }
  2969. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2970. pstate->multirect_mode);
  2971. pstate->pending = true;
  2972. pstate->static_cache_state = CACHE_STATE_DISABLED;
  2973. if (is_sde_plane_virtual(plane))
  2974. multirect_index = SDE_SSPP_RECT_1;
  2975. /* disable multirect config of corresponding rect */
  2976. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2977. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2978. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2979. }
  2980. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2981. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2982. struct drm_plane_state *old_state)
  2983. #else
  2984. static void sde_plane_atomic_update(struct drm_plane *plane,
  2985. struct drm_plane_state *old_state)
  2986. #endif
  2987. {
  2988. struct sde_plane *psde;
  2989. struct drm_plane_state *state;
  2990. if (!plane) {
  2991. SDE_ERROR("invalid plane\n");
  2992. return;
  2993. } else if (!plane->state) {
  2994. SDE_ERROR("invalid plane state\n");
  2995. return;
  2996. }
  2997. psde = to_sde_plane(plane);
  2998. psde->is_error = false;
  2999. state = plane->state;
  3000. SDE_DEBUG_PLANE(psde, "\n");
  3001. if (!sde_plane_enabled(state)) {
  3002. _sde_plane_atomic_disable(plane, old_state);
  3003. } else {
  3004. int ret;
  3005. ret = sde_plane_sspp_atomic_update(plane, old_state);
  3006. /* atomic_check should have ensured that this doesn't fail */
  3007. WARN_ON(ret < 0);
  3008. }
  3009. }
  3010. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3011. static void sde_plane_atomic_update(struct drm_plane *plane,
  3012. struct drm_atomic_state *atomic_state)
  3013. {
  3014. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  3015. _sde_plane_atomic_update(plane, old_state);
  3016. }
  3017. #endif
  3018. void sde_plane_restore(struct drm_plane *plane)
  3019. {
  3020. struct sde_plane *psde;
  3021. if (!plane || !plane->state) {
  3022. SDE_ERROR("invalid plane\n");
  3023. return;
  3024. }
  3025. psde = to_sde_plane(plane);
  3026. /*
  3027. * Revalidate is only true here if idle PC occurred and
  3028. * there is no plane state update in current commit cycle.
  3029. */
  3030. if (!psde->revalidate)
  3031. return;
  3032. SDE_DEBUG_PLANE(psde, "\n");
  3033. /* last plane state is same as current state */
  3034. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3035. _sde_plane_atomic_update(plane, plane->state);
  3036. #else
  3037. sde_plane_atomic_update(plane, plane->state);
  3038. #endif
  3039. }
  3040. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3041. enum sde_sys_cache_type type)
  3042. {
  3043. struct sde_plane_state *pstate;
  3044. u32 cache_flag, cache_rd_type, cache_wr_type;
  3045. if (!plane || !plane->state) {
  3046. SDE_ERROR("invalid plane\n");
  3047. return false;
  3048. }
  3049. pstate = to_sde_plane_state(plane->state);
  3050. msm_framebuffer_get_cache_hint(plane->state->fb, &cache_flag, &cache_rd_type,
  3051. &cache_wr_type);
  3052. /* check if llcc is required for the plane */
  3053. if (pstate->sc_cfg.rd_en && ((pstate->sc_cfg.type == type)
  3054. || (cache_flag && (cache_rd_type == type))
  3055. || (cache_flag && (cache_wr_type == type)))) {
  3056. SDE_EVT32_VERBOSE(DRMID(plane), type, pstate->sc_cfg.rd_en, pstate->sc_cfg.type,
  3057. cache_flag, cache_rd_type, cache_wr_type,
  3058. plane->state->fb->base.id);
  3059. return true;
  3060. }
  3061. return false;
  3062. }
  3063. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3064. {
  3065. char feature_name[256];
  3066. if (psde->pipe_sblk->maxhdeciexp) {
  3067. msm_property_install_range(&psde->property_info,
  3068. "h_decimate", 0x0, 0,
  3069. psde->pipe_sblk->maxhdeciexp, 0,
  3070. PLANE_PROP_H_DECIMATE);
  3071. }
  3072. if (psde->pipe_sblk->maxvdeciexp) {
  3073. msm_property_install_range(&psde->property_info,
  3074. "v_decimate", 0x0, 0,
  3075. psde->pipe_sblk->maxvdeciexp, 0,
  3076. PLANE_PROP_V_DECIMATE);
  3077. }
  3078. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3079. msm_property_install_range(
  3080. &psde->property_info, "scaler_v2",
  3081. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3082. msm_property_install_blob(&psde->property_info,
  3083. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3084. msm_property_install_blob(&psde->property_info,
  3085. "lut_cir", 0,
  3086. PLANE_PROP_SCALER_LUT_CIR);
  3087. msm_property_install_blob(&psde->property_info,
  3088. "lut_sep", 0,
  3089. PLANE_PROP_SCALER_LUT_SEP);
  3090. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3091. msm_property_install_range(
  3092. &psde->property_info, "scaler_v2",
  3093. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3094. msm_property_install_blob(&psde->property_info,
  3095. "lut_sep", 0,
  3096. PLANE_PROP_SCALER_LUT_SEP);
  3097. } else if (psde->features & SDE_SSPP_SCALER) {
  3098. msm_property_install_range(
  3099. &psde->property_info, "scaler_v1", 0x0,
  3100. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3101. }
  3102. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3103. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3104. msm_property_install_volatile_range(
  3105. &psde->property_info, "csc_v1", 0x0,
  3106. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3107. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3108. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3109. "SDE_SSPP_HUE_V",
  3110. psde->pipe_sblk->hsic_blk.version >> 16);
  3111. msm_property_install_range(&psde->property_info,
  3112. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3113. PLANE_PROP_HUE_ADJUST);
  3114. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3115. "SDE_SSPP_SATURATION_V",
  3116. psde->pipe_sblk->hsic_blk.version >> 16);
  3117. msm_property_install_range(&psde->property_info,
  3118. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3119. PLANE_PROP_SATURATION_ADJUST);
  3120. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3121. "SDE_SSPP_VALUE_V",
  3122. psde->pipe_sblk->hsic_blk.version >> 16);
  3123. msm_property_install_range(&psde->property_info,
  3124. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3125. PLANE_PROP_VALUE_ADJUST);
  3126. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3127. "SDE_SSPP_CONTRAST_V",
  3128. psde->pipe_sblk->hsic_blk.version >> 16);
  3129. msm_property_install_range(&psde->property_info,
  3130. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3131. PLANE_PROP_CONTRAST_ADJUST);
  3132. }
  3133. }
  3134. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3135. struct sde_kms_info *info)
  3136. {
  3137. char feature_name[256];
  3138. bool is_master = !psde->is_virtual;
  3139. if ((is_master &&
  3140. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3141. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3142. msm_property_install_range(&psde->property_info,
  3143. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3144. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3145. }
  3146. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3147. msm_property_install_volatile_range(
  3148. &psde->property_info, "csc_dma_v1", 0x0,
  3149. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3150. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3151. }
  3152. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3153. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3154. "SDE_SSPP_SKIN_COLOR_V",
  3155. psde->pipe_sblk->memcolor_blk.version >> 16);
  3156. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3157. PLANE_PROP_SKIN_COLOR);
  3158. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3159. "SDE_SSPP_SKY_COLOR_V",
  3160. psde->pipe_sblk->memcolor_blk.version >> 16);
  3161. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3162. PLANE_PROP_SKY_COLOR);
  3163. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3164. "SDE_SSPP_FOLIAGE_COLOR_V",
  3165. psde->pipe_sblk->memcolor_blk.version >> 16);
  3166. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3167. PLANE_PROP_FOLIAGE_COLOR);
  3168. }
  3169. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3170. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3171. "SDE_VIG_3D_LUT_GAMUT_V",
  3172. psde->pipe_sblk->gamut_blk.version >> 16);
  3173. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3174. PLANE_PROP_VIG_GAMUT);
  3175. }
  3176. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3177. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3178. "SDE_VIG_1D_LUT_IGC_V",
  3179. psde->pipe_sblk->igc_blk[0].version >> 16);
  3180. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3181. PLANE_PROP_VIG_IGC);
  3182. }
  3183. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3184. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3185. "SDE_DGM_1D_LUT_IGC_V",
  3186. psde->pipe_sblk->igc_blk[0].version >> 16);
  3187. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3188. PLANE_PROP_DMA_IGC);
  3189. }
  3190. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3191. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3192. "SDE_DGM_1D_LUT_GC_V",
  3193. psde->pipe_sblk->gc_blk[0].version >> 16);
  3194. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3195. PLANE_PROP_DMA_GC);
  3196. }
  3197. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3198. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3199. "SDE_SSPP_FP16_IGC_V",
  3200. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3201. msm_property_install_range(&psde->property_info, feature_name,
  3202. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3203. }
  3204. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3205. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3206. "SDE_SSPP_FP16_GC_V",
  3207. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3208. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3209. PLANE_PROP_FP16_GC);
  3210. }
  3211. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3212. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3213. "SDE_SSPP_FP16_CSC_V",
  3214. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3215. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3216. PLANE_PROP_FP16_CSC);
  3217. }
  3218. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3219. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3220. "SDE_SSPP_FP16_UNMULT_V",
  3221. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3222. msm_property_install_range(&psde->property_info, feature_name,
  3223. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3224. }
  3225. }
  3226. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3227. u32 master_plane_id, struct sde_kms_info *info,
  3228. struct sde_mdss_cfg *catalog)
  3229. {
  3230. bool is_master = !psde->is_virtual;
  3231. const struct sde_format_extended *format_list;
  3232. u32 index;
  3233. int pipe_id;
  3234. if (is_master) {
  3235. format_list = psde->pipe_sblk->format_list;
  3236. } else {
  3237. format_list = psde->pipe_sblk->virt_format_list;
  3238. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3239. master_plane_id);
  3240. }
  3241. if (format_list) {
  3242. sde_kms_info_start(info, "pixel_formats");
  3243. while (format_list->fourcc_format) {
  3244. sde_kms_info_append_format(info,
  3245. format_list->fourcc_format,
  3246. format_list->modifier);
  3247. ++format_list;
  3248. }
  3249. sde_kms_info_stop(info);
  3250. }
  3251. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3252. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3253. sde_kms_info_add_keyint(info, "max_linewidth",
  3254. psde->pipe_sblk->maxlinewidth);
  3255. sde_kms_info_add_keyint(info, "max_upscale",
  3256. psde->pipe_sblk->maxupscale);
  3257. sde_kms_info_add_keyint(info, "max_downscale",
  3258. psde->pipe_sblk->maxdwnscale);
  3259. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3260. psde->pipe_sblk->maxhdeciexp);
  3261. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3262. psde->pipe_sblk->maxvdeciexp);
  3263. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3264. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3265. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3266. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3267. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3268. pipe_id = psde->pipe - SSPP_VIG0;
  3269. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3270. pipe_id = psde->pipe - SSPP_DMA0;
  3271. else
  3272. pipe_id = -1;
  3273. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3274. index = (master_plane_id == 0) ? 0 : 1;
  3275. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3276. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3277. sde_kms_info_add_keyint(info, "demura_block", index);
  3278. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3279. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3280. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3281. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3282. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3283. const struct sde_format_extended *inline_rot_fmt_list;
  3284. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3285. catalog->true_inline_rot_rev);
  3286. sde_kms_info_add_keyint(info,
  3287. "true_inline_dwnscale_rt",
  3288. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3289. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3290. sde_kms_info_add_keyint(info,
  3291. "true_inline_dwnscale_rt_numerator",
  3292. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3293. sde_kms_info_add_keyint(info,
  3294. "true_inline_dwnscale_rt_denominator",
  3295. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3296. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3297. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3298. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3299. psde->pipe_sblk->in_rot_maxheight);
  3300. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3301. if (inline_rot_fmt_list) {
  3302. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3303. while (inline_rot_fmt_list->fourcc_format) {
  3304. sde_kms_info_append_format(info,
  3305. inline_rot_fmt_list->fourcc_format,
  3306. inline_rot_fmt_list->modifier);
  3307. ++inline_rot_fmt_list;
  3308. }
  3309. sde_kms_info_stop(info);
  3310. }
  3311. }
  3312. }
  3313. /* helper to install properties which are common to planes and crtcs */
  3314. static void _sde_plane_install_properties(struct drm_plane *plane,
  3315. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3316. {
  3317. static const struct drm_prop_enum_list e_blend_op[] = {
  3318. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3319. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3320. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3321. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3322. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3323. };
  3324. static const struct drm_prop_enum_list e_src_config[] = {
  3325. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3326. };
  3327. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3328. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3329. {SDE_DRM_FB_SEC, "sec"},
  3330. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3331. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3332. };
  3333. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3334. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3335. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3336. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3337. };
  3338. struct sde_kms_info *info;
  3339. struct sde_plane *psde = to_sde_plane(plane);
  3340. bool is_master;
  3341. int zpos_max = 255;
  3342. int zpos_def = 0;
  3343. if (!plane || !psde) {
  3344. SDE_ERROR("invalid plane\n");
  3345. return;
  3346. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3347. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3348. !psde->pipe_hw, !psde->pipe_sblk);
  3349. return;
  3350. } else if (!catalog) {
  3351. SDE_ERROR("invalid catalog\n");
  3352. return;
  3353. }
  3354. psde->catalog = catalog;
  3355. is_master = !psde->is_virtual;
  3356. info = vzalloc(sizeof(struct sde_kms_info));
  3357. if (!info) {
  3358. SDE_ERROR("failed to allocate info memory\n");
  3359. return;
  3360. }
  3361. if (sde_is_custom_client()) {
  3362. if (catalog->mixer_count &&
  3363. catalog->mixer[0].sblk->maxblendstages) {
  3364. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3365. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3366. (zpos_max > SDE_STAGE_MAX - 1))
  3367. zpos_max = SDE_STAGE_MAX - 1;
  3368. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3369. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3370. }
  3371. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3372. /* reserve zpos == 0 for primary planes */
  3373. zpos_def = drm_plane_index(plane) + 1;
  3374. }
  3375. msm_property_install_range(&psde->property_info, "zpos",
  3376. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3377. msm_property_install_range(&psde->property_info, "alpha",
  3378. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3379. /* linux default file descriptor range on each process */
  3380. msm_property_install_range(&psde->property_info, "input_fence",
  3381. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3382. if (is_master)
  3383. _sde_plane_install_master_only_properties(psde);
  3384. else
  3385. msm_property_install_enum(&psde->property_info,
  3386. "multirect_mode", 0x0, 0, e_multirect_mode,
  3387. ARRAY_SIZE(e_multirect_mode), 0,
  3388. PLANE_PROP_MULTIRECT_MODE);
  3389. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3390. msm_property_install_volatile_range(&psde->property_info,
  3391. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3392. sde_plane_rot_install_properties(plane, catalog);
  3393. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3394. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3395. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3396. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3397. PLANE_PROP_SRC_CONFIG);
  3398. if (psde->pipe_hw->ops.setup_solidfill)
  3399. msm_property_install_range(&psde->property_info, "color_fill",
  3400. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3401. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3402. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3403. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3404. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3405. msm_property_install_blob(&psde->property_info, "capabilities",
  3406. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3407. sde_kms_info_reset(info);
  3408. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3409. catalog);
  3410. _sde_plane_install_colorproc_properties(psde, info);
  3411. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3412. info->data, SDE_KMS_INFO_DATALEN(info),
  3413. PLANE_PROP_INFO);
  3414. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3415. 0x0, 0, e_fb_translation_mode,
  3416. ARRAY_SIZE(e_fb_translation_mode), 0,
  3417. PLANE_PROP_FB_TRANSLATION_MODE);
  3418. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3419. msm_property_install_range(&psde->property_info, "ubwc_stats_roi",
  3420. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_UBWC_STATS_ROI);
  3421. vfree(info);
  3422. }
  3423. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3424. void __user *usr_ptr)
  3425. {
  3426. struct sde_drm_csc_v1 csc_v1;
  3427. int i;
  3428. if (!psde) {
  3429. SDE_ERROR("invalid plane\n");
  3430. return;
  3431. }
  3432. psde->csc_usr_ptr = NULL;
  3433. if (!usr_ptr) {
  3434. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3435. return;
  3436. }
  3437. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3438. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3439. return;
  3440. }
  3441. /* populate from user space */
  3442. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3443. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3444. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3445. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3446. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3447. }
  3448. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3449. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3450. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3451. }
  3452. psde->csc_usr_ptr = &psde->csc_cfg;
  3453. }
  3454. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3455. struct sde_plane_state *pstate, void __user *usr)
  3456. {
  3457. struct sde_drm_scaler_v1 scale_v1;
  3458. struct sde_hw_pixel_ext *pe;
  3459. int i;
  3460. if (!psde || !pstate) {
  3461. SDE_ERROR("invalid argument(s)\n");
  3462. return;
  3463. }
  3464. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3465. if (!usr) {
  3466. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3467. return;
  3468. }
  3469. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3470. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3471. return;
  3472. }
  3473. /* force property to be dirty, even if the pointer didn't change */
  3474. msm_property_set_dirty(&psde->property_info,
  3475. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3476. /* populate from user space */
  3477. pe = &pstate->pixel_ext;
  3478. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3479. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3480. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3481. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3482. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3483. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3484. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3485. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3486. }
  3487. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3488. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3489. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3490. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3491. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3492. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3493. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3494. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3495. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3496. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3497. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3498. }
  3499. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3500. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3501. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3502. }
  3503. static void _sde_plane_clear_predownscale_settings(
  3504. struct sde_plane_state *pstate)
  3505. {
  3506. pstate->pre_down.pre_downscale_x_0 = 0;
  3507. pstate->pre_down.pre_downscale_x_1 = 0;
  3508. pstate->pre_down.pre_downscale_y_0 = 0;
  3509. pstate->pre_down.pre_downscale_y_1 = 0;
  3510. }
  3511. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3512. struct sde_plane_state *pstate, void __user *usr)
  3513. {
  3514. struct sde_drm_scaler_v2 scale_v2;
  3515. struct sde_hw_pixel_ext *pe;
  3516. int i;
  3517. struct sde_hw_scaler3_cfg *cfg;
  3518. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3519. if (!psde || !pstate) {
  3520. SDE_ERROR("invalid argument(s)\n");
  3521. return;
  3522. }
  3523. cfg = &pstate->scaler3_cfg;
  3524. pd_cfg = &pstate->pre_down;
  3525. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3526. if (!usr) {
  3527. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3528. cfg->enable = 0;
  3529. _sde_plane_clear_predownscale_settings(pstate);
  3530. goto end;
  3531. }
  3532. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3533. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3534. return;
  3535. }
  3536. /* detach/ignore user data if 'disabled' */
  3537. if (!scale_v2.enable) {
  3538. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3539. cfg->enable = 0;
  3540. _sde_plane_clear_predownscale_settings(pstate);
  3541. goto end;
  3542. }
  3543. /* populate from user space */
  3544. sde_set_scaler_v2(cfg, &scale_v2);
  3545. if (_sde_plane_has_pre_downscale(psde)) {
  3546. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3547. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3548. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3549. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3550. }
  3551. pe = &pstate->pixel_ext;
  3552. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3553. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3554. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3555. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3556. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3557. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3558. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3559. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3560. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3561. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3562. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3563. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3564. }
  3565. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3566. end:
  3567. /* force property to be dirty, even if the pointer didn't change */
  3568. msm_property_set_dirty(&psde->property_info,
  3569. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3570. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3571. cfg->src_width[0], cfg->src_height[0],
  3572. cfg->dst_width, cfg->dst_height);
  3573. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3574. }
  3575. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3576. struct sde_plane_state *pstate, void __user *usr_ptr)
  3577. {
  3578. struct drm_clip_rect excl_rect_v1;
  3579. if (!psde || !pstate) {
  3580. SDE_ERROR("invalid argument(s)\n");
  3581. return;
  3582. }
  3583. if (!usr_ptr) {
  3584. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3585. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3586. return;
  3587. }
  3588. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3589. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3590. return;
  3591. }
  3592. /* populate from user space */
  3593. pstate->excl_rect.x = excl_rect_v1.x1;
  3594. pstate->excl_rect.y = excl_rect_v1.y1;
  3595. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3596. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3597. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3598. pstate->excl_rect.x, pstate->excl_rect.y,
  3599. pstate->excl_rect.w, pstate->excl_rect.h);
  3600. }
  3601. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3602. struct sde_plane_state *pstate, void __user *usr_ptr)
  3603. {
  3604. struct sde_drm_ubwc_stats_roi roi = {0};
  3605. if (!psde || !pstate) {
  3606. SDE_ERROR("invalid argument(s)\n");
  3607. return;
  3608. }
  3609. if (!usr_ptr) {
  3610. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3611. goto end;
  3612. }
  3613. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3614. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3615. return;
  3616. }
  3617. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3618. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3619. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3620. memset(&roi, 0, sizeof(roi));
  3621. }
  3622. end:
  3623. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3624. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3625. }
  3626. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3627. struct drm_plane_state *state, struct drm_property *property,
  3628. uint64_t val)
  3629. {
  3630. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3631. struct sde_plane_state *pstate;
  3632. int idx, ret = -EINVAL;
  3633. SDE_DEBUG_PLANE(psde, "\n");
  3634. if (!plane) {
  3635. SDE_ERROR("invalid plane\n");
  3636. } else if (!state) {
  3637. SDE_ERROR_PLANE(psde, "invalid state\n");
  3638. } else {
  3639. pstate = to_sde_plane_state(state);
  3640. ret = msm_property_atomic_set(&psde->property_info,
  3641. &pstate->property_state, property, val);
  3642. if (!ret) {
  3643. idx = msm_property_index(&psde->property_info,
  3644. property);
  3645. switch (idx) {
  3646. case PLANE_PROP_INPUT_FENCE:
  3647. _sde_plane_set_input_fence(psde, pstate, val);
  3648. break;
  3649. case PLANE_PROP_CSC_V1:
  3650. case PLANE_PROP_CSC_DMA_V1:
  3651. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3652. break;
  3653. case PLANE_PROP_SCALER_V1:
  3654. _sde_plane_set_scaler_v1(psde, pstate,
  3655. (void *)(uintptr_t)val);
  3656. break;
  3657. case PLANE_PROP_SCALER_V2:
  3658. _sde_plane_set_scaler_v2(psde, pstate,
  3659. (void *)(uintptr_t)val);
  3660. break;
  3661. case PLANE_PROP_EXCL_RECT_V1:
  3662. _sde_plane_set_excl_rect_v1(psde, pstate,
  3663. (void *)(uintptr_t)val);
  3664. break;
  3665. case PLANE_PROP_UBWC_STATS_ROI:
  3666. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3667. (void __user *)(uintptr_t)val);
  3668. break;
  3669. default:
  3670. /* nothing to do */
  3671. break;
  3672. }
  3673. }
  3674. }
  3675. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3676. property->name, property->base.id, val, ret);
  3677. return ret;
  3678. }
  3679. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3680. const struct drm_plane_state *state,
  3681. struct drm_property *property, uint64_t *val)
  3682. {
  3683. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3684. struct sde_plane_state *pstate;
  3685. int ret = -EINVAL;
  3686. if (!plane) {
  3687. SDE_ERROR("invalid plane\n");
  3688. } else if (!state) {
  3689. SDE_ERROR("invalid state\n");
  3690. } else {
  3691. SDE_DEBUG_PLANE(psde, "\n");
  3692. pstate = to_sde_plane_state(state);
  3693. ret = msm_property_atomic_get(&psde->property_info,
  3694. &pstate->property_state, property, val);
  3695. }
  3696. return ret;
  3697. }
  3698. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3699. struct drm_plane_state *plane_state)
  3700. {
  3701. struct sde_plane *psde;
  3702. struct sde_plane_state *pstate;
  3703. struct drm_property *drm_prop;
  3704. enum msm_mdp_plane_property prop_idx;
  3705. if (!plane || !plane_state) {
  3706. SDE_ERROR("invalid params\n");
  3707. return -EINVAL;
  3708. }
  3709. psde = to_sde_plane(plane);
  3710. pstate = to_sde_plane_state(plane_state);
  3711. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3712. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3713. uint64_t val = pstate->property_values[prop_idx].value;
  3714. uint64_t def;
  3715. int ret;
  3716. drm_prop = msm_property_index_to_drm_property(
  3717. &psde->property_info, prop_idx);
  3718. if (!drm_prop) {
  3719. /* not all props will be installed, based on caps */
  3720. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3721. prop_idx);
  3722. continue;
  3723. }
  3724. def = msm_property_get_default(&psde->property_info, prop_idx);
  3725. if (val == def)
  3726. continue;
  3727. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3728. drm_prop->name, prop_idx, val, def);
  3729. ret = sde_plane_atomic_set_property(plane, plane_state,
  3730. drm_prop, def);
  3731. if (ret) {
  3732. SDE_ERROR_PLANE(psde,
  3733. "set property failed, idx %d ret %d\n",
  3734. prop_idx, ret);
  3735. continue;
  3736. }
  3737. }
  3738. return 0;
  3739. }
  3740. static void sde_plane_destroy(struct drm_plane *plane)
  3741. {
  3742. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3743. SDE_DEBUG_PLANE(psde, "\n");
  3744. if (psde) {
  3745. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3746. if (psde->blob_info)
  3747. drm_property_blob_put(psde->blob_info);
  3748. msm_property_destroy(&psde->property_info);
  3749. mutex_destroy(&psde->lock);
  3750. /* this will destroy the states as well */
  3751. drm_plane_cleanup(plane);
  3752. if (psde->pipe_hw)
  3753. sde_hw_sspp_destroy(psde->pipe_hw);
  3754. kfree(psde);
  3755. }
  3756. }
  3757. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3758. {
  3759. struct sde_plane_state *pstate;
  3760. if (!state) {
  3761. SDE_ERROR("invalid arg state %d\n", !state);
  3762. return;
  3763. }
  3764. pstate = to_sde_plane_state(state);
  3765. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3766. SDE_DRM_FB_SEC) {
  3767. /* remove ref count for frame buffers */
  3768. if (state->fb) {
  3769. drm_framebuffer_put(state->fb);
  3770. state->fb = NULL;
  3771. }
  3772. }
  3773. }
  3774. static void sde_plane_destroy_state(struct drm_plane *plane,
  3775. struct drm_plane_state *state)
  3776. {
  3777. struct sde_plane *psde;
  3778. struct sde_plane_state *pstate;
  3779. if (!plane || !state) {
  3780. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3781. !plane, !state);
  3782. return;
  3783. }
  3784. psde = to_sde_plane(plane);
  3785. pstate = to_sde_plane_state(state);
  3786. SDE_DEBUG_PLANE(psde, "\n");
  3787. /* remove ref count for frame buffers */
  3788. if (state->fb)
  3789. drm_framebuffer_put(state->fb);
  3790. /* remove ref count for fence */
  3791. if (pstate->input_fence)
  3792. sde_sync_put(pstate->input_fence);
  3793. pstate->input_fence = 0;
  3794. /* destroy value helper */
  3795. msm_property_destroy_state(&psde->property_info, pstate,
  3796. &pstate->property_state);
  3797. }
  3798. static struct drm_plane_state *
  3799. sde_plane_duplicate_state(struct drm_plane *plane)
  3800. {
  3801. struct sde_plane *psde;
  3802. struct sde_plane_state *pstate;
  3803. struct sde_plane_state *old_state;
  3804. struct drm_property *drm_prop;
  3805. uint64_t input_fence_default;
  3806. if (!plane) {
  3807. SDE_ERROR("invalid plane\n");
  3808. return NULL;
  3809. } else if (!plane->state) {
  3810. SDE_ERROR("invalid plane state\n");
  3811. return NULL;
  3812. }
  3813. old_state = to_sde_plane_state(plane->state);
  3814. psde = to_sde_plane(plane);
  3815. if (old_state->cont_splash_populated) {
  3816. plane->state->crtc = NULL;
  3817. old_state->cont_splash_populated = false;
  3818. }
  3819. pstate = msm_property_alloc_state(&psde->property_info);
  3820. if (!pstate) {
  3821. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3822. return NULL;
  3823. }
  3824. SDE_DEBUG_PLANE(psde, "\n");
  3825. /* duplicate value helper */
  3826. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3827. &pstate->property_state, pstate->property_values);
  3828. /* clear out any input fence */
  3829. pstate->input_fence = 0;
  3830. input_fence_default = msm_property_get_default(
  3831. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3832. drm_prop = msm_property_index_to_drm_property(
  3833. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3834. if (msm_property_atomic_set(&psde->property_info,
  3835. &pstate->property_state, drm_prop,
  3836. input_fence_default))
  3837. SDE_DEBUG_PLANE(psde,
  3838. "error clearing duplicated input fence\n");
  3839. pstate->dirty = 0x0;
  3840. pstate->pending = false;
  3841. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3842. /* reset layout offset */
  3843. if (pstate->layout_offset) {
  3844. if (pstate->layout_offset > 0)
  3845. pstate->base.crtc_x += pstate->layout_offset;
  3846. pstate->layout = SDE_LAYOUT_NONE;
  3847. pstate->layout_offset = 0;
  3848. }
  3849. return &pstate->base;
  3850. }
  3851. static void sde_plane_reset(struct drm_plane *plane)
  3852. {
  3853. struct sde_plane *psde;
  3854. struct sde_plane_state *pstate;
  3855. if (!plane) {
  3856. SDE_ERROR("invalid plane\n");
  3857. return;
  3858. }
  3859. psde = to_sde_plane(plane);
  3860. SDE_DEBUG_PLANE(psde, "\n");
  3861. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3862. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3863. return;
  3864. }
  3865. /* remove previous state, if present */
  3866. if (plane->state) {
  3867. sde_plane_destroy_state(plane, plane->state);
  3868. plane->state = 0;
  3869. }
  3870. pstate = msm_property_alloc_state(&psde->property_info);
  3871. if (!pstate) {
  3872. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3873. return;
  3874. }
  3875. /* reset value helper */
  3876. msm_property_reset_state(&psde->property_info, pstate,
  3877. &pstate->property_state,
  3878. pstate->property_values);
  3879. pstate->base.plane = plane;
  3880. plane->state = &pstate->base;
  3881. }
  3882. void sde_plane_get_frame_data(struct drm_plane *plane,
  3883. struct sde_drm_plane_frame_data *data)
  3884. {
  3885. struct sde_plane *psde;
  3886. struct sde_plane_state *pstate;
  3887. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3888. if (!plane) {
  3889. SDE_ERROR("invalid plane\n");
  3890. return;
  3891. }
  3892. psde = to_sde_plane(plane);
  3893. pstate = to_sde_plane_state(plane->state);
  3894. ubwc_stats = &data->ubwc_stats;
  3895. data->plane_id = DRMID(plane);
  3896. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3897. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3898. sizeof(struct sde_drm_ubwc_stats_roi));
  3899. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3900. pstate->multirect_index, ubwc_stats);
  3901. }
  3902. if (psde->pipe_hw->ops.get_ubwc_error)
  3903. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3904. pstate->multirect_index);
  3905. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3906. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3907. if (psde->pipe_hw->ops.get_meta_error)
  3908. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3909. pstate->multirect_index);
  3910. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3911. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3912. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3913. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3914. SDE_EVTLOG_ERROR);
  3915. SDE_DEBUG_PLANE(psde, "plane%d ubwc_error %d meta_error %d\n",
  3916. ubwc_stats->error, ubwc_stats->meta_error);
  3917. }
  3918. }
  3919. #if IS_ENABLED(CONFIG_DEBUG_FS)
  3920. static ssize_t _sde_plane_danger_read(struct file *file,
  3921. char __user *buff, size_t count, loff_t *ppos)
  3922. {
  3923. struct sde_kms *kms = file->private_data;
  3924. struct sde_mdss_cfg *cfg = kms->catalog;
  3925. int len = 0;
  3926. char buf[40] = {'\0'};
  3927. if (!cfg)
  3928. return -ENODEV;
  3929. if (*ppos)
  3930. return 0; /* the end */
  3931. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3932. if (len < 0 || len >= sizeof(buf))
  3933. return 0;
  3934. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3935. return -EFAULT;
  3936. *ppos += len; /* increase offset */
  3937. return len;
  3938. }
  3939. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3940. {
  3941. struct drm_plane *plane;
  3942. drm_for_each_plane(plane, kms->dev) {
  3943. if (plane->fb && plane->state) {
  3944. sde_plane_danger_signal_ctrl(plane, enable);
  3945. SDE_DEBUG("plane:%d img:%dx%d ",
  3946. plane->base.id, plane->fb->width,
  3947. plane->fb->height);
  3948. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3949. plane->state->src_x >> 16,
  3950. plane->state->src_y >> 16,
  3951. plane->state->src_w >> 16,
  3952. plane->state->src_h >> 16,
  3953. plane->state->crtc_x, plane->state->crtc_y,
  3954. plane->state->crtc_w, plane->state->crtc_h);
  3955. } else {
  3956. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3957. }
  3958. }
  3959. }
  3960. static ssize_t _sde_plane_danger_write(struct file *file,
  3961. const char __user *user_buf, size_t count, loff_t *ppos)
  3962. {
  3963. struct sde_kms *kms = file->private_data;
  3964. struct sde_mdss_cfg *cfg = kms->catalog;
  3965. int disable_panic;
  3966. char buf[10];
  3967. if (!cfg)
  3968. return -EFAULT;
  3969. if (count >= sizeof(buf))
  3970. return -EFAULT;
  3971. if (copy_from_user(buf, user_buf, count))
  3972. return -EFAULT;
  3973. buf[count] = 0; /* end of string */
  3974. if (kstrtoint(buf, 0, &disable_panic))
  3975. return -EFAULT;
  3976. if (disable_panic) {
  3977. /* Disable panic signal for all active pipes */
  3978. SDE_DEBUG("Disabling danger:\n");
  3979. _sde_plane_set_danger_state(kms, false);
  3980. kms->has_danger_ctrl = false;
  3981. } else {
  3982. /* Enable panic signal for all active pipes */
  3983. SDE_DEBUG("Enabling danger:\n");
  3984. kms->has_danger_ctrl = true;
  3985. _sde_plane_set_danger_state(kms, true);
  3986. }
  3987. return count;
  3988. }
  3989. static const struct file_operations sde_plane_danger_enable = {
  3990. .open = simple_open,
  3991. .read = _sde_plane_danger_read,
  3992. .write = _sde_plane_danger_write,
  3993. };
  3994. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3995. {
  3996. struct sde_plane *psde;
  3997. struct sde_kms *kms;
  3998. struct msm_drm_private *priv;
  3999. const struct sde_sspp_sub_blks *sblk = 0;
  4000. const struct sde_sspp_cfg *cfg = 0;
  4001. if (!plane || !plane->dev) {
  4002. SDE_ERROR("invalid arguments\n");
  4003. return -EINVAL;
  4004. }
  4005. priv = plane->dev->dev_private;
  4006. if (!priv || !priv->kms) {
  4007. SDE_ERROR("invalid KMS reference\n");
  4008. return -EINVAL;
  4009. }
  4010. kms = to_sde_kms(priv->kms);
  4011. psde = to_sde_plane(plane);
  4012. if (psde && psde->pipe_hw)
  4013. cfg = psde->pipe_hw->cap;
  4014. if (cfg)
  4015. sblk = cfg->sblk;
  4016. if (!sblk)
  4017. return 0;
  4018. /* create overall sub-directory for the pipe */
  4019. psde->debugfs_root =
  4020. debugfs_create_dir(psde->pipe_name,
  4021. plane->dev->primary->debugfs_root);
  4022. if (!psde->debugfs_root)
  4023. return -ENOMEM;
  4024. /* don't error check these */
  4025. debugfs_create_x64("features", 0400,
  4026. psde->debugfs_root, &psde->features);
  4027. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  4028. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  4029. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  4030. debugfs_create_bool("default_scaling",
  4031. 0600,
  4032. psde->debugfs_root,
  4033. &psde->debugfs_default_scale);
  4034. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4035. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4036. 0600,
  4037. psde->debugfs_root,
  4038. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4039. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4040. 0600,
  4041. psde->debugfs_root,
  4042. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4043. debugfs_create_u32("in_rot_max_downscale_nrt",
  4044. 0600,
  4045. psde->debugfs_root,
  4046. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4047. debugfs_create_u32("in_rot_max_height",
  4048. 0600,
  4049. psde->debugfs_root,
  4050. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4051. }
  4052. debugfs_create_u32("xin_id",
  4053. 0400,
  4054. psde->debugfs_root,
  4055. (u32 *) &cfg->xin_id);
  4056. debugfs_create_x32("creq_vblank",
  4057. 0600,
  4058. psde->debugfs_root,
  4059. (u32 *) &sblk->creq_vblank);
  4060. debugfs_create_x32("danger_vblank",
  4061. 0600,
  4062. psde->debugfs_root,
  4063. (u32 *) &sblk->danger_vblank);
  4064. debugfs_create_file("disable_danger",
  4065. 0600,
  4066. psde->debugfs_root,
  4067. kms, &sde_plane_danger_enable);
  4068. return 0;
  4069. }
  4070. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4071. {
  4072. struct sde_plane *psde;
  4073. if (!plane)
  4074. return;
  4075. psde = to_sde_plane(plane);
  4076. debugfs_remove_recursive(psde->debugfs_root);
  4077. }
  4078. #else
  4079. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4080. {
  4081. return 0;
  4082. }
  4083. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4084. {
  4085. }
  4086. #endif /* CONFIG_DEBUG_FS */
  4087. static int sde_plane_late_register(struct drm_plane *plane)
  4088. {
  4089. return _sde_plane_init_debugfs(plane);
  4090. }
  4091. static void sde_plane_early_unregister(struct drm_plane *plane)
  4092. {
  4093. _sde_plane_destroy_debugfs(plane);
  4094. }
  4095. static const struct drm_plane_funcs sde_plane_funcs = {
  4096. .update_plane = drm_atomic_helper_update_plane,
  4097. .disable_plane = drm_atomic_helper_disable_plane,
  4098. .destroy = sde_plane_destroy,
  4099. .atomic_set_property = sde_plane_atomic_set_property,
  4100. .atomic_get_property = sde_plane_atomic_get_property,
  4101. .reset = sde_plane_reset,
  4102. .atomic_duplicate_state = sde_plane_duplicate_state,
  4103. .atomic_destroy_state = sde_plane_destroy_state,
  4104. .late_register = sde_plane_late_register,
  4105. .early_unregister = sde_plane_early_unregister,
  4106. };
  4107. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4108. .prepare_fb = sde_plane_prepare_fb,
  4109. .cleanup_fb = sde_plane_cleanup_fb,
  4110. .atomic_check = sde_plane_atomic_check,
  4111. .atomic_update = sde_plane_atomic_update,
  4112. };
  4113. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4114. {
  4115. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4116. }
  4117. bool is_sde_plane_virtual(struct drm_plane *plane)
  4118. {
  4119. return plane ? to_sde_plane(plane)->is_virtual : false;
  4120. }
  4121. /* initialize plane */
  4122. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4123. uint32_t pipe, bool primary_plane,
  4124. unsigned long possible_crtcs, u32 master_plane_id)
  4125. {
  4126. struct drm_plane *plane = NULL, *master_plane = NULL;
  4127. const struct sde_format_extended *format_list;
  4128. struct sde_plane *psde;
  4129. struct msm_drm_private *priv;
  4130. struct sde_kms *kms;
  4131. enum drm_plane_type type;
  4132. struct sde_vbif_clk_client clk_client;
  4133. int ret = -EINVAL;
  4134. if (!dev) {
  4135. SDE_ERROR("[%u]device is NULL\n", pipe);
  4136. goto exit;
  4137. }
  4138. priv = dev->dev_private;
  4139. if (!priv) {
  4140. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4141. goto exit;
  4142. }
  4143. if (!priv->kms) {
  4144. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4145. goto exit;
  4146. }
  4147. kms = to_sde_kms(priv->kms);
  4148. if (!kms->catalog) {
  4149. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4150. goto exit;
  4151. }
  4152. /* create and zero local structure */
  4153. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4154. if (!psde) {
  4155. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4156. ret = -ENOMEM;
  4157. goto exit;
  4158. }
  4159. /* cache local stuff for later */
  4160. plane = &psde->base;
  4161. psde->pipe = pipe;
  4162. psde->is_virtual = (master_plane_id != 0);
  4163. INIT_LIST_HEAD(&psde->mplane_list);
  4164. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4165. if (master_plane) {
  4166. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4167. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4168. }
  4169. /* initialize underlying h/w driver */
  4170. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4171. &clk_client);
  4172. if (IS_ERR(psde->pipe_hw)) {
  4173. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4174. ret = PTR_ERR(psde->pipe_hw);
  4175. goto clean_plane;
  4176. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4177. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4178. goto clean_sspp;
  4179. }
  4180. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4181. ret = sde_vbif_clk_register(kms, &clk_client);
  4182. if (ret) {
  4183. SDE_ERROR("failed to register vbif client %d\n",
  4184. clk_client.clk_ctrl);
  4185. goto clean_sspp;
  4186. }
  4187. }
  4188. /* cache features mask for later */
  4189. psde->features = psde->pipe_hw->cap->features_ext;
  4190. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4191. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4192. if (!psde->pipe_sblk) {
  4193. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4194. goto clean_sspp;
  4195. }
  4196. if (psde->is_virtual)
  4197. format_list = psde->pipe_sblk->virt_format_list;
  4198. else
  4199. format_list = psde->pipe_sblk->format_list;
  4200. psde->nformats = sde_populate_formats(format_list,
  4201. psde->formats,
  4202. 0,
  4203. ARRAY_SIZE(psde->formats));
  4204. if (!psde->nformats) {
  4205. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4206. goto clean_sspp;
  4207. }
  4208. if (primary_plane)
  4209. type = DRM_PLANE_TYPE_PRIMARY;
  4210. else
  4211. type = DRM_PLANE_TYPE_OVERLAY;
  4212. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4213. psde->formats, psde->nformats,
  4214. NULL, type, NULL);
  4215. if (ret)
  4216. goto clean_sspp;
  4217. /* Populate static array of plane property flags */
  4218. _sde_plane_map_prop_to_dirty_bits();
  4219. /* success! finalize initialization */
  4220. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4221. msm_property_init(&psde->property_info, &plane->base, dev,
  4222. priv->plane_property, psde->property_data,
  4223. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4224. sizeof(struct sde_plane_state));
  4225. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4226. /* save user friendly pipe name for later */
  4227. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4228. mutex_init(&psde->lock);
  4229. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4230. pipe, plane->base.id, master_plane_id);
  4231. return plane;
  4232. clean_sspp:
  4233. if (psde && psde->pipe_hw)
  4234. sde_hw_sspp_destroy(psde->pipe_hw);
  4235. clean_plane:
  4236. kfree(psde);
  4237. exit:
  4238. return ERR_PTR(ret);
  4239. }
  4240. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4241. {
  4242. struct sde_plane *sde_plane;
  4243. struct sde_plane_state *pstate;
  4244. sde_plane = to_sde_plane(plane);
  4245. pstate = to_sde_plane_state(plane->state);
  4246. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4247. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4248. }