sde_crtc.c 229 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/sort.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/ktime.h>
  23. #include <drm/sde_drm.h>
  24. #include <drm/drm_mode.h>
  25. #include <drm/drm_crtc.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include <drm/drm_flip_work.h>
  28. #include <soc/qcom/of_common.h>
  29. #include <linux/version.h>
  30. #include "sde_kms.h"
  31. #include "sde_hw_lm.h"
  32. #include "sde_hw_ctl.h"
  33. #include "sde_hw_dspp.h"
  34. #include "sde_crtc.h"
  35. #include "sde_plane.h"
  36. #include "sde_hw_util.h"
  37. #include "sde_hw_catalog.h"
  38. #include "sde_color_processing.h"
  39. #include "sde_encoder.h"
  40. #include "sde_connector.h"
  41. #include "sde_vbif.h"
  42. #include "sde_power_handle.h"
  43. #include "sde_core_perf.h"
  44. #include "sde_trace.h"
  45. #include "msm_drv.h"
  46. #include "sde_vm.h"
  47. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  48. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  49. /* Max number of planes with hw fences within one commit */
  50. #define MAX_HW_FENCES SDE_MULTIRECT_PLANE_MAX
  51. struct sde_crtc_custom_events {
  52. u32 event;
  53. int (*func)(struct drm_crtc *crtc, bool en,
  54. struct sde_irq_callback *irq);
  55. };
  56. struct vblank_work {
  57. struct kthread_work work;
  58. int crtc_id;
  59. bool enable;
  60. struct msm_drm_private *priv;
  61. };
  62. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  63. bool en, struct sde_irq_callback *ad_irq);
  64. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  65. bool en, struct sde_irq_callback *idle_irq);
  66. static int sde_crtc_mmrm_interrupt_handler(struct drm_crtc *crtc_drm,
  67. bool en, struct sde_irq_callback *idle_irq);
  68. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  69. struct sde_irq_callback *noirq);
  70. static int sde_crtc_frame_data_interrupt_handler(struct drm_crtc *crtc_drm,
  71. bool en, struct sde_irq_callback *idle_irq);
  72. static int _sde_crtc_set_noise_layer(struct sde_crtc *sde_crtc,
  73. struct sde_crtc_state *cstate,
  74. void __user *usr_ptr);
  75. static int sde_crtc_vm_release_handler(struct drm_crtc *crtc_drm,
  76. bool en, struct sde_irq_callback *irq);
  77. static int sde_crtc_opr_event_handler(struct drm_crtc *crtc_drm,
  78. bool en, struct sde_irq_callback *irq);
  79. static struct sde_crtc_custom_events custom_events[] = {
  80. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  81. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  82. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  83. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  84. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  85. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  86. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  87. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  88. {DRM_EVENT_MMRM_CB, sde_crtc_mmrm_interrupt_handler},
  89. {DRM_EVENT_VM_RELEASE, sde_crtc_vm_release_handler},
  90. {DRM_EVENT_FRAME_DATA, sde_crtc_frame_data_interrupt_handler},
  91. {DRM_EVENT_OPR_VALUE, sde_crtc_opr_event_handler},
  92. };
  93. /* default input fence timeout, in ms */
  94. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  95. /*
  96. * The default input fence timeout is 2 seconds while max allowed
  97. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  98. * tolerance limit.
  99. */
  100. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  101. /* layer mixer index on sde_crtc */
  102. #define LEFT_MIXER 0
  103. #define RIGHT_MIXER 1
  104. #define MISR_BUFF_SIZE 256
  105. /*
  106. * Time period for fps calculation in micro seconds.
  107. * Default value is set to 1 sec.
  108. */
  109. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  110. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  111. #define MAX_FRAME_COUNT 1000
  112. #define MILI_TO_MICRO 1000
  113. #define SKIP_STAGING_PIPE_ZPOS 255
  114. static void sde_crtc_install_noise_layer_properties(struct sde_crtc *sde_crtc,
  115. struct sde_mdss_cfg *catalog, struct sde_kms_info *info);
  116. static void sde_cp_crtc_apply_noise(struct drm_crtc *crtc,
  117. struct drm_crtc_state *state);
  118. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  119. {
  120. struct msm_drm_private *priv;
  121. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  122. SDE_ERROR("invalid crtc\n");
  123. return NULL;
  124. }
  125. priv = crtc->dev->dev_private;
  126. if (!priv || !priv->kms) {
  127. SDE_ERROR("invalid kms\n");
  128. return NULL;
  129. }
  130. return to_sde_kms(priv->kms);
  131. }
  132. enum sde_wb_usage_type sde_crtc_get_wb_usage_type(struct drm_crtc *crtc)
  133. {
  134. struct drm_connector *conn;
  135. struct drm_connector_list_iter conn_iter;
  136. enum sde_wb_usage_type usage_type = 0;
  137. drm_connector_list_iter_begin(crtc->dev, &conn_iter);
  138. drm_for_each_connector_iter(conn, &conn_iter) {
  139. if (conn->state && (conn->state->crtc == crtc)
  140. && (conn->connector_type == DRM_MODE_CONNECTOR_VIRTUAL)) {
  141. usage_type = sde_connector_get_property(conn->state,
  142. CONNECTOR_PROP_WB_USAGE_TYPE);
  143. break;
  144. }
  145. }
  146. drm_connector_list_iter_end(&conn_iter);
  147. return usage_type;
  148. }
  149. static inline struct drm_connector_state *_sde_crtc_get_virt_conn_state(
  150. struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
  151. {
  152. struct drm_connector *conn;
  153. struct drm_connector_state *conn_state, *virt_conn_state = NULL;
  154. struct drm_connector_list_iter conn_iter;
  155. int i;
  156. if (crtc_state->state) {
  157. for_each_new_connector_in_state(crtc_state->state, conn, conn_state, i) {
  158. if (conn_state && (conn_state->crtc == crtc)
  159. && (conn->connector_type == DRM_MODE_CONNECTOR_VIRTUAL)) {
  160. virt_conn_state = conn_state;
  161. break;
  162. }
  163. }
  164. } else {
  165. drm_connector_list_iter_begin(crtc->dev, &conn_iter);
  166. drm_for_each_connector_iter(conn, &conn_iter) {
  167. if (conn->state && (conn->state->crtc == crtc)
  168. && (conn->connector_type == DRM_MODE_CONNECTOR_VIRTUAL)) {
  169. virt_conn_state = conn->state;
  170. break;
  171. }
  172. }
  173. drm_connector_list_iter_end(&conn_iter);
  174. }
  175. return virt_conn_state;
  176. }
  177. void sde_crtc_get_mixer_resolution(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state,
  178. struct drm_display_mode *mode, u32 *width, u32 *height)
  179. {
  180. struct sde_crtc *sde_crtc;
  181. struct sde_crtc_state *cstate;
  182. struct drm_connector_state *virt_conn_state;
  183. struct sde_connector_state *virt_cstate;
  184. *width = 0;
  185. *height = 0;
  186. if (!crtc || !crtc_state || !mode)
  187. return;
  188. sde_crtc = to_sde_crtc(crtc);
  189. cstate = to_sde_crtc_state(crtc_state);
  190. virt_conn_state = _sde_crtc_get_virt_conn_state(crtc, crtc_state);
  191. virt_cstate = virt_conn_state ? to_sde_connector_state(virt_conn_state) : NULL;
  192. if (cstate->num_ds_enabled) {
  193. *width = cstate->ds_cfg[0].lm_width;
  194. *height = cstate->ds_cfg[0].lm_height;
  195. } else if (virt_cstate && virt_cstate->dnsc_blur_count) {
  196. *width = (virt_cstate->dnsc_blur_cfg[0].src_width
  197. * virt_cstate->dnsc_blur_count) / sde_crtc->num_mixers;
  198. *height = virt_cstate->dnsc_blur_cfg[0].src_height;
  199. } else {
  200. *width = mode->hdisplay / sde_crtc->num_mixers;
  201. *height = mode->vdisplay;
  202. }
  203. }
  204. void sde_crtc_get_resolution(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state,
  205. struct drm_display_mode *mode, u32 *width, u32 *height)
  206. {
  207. struct sde_crtc *sde_crtc;
  208. struct sde_crtc_state *cstate;
  209. struct drm_connector_state *virt_conn_state;
  210. struct sde_connector_state *virt_cstate;
  211. *width = 0;
  212. *height = 0;
  213. if (!crtc || !crtc_state || !mode)
  214. return;
  215. sde_crtc = to_sde_crtc(crtc);
  216. cstate = to_sde_crtc_state(crtc_state);
  217. virt_conn_state = _sde_crtc_get_virt_conn_state(crtc, crtc_state);
  218. virt_cstate = virt_conn_state ? to_sde_connector_state(virt_conn_state) : NULL;
  219. if (cstate->num_ds_enabled) {
  220. *width = cstate->ds_cfg[0].lm_width * cstate->num_ds_enabled;
  221. *height = cstate->ds_cfg[0].lm_height;
  222. } else if (virt_cstate && virt_cstate->dnsc_blur_count) {
  223. *width = virt_cstate->dnsc_blur_cfg[0].src_width * virt_cstate->dnsc_blur_count;
  224. *height = virt_cstate->dnsc_blur_cfg[0].src_height;
  225. } else {
  226. *width = mode->hdisplay;
  227. *height = mode->vdisplay;
  228. }
  229. }
  230. /**
  231. * sde_crtc_calc_fps() - Calculates fps value.
  232. * @sde_crtc : CRTC structure
  233. *
  234. * This function is called at frame done. It counts the number
  235. * of frames done for every 1 sec. Stores the value in measured_fps.
  236. * measured_fps value is 10 times the calculated fps value.
  237. * For example, measured_fps= 594 for calculated fps of 59.4
  238. */
  239. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  240. {
  241. ktime_t current_time_us;
  242. u64 fps, diff_us;
  243. current_time_us = ktime_get();
  244. diff_us = (u64)ktime_us_delta(current_time_us,
  245. sde_crtc->fps_info.last_sampled_time_us);
  246. sde_crtc->fps_info.frame_count++;
  247. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  248. /* Multiplying with 10 to get fps in floating point */
  249. fps = ((u64)sde_crtc->fps_info.frame_count)
  250. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  251. do_div(fps, diff_us);
  252. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  253. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  254. sde_crtc->base.base.id, (unsigned int)fps/10,
  255. (unsigned int)fps%10);
  256. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  257. sde_crtc->fps_info.frame_count = 0;
  258. }
  259. if (!sde_crtc->fps_info.time_buf)
  260. return;
  261. /**
  262. * Array indexing is based on sliding window algorithm.
  263. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  264. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  265. * counter loops around and comes back to the first index to store
  266. * the next ktime.
  267. */
  268. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  269. ktime_get();
  270. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  271. }
  272. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  273. {
  274. if (!sde_crtc)
  275. return;
  276. }
  277. #if IS_ENABLED(CONFIG_DEBUG_FS)
  278. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  279. {
  280. struct sde_crtc *sde_crtc;
  281. u64 fps_int, fps_float;
  282. ktime_t current_time_us;
  283. u64 fps, diff_us;
  284. if (!s || !s->private) {
  285. SDE_ERROR("invalid input param(s)\n");
  286. return -EAGAIN;
  287. }
  288. sde_crtc = s->private;
  289. current_time_us = ktime_get();
  290. diff_us = (u64)ktime_us_delta(current_time_us,
  291. sde_crtc->fps_info.last_sampled_time_us);
  292. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  293. /* Multiplying with 10 to get fps in floating point */
  294. fps = ((u64)sde_crtc->fps_info.frame_count)
  295. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  296. do_div(fps, diff_us);
  297. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  298. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  299. sde_crtc->fps_info.frame_count = 0;
  300. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  301. sde_crtc->base.base.id, (unsigned int)fps/10,
  302. (unsigned int)fps%10);
  303. }
  304. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  305. fps_float = do_div(fps_int, 10);
  306. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  307. return 0;
  308. }
  309. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  310. {
  311. return single_open(file, _sde_debugfs_fps_status_show,
  312. inode->i_private);
  313. }
  314. #endif /* CONFIG_DEBUG_FS */
  315. static ssize_t fps_periodicity_ms_store(struct device *device,
  316. struct device_attribute *attr, const char *buf, size_t count)
  317. {
  318. struct drm_crtc *crtc;
  319. struct sde_crtc *sde_crtc;
  320. int res;
  321. /* Base of the input */
  322. int cnt = 10;
  323. if (!device || !buf) {
  324. SDE_ERROR("invalid input param(s)\n");
  325. return -EAGAIN;
  326. }
  327. crtc = dev_get_drvdata(device);
  328. if (!crtc)
  329. return -EINVAL;
  330. sde_crtc = to_sde_crtc(crtc);
  331. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  332. if (res < 0)
  333. return res;
  334. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  335. sde_crtc->fps_info.fps_periodic_duration =
  336. DEFAULT_FPS_PERIOD_1_SEC;
  337. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  338. MAX_FPS_PERIOD_5_SECONDS)
  339. sde_crtc->fps_info.fps_periodic_duration =
  340. MAX_FPS_PERIOD_5_SECONDS;
  341. else
  342. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  343. return count;
  344. }
  345. static ssize_t fps_periodicity_ms_show(struct device *device,
  346. struct device_attribute *attr, char *buf)
  347. {
  348. struct drm_crtc *crtc;
  349. struct sde_crtc *sde_crtc;
  350. if (!device || !buf) {
  351. SDE_ERROR("invalid input param(s)\n");
  352. return -EAGAIN;
  353. }
  354. crtc = dev_get_drvdata(device);
  355. if (!crtc)
  356. return -EINVAL;
  357. sde_crtc = to_sde_crtc(crtc);
  358. return scnprintf(buf, PAGE_SIZE, "%d\n",
  359. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  360. }
  361. static ssize_t measured_fps_show(struct device *device,
  362. struct device_attribute *attr, char *buf)
  363. {
  364. struct drm_crtc *crtc;
  365. struct sde_crtc *sde_crtc;
  366. uint64_t fps_int, fps_decimal;
  367. u64 fps = 0, frame_count = 0;
  368. ktime_t current_time;
  369. int i = 0, current_time_index;
  370. u64 diff_us;
  371. if (!device || !buf) {
  372. SDE_ERROR("invalid input param(s)\n");
  373. return -EAGAIN;
  374. }
  375. crtc = dev_get_drvdata(device);
  376. if (!crtc) {
  377. scnprintf(buf, PAGE_SIZE, "fps information not available");
  378. return -EINVAL;
  379. }
  380. sde_crtc = to_sde_crtc(crtc);
  381. if (!sde_crtc->fps_info.time_buf) {
  382. scnprintf(buf, PAGE_SIZE,
  383. "timebuf null - fps information not available");
  384. return -EINVAL;
  385. }
  386. /**
  387. * Whenever the time_index counter comes to zero upon decrementing,
  388. * it is set to the last index since it is the next index that we
  389. * should check for calculating the buftime.
  390. */
  391. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  392. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  393. current_time = ktime_get();
  394. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  395. u64 ptime = (u64)ktime_to_us(current_time);
  396. u64 buftime = (u64)ktime_to_us(
  397. sde_crtc->fps_info.time_buf[current_time_index]);
  398. diff_us = (u64)ktime_us_delta(current_time,
  399. sde_crtc->fps_info.time_buf[current_time_index]);
  400. if (ptime > buftime && diff_us >= (u64)
  401. sde_crtc->fps_info.fps_periodic_duration) {
  402. /* Multiplying with 10 to get fps in floating point */
  403. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  404. do_div(fps, diff_us);
  405. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  406. SDE_DEBUG("measured fps: %d\n",
  407. sde_crtc->fps_info.measured_fps);
  408. break;
  409. }
  410. current_time_index = (current_time_index == 0) ?
  411. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  412. SDE_DEBUG("current time index: %d\n", current_time_index);
  413. frame_count++;
  414. }
  415. if (i == MAX_FRAME_COUNT) {
  416. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  417. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  418. diff_us = (u64)ktime_us_delta(current_time,
  419. sde_crtc->fps_info.time_buf[current_time_index]);
  420. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  421. /* Multiplying with 10 to get fps in floating point */
  422. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  423. do_div(fps, diff_us);
  424. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  425. }
  426. }
  427. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  428. fps_decimal = do_div(fps_int, 10);
  429. return scnprintf(buf, PAGE_SIZE,
  430. "fps: %lld.%lld duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  431. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  432. }
  433. static ssize_t vsync_event_show(struct device *device,
  434. struct device_attribute *attr, char *buf)
  435. {
  436. struct drm_crtc *crtc;
  437. struct sde_crtc *sde_crtc;
  438. struct drm_encoder *encoder;
  439. int avr_status = -EPIPE;
  440. if (!device || !buf) {
  441. SDE_ERROR("invalid input param(s)\n");
  442. return -EAGAIN;
  443. }
  444. crtc = dev_get_drvdata(device);
  445. sde_crtc = to_sde_crtc(crtc);
  446. mutex_lock(&sde_crtc->crtc_lock);
  447. if (sde_crtc->enabled) {
  448. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  449. if (sde_encoder_in_clone_mode(encoder))
  450. continue;
  451. avr_status = sde_encoder_get_avr_status(encoder);
  452. break;
  453. }
  454. }
  455. mutex_unlock(&sde_crtc->crtc_lock);
  456. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\nAVR_STATUS=%d\n",
  457. ktime_to_ns(sde_crtc->vblank_last_cb_time), avr_status);
  458. }
  459. static ssize_t retire_frame_event_show(struct device *device,
  460. struct device_attribute *attr, char *buf)
  461. {
  462. struct drm_crtc *crtc;
  463. struct sde_crtc *sde_crtc;
  464. if (!device || !buf) {
  465. SDE_ERROR("invalid input param(s)\n");
  466. return -EAGAIN;
  467. }
  468. crtc = dev_get_drvdata(device);
  469. sde_crtc = to_sde_crtc(crtc);
  470. return scnprintf(buf, PAGE_SIZE, "RETIRE_FRAME_TIME=%llu\n",
  471. ktime_to_ns(sde_crtc->retire_frame_event_time));
  472. }
  473. static DEVICE_ATTR_RO(vsync_event);
  474. static DEVICE_ATTR_RO(measured_fps);
  475. static DEVICE_ATTR_RW(fps_periodicity_ms);
  476. static DEVICE_ATTR_RO(retire_frame_event);
  477. static struct attribute *sde_crtc_dev_attrs[] = {
  478. &dev_attr_vsync_event.attr,
  479. &dev_attr_measured_fps.attr,
  480. &dev_attr_fps_periodicity_ms.attr,
  481. &dev_attr_retire_frame_event.attr,
  482. NULL
  483. };
  484. static const struct attribute_group sde_crtc_attr_group = {
  485. .attrs = sde_crtc_dev_attrs,
  486. };
  487. static const struct attribute_group *sde_crtc_attr_groups[] = {
  488. &sde_crtc_attr_group,
  489. NULL,
  490. };
  491. static void sde_crtc_event_notify(struct drm_crtc *crtc, uint32_t type, void *payload, uint32_t len)
  492. {
  493. struct drm_event event;
  494. uint32_t *data = (uint32_t *)payload;
  495. if (!crtc) {
  496. SDE_ERROR("invalid crtc\n");
  497. return;
  498. }
  499. event.type = type;
  500. event.length = len;
  501. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, (u8 *)payload);
  502. SDE_EVT32(DRMID(crtc), type, len, *data,
  503. ((uint64_t)payload) >> 32, ((uint64_t)payload) & 0xFFFFFFFF);
  504. SDE_DEBUG("crtc:%d event(%lu) ptr(%pK) value(%lu) notified\n",
  505. DRMID(crtc), type, payload, *data);
  506. }
  507. static void sde_crtc_destroy(struct drm_crtc *crtc)
  508. {
  509. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  510. SDE_DEBUG("\n");
  511. if (!crtc)
  512. return;
  513. if (sde_crtc->vsync_event_sf)
  514. sysfs_put(sde_crtc->vsync_event_sf);
  515. if (sde_crtc->retire_frame_event_sf)
  516. sysfs_put(sde_crtc->retire_frame_event_sf);
  517. if (sde_crtc->sysfs_dev)
  518. device_unregister(sde_crtc->sysfs_dev);
  519. if (sde_crtc->blob_info)
  520. drm_property_blob_put(sde_crtc->blob_info);
  521. msm_property_destroy(&sde_crtc->property_info);
  522. sde_cp_crtc_destroy_properties(crtc);
  523. sde_fence_deinit(sde_crtc->output_fence);
  524. _sde_crtc_deinit_events(sde_crtc);
  525. drm_crtc_cleanup(crtc);
  526. mutex_destroy(&sde_crtc->crtc_lock);
  527. kfree(sde_crtc);
  528. }
  529. struct sde_connector_state *_sde_crtc_get_sde_connector_state(struct drm_crtc *crtc,
  530. struct drm_atomic_state *state)
  531. {
  532. struct drm_connector *conn;
  533. struct drm_connector_state *conn_state;
  534. int i;
  535. for_each_new_connector_in_state(state, conn, conn_state, i) {
  536. if (!conn_state || conn_state->crtc != crtc)
  537. continue;
  538. return to_sde_connector_state(conn_state);
  539. }
  540. return NULL;
  541. }
  542. struct msm_display_mode *sde_crtc_get_msm_mode(struct drm_crtc_state *c_state)
  543. {
  544. struct drm_connector *connector;
  545. struct drm_encoder *encoder;
  546. struct sde_connector_state *conn_state;
  547. bool encoder_valid = false;
  548. drm_for_each_encoder_mask(encoder, c_state->crtc->dev,
  549. c_state->encoder_mask) {
  550. if (!sde_encoder_in_clone_mode(encoder)) {
  551. encoder_valid = true;
  552. break;
  553. }
  554. }
  555. if (!encoder_valid)
  556. return NULL;
  557. connector = sde_encoder_get_connector(c_state->crtc->dev, encoder);
  558. if (!connector)
  559. return NULL;
  560. conn_state = to_sde_connector_state(connector->state);
  561. if (!conn_state)
  562. return NULL;
  563. return &conn_state->msm_mode;
  564. }
  565. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  566. const struct drm_display_mode *mode,
  567. struct drm_display_mode *adjusted_mode)
  568. {
  569. struct msm_display_mode *msm_mode;
  570. struct drm_crtc_state *c_state;
  571. struct drm_connector *connector;
  572. struct drm_encoder *encoder;
  573. struct drm_connector_state *new_conn_state;
  574. struct sde_connector_state *c_conn_state = NULL;
  575. bool encoder_valid = false;
  576. int i;
  577. SDE_DEBUG("\n");
  578. c_state = container_of(adjusted_mode, struct drm_crtc_state,
  579. adjusted_mode);
  580. drm_for_each_encoder_mask(encoder, c_state->crtc->dev,
  581. c_state->encoder_mask) {
  582. if (!sde_crtc_state_in_clone_mode(encoder, c_state)) {
  583. encoder_valid = true;
  584. break;
  585. }
  586. }
  587. if (!encoder_valid) {
  588. SDE_ERROR("encoder not found\n");
  589. return true;
  590. }
  591. for_each_new_connector_in_state(c_state->state, connector,
  592. new_conn_state, i) {
  593. if (new_conn_state->best_encoder == encoder) {
  594. c_conn_state = to_sde_connector_state(new_conn_state);
  595. break;
  596. }
  597. }
  598. if (!c_conn_state) {
  599. SDE_ERROR("could not get connector state\n");
  600. return true;
  601. }
  602. msm_mode = &c_conn_state->msm_mode;
  603. if ((msm_is_mode_seamless(msm_mode) ||
  604. (msm_is_mode_seamless_vrr(msm_mode) ||
  605. msm_is_mode_seamless_dyn_clk(msm_mode))) &&
  606. (!crtc->enabled)) {
  607. SDE_ERROR("crtc state prevents seamless transition\n");
  608. return false;
  609. }
  610. return true;
  611. }
  612. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  613. struct sde_plane_state *pstate, struct sde_format *format)
  614. {
  615. uint32_t blend_op, fg_alpha, bg_alpha;
  616. uint32_t blend_type;
  617. struct sde_hw_mixer *lm = mixer->hw_lm;
  618. /* default to opaque blending */
  619. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  620. bg_alpha = 0xFF - fg_alpha;
  621. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  622. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  623. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  624. switch (blend_type) {
  625. case SDE_DRM_BLEND_OP_OPAQUE:
  626. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  627. SDE_BLEND_BG_ALPHA_BG_CONST;
  628. break;
  629. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  630. if (format->alpha_enable) {
  631. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  632. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  633. if (fg_alpha != 0xff) {
  634. bg_alpha = fg_alpha;
  635. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  636. SDE_BLEND_BG_INV_MOD_ALPHA;
  637. } else {
  638. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  639. }
  640. }
  641. break;
  642. case SDE_DRM_BLEND_OP_COVERAGE:
  643. if (format->alpha_enable) {
  644. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  645. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  646. if (fg_alpha != 0xff) {
  647. bg_alpha = fg_alpha;
  648. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  649. SDE_BLEND_BG_MOD_ALPHA |
  650. SDE_BLEND_BG_INV_MOD_ALPHA;
  651. } else {
  652. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  653. }
  654. }
  655. break;
  656. default:
  657. /* do nothing */
  658. break;
  659. }
  660. if (lm->ops.setup_blend_config)
  661. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha, bg_alpha, blend_op);
  662. SDE_DEBUG(
  663. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  664. (char *) &format->base.pixel_format,
  665. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  666. }
  667. static void _sde_crtc_calc_split_dim_layer_yh_param(struct drm_crtc *crtc, u16 *y, u16 *h)
  668. {
  669. u32 padding_y = 0, padding_start = 0, padding_height = 0;
  670. struct sde_crtc_state *cstate;
  671. cstate = to_sde_crtc_state(crtc->state);
  672. if (!cstate->line_insertion.panel_line_insertion_enable)
  673. return;
  674. sde_crtc_calc_vpadding_param(crtc->state, *y, *h, &padding_y,
  675. &padding_start, &padding_height);
  676. *y = padding_y;
  677. *h = padding_height;
  678. }
  679. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  680. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  681. struct sde_hw_dim_layer *dim_layer)
  682. {
  683. struct sde_crtc_state *cstate;
  684. struct sde_hw_mixer *lm;
  685. struct sde_hw_dim_layer split_dim_layer;
  686. int i;
  687. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  688. SDE_DEBUG("empty dim_layer\n");
  689. return;
  690. }
  691. cstate = to_sde_crtc_state(crtc->state);
  692. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  693. dim_layer->flags, dim_layer->stage);
  694. split_dim_layer.stage = dim_layer->stage;
  695. split_dim_layer.color_fill = dim_layer->color_fill;
  696. /*
  697. * traverse through the layer mixers attached to crtc and find the
  698. * intersecting dim layer rect in each LM and program accordingly.
  699. */
  700. for (i = 0; i < sde_crtc->num_mixers; i++) {
  701. split_dim_layer.flags = dim_layer->flags;
  702. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  703. &split_dim_layer.rect);
  704. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  705. /*
  706. * no extra programming required for non-intersecting
  707. * layer mixers with INCLUSIVE dim layer
  708. */
  709. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  710. continue;
  711. /*
  712. * program the other non-intersecting layer mixers with
  713. * INCLUSIVE dim layer of full size for uniformity
  714. * with EXCLUSIVE dim layer config.
  715. */
  716. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  717. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  718. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  719. sizeof(split_dim_layer.rect));
  720. } else {
  721. split_dim_layer.rect.x =
  722. split_dim_layer.rect.x -
  723. cstate->lm_roi[i].x;
  724. split_dim_layer.rect.y =
  725. split_dim_layer.rect.y -
  726. cstate->lm_roi[i].y;
  727. }
  728. /* update dim layer rect for panel stacking crtc */
  729. if (cstate->line_insertion.padding_height)
  730. _sde_crtc_calc_split_dim_layer_yh_param(crtc, &split_dim_layer.rect.y,
  731. &split_dim_layer.rect.h);
  732. SDE_EVT32(DRMID(crtc), dim_layer->stage,
  733. cstate->lm_roi[i].x,
  734. cstate->lm_roi[i].y,
  735. cstate->lm_roi[i].w,
  736. cstate->lm_roi[i].h,
  737. dim_layer->rect.x,
  738. dim_layer->rect.y,
  739. dim_layer->rect.w,
  740. dim_layer->rect.h,
  741. split_dim_layer.rect.x,
  742. split_dim_layer.rect.y,
  743. split_dim_layer.rect.w,
  744. split_dim_layer.rect.h);
  745. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  746. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  747. split_dim_layer.rect.w, split_dim_layer.rect.h);
  748. lm = mixer[i].hw_lm;
  749. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  750. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  751. }
  752. }
  753. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  754. const struct sde_rect **crtc_roi)
  755. {
  756. struct sde_crtc_state *crtc_state;
  757. if (!state || !crtc_roi)
  758. return;
  759. crtc_state = to_sde_crtc_state(state);
  760. *crtc_roi = &crtc_state->crtc_roi;
  761. }
  762. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  763. {
  764. struct sde_crtc_state *cstate;
  765. struct sde_crtc *sde_crtc;
  766. if (!state || !state->crtc)
  767. return false;
  768. sde_crtc = to_sde_crtc(state->crtc);
  769. cstate = to_sde_crtc_state(state);
  770. return msm_property_is_dirty(&sde_crtc->property_info,
  771. &cstate->property_state, CRTC_PROP_ROI_V1);
  772. }
  773. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  774. void __user *usr_ptr)
  775. {
  776. struct drm_crtc *crtc;
  777. struct sde_crtc_state *cstate;
  778. struct sde_drm_roi_v1 roi_v1;
  779. int i;
  780. if (!state) {
  781. SDE_ERROR("invalid args\n");
  782. return -EINVAL;
  783. }
  784. cstate = to_sde_crtc_state(state);
  785. crtc = cstate->base.crtc;
  786. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  787. if (!usr_ptr) {
  788. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  789. return 0;
  790. }
  791. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  792. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  793. return -EINVAL;
  794. }
  795. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  796. if (roi_v1.num_rects == 0) {
  797. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  798. return 0;
  799. }
  800. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  801. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  802. roi_v1.num_rects);
  803. return -EINVAL;
  804. }
  805. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  806. for (i = 0; i < roi_v1.num_rects; ++i) {
  807. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  808. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  809. DRMID(crtc), i,
  810. cstate->user_roi_list.roi[i].x1,
  811. cstate->user_roi_list.roi[i].y1,
  812. cstate->user_roi_list.roi[i].x2,
  813. cstate->user_roi_list.roi[i].y2);
  814. SDE_EVT32_VERBOSE(DRMID(crtc),
  815. cstate->user_roi_list.roi[i].x1,
  816. cstate->user_roi_list.roi[i].y1,
  817. cstate->user_roi_list.roi[i].x2,
  818. cstate->user_roi_list.roi[i].y2);
  819. }
  820. return 0;
  821. }
  822. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  823. struct drm_crtc_state *state)
  824. {
  825. struct drm_connector *conn;
  826. struct drm_connector_state *conn_state;
  827. struct sde_crtc *sde_crtc;
  828. struct sde_crtc_state *crtc_state;
  829. struct sde_rect *crtc_roi;
  830. struct msm_mode_info mode_info;
  831. int i = 0, rc;
  832. bool is_crtc_roi_dirty, is_conn_roi_dirty;
  833. u32 crtc_width, crtc_height;
  834. struct drm_display_mode *adj_mode;
  835. if (!crtc || !state)
  836. return -EINVAL;
  837. sde_crtc = to_sde_crtc(crtc);
  838. crtc_state = to_sde_crtc_state(state);
  839. crtc_roi = &crtc_state->crtc_roi;
  840. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  841. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  842. struct sde_connector *sde_conn;
  843. struct sde_connector_state *sde_conn_state;
  844. struct sde_rect conn_roi;
  845. if (!conn_state || conn_state->crtc != crtc)
  846. continue;
  847. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  848. if (rc) {
  849. SDE_ERROR("failed to get mode info\n");
  850. return -EINVAL;
  851. }
  852. sde_conn = to_sde_connector(conn_state->connector);
  853. sde_conn_state = to_sde_connector_state(conn_state);
  854. is_conn_roi_dirty = msm_property_is_dirty(&sde_conn->property_info,
  855. &sde_conn_state->property_state,
  856. CONNECTOR_PROP_ROI_V1);
  857. /*
  858. * Check against CRTC ROI and Connector ROI not being updated together.
  859. * This restriction should be relaxed when Connector ROI scaling is
  860. * supported and while in clone mode.
  861. */
  862. if (!sde_crtc_state_in_clone_mode(sde_conn->encoder, state) &&
  863. is_conn_roi_dirty != is_crtc_roi_dirty) {
  864. SDE_ERROR("connector/crtc rois not updated together\n");
  865. return -EINVAL;
  866. }
  867. if (!mode_info.roi_caps.enabled)
  868. continue;
  869. /*
  870. * current driver only supports same connector and crtc size,
  871. * but if support for different sizes is added, driver needs
  872. * to check the connector roi here to make sure is full screen
  873. * for dsc 3d-mux topology that doesn't support partial update.
  874. */
  875. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  876. sizeof(crtc_state->user_roi_list))) {
  877. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  878. sde_crtc->name);
  879. return -EINVAL;
  880. }
  881. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  882. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  883. conn_roi.x, conn_roi.y,
  884. conn_roi.w, conn_roi.h);
  885. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  886. conn_roi.x, conn_roi.y,
  887. conn_roi.w, conn_roi.h);
  888. }
  889. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  890. /* clear the ROI to null if it matches full screen anyways */
  891. adj_mode = &state->adjusted_mode;
  892. sde_crtc_get_resolution(crtc, state, adj_mode, &crtc_width, &crtc_height);
  893. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  894. crtc_roi->w == crtc_width && crtc_roi->h == crtc_height)
  895. memset(crtc_roi, 0, sizeof(*crtc_roi));
  896. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  897. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  898. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  899. return 0;
  900. }
  901. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  902. struct drm_crtc_state *state)
  903. {
  904. struct sde_crtc *sde_crtc;
  905. struct sde_crtc_state *crtc_state;
  906. struct drm_connector *conn;
  907. struct drm_connector_state *conn_state;
  908. int i;
  909. if (!crtc || !state)
  910. return -EINVAL;
  911. sde_crtc = to_sde_crtc(crtc);
  912. crtc_state = to_sde_crtc_state(state);
  913. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  914. return 0;
  915. /* partial update active, check if autorefresh is also requested */
  916. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  917. uint64_t autorefresh;
  918. if (!conn_state || conn_state->crtc != crtc)
  919. continue;
  920. autorefresh = sde_connector_get_property(conn_state,
  921. CONNECTOR_PROP_AUTOREFRESH);
  922. if (autorefresh) {
  923. SDE_ERROR(
  924. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  925. sde_crtc->name, autorefresh);
  926. return -EINVAL;
  927. }
  928. }
  929. return 0;
  930. }
  931. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  932. struct drm_crtc_state *state, int lm_idx)
  933. {
  934. struct sde_kms *sde_kms;
  935. struct sde_crtc *sde_crtc;
  936. struct sde_crtc_state *crtc_state;
  937. const struct sde_rect *crtc_roi;
  938. const struct sde_rect *lm_bounds;
  939. struct sde_rect *lm_roi;
  940. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  941. return -EINVAL;
  942. sde_kms = _sde_crtc_get_kms(crtc);
  943. if (!sde_kms || !sde_kms->catalog) {
  944. SDE_ERROR("invalid parameters\n");
  945. return -EINVAL;
  946. }
  947. sde_crtc = to_sde_crtc(crtc);
  948. crtc_state = to_sde_crtc_state(state);
  949. crtc_roi = &crtc_state->crtc_roi;
  950. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  951. lm_roi = &crtc_state->lm_roi[lm_idx];
  952. if (sde_kms_rect_is_null(crtc_roi))
  953. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  954. else
  955. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  956. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  957. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  958. /*
  959. * partial update is not supported with 3dmux dsc or dest scaler.
  960. * hence, crtc roi must match the mixer dimensions.
  961. */
  962. if (crtc_state->num_ds_enabled ||
  963. sde_rm_topology_is_group(&sde_kms->rm, state,
  964. SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC)) {
  965. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  966. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  967. return -EINVAL;
  968. }
  969. }
  970. /* if any dimension is zero, clear all dimensions for clarity */
  971. if (sde_kms_rect_is_null(lm_roi))
  972. memset(lm_roi, 0, sizeof(*lm_roi));
  973. return 0;
  974. }
  975. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  976. struct drm_crtc_state *state)
  977. {
  978. struct sde_crtc *sde_crtc;
  979. struct sde_crtc_state *crtc_state;
  980. u32 disp_bitmask = 0;
  981. int i;
  982. if (!crtc || !state) {
  983. pr_err("Invalid crtc or state\n");
  984. return 0;
  985. }
  986. sde_crtc = to_sde_crtc(crtc);
  987. crtc_state = to_sde_crtc_state(state);
  988. /* pingpong split: one ROI, one LM, two physical displays */
  989. if (crtc_state->is_ppsplit) {
  990. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  991. struct sde_rect *roi = &crtc_state->lm_roi[0];
  992. if (sde_kms_rect_is_null(roi))
  993. disp_bitmask = 0;
  994. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  995. disp_bitmask = BIT(0); /* left only */
  996. else if (roi->x >= lm_split_width)
  997. disp_bitmask = BIT(1); /* right only */
  998. else
  999. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  1000. } else if (sde_crtc->mixers_swapped) {
  1001. disp_bitmask = BIT(0);
  1002. } else {
  1003. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1004. if (!sde_kms_rect_is_null(
  1005. &crtc_state->lm_roi[i]))
  1006. disp_bitmask |= BIT(i);
  1007. }
  1008. }
  1009. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  1010. return disp_bitmask;
  1011. }
  1012. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  1013. struct drm_crtc_state *state)
  1014. {
  1015. struct sde_crtc *sde_crtc;
  1016. struct sde_crtc_state *crtc_state;
  1017. const struct sde_rect *roi[MAX_MIXERS_PER_CRTC];
  1018. if (!crtc || !state)
  1019. return -EINVAL;
  1020. sde_crtc = to_sde_crtc(crtc);
  1021. crtc_state = to_sde_crtc_state(state);
  1022. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1023. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  1024. sde_crtc->name, sde_crtc->num_mixers);
  1025. return -EINVAL;
  1026. }
  1027. /*
  1028. * If using pingpong split: one ROI, one LM, two physical displays
  1029. * then the ROI must be centered on the panel split boundary and
  1030. * be of equal width across the split.
  1031. */
  1032. if (crtc_state->is_ppsplit) {
  1033. u16 panel_split_width;
  1034. u32 display_mask;
  1035. roi[0] = &crtc_state->lm_roi[0];
  1036. if (sde_kms_rect_is_null(roi[0]))
  1037. return 0;
  1038. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  1039. if (display_mask != (BIT(0) | BIT(1)))
  1040. return 0;
  1041. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  1042. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  1043. SDE_ERROR("%s: roi x %d w %d split %d\n",
  1044. sde_crtc->name, roi[0]->x, roi[0]->w,
  1045. panel_split_width);
  1046. return -EINVAL;
  1047. }
  1048. return 0;
  1049. }
  1050. /*
  1051. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  1052. * LMs and be of equal width.
  1053. */
  1054. if (sde_crtc->num_mixers < CRTC_DUAL_MIXERS_ONLY)
  1055. return 0;
  1056. roi[0] = &crtc_state->lm_roi[0];
  1057. roi[1] = &crtc_state->lm_roi[1];
  1058. /* if one of the roi is null it's a left/right-only update */
  1059. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  1060. return 0;
  1061. /* check lm rois are equal width & first roi ends at 2nd roi */
  1062. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  1063. SDE_ERROR(
  1064. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  1065. sde_crtc->name, roi[0]->x, roi[0]->w,
  1066. roi[1]->x, roi[1]->w);
  1067. return -EINVAL;
  1068. }
  1069. return 0;
  1070. }
  1071. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  1072. struct drm_crtc_state *state)
  1073. {
  1074. struct sde_crtc *sde_crtc;
  1075. struct sde_crtc_state *crtc_state;
  1076. const struct sde_rect *crtc_roi;
  1077. const struct drm_plane_state *pstate;
  1078. struct drm_plane *plane;
  1079. if (!crtc || !state)
  1080. return -EINVAL;
  1081. /*
  1082. * Reject commit if a Plane CRTC destination coordinates fall outside
  1083. * the partial CRTC ROI. LM output is determined via connector ROIs,
  1084. * if they are specified, not Plane CRTC ROIs.
  1085. */
  1086. sde_crtc = to_sde_crtc(crtc);
  1087. crtc_state = to_sde_crtc_state(state);
  1088. crtc_roi = &crtc_state->crtc_roi;
  1089. if (sde_kms_rect_is_null(crtc_roi))
  1090. return 0;
  1091. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1092. struct sde_rect plane_roi, intersection;
  1093. if (IS_ERR_OR_NULL(pstate)) {
  1094. int rc = PTR_ERR(pstate);
  1095. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  1096. sde_crtc->name, plane->base.id, rc);
  1097. return rc;
  1098. }
  1099. plane_roi.x = pstate->crtc_x;
  1100. plane_roi.y = pstate->crtc_y;
  1101. plane_roi.w = pstate->crtc_w;
  1102. plane_roi.h = pstate->crtc_h;
  1103. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  1104. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  1105. SDE_ERROR(
  1106. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  1107. sde_crtc->name, plane->base.id,
  1108. plane_roi.x, plane_roi.y,
  1109. plane_roi.w, plane_roi.h,
  1110. crtc_roi->x, crtc_roi->y,
  1111. crtc_roi->w, crtc_roi->h);
  1112. return -E2BIG;
  1113. }
  1114. }
  1115. return 0;
  1116. }
  1117. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  1118. struct drm_crtc_state *state)
  1119. {
  1120. struct sde_crtc *sde_crtc;
  1121. struct sde_crtc_state *sde_crtc_state;
  1122. struct msm_mode_info mode_info;
  1123. int rc, lm_idx, i;
  1124. if (!crtc || !state)
  1125. return -EINVAL;
  1126. memset(&mode_info, 0, sizeof(mode_info));
  1127. sde_crtc = to_sde_crtc(crtc);
  1128. sde_crtc_state = to_sde_crtc_state(state);
  1129. /*
  1130. * check connector array cached at modeset time since incoming atomic
  1131. * state may not include any connectors if they aren't modified
  1132. */
  1133. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  1134. struct drm_connector *conn = sde_crtc_state->connectors[i];
  1135. if (!conn || !conn->state)
  1136. continue;
  1137. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  1138. if (rc) {
  1139. SDE_ERROR("failed to get mode info\n");
  1140. return -EINVAL;
  1141. }
  1142. if (!mode_info.roi_caps.enabled)
  1143. continue;
  1144. if (sde_crtc_state->user_roi_list.num_rects >
  1145. mode_info.roi_caps.num_roi) {
  1146. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  1147. sde_crtc_state->user_roi_list.num_rects,
  1148. mode_info.roi_caps.num_roi);
  1149. return -E2BIG;
  1150. }
  1151. rc = _sde_crtc_set_crtc_roi(crtc, state);
  1152. if (rc)
  1153. return rc;
  1154. rc = _sde_crtc_check_autorefresh(crtc, state);
  1155. if (rc)
  1156. return rc;
  1157. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  1158. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  1159. if (rc)
  1160. return rc;
  1161. }
  1162. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  1163. if (rc)
  1164. return rc;
  1165. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  1166. if (rc)
  1167. return rc;
  1168. }
  1169. return 0;
  1170. }
  1171. static u32 _sde_crtc_calc_gcd(u32 a, u32 b)
  1172. {
  1173. if (b == 0)
  1174. return a;
  1175. return _sde_crtc_calc_gcd(b, a % b);
  1176. }
  1177. static int _sde_crtc_check_panel_stacking(struct drm_crtc *crtc, struct drm_crtc_state *state)
  1178. {
  1179. struct sde_kms *kms;
  1180. struct sde_crtc *sde_crtc;
  1181. struct sde_crtc_state *sde_crtc_state;
  1182. struct drm_connector *conn;
  1183. struct msm_mode_info mode_info;
  1184. struct drm_display_mode *adj_mode = &state->adjusted_mode;
  1185. struct msm_sub_mode sub_mode;
  1186. u32 gcd = 0, num_of_active_lines = 0, num_of_dummy_lines = 0;
  1187. int rc;
  1188. struct drm_encoder *encoder;
  1189. const u32 max_encoder_cnt = 1;
  1190. u32 encoder_cnt = 0;
  1191. kms = _sde_crtc_get_kms(crtc);
  1192. if (!kms || !kms->catalog) {
  1193. SDE_ERROR("invalid kms\n");
  1194. return -EINVAL;
  1195. }
  1196. sde_crtc = to_sde_crtc(crtc);
  1197. sde_crtc_state = to_sde_crtc_state(state);
  1198. /* panel stacking only support single connector */
  1199. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
  1200. encoder_cnt++;
  1201. if (!kms->catalog->has_line_insertion || !state->mode_changed ||
  1202. encoder_cnt > max_encoder_cnt) {
  1203. SDE_DEBUG("no line insertion support mode change %d enc cnt %d\n",
  1204. state->mode_changed, encoder_cnt);
  1205. sde_crtc_state->line_insertion.padding_height = 0;
  1206. return 0;
  1207. }
  1208. conn = sde_crtc_state->connectors[0];
  1209. rc = sde_connector_get_mode_info(conn, adj_mode, &sub_mode, &mode_info);
  1210. if (rc) {
  1211. SDE_ERROR("failed to get mode info %d\n", rc);
  1212. return -EINVAL;
  1213. }
  1214. if (!mode_info.vpadding) {
  1215. sde_crtc_state->line_insertion.padding_height = 0;
  1216. return 0;
  1217. }
  1218. if (mode_info.vpadding < state->mode.vdisplay) {
  1219. SDE_ERROR("padding height %d is less than vdisplay %d\n",
  1220. mode_info.vpadding, state->mode.vdisplay);
  1221. return -EINVAL;
  1222. } else if (mode_info.vpadding == state->mode.vdisplay) {
  1223. SDE_DEBUG("padding height %d is equal to the vdisplay %d\n",
  1224. mode_info.vpadding, state->mode.vdisplay);
  1225. sde_crtc_state->line_insertion.padding_height = 0;
  1226. return 0;
  1227. } else if (mode_info.vpadding == sde_crtc_state->line_insertion.padding_height) {
  1228. return 0; /* skip calculation if already cached */
  1229. }
  1230. gcd = _sde_crtc_calc_gcd(mode_info.vpadding, state->mode.vdisplay);
  1231. if (!gcd) {
  1232. SDE_ERROR("zero gcd found for padding height %d %d\n",
  1233. mode_info.vpadding, state->mode.vdisplay);
  1234. return -EINVAL;
  1235. }
  1236. num_of_active_lines = state->mode.vdisplay;
  1237. do_div(num_of_active_lines, gcd);
  1238. num_of_dummy_lines = mode_info.vpadding;
  1239. do_div(num_of_dummy_lines, gcd);
  1240. num_of_dummy_lines = num_of_dummy_lines - num_of_active_lines;
  1241. if (num_of_active_lines > MAX_VPADDING_RATIO_M ||
  1242. num_of_dummy_lines > MAX_VPADDING_RATIO_N) {
  1243. SDE_ERROR("unsupported panel stacking pattern %d:%d", num_of_active_lines,
  1244. num_of_dummy_lines);
  1245. return -EINVAL;
  1246. }
  1247. sde_crtc_state->line_insertion.padding_active = num_of_active_lines;
  1248. sde_crtc_state->line_insertion.padding_dummy = num_of_dummy_lines;
  1249. sde_crtc_state->line_insertion.padding_height = mode_info.vpadding;
  1250. return 0;
  1251. }
  1252. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  1253. {
  1254. struct sde_crtc *sde_crtc;
  1255. struct sde_crtc_state *cstate;
  1256. const struct sde_rect *lm_roi;
  1257. struct sde_hw_mixer *hw_lm;
  1258. bool right_mixer = false;
  1259. bool lm_updated = false;
  1260. int lm_idx;
  1261. if (!crtc)
  1262. return;
  1263. sde_crtc = to_sde_crtc(crtc);
  1264. cstate = to_sde_crtc_state(crtc->state);
  1265. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  1266. struct sde_hw_mixer_cfg cfg;
  1267. lm_roi = &cstate->lm_roi[lm_idx];
  1268. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1269. if (!sde_crtc->mixers_swapped)
  1270. right_mixer = lm_idx % MAX_MIXERS_PER_LAYOUT;
  1271. if (lm_roi->w != hw_lm->cfg.out_width ||
  1272. lm_roi->h != hw_lm->cfg.out_height ||
  1273. right_mixer != hw_lm->cfg.right_mixer) {
  1274. hw_lm->cfg.out_width = lm_roi->w;
  1275. hw_lm->cfg.out_height = lm_roi->h;
  1276. hw_lm->cfg.right_mixer = right_mixer;
  1277. cfg.out_width = lm_roi->w;
  1278. cfg.out_height = lm_roi->h;
  1279. cfg.right_mixer = right_mixer;
  1280. cfg.flags = 0;
  1281. if (hw_lm->ops.setup_mixer_out)
  1282. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  1283. lm_updated = true;
  1284. }
  1285. SDE_EVT32(DRMID(crtc), lm_idx, lm_roi->x, lm_roi->y, lm_roi->w,
  1286. lm_roi->h, right_mixer, lm_updated);
  1287. }
  1288. if (lm_updated)
  1289. sde_cp_crtc_res_change(crtc);
  1290. }
  1291. struct plane_state {
  1292. struct sde_plane_state *sde_pstate;
  1293. const struct drm_plane_state *drm_pstate;
  1294. int stage;
  1295. u32 pipe_id;
  1296. };
  1297. static int pstate_cmp(const void *a, const void *b)
  1298. {
  1299. struct plane_state *pa = (struct plane_state *)a;
  1300. struct plane_state *pb = (struct plane_state *)b;
  1301. int rc = 0;
  1302. int pa_zpos, pb_zpos;
  1303. enum sde_layout pa_layout, pb_layout;
  1304. if ((!pa || !pa->sde_pstate) || (!pb || !pb->sde_pstate))
  1305. return rc;
  1306. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  1307. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  1308. pa_layout = pa->sde_pstate->layout;
  1309. pb_layout = pb->sde_pstate->layout;
  1310. if (pa_zpos != pb_zpos)
  1311. rc = pa_zpos - pb_zpos;
  1312. else if (pa_layout != pb_layout)
  1313. rc = pa_layout - pb_layout;
  1314. else
  1315. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  1316. return rc;
  1317. }
  1318. /*
  1319. * validate and set source split:
  1320. * use pstates sorted by stage to check planes on same stage
  1321. * we assume that all pipes are in source split so its valid to compare
  1322. * without taking into account left/right mixer placement
  1323. */
  1324. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  1325. struct plane_state *pstates, int cnt)
  1326. {
  1327. struct plane_state *prv_pstate, *cur_pstate;
  1328. enum sde_layout prev_layout, cur_layout;
  1329. struct sde_rect left_rect, right_rect;
  1330. struct sde_kms *sde_kms;
  1331. int32_t left_pid, right_pid;
  1332. int32_t stage;
  1333. int i, rc = 0;
  1334. sde_kms = _sde_crtc_get_kms(crtc);
  1335. if (!sde_kms || !sde_kms->catalog) {
  1336. SDE_ERROR("invalid parameters\n");
  1337. return -EINVAL;
  1338. }
  1339. for (i = 1; i < cnt; i++) {
  1340. prv_pstate = &pstates[i - 1];
  1341. cur_pstate = &pstates[i];
  1342. prev_layout = prv_pstate->sde_pstate->layout;
  1343. cur_layout = cur_pstate->sde_pstate->layout;
  1344. if (prv_pstate->stage != cur_pstate->stage ||
  1345. prev_layout != cur_layout)
  1346. continue;
  1347. stage = cur_pstate->stage;
  1348. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1349. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1350. prv_pstate->drm_pstate->crtc_y,
  1351. prv_pstate->drm_pstate->crtc_w,
  1352. prv_pstate->drm_pstate->crtc_h, false);
  1353. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1354. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1355. cur_pstate->drm_pstate->crtc_y,
  1356. cur_pstate->drm_pstate->crtc_w,
  1357. cur_pstate->drm_pstate->crtc_h, false);
  1358. if (right_rect.x < left_rect.x) {
  1359. swap(left_pid, right_pid);
  1360. swap(left_rect, right_rect);
  1361. swap(prv_pstate, cur_pstate);
  1362. }
  1363. /*
  1364. * - planes are enumerated in pipe-priority order such that
  1365. * planes with lower drm_id must be left-most in a shared
  1366. * blend-stage when using source split.
  1367. * - planes in source split must be contiguous in width
  1368. * - planes in source split must have same dest yoff and height
  1369. */
  1370. if ((right_pid < left_pid) &&
  1371. !sde_kms->catalog->pipe_order_type) {
  1372. SDE_ERROR(
  1373. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1374. stage, left_pid, right_pid);
  1375. return -EINVAL;
  1376. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1377. SDE_ERROR(
  1378. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1379. stage, left_rect.x, left_rect.w,
  1380. right_rect.x, right_rect.w);
  1381. return -EINVAL;
  1382. } else if ((left_rect.y != right_rect.y) ||
  1383. (left_rect.h != right_rect.h)) {
  1384. SDE_ERROR(
  1385. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1386. stage, left_rect.y, left_rect.h,
  1387. right_rect.y, right_rect.h);
  1388. return -EINVAL;
  1389. }
  1390. }
  1391. return rc;
  1392. }
  1393. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1394. struct plane_state *pstates, int cnt)
  1395. {
  1396. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1397. enum sde_layout prev_layout, cur_layout;
  1398. struct sde_kms *sde_kms;
  1399. struct sde_rect left_rect, right_rect;
  1400. int32_t left_pid, right_pid;
  1401. int32_t stage;
  1402. int i;
  1403. sde_kms = _sde_crtc_get_kms(crtc);
  1404. if (!sde_kms || !sde_kms->catalog) {
  1405. SDE_ERROR("invalid parameters\n");
  1406. return;
  1407. }
  1408. if (!sde_kms->catalog->pipe_order_type)
  1409. return;
  1410. for (i = 0; i < cnt; i++) {
  1411. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1412. cur_pstate = &pstates[i];
  1413. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1414. prev_layout = prv_pstate ? prv_pstate->sde_pstate->layout :
  1415. SDE_LAYOUT_NONE;
  1416. cur_layout = cur_pstate->sde_pstate->layout;
  1417. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)
  1418. || (prev_layout != cur_layout)) {
  1419. /*
  1420. * reset if prv or nxt pipes are not in the same stage
  1421. * as the cur pipe
  1422. */
  1423. if ((!nxt_pstate)
  1424. || (nxt_pstate->stage != cur_pstate->stage)
  1425. || (nxt_pstate->sde_pstate->layout !=
  1426. cur_pstate->sde_pstate->layout))
  1427. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1428. continue;
  1429. }
  1430. stage = cur_pstate->stage;
  1431. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1432. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1433. prv_pstate->drm_pstate->crtc_y,
  1434. prv_pstate->drm_pstate->crtc_w,
  1435. prv_pstate->drm_pstate->crtc_h, false);
  1436. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1437. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1438. cur_pstate->drm_pstate->crtc_y,
  1439. cur_pstate->drm_pstate->crtc_w,
  1440. cur_pstate->drm_pstate->crtc_h, false);
  1441. if (right_rect.x < left_rect.x) {
  1442. swap(left_pid, right_pid);
  1443. swap(left_rect, right_rect);
  1444. swap(prv_pstate, cur_pstate);
  1445. }
  1446. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1447. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1448. }
  1449. for (i = 0; i < cnt; i++) {
  1450. cur_pstate = &pstates[i];
  1451. sde_plane_setup_src_split_order(
  1452. cur_pstate->drm_pstate->plane,
  1453. cur_pstate->sde_pstate->multirect_index,
  1454. cur_pstate->sde_pstate->pipe_order_flags);
  1455. }
  1456. }
  1457. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1458. int num_mixers, struct plane_state *pstates, int cnt)
  1459. {
  1460. int i, lm_idx;
  1461. struct sde_format *format;
  1462. bool blend_stage[SDE_STAGE_MAX] = { false };
  1463. u32 blend_type;
  1464. for (i = cnt - 1; i >= 0; i--) {
  1465. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1466. PLANE_PROP_BLEND_OP);
  1467. /* stage has already been programmed or BLEND_OP_SKIP type */
  1468. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1469. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1470. continue;
  1471. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1472. format = to_sde_format(msm_framebuffer_format(
  1473. pstates[i].sde_pstate->base.fb));
  1474. if (!format) {
  1475. SDE_ERROR("invalid format\n");
  1476. return;
  1477. }
  1478. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1479. pstates[i].sde_pstate, format);
  1480. blend_stage[pstates[i].sde_pstate->stage] = true;
  1481. }
  1482. }
  1483. }
  1484. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1485. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1486. struct sde_crtc_mixer *mixer)
  1487. {
  1488. struct drm_plane *plane;
  1489. struct drm_framebuffer *fb;
  1490. struct drm_plane_state *state;
  1491. struct sde_crtc_state *cstate;
  1492. struct sde_plane_state *pstate = NULL;
  1493. struct plane_state *pstates = NULL;
  1494. struct sde_format *format;
  1495. struct sde_hw_ctl *ctl;
  1496. struct sde_hw_mixer *lm;
  1497. struct sde_hw_stage_cfg *stage_cfg;
  1498. struct sde_rect plane_crtc_roi;
  1499. uint32_t stage_idx, lm_idx, layout_idx;
  1500. int zpos_cnt[MAX_LAYOUTS_PER_CRTC][SDE_STAGE_MAX + 1];
  1501. int i, mode, cnt = 0;
  1502. bool bg_alpha_enable = false;
  1503. u32 blend_type;
  1504. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  1505. DECLARE_BITMAP(fetch_active, SSPP_MAX);
  1506. if (!sde_crtc || !crtc->state || !mixer) {
  1507. SDE_ERROR("invalid sde_crtc or mixer\n");
  1508. return;
  1509. }
  1510. ctl = mixer->hw_ctl;
  1511. lm = mixer->hw_lm;
  1512. cstate = to_sde_crtc_state(crtc->state);
  1513. pstates = kcalloc(SDE_PSTATES_MAX,
  1514. sizeof(struct plane_state), GFP_KERNEL);
  1515. if (!pstates)
  1516. return;
  1517. memset(fetch_active, 0, sizeof(fetch_active));
  1518. memset(zpos_cnt, 0, sizeof(zpos_cnt));
  1519. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1520. state = plane->state;
  1521. if (!state)
  1522. continue;
  1523. plane_crtc_roi.x = state->crtc_x;
  1524. plane_crtc_roi.y = state->crtc_y;
  1525. plane_crtc_roi.w = state->crtc_w;
  1526. plane_crtc_roi.h = state->crtc_h;
  1527. pstate = to_sde_plane_state(state);
  1528. fb = state->fb;
  1529. mode = sde_plane_get_property(pstate,
  1530. PLANE_PROP_FB_TRANSLATION_MODE);
  1531. set_bit(sde_plane_pipe(plane), fetch_active);
  1532. sde_plane_ctl_flush(plane, ctl, true);
  1533. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1534. crtc->base.id,
  1535. pstate->stage,
  1536. plane->base.id,
  1537. sde_plane_pipe(plane) - SSPP_VIG0,
  1538. state->fb ? state->fb->base.id : -1);
  1539. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1540. if (!format) {
  1541. SDE_ERROR("invalid format\n");
  1542. goto end;
  1543. }
  1544. blend_type = sde_plane_get_property(pstate,
  1545. PLANE_PROP_BLEND_OP);
  1546. if (blend_type == SDE_DRM_BLEND_OP_SKIP) {
  1547. skip_blend_plane.valid_plane = true;
  1548. skip_blend_plane.plane = sde_plane_pipe(plane);
  1549. skip_blend_plane.height = plane_crtc_roi.h;
  1550. skip_blend_plane.width = plane_crtc_roi.w;
  1551. sde_cp_set_skip_blend_plane_info(crtc, &skip_blend_plane);
  1552. }
  1553. if (blend_type != SDE_DRM_BLEND_OP_SKIP) {
  1554. if (pstate->stage == SDE_STAGE_BASE &&
  1555. format->alpha_enable)
  1556. bg_alpha_enable = true;
  1557. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1558. state->fb ? state->fb->base.id : -1,
  1559. state->src_x >> 16, state->src_y >> 16,
  1560. state->src_w >> 16, state->src_h >> 16,
  1561. state->crtc_x, state->crtc_y,
  1562. state->crtc_w, state->crtc_h,
  1563. pstate->rotation, mode);
  1564. /*
  1565. * none or left layout will program to layer mixer
  1566. * group 0, right layout will program to layer mixer
  1567. * group 1.
  1568. */
  1569. if (pstate->layout <= SDE_LAYOUT_LEFT)
  1570. layout_idx = 0;
  1571. else
  1572. layout_idx = 1;
  1573. stage_cfg = &sde_crtc->stage_cfg[layout_idx];
  1574. stage_idx = zpos_cnt[layout_idx][pstate->stage]++;
  1575. stage_cfg->stage[pstate->stage][stage_idx] =
  1576. sde_plane_pipe(plane);
  1577. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1578. pstate->multirect_index;
  1579. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1580. sde_plane_pipe(plane) - SSPP_VIG0,
  1581. pstate->stage,
  1582. pstate->multirect_index,
  1583. pstate->multirect_mode,
  1584. format->base.pixel_format,
  1585. fb ? fb->modifier : 0,
  1586. layout_idx);
  1587. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1588. lm_idx++) {
  1589. if (bg_alpha_enable && !format->alpha_enable)
  1590. mixer[lm_idx].mixer_op_mode = 0;
  1591. else
  1592. mixer[lm_idx].mixer_op_mode |=
  1593. 1 << pstate->stage;
  1594. }
  1595. }
  1596. if (cnt >= SDE_PSTATES_MAX)
  1597. continue;
  1598. pstates[cnt].sde_pstate = pstate;
  1599. pstates[cnt].drm_pstate = state;
  1600. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1601. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1602. else
  1603. pstates[cnt].stage = sde_plane_get_property(
  1604. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1605. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1606. cnt++;
  1607. }
  1608. /* blend config update */
  1609. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1610. pstates, cnt);
  1611. if (ctl->ops.set_active_pipes)
  1612. ctl->ops.set_active_pipes(ctl, fetch_active);
  1613. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1614. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1615. if (lm && lm->ops.setup_dim_layer) {
  1616. cstate = to_sde_crtc_state(crtc->state);
  1617. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1618. for (i = 0; i < cstate->num_dim_layers; i++)
  1619. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1620. mixer, &cstate->dim_layer[i]);
  1621. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1622. }
  1623. }
  1624. end:
  1625. kfree(pstates);
  1626. }
  1627. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1628. struct drm_crtc *crtc)
  1629. {
  1630. struct sde_crtc *sde_crtc;
  1631. struct sde_crtc_state *cstate;
  1632. struct drm_encoder *drm_enc;
  1633. bool is_right_only;
  1634. bool encoder_in_dsc_merge = false;
  1635. if (!crtc || !crtc->state)
  1636. return;
  1637. sde_crtc = to_sde_crtc(crtc);
  1638. cstate = to_sde_crtc_state(crtc->state);
  1639. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS_ONLY)
  1640. return;
  1641. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1642. crtc->state->encoder_mask) {
  1643. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1644. encoder_in_dsc_merge = true;
  1645. break;
  1646. }
  1647. }
  1648. /**
  1649. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1650. * This is due to two reasons:
  1651. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1652. * the left DSC must be used, right DSC cannot be used alone.
  1653. * For right-only partial update, this means swap layer mixers to map
  1654. * Left LM to Right INTF. On later HW this was relaxed.
  1655. * - In DSC Merge mode, the physical encoder has already registered
  1656. * PP0 as the master, to switch to right-only we would have to
  1657. * reprogram to be driven by PP1 instead.
  1658. * To support both cases, we prefer to support the mixer swap solution.
  1659. */
  1660. if (!encoder_in_dsc_merge) {
  1661. if (sde_crtc->mixers_swapped) {
  1662. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1663. sde_crtc->mixers_swapped = false;
  1664. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  1665. }
  1666. return;
  1667. }
  1668. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1669. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1670. if (is_right_only && !sde_crtc->mixers_swapped) {
  1671. /* right-only update swap mixers */
  1672. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1673. sde_crtc->mixers_swapped = true;
  1674. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1675. /* left-only or full update, swap back */
  1676. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1677. sde_crtc->mixers_swapped = false;
  1678. }
  1679. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1680. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1681. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1682. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1683. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1684. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1685. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1686. }
  1687. /**
  1688. * _sde_crtc_blend_setup - configure crtc mixers
  1689. * @crtc: Pointer to drm crtc structure
  1690. * @old_state: Pointer to old crtc state
  1691. * @add_planes: Whether or not to add planes to mixers
  1692. */
  1693. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1694. struct drm_crtc_state *old_state, bool add_planes)
  1695. {
  1696. struct sde_crtc *sde_crtc;
  1697. struct sde_crtc_state *sde_crtc_state;
  1698. struct sde_crtc_mixer *mixer;
  1699. struct sde_hw_ctl *ctl;
  1700. struct sde_hw_mixer *lm;
  1701. struct sde_ctl_flush_cfg cfg = {0,};
  1702. int i;
  1703. if (!crtc)
  1704. return;
  1705. sde_crtc = to_sde_crtc(crtc);
  1706. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1707. mixer = sde_crtc->mixers;
  1708. SDE_DEBUG("%s\n", sde_crtc->name);
  1709. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1710. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1711. return;
  1712. }
  1713. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask)) {
  1714. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, sde_crtc_state->dirty);
  1715. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask);
  1716. }
  1717. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1718. if (!mixer[i].hw_lm) {
  1719. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1720. return;
  1721. }
  1722. mixer[i].mixer_op_mode = 0;
  1723. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1724. sde_crtc_state->dirty)) {
  1725. /* clear dim_layer settings */
  1726. lm = mixer[i].hw_lm;
  1727. if (lm->ops.clear_dim_layer)
  1728. lm->ops.clear_dim_layer(lm);
  1729. }
  1730. }
  1731. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1732. /* initialize stage cfg */
  1733. memset(&sde_crtc->stage_cfg, 0, sizeof(sde_crtc->stage_cfg));
  1734. if (add_planes)
  1735. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1736. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1737. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1738. int lm_layout = i / MAX_MIXERS_PER_LAYOUT;
  1739. ctl = mixer[i].hw_ctl;
  1740. lm = mixer[i].hw_lm;
  1741. if (sde_kms_rect_is_null(lm_roi))
  1742. sde_crtc->mixers[i].mixer_op_mode = 0;
  1743. if (lm->ops.setup_alpha_out)
  1744. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1745. /* stage config flush mask */
  1746. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1747. ctl->ops.get_pending_flush(ctl, &cfg);
  1748. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1749. mixer[i].hw_lm->idx - LM_0,
  1750. mixer[i].mixer_op_mode,
  1751. ctl->idx - CTL_0,
  1752. cfg.pending_flush_mask);
  1753. if (sde_kms_rect_is_null(lm_roi)) {
  1754. SDE_DEBUG(
  1755. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1756. sde_crtc->name, lm->idx - LM_0,
  1757. ctl->idx - CTL_0);
  1758. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1759. NULL, true);
  1760. } else {
  1761. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1762. &sde_crtc->stage_cfg[lm_layout],
  1763. false);
  1764. }
  1765. }
  1766. _sde_crtc_program_lm_output_roi(crtc);
  1767. }
  1768. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1769. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1770. {
  1771. struct drm_plane *plane;
  1772. struct sde_plane_state *sde_pstate;
  1773. uint32_t mode = 0;
  1774. int rc;
  1775. if (!crtc) {
  1776. SDE_ERROR("invalid state\n");
  1777. return -EINVAL;
  1778. }
  1779. *fb_ns = 0;
  1780. *fb_sec = 0;
  1781. *fb_sec_dir = 0;
  1782. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1783. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1784. rc = PTR_ERR(plane);
  1785. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1786. DRMID(crtc), DRMID(plane), rc);
  1787. return rc;
  1788. }
  1789. sde_pstate = to_sde_plane_state(plane->state);
  1790. mode = sde_plane_get_property(sde_pstate,
  1791. PLANE_PROP_FB_TRANSLATION_MODE);
  1792. switch (mode) {
  1793. case SDE_DRM_FB_NON_SEC:
  1794. (*fb_ns)++;
  1795. break;
  1796. case SDE_DRM_FB_SEC:
  1797. (*fb_sec)++;
  1798. break;
  1799. case SDE_DRM_FB_SEC_DIR_TRANS:
  1800. (*fb_sec_dir)++;
  1801. break;
  1802. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1803. break;
  1804. default:
  1805. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1806. DRMID(plane), mode);
  1807. return -EINVAL;
  1808. }
  1809. }
  1810. return 0;
  1811. }
  1812. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1813. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1814. {
  1815. struct drm_plane *plane;
  1816. const struct drm_plane_state *pstate;
  1817. struct sde_plane_state *sde_pstate;
  1818. uint32_t mode = 0;
  1819. int rc;
  1820. if (!state) {
  1821. SDE_ERROR("invalid state\n");
  1822. return -EINVAL;
  1823. }
  1824. *fb_ns = 0;
  1825. *fb_sec = 0;
  1826. *fb_sec_dir = 0;
  1827. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1828. if (IS_ERR_OR_NULL(pstate)) {
  1829. rc = PTR_ERR(pstate);
  1830. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1831. DRMID(state->crtc), DRMID(plane), rc);
  1832. return rc;
  1833. }
  1834. sde_pstate = to_sde_plane_state(pstate);
  1835. mode = sde_plane_get_property(sde_pstate,
  1836. PLANE_PROP_FB_TRANSLATION_MODE);
  1837. switch (mode) {
  1838. case SDE_DRM_FB_NON_SEC:
  1839. (*fb_ns)++;
  1840. break;
  1841. case SDE_DRM_FB_SEC:
  1842. (*fb_sec)++;
  1843. break;
  1844. case SDE_DRM_FB_SEC_DIR_TRANS:
  1845. (*fb_sec_dir)++;
  1846. break;
  1847. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1848. break;
  1849. default:
  1850. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1851. DRMID(plane), mode);
  1852. return -EINVAL;
  1853. }
  1854. }
  1855. return 0;
  1856. }
  1857. static void _sde_drm_fb_sec_dir_trans(
  1858. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1859. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1860. {
  1861. /* secure display usecase */
  1862. if ((smmu_state->state == ATTACHED) && (secure_level == SDE_DRM_SEC_ONLY)) {
  1863. smmu_state->state = (test_bit(SDE_FEATURE_SUI_NS_ALLOWED, catalog->features)) ?
  1864. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1865. smmu_state->secure_level = secure_level;
  1866. smmu_state->transition_type = PRE_COMMIT;
  1867. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1868. if (old_valid_fb)
  1869. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1870. if (test_bit(SDE_FEATURE_SUI_MISR, catalog->features))
  1871. smmu_state->sui_misr_state = SUI_MISR_ENABLE_REQ;
  1872. /* secure camera usecase */
  1873. } else if (smmu_state->state == ATTACHED) {
  1874. smmu_state->state = DETACH_SEC_REQ;
  1875. smmu_state->secure_level = secure_level;
  1876. smmu_state->transition_type = PRE_COMMIT;
  1877. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1878. }
  1879. }
  1880. static void _sde_drm_fb_transactions(
  1881. struct sde_kms_smmu_state_data *smmu_state,
  1882. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1883. int *ops)
  1884. {
  1885. if (((smmu_state->state == DETACHED)
  1886. || (smmu_state->state == DETACH_ALL_REQ))
  1887. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1888. && ((smmu_state->state == DETACHED_SEC)
  1889. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1890. smmu_state->state = (test_bit(SDE_FEATURE_SUI_NS_ALLOWED, catalog->features)) ?
  1891. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1892. smmu_state->transition_type = post_commit ?
  1893. POST_COMMIT : PRE_COMMIT;
  1894. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1895. if (old_valid_fb)
  1896. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1897. if (test_bit(SDE_FEATURE_SUI_MISR, catalog->features))
  1898. smmu_state->sui_misr_state = SUI_MISR_DISABLE_REQ;
  1899. } else if ((smmu_state->state == DETACHED_SEC)
  1900. || (smmu_state->state == DETACH_SEC_REQ)) {
  1901. smmu_state->state = ATTACH_SEC_REQ;
  1902. smmu_state->transition_type = post_commit ?
  1903. POST_COMMIT : PRE_COMMIT;
  1904. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1905. if (old_valid_fb)
  1906. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1907. }
  1908. }
  1909. /**
  1910. * sde_crtc_get_secure_transition_ops - determines the operations that
  1911. * need to be performed before transitioning to secure state
  1912. * This function should be called after swapping the new state
  1913. * @crtc: Pointer to drm crtc structure
  1914. * Returns the bitmask of operations need to be performed, -Error in
  1915. * case of error cases
  1916. */
  1917. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1918. struct drm_crtc_state *old_crtc_state,
  1919. bool old_valid_fb)
  1920. {
  1921. struct drm_plane *plane;
  1922. struct drm_encoder *encoder;
  1923. struct sde_crtc *sde_crtc;
  1924. struct sde_kms *sde_kms;
  1925. struct sde_mdss_cfg *catalog;
  1926. struct sde_kms_smmu_state_data *smmu_state;
  1927. uint32_t translation_mode = 0, secure_level;
  1928. int ops = 0;
  1929. bool post_commit = false;
  1930. if (!crtc || !crtc->state) {
  1931. SDE_ERROR("invalid crtc\n");
  1932. return -EINVAL;
  1933. }
  1934. sde_kms = _sde_crtc_get_kms(crtc);
  1935. if (!sde_kms)
  1936. return -EINVAL;
  1937. smmu_state = &sde_kms->smmu_state;
  1938. smmu_state->prev_state = smmu_state->state;
  1939. smmu_state->prev_secure_level = smmu_state->secure_level;
  1940. sde_crtc = to_sde_crtc(crtc);
  1941. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1942. catalog = sde_kms->catalog;
  1943. /*
  1944. * SMMU operations need to be delayed in case of video mode panels
  1945. * when switching back to non_secure mode
  1946. */
  1947. drm_for_each_encoder_mask(encoder, crtc->dev,
  1948. crtc->state->encoder_mask) {
  1949. if (sde_encoder_is_dsi_display(encoder))
  1950. post_commit |= sde_encoder_check_curr_mode(encoder,
  1951. MSM_DISPLAY_VIDEO_MODE);
  1952. }
  1953. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1954. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1955. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1956. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1957. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1958. if (!plane->state)
  1959. continue;
  1960. translation_mode = sde_plane_get_property(
  1961. to_sde_plane_state(plane->state),
  1962. PLANE_PROP_FB_TRANSLATION_MODE);
  1963. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1964. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1965. DRMID(crtc), translation_mode);
  1966. return -EINVAL;
  1967. }
  1968. /* we can break if we find sec_dir plane */
  1969. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1970. break;
  1971. }
  1972. mutex_lock(&sde_kms->secure_transition_lock);
  1973. switch (translation_mode) {
  1974. case SDE_DRM_FB_SEC_DIR_TRANS:
  1975. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1976. catalog, old_valid_fb, &ops);
  1977. break;
  1978. case SDE_DRM_FB_SEC:
  1979. case SDE_DRM_FB_NON_SEC:
  1980. _sde_drm_fb_transactions(smmu_state, catalog,
  1981. old_valid_fb, post_commit, &ops);
  1982. break;
  1983. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1984. ops = 0;
  1985. break;
  1986. default:
  1987. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1988. DRMID(crtc), translation_mode);
  1989. ops = -EINVAL;
  1990. }
  1991. /* log only during actual transition times */
  1992. if (ops) {
  1993. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1994. DRMID(crtc), smmu_state->state,
  1995. secure_level, smmu_state->secure_level,
  1996. smmu_state->transition_type, ops);
  1997. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1998. smmu_state->state, smmu_state->transition_type,
  1999. smmu_state->secure_level, old_valid_fb,
  2000. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  2001. }
  2002. mutex_unlock(&sde_kms->secure_transition_lock);
  2003. return ops;
  2004. }
  2005. /**
  2006. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  2007. * LUTs are configured only once during boot
  2008. * @sde_crtc: Pointer to sde crtc
  2009. * @cstate: Pointer to sde crtc state
  2010. */
  2011. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  2012. struct sde_crtc_state *cstate, uint32_t lut_idx)
  2013. {
  2014. struct sde_hw_scaler3_lut_cfg *cfg;
  2015. struct sde_kms *sde_kms;
  2016. u32 *lut_data = NULL;
  2017. size_t len = 0;
  2018. int ret = 0;
  2019. if (!sde_crtc || !cstate) {
  2020. SDE_ERROR("invalid args\n");
  2021. return -EINVAL;
  2022. }
  2023. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  2024. if (!sde_kms)
  2025. return -EINVAL;
  2026. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  2027. return 0;
  2028. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  2029. &cstate->property_state, &len, lut_idx);
  2030. if (!lut_data || !len) {
  2031. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  2032. lut_idx, lut_data, len);
  2033. lut_data = NULL;
  2034. len = 0;
  2035. }
  2036. cfg = &cstate->scl3_lut_cfg;
  2037. switch (lut_idx) {
  2038. case CRTC_PROP_DEST_SCALER_LUT_ED:
  2039. cfg->dir_lut = lut_data;
  2040. cfg->dir_len = len;
  2041. break;
  2042. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  2043. cfg->cir_lut = lut_data;
  2044. cfg->cir_len = len;
  2045. break;
  2046. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  2047. cfg->sep_lut = lut_data;
  2048. cfg->sep_len = len;
  2049. break;
  2050. default:
  2051. ret = -EINVAL;
  2052. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  2053. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  2054. break;
  2055. }
  2056. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  2057. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  2058. cfg->is_configured);
  2059. return ret;
  2060. }
  2061. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  2062. {
  2063. struct sde_crtc *sde_crtc;
  2064. if (!crtc) {
  2065. SDE_ERROR("invalid crtc\n");
  2066. return;
  2067. }
  2068. sde_crtc = to_sde_crtc(crtc);
  2069. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  2070. }
  2071. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  2072. {
  2073. int i;
  2074. /**
  2075. * Check if sufficient hw resources are
  2076. * available as per target caps & topology
  2077. */
  2078. if (!sde_crtc) {
  2079. SDE_ERROR("invalid argument\n");
  2080. return -EINVAL;
  2081. }
  2082. if (!sde_crtc->num_mixers ||
  2083. sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  2084. SDE_ERROR("%s: invalid number mixers: %d\n",
  2085. sde_crtc->name, sde_crtc->num_mixers);
  2086. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  2087. SDE_EVTLOG_ERROR);
  2088. return -EINVAL;
  2089. }
  2090. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2091. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  2092. || !sde_crtc->mixers[i].hw_ds) {
  2093. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  2094. sde_crtc->name, i);
  2095. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  2096. i, sde_crtc->mixers[i].hw_lm,
  2097. sde_crtc->mixers[i].hw_ctl,
  2098. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  2099. return -EINVAL;
  2100. }
  2101. }
  2102. return 0;
  2103. }
  2104. /**
  2105. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  2106. * @crtc: Pointer to drm crtc
  2107. */
  2108. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  2109. {
  2110. struct sde_crtc *sde_crtc;
  2111. struct sde_crtc_state *cstate;
  2112. struct sde_hw_mixer *hw_lm;
  2113. struct sde_hw_ctl *hw_ctl;
  2114. struct sde_hw_ds *hw_ds;
  2115. struct sde_hw_ds_cfg *cfg;
  2116. struct sde_kms *kms;
  2117. u32 op_mode = 0;
  2118. u32 lm_idx = 0, num_mixers = 0;
  2119. int i, count = 0;
  2120. if (!crtc)
  2121. return;
  2122. sde_crtc = to_sde_crtc(crtc);
  2123. cstate = to_sde_crtc_state(crtc->state);
  2124. kms = _sde_crtc_get_kms(crtc);
  2125. num_mixers = sde_crtc->num_mixers;
  2126. count = cstate->num_ds;
  2127. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2128. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  2129. cstate->num_ds_enabled);
  2130. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2131. SDE_DEBUG("no change in settings, skip commit\n");
  2132. } else if (!kms || !kms->catalog) {
  2133. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  2134. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  2135. SDE_DEBUG("dest scaler feature not supported\n");
  2136. } else if (_sde_validate_hw_resources(sde_crtc)) {
  2137. //do nothing
  2138. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  2139. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  2140. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  2141. } else {
  2142. for (i = 0; i < count; i++) {
  2143. cfg = &cstate->ds_cfg[i];
  2144. if (!cfg->flags)
  2145. continue;
  2146. lm_idx = cfg->idx;
  2147. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  2148. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  2149. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2150. /* Setup op mode - Dual/single */
  2151. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2152. op_mode |= BIT(hw_ds->idx - DS_0);
  2153. if (hw_ds->ops.setup_opmode) {
  2154. op_mode |= (cstate->num_ds_enabled ==
  2155. CRTC_DUAL_MIXERS_ONLY) ?
  2156. SDE_DS_OP_MODE_DUAL : 0;
  2157. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  2158. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  2159. }
  2160. /* Setup scaler */
  2161. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  2162. (cfg->flags &
  2163. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  2164. if (hw_ds->ops.setup_scaler)
  2165. hw_ds->ops.setup_scaler(hw_ds,
  2166. &cfg->scl3_cfg,
  2167. &cstate->scl3_lut_cfg);
  2168. }
  2169. /*
  2170. * Dest scaler shares the flush bit of the LM in control
  2171. */
  2172. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  2173. hw_ctl->ops.update_bitmask_mixer(
  2174. hw_ctl, hw_lm->idx, 1);
  2175. }
  2176. }
  2177. }
  2178. static void _sde_crtc_put_frame_data_buffer(struct sde_frame_data_buffer *buf)
  2179. {
  2180. if (!buf)
  2181. return;
  2182. msm_gem_put_buffer(buf->gem);
  2183. kfree(buf);
  2184. buf = NULL;
  2185. }
  2186. static int _sde_crtc_get_frame_data_buffer(struct drm_crtc *crtc, uint32_t fd)
  2187. {
  2188. struct sde_crtc *sde_crtc;
  2189. struct sde_frame_data_buffer *buf;
  2190. uint32_t cur_buf;
  2191. sde_crtc = to_sde_crtc(crtc);
  2192. cur_buf = sde_crtc->frame_data.cnt;
  2193. buf = kzalloc(sizeof(struct sde_frame_data_buffer), GFP_KERNEL);
  2194. if (!buf)
  2195. return -ENOMEM;
  2196. sde_crtc->frame_data.buf[cur_buf] = buf;
  2197. buf->fd = fd;
  2198. buf->fb = drm_framebuffer_lookup(crtc->dev, NULL, fd);
  2199. if (!buf->fb) {
  2200. SDE_ERROR("unable to get fb");
  2201. return -EINVAL;
  2202. }
  2203. buf->gem = msm_framebuffer_bo(buf->fb, 0);
  2204. if (!buf->gem) {
  2205. SDE_ERROR("unable to get drm gem");
  2206. return -EINVAL;
  2207. }
  2208. return msm_gem_get_buffer(buf->gem, crtc->dev, buf->fb,
  2209. sizeof(struct sde_drm_frame_data_packet));
  2210. }
  2211. static void _sde_crtc_set_frame_data_buffers(struct drm_crtc *crtc,
  2212. struct sde_crtc_state *cstate, void __user *usr)
  2213. {
  2214. struct sde_crtc *sde_crtc;
  2215. struct sde_drm_frame_data_buffers_ctrl ctrl;
  2216. int i, ret;
  2217. if (!crtc || !cstate || !usr)
  2218. return;
  2219. sde_crtc = to_sde_crtc(crtc);
  2220. ret = copy_from_user(&ctrl, usr, sizeof(ctrl));
  2221. if (ret) {
  2222. SDE_ERROR("failed to copy frame data ctrl, ret %d\n", ret);
  2223. return;
  2224. }
  2225. if (!ctrl.num_buffers) {
  2226. SDE_DEBUG("clearing frame data buffers");
  2227. goto exit;
  2228. } else if (ctrl.num_buffers > SDE_FRAME_DATA_BUFFER_MAX) {
  2229. SDE_ERROR("invalid number of buffers %d", ctrl.num_buffers);
  2230. return;
  2231. }
  2232. for (i = 0; i < ctrl.num_buffers; i++) {
  2233. if (_sde_crtc_get_frame_data_buffer(crtc, ctrl.fds[i])) {
  2234. SDE_ERROR("unable to set buffer for fd %d", ctrl.fds[i]);
  2235. goto exit;
  2236. }
  2237. sde_crtc->frame_data.cnt++;
  2238. }
  2239. return;
  2240. exit:
  2241. while (sde_crtc->frame_data.cnt--)
  2242. _sde_crtc_put_frame_data_buffer(
  2243. sde_crtc->frame_data.buf[sde_crtc->frame_data.cnt]);
  2244. sde_crtc->frame_data.cnt = 0;
  2245. }
  2246. static void _sde_crtc_frame_data_notify(struct drm_crtc *crtc,
  2247. struct sde_drm_frame_data_packet *frame_data_packet)
  2248. {
  2249. struct sde_crtc *sde_crtc;
  2250. struct sde_drm_frame_data_buf buf;
  2251. struct msm_gem_object *msm_gem;
  2252. u32 cur_buf;
  2253. sde_crtc = to_sde_crtc(crtc);
  2254. cur_buf = sde_crtc->frame_data.idx;
  2255. msm_gem = to_msm_bo(sde_crtc->frame_data.buf[cur_buf]->gem);
  2256. buf.fd = sde_crtc->frame_data.buf[cur_buf]->fd;
  2257. buf.offset = msm_gem->offset;
  2258. sde_crtc_event_notify(crtc, DRM_EVENT_FRAME_DATA, &buf,
  2259. sizeof(struct sde_drm_frame_data_buf));
  2260. sde_crtc->frame_data.idx = ++sde_crtc->frame_data.idx % sde_crtc->frame_data.cnt;
  2261. }
  2262. void sde_crtc_get_frame_data(struct drm_crtc *crtc)
  2263. {
  2264. struct sde_crtc *sde_crtc;
  2265. struct drm_plane *plane;
  2266. struct sde_drm_frame_data_packet frame_data_packet = {0, 0};
  2267. struct sde_drm_frame_data_packet *data;
  2268. struct sde_frame_data *frame_data;
  2269. int i = 0;
  2270. if (!crtc || !crtc->state)
  2271. return;
  2272. sde_crtc = to_sde_crtc(crtc);
  2273. frame_data = &sde_crtc->frame_data;
  2274. if (frame_data->cnt) {
  2275. struct msm_gem_object *msm_gem;
  2276. msm_gem = to_msm_bo(frame_data->buf[frame_data->idx]->gem);
  2277. data = (struct sde_drm_frame_data_packet *)
  2278. (((u8 *)msm_gem->vaddr) + msm_gem->offset);
  2279. } else {
  2280. data = &frame_data_packet;
  2281. }
  2282. data->commit_count = sde_crtc->play_count;
  2283. data->frame_count = sde_crtc->fps_info.frame_count;
  2284. /* Collect plane specific data */
  2285. drm_for_each_plane_mask(plane, crtc->dev, sde_crtc->plane_mask_old)
  2286. sde_plane_get_frame_data(plane, &data->plane_frame_data[i]);
  2287. if (frame_data->cnt)
  2288. _sde_crtc_frame_data_notify(crtc, data);
  2289. }
  2290. static void sde_crtc_frame_event_cb(void *data, u32 event, ktime_t ts)
  2291. {
  2292. struct drm_crtc *crtc = (struct drm_crtc *)data;
  2293. struct sde_crtc *sde_crtc;
  2294. struct msm_drm_private *priv;
  2295. struct sde_crtc_frame_event *fevent;
  2296. struct sde_kms_frame_event_cb_data *cb_data;
  2297. unsigned long flags;
  2298. u32 crtc_id;
  2299. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  2300. if (!data) {
  2301. SDE_ERROR("invalid parameters\n");
  2302. return;
  2303. }
  2304. crtc = cb_data->crtc;
  2305. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2306. SDE_ERROR("invalid parameters\n");
  2307. return;
  2308. }
  2309. sde_crtc = to_sde_crtc(crtc);
  2310. priv = crtc->dev->dev_private;
  2311. crtc_id = drm_crtc_index(crtc);
  2312. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2313. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  2314. spin_lock_irqsave(&sde_crtc->fevent_spin_lock, flags);
  2315. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  2316. struct sde_crtc_frame_event, list);
  2317. if (fevent)
  2318. list_del_init(&fevent->list);
  2319. spin_unlock_irqrestore(&sde_crtc->fevent_spin_lock, flags);
  2320. if (!fevent) {
  2321. SDE_ERROR("crtc%d event %d overflow\n",
  2322. crtc->base.id, event);
  2323. SDE_EVT32(DRMID(crtc), event);
  2324. return;
  2325. }
  2326. /* log and clear plane ubwc errors if any */
  2327. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2328. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2329. | SDE_ENCODER_FRAME_EVENT_DONE))
  2330. sde_crtc_get_frame_data(crtc);
  2331. if ((event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE) &&
  2332. (sde_crtc && sde_crtc->retire_frame_event_sf)) {
  2333. sde_crtc->retire_frame_event_time = ktime_get();
  2334. sysfs_notify_dirent(sde_crtc->retire_frame_event_sf);
  2335. }
  2336. fevent->event = event;
  2337. fevent->ts = ts;
  2338. fevent->crtc = crtc;
  2339. fevent->connector = cb_data->connector;
  2340. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  2341. }
  2342. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  2343. struct drm_crtc_state *old_state)
  2344. {
  2345. struct drm_device *dev;
  2346. struct sde_crtc *sde_crtc;
  2347. struct sde_crtc_state *cstate;
  2348. struct drm_connector *conn;
  2349. struct drm_encoder *encoder;
  2350. struct drm_connector_list_iter conn_iter;
  2351. if (!crtc || !crtc->state) {
  2352. SDE_ERROR("invalid crtc\n");
  2353. return;
  2354. }
  2355. dev = crtc->dev;
  2356. sde_crtc = to_sde_crtc(crtc);
  2357. cstate = to_sde_crtc_state(crtc->state);
  2358. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->cwb_enc_mask);
  2359. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  2360. /* identify connectors attached to this crtc */
  2361. cstate->num_connectors = 0;
  2362. drm_connector_list_iter_begin(dev, &conn_iter);
  2363. drm_for_each_connector_iter(conn, &conn_iter)
  2364. if (conn->state && conn->state->crtc == crtc &&
  2365. cstate->num_connectors < MAX_CONNECTORS) {
  2366. encoder = conn->state->best_encoder;
  2367. if (encoder)
  2368. sde_encoder_register_frame_event_callback(
  2369. encoder,
  2370. sde_crtc_frame_event_cb,
  2371. crtc);
  2372. cstate->connectors[cstate->num_connectors++] = conn;
  2373. sde_connector_prepare_fence(conn);
  2374. sde_encoder_set_clone_mode(encoder, crtc->state);
  2375. }
  2376. drm_connector_list_iter_end(&conn_iter);
  2377. /* prepare main output fence */
  2378. sde_fence_prepare(sde_crtc->output_fence);
  2379. SDE_ATRACE_END("sde_crtc_prepare_commit");
  2380. }
  2381. /**
  2382. * sde_crtc_complete_flip - signal pending page_flip events
  2383. * Any pending vblank events are added to the vblank_event_list
  2384. * so that the next vblank interrupt shall signal them.
  2385. * However PAGE_FLIP events are not handled through the vblank_event_list.
  2386. * This API signals any pending PAGE_FLIP events requested through
  2387. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  2388. * if file!=NULL, this is preclose potential cancel-flip path
  2389. * @crtc: Pointer to drm crtc structure
  2390. * @file: Pointer to drm file
  2391. */
  2392. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  2393. struct drm_file *file)
  2394. {
  2395. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2396. struct drm_device *dev = crtc->dev;
  2397. struct drm_pending_vblank_event *event;
  2398. unsigned long flags;
  2399. spin_lock_irqsave(&dev->event_lock, flags);
  2400. event = sde_crtc->event;
  2401. if (!event)
  2402. goto end;
  2403. /*
  2404. * if regular vblank case (!file) or if cancel-flip from
  2405. * preclose on file that requested flip, then send the
  2406. * event:
  2407. */
  2408. if (!file || (event->base.file_priv == file)) {
  2409. sde_crtc->event = NULL;
  2410. DRM_DEBUG_VBL("%s: send event: %pK\n",
  2411. sde_crtc->name, event);
  2412. SDE_EVT32_VERBOSE(DRMID(crtc));
  2413. drm_crtc_send_vblank_event(crtc, event);
  2414. }
  2415. end:
  2416. spin_unlock_irqrestore(&dev->event_lock, flags);
  2417. }
  2418. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  2419. struct drm_crtc_state *cstate)
  2420. {
  2421. struct drm_encoder *encoder;
  2422. if (!crtc || !crtc->dev || !cstate) {
  2423. SDE_ERROR("invalid crtc\n");
  2424. return INTF_MODE_NONE;
  2425. }
  2426. drm_for_each_encoder_mask(encoder, crtc->dev,
  2427. cstate->encoder_mask) {
  2428. /* continue if copy encoder is encountered */
  2429. if (sde_crtc_state_in_clone_mode(encoder, cstate))
  2430. continue;
  2431. return sde_encoder_get_intf_mode(encoder);
  2432. }
  2433. return INTF_MODE_NONE;
  2434. }
  2435. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  2436. {
  2437. struct drm_encoder *encoder;
  2438. if (!crtc || !crtc->dev) {
  2439. SDE_ERROR("invalid crtc\n");
  2440. return INTF_MODE_NONE;
  2441. }
  2442. drm_for_each_encoder(encoder, crtc->dev)
  2443. if ((encoder->crtc == crtc)
  2444. && !sde_encoder_in_cont_splash(encoder))
  2445. return sde_encoder_get_fps(encoder);
  2446. return 0;
  2447. }
  2448. u32 sde_crtc_get_dfps_maxfps(struct drm_crtc *crtc)
  2449. {
  2450. struct drm_encoder *encoder;
  2451. if (!crtc || !crtc->dev) {
  2452. SDE_ERROR("invalid crtc\n");
  2453. return 0;
  2454. }
  2455. drm_for_each_encoder_mask(encoder, crtc->dev,
  2456. crtc->state->encoder_mask) {
  2457. if (!sde_encoder_in_cont_splash(encoder))
  2458. return sde_encoder_get_dfps_maxfps(encoder);
  2459. }
  2460. return 0;
  2461. }
  2462. struct drm_encoder *sde_crtc_get_src_encoder_of_clone(struct drm_crtc *crtc)
  2463. {
  2464. struct drm_encoder *enc;
  2465. struct sde_crtc *sde_crtc;
  2466. if (!crtc || !crtc->dev)
  2467. return NULL;
  2468. sde_crtc = to_sde_crtc(crtc);
  2469. drm_for_each_encoder_mask(enc, crtc->dev, sde_crtc->cached_encoder_mask) {
  2470. if (sde_encoder_in_clone_mode(enc))
  2471. continue;
  2472. return enc;
  2473. }
  2474. return NULL;
  2475. }
  2476. static void sde_crtc_vblank_cb(void *data, ktime_t ts)
  2477. {
  2478. struct drm_crtc *crtc = (struct drm_crtc *)data;
  2479. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2480. /* keep statistics on vblank callback - with auto reset via debugfs */
  2481. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  2482. sde_crtc->vblank_cb_time = ts;
  2483. else
  2484. sde_crtc->vblank_cb_count++;
  2485. sde_crtc->vblank_last_cb_time = ts;
  2486. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  2487. drm_crtc_handle_vblank(crtc);
  2488. DRM_DEBUG_VBL("crtc%d, ts:%llu\n", crtc->base.id, ktime_to_us(ts));
  2489. SDE_EVT32_VERBOSE(DRMID(crtc), ktime_to_us(ts));
  2490. }
  2491. static void _sde_crtc_retire_event(struct drm_connector *connector,
  2492. ktime_t ts, enum sde_fence_event fence_event)
  2493. {
  2494. if (!connector) {
  2495. SDE_ERROR("invalid param\n");
  2496. return;
  2497. }
  2498. SDE_ATRACE_BEGIN("signal_retire_fence");
  2499. sde_connector_complete_commit(connector, ts, fence_event);
  2500. SDE_ATRACE_END("signal_retire_fence");
  2501. }
  2502. void sde_crtc_opr_event_notify(struct drm_crtc *crtc)
  2503. {
  2504. struct sde_crtc *sde_crtc;
  2505. uint32_t current_opr_value[MAX_DSI_DISPLAYS] = {0};
  2506. int i, rc;
  2507. bool updated = false;
  2508. struct drm_event event;
  2509. sde_crtc = to_sde_crtc(crtc);
  2510. atomic_set(&sde_crtc->previous_opr_value.num_valid_opr, 0);
  2511. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2512. rc = sde_dspp_spr_read_opr_value(sde_crtc->mixers[i].hw_dspp,
  2513. &current_opr_value[i]);
  2514. if (rc) {
  2515. SDE_ERROR("failed to collect OPR %d", i, rc);
  2516. continue;
  2517. }
  2518. atomic_inc(&sde_crtc->previous_opr_value.num_valid_opr);
  2519. if (current_opr_value[i] == sde_crtc->previous_opr_value.opr_value[i])
  2520. continue;
  2521. sde_crtc->previous_opr_value.opr_value[i] = current_opr_value[i];
  2522. updated = true;
  2523. }
  2524. if (updated) {
  2525. event.type = DRM_EVENT_OPR_VALUE;
  2526. event.length = sizeof(sde_crtc->previous_opr_value);
  2527. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  2528. (u8 *)&sde_crtc->previous_opr_value);
  2529. }
  2530. }
  2531. static void _sde_crtc_frame_done_notify(struct drm_crtc *crtc,
  2532. struct sde_crtc_frame_event *fevent)
  2533. {
  2534. struct sde_crtc *sde_crtc;
  2535. struct sde_connector *sde_conn;
  2536. sde_crtc = to_sde_crtc(crtc);
  2537. if (sde_crtc->opr_event_notify_enabled)
  2538. sde_crtc_opr_event_notify(crtc);
  2539. sde_conn = to_sde_connector(fevent->connector);
  2540. if (sde_conn && sde_conn->misr_event_notify_enabled)
  2541. sde_encoder_misr_sign_event_notify(fevent->connector->encoder);
  2542. }
  2543. static void sde_crtc_frame_event_work(struct kthread_work *work)
  2544. {
  2545. struct msm_drm_private *priv;
  2546. struct sde_crtc_frame_event *fevent;
  2547. struct drm_crtc *crtc;
  2548. struct sde_crtc *sde_crtc;
  2549. struct sde_kms *sde_kms;
  2550. unsigned long flags;
  2551. bool in_clone_mode = false;
  2552. if (!work) {
  2553. SDE_ERROR("invalid work handle\n");
  2554. return;
  2555. }
  2556. fevent = container_of(work, struct sde_crtc_frame_event, work);
  2557. if (!fevent->crtc || !fevent->crtc->state) {
  2558. SDE_ERROR("invalid crtc\n");
  2559. return;
  2560. }
  2561. crtc = fevent->crtc;
  2562. sde_crtc = to_sde_crtc(crtc);
  2563. sde_kms = _sde_crtc_get_kms(crtc);
  2564. if (!sde_kms) {
  2565. SDE_ERROR("invalid kms handle\n");
  2566. return;
  2567. }
  2568. priv = sde_kms->dev->dev_private;
  2569. SDE_ATRACE_BEGIN("crtc_frame_event");
  2570. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2571. ktime_to_ns(fevent->ts));
  2572. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2573. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2574. true : false;
  2575. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2576. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2577. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2578. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2579. /* this should not happen */
  2580. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2581. crtc->base.id,
  2582. ktime_to_ns(fevent->ts),
  2583. atomic_read(&sde_crtc->frame_pending));
  2584. SDE_EVT32(DRMID(crtc), fevent->event,
  2585. SDE_EVTLOG_FUNC_CASE1);
  2586. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2587. /* release bandwidth and other resources */
  2588. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2589. crtc->base.id,
  2590. ktime_to_ns(fevent->ts));
  2591. SDE_EVT32(DRMID(crtc), fevent->event,
  2592. SDE_EVTLOG_FUNC_CASE2);
  2593. sde_core_perf_crtc_release_bw(crtc);
  2594. } else {
  2595. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2596. SDE_EVTLOG_FUNC_CASE3);
  2597. }
  2598. }
  2599. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2600. SDE_ATRACE_BEGIN("signal_release_fence");
  2601. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2602. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2603. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL, NULL);
  2604. _sde_crtc_frame_done_notify(crtc, fevent);
  2605. SDE_ATRACE_END("signal_release_fence");
  2606. }
  2607. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2608. /* this api should be called without spin_lock */
  2609. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2610. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2611. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2612. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2613. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2614. crtc->base.id, ktime_to_ns(fevent->ts));
  2615. spin_lock_irqsave(&sde_crtc->fevent_spin_lock, flags);
  2616. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2617. spin_unlock_irqrestore(&sde_crtc->fevent_spin_lock, flags);
  2618. SDE_ATRACE_END("crtc_frame_event");
  2619. }
  2620. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2621. struct drm_crtc_state *old_state)
  2622. {
  2623. struct sde_crtc *sde_crtc;
  2624. struct sde_splash_display *splash_display = NULL;
  2625. struct sde_kms *sde_kms;
  2626. bool cont_splash_enabled = false;
  2627. int i;
  2628. u32 power_on = 1;
  2629. if (!crtc || !crtc->state) {
  2630. SDE_ERROR("invalid crtc\n");
  2631. return;
  2632. }
  2633. sde_crtc = to_sde_crtc(crtc);
  2634. SDE_EVT32_VERBOSE(DRMID(crtc));
  2635. sde_kms = _sde_crtc_get_kms(crtc);
  2636. if (!sde_kms)
  2637. return;
  2638. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2639. splash_display = &sde_kms->splash_data.splash_display[i];
  2640. if (splash_display->cont_splash_enabled &&
  2641. crtc == splash_display->encoder->crtc)
  2642. cont_splash_enabled = true;
  2643. }
  2644. if ((crtc->state->active_changed || cont_splash_enabled) && crtc->state->active)
  2645. sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, &power_on, sizeof(u32));
  2646. sde_core_perf_crtc_update(crtc, 0, false);
  2647. }
  2648. /**
  2649. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2650. * @cstate: Pointer to sde crtc state
  2651. */
  2652. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2653. {
  2654. if (!cstate) {
  2655. SDE_ERROR("invalid cstate\n");
  2656. return;
  2657. }
  2658. cstate->input_fence_timeout_ns =
  2659. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2660. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2661. }
  2662. void _sde_crtc_clear_dim_layers_v1(struct drm_crtc_state *state)
  2663. {
  2664. u32 i;
  2665. struct sde_crtc_state *cstate;
  2666. if (!state)
  2667. return;
  2668. cstate = to_sde_crtc_state(state);
  2669. for (i = 0; i < cstate->num_dim_layers; i++)
  2670. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2671. cstate->num_dim_layers = 0;
  2672. }
  2673. /**
  2674. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2675. * @cstate: Pointer to sde crtc state
  2676. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2677. */
  2678. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2679. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2680. {
  2681. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2682. struct sde_drm_dim_layer_cfg *user_cfg;
  2683. struct sde_hw_dim_layer *dim_layer;
  2684. u32 count, i;
  2685. struct sde_kms *kms;
  2686. if (!crtc || !cstate) {
  2687. SDE_ERROR("invalid crtc or cstate\n");
  2688. return;
  2689. }
  2690. dim_layer = cstate->dim_layer;
  2691. if (!usr_ptr) {
  2692. /* usr_ptr is null when setting the default property value */
  2693. _sde_crtc_clear_dim_layers_v1(&cstate->base);
  2694. SDE_DEBUG("dim_layer data removed\n");
  2695. goto clear;
  2696. }
  2697. kms = _sde_crtc_get_kms(crtc);
  2698. if (!kms || !kms->catalog) {
  2699. SDE_ERROR("invalid kms\n");
  2700. return;
  2701. }
  2702. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2703. SDE_ERROR("failed to copy dim_layer data\n");
  2704. return;
  2705. }
  2706. count = dim_layer_v1.num_layers;
  2707. if (count > SDE_MAX_DIM_LAYERS) {
  2708. SDE_ERROR("invalid number of dim_layers:%d", count);
  2709. return;
  2710. }
  2711. /* populate from user space */
  2712. cstate->num_dim_layers = count;
  2713. for (i = 0; i < count; i++) {
  2714. user_cfg = &dim_layer_v1.layer_cfg[i];
  2715. dim_layer[i].flags = user_cfg->flags;
  2716. dim_layer[i].stage = test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features) ?
  2717. user_cfg->stage : user_cfg->stage + SDE_STAGE_0;
  2718. dim_layer[i].rect.x = user_cfg->rect.x1;
  2719. dim_layer[i].rect.y = user_cfg->rect.y1;
  2720. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2721. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2722. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2723. user_cfg->color_fill.color_0,
  2724. user_cfg->color_fill.color_1,
  2725. user_cfg->color_fill.color_2,
  2726. user_cfg->color_fill.color_3,
  2727. };
  2728. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2729. i, dim_layer[i].flags, dim_layer[i].stage);
  2730. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2731. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2732. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2733. dim_layer[i].color_fill.color_0,
  2734. dim_layer[i].color_fill.color_1,
  2735. dim_layer[i].color_fill.color_2,
  2736. dim_layer[i].color_fill.color_3);
  2737. }
  2738. clear:
  2739. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2740. }
  2741. /**
  2742. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2743. * @sde_crtc : Pointer to sde crtc
  2744. * @cstate : Pointer to sde crtc state
  2745. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2746. */
  2747. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2748. struct sde_crtc_state *cstate,
  2749. void __user *usr_ptr)
  2750. {
  2751. struct sde_drm_dest_scaler_data ds_data;
  2752. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2753. struct sde_drm_scaler_v2 scaler_v2;
  2754. void __user *scaler_v2_usr;
  2755. int i, count;
  2756. if (!sde_crtc || !cstate) {
  2757. SDE_ERROR("invalid sde_crtc/state\n");
  2758. return -EINVAL;
  2759. }
  2760. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2761. if (!usr_ptr) {
  2762. SDE_DEBUG("ds data removed\n");
  2763. return 0;
  2764. }
  2765. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2766. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2767. sde_crtc->name);
  2768. return -EINVAL;
  2769. }
  2770. count = ds_data.num_dest_scaler;
  2771. if (!count) {
  2772. SDE_DEBUG("no ds data available\n");
  2773. return 0;
  2774. }
  2775. if (count > SDE_MAX_DS_COUNT) {
  2776. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2777. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2778. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2779. return -EINVAL;
  2780. }
  2781. /* Populate from user space */
  2782. for (i = 0; i < count; i++) {
  2783. ds_cfg_usr = &ds_data.ds_cfg[i];
  2784. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2785. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2786. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2787. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2788. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2789. if (ds_cfg_usr->scaler_cfg) {
  2790. scaler_v2_usr =
  2791. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2792. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2793. sizeof(scaler_v2))) {
  2794. SDE_ERROR("%s:scaler: copy from user failed\n",
  2795. sde_crtc->name);
  2796. return -EINVAL;
  2797. }
  2798. }
  2799. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2800. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2801. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2802. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2803. scaler_v2.dst_width, scaler_v2.dst_height);
  2804. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2805. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2806. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2807. scaler_v2.dst_width, scaler_v2.dst_height);
  2808. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2809. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2810. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2811. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2812. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2813. ds_cfg_usr->lm_height);
  2814. }
  2815. cstate->num_ds = count;
  2816. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2817. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2818. return 0;
  2819. }
  2820. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2821. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2822. struct sde_hw_ds_cfg *prev_cfg)
  2823. {
  2824. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2825. || !cfg->lm_width || !cfg->lm_height) {
  2826. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2827. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2828. hdisplay, mode->vdisplay);
  2829. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2830. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2831. return -E2BIG;
  2832. }
  2833. if (prev_cfg && (cfg->lm_width != prev_cfg->lm_width ||
  2834. cfg->lm_height != prev_cfg->lm_height)) {
  2835. SDE_ERROR("crtc%d: uneven lm split [%d,%d], [%d %d]\n",
  2836. crtc->base.id, cfg->lm_width,
  2837. cfg->lm_height, prev_cfg->lm_width,
  2838. prev_cfg->lm_height);
  2839. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2840. prev_cfg->lm_width, prev_cfg->lm_height,
  2841. SDE_EVTLOG_ERROR);
  2842. return -EINVAL;
  2843. }
  2844. return 0;
  2845. }
  2846. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2847. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2848. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2849. u32 max_in_width, u32 max_out_width)
  2850. {
  2851. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2852. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2853. /**
  2854. * Scaler src and dst width shouldn't exceed the maximum
  2855. * width limitation. Also, if there is no partial update
  2856. * dst width and height must match display resolution.
  2857. */
  2858. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2859. cfg->scl3_cfg.dst_width > max_out_width ||
  2860. !cfg->scl3_cfg.src_width[0] ||
  2861. !cfg->scl3_cfg.dst_width ||
  2862. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2863. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2864. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2865. SDE_ERROR("crtc%d: ", crtc->base.id);
  2866. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2867. cfg->scl3_cfg.src_width[0],
  2868. cfg->scl3_cfg.dst_width,
  2869. cfg->scl3_cfg.dst_height,
  2870. hdisplay, mode->vdisplay);
  2871. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2872. sde_crtc->num_mixers, cfg->flags,
  2873. hw_ds->idx - DS_0);
  2874. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2875. cfg->scl3_cfg.enable,
  2876. cfg->scl3_cfg.de.enable);
  2877. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2878. cfg->scl3_cfg.de.enable, cfg->flags,
  2879. max_in_width, max_out_width,
  2880. cfg->scl3_cfg.src_width[0],
  2881. cfg->scl3_cfg.dst_width,
  2882. cfg->scl3_cfg.dst_height, hdisplay,
  2883. mode->vdisplay, sde_crtc->num_mixers,
  2884. SDE_EVTLOG_ERROR);
  2885. cfg->flags &=
  2886. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2887. cfg->flags &=
  2888. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2889. return -EINVAL;
  2890. }
  2891. }
  2892. return 0;
  2893. }
  2894. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2895. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2896. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2897. u32 hdisplay, u32 *num_ds_enable, u32 max_in_width, u32 max_out_width)
  2898. {
  2899. int i, ret;
  2900. u32 lm_idx;
  2901. struct sde_hw_ds_cfg *cfg, *prev_cfg;
  2902. for (i = 0; i < cstate->num_ds; i++) {
  2903. cfg = &cstate->ds_cfg[i];
  2904. prev_cfg = (i > 0) ? &cstate->ds_cfg[i - 1] : NULL;
  2905. lm_idx = cfg->idx;
  2906. /**
  2907. * Validate against topology
  2908. * No of dest scalers should match the num of mixers
  2909. * unless it is partial update left only/right only use case
  2910. */
  2911. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2912. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2913. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2914. crtc->base.id, i, lm_idx, cfg->flags);
  2915. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2916. SDE_EVTLOG_ERROR);
  2917. return -EINVAL;
  2918. }
  2919. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2920. if (!max_in_width && !max_out_width) {
  2921. max_in_width = hw_ds->scl->top->maxinputwidth;
  2922. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2923. if (cstate->num_ds == CRTC_DUAL_MIXERS_ONLY)
  2924. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2925. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2926. max_in_width, max_out_width, cstate->num_ds);
  2927. }
  2928. /* Check LM width and height */
  2929. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2930. prev_cfg);
  2931. if (ret)
  2932. return ret;
  2933. /* Check scaler data */
  2934. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2935. hw_ds, cfg, hdisplay,
  2936. max_in_width, max_out_width);
  2937. if (ret)
  2938. return ret;
  2939. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2940. (*num_ds_enable)++;
  2941. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2942. hw_ds->idx - DS_0, cfg->flags);
  2943. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2944. }
  2945. return 0;
  2946. }
  2947. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2948. struct sde_crtc_state *cstate, u32 num_ds_enable)
  2949. {
  2950. struct sde_hw_ds_cfg *cfg;
  2951. int i;
  2952. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2953. cstate->num_ds_enabled, num_ds_enable);
  2954. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2955. cstate->num_ds, cstate->dirty[0]);
  2956. if (cstate->num_ds_enabled != num_ds_enable) {
  2957. /* Disabling destination scaler */
  2958. if (!num_ds_enable) {
  2959. for (i = 0; i < cstate->num_ds; i++) {
  2960. cfg = &cstate->ds_cfg[i];
  2961. cfg->idx = i;
  2962. /* Update scaler settings in disable case */
  2963. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2964. cfg->scl3_cfg.enable = 0;
  2965. cfg->scl3_cfg.de.enable = 0;
  2966. }
  2967. }
  2968. cstate->num_ds_enabled = num_ds_enable;
  2969. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2970. } else {
  2971. if (!cstate->num_ds_enabled)
  2972. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2973. }
  2974. }
  2975. /**
  2976. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2977. * @crtc : Pointer to drm crtc
  2978. * @state : Pointer to drm crtc state
  2979. */
  2980. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2981. struct drm_crtc_state *state)
  2982. {
  2983. struct sde_crtc *sde_crtc;
  2984. struct sde_crtc_state *cstate;
  2985. struct drm_display_mode *mode;
  2986. struct sde_kms *kms;
  2987. struct sde_hw_ds *hw_ds = NULL;
  2988. u32 ret = 0;
  2989. u32 num_ds_enable = 0, hdisplay = 0;
  2990. u32 max_in_width = 0, max_out_width = 0;
  2991. if (!crtc || !state)
  2992. return -EINVAL;
  2993. sde_crtc = to_sde_crtc(crtc);
  2994. cstate = to_sde_crtc_state(state);
  2995. kms = _sde_crtc_get_kms(crtc);
  2996. mode = &state->adjusted_mode;
  2997. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2998. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2999. SDE_DEBUG("dest scaler property not set, skip validation\n");
  3000. return 0;
  3001. }
  3002. if (!kms || !kms->catalog) {
  3003. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  3004. return -EINVAL;
  3005. }
  3006. if (!kms->catalog->mdp[0].has_dest_scaler) {
  3007. SDE_DEBUG("dest scaler feature not supported\n");
  3008. return 0;
  3009. }
  3010. if (!sde_crtc->num_mixers) {
  3011. SDE_DEBUG("mixers not allocated\n");
  3012. return 0;
  3013. }
  3014. ret = _sde_validate_hw_resources(sde_crtc);
  3015. if (ret)
  3016. goto err;
  3017. /**
  3018. * No of dest scalers shouldn't exceed hw ds block count and
  3019. * also, match the num of mixers unless it is partial update
  3020. * left only/right only use case - currently PU + DS is not supported
  3021. */
  3022. if (cstate->num_ds > kms->catalog->ds_count ||
  3023. ((cstate->num_ds != sde_crtc->num_mixers) &&
  3024. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  3025. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  3026. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  3027. cstate->ds_cfg[0].flags);
  3028. ret = -EINVAL;
  3029. goto err;
  3030. }
  3031. /**
  3032. * Check if DS needs to be enabled or disabled
  3033. * In case of enable, validate the data
  3034. */
  3035. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  3036. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  3037. cstate->num_ds, cstate->ds_cfg[0].flags);
  3038. goto disable;
  3039. }
  3040. /* Display resolution */
  3041. hdisplay = mode->hdisplay / sde_crtc->num_mixers;
  3042. /* Validate the DS data */
  3043. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  3044. mode, hw_ds, hdisplay, &num_ds_enable,
  3045. max_in_width, max_out_width);
  3046. if (ret)
  3047. goto err;
  3048. disable:
  3049. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, num_ds_enable);
  3050. return 0;
  3051. err:
  3052. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3053. return ret;
  3054. }
  3055. static struct sde_hw_ctl *_sde_crtc_get_hw_ctl(struct drm_crtc *drm_crtc)
  3056. {
  3057. struct sde_crtc *sde_crtc = to_sde_crtc(drm_crtc);
  3058. if (!sde_crtc || !sde_crtc->mixers[0].hw_ctl) {
  3059. DRM_ERROR("invalid crtc params %d\n", !sde_crtc);
  3060. return NULL;
  3061. }
  3062. /* it will always return the first mixer and single CTL */
  3063. return sde_crtc->mixers[0].hw_ctl;
  3064. }
  3065. static struct dma_fence *_sde_plane_get_input_hw_fence(struct drm_plane *plane)
  3066. {
  3067. struct dma_fence *fence;
  3068. struct sde_plane *psde;
  3069. struct sde_plane_state *pstate;
  3070. void *input_fence;
  3071. struct dma_fence *input_hw_fence = NULL;
  3072. if (!plane || !plane->state) {
  3073. SDE_ERROR("invalid input %d\n", !plane);
  3074. return NULL;
  3075. }
  3076. psde = to_sde_plane(plane);
  3077. pstate = to_sde_plane_state(plane->state);
  3078. input_fence = pstate->input_fence;
  3079. if (input_fence) {
  3080. fence = (struct dma_fence *)pstate->input_fence;
  3081. if (fence->flags & BIT(MSM_HW_FENCE_FLAG_ENABLED_BIT)) {
  3082. input_hw_fence = fence;
  3083. SDE_DEBUG("input hwfence ctx:%llu seqno:%llu f:0x%lx timeline:%s\n",
  3084. fence->context, fence->seqno, fence->flags,
  3085. fence->ops->get_timeline_name(fence));
  3086. }
  3087. SDE_EVT32_VERBOSE(DRMID(plane), fence->flags);
  3088. }
  3089. return input_hw_fence;
  3090. }
  3091. /**
  3092. * _sde_crtc_fences_wait_list - wait for input sw-fences and return any hw-fences
  3093. * @crtc: Pointer to CRTC object.
  3094. * @use_hw_fences: Boolean to indicate if function should use hw-fences and skip hw-fences sw-wait.
  3095. * @dma_hw_fences: List of available hw-fences, this is populated by this function.
  3096. * @max_hw_fences: Max number of hw-fences that can be added to the dma_hw_fences list
  3097. *
  3098. * This function iterates through all crtc planes, if 'use_hw_fences' is set, for each fence:
  3099. * - If the fence is a hw-fence, it will get its dma-fence object and add it to the 'dma_hw_fences'
  3100. * list, skipping any sw-wait, since wait will happen in hw.
  3101. * - If the fence is not a hw-fence, it will wait for the sw-fence to be signaled before proceed.
  3102. * If 'use_hw_fences' is not set, function will wait on the sw-fences for all fences
  3103. * regardless if they support or not hw-fence.
  3104. * Return value is the number of hw-fences added to the 'dma_hw_fences' list.
  3105. */
  3106. static int _sde_crtc_fences_wait_list(struct drm_crtc *crtc, bool use_hw_fences,
  3107. struct dma_fence **dma_hw_fences, int max_hw_fences)
  3108. {
  3109. struct drm_plane *plane = NULL;
  3110. u32 num_hw_fences = 0;
  3111. ktime_t kt_end, kt_wait;
  3112. uint32_t wait_ms = 1;
  3113. int i, rc = 0;
  3114. /* use monotonic timer to limit total fence wait time */
  3115. kt_end = ktime_add_ns(ktime_get(),
  3116. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  3117. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3118. /* check if input-fences are hw fences and if they are, add them to the list */
  3119. if (use_hw_fences) {
  3120. dma_hw_fences[num_hw_fences] = _sde_plane_get_input_hw_fence(plane);
  3121. if (dma_hw_fences[num_hw_fences] && (num_hw_fences < max_hw_fences)) {
  3122. bool repeated_fence = false;
  3123. /* check if this fence already in the hw-fences list */
  3124. for (i = num_hw_fences - 1; i >= 0; i--) {
  3125. if (dma_hw_fences[i] == dma_hw_fences[num_hw_fences]) {
  3126. repeated_fence = true;
  3127. break;
  3128. }
  3129. }
  3130. if (repeated_fence)
  3131. dma_hw_fences[num_hw_fences] = NULL; /* cleanup from list */
  3132. else
  3133. num_hw_fences++; /* keep fence in the list */
  3134. /* go to next, to skip sw-wait */
  3135. continue;
  3136. }
  3137. }
  3138. /*
  3139. * This was not a hw-fence, therefore, wait for this sw-fence to be signaled
  3140. * before proceed.
  3141. *
  3142. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  3143. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  3144. * that each plane can check its fence status and react appropriately
  3145. * if its fence has timed out. Call input fence wait multiple times if
  3146. * fence wait is interrupted due to interrupt call.
  3147. */
  3148. do {
  3149. kt_wait = ktime_sub(kt_end, ktime_get());
  3150. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  3151. wait_ms = ktime_to_ms(kt_wait);
  3152. else
  3153. wait_ms = 0;
  3154. rc = sde_plane_wait_input_fence(plane, wait_ms);
  3155. } while (wait_ms && rc == -ERESTARTSYS);
  3156. }
  3157. return num_hw_fences;
  3158. }
  3159. static inline bool _is_vid_power_on_frame(struct drm_crtc *crtc)
  3160. {
  3161. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3162. bool is_vid_mode = sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  3163. MSM_DISPLAY_VIDEO_MODE);
  3164. return is_vid_mode && crtc->state->active_changed && crtc->state->active;
  3165. }
  3166. /**
  3167. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences or register hw-fences
  3168. * @crtc: Pointer to CRTC object
  3169. *
  3170. * Returns true if hw fences are used, otherwise returns false
  3171. */
  3172. static bool _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  3173. {
  3174. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3175. bool ipcc_input_signal_wait = false;
  3176. struct dma_fence *dma_hw_fences[MAX_HW_FENCES] = {0};
  3177. int num_hw_fences = 0;
  3178. struct sde_hw_ctl *hw_ctl;
  3179. bool input_hw_fences_enable;
  3180. int ret;
  3181. SDE_DEBUG("\n");
  3182. if (!crtc || !crtc->state) {
  3183. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  3184. return false;
  3185. }
  3186. hw_ctl = _sde_crtc_get_hw_ctl(crtc);
  3187. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  3188. /* update ctl hw to wait for ipcc input signal before fetch */
  3189. if (test_bit(HW_FENCE_IN_FENCES_ENABLE, sde_crtc->hwfence_features_mask) &&
  3190. !sde_fence_update_input_hw_fence_signal(hw_ctl))
  3191. ipcc_input_signal_wait = true;
  3192. /* avoid hw-fences in first frame after timing engine enable */
  3193. input_hw_fences_enable = (ipcc_input_signal_wait && !_is_vid_power_on_frame(crtc));
  3194. /* wait for sw fences and get hw fences list (if any) */
  3195. num_hw_fences = _sde_crtc_fences_wait_list(crtc, input_hw_fences_enable, &dma_hw_fences[0],
  3196. MAX_HW_FENCES);
  3197. /* register the hw-fences for hw-wait */
  3198. if (num_hw_fences) {
  3199. ret = sde_fence_register_hw_fences_wait(hw_ctl, dma_hw_fences, num_hw_fences);
  3200. if (ret) {
  3201. SDE_ERROR("failed to register for hw-fence wait, will wait in sw\n");
  3202. SDE_EVT32(SDE_EVTLOG_ERROR, num_hw_fences,
  3203. hw_ctl ? hw_ctl->idx - CTL_0 : -1);
  3204. /* we failed to register hw-fences, wait for all fences as 'sw-fences' */
  3205. num_hw_fences = _sde_crtc_fences_wait_list(crtc, false, &dma_hw_fences[0],
  3206. MAX_HW_FENCES);
  3207. }
  3208. }
  3209. SDE_DEBUG("hfence_enable:%d no_override:%d ctl:%d wait_ipcc:%d num_hfences:%d\n",
  3210. input_hw_fences_enable,
  3211. test_bit(HW_FENCE_IN_FENCES_NO_OVERRIDE, sde_crtc->hwfence_features_mask),
  3212. hw_ctl ? hw_ctl->idx - CTL_0 : -1, ipcc_input_signal_wait, num_hw_fences);
  3213. SDE_EVT32(input_hw_fences_enable,
  3214. test_bit(HW_FENCE_IN_FENCES_NO_OVERRIDE, sde_crtc->hwfence_features_mask),
  3215. ipcc_input_signal_wait, num_hw_fences, hw_ctl ? hw_ctl->idx - CTL_0 : -1);
  3216. /* if hw is waiting for ipcc signal and no hw-fences, override signal */
  3217. if (ipcc_input_signal_wait && !num_hw_fences && hw_ctl->ops.hw_fence_trigger_sw_override &&
  3218. !test_bit(HW_FENCE_IN_FENCES_NO_OVERRIDE, sde_crtc->hwfence_features_mask))
  3219. hw_ctl->ops.hw_fence_trigger_sw_override(hw_ctl);
  3220. SDE_ATRACE_END("plane_wait_input_fence");
  3221. return num_hw_fences ? true : false;
  3222. }
  3223. static void _sde_crtc_setup_mixer_for_encoder(
  3224. struct drm_crtc *crtc,
  3225. struct drm_encoder *enc)
  3226. {
  3227. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3228. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  3229. struct sde_rm *rm = &sde_kms->rm;
  3230. struct sde_crtc_mixer *mixer;
  3231. struct sde_hw_ctl *last_valid_ctl = NULL;
  3232. int i;
  3233. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  3234. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  3235. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  3236. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  3237. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  3238. /* Set up all the mixers and ctls reserved by this encoder */
  3239. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  3240. mixer = &sde_crtc->mixers[i];
  3241. if (!sde_rm_get_hw(rm, &lm_iter))
  3242. break;
  3243. mixer->hw_lm = to_sde_hw_mixer(lm_iter.hw);
  3244. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  3245. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  3246. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  3247. mixer->hw_lm->idx - LM_0);
  3248. mixer->hw_ctl = last_valid_ctl;
  3249. } else {
  3250. mixer->hw_ctl = to_sde_hw_ctl(ctl_iter.hw);
  3251. last_valid_ctl = mixer->hw_ctl;
  3252. sde_crtc->num_ctls++;
  3253. }
  3254. /* Shouldn't happen, mixers are always >= ctls */
  3255. if (!mixer->hw_ctl) {
  3256. SDE_ERROR("no valid ctls found for lm %d\n",
  3257. mixer->hw_lm->idx - LM_0);
  3258. return;
  3259. }
  3260. /* Dspp may be null */
  3261. (void) sde_rm_get_hw(rm, &dspp_iter);
  3262. mixer->hw_dspp = to_sde_hw_dspp(dspp_iter.hw);
  3263. /* DS may be null */
  3264. (void) sde_rm_get_hw(rm, &ds_iter);
  3265. mixer->hw_ds = to_sde_hw_ds(ds_iter.hw);
  3266. mixer->encoder = enc;
  3267. sde_crtc->num_mixers++;
  3268. SDE_DEBUG("setup mixer %d: lm %d\n",
  3269. i, mixer->hw_lm->idx - LM_0);
  3270. SDE_DEBUG("setup mixer %d: ctl %d\n",
  3271. i, mixer->hw_ctl->idx - CTL_0);
  3272. if (mixer->hw_ds)
  3273. SDE_DEBUG("setup mixer %d: ds %d\n",
  3274. i, mixer->hw_ds->idx - DS_0);
  3275. }
  3276. }
  3277. bool sde_crtc_is_line_insertion_supported(struct drm_crtc *crtc)
  3278. {
  3279. struct drm_encoder *enc = NULL;
  3280. struct sde_kms *kms;
  3281. if (!crtc)
  3282. return false;
  3283. kms = _sde_crtc_get_kms(crtc);
  3284. if (!kms || !kms->catalog || !kms->catalog->has_line_insertion)
  3285. return false;
  3286. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  3287. if (enc->crtc == crtc)
  3288. return sde_encoder_is_line_insertion_supported(enc);
  3289. }
  3290. return false;
  3291. }
  3292. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  3293. {
  3294. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3295. struct drm_encoder *enc;
  3296. sde_crtc->num_ctls = 0;
  3297. sde_crtc->num_mixers = 0;
  3298. sde_crtc->mixers_swapped = false;
  3299. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3300. mutex_lock(&sde_crtc->crtc_lock);
  3301. /* Check for mixers on all encoders attached to this crtc */
  3302. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  3303. if (enc->crtc != crtc)
  3304. continue;
  3305. /* avoid overwriting mixers info from a copy encoder */
  3306. if (sde_encoder_in_clone_mode(enc))
  3307. continue;
  3308. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  3309. }
  3310. mutex_unlock(&sde_crtc->crtc_lock);
  3311. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  3312. }
  3313. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  3314. {
  3315. int i;
  3316. struct sde_crtc_state *cstate;
  3317. cstate = to_sde_crtc_state(state);
  3318. cstate->is_ppsplit = false;
  3319. for (i = 0; i < cstate->num_connectors; i++) {
  3320. struct drm_connector *conn = cstate->connectors[i];
  3321. if (sde_connector_get_topology_name(conn) ==
  3322. SDE_RM_TOPOLOGY_PPSPLIT)
  3323. cstate->is_ppsplit = true;
  3324. }
  3325. }
  3326. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc, struct drm_crtc_state *state)
  3327. {
  3328. struct sde_crtc *sde_crtc;
  3329. struct sde_crtc_state *cstate;
  3330. struct drm_display_mode *adj_mode;
  3331. u32 mixer_width, mixer_height;
  3332. int i;
  3333. if (!crtc || !state) {
  3334. SDE_ERROR("invalid args\n");
  3335. return;
  3336. }
  3337. sde_crtc = to_sde_crtc(crtc);
  3338. cstate = to_sde_crtc_state(state);
  3339. adj_mode = &state->adjusted_mode;
  3340. sde_crtc_get_mixer_resolution(crtc, state, adj_mode, &mixer_width, &mixer_height);
  3341. for (i = 0; i < sde_crtc->num_mixers; i++) {
  3342. cstate->lm_bounds[i].x = mixer_width * i;
  3343. cstate->lm_bounds[i].y = 0;
  3344. cstate->lm_bounds[i].w = mixer_width;
  3345. cstate->lm_bounds[i].h = mixer_height;
  3346. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i], sizeof(cstate->lm_roi[i]));
  3347. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  3348. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  3349. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  3350. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  3351. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  3352. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  3353. }
  3354. drm_mode_debug_printmodeline(adj_mode);
  3355. }
  3356. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  3357. {
  3358. struct sde_crtc_mixer mixer;
  3359. /*
  3360. * Use mixer[0] to get hw_ctl which will use ops to clear
  3361. * all blendstages. Clear all blendstages will iterate through
  3362. * all mixers.
  3363. */
  3364. if (sde_crtc->num_mixers) {
  3365. mixer = sde_crtc->mixers[0];
  3366. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  3367. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  3368. if (mixer.hw_ctl && mixer.hw_ctl->ops.set_active_pipes)
  3369. mixer.hw_ctl->ops.set_active_pipes(mixer.hw_ctl, NULL);
  3370. }
  3371. }
  3372. static void _sde_crtc_atomic_begin(struct drm_crtc *crtc,
  3373. struct drm_crtc_state *old_state)
  3374. {
  3375. struct sde_crtc *sde_crtc;
  3376. struct drm_encoder *encoder;
  3377. struct drm_device *dev;
  3378. struct sde_kms *sde_kms;
  3379. struct sde_splash_display *splash_display;
  3380. bool cont_splash_enabled = false;
  3381. size_t i;
  3382. if (!crtc->state->enable) {
  3383. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  3384. crtc->base.id, crtc->state->enable);
  3385. return;
  3386. }
  3387. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3388. SDE_ERROR("power resource is not enabled\n");
  3389. return;
  3390. }
  3391. sde_kms = _sde_crtc_get_kms(crtc);
  3392. if (!sde_kms)
  3393. return;
  3394. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  3395. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3396. sde_crtc = to_sde_crtc(crtc);
  3397. dev = crtc->dev;
  3398. if (!sde_crtc->num_mixers) {
  3399. _sde_crtc_setup_mixers(crtc);
  3400. _sde_crtc_setup_is_ppsplit(crtc->state);
  3401. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  3402. _sde_crtc_clear_all_blend_stages(sde_crtc);
  3403. } else if (sde_crtc->num_mixers && sde_crtc->reinit_crtc_mixers) {
  3404. _sde_crtc_setup_mixers(crtc);
  3405. sde_crtc->reinit_crtc_mixers = false;
  3406. }
  3407. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3408. if (encoder->crtc != crtc)
  3409. continue;
  3410. /* encoder will trigger pending mask now */
  3411. sde_encoder_trigger_kickoff_pending(encoder);
  3412. }
  3413. /* update performance setting */
  3414. sde_core_perf_crtc_update(crtc, 1, false);
  3415. /*
  3416. * If no mixers have been allocated in sde_crtc_atomic_check(),
  3417. * it means we are trying to flush a CRTC whose state is disabled:
  3418. * nothing else needs to be done.
  3419. */
  3420. if (unlikely(!sde_crtc->num_mixers))
  3421. goto end;
  3422. _sde_crtc_blend_setup(crtc, old_state, true);
  3423. _sde_crtc_dest_scaler_setup(crtc);
  3424. sde_cp_crtc_apply_noise(crtc, old_state);
  3425. if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)
  3426. sde_core_perf_crtc_update_uidle(crtc, true);
  3427. /* update cached_encoder_mask if new conn is added or removed */
  3428. if (crtc->state->connectors_changed)
  3429. sde_crtc->cached_encoder_mask = crtc->state->encoder_mask;
  3430. /*
  3431. * Since CP properties use AXI buffer to program the
  3432. * HW, check if context bank is in attached state,
  3433. * apply color processing properties only if
  3434. * smmu state is attached,
  3435. */
  3436. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  3437. splash_display = &sde_kms->splash_data.splash_display[i];
  3438. if (splash_display->cont_splash_enabled &&
  3439. splash_display->encoder &&
  3440. crtc == splash_display->encoder->crtc)
  3441. cont_splash_enabled = true;
  3442. }
  3443. if (sde_kms_is_cp_operation_allowed(sde_kms))
  3444. sde_cp_crtc_apply_properties(crtc);
  3445. if (!sde_crtc->enabled)
  3446. sde_cp_crtc_mark_features_dirty(crtc);
  3447. /*
  3448. * PP_DONE irq is only used by command mode for now.
  3449. * It is better to request pending before FLUSH and START trigger
  3450. * to make sure no pp_done irq missed.
  3451. * This is safe because no pp_done will happen before SW trigger
  3452. * in command mode.
  3453. */
  3454. end:
  3455. SDE_ATRACE_END("crtc_atomic_begin");
  3456. }
  3457. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3458. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  3459. struct drm_atomic_state *state)
  3460. {
  3461. struct drm_crtc_state *old_state = NULL;
  3462. if (!crtc) {
  3463. SDE_ERROR("invalid crtc\n");
  3464. return;
  3465. }
  3466. old_state = drm_atomic_get_old_crtc_state(state, crtc);
  3467. _sde_crtc_atomic_begin(crtc, old_state);
  3468. }
  3469. #else
  3470. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  3471. struct drm_crtc_state *old_state)
  3472. {
  3473. if (!crtc) {
  3474. SDE_ERROR("invalid crtc\n");
  3475. return;
  3476. }
  3477. _sde_crtc_atomic_begin(crtc, old_state);
  3478. }
  3479. #endif
  3480. static void sde_crtc_atomic_flush_common(struct drm_crtc *crtc,
  3481. struct drm_atomic_state *state)
  3482. {
  3483. struct drm_encoder *encoder;
  3484. struct sde_crtc *sde_crtc;
  3485. struct drm_device *dev;
  3486. struct drm_plane *plane;
  3487. struct msm_drm_private *priv;
  3488. struct sde_crtc_state *cstate;
  3489. struct sde_kms *sde_kms;
  3490. struct drm_connector *conn;
  3491. struct drm_connector_state *conn_state;
  3492. struct sde_connector *sde_conn = NULL;
  3493. int i;
  3494. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3495. SDE_ERROR("invalid crtc\n");
  3496. return;
  3497. }
  3498. if (!crtc->state->enable) {
  3499. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  3500. crtc->base.id, crtc->state->enable);
  3501. return;
  3502. }
  3503. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3504. SDE_ERROR("power resource is not enabled\n");
  3505. return;
  3506. }
  3507. sde_kms = _sde_crtc_get_kms(crtc);
  3508. if (!sde_kms) {
  3509. SDE_ERROR("invalid kms\n");
  3510. return;
  3511. }
  3512. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3513. sde_crtc = to_sde_crtc(crtc);
  3514. cstate = to_sde_crtc_state(crtc->state);
  3515. dev = crtc->dev;
  3516. priv = dev->dev_private;
  3517. for_each_new_connector_in_state(state, conn, conn_state, i) {
  3518. if (!conn_state || conn_state->crtc != crtc)
  3519. continue;
  3520. sde_conn = to_sde_connector(conn_state->connector);
  3521. }
  3522. /* When doze is requested, switch first to normal mode */
  3523. if (sde_conn && sde_conn->lp_mode && sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE))
  3524. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL, false);
  3525. if ((sde_crtc->cache_state == CACHE_STATE_NORMAL) &&
  3526. sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE))
  3527. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_WRITE,
  3528. false);
  3529. else
  3530. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL, false);
  3531. /*
  3532. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3533. * it means we are trying to flush a CRTC whose state is disabled:
  3534. * nothing else needs to be done.
  3535. */
  3536. if (unlikely(!sde_crtc->num_mixers))
  3537. return;
  3538. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  3539. /*
  3540. * For planes without commit update, drm framework will not add
  3541. * those planes to current state since hardware update is not
  3542. * required. However, if those planes were power collapsed since
  3543. * last commit cycle, driver has to restore the hardware state
  3544. * of those planes explicitly here prior to plane flush.
  3545. * Also use this iteration to see if any plane requires cache,
  3546. * so during the perf update driver can activate/deactivate
  3547. * the cache accordingly.
  3548. */
  3549. for (i = 0; i < SDE_SYS_CACHE_MAX; i++)
  3550. sde_crtc->new_perf.llcc_active[i] = false;
  3551. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3552. sde_plane_restore(plane);
  3553. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  3554. if (sde_plane_is_cache_required(plane, i))
  3555. sde_crtc->new_perf.llcc_active[i] = true;
  3556. }
  3557. }
  3558. sde_core_perf_crtc_update_llcc(crtc);
  3559. /* wait for acquire fences before anything else is done */
  3560. cstate->hwfence_in_fences_set = _sde_crtc_wait_for_fences(crtc);
  3561. if (!cstate->rsc_update) {
  3562. drm_for_each_encoder_mask(encoder, dev,
  3563. crtc->state->encoder_mask) {
  3564. cstate->rsc_client =
  3565. sde_encoder_get_rsc_client(encoder);
  3566. }
  3567. cstate->rsc_update = true;
  3568. }
  3569. /*
  3570. * Final plane updates: Give each plane a chance to complete all
  3571. * required writes/flushing before crtc's "flush
  3572. * everything" call below.
  3573. */
  3574. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3575. if (sde_kms->smmu_state.transition_error)
  3576. sde_plane_set_error(plane, true);
  3577. sde_plane_flush(plane);
  3578. }
  3579. /* Kickoff will be scheduled by outer layer */
  3580. SDE_ATRACE_END("sde_crtc_atomic_flush");
  3581. }
  3582. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3583. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  3584. struct drm_atomic_state *state)
  3585. {
  3586. return sde_crtc_atomic_flush_common(crtc, state);
  3587. }
  3588. #else
  3589. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  3590. struct drm_crtc_state *old_crtc_state)
  3591. {
  3592. return sde_crtc_atomic_flush_common(crtc, old_crtc_state->state);
  3593. }
  3594. #endif
  3595. /**
  3596. * sde_crtc_destroy_state - state destroy hook
  3597. * @crtc: drm CRTC
  3598. * @state: CRTC state object to release
  3599. */
  3600. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  3601. struct drm_crtc_state *state)
  3602. {
  3603. struct sde_crtc *sde_crtc;
  3604. struct sde_crtc_state *cstate;
  3605. struct drm_encoder *enc;
  3606. struct sde_kms *sde_kms;
  3607. if (!crtc || !state) {
  3608. SDE_ERROR("invalid argument(s)\n");
  3609. return;
  3610. }
  3611. sde_crtc = to_sde_crtc(crtc);
  3612. cstate = to_sde_crtc_state(state);
  3613. sde_kms = _sde_crtc_get_kms(crtc);
  3614. if (!sde_kms) {
  3615. SDE_ERROR("invalid sde_kms\n");
  3616. return;
  3617. }
  3618. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3619. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  3620. sde_rm_release(&sde_kms->rm, enc, true);
  3621. sde_cp_clear_state_info(state);
  3622. __drm_atomic_helper_crtc_destroy_state(state);
  3623. /* destroy value helper */
  3624. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  3625. &cstate->property_state);
  3626. }
  3627. static int _sde_crtc_flush_frame_events(struct drm_crtc *crtc)
  3628. {
  3629. struct sde_crtc *sde_crtc;
  3630. int i;
  3631. if (!crtc) {
  3632. SDE_ERROR("invalid argument\n");
  3633. return -EINVAL;
  3634. }
  3635. sde_crtc = to_sde_crtc(crtc);
  3636. if (!atomic_read(&sde_crtc->frame_pending)) {
  3637. SDE_DEBUG("no frames pending\n");
  3638. return 0;
  3639. }
  3640. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  3641. /*
  3642. * flush all the event thread work to make sure all the
  3643. * FRAME_EVENTS from encoder are propagated to crtc
  3644. */
  3645. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  3646. if (list_empty(&sde_crtc->frame_events[i].list))
  3647. kthread_flush_work(&sde_crtc->frame_events[i].work);
  3648. }
  3649. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  3650. return 0;
  3651. }
  3652. /**
  3653. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  3654. * @crtc: Pointer to crtc structure
  3655. */
  3656. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  3657. {
  3658. struct drm_plane *plane;
  3659. struct drm_plane_state *state;
  3660. struct sde_crtc *sde_crtc;
  3661. struct sde_crtc_mixer *mixer;
  3662. struct sde_hw_ctl *ctl;
  3663. if (!crtc)
  3664. return;
  3665. sde_crtc = to_sde_crtc(crtc);
  3666. mixer = sde_crtc->mixers;
  3667. if (!mixer)
  3668. return;
  3669. ctl = mixer->hw_ctl;
  3670. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3671. state = plane->state;
  3672. if (!state)
  3673. continue;
  3674. /* clear plane flush bitmask */
  3675. sde_plane_ctl_flush(plane, ctl, false);
  3676. }
  3677. }
  3678. /**
  3679. * sde_crtc_reset_hw - attempt hardware reset on errors
  3680. * @crtc: Pointer to DRM crtc instance
  3681. * @old_state: Pointer to crtc state for previous commit
  3682. * @recovery_events: Whether or not recovery events are enabled
  3683. * Returns: Zero if current commit should still be attempted
  3684. */
  3685. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  3686. bool recovery_events)
  3687. {
  3688. struct drm_plane *plane_halt[MAX_PLANES];
  3689. struct drm_plane *plane;
  3690. struct drm_encoder *encoder;
  3691. struct sde_crtc *sde_crtc;
  3692. struct sde_crtc_state *cstate;
  3693. struct sde_hw_ctl *ctl;
  3694. signed int i, plane_count;
  3695. int rc;
  3696. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  3697. return -EINVAL;
  3698. sde_crtc = to_sde_crtc(crtc);
  3699. cstate = to_sde_crtc_state(crtc->state);
  3700. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  3701. /* optionally generate a panic instead of performing a h/w reset */
  3702. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  3703. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3704. ctl = sde_crtc->mixers[i].hw_ctl;
  3705. if (!ctl || !ctl->ops.reset)
  3706. continue;
  3707. rc = ctl->ops.reset(ctl);
  3708. if (rc) {
  3709. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  3710. crtc->base.id, ctl->idx - CTL_0);
  3711. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  3712. SDE_EVTLOG_ERROR);
  3713. break;
  3714. }
  3715. }
  3716. /*
  3717. * Early out if simple ctl reset succeeded or reset is
  3718. * being performed after timeout
  3719. */
  3720. if (i == sde_crtc->num_ctls || crtc->state == old_state)
  3721. return 0;
  3722. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  3723. /* force all components in the system into reset at the same time */
  3724. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3725. ctl = sde_crtc->mixers[i].hw_ctl;
  3726. if (!ctl || !ctl->ops.hard_reset)
  3727. continue;
  3728. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  3729. ctl->ops.hard_reset(ctl, true);
  3730. }
  3731. plane_count = 0;
  3732. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  3733. if (plane_count >= ARRAY_SIZE(plane_halt))
  3734. break;
  3735. plane_halt[plane_count++] = plane;
  3736. sde_plane_halt_requests(plane, true);
  3737. sde_plane_set_revalidate(plane, true);
  3738. }
  3739. /* provide safe "border color only" commit configuration for later */
  3740. _sde_crtc_remove_pipe_flush(crtc);
  3741. _sde_crtc_blend_setup(crtc, old_state, false);
  3742. /* take h/w components out of reset */
  3743. for (i = plane_count - 1; i >= 0; --i)
  3744. sde_plane_halt_requests(plane_halt[i], false);
  3745. /* attempt to poll for start of frame cycle before reset release */
  3746. list_for_each_entry(encoder,
  3747. &crtc->dev->mode_config.encoder_list, head) {
  3748. if (encoder->crtc != crtc)
  3749. continue;
  3750. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3751. sde_encoder_poll_line_counts(encoder);
  3752. }
  3753. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3754. ctl = sde_crtc->mixers[i].hw_ctl;
  3755. if (!ctl || !ctl->ops.hard_reset)
  3756. continue;
  3757. ctl->ops.hard_reset(ctl, false);
  3758. }
  3759. list_for_each_entry(encoder,
  3760. &crtc->dev->mode_config.encoder_list, head) {
  3761. if (encoder->crtc != crtc)
  3762. continue;
  3763. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3764. sde_encoder_kickoff(encoder, true);
  3765. }
  3766. /* panic the device if VBIF is not in good state */
  3767. return !recovery_events ? 0 : -EAGAIN;
  3768. }
  3769. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3770. struct drm_crtc_state *old_state)
  3771. {
  3772. struct drm_encoder *encoder;
  3773. struct drm_device *dev;
  3774. struct sde_crtc *sde_crtc;
  3775. struct sde_kms *sde_kms;
  3776. struct sde_crtc_state *cstate;
  3777. bool is_error = false;
  3778. unsigned long flags;
  3779. enum sde_crtc_idle_pc_state idle_pc_state;
  3780. struct sde_encoder_kickoff_params params = { 0 };
  3781. bool is_vid = false;
  3782. if (!crtc) {
  3783. SDE_ERROR("invalid argument\n");
  3784. return;
  3785. }
  3786. dev = crtc->dev;
  3787. sde_crtc = to_sde_crtc(crtc);
  3788. sde_kms = _sde_crtc_get_kms(crtc);
  3789. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3790. SDE_ERROR("invalid argument\n");
  3791. return;
  3792. }
  3793. cstate = to_sde_crtc_state(crtc->state);
  3794. /*
  3795. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3796. * it means we are trying to start a CRTC whose state is disabled:
  3797. * nothing else needs to be done.
  3798. */
  3799. if (unlikely(!sde_crtc->num_mixers))
  3800. return;
  3801. SDE_ATRACE_BEGIN("crtc_commit");
  3802. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3803. sde_crtc->kickoff_in_progress = true;
  3804. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3805. if (encoder->crtc != crtc)
  3806. continue;
  3807. /*
  3808. * Encoder will flush/start now, unless it has a tx pending.
  3809. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3810. */
  3811. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3812. crtc->state);
  3813. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3814. sde_crtc->needs_hw_reset = true;
  3815. if (idle_pc_state != IDLE_PC_NONE)
  3816. sde_encoder_control_idle_pc(encoder,
  3817. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3818. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3819. is_vid = true;
  3820. }
  3821. /*
  3822. * Optionally attempt h/w recovery if any errors were detected while
  3823. * preparing for the kickoff
  3824. */
  3825. if (sde_crtc->needs_hw_reset) {
  3826. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3827. if (sde_crtc->frame_trigger_mode
  3828. != FRAME_DONE_WAIT_POSTED_START &&
  3829. sde_crtc_reset_hw(crtc, old_state,
  3830. params.recovery_events_enabled))
  3831. is_error = true;
  3832. sde_crtc->needs_hw_reset = false;
  3833. }
  3834. sde_crtc_calc_fps(sde_crtc);
  3835. SDE_ATRACE_BEGIN("flush_event_thread");
  3836. _sde_crtc_flush_frame_events(crtc);
  3837. SDE_ATRACE_END("flush_event_thread");
  3838. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3839. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3840. /* acquire bandwidth and other resources */
  3841. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3842. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3843. } else {
  3844. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3845. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3846. }
  3847. sde_crtc->play_count++;
  3848. sde_vbif_clear_errors(sde_kms);
  3849. if (is_error) {
  3850. _sde_crtc_remove_pipe_flush(crtc);
  3851. _sde_crtc_blend_setup(crtc, old_state, false);
  3852. }
  3853. /*
  3854. * for cmd and wb modes, update the txq for incoming fences before flush to avoid race
  3855. * condition between txq update and the hw signal during ctl-done for partial updates
  3856. */
  3857. if (test_bit(HW_FENCE_OUT_FENCES_ENABLE, sde_crtc->hwfence_features_mask) && !is_vid)
  3858. sde_fence_update_hw_fences_txq(sde_crtc->output_fence, false);
  3859. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3860. if (encoder->crtc != crtc)
  3861. continue;
  3862. sde_encoder_kickoff(encoder, true);
  3863. }
  3864. sde_crtc->kickoff_in_progress = false;
  3865. /* store the event after frame trigger */
  3866. if (sde_crtc->event) {
  3867. WARN_ON(sde_crtc->event);
  3868. } else {
  3869. spin_lock_irqsave(&dev->event_lock, flags);
  3870. sde_crtc->event = crtc->state->event;
  3871. spin_unlock_irqrestore(&dev->event_lock, flags);
  3872. }
  3873. SDE_ATRACE_END("crtc_commit");
  3874. }
  3875. /**
  3876. * _sde_crtc_vblank_enable - update power resource and vblank request
  3877. * @sde_crtc: Pointer to sde crtc structure
  3878. * @enable: Whether to enable/disable vblanks
  3879. *
  3880. * @Return: error code
  3881. */
  3882. static int _sde_crtc_vblank_enable(
  3883. struct sde_crtc *sde_crtc, bool enable)
  3884. {
  3885. struct drm_crtc *crtc;
  3886. struct drm_encoder *enc;
  3887. if (!sde_crtc) {
  3888. SDE_ERROR("invalid crtc\n");
  3889. return -EINVAL;
  3890. }
  3891. crtc = &sde_crtc->base;
  3892. SDE_EVT32(DRMID(crtc), enable, sde_crtc->enabled,
  3893. crtc->state->encoder_mask,
  3894. sde_crtc->cached_encoder_mask);
  3895. if (enable) {
  3896. int ret;
  3897. ret = pm_runtime_resume_and_get(crtc->dev->dev);
  3898. if (ret < 0) {
  3899. SDE_ERROR("failed to enable power resource %d\n", ret);
  3900. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  3901. return ret;
  3902. }
  3903. mutex_lock(&sde_crtc->crtc_lock);
  3904. drm_for_each_encoder_mask(enc, crtc->dev, sde_crtc->cached_encoder_mask) {
  3905. if (sde_encoder_in_clone_mode(enc))
  3906. continue;
  3907. sde_encoder_register_vblank_callback(enc, sde_crtc_vblank_cb, (void *)crtc);
  3908. }
  3909. mutex_unlock(&sde_crtc->crtc_lock);
  3910. } else {
  3911. mutex_lock(&sde_crtc->crtc_lock);
  3912. drm_for_each_encoder_mask(enc, crtc->dev, sde_crtc->cached_encoder_mask) {
  3913. if (sde_encoder_in_clone_mode(enc))
  3914. continue;
  3915. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3916. }
  3917. mutex_unlock(&sde_crtc->crtc_lock);
  3918. pm_runtime_put_sync(crtc->dev->dev);
  3919. }
  3920. return 0;
  3921. }
  3922. static void _sde_crtc_reserve_resource(struct drm_crtc *crtc, struct drm_connector *conn)
  3923. {
  3924. u32 min_transfer_time = 0, lm_count = 1;
  3925. u64 mode_clock_hz = 0, updated_fps = 0, topology_id;
  3926. struct drm_encoder *encoder;
  3927. if (!crtc || !conn)
  3928. return;
  3929. encoder = conn->state->best_encoder;
  3930. if (!sde_encoder_is_built_in_display(encoder))
  3931. return;
  3932. if (sde_encoder_check_curr_mode(encoder, MSM_DISPLAY_CMD_MODE))
  3933. sde_encoder_get_transfer_time(encoder, &min_transfer_time);
  3934. if (min_transfer_time)
  3935. updated_fps = DIV_ROUND_UP(1000000, min_transfer_time);
  3936. else
  3937. updated_fps = drm_mode_vrefresh(&crtc->mode);
  3938. topology_id = sde_connector_get_topology_name(conn);
  3939. if (TOPOLOGY_DUALPIPE_MODE(topology_id))
  3940. lm_count = 2;
  3941. else if (TOPOLOGY_QUADPIPE_MODE(topology_id))
  3942. lm_count = 4;
  3943. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  3944. mode_clock_hz = mult_frac(crtc->mode.htotal * crtc->mode.vtotal * updated_fps, 105, 100);
  3945. mode_clock_hz = div_u64(mode_clock_hz, lm_count);
  3946. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u\n",
  3947. crtc->mode.name, crtc->mode.htotal, crtc->mode.vtotal,
  3948. updated_fps, lm_count, mode_clock_hz);
  3949. sde_core_perf_crtc_reserve_res(crtc, mode_clock_hz);
  3950. }
  3951. /**
  3952. * sde_crtc_duplicate_state - state duplicate hook
  3953. * @crtc: Pointer to drm crtc structure
  3954. * @Returns: Pointer to new drm_crtc_state structure
  3955. */
  3956. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3957. {
  3958. struct sde_crtc *sde_crtc;
  3959. struct sde_crtc_state *cstate, *old_cstate;
  3960. if (!crtc || !crtc->state) {
  3961. SDE_ERROR("invalid argument(s)\n");
  3962. return NULL;
  3963. }
  3964. sde_crtc = to_sde_crtc(crtc);
  3965. old_cstate = to_sde_crtc_state(crtc->state);
  3966. if (old_cstate->cont_splash_populated) {
  3967. crtc->state->plane_mask = 0;
  3968. crtc->state->connector_mask = 0;
  3969. crtc->state->encoder_mask = 0;
  3970. crtc->state->enable = false;
  3971. old_cstate->cont_splash_populated = false;
  3972. }
  3973. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3974. if (!cstate) {
  3975. SDE_ERROR("failed to allocate state\n");
  3976. return NULL;
  3977. }
  3978. /* duplicate value helper */
  3979. msm_property_duplicate_state(&sde_crtc->property_info,
  3980. old_cstate, cstate,
  3981. &cstate->property_state, cstate->property_values);
  3982. sde_cp_duplicate_state_info(&old_cstate->base, &cstate->base);
  3983. /* duplicate base helper */
  3984. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3985. return &cstate->base;
  3986. }
  3987. /**
  3988. * sde_crtc_reset - reset hook for CRTCs
  3989. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3990. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3991. * @crtc: Pointer to drm crtc structure
  3992. */
  3993. static void sde_crtc_reset(struct drm_crtc *crtc)
  3994. {
  3995. struct sde_crtc *sde_crtc;
  3996. struct sde_crtc_state *cstate;
  3997. if (!crtc) {
  3998. SDE_ERROR("invalid crtc\n");
  3999. return;
  4000. }
  4001. /* revert suspend actions, if necessary */
  4002. if (!sde_crtc_is_reset_required(crtc)) {
  4003. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  4004. return;
  4005. }
  4006. /* remove previous state, if present */
  4007. if (crtc->state) {
  4008. sde_crtc_destroy_state(crtc, crtc->state);
  4009. crtc->state = 0;
  4010. }
  4011. sde_crtc = to_sde_crtc(crtc);
  4012. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  4013. if (!cstate) {
  4014. SDE_ERROR("failed to allocate state\n");
  4015. return;
  4016. }
  4017. /* reset value helper */
  4018. msm_property_reset_state(&sde_crtc->property_info, cstate,
  4019. &cstate->property_state,
  4020. cstate->property_values);
  4021. _sde_crtc_set_input_fence_timeout(cstate);
  4022. cstate->base.crtc = crtc;
  4023. crtc->state = &cstate->base;
  4024. }
  4025. static void sde_crtc_clear_cached_mixer_cfg(struct drm_crtc *crtc)
  4026. {
  4027. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4028. struct sde_hw_mixer *hw_lm;
  4029. int lm_idx;
  4030. /* clearing lm cfg marks it dirty to force reprogramming next update */
  4031. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  4032. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  4033. hw_lm->cfg.out_width = 0;
  4034. hw_lm->cfg.out_height = 0;
  4035. }
  4036. SDE_EVT32(DRMID(crtc));
  4037. }
  4038. void sde_crtc_reset_sw_state(struct drm_crtc *crtc)
  4039. {
  4040. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  4041. struct drm_plane *plane;
  4042. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4043. /* mark planes, mixers, and other blocks dirty for next update */
  4044. drm_atomic_crtc_for_each_plane(plane, crtc)
  4045. sde_plane_set_revalidate(plane, true);
  4046. /* mark mixers dirty for next update */
  4047. sde_crtc_clear_cached_mixer_cfg(crtc);
  4048. /* mark other properties which need to be dirty for next update */
  4049. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask);
  4050. if (cstate->num_ds_enabled)
  4051. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  4052. }
  4053. static void sde_crtc_post_ipc(struct drm_crtc *crtc)
  4054. {
  4055. struct sde_crtc *sde_crtc;
  4056. struct sde_crtc_state *cstate;
  4057. struct drm_encoder *encoder;
  4058. sde_crtc = to_sde_crtc(crtc);
  4059. cstate = to_sde_crtc_state(crtc->state);
  4060. /* restore encoder; crtc will be programmed during commit */
  4061. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  4062. sde_encoder_virt_restore(encoder);
  4063. /* restore UIDLE */
  4064. sde_core_perf_crtc_update_uidle(crtc, true);
  4065. sde_cp_crtc_post_ipc(crtc);
  4066. }
  4067. static void sde_crtc_mmrm_cb_notification(struct drm_crtc *crtc)
  4068. {
  4069. struct msm_drm_private *priv;
  4070. unsigned long requested_clk;
  4071. struct sde_kms *kms = NULL;
  4072. if (!crtc->dev->dev_private) {
  4073. pr_err("invalid crtc priv\n");
  4074. return;
  4075. }
  4076. priv = crtc->dev->dev_private;
  4077. kms = to_sde_kms(priv->kms);
  4078. if (!kms) {
  4079. SDE_ERROR("invalid parameters\n");
  4080. return;
  4081. }
  4082. requested_clk = sde_power_mmrm_get_requested_clk(&priv->phandle,
  4083. kms->perf.clk_name);
  4084. /* notify user space the reduced clk rate */
  4085. sde_crtc_event_notify(crtc, DRM_EVENT_MMRM_CB, &requested_clk, sizeof(unsigned long));
  4086. SDE_DEBUG("crtc[%d]: MMRM cb notified clk:%d\n",
  4087. crtc->base.id, requested_clk);
  4088. }
  4089. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  4090. {
  4091. struct drm_crtc *crtc = arg;
  4092. struct sde_crtc *sde_crtc;
  4093. struct drm_encoder *encoder;
  4094. u32 power_on;
  4095. unsigned long flags;
  4096. struct sde_crtc_irq_info *node = NULL;
  4097. int ret = 0;
  4098. if (!crtc) {
  4099. SDE_ERROR("invalid crtc\n");
  4100. return;
  4101. }
  4102. sde_crtc = to_sde_crtc(crtc);
  4103. mutex_lock(&sde_crtc->crtc_lock);
  4104. SDE_EVT32(DRMID(crtc), event_type);
  4105. switch (event_type) {
  4106. case SDE_POWER_EVENT_POST_ENABLE:
  4107. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  4108. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  4109. ret = 0;
  4110. if (node->func)
  4111. ret = node->func(crtc, true, &node->irq);
  4112. if (ret)
  4113. SDE_ERROR("%s failed to enable event %x\n",
  4114. sde_crtc->name, node->event);
  4115. }
  4116. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  4117. sde_crtc_post_ipc(crtc);
  4118. break;
  4119. case SDE_POWER_EVENT_PRE_DISABLE:
  4120. drm_for_each_encoder_mask(encoder, crtc->dev,
  4121. crtc->state->encoder_mask) {
  4122. /*
  4123. * disable the vsync source after updating the
  4124. * rsc state. rsc state update might have vsync wait
  4125. * and vsync source must be disabled after it.
  4126. * It will avoid generating any vsync from this point
  4127. * till mode-2 entry. It is SW workaround for HW
  4128. * limitation and should not be removed without
  4129. * checking the updated design.
  4130. */
  4131. sde_encoder_control_te(encoder, false);
  4132. }
  4133. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  4134. node = NULL;
  4135. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  4136. ret = 0;
  4137. if (node->func)
  4138. ret = node->func(crtc, false, &node->irq);
  4139. if (ret)
  4140. SDE_ERROR("%s failed to disable event %x\n",
  4141. sde_crtc->name, node->event);
  4142. }
  4143. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  4144. sde_cp_crtc_pre_ipc(crtc);
  4145. break;
  4146. case SDE_POWER_EVENT_POST_DISABLE:
  4147. sde_crtc_reset_sw_state(crtc);
  4148. sde_cp_crtc_suspend(crtc);
  4149. power_on = 0;
  4150. sde_crtc_event_notify(crtc, DRM_EVENT_SDE_POWER, &power_on, sizeof(u32));
  4151. break;
  4152. case SDE_POWER_EVENT_MMRM_CALLBACK:
  4153. sde_crtc_mmrm_cb_notification(crtc);
  4154. break;
  4155. default:
  4156. SDE_DEBUG("event:%d not handled\n", event_type);
  4157. break;
  4158. }
  4159. mutex_unlock(&sde_crtc->crtc_lock);
  4160. }
  4161. static void _sde_crtc_reset(struct drm_crtc *crtc)
  4162. {
  4163. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4164. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  4165. /* mark mixer cfgs dirty before wiping them */
  4166. sde_crtc_clear_cached_mixer_cfg(crtc);
  4167. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  4168. sde_crtc->num_mixers = 0;
  4169. sde_crtc->mixers_swapped = false;
  4170. /* disable clk & bw control until clk & bw properties are set */
  4171. cstate->bw_control = false;
  4172. cstate->bw_split_vote = false;
  4173. cstate->hwfence_in_fences_set = false;
  4174. sde_crtc_static_img_control(crtc, CACHE_STATE_DISABLED, false);
  4175. }
  4176. static void sde_crtc_disable(struct drm_crtc *crtc)
  4177. {
  4178. struct sde_kms *sde_kms;
  4179. struct sde_crtc *sde_crtc;
  4180. struct sde_crtc_state *cstate;
  4181. struct drm_encoder *encoder;
  4182. struct msm_drm_private *priv;
  4183. unsigned long flags;
  4184. struct sde_crtc_irq_info *node = NULL;
  4185. u32 power_on;
  4186. bool in_cont_splash = false;
  4187. int ret, i;
  4188. enum sde_intf_mode intf_mode;
  4189. struct sde_hw_ctl *hw_ctl = NULL;
  4190. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  4191. SDE_ERROR("invalid crtc\n");
  4192. return;
  4193. }
  4194. sde_kms = _sde_crtc_get_kms(crtc);
  4195. if (!sde_kms) {
  4196. SDE_ERROR("invalid kms\n");
  4197. return;
  4198. }
  4199. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  4200. SDE_ERROR("power resource is not enabled\n");
  4201. return;
  4202. }
  4203. sde_crtc = to_sde_crtc(crtc);
  4204. cstate = to_sde_crtc_state(crtc->state);
  4205. priv = crtc->dev->dev_private;
  4206. SDE_DEBUG("crtc%d\n", crtc->base.id);
  4207. /* avoid vblank on/off for virtual display */
  4208. intf_mode = sde_crtc_get_intf_mode(crtc, crtc->state);
  4209. if ((intf_mode != INTF_MODE_WB_BLOCK) && (intf_mode != INTF_MODE_WB_LINE))
  4210. drm_crtc_vblank_off(crtc);
  4211. mutex_lock(&sde_crtc->crtc_lock);
  4212. SDE_EVT32_VERBOSE(DRMID(crtc));
  4213. /* update color processing on suspend */
  4214. sde_cp_crtc_suspend(crtc);
  4215. mutex_unlock(&sde_crtc->crtc_lock);
  4216. kthread_flush_worker(&priv->event_thread[crtc->index].worker);
  4217. mutex_lock(&sde_crtc->crtc_lock);
  4218. kthread_cancel_delayed_work_sync(&sde_crtc->static_cache_read_work);
  4219. SDE_EVT32(DRMID(crtc), sde_crtc->enabled, crtc->state->active,
  4220. crtc->state->enable, sde_crtc->cached_encoder_mask);
  4221. sde_crtc->enabled = false;
  4222. sde_crtc->cached_encoder_mask = 0;
  4223. /* Try to disable uidle */
  4224. sde_core_perf_crtc_update_uidle(crtc, false);
  4225. if (atomic_read(&sde_crtc->frame_pending)) {
  4226. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  4227. atomic_read(&sde_crtc->frame_pending));
  4228. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  4229. SDE_EVTLOG_FUNC_CASE2);
  4230. sde_core_perf_crtc_release_bw(crtc);
  4231. atomic_set(&sde_crtc->frame_pending, 0);
  4232. }
  4233. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  4234. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  4235. ret = 0;
  4236. if (node->func)
  4237. ret = node->func(crtc, false, &node->irq);
  4238. if (ret)
  4239. SDE_ERROR("%s failed to disable event %x\n",
  4240. sde_crtc->name, node->event);
  4241. }
  4242. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  4243. drm_for_each_encoder_mask(encoder, crtc->dev,
  4244. crtc->state->encoder_mask) {
  4245. if (sde_encoder_in_cont_splash(encoder)) {
  4246. in_cont_splash = true;
  4247. break;
  4248. }
  4249. }
  4250. /* avoid clk/bw downvote if cont-splash is enabled */
  4251. if (!in_cont_splash)
  4252. sde_core_perf_crtc_update(crtc, 0, true);
  4253. drm_for_each_encoder_mask(encoder, crtc->dev,
  4254. crtc->state->encoder_mask) {
  4255. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  4256. cstate->rsc_client = NULL;
  4257. cstate->rsc_update = false;
  4258. /*
  4259. * reset idle power-collapse to original state during suspend;
  4260. * user-mode will change the state on resume, if required
  4261. */
  4262. if (test_bit(SDE_FEATURE_IDLE_PC, sde_kms->catalog->features))
  4263. sde_encoder_control_idle_pc(encoder, true);
  4264. }
  4265. if (sde_crtc->power_event) {
  4266. sde_power_handle_unregister_event(&priv->phandle,
  4267. sde_crtc->power_event);
  4268. sde_crtc->power_event = NULL;
  4269. }
  4270. /**
  4271. * All callbacks are unregistered and frame done waits are complete
  4272. * at this point. No buffers are accessed by hardware.
  4273. * reset the fence timeline if crtc will not be enabled for this commit
  4274. */
  4275. if (!crtc->state->active || !crtc->state->enable) {
  4276. if (test_bit(HW_FENCE_OUT_FENCES_ENABLE, sde_crtc->hwfence_features_mask))
  4277. hw_ctl = _sde_crtc_get_hw_ctl(crtc);
  4278. sde_fence_signal(sde_crtc->output_fence,
  4279. ktime_get(), SDE_FENCE_RESET_TIMELINE, hw_ctl);
  4280. for (i = 0; i < cstate->num_connectors; ++i)
  4281. sde_connector_commit_reset(cstate->connectors[i],
  4282. ktime_get());
  4283. }
  4284. _sde_crtc_reset(crtc);
  4285. sde_cp_crtc_disable(crtc);
  4286. power_on = 0;
  4287. sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, &power_on, sizeof(u32));
  4288. /* suspend case: clear stale OPR value */
  4289. if (sde_crtc->opr_event_notify_enabled)
  4290. memset(&sde_crtc->previous_opr_value, 0, sizeof(struct sde_opr_value));
  4291. mutex_unlock(&sde_crtc->crtc_lock);
  4292. }
  4293. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  4294. static void sde_crtc_enable(struct drm_crtc *crtc,
  4295. struct drm_atomic_state *old_state)
  4296. #else
  4297. static void sde_crtc_enable(struct drm_crtc *crtc,
  4298. struct drm_crtc_state *old_crtc_state)
  4299. #endif
  4300. {
  4301. struct sde_crtc *sde_crtc;
  4302. struct drm_encoder *encoder;
  4303. struct msm_drm_private *priv;
  4304. unsigned long flags;
  4305. struct sde_crtc_irq_info *node = NULL;
  4306. int ret, i;
  4307. struct sde_crtc_state *cstate;
  4308. struct msm_display_mode *msm_mode;
  4309. enum sde_intf_mode intf_mode;
  4310. struct sde_kms *kms;
  4311. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  4312. SDE_ERROR("invalid crtc\n");
  4313. return;
  4314. }
  4315. kms = _sde_crtc_get_kms(crtc);
  4316. if (!kms || !kms->catalog) {
  4317. SDE_ERROR("invalid kms handle\n");
  4318. return;
  4319. }
  4320. priv = crtc->dev->dev_private;
  4321. cstate = to_sde_crtc_state(crtc->state);
  4322. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  4323. SDE_ERROR("power resource is not enabled\n");
  4324. return;
  4325. }
  4326. SDE_DEBUG("crtc%d\n", crtc->base.id);
  4327. SDE_EVT32_VERBOSE(DRMID(crtc));
  4328. sde_crtc = to_sde_crtc(crtc);
  4329. cstate->line_insertion.panel_line_insertion_enable =
  4330. sde_crtc_is_line_insertion_supported(crtc);
  4331. /*
  4332. * Avoid drm_crtc_vblank_on during seamless DMS case
  4333. * when CRTC is already in enabled state
  4334. */
  4335. if (!sde_crtc->enabled) {
  4336. /* cache the encoder mask now for vblank work */
  4337. sde_crtc->cached_encoder_mask = crtc->state->encoder_mask;
  4338. /* avoid vblank on/off for virtual display */
  4339. intf_mode = sde_crtc_get_intf_mode(crtc, crtc->state);
  4340. if ((intf_mode != INTF_MODE_WB_BLOCK) && (intf_mode != INTF_MODE_WB_LINE)) {
  4341. /* max possible vsync_cnt(atomic_t) soft counter */
  4342. if (test_bit(SDE_FEATURE_HW_VSYNC_TS, kms->catalog->features))
  4343. drm_crtc_set_max_vblank_count(crtc, INT_MAX);
  4344. drm_crtc_vblank_on(crtc);
  4345. }
  4346. }
  4347. mutex_lock(&sde_crtc->crtc_lock);
  4348. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  4349. /*
  4350. * Try to enable uidle (if possible), we do this before the call
  4351. * to return early during seamless dms mode, so any fps
  4352. * change is also consider to enable/disable UIDLE
  4353. */
  4354. sde_core_perf_crtc_update_uidle(crtc, true);
  4355. msm_mode = sde_crtc_get_msm_mode(crtc->state);
  4356. if (!msm_mode){
  4357. SDE_ERROR("invalid msm mode, %s\n",
  4358. crtc->state->adjusted_mode.name);
  4359. return;
  4360. }
  4361. /* return early if crtc is already enabled, do this after UIDLE check */
  4362. if (sde_crtc->enabled) {
  4363. if (msm_is_mode_seamless_dms(msm_mode) ||
  4364. msm_is_mode_seamless_dyn_clk(msm_mode))
  4365. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  4366. sde_crtc->name);
  4367. else
  4368. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  4369. mutex_unlock(&sde_crtc->crtc_lock);
  4370. return;
  4371. }
  4372. drm_for_each_encoder_mask(encoder, crtc->dev,
  4373. crtc->state->encoder_mask) {
  4374. sde_encoder_register_frame_event_callback(encoder,
  4375. sde_crtc_frame_event_cb, crtc);
  4376. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL,
  4377. sde_encoder_check_curr_mode(encoder,
  4378. MSM_DISPLAY_VIDEO_MODE));
  4379. }
  4380. sde_crtc->enabled = true;
  4381. sde_cp_crtc_enable(crtc);
  4382. /* update color processing on resume */
  4383. sde_cp_crtc_resume(crtc);
  4384. mutex_unlock(&sde_crtc->crtc_lock);
  4385. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  4386. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  4387. ret = 0;
  4388. if (node->func)
  4389. ret = node->func(crtc, true, &node->irq);
  4390. if (ret)
  4391. SDE_ERROR("%s failed to enable event %x\n",
  4392. sde_crtc->name, node->event);
  4393. }
  4394. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  4395. sde_crtc->power_event = sde_power_handle_register_event(
  4396. &priv->phandle,
  4397. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  4398. SDE_POWER_EVENT_PRE_DISABLE | SDE_POWER_EVENT_MMRM_CALLBACK,
  4399. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  4400. /* Enable ESD thread */
  4401. for (i = 0; i < cstate->num_connectors; i++) {
  4402. sde_connector_schedule_status_work(cstate->connectors[i], true);
  4403. _sde_crtc_reserve_resource(crtc, cstate->connectors[i]);
  4404. }
  4405. }
  4406. /* no input validation - caller API has all the checks */
  4407. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc *crtc, struct drm_crtc_state *state,
  4408. struct plane_state pstates[], int cnt)
  4409. {
  4410. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  4411. struct drm_display_mode *mode = &state->adjusted_mode;
  4412. const struct drm_plane_state *pstate;
  4413. struct sde_plane_state *sde_pstate;
  4414. int rc = 0, i;
  4415. struct sde_rect *rect;
  4416. u32 crtc_width, crtc_height;
  4417. sde_crtc_get_resolution(crtc, state, mode, &crtc_width, &crtc_height);
  4418. /* Check dim layer rect bounds and stage */
  4419. for (i = 0; i < cstate->num_dim_layers; i++) {
  4420. rect = &cstate->dim_layer[i].rect;
  4421. if ((CHECK_LAYER_BOUNDS(rect->y, rect->h, crtc_height)) ||
  4422. (CHECK_LAYER_BOUNDS(rect->x, rect->w, crtc_width)) ||
  4423. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) || (!rect->w) || (!rect->h)) {
  4424. SDE_ERROR("crtc:%d wxh:%dx%d, invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  4425. DRMID(state->crtc), crtc_width, crtc_height,
  4426. rect->x, rect->y, rect->w, rect->h,
  4427. cstate->dim_layer[i].stage);
  4428. rc = -E2BIG;
  4429. goto end;
  4430. }
  4431. }
  4432. /* log all src and excl_rect, useful for debugging */
  4433. for (i = 0; i < cnt; i++) {
  4434. pstate = pstates[i].drm_pstate;
  4435. sde_pstate = to_sde_plane_state(pstate);
  4436. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  4437. DRMID(pstate->plane), pstates[i].stage,
  4438. pstate->crtc_x, pstate->crtc_y, pstate->crtc_w, pstate->crtc_h,
  4439. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  4440. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  4441. }
  4442. end:
  4443. return rc;
  4444. }
  4445. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  4446. struct drm_crtc_state *state, struct plane_state pstates[],
  4447. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  4448. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  4449. {
  4450. struct drm_plane *plane;
  4451. int i;
  4452. if (secure == SDE_DRM_SEC_ONLY) {
  4453. /*
  4454. * validate planes - only fb_sec_dir is allowed during sec_crtc
  4455. * - fb_sec_dir is for secure camera preview and
  4456. * secure display use case
  4457. * - fb_sec is for secure video playback
  4458. * - fb_ns is for normal non secure use cases
  4459. */
  4460. if (fb_ns || fb_sec) {
  4461. SDE_ERROR(
  4462. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  4463. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  4464. return -EINVAL;
  4465. }
  4466. /*
  4467. * - only one blending stage is allowed in sec_crtc
  4468. * - validate if pipe is allowed for sec-ui updates
  4469. */
  4470. for (i = 1; i < cnt; i++) {
  4471. if (!pstates[i].drm_pstate
  4472. || !pstates[i].drm_pstate->plane) {
  4473. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  4474. DRMID(crtc), i);
  4475. return -EINVAL;
  4476. }
  4477. plane = pstates[i].drm_pstate->plane;
  4478. if (!sde_plane_is_sec_ui_allowed(plane)) {
  4479. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  4480. DRMID(crtc), plane->base.id);
  4481. return -EINVAL;
  4482. } else if (pstates[i].stage != pstates[i-1].stage) {
  4483. SDE_ERROR(
  4484. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  4485. DRMID(crtc), i, pstates[i].stage,
  4486. i-1, pstates[i-1].stage);
  4487. return -EINVAL;
  4488. }
  4489. }
  4490. /* check if all the dim_layers are in the same stage */
  4491. for (i = 1; i < cstate->num_dim_layers; i++) {
  4492. if (cstate->dim_layer[i].stage !=
  4493. cstate->dim_layer[i-1].stage) {
  4494. SDE_ERROR(
  4495. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  4496. DRMID(crtc),
  4497. i, cstate->dim_layer[i].stage,
  4498. i-1, cstate->dim_layer[i-1].stage);
  4499. return -EINVAL;
  4500. }
  4501. }
  4502. /*
  4503. * if secure-ui supported blendstage is specified,
  4504. * - fail empty commit
  4505. * - validate dim_layer or plane is staged in the supported
  4506. * blendstage
  4507. */
  4508. if (sde_kms->catalog->sui_supported_blendstage) {
  4509. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  4510. cstate->dim_layer[0].stage;
  4511. if (!test_bit(SDE_FEATURE_BASE_LAYER, sde_kms->catalog->features))
  4512. sec_stage -= SDE_STAGE_0;
  4513. if ((!cnt && !cstate->num_dim_layers) ||
  4514. (sde_kms->catalog->sui_supported_blendstage
  4515. != sec_stage)) {
  4516. SDE_ERROR(
  4517. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  4518. DRMID(crtc), cnt,
  4519. cstate->num_dim_layers, sec_stage);
  4520. return -EINVAL;
  4521. }
  4522. }
  4523. }
  4524. return 0;
  4525. }
  4526. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  4527. struct drm_crtc_state *state, int fb_sec_dir)
  4528. {
  4529. struct drm_encoder *encoder;
  4530. int encoder_cnt = 0;
  4531. if (fb_sec_dir) {
  4532. drm_for_each_encoder_mask(encoder, crtc->dev,
  4533. state->encoder_mask)
  4534. encoder_cnt++;
  4535. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  4536. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  4537. DRMID(crtc), encoder_cnt);
  4538. return -EINVAL;
  4539. }
  4540. }
  4541. return 0;
  4542. }
  4543. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  4544. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  4545. int fb_ns, int fb_sec, int fb_sec_dir)
  4546. {
  4547. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  4548. struct drm_encoder *encoder;
  4549. int is_video_mode = false;
  4550. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4551. if (sde_encoder_is_dsi_display(encoder))
  4552. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  4553. MSM_DISPLAY_VIDEO_MODE);
  4554. }
  4555. /*
  4556. * Secure display to secure camera needs without direct
  4557. * transition is currently not allowed
  4558. */
  4559. if (fb_sec_dir && secure == SDE_DRM_SEC_NON_SEC &&
  4560. smmu_state->state != ATTACHED &&
  4561. smmu_state->secure_level == SDE_DRM_SEC_ONLY) {
  4562. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  4563. smmu_state->state, smmu_state->secure_level,
  4564. secure);
  4565. goto sec_err;
  4566. }
  4567. /*
  4568. * In video mode check for null commit before transition
  4569. * from secure to non secure and vice versa
  4570. */
  4571. if (is_video_mode && smmu_state &&
  4572. state->plane_mask && crtc->state->plane_mask &&
  4573. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  4574. (secure == SDE_DRM_SEC_ONLY))) ||
  4575. (fb_ns && ((smmu_state->state == DETACHED) ||
  4576. (smmu_state->state == DETACH_ALL_REQ))) ||
  4577. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  4578. (smmu_state->state == DETACH_SEC_REQ)) &&
  4579. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  4580. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  4581. smmu_state->state, smmu_state->secure_level,
  4582. secure, crtc->state->plane_mask, state->plane_mask);
  4583. goto sec_err;
  4584. }
  4585. return 0;
  4586. sec_err:
  4587. SDE_ERROR(
  4588. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  4589. DRMID(crtc), secure, smmu_state->state,
  4590. smmu_state->secure_level, fb_ns, fb_sec_dir);
  4591. return -EINVAL;
  4592. }
  4593. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  4594. struct drm_crtc_state *state, uint32_t fb_sec)
  4595. {
  4596. bool conn_secure = false, is_wb = false;
  4597. struct drm_connector *conn;
  4598. struct drm_connector_state *conn_state;
  4599. int i;
  4600. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  4601. if (conn_state && conn_state->crtc == crtc) {
  4602. if (conn->connector_type ==
  4603. DRM_MODE_CONNECTOR_VIRTUAL)
  4604. is_wb = true;
  4605. if (sde_connector_get_property(conn_state,
  4606. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  4607. SDE_DRM_FB_SEC)
  4608. conn_secure = true;
  4609. }
  4610. }
  4611. /*
  4612. * If any input buffers are secure for wb,
  4613. * the output buffer must also be secure.
  4614. */
  4615. if (is_wb && fb_sec && !conn_secure) {
  4616. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  4617. DRMID(crtc), fb_sec, conn_secure);
  4618. return -EINVAL;
  4619. }
  4620. return 0;
  4621. }
  4622. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  4623. struct drm_crtc_state *state, struct plane_state pstates[],
  4624. int cnt)
  4625. {
  4626. struct sde_crtc_state *cstate;
  4627. struct sde_kms *sde_kms;
  4628. uint32_t secure;
  4629. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  4630. int rc;
  4631. if (!crtc || !state) {
  4632. SDE_ERROR("invalid arguments\n");
  4633. return -EINVAL;
  4634. }
  4635. sde_kms = _sde_crtc_get_kms(crtc);
  4636. if (!sde_kms || !sde_kms->catalog) {
  4637. SDE_ERROR("invalid kms\n");
  4638. return -EINVAL;
  4639. }
  4640. cstate = to_sde_crtc_state(state);
  4641. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  4642. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  4643. &fb_sec, &fb_sec_dir);
  4644. if (rc)
  4645. return rc;
  4646. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  4647. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  4648. if (rc)
  4649. return rc;
  4650. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  4651. if (rc)
  4652. return rc;
  4653. /*
  4654. * secure_crtc is not allowed in a shared toppolgy
  4655. * across different encoders.
  4656. */
  4657. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  4658. if (rc)
  4659. return rc;
  4660. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  4661. secure, fb_ns, fb_sec, fb_sec_dir);
  4662. if (rc)
  4663. return rc;
  4664. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  4665. return 0;
  4666. }
  4667. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  4668. struct drm_crtc_state *state,
  4669. struct drm_display_mode *mode,
  4670. struct plane_state *pstates,
  4671. struct drm_plane *plane,
  4672. struct sde_multirect_plane_states *multirect_plane,
  4673. int *cnt)
  4674. {
  4675. struct sde_crtc *sde_crtc;
  4676. struct sde_crtc_state *cstate;
  4677. const struct drm_plane_state *pstate;
  4678. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  4679. int rc = 0, multirect_count = 0, i, crtc_width, crtc_height;
  4680. int inc_sde_stage = 0;
  4681. struct sde_kms *kms;
  4682. u32 blend_type;
  4683. sde_crtc = to_sde_crtc(crtc);
  4684. cstate = to_sde_crtc_state(state);
  4685. kms = _sde_crtc_get_kms(crtc);
  4686. if (!kms || !kms->catalog) {
  4687. SDE_ERROR("invalid kms\n");
  4688. return -EINVAL;
  4689. }
  4690. memset(pipe_staged, 0, sizeof(pipe_staged));
  4691. sde_crtc_get_resolution(crtc, state, mode, &crtc_width, &crtc_height);
  4692. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  4693. if (IS_ERR_OR_NULL(pstate)) {
  4694. rc = PTR_ERR(pstate);
  4695. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  4696. sde_crtc->name, plane->base.id, rc);
  4697. return rc;
  4698. }
  4699. if (*cnt >= SDE_PSTATES_MAX)
  4700. continue;
  4701. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  4702. pstates[*cnt].drm_pstate = pstate;
  4703. pstates[*cnt].stage = sde_plane_get_property(
  4704. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  4705. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  4706. blend_type = sde_plane_get_property(pstates[*cnt].sde_pstate,
  4707. PLANE_PROP_BLEND_OP);
  4708. if (!test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features))
  4709. inc_sde_stage = SDE_STAGE_0;
  4710. /* check dim layer stage with every plane */
  4711. for (i = 0; i < cstate->num_dim_layers; i++) {
  4712. if (cstate->dim_layer[i].stage ==
  4713. (pstates[*cnt].stage + inc_sde_stage)) {
  4714. SDE_ERROR(
  4715. "plane:%d/dim_layer:%i-same stage:%d\n",
  4716. plane->base.id, i,
  4717. cstate->dim_layer[i].stage);
  4718. return -EINVAL;
  4719. }
  4720. }
  4721. if (pipe_staged[pstates[*cnt].pipe_id]) {
  4722. multirect_plane[multirect_count].r0 =
  4723. pipe_staged[pstates[*cnt].pipe_id];
  4724. multirect_plane[multirect_count].r1 = pstate;
  4725. multirect_count++;
  4726. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  4727. } else {
  4728. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  4729. }
  4730. (*cnt)++;
  4731. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h, crtc_height) ||
  4732. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w, crtc_width)) {
  4733. SDE_ERROR("invalid dest - y:%d h:%d crtc_h:%d x:%d w:%d crtc_w:%d\n",
  4734. pstate->crtc_y, pstate->crtc_h, crtc_height,
  4735. pstate->crtc_x, pstate->crtc_w, crtc_width);
  4736. return -E2BIG;
  4737. }
  4738. if (blend_type != SDE_DRM_BLEND_OP_SKIP && cstate->num_ds_enabled &&
  4739. ((pstate->crtc_h > crtc_height) || (pstate->crtc_w > crtc_width))) {
  4740. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  4741. pstate->crtc_w, pstate->crtc_h, crtc_width, crtc_height);
  4742. return -E2BIG;
  4743. }
  4744. }
  4745. for (i = 1; i < SSPP_MAX; i++) {
  4746. if (pipe_staged[i]) {
  4747. sde_plane_clear_multirect(pipe_staged[i]);
  4748. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  4749. struct sde_plane_state *psde_state;
  4750. SDE_DEBUG("r1 only virt plane:%d staged\n",
  4751. pipe_staged[i]->plane->base.id);
  4752. psde_state = to_sde_plane_state(
  4753. pipe_staged[i]);
  4754. psde_state->multirect_index = SDE_SSPP_RECT_1;
  4755. }
  4756. }
  4757. }
  4758. for (i = 0; i < multirect_count; i++) {
  4759. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  4760. SDE_ERROR(
  4761. "multirect validation failed for planes (%d - %d)\n",
  4762. multirect_plane[i].r0->plane->base.id,
  4763. multirect_plane[i].r1->plane->base.id);
  4764. return -EINVAL;
  4765. }
  4766. }
  4767. return rc;
  4768. }
  4769. static int _sde_crtc_noise_layer_check_zpos(struct sde_crtc_state *cstate,
  4770. u32 zpos) {
  4771. if (!test_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty) ||
  4772. !cstate->noise_layer_en) {
  4773. SDE_DEBUG("noise layer not enabled %d\n", cstate->noise_layer_en);
  4774. return 0;
  4775. }
  4776. if (cstate->layer_cfg.zposn == zpos ||
  4777. cstate->layer_cfg.zposattn == zpos) {
  4778. SDE_ERROR("invalid zpos %d zposn %d zposattn %d\n", zpos,
  4779. cstate->layer_cfg.zposn, cstate->layer_cfg.zposattn);
  4780. return -EINVAL;
  4781. }
  4782. return 0;
  4783. }
  4784. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  4785. struct sde_crtc *sde_crtc,
  4786. struct plane_state *pstates,
  4787. struct sde_crtc_state *cstate,
  4788. struct drm_display_mode *mode,
  4789. int cnt)
  4790. {
  4791. int rc = 0, i, z_pos;
  4792. u32 zpos_cnt = 0;
  4793. struct drm_crtc *crtc;
  4794. struct sde_kms *kms;
  4795. enum sde_layout layout;
  4796. crtc = &sde_crtc->base;
  4797. kms = _sde_crtc_get_kms(crtc);
  4798. if (!kms || !kms->catalog) {
  4799. SDE_ERROR("Invalid kms\n");
  4800. return -EINVAL;
  4801. }
  4802. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  4803. rc = _sde_crtc_excl_dim_layer_check(crtc, state, pstates, cnt);
  4804. if (rc)
  4805. return rc;
  4806. if (!sde_is_custom_client()) {
  4807. int stage_old = pstates[0].stage;
  4808. z_pos = 0;
  4809. for (i = 0; i < cnt; i++) {
  4810. if (stage_old != pstates[i].stage)
  4811. ++z_pos;
  4812. stage_old = pstates[i].stage;
  4813. pstates[i].stage = z_pos;
  4814. }
  4815. }
  4816. z_pos = -1;
  4817. layout = SDE_LAYOUT_NONE;
  4818. for (i = 0; i < cnt; i++) {
  4819. /* reset counts at every new blend stage */
  4820. if (pstates[i].stage != z_pos ||
  4821. pstates[i].sde_pstate->layout != layout) {
  4822. zpos_cnt = 0;
  4823. z_pos = pstates[i].stage;
  4824. layout = pstates[i].sde_pstate->layout;
  4825. }
  4826. /* verify z_pos setting before using it */
  4827. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  4828. SDE_ERROR("> %d plane stages assigned\n",
  4829. SDE_STAGE_MAX - SDE_STAGE_0);
  4830. return -EINVAL;
  4831. } else if (zpos_cnt == 2) {
  4832. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  4833. return -EINVAL;
  4834. } else {
  4835. zpos_cnt++;
  4836. }
  4837. rc = _sde_crtc_noise_layer_check_zpos(cstate, z_pos);
  4838. if (rc)
  4839. break;
  4840. if (!test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features))
  4841. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  4842. else
  4843. pstates[i].sde_pstate->stage = z_pos;
  4844. SDE_DEBUG("%s: layout %d, zpos %d", sde_crtc->name, layout,
  4845. z_pos);
  4846. }
  4847. return rc;
  4848. }
  4849. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  4850. struct drm_crtc_state *state,
  4851. struct plane_state *pstates,
  4852. struct sde_multirect_plane_states *multirect_plane)
  4853. {
  4854. struct sde_crtc *sde_crtc;
  4855. struct sde_crtc_state *cstate;
  4856. struct sde_kms *kms;
  4857. struct drm_plane *plane = NULL;
  4858. struct drm_display_mode *mode;
  4859. int rc = 0, cnt = 0;
  4860. kms = _sde_crtc_get_kms(crtc);
  4861. if (!kms || !kms->catalog) {
  4862. SDE_ERROR("invalid parameters\n");
  4863. return -EINVAL;
  4864. }
  4865. sde_crtc = to_sde_crtc(crtc);
  4866. cstate = to_sde_crtc_state(state);
  4867. mode = &state->adjusted_mode;
  4868. /* get plane state for all drm planes associated with crtc state */
  4869. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  4870. plane, multirect_plane, &cnt);
  4871. if (rc)
  4872. return rc;
  4873. /* assign mixer stages based on sorted zpos property */
  4874. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  4875. if (rc)
  4876. return rc;
  4877. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  4878. if (rc)
  4879. return rc;
  4880. /*
  4881. * validate and set source split:
  4882. * use pstates sorted by stage to check planes on same stage
  4883. * we assume that all pipes are in source split so its valid to compare
  4884. * without taking into account left/right mixer placement
  4885. */
  4886. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  4887. if (rc)
  4888. return rc;
  4889. return 0;
  4890. }
  4891. static int _sde_crtc_check_plane_layout(struct drm_crtc *crtc,
  4892. struct drm_crtc_state *crtc_state)
  4893. {
  4894. struct sde_kms *kms;
  4895. struct drm_plane *plane;
  4896. struct drm_plane_state *plane_state;
  4897. struct sde_plane_state *pstate;
  4898. struct drm_display_mode *mode;
  4899. int layout_split;
  4900. u32 crtc_width, crtc_height;
  4901. kms = _sde_crtc_get_kms(crtc);
  4902. if (!kms || !kms->catalog) {
  4903. SDE_ERROR("invalid parameters\n");
  4904. return -EINVAL;
  4905. }
  4906. if (!sde_rm_topology_is_group(&kms->rm, crtc_state,
  4907. SDE_RM_TOPOLOGY_GROUP_QUADPIPE))
  4908. return 0;
  4909. mode = &crtc->state->adjusted_mode;
  4910. sde_crtc_get_resolution(crtc, crtc_state, mode, &crtc_width, &crtc_height);
  4911. drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
  4912. plane_state = drm_atomic_get_existing_plane_state(
  4913. crtc_state->state, plane);
  4914. if (!plane_state)
  4915. continue;
  4916. pstate = to_sde_plane_state(plane_state);
  4917. layout_split = crtc_width >> 1;
  4918. if (plane_state->crtc_x >= layout_split) {
  4919. plane_state->crtc_x -= layout_split;
  4920. pstate->layout_offset = layout_split;
  4921. pstate->layout = SDE_LAYOUT_RIGHT;
  4922. } else {
  4923. pstate->layout_offset = -1;
  4924. pstate->layout = SDE_LAYOUT_LEFT;
  4925. }
  4926. SDE_DEBUG("plane%d updated: crtc_x=%d layout=%d\n",
  4927. DRMID(plane), plane_state->crtc_x,
  4928. pstate->layout);
  4929. /* check layout boundary */
  4930. if (CHECK_LAYER_BOUNDS(plane_state->crtc_x,
  4931. plane_state->crtc_w, layout_split)) {
  4932. SDE_ERROR("invalid horizontal destination\n");
  4933. SDE_ERROR("x:%d w:%d hdisp:%d layout:%d\n",
  4934. plane_state->crtc_x,
  4935. plane_state->crtc_w,
  4936. layout_split, pstate->layout);
  4937. return -E2BIG;
  4938. }
  4939. }
  4940. return 0;
  4941. }
  4942. static int _sde_crtc_atomic_check(struct drm_crtc *crtc,
  4943. struct drm_crtc_state *state)
  4944. {
  4945. struct drm_device *dev;
  4946. struct sde_crtc *sde_crtc;
  4947. struct plane_state *pstates = NULL;
  4948. struct sde_crtc_state *cstate;
  4949. struct drm_display_mode *mode;
  4950. int rc = 0;
  4951. struct sde_multirect_plane_states *multirect_plane = NULL;
  4952. struct drm_connector *conn;
  4953. struct drm_connector_list_iter conn_iter;
  4954. if (!crtc) {
  4955. SDE_ERROR("invalid crtc\n");
  4956. return -EINVAL;
  4957. }
  4958. dev = crtc->dev;
  4959. sde_crtc = to_sde_crtc(crtc);
  4960. cstate = to_sde_crtc_state(state);
  4961. if (!state->enable || !state->active) {
  4962. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  4963. crtc->base.id, state->enable, state->active);
  4964. goto end;
  4965. }
  4966. pstates = kcalloc(SDE_PSTATES_MAX,
  4967. sizeof(struct plane_state), GFP_KERNEL);
  4968. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  4969. sizeof(struct sde_multirect_plane_states),
  4970. GFP_KERNEL);
  4971. if (!pstates || !multirect_plane) {
  4972. rc = -ENOMEM;
  4973. goto end;
  4974. }
  4975. mode = &state->adjusted_mode;
  4976. SDE_DEBUG("%s: check", sde_crtc->name);
  4977. /* force a full mode set if active state changed */
  4978. if (state->active_changed)
  4979. state->mode_changed = true;
  4980. /* identify connectors attached to this crtc */
  4981. cstate->num_connectors = 0;
  4982. drm_connector_list_iter_begin(dev, &conn_iter);
  4983. drm_for_each_connector_iter(conn, &conn_iter)
  4984. if ((state->connector_mask & (1 << drm_connector_index(conn)))
  4985. && cstate->num_connectors < MAX_CONNECTORS) {
  4986. cstate->connectors[cstate->num_connectors++] = conn;
  4987. }
  4988. drm_connector_list_iter_end(&conn_iter);
  4989. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4990. if (rc) {
  4991. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4992. crtc->base.id, rc);
  4993. goto end;
  4994. }
  4995. rc = _sde_crtc_check_plane_layout(crtc, state);
  4996. if (rc) {
  4997. SDE_ERROR("crtc%d failed plane layout check %d\n",
  4998. crtc->base.id, rc);
  4999. goto end;
  5000. }
  5001. _sde_crtc_setup_is_ppsplit(state);
  5002. _sde_crtc_setup_lm_bounds(crtc, state);
  5003. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  5004. multirect_plane);
  5005. if (rc) {
  5006. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  5007. goto end;
  5008. }
  5009. rc = sde_core_perf_crtc_check(crtc, state);
  5010. if (rc) {
  5011. SDE_ERROR("crtc%d failed performance check %d\n",
  5012. crtc->base.id, rc);
  5013. goto end;
  5014. }
  5015. rc = _sde_crtc_check_rois(crtc, state);
  5016. if (rc) {
  5017. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  5018. goto end;
  5019. }
  5020. rc = sde_cp_crtc_check_properties(crtc, state);
  5021. if (rc) {
  5022. SDE_ERROR("crtc%d failed cp properties check %d\n",
  5023. crtc->base.id, rc);
  5024. goto end;
  5025. }
  5026. rc = _sde_crtc_check_panel_stacking(crtc, state);
  5027. if (rc) {
  5028. SDE_ERROR("crtc%d failed panel stacking check %d\n",
  5029. crtc->base.id, rc);
  5030. goto end;
  5031. }
  5032. end:
  5033. kfree(pstates);
  5034. kfree(multirect_plane);
  5035. return rc;
  5036. }
  5037. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  5038. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  5039. struct drm_atomic_state *atomic_state)
  5040. {
  5041. struct drm_crtc_state *state = NULL;
  5042. if (!crtc) {
  5043. SDE_ERROR("invalid crtc\n");
  5044. return -EINVAL;
  5045. }
  5046. state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
  5047. return _sde_crtc_atomic_check(crtc, state);
  5048. }
  5049. #else
  5050. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  5051. struct drm_crtc_state *state)
  5052. {
  5053. if (!crtc) {
  5054. SDE_ERROR("invalid crtc\n");
  5055. return -EINVAL;
  5056. }
  5057. return _sde_crtc_atomic_check(crtc, state);
  5058. }
  5059. #endif
  5060. /**
  5061. * sde_crtc_get_num_datapath - get the number of layermixers active
  5062. * on primary connector
  5063. * @crtc: Pointer to DRM crtc object
  5064. * @virtual_conn: Pointer to DRM connector object of WB in CWB case
  5065. * @crtc_state: Pointer to DRM crtc state
  5066. */
  5067. int sde_crtc_get_num_datapath(struct drm_crtc *crtc,
  5068. struct drm_connector *virtual_conn, struct drm_crtc_state *crtc_state)
  5069. {
  5070. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  5071. struct drm_connector *conn, *primary_conn = NULL;
  5072. struct sde_connector_state *sde_conn_state = NULL;
  5073. struct drm_connector_list_iter conn_iter;
  5074. int num_lm = 0;
  5075. if (!sde_crtc || !virtual_conn || !crtc_state) {
  5076. SDE_DEBUG("Invalid argument\n");
  5077. return 0;
  5078. }
  5079. /* return num_mixers used for primary when available in sde_crtc */
  5080. if (sde_crtc->num_mixers)
  5081. return sde_crtc->num_mixers;
  5082. drm_connector_list_iter_begin(crtc->dev, &conn_iter);
  5083. drm_for_each_connector_iter(conn, &conn_iter) {
  5084. if ((drm_connector_mask(conn) & crtc_state->connector_mask)
  5085. && conn != virtual_conn) {
  5086. sde_conn_state = to_sde_connector_state(conn->state);
  5087. primary_conn = conn;
  5088. break;
  5089. }
  5090. }
  5091. drm_connector_list_iter_end(&conn_iter);
  5092. /* if primary sde_conn_state has mode info available, return num_lm from here */
  5093. if (sde_conn_state)
  5094. num_lm = sde_conn_state->mode_info.topology.num_lm;
  5095. /* if PM resume occurs with CWB enabled, retrieve num_lm from primary dsi panel mode */
  5096. if (primary_conn && !num_lm) {
  5097. num_lm = sde_connector_get_lm_cnt_from_topology(primary_conn,
  5098. &crtc_state->adjusted_mode);
  5099. if (num_lm < 0) {
  5100. SDE_DEBUG("lm cnt fail for conn:%d num_lm:%d\n",
  5101. primary_conn->base.id, num_lm);
  5102. num_lm = 0;
  5103. }
  5104. }
  5105. return num_lm;
  5106. }
  5107. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  5108. {
  5109. struct sde_crtc *sde_crtc;
  5110. int ret;
  5111. if (!crtc) {
  5112. SDE_ERROR("invalid crtc\n");
  5113. return -EINVAL;
  5114. }
  5115. sde_crtc = to_sde_crtc(crtc);
  5116. ret = _sde_crtc_vblank_enable(sde_crtc, en);
  5117. if (ret)
  5118. SDE_ERROR("%s vblank enable failed: %d\n",
  5119. sde_crtc->name, ret);
  5120. return 0;
  5121. }
  5122. static u32 sde_crtc_get_vblank_counter(struct drm_crtc *crtc)
  5123. {
  5124. struct drm_encoder *encoder;
  5125. struct sde_crtc *sde_crtc;
  5126. bool is_built_in;
  5127. u32 vblank_cnt;
  5128. if (!crtc)
  5129. return 0;
  5130. sde_crtc = to_sde_crtc(crtc);
  5131. drm_for_each_encoder_mask(encoder, crtc->dev, sde_crtc->cached_encoder_mask) {
  5132. if (sde_encoder_in_clone_mode(encoder))
  5133. continue;
  5134. is_built_in = sde_encoder_is_built_in_display(encoder);
  5135. vblank_cnt = sde_encoder_get_frame_count(encoder);
  5136. SDE_EVT32(DRMID(crtc), DRMID(encoder), is_built_in, vblank_cnt);
  5137. SDE_DEBUG("crtc:%d enc:%d is_built_in:%d vblank_cnt:%d\n",
  5138. DRMID(crtc), DRMID(encoder), is_built_in, vblank_cnt);
  5139. return vblank_cnt;
  5140. }
  5141. return 0;
  5142. }
  5143. static bool sde_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
  5144. ktime_t *tvblank, bool in_vblank_irq)
  5145. {
  5146. struct drm_encoder *encoder;
  5147. struct sde_crtc *sde_crtc;
  5148. if (!crtc)
  5149. return false;
  5150. sde_crtc = to_sde_crtc(crtc);
  5151. drm_for_each_encoder_mask(encoder, crtc->dev, sde_crtc->cached_encoder_mask) {
  5152. if (sde_encoder_in_clone_mode(encoder))
  5153. continue;
  5154. return sde_encoder_get_vblank_timestamp(encoder, tvblank);
  5155. }
  5156. return false;
  5157. }
  5158. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  5159. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  5160. {
  5161. sde_kms_info_add_keyint(info, "has_dest_scaler",
  5162. catalog->mdp[0].has_dest_scaler);
  5163. sde_kms_info_add_keyint(info, "dest_scaler_count",
  5164. catalog->ds_count);
  5165. if (catalog->ds[0].top) {
  5166. sde_kms_info_add_keyint(info,
  5167. "max_dest_scaler_input_width",
  5168. catalog->ds[0].top->maxinputwidth);
  5169. sde_kms_info_add_keyint(info,
  5170. "max_dest_scaler_output_width",
  5171. catalog->ds[0].top->maxoutputwidth);
  5172. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  5173. catalog->ds[0].top->maxupscale);
  5174. }
  5175. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  5176. msm_property_install_volatile_range(
  5177. &sde_crtc->property_info, "dest_scaler",
  5178. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  5179. msm_property_install_blob(&sde_crtc->property_info,
  5180. "ds_lut_ed", 0,
  5181. CRTC_PROP_DEST_SCALER_LUT_ED);
  5182. msm_property_install_blob(&sde_crtc->property_info,
  5183. "ds_lut_cir", 0,
  5184. CRTC_PROP_DEST_SCALER_LUT_CIR);
  5185. msm_property_install_blob(&sde_crtc->property_info,
  5186. "ds_lut_sep", 0,
  5187. CRTC_PROP_DEST_SCALER_LUT_SEP);
  5188. } else if (catalog->ds[0].features
  5189. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  5190. msm_property_install_volatile_range(
  5191. &sde_crtc->property_info, "dest_scaler",
  5192. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  5193. }
  5194. }
  5195. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  5196. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  5197. struct sde_kms_info *info)
  5198. {
  5199. msm_property_install_range(&sde_crtc->property_info,
  5200. "core_clk", 0x0, 0, U64_MAX,
  5201. sde_kms->perf.max_core_clk_rate,
  5202. CRTC_PROP_CORE_CLK);
  5203. msm_property_install_range(&sde_crtc->property_info,
  5204. "core_ab", 0x0, 0, U64_MAX,
  5205. catalog->perf.max_bw_high * 1000ULL,
  5206. CRTC_PROP_CORE_AB);
  5207. msm_property_install_range(&sde_crtc->property_info,
  5208. "core_ib", 0x0, 0, U64_MAX,
  5209. catalog->perf.max_bw_high * 1000ULL,
  5210. CRTC_PROP_CORE_IB);
  5211. msm_property_install_range(&sde_crtc->property_info,
  5212. "llcc_ab", 0x0, 0, U64_MAX,
  5213. catalog->perf.max_bw_high * 1000ULL,
  5214. CRTC_PROP_LLCC_AB);
  5215. msm_property_install_range(&sde_crtc->property_info,
  5216. "llcc_ib", 0x0, 0, U64_MAX,
  5217. catalog->perf.max_bw_high * 1000ULL,
  5218. CRTC_PROP_LLCC_IB);
  5219. msm_property_install_range(&sde_crtc->property_info,
  5220. "dram_ab", 0x0, 0, U64_MAX,
  5221. catalog->perf.max_bw_high * 1000ULL,
  5222. CRTC_PROP_DRAM_AB);
  5223. msm_property_install_range(&sde_crtc->property_info,
  5224. "dram_ib", 0x0, 0, U64_MAX,
  5225. catalog->perf.max_bw_high * 1000ULL,
  5226. CRTC_PROP_DRAM_IB);
  5227. msm_property_install_range(&sde_crtc->property_info,
  5228. "rot_prefill_bw", 0, 0, U64_MAX,
  5229. catalog->perf.max_bw_high * 1000ULL,
  5230. CRTC_PROP_ROT_PREFILL_BW);
  5231. msm_property_install_range(&sde_crtc->property_info,
  5232. "rot_clk", 0, 0, U64_MAX,
  5233. sde_kms->perf.max_core_clk_rate,
  5234. CRTC_PROP_ROT_CLK);
  5235. if (catalog->perf.max_bw_low)
  5236. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  5237. catalog->perf.max_bw_low * 1000LL);
  5238. if (catalog->perf.max_bw_high)
  5239. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  5240. catalog->perf.max_bw_high * 1000LL);
  5241. if (catalog->perf.min_core_ib)
  5242. sde_kms_info_add_keyint(info, "min_core_ib",
  5243. catalog->perf.min_core_ib * 1000LL);
  5244. if (catalog->perf.min_llcc_ib)
  5245. sde_kms_info_add_keyint(info, "min_llcc_ib",
  5246. catalog->perf.min_llcc_ib * 1000LL);
  5247. if (catalog->perf.min_dram_ib)
  5248. sde_kms_info_add_keyint(info, "min_dram_ib",
  5249. catalog->perf.min_dram_ib * 1000LL);
  5250. if (sde_kms->perf.max_core_clk_rate)
  5251. sde_kms_info_add_keyint(info, "max_mdp_clk",
  5252. sde_kms->perf.max_core_clk_rate);
  5253. }
  5254. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  5255. struct sde_mdss_cfg *catalog)
  5256. {
  5257. sde_kms_info_reset(info);
  5258. sde_kms_info_add_keyint(info, "hw_version", catalog->hw_rev);
  5259. sde_kms_info_add_keyint(info, "max_linewidth",
  5260. catalog->max_mixer_width);
  5261. sde_kms_info_add_keyint(info, "max_blendstages",
  5262. catalog->max_mixer_blendstages);
  5263. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2)
  5264. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  5265. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)
  5266. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  5267. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)
  5268. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  5269. if (catalog->ubwc_rev) {
  5270. sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_rev);
  5271. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  5272. catalog->macrotile_mode);
  5273. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  5274. catalog->mdp[0].highest_bank_bit);
  5275. sde_kms_info_add_keyint(info, "UBWC swizzle",
  5276. catalog->mdp[0].ubwc_swizzle);
  5277. }
  5278. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  5279. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  5280. else
  5281. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  5282. if (sde_is_custom_client()) {
  5283. /* No support for SMART_DMA_V1 yet */
  5284. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  5285. sde_kms_info_add_keystr(info,
  5286. "smart_dma_rev", "smart_dma_v2");
  5287. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  5288. sde_kms_info_add_keystr(info,
  5289. "smart_dma_rev", "smart_dma_v2p5");
  5290. }
  5291. sde_kms_info_add_keyint(info, "has_src_split", test_bit(SDE_FEATURE_SRC_SPLIT,
  5292. catalog->features));
  5293. sde_kms_info_add_keyint(info, "has_hdr", test_bit(SDE_FEATURE_HDR, catalog->features));
  5294. sde_kms_info_add_keyint(info, "has_hdr_plus", test_bit(SDE_FEATURE_HDR_PLUS,
  5295. catalog->features));
  5296. sde_kms_info_add_keyint(info, "skip_inline_rot_threshold",
  5297. test_bit(SDE_FEATURE_INLINE_SKIP_THRESHOLD, catalog->features));
  5298. if (catalog->allowed_dsc_reservation_switch)
  5299. sde_kms_info_add_keyint(info, "allowed_dsc_reservation_switch",
  5300. catalog->allowed_dsc_reservation_switch);
  5301. if (catalog->uidle_cfg.uidle_rev)
  5302. sde_kms_info_add_keyint(info, "has_uidle",
  5303. true);
  5304. sde_kms_info_add_keystr(info, "core_ib_ff",
  5305. catalog->perf.core_ib_ff);
  5306. sde_kms_info_add_keystr(info, "core_clk_ff",
  5307. catalog->perf.core_clk_ff);
  5308. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  5309. catalog->perf.comp_ratio_rt);
  5310. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  5311. catalog->perf.comp_ratio_nrt);
  5312. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  5313. catalog->perf.dest_scale_prefill_lines);
  5314. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  5315. catalog->perf.undersized_prefill_lines);
  5316. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  5317. catalog->perf.macrotile_prefill_lines);
  5318. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  5319. catalog->perf.yuv_nv12_prefill_lines);
  5320. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  5321. catalog->perf.linear_prefill_lines);
  5322. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  5323. catalog->perf.downscaling_prefill_lines);
  5324. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  5325. catalog->perf.xtra_prefill_lines);
  5326. sde_kms_info_add_keyint(info, "amortizable_threshold",
  5327. catalog->perf.amortizable_threshold);
  5328. sde_kms_info_add_keyint(info, "min_prefill_lines",
  5329. catalog->perf.min_prefill_lines);
  5330. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  5331. catalog->perf.num_mnoc_ports);
  5332. sde_kms_info_add_keyint(info, "axi_bus_width",
  5333. catalog->perf.axi_bus_width);
  5334. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  5335. catalog->sui_supported_blendstage);
  5336. if (catalog->ubwc_bw_calc_rev)
  5337. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver", catalog->ubwc_bw_calc_rev);
  5338. }
  5339. /**
  5340. * sde_crtc_install_properties - install all drm properties for crtc
  5341. * @crtc: Pointer to drm crtc structure
  5342. */
  5343. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  5344. struct sde_mdss_cfg *catalog)
  5345. {
  5346. struct sde_crtc *sde_crtc;
  5347. struct sde_kms_info *info;
  5348. struct sde_kms *sde_kms;
  5349. static const struct drm_prop_enum_list e_secure_level[] = {
  5350. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  5351. {SDE_DRM_SEC_ONLY, "sec_only"},
  5352. };
  5353. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  5354. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  5355. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  5356. };
  5357. static const struct drm_prop_enum_list e_dcwb_data_points[] = {
  5358. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  5359. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  5360. {CAPTURE_DEMURA_OUT, "capture_demura_out"},
  5361. };
  5362. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  5363. {IDLE_PC_NONE, "idle_pc_none"},
  5364. {IDLE_PC_ENABLE, "idle_pc_enable"},
  5365. {IDLE_PC_DISABLE, "idle_pc_disable"},
  5366. };
  5367. static const struct drm_prop_enum_list e_cache_state[] = {
  5368. {CACHE_STATE_DISABLED, "cache_state_disabled"},
  5369. {CACHE_STATE_ENABLED, "cache_state_enabled"},
  5370. };
  5371. static const struct drm_prop_enum_list e_vm_req_state[] = {
  5372. {VM_REQ_NONE, "vm_req_none"},
  5373. {VM_REQ_RELEASE, "vm_req_release"},
  5374. {VM_REQ_ACQUIRE, "vm_req_acquire"},
  5375. };
  5376. SDE_DEBUG("\n");
  5377. if (!crtc || !catalog) {
  5378. SDE_ERROR("invalid crtc or catalog\n");
  5379. return;
  5380. }
  5381. sde_crtc = to_sde_crtc(crtc);
  5382. sde_kms = _sde_crtc_get_kms(crtc);
  5383. if (!sde_kms) {
  5384. SDE_ERROR("invalid argument\n");
  5385. return;
  5386. }
  5387. info = vzalloc(sizeof(struct sde_kms_info));
  5388. if (!info) {
  5389. SDE_ERROR("failed to allocate info memory\n");
  5390. return;
  5391. }
  5392. sde_crtc_setup_capabilities_blob(info, catalog);
  5393. msm_property_install_range(&sde_crtc->property_info,
  5394. "input_fence_timeout", 0x0, 0,
  5395. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  5396. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  5397. msm_property_install_volatile_range(&sde_crtc->property_info,
  5398. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  5399. msm_property_install_range(&sde_crtc->property_info,
  5400. "output_fence_offset", 0x0, 0, 1, 0,
  5401. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  5402. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  5403. if (test_bit(SDE_FEATURE_TRUSTED_VM, catalog->features)) {
  5404. int init_idx = sde_in_trusted_vm(sde_kms) ? 1 : 0;
  5405. msm_property_install_enum(&sde_crtc->property_info,
  5406. "vm_request_state", 0x0, 0, e_vm_req_state,
  5407. ARRAY_SIZE(e_vm_req_state), init_idx,
  5408. CRTC_PROP_VM_REQ_STATE);
  5409. }
  5410. if (test_bit(SDE_FEATURE_IDLE_PC, catalog->features))
  5411. msm_property_install_enum(&sde_crtc->property_info,
  5412. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  5413. ARRAY_SIZE(e_idle_pc_state), 0,
  5414. CRTC_PROP_IDLE_PC_STATE);
  5415. if (test_bit(SDE_FEATURE_DEDICATED_CWB, catalog->features))
  5416. msm_property_install_enum(&sde_crtc->property_info,
  5417. "capture_mode", 0, 0, e_dcwb_data_points,
  5418. ARRAY_SIZE(e_dcwb_data_points), 0,
  5419. CRTC_PROP_CAPTURE_OUTPUT);
  5420. else if (test_bit(SDE_FEATURE_CWB, catalog->features))
  5421. msm_property_install_enum(&sde_crtc->property_info,
  5422. "capture_mode", 0, 0, e_cwb_data_points,
  5423. ARRAY_SIZE(e_cwb_data_points), 0,
  5424. CRTC_PROP_CAPTURE_OUTPUT);
  5425. msm_property_install_volatile_range(&sde_crtc->property_info,
  5426. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  5427. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  5428. 0x0, 0, e_secure_level,
  5429. ARRAY_SIZE(e_secure_level), 0,
  5430. CRTC_PROP_SECURITY_LEVEL);
  5431. if (test_bit(SDE_SYS_CACHE_DISP, catalog->sde_sys_cache_type_map))
  5432. msm_property_install_enum(&sde_crtc->property_info, "cache_state",
  5433. 0x0, 0, e_cache_state,
  5434. ARRAY_SIZE(e_cache_state), 0,
  5435. CRTC_PROP_CACHE_STATE);
  5436. if (test_bit(SDE_FEATURE_DIM_LAYER, catalog->features)) {
  5437. msm_property_install_volatile_range(&sde_crtc->property_info,
  5438. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  5439. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  5440. SDE_MAX_DIM_LAYERS);
  5441. }
  5442. if (catalog->mdp[0].has_dest_scaler)
  5443. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  5444. info);
  5445. if (catalog->dspp_count) {
  5446. sde_kms_info_add_keyint(info, "dspp_count",
  5447. catalog->dspp_count);
  5448. if (catalog->rc_count) {
  5449. sde_kms_info_add_keyint(info, "rc_count", catalog->rc_count);
  5450. sde_kms_info_add_keyint(info, "rc_mem_size",
  5451. catalog->dspp[0].sblk->rc.mem_total_size);
  5452. }
  5453. if (catalog->demura_count)
  5454. sde_kms_info_add_keyint(info, "demura_count",
  5455. catalog->demura_count);
  5456. }
  5457. sde_kms_info_add_keyint(info, "dsc_block_count", catalog->dsc_count);
  5458. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  5459. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  5460. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  5461. test_bit(SDE_FEATURE_BASE_LAYER, catalog->features));
  5462. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  5463. info->data, SDE_KMS_INFO_DATALEN(info),
  5464. CRTC_PROP_INFO);
  5465. sde_crtc_install_noise_layer_properties(sde_crtc, catalog, info);
  5466. if (test_bit(SDE_FEATURE_UBWC_STATS, catalog->features))
  5467. msm_property_install_range(&sde_crtc->property_info, "frame_data",
  5468. 0x0, 0, ~0, 0, CRTC_PROP_FRAME_DATA_BUF);
  5469. vfree(info);
  5470. }
  5471. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  5472. const struct drm_crtc_state *state, uint64_t *val)
  5473. {
  5474. struct sde_crtc *sde_crtc;
  5475. struct sde_crtc_state *cstate;
  5476. uint32_t offset;
  5477. bool is_vid = false;
  5478. struct drm_encoder *encoder;
  5479. struct sde_hw_ctl *hw_ctl = NULL;
  5480. static u32 count;
  5481. sde_crtc = to_sde_crtc(crtc);
  5482. cstate = to_sde_crtc_state(state);
  5483. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  5484. if (sde_encoder_check_curr_mode(encoder,
  5485. MSM_DISPLAY_VIDEO_MODE))
  5486. is_vid = true;
  5487. if (is_vid)
  5488. break;
  5489. }
  5490. /*
  5491. * If hw-fence is enabled, find hw_ctl and pass it to sde_fence_create, this will attempt
  5492. * to create a hw-fence for this ctl, whereas if hw_ctl is not passed to sde_fence, this
  5493. * won't use hw-fences for this output-fence.
  5494. */
  5495. if (test_bit(HW_FENCE_OUT_FENCES_ENABLE, sde_crtc->hwfence_features_mask) &&
  5496. (count++ % sde_crtc->hwfence_out_fences_skip))
  5497. hw_ctl = _sde_crtc_get_hw_ctl(crtc);
  5498. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  5499. /*
  5500. * Increment trigger offset for vidoe mode alone as its release fence
  5501. * can be triggered only after the next frame-update. For cmd mode &
  5502. * virtual displays the release fence for the current frame can be
  5503. * triggered right after PP_DONE/WB_DONE interrupt
  5504. */
  5505. if (is_vid)
  5506. offset++;
  5507. /*
  5508. * Hwcomposer now queries the fences using the commit list in atomic
  5509. * commit ioctl. The offset should be set to next timeline
  5510. * which will be incremented during the prepare commit phase
  5511. */
  5512. offset++;
  5513. return sde_fence_create(sde_crtc->output_fence, val, offset, hw_ctl);
  5514. }
  5515. /**
  5516. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  5517. * @crtc: Pointer to drm crtc structure
  5518. * @state: Pointer to drm crtc state structure
  5519. * @property: Pointer to targeted drm property
  5520. * @val: Updated property value
  5521. * @Returns: Zero on success
  5522. */
  5523. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  5524. struct drm_crtc_state *state,
  5525. struct drm_property *property,
  5526. uint64_t val)
  5527. {
  5528. struct sde_crtc *sde_crtc;
  5529. struct sde_crtc_state *cstate;
  5530. int idx, ret;
  5531. uint64_t fence_user_fd;
  5532. uint64_t __user prev_user_fd;
  5533. if (!crtc || !state || !property) {
  5534. SDE_ERROR("invalid argument(s)\n");
  5535. return -EINVAL;
  5536. }
  5537. sde_crtc = to_sde_crtc(crtc);
  5538. cstate = to_sde_crtc_state(state);
  5539. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  5540. /* check with cp property system first */
  5541. ret = sde_cp_crtc_set_property(crtc, state, property, val);
  5542. if (ret != -ENOENT)
  5543. goto exit;
  5544. /* if not handled by cp, check msm_property system */
  5545. ret = msm_property_atomic_set(&sde_crtc->property_info,
  5546. &cstate->property_state, property, val);
  5547. if (ret)
  5548. goto exit;
  5549. idx = msm_property_index(&sde_crtc->property_info, property);
  5550. switch (idx) {
  5551. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  5552. _sde_crtc_set_input_fence_timeout(cstate);
  5553. break;
  5554. case CRTC_PROP_DIM_LAYER_V1:
  5555. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  5556. (void __user *)(uintptr_t)val);
  5557. break;
  5558. case CRTC_PROP_ROI_V1:
  5559. ret = _sde_crtc_set_roi_v1(state,
  5560. (void __user *)(uintptr_t)val);
  5561. break;
  5562. case CRTC_PROP_DEST_SCALER:
  5563. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  5564. (void __user *)(uintptr_t)val);
  5565. break;
  5566. case CRTC_PROP_DEST_SCALER_LUT_ED:
  5567. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  5568. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  5569. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  5570. break;
  5571. case CRTC_PROP_CORE_CLK:
  5572. case CRTC_PROP_CORE_AB:
  5573. case CRTC_PROP_CORE_IB:
  5574. cstate->bw_control = true;
  5575. break;
  5576. case CRTC_PROP_LLCC_AB:
  5577. case CRTC_PROP_LLCC_IB:
  5578. case CRTC_PROP_DRAM_AB:
  5579. case CRTC_PROP_DRAM_IB:
  5580. cstate->bw_control = true;
  5581. cstate->bw_split_vote = true;
  5582. break;
  5583. case CRTC_PROP_OUTPUT_FENCE:
  5584. if (!val)
  5585. goto exit;
  5586. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  5587. sizeof(uint64_t));
  5588. if (ret) {
  5589. SDE_ERROR("copy from user failed rc:%d\n", ret);
  5590. ret = -EFAULT;
  5591. goto exit;
  5592. }
  5593. /*
  5594. * client is expected to reset the property to -1 before
  5595. * requesting for the release fence
  5596. */
  5597. if (prev_user_fd == -1) {
  5598. ret = _sde_crtc_get_output_fence(crtc, state,
  5599. &fence_user_fd);
  5600. if (ret) {
  5601. SDE_ERROR("fence create failed rc:%d\n", ret);
  5602. goto exit;
  5603. }
  5604. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  5605. &fence_user_fd, sizeof(uint64_t));
  5606. if (ret) {
  5607. SDE_ERROR("copy to user failed rc:%d\n", ret);
  5608. put_unused_fd(fence_user_fd);
  5609. ret = -EFAULT;
  5610. goto exit;
  5611. }
  5612. }
  5613. break;
  5614. case CRTC_PROP_NOISE_LAYER_V1:
  5615. _sde_crtc_set_noise_layer(sde_crtc, cstate,
  5616. (void __user *)(uintptr_t)val);
  5617. break;
  5618. case CRTC_PROP_FRAME_DATA_BUF:
  5619. _sde_crtc_set_frame_data_buffers(crtc, cstate, (void __user *)(uintptr_t)val);
  5620. break;
  5621. default:
  5622. /* nothing to do */
  5623. break;
  5624. }
  5625. exit:
  5626. if (ret) {
  5627. if (ret != -EPERM)
  5628. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  5629. crtc->name, DRMID(property),
  5630. property->name, ret);
  5631. else
  5632. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  5633. crtc->name, DRMID(property),
  5634. property->name, ret);
  5635. } else {
  5636. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  5637. property->base.id, val);
  5638. }
  5639. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  5640. return ret;
  5641. }
  5642. static void sde_crtc_update_line_time(struct drm_crtc *crtc)
  5643. {
  5644. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  5645. struct drm_encoder *encoder;
  5646. u32 min_transfer_time = 0, updated_fps = 0;
  5647. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  5648. if (sde_encoder_check_curr_mode(encoder, MSM_DISPLAY_CMD_MODE))
  5649. sde_encoder_get_transfer_time(encoder, &min_transfer_time);
  5650. }
  5651. if (min_transfer_time) {
  5652. /* get fps by doing 1000 ms / transfer_time */
  5653. updated_fps = DIV_ROUND_UP(1000000, min_transfer_time);
  5654. /* get line time by doing 1000ns / (fps * vactive) */
  5655. sde_crtc->line_time_in_ns = DIV_ROUND_UP(1000000000,
  5656. updated_fps * crtc->mode.vdisplay);
  5657. } else {
  5658. /* get line time by doing 1000ns / (fps * vtotal) */
  5659. sde_crtc->line_time_in_ns = DIV_ROUND_UP(1000000000,
  5660. drm_mode_vrefresh(&crtc->mode) * crtc->mode.vtotal);
  5661. }
  5662. SDE_EVT32(min_transfer_time, updated_fps, crtc->mode.vdisplay, crtc->mode.vtotal,
  5663. drm_mode_vrefresh(&crtc->mode), sde_crtc->line_time_in_ns);
  5664. }
  5665. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  5666. {
  5667. struct drm_plane *plane;
  5668. struct drm_plane_state *state;
  5669. struct sde_plane_state *pstate;
  5670. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5671. state = plane->state;
  5672. if (!state)
  5673. continue;
  5674. pstate = to_sde_plane_state(state);
  5675. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  5676. }
  5677. sde_crtc_update_line_time(crtc);
  5678. }
  5679. /**
  5680. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  5681. * @crtc: Pointer to drm crtc structure
  5682. * @state: Pointer to drm crtc state structure
  5683. * @property: Pointer to targeted drm property
  5684. * @val: Pointer to variable for receiving property value
  5685. * @Returns: Zero on success
  5686. */
  5687. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  5688. const struct drm_crtc_state *state,
  5689. struct drm_property *property,
  5690. uint64_t *val)
  5691. {
  5692. struct sde_crtc *sde_crtc;
  5693. struct sde_crtc_state *cstate;
  5694. int ret = -EINVAL, i;
  5695. if (!crtc || !state) {
  5696. SDE_ERROR("invalid argument(s)\n");
  5697. goto end;
  5698. }
  5699. sde_crtc = to_sde_crtc(crtc);
  5700. cstate = to_sde_crtc_state(state);
  5701. i = msm_property_index(&sde_crtc->property_info, property);
  5702. if (i == CRTC_PROP_OUTPUT_FENCE) {
  5703. *val = ~0;
  5704. ret = 0;
  5705. } else {
  5706. ret = msm_property_atomic_get(&sde_crtc->property_info,
  5707. &cstate->property_state, property, val);
  5708. if (ret)
  5709. ret = sde_cp_crtc_get_property(crtc, property, val);
  5710. }
  5711. if (ret)
  5712. DRM_ERROR("get property failed\n");
  5713. end:
  5714. return ret;
  5715. }
  5716. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  5717. struct drm_crtc_state *crtc_state)
  5718. {
  5719. struct sde_crtc *sde_crtc;
  5720. struct sde_crtc_state *cstate;
  5721. struct drm_property *drm_prop;
  5722. enum msm_mdp_crtc_property prop_idx;
  5723. if (!crtc || !crtc_state) {
  5724. SDE_ERROR("invalid params\n");
  5725. return -EINVAL;
  5726. }
  5727. sde_crtc = to_sde_crtc(crtc);
  5728. cstate = to_sde_crtc_state(crtc_state);
  5729. sde_cp_crtc_clear(crtc);
  5730. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  5731. uint64_t val = cstate->property_values[prop_idx].value;
  5732. uint64_t def;
  5733. int ret;
  5734. drm_prop = msm_property_index_to_drm_property(
  5735. &sde_crtc->property_info, prop_idx);
  5736. if (!drm_prop) {
  5737. /* not all props will be installed, based on caps */
  5738. SDE_DEBUG("%s: invalid property index %d\n",
  5739. sde_crtc->name, prop_idx);
  5740. continue;
  5741. }
  5742. def = msm_property_get_default(&sde_crtc->property_info,
  5743. prop_idx);
  5744. if (val == def)
  5745. continue;
  5746. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  5747. sde_crtc->name, drm_prop->name, prop_idx, val,
  5748. def);
  5749. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  5750. def);
  5751. if (ret) {
  5752. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  5753. sde_crtc->name, prop_idx, ret);
  5754. continue;
  5755. }
  5756. }
  5757. /* disable clk and bw control until clk & bw properties are set */
  5758. cstate->bw_control = false;
  5759. cstate->bw_split_vote = false;
  5760. return 0;
  5761. }
  5762. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  5763. {
  5764. struct sde_crtc *sde_crtc;
  5765. struct sde_crtc_mixer *m;
  5766. int i;
  5767. if (!crtc) {
  5768. SDE_ERROR("invalid argument\n");
  5769. return;
  5770. }
  5771. sde_crtc = to_sde_crtc(crtc);
  5772. sde_crtc->misr_enable_sui = enable;
  5773. sde_crtc->misr_frame_count = frame_count;
  5774. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  5775. m = &sde_crtc->mixers[i];
  5776. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  5777. continue;
  5778. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  5779. }
  5780. }
  5781. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  5782. struct sde_crtc_misr_info *crtc_misr_info)
  5783. {
  5784. struct sde_crtc *sde_crtc;
  5785. struct sde_kms *sde_kms;
  5786. if (!crtc_misr_info) {
  5787. SDE_ERROR("invalid misr info\n");
  5788. return;
  5789. }
  5790. crtc_misr_info->misr_enable = false;
  5791. crtc_misr_info->misr_frame_count = 0;
  5792. if (!crtc) {
  5793. SDE_ERROR("invalid crtc\n");
  5794. return;
  5795. }
  5796. sde_kms = _sde_crtc_get_kms(crtc);
  5797. if (!sde_kms) {
  5798. SDE_ERROR("invalid sde_kms\n");
  5799. return;
  5800. }
  5801. if (sde_kms_is_secure_session_inprogress(sde_kms))
  5802. return;
  5803. sde_crtc = to_sde_crtc(crtc);
  5804. crtc_misr_info->misr_enable =
  5805. sde_crtc->misr_enable_debugfs ? true : false;
  5806. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  5807. }
  5808. #if IS_ENABLED(CONFIG_DEBUG_FS)
  5809. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  5810. {
  5811. struct sde_crtc *sde_crtc;
  5812. struct sde_plane_state *pstate = NULL;
  5813. struct sde_crtc_mixer *m;
  5814. struct drm_crtc *crtc;
  5815. struct drm_plane *plane;
  5816. struct drm_display_mode *mode;
  5817. struct drm_framebuffer *fb;
  5818. struct drm_plane_state *state;
  5819. struct sde_crtc_state *cstate;
  5820. int i, mixer_width, mixer_height;
  5821. if (!s || !s->private)
  5822. return -EINVAL;
  5823. sde_crtc = s->private;
  5824. crtc = &sde_crtc->base;
  5825. cstate = to_sde_crtc_state(crtc->state);
  5826. mutex_lock(&sde_crtc->crtc_lock);
  5827. mode = &crtc->state->adjusted_mode;
  5828. sde_crtc_get_mixer_resolution(crtc, crtc->state, mode, &mixer_width, &mixer_height);
  5829. seq_printf(s, "crtc:%d width:%d height:%d\n", DRMID(crtc),
  5830. mixer_width * sde_crtc->num_mixers, mixer_height);
  5831. seq_puts(s, "\n");
  5832. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  5833. m = &sde_crtc->mixers[i];
  5834. if (!m->hw_lm)
  5835. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  5836. else if (!m->hw_ctl)
  5837. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  5838. else
  5839. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  5840. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  5841. mixer_width, mixer_height);
  5842. }
  5843. seq_puts(s, "\n");
  5844. for (i = 0; i < cstate->num_dim_layers; i++) {
  5845. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  5846. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  5847. i, dim_layer->stage, dim_layer->flags);
  5848. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  5849. dim_layer->rect.x, dim_layer->rect.y,
  5850. dim_layer->rect.w, dim_layer->rect.h);
  5851. seq_printf(s,
  5852. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  5853. dim_layer->color_fill.color_0,
  5854. dim_layer->color_fill.color_1,
  5855. dim_layer->color_fill.color_2,
  5856. dim_layer->color_fill.color_3);
  5857. seq_puts(s, "\n");
  5858. }
  5859. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5860. pstate = to_sde_plane_state(plane->state);
  5861. state = plane->state;
  5862. if (!pstate || !state)
  5863. continue;
  5864. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  5865. plane->base.id, pstate->stage, pstate->rotation);
  5866. if (plane->state->fb) {
  5867. fb = plane->state->fb;
  5868. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  5869. fb->base.id, (char *) &fb->format->format,
  5870. fb->width, fb->height);
  5871. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  5872. seq_printf(s, "cpp[%d]:%u ",
  5873. i, fb->format->cpp[i]);
  5874. seq_puts(s, "\n\t");
  5875. seq_printf(s, "modifier:%8llu ", fb->modifier);
  5876. seq_puts(s, "\n");
  5877. seq_puts(s, "\t");
  5878. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  5879. seq_printf(s, "pitches[%d]:%8u ", i,
  5880. fb->pitches[i]);
  5881. seq_puts(s, "\n");
  5882. seq_puts(s, "\t");
  5883. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  5884. seq_printf(s, "offsets[%d]:%8u ", i,
  5885. fb->offsets[i]);
  5886. seq_puts(s, "\n");
  5887. }
  5888. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  5889. state->src_x >> 16, state->src_y >> 16,
  5890. state->src_w >> 16, state->src_h >> 16);
  5891. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  5892. state->crtc_x, state->crtc_y, state->crtc_w,
  5893. state->crtc_h);
  5894. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  5895. pstate->multirect_mode, pstate->multirect_index);
  5896. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  5897. pstate->excl_rect.x, pstate->excl_rect.y,
  5898. pstate->excl_rect.w, pstate->excl_rect.h);
  5899. seq_puts(s, "\n");
  5900. }
  5901. if (sde_crtc->vblank_cb_count) {
  5902. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  5903. u32 diff_ms = ktime_to_ms(diff);
  5904. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  5905. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  5906. seq_printf(s,
  5907. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  5908. fps, sde_crtc->vblank_cb_count,
  5909. ktime_to_ms(diff), sde_crtc->play_count);
  5910. /* reset time & count for next measurement */
  5911. sde_crtc->vblank_cb_count = 0;
  5912. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  5913. }
  5914. mutex_unlock(&sde_crtc->crtc_lock);
  5915. return 0;
  5916. }
  5917. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  5918. {
  5919. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  5920. }
  5921. static ssize_t _sde_debugfs_hw_fence_features_mask_wr(struct file *file,
  5922. const char __user *user_buf, size_t count, loff_t *ppos)
  5923. {
  5924. struct sde_crtc *sde_crtc;
  5925. u32 bit, enable;
  5926. char buf[10];
  5927. if (!file || !file->private_data)
  5928. return -EINVAL;
  5929. if (count >= sizeof(buf))
  5930. return -EINVAL;
  5931. if (copy_from_user(buf, user_buf, count)) {
  5932. SDE_ERROR("buffer copy failed\n");
  5933. return -EINVAL;
  5934. }
  5935. buf[count] = 0; /* end of string */
  5936. sde_crtc = file->private_data;
  5937. if (sscanf(buf, "%u %u", &bit, &enable) != 2) {
  5938. SDE_ERROR("incorrect usage: expected 2 parameters, bit and enable\n");
  5939. return -EINVAL;
  5940. }
  5941. if (enable)
  5942. set_bit(bit, sde_crtc->hwfence_features_mask);
  5943. else
  5944. clear_bit(bit, sde_crtc->hwfence_features_mask);
  5945. return count;
  5946. }
  5947. static ssize_t _sde_debugfs_hw_fence_features_mask_rd(struct file *file,
  5948. char __user *user_buff, size_t count, loff_t *ppos)
  5949. {
  5950. struct sde_crtc *sde_crtc;
  5951. ssize_t len = 0;
  5952. char buf[256] = {'\0'};
  5953. int i;
  5954. if (*ppos)
  5955. return 0;
  5956. if (!file || !file->private_data)
  5957. return -EINVAL;
  5958. sde_crtc = file->private_data;
  5959. for (i = HW_FENCE_OUT_FENCES_ENABLE; i < HW_FENCE_FEATURES_MAX; i++) {
  5960. len += scnprintf(buf + len, 256 - len,
  5961. "bit %d: %d\n", i, test_bit(i, sde_crtc->hwfence_features_mask));
  5962. }
  5963. if (count <= len)
  5964. return 0;
  5965. if (copy_to_user(user_buff, buf, len))
  5966. return -EFAULT;
  5967. *ppos += len; /* increase offset */
  5968. return len;
  5969. }
  5970. static ssize_t _sde_crtc_misr_setup(struct file *file,
  5971. const char __user *user_buf, size_t count, loff_t *ppos)
  5972. {
  5973. struct drm_crtc *crtc;
  5974. struct sde_crtc *sde_crtc;
  5975. char buf[MISR_BUFF_SIZE + 1];
  5976. u32 frame_count, enable;
  5977. size_t buff_copy;
  5978. struct sde_kms *sde_kms;
  5979. if (!file || !file->private_data)
  5980. return -EINVAL;
  5981. sde_crtc = file->private_data;
  5982. crtc = &sde_crtc->base;
  5983. sde_kms = _sde_crtc_get_kms(crtc);
  5984. if (!sde_kms) {
  5985. SDE_ERROR("invalid sde_kms\n");
  5986. return -EINVAL;
  5987. }
  5988. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  5989. if (copy_from_user(buf, user_buf, buff_copy)) {
  5990. SDE_ERROR("buffer copy failed\n");
  5991. return -EINVAL;
  5992. }
  5993. buf[buff_copy] = 0; /* end of string */
  5994. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  5995. return -EINVAL;
  5996. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  5997. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  5998. DRMID(crtc));
  5999. return -EINVAL;
  6000. }
  6001. sde_crtc->misr_enable_debugfs = enable;
  6002. sde_crtc->misr_frame_count = frame_count;
  6003. sde_crtc->misr_reconfigure = true;
  6004. return count;
  6005. }
  6006. static ssize_t _sde_crtc_misr_read(struct file *file,
  6007. char __user *user_buff, size_t count, loff_t *ppos)
  6008. {
  6009. struct drm_crtc *crtc;
  6010. struct sde_crtc *sde_crtc;
  6011. struct sde_kms *sde_kms;
  6012. struct sde_crtc_mixer *m;
  6013. int i = 0, rc;
  6014. ssize_t len = 0;
  6015. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  6016. if (*ppos)
  6017. return 0;
  6018. if (!file || !file->private_data)
  6019. return -EINVAL;
  6020. sde_crtc = file->private_data;
  6021. crtc = &sde_crtc->base;
  6022. sde_kms = _sde_crtc_get_kms(crtc);
  6023. if (!sde_kms)
  6024. return -EINVAL;
  6025. rc = pm_runtime_resume_and_get(crtc->dev->dev);
  6026. if (rc < 0) {
  6027. SDE_ERROR("failed to enable power resource %d\n", rc);
  6028. return rc;
  6029. }
  6030. sde_vm_lock(sde_kms);
  6031. if (!sde_vm_owns_hw(sde_kms)) {
  6032. SDE_DEBUG("op not supported due to HW unavailability\n");
  6033. rc = -EOPNOTSUPP;
  6034. goto end;
  6035. }
  6036. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  6037. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  6038. rc = -EOPNOTSUPP;
  6039. goto end;
  6040. }
  6041. if (!sde_crtc->misr_enable_debugfs) {
  6042. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  6043. "disabled\n");
  6044. goto buff_check;
  6045. }
  6046. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  6047. u32 misr_value = 0;
  6048. m = &sde_crtc->mixers[i];
  6049. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  6050. if (!m->hw_lm || !m->hw_lm->cap->dummy_mixer) {
  6051. len += scnprintf(buf + len, MISR_BUFF_SIZE - len, "invalid\n");
  6052. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  6053. }
  6054. continue;
  6055. }
  6056. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  6057. if (rc) {
  6058. len += scnprintf(buf + len, MISR_BUFF_SIZE - len, "invalid\n");
  6059. SDE_ERROR("crtc:%d failed to collect misr %d\n", DRMID(crtc), rc);
  6060. continue;
  6061. } else {
  6062. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  6063. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  6064. len += scnprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n", misr_value);
  6065. }
  6066. }
  6067. buff_check:
  6068. if (count <= len) {
  6069. len = 0;
  6070. goto end;
  6071. }
  6072. if (copy_to_user(user_buff, buf, len)) {
  6073. len = -EFAULT;
  6074. goto end;
  6075. }
  6076. *ppos += len; /* increase offset */
  6077. end:
  6078. sde_vm_unlock(sde_kms);
  6079. pm_runtime_put_sync(crtc->dev->dev);
  6080. return len;
  6081. }
  6082. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  6083. static int __prefix ## _open(struct inode *inode, struct file *file) \
  6084. { \
  6085. return single_open(file, __prefix ## _show, inode->i_private); \
  6086. } \
  6087. static const struct file_operations __prefix ## _fops = { \
  6088. .owner = THIS_MODULE, \
  6089. .open = __prefix ## _open, \
  6090. .release = single_release, \
  6091. .read = seq_read, \
  6092. .llseek = seq_lseek, \
  6093. }
  6094. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  6095. {
  6096. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  6097. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  6098. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  6099. int i;
  6100. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  6101. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  6102. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  6103. crtc->state));
  6104. seq_printf(s, "core_clk_rate: %llu\n",
  6105. sde_crtc->cur_perf.core_clk_rate);
  6106. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  6107. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  6108. seq_printf(s, "bw_ctl[%s]: %llu\n",
  6109. sde_power_handle_get_dbus_name(i),
  6110. sde_crtc->cur_perf.bw_ctl[i]);
  6111. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  6112. sde_power_handle_get_dbus_name(i),
  6113. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  6114. }
  6115. return 0;
  6116. }
  6117. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  6118. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  6119. {
  6120. struct drm_crtc *crtc;
  6121. struct drm_plane *plane;
  6122. struct drm_connector *conn;
  6123. struct drm_mode_object *drm_obj;
  6124. struct sde_crtc *sde_crtc;
  6125. struct sde_crtc_state *cstate;
  6126. struct sde_fence_context *ctx;
  6127. struct drm_connector_list_iter conn_iter;
  6128. struct drm_device *dev;
  6129. if (!s || !s->private)
  6130. return -EINVAL;
  6131. sde_crtc = s->private;
  6132. crtc = &sde_crtc->base;
  6133. dev = crtc->dev;
  6134. cstate = to_sde_crtc_state(crtc->state);
  6135. if (!sde_crtc->kickoff_in_progress)
  6136. goto skip_input_fence;
  6137. /* Dump input fence info */
  6138. seq_puts(s, "===Input fence===\n");
  6139. drm_atomic_crtc_for_each_plane(plane, crtc) {
  6140. struct sde_plane_state *pstate;
  6141. struct dma_fence *fence;
  6142. pstate = to_sde_plane_state(plane->state);
  6143. if (!pstate)
  6144. continue;
  6145. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  6146. pstate->stage);
  6147. SDE_EVT32(DRMID(crtc), plane->base.id, pstate->input_fence);
  6148. if (pstate->input_fence) {
  6149. rcu_read_lock();
  6150. fence = dma_fence_get_rcu(pstate->input_fence);
  6151. rcu_read_unlock();
  6152. if (fence) {
  6153. sde_fence_list_dump(fence, &s);
  6154. dma_fence_put(fence);
  6155. }
  6156. }
  6157. }
  6158. skip_input_fence:
  6159. /* Dump release fence info */
  6160. seq_puts(s, "\n");
  6161. seq_puts(s, "===Release fence===\n");
  6162. ctx = sde_crtc->output_fence;
  6163. drm_obj = &crtc->base;
  6164. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  6165. seq_puts(s, "\n");
  6166. /* Dump retire fence info */
  6167. seq_puts(s, "===Retire fence===\n");
  6168. drm_connector_list_iter_begin(dev, &conn_iter);
  6169. drm_for_each_connector_iter(conn, &conn_iter)
  6170. if (conn->state && conn->state->crtc == crtc &&
  6171. cstate->num_connectors < MAX_CONNECTORS) {
  6172. struct sde_connector *c_conn;
  6173. c_conn = to_sde_connector(conn);
  6174. ctx = c_conn->retire_fence;
  6175. drm_obj = &conn->base;
  6176. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  6177. }
  6178. drm_connector_list_iter_end(&conn_iter);
  6179. seq_puts(s, "\n");
  6180. return 0;
  6181. }
  6182. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  6183. {
  6184. return single_open(file, _sde_debugfs_fence_status_show,
  6185. inode->i_private);
  6186. }
  6187. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  6188. {
  6189. struct sde_crtc *sde_crtc;
  6190. struct sde_kms *sde_kms;
  6191. static const struct file_operations debugfs_status_fops = {
  6192. .open = _sde_debugfs_status_open,
  6193. .read = seq_read,
  6194. .llseek = seq_lseek,
  6195. .release = single_release,
  6196. };
  6197. static const struct file_operations debugfs_misr_fops = {
  6198. .open = simple_open,
  6199. .read = _sde_crtc_misr_read,
  6200. .write = _sde_crtc_misr_setup,
  6201. };
  6202. static const struct file_operations debugfs_fps_fops = {
  6203. .open = _sde_debugfs_fps_status,
  6204. .read = seq_read,
  6205. };
  6206. static const struct file_operations debugfs_fence_fops = {
  6207. .open = _sde_debugfs_fence_status,
  6208. .read = seq_read,
  6209. };
  6210. static const struct file_operations debugfs_hw_fence_features_fops = {
  6211. .open = simple_open,
  6212. .read = _sde_debugfs_hw_fence_features_mask_rd,
  6213. .write = _sde_debugfs_hw_fence_features_mask_wr,
  6214. };
  6215. if (!crtc)
  6216. return -EINVAL;
  6217. sde_crtc = to_sde_crtc(crtc);
  6218. sde_kms = _sde_crtc_get_kms(crtc);
  6219. if (!sde_kms)
  6220. return -EINVAL;
  6221. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  6222. crtc->dev->primary->debugfs_root);
  6223. if (!sde_crtc->debugfs_root)
  6224. return -ENOMEM;
  6225. /* don't error check these */
  6226. debugfs_create_file("status", 0400,
  6227. sde_crtc->debugfs_root,
  6228. sde_crtc, &debugfs_status_fops);
  6229. debugfs_create_file("state", 0400,
  6230. sde_crtc->debugfs_root,
  6231. &sde_crtc->base,
  6232. &sde_crtc_debugfs_state_fops);
  6233. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  6234. sde_crtc, &debugfs_misr_fops);
  6235. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  6236. sde_crtc, &debugfs_fps_fops);
  6237. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  6238. sde_crtc, &debugfs_fence_fops);
  6239. if (sde_kms->catalog->hw_fence_rev) {
  6240. debugfs_create_file("hwfence_features_mask", 0600, sde_crtc->debugfs_root,
  6241. &sde_crtc->base, &debugfs_hw_fence_features_fops);
  6242. debugfs_create_u32("hwfence_out_fences_skip", 0600, sde_crtc->debugfs_root,
  6243. &sde_crtc->hwfence_out_fences_skip);
  6244. }
  6245. return 0;
  6246. }
  6247. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  6248. {
  6249. struct sde_crtc *sde_crtc;
  6250. if (!crtc)
  6251. return;
  6252. sde_crtc = to_sde_crtc(crtc);
  6253. debugfs_remove_recursive(sde_crtc->debugfs_root);
  6254. }
  6255. #else
  6256. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  6257. {
  6258. return 0;
  6259. }
  6260. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  6261. {
  6262. }
  6263. #endif /* CONFIG_DEBUG_FS */
  6264. static void vblank_ctrl_worker(struct kthread_work *work)
  6265. {
  6266. struct vblank_work *cur_work = container_of(work,
  6267. struct vblank_work, work);
  6268. struct msm_drm_private *priv = cur_work->priv;
  6269. sde_crtc_vblank(priv->crtcs[cur_work->crtc_id], cur_work->enable);
  6270. kfree(cur_work);
  6271. }
  6272. static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
  6273. int crtc_id, bool enable)
  6274. {
  6275. struct vblank_work *cur_work;
  6276. struct drm_crtc *crtc;
  6277. struct kthread_worker *worker;
  6278. if (!priv || crtc_id >= priv->num_crtcs)
  6279. return -EINVAL;
  6280. cur_work = kzalloc(sizeof(*cur_work), GFP_ATOMIC);
  6281. if (!cur_work)
  6282. return -ENOMEM;
  6283. crtc = priv->crtcs[crtc_id];
  6284. kthread_init_work(&cur_work->work, vblank_ctrl_worker);
  6285. cur_work->crtc_id = crtc_id;
  6286. cur_work->enable = enable;
  6287. cur_work->priv = priv;
  6288. worker = &priv->event_thread[crtc_id].worker;
  6289. kthread_queue_work(worker, &cur_work->work);
  6290. return 0;
  6291. }
  6292. static int sde_crtc_enable_vblank(struct drm_crtc *crtc)
  6293. {
  6294. struct drm_device *dev = crtc->dev;
  6295. unsigned int pipe = crtc->index;
  6296. struct msm_drm_private *priv = dev->dev_private;
  6297. struct msm_kms *kms = priv->kms;
  6298. if (!kms)
  6299. return -ENXIO;
  6300. DBG("dev=%pK, crtc=%u", dev, pipe);
  6301. return vblank_ctrl_queue_work(priv, pipe, true);
  6302. }
  6303. static void sde_crtc_disable_vblank(struct drm_crtc *crtc)
  6304. {
  6305. struct drm_device *dev = crtc->dev;
  6306. unsigned int pipe = crtc->index;
  6307. struct msm_drm_private *priv = dev->dev_private;
  6308. struct msm_kms *kms = priv->kms;
  6309. if (!kms)
  6310. return;
  6311. DBG("dev=%pK, crtc=%u", dev, pipe);
  6312. vblank_ctrl_queue_work(priv, pipe, false);
  6313. }
  6314. static int sde_crtc_late_register(struct drm_crtc *crtc)
  6315. {
  6316. return _sde_crtc_init_debugfs(crtc);
  6317. }
  6318. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  6319. {
  6320. _sde_crtc_destroy_debugfs(crtc);
  6321. }
  6322. static const struct drm_crtc_funcs sde_crtc_funcs = {
  6323. .set_config = drm_atomic_helper_set_config,
  6324. .destroy = sde_crtc_destroy,
  6325. .enable_vblank = sde_crtc_enable_vblank,
  6326. .disable_vblank = sde_crtc_disable_vblank,
  6327. .page_flip = drm_atomic_helper_page_flip,
  6328. .atomic_set_property = sde_crtc_atomic_set_property,
  6329. .atomic_get_property = sde_crtc_atomic_get_property,
  6330. .reset = sde_crtc_reset,
  6331. .atomic_duplicate_state = sde_crtc_duplicate_state,
  6332. .atomic_destroy_state = sde_crtc_destroy_state,
  6333. .late_register = sde_crtc_late_register,
  6334. .early_unregister = sde_crtc_early_unregister,
  6335. };
  6336. static const struct drm_crtc_funcs sde_crtc_funcs_v1 = {
  6337. .set_config = drm_atomic_helper_set_config,
  6338. .destroy = sde_crtc_destroy,
  6339. .enable_vblank = sde_crtc_enable_vblank,
  6340. .disable_vblank = sde_crtc_disable_vblank,
  6341. .page_flip = drm_atomic_helper_page_flip,
  6342. .atomic_set_property = sde_crtc_atomic_set_property,
  6343. .atomic_get_property = sde_crtc_atomic_get_property,
  6344. .reset = sde_crtc_reset,
  6345. .atomic_duplicate_state = sde_crtc_duplicate_state,
  6346. .atomic_destroy_state = sde_crtc_destroy_state,
  6347. .late_register = sde_crtc_late_register,
  6348. .early_unregister = sde_crtc_early_unregister,
  6349. .get_vblank_timestamp = sde_crtc_get_vblank_timestamp,
  6350. .get_vblank_counter = sde_crtc_get_vblank_counter,
  6351. };
  6352. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  6353. .mode_fixup = sde_crtc_mode_fixup,
  6354. .disable = sde_crtc_disable,
  6355. .atomic_enable = sde_crtc_enable,
  6356. .atomic_check = sde_crtc_atomic_check,
  6357. .atomic_begin = sde_crtc_atomic_begin,
  6358. .atomic_flush = sde_crtc_atomic_flush,
  6359. };
  6360. static void _sde_crtc_event_cb(struct kthread_work *work)
  6361. {
  6362. struct sde_crtc_event *event;
  6363. struct sde_crtc *sde_crtc;
  6364. unsigned long irq_flags;
  6365. if (!work) {
  6366. SDE_ERROR("invalid work item\n");
  6367. return;
  6368. }
  6369. event = container_of(work, struct sde_crtc_event, kt_work);
  6370. /* set sde_crtc to NULL for static work structures */
  6371. sde_crtc = event->sde_crtc;
  6372. if (!sde_crtc)
  6373. return;
  6374. if (event->cb_func)
  6375. event->cb_func(&sde_crtc->base, event->usr);
  6376. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  6377. list_add_tail(&event->list, &sde_crtc->event_free_list);
  6378. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  6379. }
  6380. int sde_crtc_event_queue(struct drm_crtc *crtc,
  6381. void (*func)(struct drm_crtc *crtc, void *usr),
  6382. void *usr, bool color_processing_event)
  6383. {
  6384. unsigned long irq_flags;
  6385. struct sde_crtc *sde_crtc;
  6386. struct msm_drm_private *priv;
  6387. struct sde_crtc_event *event = NULL;
  6388. u32 crtc_id;
  6389. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  6390. SDE_ERROR("invalid parameters\n");
  6391. return -EINVAL;
  6392. }
  6393. sde_crtc = to_sde_crtc(crtc);
  6394. priv = crtc->dev->dev_private;
  6395. crtc_id = drm_crtc_index(crtc);
  6396. /*
  6397. * Obtain an event struct from the private cache. This event
  6398. * queue may be called from ISR contexts, so use a private
  6399. * cache to avoid calling any memory allocation functions.
  6400. */
  6401. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  6402. if (!list_empty(&sde_crtc->event_free_list)) {
  6403. event = list_first_entry(&sde_crtc->event_free_list,
  6404. struct sde_crtc_event, list);
  6405. list_del_init(&event->list);
  6406. }
  6407. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  6408. if (!event)
  6409. return -ENOMEM;
  6410. /* populate event node */
  6411. event->sde_crtc = sde_crtc;
  6412. event->cb_func = func;
  6413. event->usr = usr;
  6414. /* queue new event request */
  6415. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  6416. if (color_processing_event)
  6417. kthread_queue_work(&priv->pp_event_worker,
  6418. &event->kt_work);
  6419. else
  6420. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  6421. &event->kt_work);
  6422. return 0;
  6423. }
  6424. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  6425. {
  6426. int i, rc = 0;
  6427. if (!sde_crtc) {
  6428. SDE_ERROR("invalid crtc\n");
  6429. return -EINVAL;
  6430. }
  6431. spin_lock_init(&sde_crtc->event_lock);
  6432. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  6433. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  6434. list_add_tail(&sde_crtc->event_cache[i].list,
  6435. &sde_crtc->event_free_list);
  6436. return rc;
  6437. }
  6438. void sde_crtc_static_img_control(struct drm_crtc *crtc,
  6439. enum sde_sys_cache_state state,
  6440. bool is_vidmode)
  6441. {
  6442. struct drm_plane *plane;
  6443. struct sde_crtc *sde_crtc;
  6444. struct sde_kms *sde_kms;
  6445. if (!crtc || !crtc->dev)
  6446. return;
  6447. sde_kms = _sde_crtc_get_kms(crtc);
  6448. if (!sde_kms || !sde_kms->catalog) {
  6449. SDE_ERROR("invalid params\n");
  6450. return;
  6451. }
  6452. if (!test_bit(SDE_SYS_CACHE_DISP, sde_kms->catalog->sde_sys_cache_type_map)) {
  6453. SDE_DEBUG("DISP syscache not supported\n");
  6454. return;
  6455. }
  6456. sde_crtc = to_sde_crtc(crtc);
  6457. if (sde_crtc->cache_state == state)
  6458. return;
  6459. switch (state) {
  6460. case CACHE_STATE_NORMAL:
  6461. if (sde_crtc->cache_state == CACHE_STATE_DISABLED
  6462. && !is_vidmode)
  6463. return;
  6464. kthread_cancel_delayed_work_sync(
  6465. &sde_crtc->static_cache_read_work);
  6466. break;
  6467. case CACHE_STATE_FRAME_WRITE:
  6468. if (sde_crtc->cache_state != CACHE_STATE_NORMAL)
  6469. return;
  6470. break;
  6471. case CACHE_STATE_FRAME_READ:
  6472. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  6473. return;
  6474. break;
  6475. case CACHE_STATE_DISABLED:
  6476. break;
  6477. default:
  6478. return;
  6479. }
  6480. if (test_bit(SDE_SYS_CACHE_DISP_1, sde_kms->catalog->sde_sys_cache_type_map)) {
  6481. if (state == CACHE_STATE_FRAME_WRITE)
  6482. sde_crtc->cache_type = (sde_crtc->cache_type == SDE_SYS_CACHE_DISP) ?
  6483. SDE_SYS_CACHE_DISP_1 : SDE_SYS_CACHE_DISP;
  6484. } else {
  6485. sde_crtc->cache_type = SDE_SYS_CACHE_DISP;
  6486. }
  6487. SDE_EVT32(DRMID(crtc), state, sde_crtc->cache_state, sde_crtc->cache_type);
  6488. sde_crtc->cache_state = state;
  6489. drm_atomic_crtc_for_each_plane(plane, crtc)
  6490. sde_plane_static_img_control(plane, sde_crtc->cache_state, sde_crtc->cache_type);
  6491. }
  6492. /*
  6493. * __sde_crtc_static_cache_read_work - transition to cache read
  6494. */
  6495. void __sde_crtc_static_cache_read_work(struct kthread_work *work)
  6496. {
  6497. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  6498. static_cache_read_work.work);
  6499. struct drm_crtc *crtc = &sde_crtc->base;
  6500. struct sde_hw_ctl *ctl = sde_crtc->mixers[0].hw_ctl;
  6501. struct drm_encoder *enc, *drm_enc = NULL;
  6502. struct drm_plane *plane;
  6503. struct sde_encoder_kickoff_params params = { 0 };
  6504. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  6505. return;
  6506. drm_for_each_encoder_mask(enc, crtc->dev, crtc->state->encoder_mask) {
  6507. drm_enc = enc;
  6508. if (sde_encoder_in_clone_mode(drm_enc))
  6509. return;
  6510. }
  6511. if (!drm_enc || !ctl || !sde_crtc->num_mixers) {
  6512. SDE_ERROR("invalid object, drm_enc:%d, ctl:%d\n", !drm_enc,
  6513. !ctl);
  6514. return;
  6515. }
  6516. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  6517. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_READ, false);
  6518. /* flush only the sys-cache enabled SSPPs */
  6519. if (ctl->ops.clear_pending_flush)
  6520. ctl->ops.clear_pending_flush(ctl);
  6521. drm_atomic_crtc_for_each_plane(plane, crtc)
  6522. sde_plane_ctl_flush(plane, ctl, true);
  6523. /* Enable clocks and IRQ and wait for VBLANK */
  6524. params.affected_displays = _sde_crtc_get_displays_affected(crtc, crtc->state);
  6525. sde_encoder_prepare_for_kickoff(drm_enc, &params);
  6526. sde_encoder_kickoff(drm_enc, false);
  6527. sde_encoder_wait_for_event(drm_enc, MSM_ENC_VBLANK);
  6528. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  6529. }
  6530. void sde_crtc_static_cache_read_kickoff(struct drm_crtc *crtc)
  6531. {
  6532. struct drm_device *dev;
  6533. struct msm_drm_private *priv;
  6534. struct msm_drm_thread *disp_thread;
  6535. struct sde_crtc *sde_crtc;
  6536. struct sde_crtc_state *cstate;
  6537. u32 msecs_fps = 0;
  6538. if (!crtc)
  6539. return;
  6540. dev = crtc->dev;
  6541. sde_crtc = to_sde_crtc(crtc);
  6542. cstate = to_sde_crtc_state(crtc->state);
  6543. if (!dev || !dev->dev_private || !sde_crtc)
  6544. return;
  6545. priv = dev->dev_private;
  6546. disp_thread = &priv->disp_thread[crtc->index];
  6547. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  6548. return;
  6549. msecs_fps = DIV_ROUND_UP((1 * 1000), sde_crtc_get_fps_mode(crtc));
  6550. /* Kickoff transition to read state after next vblank */
  6551. kthread_queue_delayed_work(&disp_thread->worker,
  6552. &sde_crtc->static_cache_read_work,
  6553. msecs_to_jiffies(msecs_fps));
  6554. SDE_EVT32(DRMID(crtc), sde_crtc->cache_state, msecs_fps);
  6555. }
  6556. void sde_crtc_cancel_delayed_work(struct drm_crtc *crtc)
  6557. {
  6558. struct sde_crtc *sde_crtc;
  6559. struct sde_crtc_state *cstate;
  6560. bool cache_status;
  6561. if (!crtc || !crtc->state)
  6562. return;
  6563. sde_crtc = to_sde_crtc(crtc);
  6564. cstate = to_sde_crtc_state(crtc->state);
  6565. cache_status = kthread_cancel_delayed_work_sync(&sde_crtc->static_cache_read_work);
  6566. SDE_EVT32(DRMID(crtc), cache_status);
  6567. }
  6568. /* initialize crtc */
  6569. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  6570. {
  6571. struct drm_crtc *crtc = NULL;
  6572. struct sde_crtc *sde_crtc = NULL;
  6573. struct msm_drm_private *priv = NULL;
  6574. struct sde_kms *kms = NULL;
  6575. const struct drm_crtc_funcs *crtc_funcs;
  6576. int i, rc;
  6577. priv = dev->dev_private;
  6578. kms = to_sde_kms(priv->kms);
  6579. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  6580. if (!sde_crtc)
  6581. return ERR_PTR(-ENOMEM);
  6582. crtc = &sde_crtc->base;
  6583. crtc->dev = dev;
  6584. mutex_init(&sde_crtc->crtc_lock);
  6585. spin_lock_init(&sde_crtc->spin_lock);
  6586. spin_lock_init(&sde_crtc->fevent_spin_lock);
  6587. atomic_set(&sde_crtc->frame_pending, 0);
  6588. sde_crtc->enabled = false;
  6589. sde_crtc->kickoff_in_progress = false;
  6590. /* Below parameters are for fps calculation for sysfs node */
  6591. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  6592. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  6593. sizeof(ktime_t), GFP_KERNEL);
  6594. if (!sde_crtc->fps_info.time_buf)
  6595. SDE_ERROR("invalid buffer\n");
  6596. else
  6597. memset(sde_crtc->fps_info.time_buf, 0,
  6598. sizeof(*(sde_crtc->fps_info.time_buf)));
  6599. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  6600. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  6601. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  6602. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  6603. list_add(&sde_crtc->frame_events[i].list,
  6604. &sde_crtc->frame_event_list);
  6605. kthread_init_work(&sde_crtc->frame_events[i].work,
  6606. sde_crtc_frame_event_work);
  6607. }
  6608. crtc_funcs = test_bit(SDE_FEATURE_HW_VSYNC_TS, kms->catalog->features) ?
  6609. &sde_crtc_funcs_v1 : &sde_crtc_funcs;
  6610. drm_crtc_init_with_planes(dev, crtc, plane, NULL, crtc_funcs, NULL);
  6611. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  6612. if (kms->catalog->hw_fence_rev) {
  6613. set_bit(HW_FENCE_OUT_FENCES_ENABLE, sde_crtc->hwfence_features_mask);
  6614. set_bit(HW_FENCE_IN_FENCES_ENABLE, sde_crtc->hwfence_features_mask);
  6615. }
  6616. /* save user friendly CRTC name for later */
  6617. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  6618. /* initialize event handling */
  6619. rc = _sde_crtc_init_events(sde_crtc);
  6620. if (rc) {
  6621. drm_crtc_cleanup(crtc);
  6622. kfree(sde_crtc);
  6623. return ERR_PTR(rc);
  6624. }
  6625. /* initialize output fence support */
  6626. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  6627. if (IS_ERR(sde_crtc->output_fence)) {
  6628. rc = PTR_ERR(sde_crtc->output_fence);
  6629. SDE_ERROR("failed to init fence, %d\n", rc);
  6630. drm_crtc_cleanup(crtc);
  6631. kfree(sde_crtc);
  6632. return ERR_PTR(rc);
  6633. }
  6634. /* create CRTC properties */
  6635. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  6636. priv->crtc_property, sde_crtc->property_data,
  6637. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  6638. sizeof(struct sde_crtc_state));
  6639. sde_crtc_install_properties(crtc, kms->catalog);
  6640. /* Install color processing properties */
  6641. sde_cp_crtc_init(crtc);
  6642. sde_cp_crtc_install_properties(crtc);
  6643. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  6644. sde_crtc->cur_perf.llcc_active[i] = false;
  6645. sde_crtc->new_perf.llcc_active[i] = false;
  6646. }
  6647. kthread_init_delayed_work(&sde_crtc->static_cache_read_work,
  6648. __sde_crtc_static_cache_read_work);
  6649. SDE_DEBUG("%s: successfully initialized crtc, hwfence_out:%d, hwfence_in:%d\n",
  6650. sde_crtc->name,
  6651. test_bit(HW_FENCE_OUT_FENCES_ENABLE, sde_crtc->hwfence_features_mask),
  6652. test_bit(HW_FENCE_IN_FENCES_ENABLE, sde_crtc->hwfence_features_mask));
  6653. return crtc;
  6654. }
  6655. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  6656. {
  6657. struct sde_crtc *sde_crtc;
  6658. int rc = 0;
  6659. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  6660. SDE_ERROR("invalid input param(s)\n");
  6661. rc = -EINVAL;
  6662. goto end;
  6663. }
  6664. sde_crtc = to_sde_crtc(crtc);
  6665. sde_crtc->sysfs_dev = device_create_with_groups(
  6666. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  6667. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  6668. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  6669. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  6670. PTR_ERR(sde_crtc->sysfs_dev));
  6671. if (!sde_crtc->sysfs_dev)
  6672. rc = -EINVAL;
  6673. else
  6674. rc = PTR_ERR(sde_crtc->sysfs_dev);
  6675. goto end;
  6676. }
  6677. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  6678. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  6679. if (!sde_crtc->vsync_event_sf)
  6680. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  6681. crtc->base.id);
  6682. sde_crtc->retire_frame_event_sf = sysfs_get_dirent(
  6683. sde_crtc->sysfs_dev->kobj.sd, "retire_frame_event");
  6684. if (!sde_crtc->retire_frame_event_sf)
  6685. SDE_ERROR("crtc:%d retire frame event sysfs create failed\n",
  6686. crtc->base.id);
  6687. end:
  6688. return rc;
  6689. }
  6690. static int _sde_crtc_event_enable(struct sde_kms *kms,
  6691. struct drm_crtc *crtc_drm, u32 event)
  6692. {
  6693. struct sde_crtc *crtc = NULL;
  6694. struct sde_crtc_irq_info *node;
  6695. unsigned long flags;
  6696. bool found = false;
  6697. int ret, i = 0;
  6698. bool add_event = false;
  6699. crtc = to_sde_crtc(crtc_drm);
  6700. spin_lock_irqsave(&crtc->spin_lock, flags);
  6701. list_for_each_entry(node, &crtc->user_event_list, list) {
  6702. if (node->event == event) {
  6703. found = true;
  6704. break;
  6705. }
  6706. }
  6707. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6708. /* event already enabled */
  6709. if (found)
  6710. return 0;
  6711. node = NULL;
  6712. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  6713. if (custom_events[i].event == event &&
  6714. custom_events[i].func) {
  6715. node = kzalloc(sizeof(*node), GFP_KERNEL);
  6716. if (!node)
  6717. return -ENOMEM;
  6718. INIT_LIST_HEAD(&node->list);
  6719. INIT_LIST_HEAD(&node->irq.list);
  6720. node->func = custom_events[i].func;
  6721. node->event = event;
  6722. node->state = IRQ_NOINIT;
  6723. spin_lock_init(&node->state_lock);
  6724. break;
  6725. }
  6726. }
  6727. if (!node) {
  6728. SDE_ERROR("unsupported event %x\n", event);
  6729. return -EINVAL;
  6730. }
  6731. ret = 0;
  6732. if (crtc_drm->enabled) {
  6733. ret = pm_runtime_resume_and_get(crtc_drm->dev->dev);
  6734. if (ret < 0) {
  6735. SDE_ERROR("failed to enable power resource %d\n", ret);
  6736. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  6737. kfree(node);
  6738. return ret;
  6739. }
  6740. INIT_LIST_HEAD(&node->irq.list);
  6741. mutex_lock(&crtc->crtc_lock);
  6742. ret = node->func(crtc_drm, true, &node->irq);
  6743. if (!ret) {
  6744. spin_lock_irqsave(&crtc->spin_lock, flags);
  6745. list_add_tail(&node->list, &crtc->user_event_list);
  6746. add_event = true;
  6747. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6748. }
  6749. mutex_unlock(&crtc->crtc_lock);
  6750. pm_runtime_put_sync(crtc_drm->dev->dev);
  6751. }
  6752. if (add_event)
  6753. return 0;
  6754. if (!ret) {
  6755. spin_lock_irqsave(&crtc->spin_lock, flags);
  6756. list_add_tail(&node->list, &crtc->user_event_list);
  6757. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6758. } else {
  6759. kfree(node);
  6760. }
  6761. return ret;
  6762. }
  6763. static int _sde_crtc_event_disable(struct sde_kms *kms,
  6764. struct drm_crtc *crtc_drm, u32 event)
  6765. {
  6766. struct sde_crtc *crtc = NULL;
  6767. struct sde_crtc_irq_info *node = NULL;
  6768. unsigned long flags;
  6769. bool found = false;
  6770. int ret;
  6771. crtc = to_sde_crtc(crtc_drm);
  6772. spin_lock_irqsave(&crtc->spin_lock, flags);
  6773. list_for_each_entry(node, &crtc->user_event_list, list) {
  6774. if (node->event == event) {
  6775. list_del_init(&node->list);
  6776. found = true;
  6777. break;
  6778. }
  6779. }
  6780. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6781. /* event already disabled */
  6782. if (!found)
  6783. return 0;
  6784. /**
  6785. * crtc is disabled interrupts are cleared remove from the list,
  6786. * no need to disable/de-register.
  6787. */
  6788. if (!crtc_drm->enabled) {
  6789. kfree(node);
  6790. return 0;
  6791. }
  6792. ret = pm_runtime_resume_and_get(crtc_drm->dev->dev);
  6793. if (ret < 0) {
  6794. SDE_ERROR("failed to enable power resource %d\n", ret);
  6795. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  6796. kfree(node);
  6797. return ret;
  6798. }
  6799. ret = node->func(crtc_drm, false, &node->irq);
  6800. if (ret) {
  6801. spin_lock_irqsave(&crtc->spin_lock, flags);
  6802. list_add_tail(&node->list, &crtc->user_event_list);
  6803. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6804. } else {
  6805. kfree(node);
  6806. }
  6807. pm_runtime_put_sync(crtc_drm->dev->dev);
  6808. return ret;
  6809. }
  6810. int sde_crtc_register_custom_event(struct sde_kms *kms,
  6811. struct drm_crtc *crtc_drm, u32 event, bool en)
  6812. {
  6813. struct sde_crtc *crtc = NULL;
  6814. int ret;
  6815. crtc = to_sde_crtc(crtc_drm);
  6816. if (!crtc || !kms || !kms->dev) {
  6817. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  6818. kms, ((kms) ? (kms->dev) : NULL));
  6819. return -EINVAL;
  6820. }
  6821. if (en)
  6822. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  6823. else
  6824. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  6825. return ret;
  6826. }
  6827. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  6828. bool en, struct sde_irq_callback *irq)
  6829. {
  6830. return 0;
  6831. }
  6832. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  6833. struct sde_irq_callback *noirq)
  6834. {
  6835. /*
  6836. * IRQ object noirq is not being used here since there is
  6837. * no crtc irq from pm event.
  6838. */
  6839. return 0;
  6840. }
  6841. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  6842. bool en, struct sde_irq_callback *irq)
  6843. {
  6844. return 0;
  6845. }
  6846. static int sde_crtc_mmrm_interrupt_handler(struct drm_crtc *crtc_drm,
  6847. bool en, struct sde_irq_callback *irq)
  6848. {
  6849. return 0;
  6850. }
  6851. static int sde_crtc_opr_event_handler(struct drm_crtc *crtc_drm,
  6852. bool en, struct sde_irq_callback *irq)
  6853. {
  6854. struct sde_crtc *sde_crtc;
  6855. sde_crtc = to_sde_crtc(crtc_drm);
  6856. if (!sde_crtc)
  6857. return -EINVAL;
  6858. sde_crtc->opr_event_notify_enabled = en;
  6859. return 0;
  6860. }
  6861. static int sde_crtc_vm_release_handler(struct drm_crtc *crtc_drm,
  6862. bool en, struct sde_irq_callback *irq)
  6863. {
  6864. return 0;
  6865. }
  6866. static int sde_crtc_frame_data_interrupt_handler(struct drm_crtc *crtc_drm,
  6867. bool en, struct sde_irq_callback *irq)
  6868. {
  6869. return 0;
  6870. }
  6871. /**
  6872. * sde_crtc_update_cont_splash_settings - update mixer settings
  6873. * and initial clk during device bootup for cont_splash use case
  6874. * @crtc: Pointer to drm crtc structure
  6875. */
  6876. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  6877. {
  6878. struct sde_kms *kms = NULL;
  6879. struct msm_drm_private *priv;
  6880. struct sde_crtc *sde_crtc;
  6881. u64 rate;
  6882. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  6883. SDE_ERROR("invalid crtc\n");
  6884. return;
  6885. }
  6886. priv = crtc->dev->dev_private;
  6887. kms = to_sde_kms(priv->kms);
  6888. if (!kms || !kms->catalog) {
  6889. SDE_ERROR("invalid parameters\n");
  6890. return;
  6891. }
  6892. _sde_crtc_setup_mixers(crtc);
  6893. sde_cp_crtc_refresh_status_properties(crtc);
  6894. crtc->enabled = true;
  6895. /* update core clk value for initial state with cont-splash */
  6896. sde_crtc = to_sde_crtc(crtc);
  6897. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  6898. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  6899. rate : kms->perf.max_core_clk_rate;
  6900. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  6901. }
  6902. static void sde_crtc_install_noise_layer_properties(struct sde_crtc *sde_crtc,
  6903. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  6904. {
  6905. struct sde_lm_cfg *lm;
  6906. char feature_name[256];
  6907. u32 version;
  6908. if (!catalog->mixer_count)
  6909. return;
  6910. lm = &catalog->mixer[0];
  6911. if (!(lm->features & BIT(SDE_MIXER_NOISE_LAYER)))
  6912. return;
  6913. version = lm->sblk->nlayer.version >> 16;
  6914. snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d", "noise_layer_v", version);
  6915. switch (version) {
  6916. case 1:
  6917. sde_kms_info_add_keyint(info, "has_noise_layer", 1);
  6918. msm_property_install_volatile_range(&sde_crtc->property_info,
  6919. feature_name, 0x0, 0, ~0, 0, CRTC_PROP_NOISE_LAYER_V1);
  6920. break;
  6921. default:
  6922. SDE_ERROR("unsupported noise layer version %d\n", version);
  6923. break;
  6924. }
  6925. }
  6926. static int _sde_crtc_set_noise_layer(struct sde_crtc *sde_crtc,
  6927. struct sde_crtc_state *cstate,
  6928. void __user *usr_ptr)
  6929. {
  6930. int ret;
  6931. if (!sde_crtc || !cstate) {
  6932. SDE_ERROR("invalid sde_crtc/state\n");
  6933. return -EINVAL;
  6934. }
  6935. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  6936. if (!usr_ptr) {
  6937. SDE_DEBUG("noise layer removed\n");
  6938. cstate->noise_layer_en = false;
  6939. set_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty);
  6940. return 0;
  6941. }
  6942. ret = copy_from_user(&cstate->layer_cfg, usr_ptr,
  6943. sizeof(cstate->layer_cfg));
  6944. if (ret) {
  6945. SDE_ERROR("failed to copy noise layer %d\n", ret);
  6946. return -EFAULT;
  6947. }
  6948. if (cstate->layer_cfg.zposn != cstate->layer_cfg.zposattn - 1 ||
  6949. cstate->layer_cfg.zposattn >= SDE_STAGE_MAX ||
  6950. !cstate->layer_cfg.attn_factor ||
  6951. cstate->layer_cfg.attn_factor > DRM_NOISE_ATTN_MAX ||
  6952. cstate->layer_cfg.strength > DRM_NOISE_STREN_MAX ||
  6953. !cstate->layer_cfg.alpha_noise ||
  6954. cstate->layer_cfg.alpha_noise > DRM_NOISE_ATTN_MAX) {
  6955. SDE_ERROR("invalid param zposn %d zposattn %d attn_factor %d \
  6956. strength %d alpha noise %d\n", cstate->layer_cfg.zposn,
  6957. cstate->layer_cfg.zposattn, cstate->layer_cfg.attn_factor,
  6958. cstate->layer_cfg.strength, cstate->layer_cfg.alpha_noise);
  6959. return -EINVAL;
  6960. }
  6961. cstate->noise_layer_en = true;
  6962. set_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty);
  6963. return 0;
  6964. }
  6965. static void sde_cp_crtc_apply_noise(struct drm_crtc *crtc,
  6966. struct drm_crtc_state *state)
  6967. {
  6968. struct sde_crtc *scrtc = to_sde_crtc(crtc);
  6969. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  6970. struct sde_hw_mixer *lm;
  6971. int i;
  6972. struct sde_hw_noise_layer_cfg cfg;
  6973. struct sde_kms *kms;
  6974. if (!test_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty))
  6975. return;
  6976. kms = _sde_crtc_get_kms(crtc);
  6977. if (!kms || !kms->catalog) {
  6978. SDE_ERROR("Invalid kms\n");
  6979. return;
  6980. }
  6981. cfg.flags = cstate->layer_cfg.flags;
  6982. cfg.alpha_noise = cstate->layer_cfg.alpha_noise;
  6983. cfg.attn_factor = cstate->layer_cfg.attn_factor;
  6984. cfg.strength = cstate->layer_cfg.strength;
  6985. if (!test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features)) {
  6986. cfg.noise_blend_stage = cstate->layer_cfg.zposn + SDE_STAGE_0;
  6987. cfg.attn_blend_stage = cstate->layer_cfg.zposattn + SDE_STAGE_0;
  6988. } else {
  6989. cfg.noise_blend_stage = cstate->layer_cfg.zposn;
  6990. cfg.attn_blend_stage = cstate->layer_cfg.zposattn;
  6991. }
  6992. for (i = 0; i < scrtc->num_mixers; i++) {
  6993. lm = scrtc->mixers[i].hw_lm;
  6994. if (!lm->ops.setup_noise_layer)
  6995. break;
  6996. if (!cstate->noise_layer_en)
  6997. lm->ops.setup_noise_layer(lm, NULL);
  6998. else
  6999. lm->ops.setup_noise_layer(lm, &cfg);
  7000. }
  7001. if (!cstate->noise_layer_en)
  7002. clear_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty);
  7003. }
  7004. void sde_crtc_disable_cp_features(struct drm_crtc *crtc)
  7005. {
  7006. sde_cp_disable_features(crtc);
  7007. }
  7008. void _sde_crtc_vm_release_notify(struct drm_crtc *crtc)
  7009. {
  7010. uint32_t val = 1;
  7011. sde_crtc_event_notify(crtc, DRM_EVENT_VM_RELEASE, &val, sizeof(uint32_t));
  7012. }
  7013. void sde_crtc_calc_vpadding_param(struct drm_crtc_state *state, u32 crtc_y, uint32_t crtc_h,
  7014. u32 *padding_y, u32 *padding_start, u32 *padding_height)
  7015. {
  7016. struct sde_kms *kms;
  7017. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  7018. u32 y_remain, y_start, y_end;
  7019. u32 m, n;
  7020. kms = _sde_crtc_get_kms(state->crtc);
  7021. if (!kms || !kms->catalog) {
  7022. SDE_ERROR("invalid kms or catalog\n");
  7023. return;
  7024. }
  7025. if (!kms->catalog->has_line_insertion)
  7026. return;
  7027. if (!cstate->line_insertion.padding_active) {
  7028. SDE_ERROR("zero padding active value\n");
  7029. return;
  7030. }
  7031. /*
  7032. * Computation logic to add number of dummy and active line at
  7033. * precise position on display
  7034. */
  7035. m = cstate->line_insertion.padding_active;
  7036. n = m + cstate->line_insertion.padding_dummy;
  7037. if (m == 0)
  7038. return;
  7039. y_remain = crtc_y % m;
  7040. y_start = y_remain + crtc_y / m * n;
  7041. y_end = (((crtc_y + crtc_h - 1) / m) * n) + ((crtc_y + crtc_h - 1) % m);
  7042. *padding_y = y_start;
  7043. *padding_start = m - y_remain;
  7044. *padding_height = y_end - y_start + 1;
  7045. SDE_EVT32(DRMID(cstate->base.crtc), y_remain, y_start, y_end, *padding_y, *padding_start,
  7046. *padding_height);
  7047. SDE_DEBUG("crtc:%d padding_y:%d padding_start:%d padding_height:%d\n",
  7048. DRMID(cstate->base.crtc), *padding_y, *padding_start, *padding_height);
  7049. }