dsi_ctrl_hw.h 38 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #ifndef _DSI_CTRL_HW_H_
  7. #define _DSI_CTRL_HW_H_
  8. #include <linux/kernel.h>
  9. #include <linux/types.h>
  10. #include <linux/bitops.h>
  11. #include <linux/bitmap.h>
  12. #include "dsi_defs.h"
  13. #include "dsi_hw.h"
  14. #define DSI_CTRL_HW_DBG(c, fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: DSI_%d: "\
  15. fmt, c ? c->index : -1, ##__VA_ARGS__)
  16. #define DSI_CTRL_HW_ERR(c, fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: DSI_%d: "\
  17. fmt, c ? c->index : -1, ##__VA_ARGS__)
  18. #define DSI_CTRL_HW_INFO(c, fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: DSI_%d: "\
  19. fmt, c ? c->index : -1, ##__VA_ARGS__)
  20. #define DSI_MMSS_MISC_R32(dsi_ctrl_hw, off) DSI_GEN_R32((dsi_ctrl_hw)->mmss_misc_base, off)
  21. #define DSI_MMSS_MISC_W32(dsi_ctrl_hw, off, val) \
  22. DSI_GEN_W32_DEBUG((dsi_ctrl_hw)->mmss_misc_base, (dsi_ctrl_hw)->index, off, val)
  23. #define DSI_DISP_CC_R32(dsi_ctrl_hw, off) DSI_GEN_R32((dsi_ctrl_hw)->disp_cc_base, off)
  24. #define DSI_DISP_CC_W32(dsi_ctrl_hw, off, val) \
  25. DSI_GEN_W32_DEBUG((dsi_ctrl_hw)->disp_cc_base, (dsi_ctrl_hw)->index, off, val)
  26. #define DSI_MDP_INTF_R32(dsi_ctrl_hw, off) DSI_GEN_R32((dsi_ctrl_hw)->mdp_intf_base, off)
  27. #define DSI_MDP_INTF_W32(dsi_ctrl_hw, off, val) \
  28. DSI_GEN_W32_DEBUG((dsi_ctrl_hw)->mdp_intf_base, (dsi_ctrl_hw)->index, off, val)
  29. /**
  30. * Modifier flag for command transmission. If this flag is set, command
  31. * information is programmed to hardware and transmission is not triggered.
  32. * Caller should call the trigger_command_dma() to start the transmission. This
  33. * flag is valed for kickoff_command() and kickoff_fifo_command() operations.
  34. */
  35. #define DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER 0x1
  36. /**
  37. * enum dsi_ctrl_tpg_pattern - type of TPG pattern
  38. * @DSI_CTRL_TPG_COUNTER:
  39. * @DSI_CTRL_TPG_FIXED:
  40. * @DSI_CTRL_TPG_COLOR_RAMP_64L_64P:
  41. * @DSI_CTRL_TPG_COLOR_RAMP_64L_256P:
  42. * @DSI_CTRL_TPG_GRAYSCALE_RAMP:
  43. * @DSI_CTRL_TPG_COLOR_SQUARE:
  44. * @DSI_CTRL_TPG_CHECKERED_RECTANGLE:
  45. * @DSI_CTRL_TPG_BASIC_COLOR_CHANGING:
  46. */
  47. enum dsi_ctrl_tpg_pattern {
  48. DSI_CTRL_TPG_COUNTER = 0,
  49. DSI_CTRL_TPG_FIXED,
  50. DSI_CTRL_TPG_COLOR_RAMP_64L_64P,
  51. DSI_CTRL_TPG_COLOR_RAMP_64L_256P,
  52. DSI_CTRL_TPG_BLACK_WHITE_VERTICAL_LINES,
  53. DSI_CTRL_TPG_GRAYSCALE_RAMP,
  54. DSI_CTRL_TPG_COLOR_SQUARE,
  55. DSI_CTRL_TPG_CHECKERED_RECTANGLE,
  56. DSI_CTRL_TPG_BASIC_COLOR_CHANGING
  57. };
  58. /**
  59. * enum dsi_ctrl_version - version of the dsi host controller
  60. * @DSI_CTRL_VERSION_UNKNOWN: Unknown controller version
  61. * @DSI_CTRL_VERSION_2_2: DSI host v2.2 controller
  62. * @DSI_CTRL_VERSION_2_3: DSI host v2.3 controller
  63. * @DSI_CTRL_VERSION_2_4: DSI host v2.4 controller
  64. * @DSI_CTRL_VERSION_2_5: DSI host v2.5 controller
  65. * @DSI_CTRL_VERSION_2_6: DSI host v2.6 controller
  66. * @DSI_CTRL_VERSION_2_7: DSI host v2.7 controller
  67. * @DSI_CTRL_VERSION_2_8: DSI host v2.8 controller
  68. * @DSI_CTRL_VERSION_MAX: max version
  69. */
  70. enum dsi_ctrl_version {
  71. DSI_CTRL_VERSION_UNKNOWN,
  72. DSI_CTRL_VERSION_2_2,
  73. DSI_CTRL_VERSION_2_3,
  74. DSI_CTRL_VERSION_2_4,
  75. DSI_CTRL_VERSION_2_5,
  76. DSI_CTRL_VERSION_2_6,
  77. DSI_CTRL_VERSION_2_7,
  78. DSI_CTRL_VERSION_2_8,
  79. DSI_CTRL_VERSION_MAX
  80. };
  81. /**
  82. * enum dsi_ctrl_hw_features - features supported by dsi host controller
  83. * @DSI_CTRL_VIDEO_TPG: Test pattern support for video mode.
  84. * @DSI_CTRL_CMD_TPG: Test pattern support for command mode.
  85. * @DSI_CTRL_VARIABLE_REFRESH_RATE: variable panel timing
  86. * @DSI_CTRL_DYNAMIC_REFRESH: variable pixel clock rate
  87. * @DSI_CTRL_NULL_PACKET_INSERTION: NULL packet insertion
  88. * @DSI_CTRL_DESKEW_CALIB: Deskew calibration support
  89. * @DSI_CTRL_DPHY: Controller support for DPHY
  90. * @DSI_CTRL_CPHY: Controller support for CPHY
  91. * @DSI_CTRL_MAX_FEATURES:
  92. */
  93. enum dsi_ctrl_hw_features {
  94. DSI_CTRL_VIDEO_TPG,
  95. DSI_CTRL_CMD_TPG,
  96. DSI_CTRL_VARIABLE_REFRESH_RATE,
  97. DSI_CTRL_DYNAMIC_REFRESH,
  98. DSI_CTRL_NULL_PACKET_INSERTION,
  99. DSI_CTRL_DESKEW_CALIB,
  100. DSI_CTRL_DPHY,
  101. DSI_CTRL_CPHY,
  102. DSI_CTRL_MAX_FEATURES
  103. };
  104. /**
  105. * enum dsi_test_pattern - test pattern type
  106. * @DSI_TEST_PATTERN_FIXED: Test pattern is fixed, based on init value.
  107. * @DSI_TEST_PATTERN_INC: Incremental test pattern, base on init value.
  108. * @DSI_TEST_PATTERN_POLY: Pattern generated from polynomial and init val.
  109. * @DSI_TEST_PATTERN_GENERAL: MDSS general test pattern.
  110. * @DSI_TEST_PATTERN_MAX:
  111. */
  112. enum dsi_test_pattern {
  113. DSI_TEST_PATTERN_FIXED = 0,
  114. DSI_TEST_PATTERN_INC,
  115. DSI_TEST_PATTERN_POLY,
  116. DSI_TEST_PATTERN_GENERAL,
  117. DSI_TEST_PATTERN_MAX
  118. };
  119. /**
  120. * enum dsi_status_int_index - index of interrupts generated by DSI controller
  121. * @DSI_SINT_CMD_MODE_DMA_DONE: Command mode DMA packets are sent out.
  122. * @DSI_SINT_CMD_STREAM0_FRAME_DONE: A frame of cmd mode stream0 is sent out.
  123. * @DSI_SINT_CMD_STREAM1_FRAME_DONE: A frame of cmd mode stream1 is sent out.
  124. * @DSI_SINT_CMD_STREAM2_FRAME_DONE: A frame of cmd mode stream2 is sent out.
  125. * @DSI_SINT_VIDEO_MODE_FRAME_DONE: A frame of video mode stream is sent out.
  126. * @DSI_SINT_BTA_DONE: A BTA is completed.
  127. * @DSI_SINT_CMD_FRAME_DONE: A frame of selected cmd mode stream is
  128. * sent out by MDP.
  129. * @DSI_SINT_DYN_REFRESH_DONE: The dynamic refresh operation completed.
  130. * @DSI_SINT_DESKEW_DONE: The deskew calibration operation done.
  131. * @DSI_SINT_DYN_BLANK_DMA_DONE: The dynamic blankin DMA operation has
  132. * completed.
  133. * @DSI_SINT_ERROR: DSI error has happened.
  134. */
  135. enum dsi_status_int_index {
  136. DSI_SINT_CMD_MODE_DMA_DONE = 0,
  137. DSI_SINT_CMD_STREAM0_FRAME_DONE = 1,
  138. DSI_SINT_CMD_STREAM1_FRAME_DONE = 2,
  139. DSI_SINT_CMD_STREAM2_FRAME_DONE = 3,
  140. DSI_SINT_VIDEO_MODE_FRAME_DONE = 4,
  141. DSI_SINT_BTA_DONE = 5,
  142. DSI_SINT_CMD_FRAME_DONE = 6,
  143. DSI_SINT_DYN_REFRESH_DONE = 7,
  144. DSI_SINT_DESKEW_DONE = 8,
  145. DSI_SINT_DYN_BLANK_DMA_DONE = 9,
  146. DSI_SINT_ERROR = 10,
  147. DSI_STATUS_INTERRUPT_COUNT
  148. };
  149. /**
  150. * enum dsi_status_int_type - status interrupts generated by DSI controller
  151. * @DSI_CMD_MODE_DMA_DONE: Command mode DMA packets are sent out.
  152. * @DSI_CMD_STREAM0_FRAME_DONE: A frame of command mode stream0 is sent out.
  153. * @DSI_CMD_STREAM1_FRAME_DONE: A frame of command mode stream1 is sent out.
  154. * @DSI_CMD_STREAM2_FRAME_DONE: A frame of command mode stream2 is sent out.
  155. * @DSI_VIDEO_MODE_FRAME_DONE: A frame of video mode stream is sent out.
  156. * @DSI_BTA_DONE: A BTA is completed.
  157. * @DSI_CMD_FRAME_DONE: A frame of selected command mode stream is
  158. * sent out by MDP.
  159. * @DSI_DYN_REFRESH_DONE: The dynamic refresh operation has completed.
  160. * @DSI_DESKEW_DONE: The deskew calibration operation has completed
  161. * @DSI_DYN_BLANK_DMA_DONE: The dynamic blankin DMA operation has
  162. * completed.
  163. * @DSI_ERROR: DSI error has happened.
  164. */
  165. enum dsi_status_int_type {
  166. DSI_CMD_MODE_DMA_DONE = BIT(DSI_SINT_CMD_MODE_DMA_DONE),
  167. DSI_CMD_STREAM0_FRAME_DONE = BIT(DSI_SINT_CMD_STREAM0_FRAME_DONE),
  168. DSI_CMD_STREAM1_FRAME_DONE = BIT(DSI_SINT_CMD_STREAM1_FRAME_DONE),
  169. DSI_CMD_STREAM2_FRAME_DONE = BIT(DSI_SINT_CMD_STREAM2_FRAME_DONE),
  170. DSI_VIDEO_MODE_FRAME_DONE = BIT(DSI_SINT_VIDEO_MODE_FRAME_DONE),
  171. DSI_BTA_DONE = BIT(DSI_SINT_BTA_DONE),
  172. DSI_CMD_FRAME_DONE = BIT(DSI_SINT_CMD_FRAME_DONE),
  173. DSI_DYN_REFRESH_DONE = BIT(DSI_SINT_DYN_REFRESH_DONE),
  174. DSI_DESKEW_DONE = BIT(DSI_SINT_DESKEW_DONE),
  175. DSI_DYN_BLANK_DMA_DONE = BIT(DSI_SINT_DYN_BLANK_DMA_DONE),
  176. DSI_ERROR = BIT(DSI_SINT_ERROR)
  177. };
  178. /**
  179. * enum dsi_error_int_index - index of error interrupts from DSI controller
  180. * @DSI_EINT_RDBK_SINGLE_ECC_ERR: Single bit ECC error in read packet.
  181. * @DSI_EINT_RDBK_MULTI_ECC_ERR: Multi bit ECC error in read packet.
  182. * @DSI_EINT_RDBK_CRC_ERR: CRC error in read packet.
  183. * @DSI_EINT_RDBK_INCOMPLETE_PKT: Incomplete read packet.
  184. * @DSI_EINT_PERIPH_ERROR_PKT: Error packet returned from peripheral,
  185. * @DSI_EINT_LP_RX_TIMEOUT: Low power reverse transmission timeout.
  186. * @DSI_EINT_HS_TX_TIMEOUT: High speed fwd transmission timeout.
  187. * @DSI_EINT_BTA_TIMEOUT: BTA timeout.
  188. * @DSI_EINT_PLL_UNLOCK: PLL has unlocked.
  189. * @DSI_EINT_DLN0_ESC_ENTRY_ERR: Incorrect LP Rx escape entry.
  190. * @DSI_EINT_DLN0_ESC_SYNC_ERR: LP Rx data is not byte aligned.
  191. * @DSI_EINT_DLN0_LP_CONTROL_ERR: Incorrect LP Rx state sequence.
  192. * @DSI_EINT_PANEL_SPECIFIC_ERR: DSI Protocol violation error.
  193. * @DSI_EINT_INTERLEAVE_OP_CONTENTION: Interleave operation contention.
  194. * @DSI_EINT_CMD_DMA_FIFO_UNDERFLOW: Command mode DMA FIFO underflow.
  195. * @DSI_EINT_CMD_MDP_FIFO_UNDERFLOW: Command MDP FIFO underflow (failed to
  196. * receive one complete line from MDP).
  197. * @DSI_EINT_DLN0_HS_FIFO_OVERFLOW: High speed FIFO data lane 0 overflows.
  198. * @DSI_EINT_DLN1_HS_FIFO_OVERFLOW: High speed FIFO data lane 1 overflows.
  199. * @DSI_EINT_DLN2_HS_FIFO_OVERFLOW: High speed FIFO data lane 2 overflows.
  200. * @DSI_EINT_DLN3_HS_FIFO_OVERFLOW: High speed FIFO data lane 3 overflows.
  201. * @DSI_EINT_DLN0_HS_FIFO_UNDERFLOW: High speed FIFO data lane 0 underflows.
  202. * @DSI_EINT_DLN1_HS_FIFO_UNDERFLOW: High speed FIFO data lane 1 underflows.
  203. * @DSI_EINT_DLN2_HS_FIFO_UNDERFLOW: High speed FIFO data lane 2 underflows.
  204. * @DSI_EINT_DLN3_HS_FIFO_UNDERFLOW: High speed FIFO data lane 3 undeflows.
  205. * @DSI_EINT_DLN0_LP0_CONTENTION: PHY level contention while lane 0 low.
  206. * @DSI_EINT_DLN1_LP0_CONTENTION: PHY level contention while lane 1 low.
  207. * @DSI_EINT_DLN2_LP0_CONTENTION: PHY level contention while lane 2 low.
  208. * @DSI_EINT_DLN3_LP0_CONTENTION: PHY level contention while lane 3 low.
  209. * @DSI_EINT_DLN0_LP1_CONTENTION: PHY level contention while lane 0 high.
  210. * @DSI_EINT_DLN1_LP1_CONTENTION: PHY level contention while lane 1 high.
  211. * @DSI_EINT_DLN2_LP1_CONTENTION: PHY level contention while lane 2 high.
  212. * @DSI_EINT_DLN3_LP1_CONTENTION: PHY level contention while lane 3 high.
  213. */
  214. enum dsi_error_int_index {
  215. DSI_EINT_RDBK_SINGLE_ECC_ERR = 0,
  216. DSI_EINT_RDBK_MULTI_ECC_ERR = 1,
  217. DSI_EINT_RDBK_CRC_ERR = 2,
  218. DSI_EINT_RDBK_INCOMPLETE_PKT = 3,
  219. DSI_EINT_PERIPH_ERROR_PKT = 4,
  220. DSI_EINT_LP_RX_TIMEOUT = 5,
  221. DSI_EINT_HS_TX_TIMEOUT = 6,
  222. DSI_EINT_BTA_TIMEOUT = 7,
  223. DSI_EINT_PLL_UNLOCK = 8,
  224. DSI_EINT_DLN0_ESC_ENTRY_ERR = 9,
  225. DSI_EINT_DLN0_ESC_SYNC_ERR = 10,
  226. DSI_EINT_DLN0_LP_CONTROL_ERR = 11,
  227. DSI_EINT_PANEL_SPECIFIC_ERR = 12,
  228. DSI_EINT_INTERLEAVE_OP_CONTENTION = 13,
  229. DSI_EINT_CMD_DMA_FIFO_UNDERFLOW = 14,
  230. DSI_EINT_CMD_MDP_FIFO_UNDERFLOW = 15,
  231. DSI_EINT_DLN0_HS_FIFO_OVERFLOW = 16,
  232. DSI_EINT_DLN1_HS_FIFO_OVERFLOW = 17,
  233. DSI_EINT_DLN2_HS_FIFO_OVERFLOW = 18,
  234. DSI_EINT_DLN3_HS_FIFO_OVERFLOW = 19,
  235. DSI_EINT_DLN0_HS_FIFO_UNDERFLOW = 20,
  236. DSI_EINT_DLN1_HS_FIFO_UNDERFLOW = 21,
  237. DSI_EINT_DLN2_HS_FIFO_UNDERFLOW = 22,
  238. DSI_EINT_DLN3_HS_FIFO_UNDERFLOW = 23,
  239. DSI_EINT_DLN0_LP0_CONTENTION = 24,
  240. DSI_EINT_DLN1_LP0_CONTENTION = 25,
  241. DSI_EINT_DLN2_LP0_CONTENTION = 26,
  242. DSI_EINT_DLN3_LP0_CONTENTION = 27,
  243. DSI_EINT_DLN0_LP1_CONTENTION = 28,
  244. DSI_EINT_DLN1_LP1_CONTENTION = 29,
  245. DSI_EINT_DLN2_LP1_CONTENTION = 30,
  246. DSI_EINT_DLN3_LP1_CONTENTION = 31,
  247. DSI_ERROR_INTERRUPT_COUNT
  248. };
  249. /**
  250. * enum dsi_error_int_type - error interrupts generated by DSI controller
  251. * @DSI_RDBK_SINGLE_ECC_ERR: Single bit ECC error in read packet.
  252. * @DSI_RDBK_MULTI_ECC_ERR: Multi bit ECC error in read packet.
  253. * @DSI_RDBK_CRC_ERR: CRC error in read packet.
  254. * @DSI_RDBK_INCOMPLETE_PKT: Incomplete read packet.
  255. * @DSI_PERIPH_ERROR_PKT: Error packet returned from peripheral,
  256. * @DSI_LP_RX_TIMEOUT: Low power reverse transmission timeout.
  257. * @DSI_HS_TX_TIMEOUT: High speed forward transmission timeout.
  258. * @DSI_BTA_TIMEOUT: BTA timeout.
  259. * @DSI_PLL_UNLOCK: PLL has unlocked.
  260. * @DSI_DLN0_ESC_ENTRY_ERR: Incorrect LP Rx escape entry.
  261. * @DSI_DLN0_ESC_SYNC_ERR: LP Rx data is not byte aligned.
  262. * @DSI_DLN0_LP_CONTROL_ERR: Incorrect LP Rx state sequence.
  263. * @DSI_PANEL_SPECIFIC_ERR: DSI Protocol violation.
  264. * @DSI_INTERLEAVE_OP_CONTENTION: Interleave operation contention.
  265. * @DSI_CMD_DMA_FIFO_UNDERFLOW: Command mode DMA FIFO underflow.
  266. * @DSI_CMD_MDP_FIFO_UNDERFLOW: Command MDP FIFO underflow (failed to
  267. * receive one complete line from MDP).
  268. * @DSI_DLN0_HS_FIFO_OVERFLOW: High speed FIFO for data lane 0 overflows.
  269. * @DSI_DLN1_HS_FIFO_OVERFLOW: High speed FIFO for data lane 1 overflows.
  270. * @DSI_DLN2_HS_FIFO_OVERFLOW: High speed FIFO for data lane 2 overflows.
  271. * @DSI_DLN3_HS_FIFO_OVERFLOW: High speed FIFO for data lane 3 overflows.
  272. * @DSI_DLN0_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 0 underflows.
  273. * @DSI_DLN1_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 1 underflows.
  274. * @DSI_DLN2_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 2 underflows.
  275. * @DSI_DLN3_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 3 undeflows.
  276. * @DSI_DLN0_LP0_CONTENTION: PHY level contention while lane 0 is low.
  277. * @DSI_DLN1_LP0_CONTENTION: PHY level contention while lane 1 is low.
  278. * @DSI_DLN2_LP0_CONTENTION: PHY level contention while lane 2 is low.
  279. * @DSI_DLN3_LP0_CONTENTION: PHY level contention while lane 3 is low.
  280. * @DSI_DLN0_LP1_CONTENTION: PHY level contention while lane 0 is high.
  281. * @DSI_DLN1_LP1_CONTENTION: PHY level contention while lane 1 is high.
  282. * @DSI_DLN2_LP1_CONTENTION: PHY level contention while lane 2 is high.
  283. * @DSI_DLN3_LP1_CONTENTION: PHY level contention while lane 3 is high.
  284. */
  285. enum dsi_error_int_type {
  286. DSI_RDBK_SINGLE_ECC_ERR = BIT(DSI_EINT_RDBK_SINGLE_ECC_ERR),
  287. DSI_RDBK_MULTI_ECC_ERR = BIT(DSI_EINT_RDBK_MULTI_ECC_ERR),
  288. DSI_RDBK_CRC_ERR = BIT(DSI_EINT_RDBK_CRC_ERR),
  289. DSI_RDBK_INCOMPLETE_PKT = BIT(DSI_EINT_RDBK_INCOMPLETE_PKT),
  290. DSI_PERIPH_ERROR_PKT = BIT(DSI_EINT_PERIPH_ERROR_PKT),
  291. DSI_LP_RX_TIMEOUT = BIT(DSI_EINT_LP_RX_TIMEOUT),
  292. DSI_HS_TX_TIMEOUT = BIT(DSI_EINT_HS_TX_TIMEOUT),
  293. DSI_BTA_TIMEOUT = BIT(DSI_EINT_BTA_TIMEOUT),
  294. DSI_PLL_UNLOCK = BIT(DSI_EINT_PLL_UNLOCK),
  295. DSI_DLN0_ESC_ENTRY_ERR = BIT(DSI_EINT_DLN0_ESC_ENTRY_ERR),
  296. DSI_DLN0_ESC_SYNC_ERR = BIT(DSI_EINT_DLN0_ESC_SYNC_ERR),
  297. DSI_DLN0_LP_CONTROL_ERR = BIT(DSI_EINT_DLN0_LP_CONTROL_ERR),
  298. DSI_PANEL_SPECIFIC_ERR = BIT(DSI_EINT_PANEL_SPECIFIC_ERR),
  299. DSI_INTERLEAVE_OP_CONTENTION = BIT(DSI_EINT_INTERLEAVE_OP_CONTENTION),
  300. DSI_CMD_DMA_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_DMA_FIFO_UNDERFLOW),
  301. DSI_CMD_MDP_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_MDP_FIFO_UNDERFLOW),
  302. DSI_DLN0_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN0_HS_FIFO_OVERFLOW),
  303. DSI_DLN1_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN1_HS_FIFO_OVERFLOW),
  304. DSI_DLN2_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN2_HS_FIFO_OVERFLOW),
  305. DSI_DLN3_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN3_HS_FIFO_OVERFLOW),
  306. DSI_DLN0_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN0_HS_FIFO_UNDERFLOW),
  307. DSI_DLN1_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN1_HS_FIFO_UNDERFLOW),
  308. DSI_DLN2_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN2_HS_FIFO_UNDERFLOW),
  309. DSI_DLN3_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN3_HS_FIFO_UNDERFLOW),
  310. DSI_DLN0_LP0_CONTENTION = BIT(DSI_EINT_DLN0_LP0_CONTENTION),
  311. DSI_DLN1_LP0_CONTENTION = BIT(DSI_EINT_DLN1_LP0_CONTENTION),
  312. DSI_DLN2_LP0_CONTENTION = BIT(DSI_EINT_DLN2_LP0_CONTENTION),
  313. DSI_DLN3_LP0_CONTENTION = BIT(DSI_EINT_DLN3_LP0_CONTENTION),
  314. DSI_DLN0_LP1_CONTENTION = BIT(DSI_EINT_DLN0_LP1_CONTENTION),
  315. DSI_DLN1_LP1_CONTENTION = BIT(DSI_EINT_DLN1_LP1_CONTENTION),
  316. DSI_DLN2_LP1_CONTENTION = BIT(DSI_EINT_DLN2_LP1_CONTENTION),
  317. DSI_DLN3_LP1_CONTENTION = BIT(DSI_EINT_DLN3_LP1_CONTENTION),
  318. };
  319. /**
  320. * struct dsi_ctrl_cmd_dma_info - command buffer information
  321. * @offset: IOMMU VA for command buffer address.
  322. * @length: Length of the command buffer.
  323. * @datatype: Datatype of cmd.
  324. * @en_broadcast: Enable broadcast mode if set to true.
  325. * @is_master: Is master in broadcast mode.
  326. * @use_lpm: Use low power mode for command transmission.
  327. */
  328. struct dsi_ctrl_cmd_dma_info {
  329. u32 offset;
  330. u32 length;
  331. u8 datatype;
  332. bool en_broadcast;
  333. bool is_master;
  334. bool use_lpm;
  335. };
  336. /**
  337. * struct dsi_ctrl_cmd_dma_fifo_info - command payload tp be sent using FIFO
  338. * @command: VA for command buffer.
  339. * @size: Size of the command buffer.
  340. * @en_broadcast: Enable broadcast mode if set to true.
  341. * @is_master: Is master in broadcast mode.
  342. * @use_lpm: Use low power mode for command transmission.
  343. */
  344. struct dsi_ctrl_cmd_dma_fifo_info {
  345. u32 *command;
  346. u32 size;
  347. bool en_broadcast;
  348. bool is_master;
  349. bool use_lpm;
  350. };
  351. struct dsi_ctrl_hw;
  352. struct ctrl_ulps_config_ops {
  353. /**
  354. * ulps_request() - request ulps entry for specified lanes
  355. * @ctrl: Pointer to the controller host hardware.
  356. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  357. * to enter ULPS.
  358. *
  359. * Caller should check if lanes are in ULPS mode by calling
  360. * get_lanes_in_ulps() operation.
  361. */
  362. void (*ulps_request)(struct dsi_ctrl_hw *ctrl, u32 lanes);
  363. /**
  364. * ulps_exit() - exit ULPS on specified lanes
  365. * @ctrl: Pointer to the controller host hardware.
  366. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  367. * to exit ULPS.
  368. *
  369. * Caller should check if lanes are in active mode by calling
  370. * get_lanes_in_ulps() operation.
  371. */
  372. void (*ulps_exit)(struct dsi_ctrl_hw *ctrl, u32 lanes);
  373. /**
  374. * get_lanes_in_ulps() - returns the list of lanes in ULPS mode
  375. * @ctrl: Pointer to the controller host hardware.
  376. *
  377. * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
  378. * state. If 0 is returned, all the lanes are active.
  379. *
  380. * Return: List of lanes in ULPS state.
  381. */
  382. u32 (*get_lanes_in_ulps)(struct dsi_ctrl_hw *ctrl);
  383. };
  384. /**
  385. * struct dsi_ctrl_hw_ops - operations supported by dsi host hardware
  386. */
  387. struct dsi_ctrl_hw_ops {
  388. /**
  389. * host_setup() - Setup DSI host configuration
  390. * @ctrl: Pointer to controller host hardware.
  391. * @config: Configuration for DSI host controller
  392. */
  393. void (*host_setup)(struct dsi_ctrl_hw *ctrl,
  394. struct dsi_host_common_cfg *config);
  395. /**
  396. * video_engine_en() - enable DSI video engine
  397. * @ctrl: Pointer to controller host hardware.
  398. * @on: Enable/disabel video engine.
  399. */
  400. void (*video_engine_en)(struct dsi_ctrl_hw *ctrl, bool on);
  401. /**
  402. * setup_avr() - set the AVR_SUPPORT_ENABLE bit in DSI_VIDEO_MODE_CTRL
  403. * @ctrl: Pointer to controller host hardware.
  404. * @enable: Controls whether this bit is set or cleared
  405. */
  406. void (*setup_avr)(struct dsi_ctrl_hw *ctrl, bool enable);
  407. /**
  408. * video_engine_setup() - Setup dsi host controller for video mode
  409. * @ctrl: Pointer to controller host hardware.
  410. * @common_cfg: Common configuration parameters.
  411. * @cfg: Video mode configuration.
  412. *
  413. * Set up DSI video engine with a specific configuration. Controller and
  414. * video engine are not enabled as part of this function.
  415. */
  416. void (*video_engine_setup)(struct dsi_ctrl_hw *ctrl,
  417. struct dsi_host_common_cfg *common_cfg,
  418. struct dsi_video_engine_cfg *cfg);
  419. /**
  420. * set_video_timing() - set up the timing for video frame
  421. * @ctrl: Pointer to controller host hardware.
  422. * @mode: Video mode information.
  423. *
  424. * Set up the video timing parameters for the DSI video mode operation.
  425. */
  426. void (*set_video_timing)(struct dsi_ctrl_hw *ctrl,
  427. struct dsi_mode_info *mode);
  428. /**
  429. * cmd_engine_setup() - setup dsi host controller for command mode
  430. * @ctrl: Pointer to the controller host hardware.
  431. * @common_cfg: Common configuration parameters.
  432. * @cfg: Command mode configuration.
  433. *
  434. * Setup DSI CMD engine with a specific configuration. Controller and
  435. * command engine are not enabled as part of this function.
  436. */
  437. void (*cmd_engine_setup)(struct dsi_ctrl_hw *ctrl,
  438. struct dsi_host_common_cfg *common_cfg,
  439. struct dsi_cmd_engine_cfg *cfg);
  440. /**
  441. * setup_cmd_stream() - set up parameters for command pixel streams
  442. * @ctrl: Pointer to controller host hardware.
  443. * @mode: Pointer to mode information.
  444. * @cfg: DSI host configuration that is common to both
  445. * video and command modes.
  446. * @vc_id: stream_id.
  447. *
  448. * Setup parameters for command mode pixel stream size.
  449. */
  450. void (*setup_cmd_stream)(struct dsi_ctrl_hw *ctrl,
  451. struct dsi_mode_info *mode,
  452. struct dsi_host_common_cfg *cfg,
  453. u32 vc_id,
  454. struct dsi_rect *roi);
  455. /**
  456. * ctrl_en() - enable DSI controller engine
  457. * @ctrl: Pointer to the controller host hardware.
  458. * @on: turn on/off the DSI controller engine.
  459. */
  460. void (*ctrl_en)(struct dsi_ctrl_hw *ctrl, bool on);
  461. /**
  462. * cmd_engine_en() - enable DSI controller command engine
  463. * @ctrl: Pointer to the controller host hardware.
  464. * @on: Turn on/off the DSI command engine.
  465. */
  466. void (*cmd_engine_en)(struct dsi_ctrl_hw *ctrl, bool on);
  467. /**
  468. * phy_sw_reset() - perform a soft reset on the PHY.
  469. * @ctrl: Pointer to the controller host hardware.
  470. */
  471. void (*phy_sw_reset)(struct dsi_ctrl_hw *ctrl);
  472. /**
  473. * config_clk_gating() - enable/disable DSI PHY clk gating
  474. * @ctrl: Pointer to the controller host hardware.
  475. * @enable: enable/disable DSI PHY clock gating.
  476. * @clk_selection: clock to enable/disable clock gating.
  477. */
  478. void (*config_clk_gating)(struct dsi_ctrl_hw *ctrl, bool enable,
  479. enum dsi_clk_gate_type clk_selection);
  480. /**
  481. * soft_reset() - perform a soft reset on DSI controller
  482. * @ctrl: Pointer to the controller host hardware.
  483. *
  484. * The video, command and controller engines will be disabled before the
  485. * reset is triggered. After, the engines will be re-enabled to the same
  486. * state as before the reset.
  487. *
  488. * If the reset is done while MDP timing engine is turned on, the video
  489. * engine should be re-enabled only during the vertical blanking time.
  490. */
  491. void (*soft_reset)(struct dsi_ctrl_hw *ctrl);
  492. /**
  493. * setup_lane_map() - setup mapping between logical and physical lanes
  494. * @ctrl: Pointer to the controller host hardware.
  495. * @lane_map: Structure defining the mapping between DSI logical
  496. * lanes and physical lanes.
  497. */
  498. void (*setup_lane_map)(struct dsi_ctrl_hw *ctrl,
  499. struct dsi_lane_map *lane_map);
  500. /**
  501. * kickoff_command() - transmits commands stored in memory
  502. * @ctrl: Pointer to the controller host hardware.
  503. * @cmd: Command information.
  504. * @flags: Modifiers for command transmission.
  505. *
  506. * The controller hardware is programmed with address and size of the
  507. * command buffer. The transmission is kicked off if
  508. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
  509. * set, caller should make a separate call to trigger_command_dma() to
  510. * transmit the command.
  511. */
  512. void (*kickoff_command)(struct dsi_ctrl_hw *ctrl,
  513. struct dsi_ctrl_cmd_dma_info *cmd,
  514. u32 flags);
  515. /**
  516. * kickoff_command_non_embedded_mode() - cmd in non embedded mode
  517. * @ctrl: Pointer to the controller host hardware.
  518. * @cmd: Command information.
  519. * @flags: Modifiers for command transmission.
  520. *
  521. * If command length is greater than DMA FIFO size of 256 bytes we use
  522. * this non- embedded mode.
  523. * The controller hardware is programmed with address and size of the
  524. * command buffer. The transmission is kicked off if
  525. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
  526. * set, caller should make a separate call to trigger_command_dma() to
  527. * transmit the command.
  528. */
  529. void (*kickoff_command_non_embedded_mode)(struct dsi_ctrl_hw *ctrl,
  530. struct dsi_ctrl_cmd_dma_info *cmd,
  531. u32 flags);
  532. /**
  533. * kickoff_fifo_command() - transmits a command using FIFO in dsi
  534. * hardware.
  535. * @ctrl: Pointer to the controller host hardware.
  536. * @cmd: Command information.
  537. * @flags: Modifiers for command transmission.
  538. *
  539. * The controller hardware FIFO is programmed with command header and
  540. * payload. The transmission is kicked off if
  541. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
  542. * set, caller should make a separate call to trigger_command_dma() to
  543. * transmit the command.
  544. */
  545. void (*kickoff_fifo_command)(struct dsi_ctrl_hw *ctrl,
  546. struct dsi_ctrl_cmd_dma_fifo_info *cmd,
  547. u32 flags);
  548. void (*reset_cmd_fifo)(struct dsi_ctrl_hw *ctrl);
  549. /**
  550. * trigger_command_dma() - trigger transmission of command buffer.
  551. * @ctrl: Pointer to the controller host hardware.
  552. *
  553. * This trigger can be only used if there was a prior call to
  554. * kickoff_command() of kickoff_fifo_command() with
  555. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag.
  556. */
  557. void (*trigger_command_dma)(struct dsi_ctrl_hw *ctrl);
  558. /**
  559. * get_cmd_read_data() - get data read from the peripheral
  560. * @ctrl: Pointer to the controller host hardware.
  561. * @rd_buf: Buffer where data will be read into.
  562. * @read_offset: Offset from where to read.
  563. * @rx_byte: Number of bytes to be read.
  564. * @pkt_size: Size of response expected.
  565. * @hw_read_cnt: Actual number of bytes read by HW.
  566. */
  567. u32 (*get_cmd_read_data)(struct dsi_ctrl_hw *ctrl,
  568. u8 *rd_buf,
  569. u32 read_offset,
  570. u32 rx_byte,
  571. u32 pkt_size,
  572. u32 *hw_read_cnt);
  573. /**
  574. * wait_for_lane_idle() - wait for DSI lanes to go to idle state
  575. * @ctrl: Pointer to the controller host hardware.
  576. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  577. * to be checked to be in idle state.
  578. */
  579. int (*wait_for_lane_idle)(struct dsi_ctrl_hw *ctrl, u32 lanes);
  580. struct ctrl_ulps_config_ops ulps_ops;
  581. /**
  582. * clamp_enable() - enable DSI clamps
  583. * @ctrl: Pointer to the controller host hardware.
  584. * @lanes: ORed list of lanes which need to have clamps released.
  585. * @enable_ulps: ulps state.
  586. */
  587. /**
  588. * clamp_enable() - enable DSI clamps to keep PHY driving a stable link
  589. * @ctrl: Pointer to the controller host hardware.
  590. * @lanes: ORed list of lanes which need to have clamps released.
  591. * @enable_ulps: TODO:??
  592. */
  593. void (*clamp_enable)(struct dsi_ctrl_hw *ctrl,
  594. u32 lanes,
  595. bool enable_ulps);
  596. /**
  597. * clamp_disable() - disable DSI clamps
  598. * @ctrl: Pointer to the controller host hardware.
  599. * @lanes: ORed list of lanes which need to have clamps released.
  600. * @disable_ulps: ulps state.
  601. */
  602. void (*clamp_disable)(struct dsi_ctrl_hw *ctrl,
  603. u32 lanes,
  604. bool disable_ulps);
  605. /**
  606. * phy_reset_config() - Disable/enable propagation of reset signal
  607. * from ahb domain to DSI PHY
  608. * @ctrl: Pointer to the controller host hardware.
  609. * @enable: True to mask the reset signal, false to unmask
  610. */
  611. void (*phy_reset_config)(struct dsi_ctrl_hw *ctrl,
  612. bool enable);
  613. /**
  614. * get_interrupt_status() - returns the interrupt status
  615. * @ctrl: Pointer to the controller host hardware.
  616. *
  617. * Returns the ORed list of interrupts(enum dsi_status_int_type) that
  618. * are active. This list does not include any error interrupts. Caller
  619. * should call get_error_status for error interrupts.
  620. *
  621. * Return: List of active interrupts.
  622. */
  623. u32 (*get_interrupt_status)(struct dsi_ctrl_hw *ctrl);
  624. /**
  625. * clear_interrupt_status() - clears the specified interrupts
  626. * @ctrl: Pointer to the controller host hardware.
  627. * @ints: List of interrupts to be cleared.
  628. */
  629. void (*clear_interrupt_status)(struct dsi_ctrl_hw *ctrl, u32 ints);
  630. /**
  631. * poll_dma_status()- API to poll DMA status
  632. * @ctrl: Pointer to the controller host hardware.
  633. */
  634. u32 (*poll_dma_status)(struct dsi_ctrl_hw *ctrl);
  635. /**
  636. * enable_status_interrupts() - enable the specified interrupts
  637. * @ctrl: Pointer to the controller host hardware.
  638. * @ints: List of interrupts to be enabled.
  639. *
  640. * Enables the specified interrupts. This list will override the
  641. * previous interrupts enabled through this function. Caller has to
  642. * maintain the state of the interrupts enabled. To disable all
  643. * interrupts, set ints to 0.
  644. */
  645. void (*enable_status_interrupts)(struct dsi_ctrl_hw *ctrl, u32 ints);
  646. /**
  647. * get_error_status() - returns the error status
  648. * @ctrl: Pointer to the controller host hardware.
  649. *
  650. * Returns the ORed list of errors(enum dsi_error_int_type) that are
  651. * active. This list does not include any status interrupts. Caller
  652. * should call get_interrupt_status for status interrupts.
  653. *
  654. * Return: List of active error interrupts.
  655. */
  656. u64 (*get_error_status)(struct dsi_ctrl_hw *ctrl);
  657. /**
  658. * clear_error_status() - clears the specified errors
  659. * @ctrl: Pointer to the controller host hardware.
  660. * @errors: List of errors to be cleared.
  661. */
  662. void (*clear_error_status)(struct dsi_ctrl_hw *ctrl, u64 errors);
  663. /**
  664. * enable_error_interrupts() - enable the specified interrupts
  665. * @ctrl: Pointer to the controller host hardware.
  666. * @errors: List of errors to be enabled.
  667. *
  668. * Enables the specified interrupts. This list will override the
  669. * previous interrupts enabled through this function. Caller has to
  670. * maintain the state of the interrupts enabled. To disable all
  671. * interrupts, set errors to 0.
  672. */
  673. void (*enable_error_interrupts)(struct dsi_ctrl_hw *ctrl, u64 errors);
  674. /**
  675. * video_test_pattern_setup() - setup test pattern engine for video mode
  676. * @ctrl: Pointer to the controller host hardware.
  677. * @type: Type of test pattern.
  678. * @init_val: Initial value to use for generating test pattern.
  679. */
  680. void (*video_test_pattern_setup)(struct dsi_ctrl_hw *ctrl,
  681. enum dsi_test_pattern type,
  682. u32 init_val);
  683. /**
  684. * cmd_test_pattern_setup() - setup test patttern engine for cmd mode
  685. * @ctrl: Pointer to the controller host hardware.
  686. * @type: Type of test pattern.
  687. * @init_val: Initial value to use for generating test pattern.
  688. * @stream_id: Stream Id on which packets are generated.
  689. */
  690. void (*cmd_test_pattern_setup)(struct dsi_ctrl_hw *ctrl,
  691. enum dsi_test_pattern type,
  692. u32 init_val,
  693. u32 stream_id);
  694. /**
  695. * test_pattern_enable() - enable test pattern engine
  696. * @ctrl: Pointer to the controller host hardware.
  697. * @enable: Enable/Disable test pattern engine.
  698. * @pattern: Type of TPG pattern
  699. * @panel_mode: DSI operation mode
  700. */
  701. void (*test_pattern_enable)(struct dsi_ctrl_hw *ctrl, bool enable,
  702. enum dsi_ctrl_tpg_pattern pattern,
  703. enum dsi_op_mode panel_mode);
  704. /**
  705. * clear_phy0_ln_err() - clear DSI PHY lane-0 errors
  706. * @ctrl: Pointer to the controller host hardware.
  707. */
  708. void (*clear_phy0_ln_err)(struct dsi_ctrl_hw *ctrl);
  709. /**
  710. * trigger_cmd_test_pattern() - trigger a command mode frame update with
  711. * test pattern
  712. * @ctrl: Pointer to the controller host hardware.
  713. * @stream_id: Stream on which frame update is sent.
  714. */
  715. void (*trigger_cmd_test_pattern)(struct dsi_ctrl_hw *ctrl,
  716. u32 stream_id);
  717. ssize_t (*reg_dump_to_buffer)(struct dsi_ctrl_hw *ctrl,
  718. char *buf,
  719. u32 size);
  720. /**
  721. * setup_misr() - Setup frame MISR
  722. * @ctrl: Pointer to the controller host hardware.
  723. * @panel_mode: CMD or VIDEO mode indicator
  724. * @enable: Enable/disable MISR.
  725. * @frame_count: Number of frames to accumulate MISR.
  726. */
  727. void (*setup_misr)(struct dsi_ctrl_hw *ctrl,
  728. enum dsi_op_mode panel_mode,
  729. bool enable, u32 frame_count);
  730. /**
  731. * collect_misr() - Read frame MISR
  732. * @ctrl: Pointer to the controller host hardware.
  733. * @panel_mode: CMD or VIDEO mode indicator
  734. */
  735. u32 (*collect_misr)(struct dsi_ctrl_hw *ctrl,
  736. enum dsi_op_mode panel_mode);
  737. /**
  738. * set_timing_db() - enable/disable Timing DB register
  739. * @ctrl: Pointer to controller host hardware.
  740. * @enable: Enable/Disable flag.
  741. *
  742. * Enable or Disabe the Timing DB register.
  743. */
  744. void (*set_timing_db)(struct dsi_ctrl_hw *ctrl,
  745. bool enable);
  746. /**
  747. * clear_rdbk_register() - Clear and reset read back register
  748. * @ctrl: Pointer to the controller host hardware.
  749. */
  750. void (*clear_rdbk_register)(struct dsi_ctrl_hw *ctrl);
  751. /** schedule_dma_cmd() - Schdeule DMA command transfer on a
  752. * particular blanking line.
  753. * @ctrl: Pointer to the controller host hardware.
  754. * @line_no: Blanking line number on whihch DMA command
  755. * needs to be sent.
  756. */
  757. void (*schedule_dma_cmd)(struct dsi_ctrl_hw *ctrl, int line_no);
  758. /**
  759. * ctrl_reset() - Reset DSI lanes to recover from DSI errors
  760. * @ctrl: Pointer to the controller host hardware.
  761. * @mask: Indicates the error type.
  762. */
  763. int (*ctrl_reset)(struct dsi_ctrl_hw *ctrl, int mask);
  764. /**
  765. * mask_error_int() - Mask/Unmask particular DSI error interrupts
  766. * @ctrl: Pointer to the controller host hardware.
  767. * @idx: Indicates the errors to be masked.
  768. * @en: Bool for mask or unmask of the error
  769. */
  770. void (*mask_error_intr)(struct dsi_ctrl_hw *ctrl, u32 idx, bool en);
  771. /**
  772. * error_intr_ctrl() - Mask/Unmask master DSI error interrupt
  773. * @ctrl: Pointer to the controller host hardware.
  774. * @en: Bool for mask or unmask of DSI error
  775. */
  776. void (*error_intr_ctrl)(struct dsi_ctrl_hw *ctrl, bool en);
  777. /**
  778. * get_error_mask() - get DSI error interrupt mask status
  779. * @ctrl: Pointer to the controller host hardware.
  780. */
  781. u32 (*get_error_mask)(struct dsi_ctrl_hw *ctrl);
  782. /**
  783. * get_hw_version() - get DSI controller hw version
  784. * @ctrl: Pointer to the controller host hardware.
  785. */
  786. u32 (*get_hw_version)(struct dsi_ctrl_hw *ctrl);
  787. /**
  788. * wait_for_cmd_mode_mdp_idle() - wait for command mode engine not to
  789. * be busy sending data from display engine
  790. * @ctrl: Pointer to the controller host hardware.
  791. */
  792. int (*wait_for_cmd_mode_mdp_idle)(struct dsi_ctrl_hw *ctrl);
  793. /**
  794. * hw.ops.set_continuous_clk() - Set continuous clock
  795. * @ctrl: Pointer to the controller host hardware.
  796. * @enable: Bool to control continuous clock request.
  797. */
  798. void (*set_continuous_clk)(struct dsi_ctrl_hw *ctrl, bool enable);
  799. /**
  800. * hw.ops.wait4dynamic_refresh_done() - Wait for dynamic refresh done
  801. * @ctrl: Pointer to the controller host hardware.
  802. */
  803. int (*wait4dynamic_refresh_done)(struct dsi_ctrl_hw *ctrl);
  804. /**
  805. * hw.ops.vid_engine_busy() - Returns true if vid engine is busy
  806. * @ctrl: Pointer to the controller host hardware.
  807. */
  808. bool (*vid_engine_busy)(struct dsi_ctrl_hw *ctrl);
  809. /**
  810. * hw.ops.hs_req_sel() - enable continuous clk support through phy
  811. * @ctrl: Pointer to the controller host hardware.
  812. * @sel_phy: Bool to control whether to select phy or controller
  813. */
  814. void (*hs_req_sel)(struct dsi_ctrl_hw *ctrl, bool sel_phy);
  815. /**
  816. * hw.ops.configure_cmddma_window() - configure DMA window for CMD TX
  817. * @ctrl: Pointer to the controller host hardware.
  818. * @cmd: Pointer to the DSI DMA command info.
  819. * @line_no: Line number at which the CMD needs to be triggered.
  820. * @window: Width of the DMA CMD window.
  821. */
  822. void (*configure_cmddma_window)(struct dsi_ctrl_hw *ctrl,
  823. struct dsi_ctrl_cmd_dma_info *cmd,
  824. u32 line_no, u32 window);
  825. /**
  826. * hw.ops.reset_trig_ctrl() - resets trigger control of DSI controller
  827. * @ctrl: Pointer to the controller host hardware.
  828. * @cfg: Common configuration parameters.
  829. */
  830. void (*reset_trig_ctrl)(struct dsi_ctrl_hw *ctrl,
  831. struct dsi_host_common_cfg *cfg);
  832. /**
  833. * hw.ops.log_line_count() - reads the MDP interface line count
  834. * registers.
  835. * @ctrl: Pointer to the controller host hardware.
  836. * @cmd_mode: Boolean to indicate command mode operation.
  837. */
  838. u32 (*log_line_count)(struct dsi_ctrl_hw *ctrl, bool cmd_mode);
  839. /**
  840. * hw.ops.splitlink_cmd_setup() - configure the sublink to transfer
  841. * @ctrl: Pointer to the controller host hardware.
  842. * @common_cfg: Common configuration parameters.
  843. * @sublink: Which sublink to transfer the command.
  844. */
  845. void (*splitlink_cmd_setup)(struct dsi_ctrl_hw *ctrl,
  846. struct dsi_host_common_cfg *common_cfg, u32 sublink);
  847. };
  848. /*
  849. * struct dsi_ctrl_hw - DSI controller hardware object specific to an instance
  850. * @base: VA for the DSI controller base address.
  851. * @length: Length of the DSI controller register map.
  852. * @mmss_misc_base: Base address of mmss_misc register map.
  853. * @mmss_misc_length: Length of mmss_misc register map.
  854. * @disp_cc_base: Base address of disp_cc register map.
  855. * @disp_cc_length: Length of disp_cc register map.
  856. * @mdp_intf_base: Base address of mdp_intf register map. Addresses of
  857. * MDP_TEAR_INTF_TEAR_LINE_COUNT and MDP_TEAR_INTF_LINE_COUNT
  858. * are mapped using the base address to test and validate
  859. * the RD ptr value and line count value respectively when
  860. * a CMD is triggered and it succeeds.
  861. * @index: Instance ID of the controller.
  862. * @feature_map: Features supported by the DSI controller.
  863. * @ops: Function pointers to the operations supported by the
  864. * controller.
  865. * @supported_interrupts: Number of supported interrupts.
  866. * @supported_errors: Number of supported errors.
  867. * @phy_isolation_enabled: A boolean property allows to isolate the phy from
  868. * dsi controller and run only dsi controller.
  869. * @null_insertion_enabled: A boolean property to allow dsi controller to
  870. * insert null packet.
  871. * @widebus_support: 48 bit wide data bus is supported.
  872. * @reset_trig_ctrl: Boolean to indicate if trigger control needs to
  873. * be reset to default.
  874. */
  875. struct dsi_ctrl_hw {
  876. void __iomem *base;
  877. u32 length;
  878. void __iomem *mmss_misc_base;
  879. u32 mmss_misc_length;
  880. void __iomem *disp_cc_base;
  881. u32 disp_cc_length;
  882. void __iomem *mdp_intf_base;
  883. u32 index;
  884. /* features */
  885. DECLARE_BITMAP(feature_map, DSI_CTRL_MAX_FEATURES);
  886. struct dsi_ctrl_hw_ops ops;
  887. /* capabilities */
  888. u32 supported_interrupts;
  889. u64 supported_errors;
  890. bool phy_isolation_enabled;
  891. bool null_insertion_enabled;
  892. bool widebus_support;
  893. bool reset_trig_ctrl;
  894. };
  895. #endif /* _DSI_CTRL_HW_H_ */