msm_sdw.h 4.3 KB

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  1. /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #ifndef MSM_SDW_H
  13. #define MSM_SDW_H
  14. #include <sound/soc.h>
  15. #include <sound/q6afe-v2.h>
  16. #include "msm_sdw_registers.h"
  17. #define MSM_SDW_MAX_REGISTER 0x400
  18. extern const struct regmap_config msm_sdw_regmap_config;
  19. extern const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER];
  20. extern const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER];
  21. extern const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER];
  22. enum {
  23. MSM_SDW_RX4 = 0,
  24. MSM_SDW_RX5,
  25. MSM_SDW_RX_MAX,
  26. };
  27. enum {
  28. MSM_SDW_TX0 = 0,
  29. MSM_SDW_TX1,
  30. MSM_SDW_TX_MAX,
  31. };
  32. enum {
  33. COMP1, /* SPK_L */
  34. COMP2, /* SPK_R */
  35. COMP_MAX
  36. };
  37. /*
  38. * Structure used to update codec
  39. * register defaults after reset
  40. */
  41. struct msm_sdw_reg_mask_val {
  42. u16 reg;
  43. u8 mask;
  44. u8 val;
  45. };
  46. /*
  47. * Selects compander and smart boost settings
  48. * for a given speaker mode
  49. */
  50. enum {
  51. SPKR_MODE_DEFAULT,
  52. SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
  53. };
  54. /* Rx path gain offsets */
  55. enum {
  56. RX_GAIN_OFFSET_M1P5_DB,
  57. RX_GAIN_OFFSET_0_DB,
  58. };
  59. struct msm_sdw_reg_val {
  60. unsigned short reg; /* register address */
  61. u8 *buf; /* buffer to be written to reg. addr */
  62. int bytes; /* number of bytes to be written */
  63. };
  64. /* Hold instance to soundwire platform device */
  65. struct msm_sdw_ctrl_data {
  66. struct platform_device *sdw_pdev;
  67. };
  68. struct wcd_sdw_ctrl_platform_data {
  69. void *handle; /* holds codec private data */
  70. int (*read)(void *handle, int reg);
  71. int (*write)(void *handle, int reg, int val);
  72. int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
  73. int (*clk)(void *handle, bool enable);
  74. int (*handle_irq)(void *handle,
  75. irqreturn_t (*swrm_irq_handler)(int irq,
  76. void *data),
  77. void *swrm_handle,
  78. int action);
  79. };
  80. struct msm_sdw_priv {
  81. struct device *dev;
  82. struct mutex io_lock;
  83. int (*read_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
  84. int bytes, void *dest);
  85. int (*write_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
  86. int bytes, void *src);
  87. int (*multi_reg_write)(struct msm_sdw_priv *msm_sdw, const void *data,
  88. size_t count);
  89. struct snd_soc_codec *codec;
  90. struct device_node *sdw_gpio_p; /* used by pinctrl API */
  91. /* SoundWire data structure */
  92. struct msm_sdw_ctrl_data *sdw_ctrl_data;
  93. int nr;
  94. /* compander */
  95. int comp_enabled[COMP_MAX];
  96. int ear_spkr_gain;
  97. /* to track the status */
  98. unsigned long status_mask;
  99. struct work_struct msm_sdw_add_child_devices_work;
  100. struct wcd_sdw_ctrl_platform_data sdw_plat_data;
  101. unsigned int vi_feed_value;
  102. struct mutex sdw_read_lock;
  103. struct mutex sdw_write_lock;
  104. struct mutex sdw_clk_lock;
  105. int sdw_clk_users;
  106. int sdw_mclk_users;
  107. int sdw_irq;
  108. int int_mclk1_rsc_ref;
  109. bool int_mclk1_enabled;
  110. bool sdw_npl_clk_enabled;
  111. struct mutex cdc_int_mclk1_mutex;
  112. struct mutex sdw_npl_clk_mutex;
  113. struct delayed_work disable_int_mclk1_work;
  114. struct afe_clk_set sdw_cdc_core_clk;
  115. struct afe_clk_set sdw_npl_clk;
  116. struct notifier_block service_nb;
  117. int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec);
  118. bool dev_up;
  119. int spkr_gain_offset;
  120. int spkr_mode;
  121. struct mutex codec_mutex;
  122. int rx_4_count;
  123. int rx_5_count;
  124. u32 mclk_rate;
  125. struct regmap *regmap;
  126. bool prev_pg_valid;
  127. u8 prev_pg;
  128. u32 sdw_base_addr;
  129. char __iomem *sdw_base;
  130. u32 version;
  131. /* Entry for version info */
  132. struct snd_info_entry *entry;
  133. struct snd_info_entry *version_entry;
  134. };
  135. extern int msm_sdw_set_spkr_mode(struct snd_soc_codec *codec, int mode);
  136. extern int msm_sdw_set_spkr_gain_offset(struct snd_soc_codec *codec,
  137. int offset);
  138. extern void msm_sdw_gpio_cb(
  139. int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec),
  140. struct snd_soc_codec *codec);
  141. extern struct regmap *msm_sdw_regmap_init(struct device *dev,
  142. const struct regmap_config *config);
  143. extern int msm_sdw_codec_info_create_codec_entry(
  144. struct snd_info_entry *codec_root,
  145. struct snd_soc_codec *codec);
  146. #endif