core.h 12 KB

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  1. /* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #ifndef __MFD_TABLA_CORE_H__
  13. #define __MFD_TABLA_CORE_H__
  14. #include <linux/types.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/pm_qos.h>
  19. #define WCD9XXX_MAX_IRQ_REGS 4
  20. #define WCD9XXX_MAX_NUM_IRQS (WCD9XXX_MAX_IRQ_REGS * 8)
  21. #define WCD9XXX_SLIM_NUM_PORT_REG 3
  22. #define TABLA_VERSION_1_0 0
  23. #define TABLA_VERSION_1_1 1
  24. #define TABLA_VERSION_2_0 2
  25. #define TABLA_IS_1_X(ver) \
  26. (((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0)
  27. #define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0)
  28. #define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck"
  29. #define SITAR_VERSION_1P0 0
  30. #define SITAR_VERSION_1P1 1
  31. #define SITAR_IS_1P0(ver) \
  32. ((ver == SITAR_VERSION_1P0) ? 1 : 0)
  33. #define SITAR_IS_1P1(ver) \
  34. ((ver == SITAR_VERSION_1P1) ? 1 : 0)
  35. #define TAIKO_VERSION_1_0 1
  36. #define TAIKO_IS_1_0(ver) \
  37. ((ver == TAIKO_VERSION_1_0) ? 1 : 0)
  38. #define TAPAN_VERSION_1_0 0
  39. #define TAPAN_IS_1_0(ver) \
  40. ((ver == TAPAN_VERSION_1_0) ? 1 : 0)
  41. #define TOMTOM_VERSION_1_0 1
  42. #define TOMTOM_IS_1_0(ver) \
  43. ((ver == TOMTOM_VERSION_1_0) ? 1 : 0)
  44. #define TASHA_VERSION_1_0 0
  45. #define TASHA_VERSION_1_1 1
  46. #define TASHA_VERSION_2_0 2
  47. #define TASHA_IS_1_0(wcd) \
  48. ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
  49. ((wcd->version == TASHA_VERSION_1_0) ? 1 : 0) : 0)
  50. #define TASHA_IS_1_1(wcd) \
  51. ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
  52. ((wcd->version == TASHA_VERSION_1_1) ? 1 : 0) : 0)
  53. #define TASHA_IS_2_0(wcd) \
  54. ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
  55. ((wcd->version == TASHA_VERSION_2_0) ? 1 : 0) : 0)
  56. /*
  57. * As fine version info cannot be retrieved before tavil probe.
  58. * Define three coarse versions for possible future use before tavil probe.
  59. */
  60. #define TAVIL_VERSION_1_0 0
  61. #define TAVIL_VERSION_1_1 1
  62. #define TAVIL_VERSION_WCD9340_1_0 2
  63. #define TAVIL_VERSION_WCD9341_1_0 3
  64. #define TAVIL_VERSION_WCD9340_1_1 4
  65. #define TAVIL_VERSION_WCD9341_1_1 5
  66. #define TAVIL_IS_1_0(wcd) \
  67. ((wcd->type == WCD934X) ? \
  68. ((wcd->version == TAVIL_VERSION_1_0 || \
  69. wcd->version == TAVIL_VERSION_WCD9340_1_0 || \
  70. wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
  71. #define TAVIL_IS_1_1(wcd) \
  72. ((wcd->type == WCD934X) ? \
  73. ((wcd->version == TAVIL_VERSION_1_1 || \
  74. wcd->version == TAVIL_VERSION_WCD9340_1_1 || \
  75. wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
  76. #define TAVIL_IS_WCD9340_1_0(wcd) \
  77. ((wcd->type == WCD934X) ? \
  78. ((wcd->version == TAVIL_VERSION_WCD9340_1_0) ? 1 : 0) : 0)
  79. #define TAVIL_IS_WCD9341_1_0(wcd) \
  80. ((wcd->type == WCD934X) ? \
  81. ((wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
  82. #define TAVIL_IS_WCD9340_1_1(wcd) \
  83. ((wcd->type == WCD934X) ? \
  84. ((wcd->version == TAVIL_VERSION_WCD9340_1_1) ? 1 : 0) : 0)
  85. #define TAVIL_IS_WCD9341_1_1(wcd) \
  86. ((wcd->type == WCD934X) ? \
  87. ((wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
  88. #define IS_CODEC_TYPE(wcd, wcdtype) \
  89. ((wcd->type == wcdtype) ? true : false)
  90. #define IS_CODEC_VERSION(wcd, wcdversion) \
  91. ((wcd->version == wcdversion) ? true : false)
  92. enum {
  93. CDC_V_1_0,
  94. CDC_V_1_1,
  95. CDC_V_2_0,
  96. };
  97. enum codec_variant {
  98. WCD9XXX,
  99. WCD9330,
  100. WCD9335,
  101. WCD9326,
  102. WCD934X,
  103. };
  104. enum wcd9xxx_slim_slave_addr_type {
  105. WCD9XXX_SLIM_SLAVE_ADDR_TYPE_0,
  106. WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1,
  107. };
  108. enum wcd9xxx_pm_state {
  109. WCD9XXX_PM_SLEEPABLE,
  110. WCD9XXX_PM_AWAKE,
  111. WCD9XXX_PM_ASLEEP,
  112. };
  113. enum {
  114. WCD9XXX_INTR_STATUS_BASE = 0,
  115. WCD9XXX_INTR_CLEAR_BASE,
  116. WCD9XXX_INTR_MASK_BASE,
  117. WCD9XXX_INTR_LEVEL_BASE,
  118. WCD9XXX_INTR_CLR_COMMIT,
  119. WCD9XXX_INTR_REG_MAX,
  120. };
  121. enum wcd9xxx_intf_status {
  122. WCD9XXX_INTERFACE_TYPE_PROBING,
  123. WCD9XXX_INTERFACE_TYPE_SLIMBUS,
  124. WCD9XXX_INTERFACE_TYPE_I2C,
  125. };
  126. enum {
  127. /* INTR_REG 0 */
  128. WCD9XXX_IRQ_SLIMBUS = 0,
  129. WCD9XXX_IRQ_MBHC_REMOVAL,
  130. WCD9XXX_IRQ_MBHC_SHORT_TERM,
  131. WCD9XXX_IRQ_MBHC_PRESS,
  132. WCD9XXX_IRQ_MBHC_RELEASE,
  133. WCD9XXX_IRQ_MBHC_POTENTIAL,
  134. WCD9XXX_IRQ_MBHC_INSERTION,
  135. WCD9XXX_IRQ_BG_PRECHARGE,
  136. /* INTR_REG 1 */
  137. WCD9XXX_IRQ_PA1_STARTUP,
  138. WCD9XXX_IRQ_PA2_STARTUP,
  139. WCD9XXX_IRQ_PA3_STARTUP,
  140. WCD9XXX_IRQ_PA4_STARTUP,
  141. WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP,
  142. WCD9XXX_IRQ_PA5_STARTUP,
  143. WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
  144. WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
  145. WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
  146. WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
  147. /* INTR_REG 2 */
  148. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
  149. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
  150. WCD9XXX_IRQ_EAR_PA_OCPL_FAULT,
  151. WCD9XXX_IRQ_HPH_L_PA_STARTUP,
  152. WCD9XXX_IRQ_HPH_R_PA_STARTUP,
  153. WCD9320_IRQ_EAR_PA_STARTUP,
  154. WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP,
  155. WCD9310_NUM_IRQS,
  156. WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS,
  157. WCD9XXX_IRQ_RESERVED_1,
  158. WCD9330_IRQ_SVASS_ERR_EXCEPTION = WCD9310_NUM_IRQS,
  159. WCD9330_IRQ_MBHC_JACK_SWITCH,
  160. /* INTR_REG 3 */
  161. WCD9XXX_IRQ_MAD_AUDIO,
  162. WCD9XXX_IRQ_MAD_ULTRASOUND,
  163. WCD9XXX_IRQ_MAD_BEACON,
  164. WCD9XXX_IRQ_SPEAKER_CLIPPING,
  165. WCD9320_IRQ_MBHC_JACK_SWITCH,
  166. WCD9306_NUM_IRQS,
  167. WCD9XXX_IRQ_VBAT_MONITOR_ATTACK = WCD9306_NUM_IRQS,
  168. WCD9XXX_IRQ_VBAT_MONITOR_RELEASE,
  169. WCD9XXX_NUM_IRQS,
  170. /* WCD9330 INTR1_REG 3*/
  171. WCD9330_IRQ_SVASS_ENGINE = WCD9XXX_IRQ_MAD_AUDIO,
  172. WCD9330_IRQ_MAD_AUDIO,
  173. WCD9330_IRQ_MAD_ULTRASOUND,
  174. WCD9330_IRQ_MAD_BEACON,
  175. WCD9330_IRQ_SPEAKER1_CLIPPING,
  176. WCD9330_IRQ_SPEAKER2_CLIPPING,
  177. WCD9330_IRQ_VBAT_MONITOR_ATTACK,
  178. WCD9330_IRQ_VBAT_MONITOR_RELEASE,
  179. WCD9330_NUM_IRQS,
  180. WCD9XXX_IRQ_RESERVED_2 = WCD9330_NUM_IRQS,
  181. };
  182. enum {
  183. TABLA_NUM_IRQS = WCD9310_NUM_IRQS,
  184. SITAR_NUM_IRQS = WCD9310_NUM_IRQS,
  185. TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
  186. TAPAN_NUM_IRQS = WCD9306_NUM_IRQS,
  187. TOMTOM_NUM_IRQS = WCD9330_NUM_IRQS,
  188. };
  189. struct intr_data {
  190. int intr_num;
  191. bool clear_first;
  192. };
  193. struct wcd9xxx_core_resource {
  194. struct mutex irq_lock;
  195. struct mutex nested_irq_lock;
  196. enum wcd9xxx_pm_state pm_state;
  197. struct mutex pm_lock;
  198. /* pm_wq notifies change of pm_state */
  199. wait_queue_head_t pm_wq;
  200. struct pm_qos_request pm_qos_req;
  201. int wlock_holders;
  202. /* holds the table of interrupts per codec */
  203. const struct intr_data *intr_table;
  204. int intr_table_size;
  205. unsigned int irq_base;
  206. unsigned int irq;
  207. u8 irq_masks_cur[WCD9XXX_MAX_IRQ_REGS];
  208. u8 irq_masks_cache[WCD9XXX_MAX_IRQ_REGS];
  209. bool irq_level_high[WCD9XXX_MAX_NUM_IRQS];
  210. int num_irqs;
  211. int num_irq_regs;
  212. u16 intr_reg[WCD9XXX_INTR_REG_MAX];
  213. struct regmap *wcd_core_regmap;
  214. /* Pointer to parent container data structure */
  215. void *parent;
  216. struct device *dev;
  217. struct irq_domain *domain;
  218. };
  219. /*
  220. * data structure for Slimbus and I2S channel.
  221. * Some of fields are only used in smilbus mode
  222. */
  223. struct wcd9xxx_ch {
  224. u32 sph; /* share channel handle - slimbus only */
  225. u32 ch_num; /*
  226. * vitrual channel number, such as 128 -144.
  227. * apply for slimbus only
  228. */
  229. u16 ch_h; /* chanel handle - slimbus only */
  230. u16 port; /*
  231. * tabla port for RX and TX
  232. * such as 0-9 for TX and 10 -16 for RX
  233. * apply for both i2s and slimbus
  234. */
  235. u16 shift; /*
  236. * shift bit for RX and TX
  237. * apply for both i2s and slimbus
  238. */
  239. struct list_head list; /*
  240. * channel link list
  241. * apply for both i2s and slimbus
  242. */
  243. };
  244. struct wcd9xxx_codec_dai_data {
  245. u32 rate; /* sample rate */
  246. u32 bit_width; /* sit width 16,24,32 */
  247. struct list_head wcd9xxx_ch_list; /* channel list */
  248. u16 grph; /* slimbus group handle */
  249. unsigned long ch_mask;
  250. wait_queue_head_t dai_wait;
  251. bool bus_down_in_recovery;
  252. };
  253. #define WCD9XXX_CH(xport, xshift) \
  254. {.port = xport, .shift = xshift}
  255. enum wcd9xxx_chipid_major {
  256. TABLA_MAJOR = cpu_to_le16(0x100),
  257. SITAR_MAJOR = cpu_to_le16(0x101),
  258. TAIKO_MAJOR = cpu_to_le16(0x102),
  259. TAPAN_MAJOR = cpu_to_le16(0x103),
  260. TOMTOM_MAJOR = cpu_to_le16(0x105),
  261. TASHA_MAJOR = cpu_to_le16(0x0),
  262. TASHA2P0_MAJOR = cpu_to_le16(0x107),
  263. TAVIL_MAJOR = cpu_to_le16(0x108),
  264. };
  265. enum codec_power_states {
  266. WCD_REGION_POWER_COLLAPSE_REMOVE,
  267. WCD_REGION_POWER_COLLAPSE_BEGIN,
  268. WCD_REGION_POWER_DOWN,
  269. };
  270. enum wcd_power_regions {
  271. WCD9XXX_DIG_CORE_REGION_1,
  272. WCD9XXX_MAX_PWR_REGIONS,
  273. };
  274. struct wcd9xxx_codec_type {
  275. u16 id_major;
  276. u16 id_minor;
  277. struct mfd_cell *dev;
  278. int size;
  279. int num_irqs;
  280. int version; /* -1 to retrieve version from chip version register */
  281. enum wcd9xxx_slim_slave_addr_type slim_slave_type;
  282. u16 i2c_chip_status;
  283. const struct intr_data *intr_tbl;
  284. int intr_tbl_size;
  285. u16 intr_reg[WCD9XXX_INTR_REG_MAX];
  286. };
  287. struct wcd9xxx_power_region {
  288. enum codec_power_states power_state;
  289. u16 pwr_collapse_reg_min;
  290. u16 pwr_collapse_reg_max;
  291. };
  292. struct wcd9xxx {
  293. struct device *dev;
  294. struct slim_device *slim;
  295. struct slim_device *slim_slave;
  296. struct mutex io_lock;
  297. struct mutex xfer_lock;
  298. struct mutex reset_lock;
  299. u8 version;
  300. int reset_gpio;
  301. struct device_node *wcd_rst_np;
  302. int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
  303. int bytes, void *dest, bool interface_reg);
  304. int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
  305. int bytes, void *src, bool interface_reg);
  306. int (*multi_reg_write)(struct wcd9xxx *wcd9xxx, const void *data,
  307. size_t count);
  308. int (*dev_down)(struct wcd9xxx *wcd9xxx);
  309. int (*post_reset)(struct wcd9xxx *wcd9xxx);
  310. void *ssr_priv;
  311. unsigned long dev_up;
  312. u32 num_of_supplies;
  313. struct regulator_bulk_data *supplies;
  314. struct wcd9xxx_core_resource core_res;
  315. u16 id_minor;
  316. u16 id_major;
  317. /* Slimbus or I2S port */
  318. u32 num_rx_port;
  319. u32 num_tx_port;
  320. struct wcd9xxx_ch *rx_chs;
  321. struct wcd9xxx_ch *tx_chs;
  322. u32 mclk_rate;
  323. enum codec_variant type;
  324. struct regmap *regmap;
  325. struct wcd9xxx_codec_type *codec_type;
  326. bool prev_pg_valid;
  327. u8 prev_pg;
  328. u8 avoid_cdc_rstlow;
  329. struct wcd9xxx_power_region *wcd9xxx_pwr[WCD9XXX_MAX_PWR_REGIONS];
  330. };
  331. struct wcd9xxx_reg_val {
  332. unsigned short reg; /* register address */
  333. u8 *buf; /* buffer to be written to reg. addr */
  334. int bytes; /* number of bytes to be written */
  335. };
  336. int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
  337. int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
  338. u8 val);
  339. int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la);
  340. int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
  341. int bytes, void *src);
  342. int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
  343. u32 bw_ops, bool commit);
  344. int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states,
  345. enum wcd_power_regions);
  346. int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
  347. enum wcd_power_regions);
  348. int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg);
  349. int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
  350. struct wcd9xxx_reg_val *bulk_reg,
  351. unsigned int size, bool interface);
  352. extern int wcd9xxx_core_res_init(
  353. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  354. int num_irqs, int num_irq_regs, struct regmap *wcd_regmap);
  355. extern void wcd9xxx_core_res_deinit(
  356. struct wcd9xxx_core_resource *wcd9xxx_core_res);
  357. extern int wcd9xxx_core_res_suspend(
  358. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  359. pm_message_t pmesg);
  360. extern int wcd9xxx_core_res_resume(
  361. struct wcd9xxx_core_resource *wcd9xxx_core_res);
  362. extern int wcd9xxx_core_irq_init(
  363. struct wcd9xxx_core_resource *wcd9xxx_core_res);
  364. extern int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
  365. unsigned int irq,
  366. unsigned int irq_base);
  367. extern enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void);
  368. extern void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status);
  369. extern enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
  370. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  371. enum wcd9xxx_pm_state o,
  372. enum wcd9xxx_pm_state n);
  373. static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
  374. struct device_node *parent)
  375. {
  376. return 0;
  377. }
  378. int wcd9xxx_init(void);
  379. void wcd9xxx_exit(void);
  380. #endif