internal.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _WCD939X_INTERNAL_H
  7. #define _WCD939X_INTERNAL_H
  8. #include <asoc/wcd-mbhc-v2.h>
  9. #include <asoc/wcd-irq.h>
  10. #include <asoc/wcd-clsh.h>
  11. #include <soc/soundwire.h>
  12. #include "wcd939x-mbhc.h"
  13. #include "wcd939x.h"
  14. #define SWR_SCP_CONTROL 0x44
  15. #define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
  16. #define WCD939X_MAX_MICBIAS 4
  17. /* Convert from vout ctl to micbias voltage in mV */
  18. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  19. #define MAX_PORT 8
  20. #define MAX_CH_PER_PORT 8
  21. #define TX_ADC_MAX 4
  22. #define SWR_NUM_PORTS 4
  23. enum {
  24. RX_CLK_9P6MHZ,
  25. RX_CLK_12P288MHZ,
  26. RX_CLK_11P2896MHZ,
  27. };
  28. enum {
  29. WCD939X_HPHL,
  30. WCD939X_HPHR,
  31. WCD939X_HPH_MAX,
  32. };
  33. enum {
  34. TX_HDR12 = 0,
  35. TX_HDR34,
  36. TX_HDR_MAX,
  37. };
  38. enum xtalk_mode {
  39. XTALK_NONE = 0,
  40. XTALK_DIGITAL = 1,
  41. XTALK_ANALOG = 2
  42. };
  43. extern struct regmap_config wcd939x_regmap_config;
  44. struct comp_coeff_val {
  45. u8 lsb;
  46. u8 msb;
  47. };
  48. struct codec_port_info {
  49. u32 slave_port_type;
  50. u32 master_port_type;
  51. u32 ch_mask;
  52. u32 num_ch;
  53. u32 ch_rate;
  54. };
  55. struct wcd939x_priv {
  56. struct device *dev;
  57. int variant;
  58. struct snd_soc_component *component;
  59. struct device_node *rst_np;
  60. struct regmap *regmap;
  61. struct swr_device *rx_swr_dev;
  62. struct swr_device *tx_swr_dev;
  63. s32 micb_ref[WCD939X_MAX_MICBIAS];
  64. s32 pullup_ref[WCD939X_MAX_MICBIAS];
  65. struct fw_info *fw_data;
  66. struct device_node *wcd_rst_np;
  67. struct mutex micb_lock;
  68. struct mutex wakeup_lock;
  69. s32 dmic_0_1_clk_cnt;
  70. s32 dmic_2_3_clk_cnt;
  71. s32 dmic_4_5_clk_cnt;
  72. s32 dmic_6_7_clk_cnt;
  73. int hdr_en[TX_HDR_MAX];
  74. /* class h specific info */
  75. struct wcd_clsh_cdc_info clsh_info;
  76. /* mbhc module */
  77. struct wcd939x_mbhc *mbhc;
  78. /*compander and xtalk*/
  79. int compander_enabled[WCD939X_HPH_MAX];
  80. int xtalk_enabled[WCD939X_HPH_MAX];
  81. u8 hph_pcm_enabled;
  82. u32 hph_mode;
  83. u32 tx_mode[TX_ADC_MAX];
  84. s32 adc_count;
  85. bool comp1_enable;
  86. bool comp2_enable;
  87. bool ldoh;
  88. bool bcs_dis;
  89. bool dapm_bias_off;
  90. bool in_2Vpk_mode;
  91. struct irq_domain *virq;
  92. struct wcd_irq_info irq_info;
  93. u32 rx_clk_cnt;
  94. int num_irq_regs;
  95. /* to track the status */
  96. unsigned long status_mask;
  97. u8 num_tx_ports;
  98. u8 num_rx_ports;
  99. struct codec_port_info
  100. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  101. struct codec_port_info
  102. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  103. struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_NUM_PORTS];
  104. struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
  105. struct regulator_bulk_data *supplies;
  106. struct notifier_block nblock;
  107. /* wcd callback to bolero */
  108. void *handle;
  109. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  110. int (*register_notifier)(void *handle,
  111. struct notifier_block *nblock,
  112. bool enable);
  113. int (*wakeup)(void *handle, bool enable);
  114. u32 version;
  115. /* Entry for version info */
  116. struct snd_info_entry *entry;
  117. struct snd_info_entry *version_entry;
  118. struct snd_info_entry *variant_entry;
  119. int flyback_cur_det_disable;
  120. int ear_rx_path;
  121. bool dev_up;
  122. u8 tx_master_ch_map[WCD939X_MAX_SLAVE_CH_TYPES];
  123. bool usbc_hs_status;
  124. u8 rx_clk_config;
  125. /* wcd to swr dmic notification */
  126. bool notify_swr_dmic;
  127. struct blocking_notifier_head notifier;
  128. };
  129. struct wcd939x_micbias_setting {
  130. u8 ldoh_v;
  131. u32 cfilt1_mv;
  132. u32 micb1_mv;
  133. u32 micb2_mv;
  134. u32 micb3_mv;
  135. u32 micb4_mv;
  136. u8 bias1_cfilt_sel;
  137. };
  138. struct wcd939x_xtalk_params {
  139. u32 r_gnd_int_fet_mohms;
  140. u32 r_gnd_par_route1_mohms;
  141. u32 r_gnd_par_route2_mohms;
  142. u32 r_gnd_ext_fet_mohms;
  143. u32 r_conn_par_load_neg_mohms;
  144. u32 r_aud_int_fet_l_mohms;
  145. u32 r_aud_int_fet_r_mohms;
  146. u32 r_aud_ext_fet_l_mohms;
  147. u32 r_aud_ext_fet_r_mohms;
  148. u32 r_conn_par_load_pos_l_mohms;
  149. u32 r_conn_par_load_pos_r_mohms;
  150. u32 r_gnd_res_tot_mohms;
  151. u32 r_aud_res_tot_l_mohms;
  152. u32 r_aud_res_tot_r_mohms;
  153. u32 zl;
  154. u32 zr;
  155. u8 scale_l;
  156. u8 alpha_l;
  157. u8 scale_r;
  158. u8 alpha_r;
  159. enum xtalk_mode xtalk_config;
  160. };
  161. struct wcd939x_pdata {
  162. struct device_node *rst_np;
  163. struct device_node *rx_slave;
  164. struct device_node *tx_slave;
  165. struct wcd939x_micbias_setting micbias;
  166. struct wcd939x_xtalk_params xtalk;
  167. struct cdc_regulator *regulator;
  168. int num_supplies;
  169. };
  170. struct wcd_ctrl_platform_data {
  171. void *handle;
  172. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  173. int (*register_notifier)(void *handle,
  174. struct notifier_block *nblock,
  175. bool enable);
  176. };
  177. enum {
  178. WCD_RX1,
  179. WCD_RX2,
  180. WCD_RX3
  181. };
  182. enum {
  183. /* INTR_CTRL_INT_MASK_0 */
  184. WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
  185. WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
  186. WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
  187. WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  188. WCD939X_IRQ_MBHC_SW_DET,
  189. WCD939X_IRQ_HPHR_OCP_INT,
  190. WCD939X_IRQ_HPHR_CNP_INT,
  191. WCD939X_IRQ_HPHL_OCP_INT,
  192. /* INTR_CTRL_INT_MASK_1 */
  193. WCD939X_IRQ_HPHL_CNP_INT,
  194. WCD939X_IRQ_EAR_CNP_INT,
  195. WCD939X_IRQ_EAR_SCD_INT,
  196. WCD939X_IRQ_HPHL_PDM_WD_INT,
  197. WCD939X_IRQ_HPHR_PDM_WD_INT,
  198. WCD939X_IRQ_EAR_PDM_WD_INT,
  199. /* INTR_CTRL_INT_MASK_2 */
  200. WCD939X_IRQ_MBHC_MOISTURE_INT,
  201. WCD939X_IRQ_HPHL_SURGE_DET_INT,
  202. WCD939X_IRQ_HPHR_SURGE_DET_INT,
  203. WCD939X_NUM_IRQS,
  204. };
  205. extern struct wcd939x_mbhc *wcd939x_soc_get_mbhc(
  206. struct snd_soc_component *component);
  207. extern void wcd939x_disable_bcs_before_slow_insert(
  208. struct snd_soc_component *component,
  209. bool bcs_disable);
  210. extern int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  211. int volt, int micb_num);
  212. extern int wcd939x_get_micb_vout_ctl_val(u32 micb_mv);
  213. extern int wcd939x_micbias_control(struct snd_soc_component *component,
  214. int micb_num, int req, bool is_dapm);
  215. #endif /* _WCD939X_INTERNAL_H */