wcd9378.c 126 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_RX0 1
  31. #define AUX_RX_PATH_RX1 1
  32. #define SWR_BASECLK_19P2MHZ (0x01)
  33. #define SWR_BASECLK_24P576MHZ (0x03)
  34. #define SWR_BASECLK_22P5792MHZ (0x04)
  35. #define SWR_CLKSCALE_DIV2 (0x02)
  36. #define ADC_MODE_VAL_HIFI 0x01
  37. #define ADC_MODE_VAL_NORMAL 0x03
  38. #define ADC_MODE_VAL_LP 0x05
  39. #define PWR_LEVEL_LOHIFI_VAL 0x00
  40. #define PWR_LEVEL_LP_VAL 0x01
  41. #define PWR_LEVEL_HIFI_VAL 0x02
  42. #define PWR_LEVEL_ULP_VAL 0x03
  43. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  44. #define MICB_USAGE_VAL_DISABLE 0x00
  45. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  46. #define MICB_USAGE_VAL_1P2V 0x02
  47. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  48. #define MICB_USAGE_VAL_2P5V 0x04
  49. #define MICB_USAGE_VAL_2P75V 0x05
  50. #define MICB_USAGE_VAL_2P2V 0xF0
  51. #define MICB_USAGE_VAL_2P7V 0xF1
  52. #define MICB_USAGE_VAL_2P8V 0xF2
  53. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  54. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  55. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  56. #define MICB_NUM_MAX 3
  57. #define NUM_ATTEMPTS 20
  58. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  59. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  60. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  61. SNDRV_PCM_RATE_384000)
  62. /* Fractional Rates */
  63. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  64. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  65. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  66. SNDRV_PCM_FMTBIT_S24_LE |\
  67. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  68. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  69. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  70. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  71. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  72. .tlv.p = (tlv_array), \
  73. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  74. .put = wcd9378_ear_pa_put_gain, \
  75. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  76. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  77. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  78. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  79. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  80. .tlv.p = (tlv_array), \
  81. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  82. .put = wcd9378_aux_pa_put_gain, \
  83. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  84. enum {
  85. CODEC_TX = 0,
  86. CODEC_RX,
  87. };
  88. enum {
  89. RX2_HP_MODE,
  90. RX2_NORMAL_MODE,
  91. };
  92. enum {
  93. WCD_ADC1 = 0,
  94. WCD_ADC2,
  95. WCD_ADC3,
  96. WCD_ADC4,
  97. ALLOW_BUCK_DISABLE,
  98. HPH_COMP_DELAY,
  99. HPH_PA_DELAY,
  100. AMIC2_BCS_ENABLE,
  101. WCD_SUPPLIES_LPM_MODE,
  102. WCD_ADC1_MODE,
  103. WCD_ADC2_MODE,
  104. WCD_ADC3_MODE,
  105. WCD_ADC4_MODE,
  106. WCD_AUX_EN,
  107. WCD_EAR_EN,
  108. };
  109. enum {
  110. NOSJ_SA_STEREO_3SM = 0,
  111. SJ_SA_AUX_2SM,
  112. NOSJ_SA_STEREO_3SM_1HDR,
  113. SJ_SA_AUX_2SM_1HDR,
  114. NOSJ_SA_EAR_3SM,
  115. SJ_SA_EAR_2SM,
  116. NOSJ_SA_EAR_3SM_1HDR,
  117. SJ_SA_EAR_2SM_1HDR,
  118. SJ_1HDR_SA_AUX_1SM,
  119. SJ_1HDR_SA_EAR_1SM,
  120. SJ_SA_STEREO_2SM,
  121. SJ_NOMIC_SA_EAR_3SM,
  122. SJ_NOMIC_SA_AUX_3SM,
  123. WCD_SYS_USAGE_MAX,
  124. };
  125. enum {
  126. NO_MICB_USED,
  127. MICB1,
  128. MICB2,
  129. MICB3,
  130. MICB_NUM,
  131. };
  132. enum {
  133. ADC_MODE_INVALID = 0,
  134. ADC_MODE_HIFI,
  135. ADC_MODE_NORMAL,
  136. ADC_MODE_LP,
  137. };
  138. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
  139. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
  140. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  141. static int wcd9378_reset(struct device *dev);
  142. static int wcd9378_reset_low(struct device *dev);
  143. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  144. static void wcd9378_class_load(struct snd_soc_component *component);
  145. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  146. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  147. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  148. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  149. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  150. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  151. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  152. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  153. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  154. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  155. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  156. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  157. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  158. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  159. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  160. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  161. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  162. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  163. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  164. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  165. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  166. };
  167. static int wcd9378_handle_post_irq(void *data)
  168. {
  169. struct wcd9378_priv *wcd9378 = data;
  170. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  171. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  172. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  173. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  174. wcd9378->tx_swr_dev->slave_irq_pending =
  175. ((sts1 || sts2 || !sts3) ? true : false);
  176. return IRQ_HANDLED;
  177. }
  178. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  179. .name = "wcd9378",
  180. .irqs = wcd9378_regmap_irqs,
  181. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  182. .num_regs = 3,
  183. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  184. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  185. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  186. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  187. .use_ack = 1,
  188. .runtime_pm = false,
  189. .handle_post_irq = wcd9378_handle_post_irq,
  190. .irq_drv_data = NULL,
  191. };
  192. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  193. {
  194. int ret = 0;
  195. int bank = 0;
  196. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  197. if (ret)
  198. return -EINVAL;
  199. return ((bank & 0x40) ? 1 : 0);
  200. }
  201. static int wcd9378_init_reg(struct snd_soc_component *component)
  202. {
  203. /*0.9 Volts*/
  204. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  205. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  206. /*BG_EN ENABLE*/
  207. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  208. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  209. usleep_range(1000, 1010);
  210. /*LDOL_BG_SEL SLEEP_BG*/
  211. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  212. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  213. usleep_range(1000, 1010);
  214. /*Start up analog master bias. Sequence cannot change*/
  215. /*VBG_FINE_ADJ 0.005 Volts*/
  216. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  217. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  218. /*ANALOG_BIAS_EN ENABLE*/
  219. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  220. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  221. /*PRECHRG_EN ENABLE*/
  222. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  223. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  224. usleep_range(10000, 10010);
  225. /*PRECHRG_EN DISABLE*/
  226. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  227. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  228. /*End Analog Master Bias enable*/
  229. /*SEQ_BYPASS ENABLE*/
  230. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  231. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  232. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  233. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  234. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  235. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  236. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  237. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  238. /*IBIAS_LDO_DRIVER 5e-06*/
  239. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  240. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  241. /*IBIAS_LDO_DRIVER 5e-06*/
  242. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  243. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  244. /*SHORT_PROT_EN ENABLE*/
  245. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  246. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  247. /*OCP FSM EN*/
  248. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  249. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  250. /*SCD OP EN*/
  251. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  252. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  253. /*OCP DET EN*/
  254. snd_soc_component_update_bits(component, WCD9378_HPH_L_TEST,
  255. WCD9378_HPH_L_TEST_OCP_DET_EN_MASK, 0x01);
  256. /*OCP DET EN*/
  257. snd_soc_component_update_bits(component, WCD9378_HPH_R_TEST,
  258. WCD9378_HPH_R_TEST_OCP_DET_EN_MASK, 0x01);
  259. /*HD2_RES_DIV_CTL_L 82.77*/
  260. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  261. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  262. /*HD2_RES_DIV_CTL_R 82.77*/
  263. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  264. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  265. /*OPAMP_CHOP_CLK_EN DISABLE*/
  266. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  267. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  268. /*RDAC_GAINCTL 0.55*/
  269. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  270. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  271. /*HPH_UP_T0: 0.002*/
  272. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  273. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  274. /*HPH_UP_T9: 0.002*/
  275. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  276. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  277. /*HPH_DN_T0: 0.007*/
  278. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  279. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  280. wcd9378_class_load(component);
  281. return 0;
  282. }
  283. static int wcd9378_set_port_params(struct snd_soc_component *component,
  284. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  285. u8 *ch_mask, u32 *ch_rate,
  286. u8 *port_type, u8 path)
  287. {
  288. int i, j;
  289. u8 num_ports = 0;
  290. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  291. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  292. switch (path) {
  293. case CODEC_RX:
  294. map = &wcd9378->rx_port_mapping;
  295. num_ports = wcd9378->num_rx_ports;
  296. break;
  297. case CODEC_TX:
  298. map = &wcd9378->tx_port_mapping;
  299. num_ports = wcd9378->num_tx_ports;
  300. break;
  301. default:
  302. dev_err(component->dev, "%s Invalid path selected %u\n",
  303. __func__, path);
  304. return -EINVAL;
  305. }
  306. for (i = 0; i <= num_ports; i++) {
  307. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  308. if ((*map)[i][j].slave_port_type == slv_prt_type)
  309. goto found;
  310. }
  311. }
  312. found:
  313. if (i > num_ports || j == MAX_CH_PER_PORT) {
  314. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  315. __func__, slv_prt_type);
  316. return -EINVAL;
  317. }
  318. *port_id = i;
  319. *num_ch = (*map)[i][j].num_ch;
  320. *ch_mask = (*map)[i][j].ch_mask;
  321. *ch_rate = (*map)[i][j].ch_rate;
  322. *port_type = (*map)[i][j].master_port_type;
  323. return 0;
  324. }
  325. static int wcd9378_parse_port_params(struct device *dev,
  326. char *prop, u8 path)
  327. {
  328. u32 *dt_array, map_size, max_uc;
  329. int ret = 0;
  330. u32 cnt = 0;
  331. u32 i, j;
  332. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  333. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  334. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  335. switch (path) {
  336. case CODEC_TX:
  337. map = &wcd9378->tx_port_params;
  338. map_uc = &wcd9378->swr_tx_port_params;
  339. break;
  340. default:
  341. ret = -EINVAL;
  342. goto err_port_map;
  343. }
  344. if (!of_find_property(dev->of_node, prop,
  345. &map_size)) {
  346. dev_err(dev, "missing port mapping prop %s\n", prop);
  347. ret = -EINVAL;
  348. goto err_port_map;
  349. }
  350. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  351. if (max_uc != SWR_UC_MAX) {
  352. dev_err(dev, "%s: port params not provided for all usecases\n",
  353. __func__);
  354. ret = -EINVAL;
  355. goto err_port_map;
  356. }
  357. dt_array = kzalloc(map_size, GFP_KERNEL);
  358. if (!dt_array) {
  359. ret = -ENOMEM;
  360. goto err_alloc;
  361. }
  362. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  363. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  364. if (ret) {
  365. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  366. __func__, prop);
  367. goto err_pdata_fail;
  368. }
  369. for (i = 0; i < max_uc; i++) {
  370. for (j = 0; j < SWR_NUM_PORTS; j++) {
  371. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  372. (*map)[i][j].offset1 = dt_array[cnt];
  373. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  374. }
  375. (*map_uc)[i].pp = &(*map)[i][0];
  376. }
  377. kfree(dt_array);
  378. return 0;
  379. err_pdata_fail:
  380. kfree(dt_array);
  381. err_alloc:
  382. err_port_map:
  383. return ret;
  384. }
  385. static int wcd9378_parse_port_mapping(struct device *dev,
  386. char *prop, u8 path)
  387. {
  388. u32 *dt_array, map_size, map_length;
  389. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  390. u32 slave_port_type, master_port_type;
  391. u32 i, ch_iter = 0;
  392. int ret = 0;
  393. u8 *num_ports = NULL;
  394. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  395. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  396. switch (path) {
  397. case CODEC_RX:
  398. map = &wcd9378->rx_port_mapping;
  399. num_ports = &wcd9378->num_rx_ports;
  400. break;
  401. case CODEC_TX:
  402. map = &wcd9378->tx_port_mapping;
  403. num_ports = &wcd9378->num_tx_ports;
  404. break;
  405. default:
  406. dev_err(dev, "%s Invalid path selected %u\n",
  407. __func__, path);
  408. return -EINVAL;
  409. }
  410. if (!of_find_property(dev->of_node, prop,
  411. &map_size)) {
  412. dev_err(dev, "missing port mapping prop %s\n", prop);
  413. ret = -EINVAL;
  414. goto err_port_map;
  415. }
  416. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  417. dt_array = kzalloc(map_size, GFP_KERNEL);
  418. if (!dt_array) {
  419. ret = -ENOMEM;
  420. goto err_alloc;
  421. }
  422. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  423. NUM_SWRS_DT_PARAMS * map_length);
  424. if (ret) {
  425. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  426. __func__, prop);
  427. goto err_pdata_fail;
  428. }
  429. for (i = 0; i < map_length; i++) {
  430. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  431. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  432. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  433. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  434. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  435. if (port_num != old_port_num)
  436. ch_iter = 0;
  437. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  438. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  439. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  440. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  441. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  442. old_port_num = port_num;
  443. }
  444. *num_ports = port_num;
  445. kfree(dt_array);
  446. return 0;
  447. err_pdata_fail:
  448. kfree(dt_array);
  449. err_alloc:
  450. err_port_map:
  451. return ret;
  452. }
  453. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  454. u8 slv_port_type, int clk_rate,
  455. u8 enable)
  456. {
  457. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  458. u8 port_id, num_ch, ch_mask;
  459. u8 ch_type = 0;
  460. u32 ch_rate;
  461. int slave_ch_idx;
  462. u8 num_port = 1;
  463. int ret = 0;
  464. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  465. &num_ch, &ch_mask, &ch_rate,
  466. &ch_type, CODEC_TX);
  467. if (ret)
  468. return ret;
  469. if (clk_rate)
  470. ch_rate = clk_rate;
  471. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  472. if (slave_ch_idx != -EINVAL)
  473. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  474. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  475. __func__, slave_ch_idx, ch_type);
  476. if (enable)
  477. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  478. num_port, &ch_mask, &ch_rate,
  479. &num_ch, &ch_type);
  480. else
  481. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  482. num_port, &ch_mask, &ch_type);
  483. return ret;
  484. }
  485. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  486. u8 slv_port_type, u8 enable)
  487. {
  488. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  489. u8 port_id, num_ch, ch_mask, port_type;
  490. u32 ch_rate;
  491. u8 num_port = 1;
  492. int ret = 0;
  493. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  494. &num_ch, &ch_mask, &ch_rate,
  495. &port_type, CODEC_RX);
  496. if (ret)
  497. return ret;
  498. if (enable)
  499. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  500. num_port, &ch_mask, &ch_rate,
  501. &num_ch, &port_type);
  502. else
  503. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  504. num_port, &ch_mask, &port_type);
  505. return ret;
  506. }
  507. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  508. struct snd_kcontrol *kcontrol,
  509. int event)
  510. {
  511. struct snd_soc_component *component =
  512. snd_soc_dapm_to_component(w->dapm);
  513. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  514. int mode = wcd9378->hph_mode;
  515. int ret = 0;
  516. int bank = 0;
  517. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  518. w->name, event);
  519. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  520. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  521. wcd9378_rx_connect_port(component, CLSH,
  522. SND_SOC_DAPM_EVENT_ON(event));
  523. }
  524. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  525. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  526. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  527. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  528. ret = swr_slvdev_datapath_control(
  529. wcd9378->rx_swr_dev,
  530. wcd9378->rx_swr_dev->dev_num,
  531. false);
  532. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  533. }
  534. return ret;
  535. }
  536. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  537. struct snd_kcontrol *kcontrol,
  538. int event)
  539. {
  540. struct snd_soc_component *component =
  541. snd_soc_dapm_to_component(w->dapm);
  542. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  543. u32 dmic_clk_reg, dmic_clk_en_reg;
  544. s32 *dmic_clk_cnt;
  545. u8 dmic_ctl_shift = 0;
  546. u8 dmic_clk_shift = 0;
  547. u8 dmic_clk_mask = 0;
  548. u32 dmic2_left_en = 0;
  549. int ret = 0;
  550. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  551. w->name, event);
  552. switch (w->shift) {
  553. case 0:
  554. case 1:
  555. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  556. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  557. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  558. dmic_clk_mask = 0x0F;
  559. dmic_clk_shift = 0x00;
  560. dmic_ctl_shift = 0x00;
  561. break;
  562. case 2:
  563. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  564. fallthrough;
  565. case 3:
  566. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  567. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  568. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  569. dmic_clk_mask = 0xF0;
  570. dmic_clk_shift = 0x04;
  571. dmic_ctl_shift = 0x01;
  572. break;
  573. case 4:
  574. case 5:
  575. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  576. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  577. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  578. dmic_clk_mask = 0x0F;
  579. dmic_clk_shift = 0x00;
  580. dmic_ctl_shift = 0x02;
  581. break;
  582. default:
  583. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  584. __func__);
  585. return -EINVAL;
  586. };
  587. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  588. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  589. switch (event) {
  590. case SND_SOC_DAPM_PRE_PMU:
  591. snd_soc_component_update_bits(component,
  592. WCD9378_CDC_AMIC_CTL,
  593. (0x01 << dmic_ctl_shift), 0x00);
  594. /* 250us sleep as per HW requirement */
  595. usleep_range(250, 260);
  596. if (dmic2_left_en)
  597. snd_soc_component_update_bits(component,
  598. dmic2_left_en, 0x80, 0x80);
  599. /* Setting DMIC clock rate to 2.4MHz */
  600. snd_soc_component_update_bits(component,
  601. dmic_clk_reg, dmic_clk_mask,
  602. (0x03 << dmic_clk_shift));
  603. snd_soc_component_update_bits(component,
  604. dmic_clk_en_reg, 0x08, 0x08);
  605. /* enable clock scaling */
  606. snd_soc_component_update_bits(component,
  607. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  608. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  609. wcd9378->tx_swr_dev->dev_num,
  610. true);
  611. break;
  612. case SND_SOC_DAPM_POST_PMD:
  613. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  614. false);
  615. snd_soc_component_update_bits(component,
  616. WCD9378_CDC_AMIC_CTL,
  617. (0x01 << dmic_ctl_shift),
  618. (0x01 << dmic_ctl_shift));
  619. if (dmic2_left_en)
  620. snd_soc_component_update_bits(component,
  621. dmic2_left_en, 0x80, 0x00);
  622. snd_soc_component_update_bits(component,
  623. dmic_clk_en_reg, 0x08, 0x00);
  624. break;
  625. };
  626. return ret;
  627. }
  628. /*
  629. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  630. * @micb_mv: micbias in mv
  631. *
  632. * return register value converted
  633. */
  634. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  635. {
  636. /* min micbias voltage is 1V and maximum is 2.85V */
  637. if (micb_mv < 1000 || micb_mv > 2850) {
  638. pr_err("%s: unsupported micbias voltage\n", __func__);
  639. return -EINVAL;
  640. }
  641. return (micb_mv - 1000) / 50;
  642. }
  643. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  644. /*
  645. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  646. * @component: handle to snd_soc_component *
  647. * @req_volt: micbias voltage to be set
  648. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  649. *
  650. * return 0 if adjustment is success or error code in case of failure
  651. */
  652. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  653. u32 micb_mv, int micb_num)
  654. {
  655. int vcout_ctl;
  656. switch (micb_mv) {
  657. case 2200:
  658. return MICB_USAGE_VAL_2P2V;
  659. case 2700:
  660. return MICB_USAGE_VAL_2P7V;
  661. case 2800:
  662. return MICB_USAGE_VAL_2P8V;
  663. default:
  664. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  665. if (micb_num == MIC_BIAS_1) {
  666. snd_soc_component_update_bits(component,
  667. WCD9378_MICB_REMAP_TABLE_VAL_3,
  668. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  669. vcout_ctl);
  670. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  671. } else if (micb_num == MIC_BIAS_2) {
  672. snd_soc_component_update_bits(component,
  673. WCD9378_MICB_REMAP_TABLE_VAL_4,
  674. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  675. vcout_ctl);
  676. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  677. } else if (micb_num == MIC_BIAS_3) {
  678. snd_soc_component_update_bits(component,
  679. WCD9378_MICB_REMAP_TABLE_VAL_5,
  680. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  681. vcout_ctl);
  682. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  683. }
  684. }
  685. return 0;
  686. }
  687. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  688. u32 micb_mv, int micb_num)
  689. {
  690. switch (micb_mv) {
  691. case 0:
  692. return MICB_USAGE_VAL_PULL_DOWN;
  693. case 1200:
  694. return MICB_USAGE_VAL_1P2V;
  695. case 1800:
  696. return MICB_USAGE_VAL_1P8VORPULLUP;
  697. case 2500:
  698. return MICB_USAGE_VAL_2P5V;
  699. case 2750:
  700. return MICB_USAGE_VAL_2P75V;
  701. default:
  702. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  703. }
  704. return MICB_USAGE_VAL_DISABLE;
  705. }
  706. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  707. int req_volt, int micb_num)
  708. {
  709. struct wcd9378_priv *wcd9378 =
  710. snd_soc_component_get_drvdata(component);
  711. int micb_usage = 0, micb_mask = 0, req_vout_ctl;
  712. int sm_num = 0;
  713. struct wcd9378_pdata *pdata = NULL;
  714. pdata = dev_get_platdata(wcd9378->dev);
  715. if (wcd9378 == NULL) {
  716. dev_err(component->dev,
  717. "%s: wcd9378 private data is NULL\n", __func__);
  718. return -EINVAL;
  719. }
  720. for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
  721. if (wcd9378->micb_sel[sm_num] == micb_num)
  722. break;
  723. if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
  724. pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
  725. __func__, micb_num);
  726. return -EINVAL;
  727. }
  728. switch (sm_num) {
  729. case SIM_MIC0:
  730. micb_usage = WCD9378_IT11_USAGE;
  731. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  732. break;
  733. case SIM_MIC1:
  734. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  735. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  736. break;
  737. case SIM_MIC2:
  738. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  739. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  740. break;
  741. default:
  742. if (micb_num == MIC_BIAS_2) {
  743. micb_usage = WCD9378_IT31_MICB;
  744. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  745. }
  746. break;
  747. }
  748. mutex_lock(&wcd9378->micb_lock);
  749. req_vout_ctl =
  750. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  751. snd_soc_component_update_bits(component,
  752. micb_usage, micb_mask, req_vout_ctl);
  753. mutex_unlock(&wcd9378->micb_lock);
  754. return 0;
  755. }
  756. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  757. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  758. bool bcs_disable)
  759. {
  760. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  761. if (wcd9378->update_wcd_event) {
  762. if (bcs_disable)
  763. wcd9378->update_wcd_event(wcd9378->handle,
  764. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  765. else
  766. wcd9378->update_wcd_event(wcd9378->handle,
  767. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  768. }
  769. }
  770. static int wcd9378_get_clk_rate(int mode)
  771. {
  772. int rate;
  773. switch (mode) {
  774. case ADC_MODE_LP:
  775. rate = SWR_CLK_RATE_4P8MHZ;
  776. break;
  777. case ADC_MODE_INVALID:
  778. case ADC_MODE_NORMAL:
  779. case ADC_MODE_HIFI:
  780. default:
  781. rate = SWR_CLK_RATE_9P6MHZ;
  782. break;
  783. }
  784. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  785. return rate;
  786. }
  787. static int wcd9378_get_adc_mode_val(int mode)
  788. {
  789. int ret = 0;
  790. switch (mode) {
  791. case ADC_MODE_INVALID:
  792. case ADC_MODE_NORMAL:
  793. ret = ADC_MODE_VAL_NORMAL;
  794. break;
  795. case ADC_MODE_HIFI:
  796. ret = ADC_MODE_VAL_HIFI;
  797. break;
  798. case ADC_MODE_LP:
  799. ret = ADC_MODE_VAL_LP;
  800. break;
  801. default:
  802. ret = -EINVAL;
  803. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  804. break;
  805. }
  806. return ret;
  807. }
  808. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  809. struct snd_kcontrol *kcontrol, int event)
  810. {
  811. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  812. struct wcd9378_priv *wcd9378 =
  813. snd_soc_component_get_drvdata(component);
  814. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  815. int act_ps = 0;
  816. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  817. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  818. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  819. w->name, w->shift, event);
  820. switch (event) {
  821. case SND_SOC_DAPM_PRE_PMU:
  822. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  823. if (mode_val < 0) {
  824. dev_dbg(component->dev,
  825. "%s: invalid mode, setting to normal mode\n",
  826. __func__);
  827. mode_val = ADC_MODE_VAL_NORMAL;
  828. }
  829. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  830. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  831. WCD9378_TX_NEW_TX_CH12_MUX) &
  832. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  833. if (!wcd9378->bcs_dis) {
  834. wcd9378_tx_connect_port(component, MBHC,
  835. SWR_CLK_RATE_4P8MHZ, true);
  836. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  837. }
  838. }
  839. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  840. wcd9378_tx_connect_port(component, w->shift, rate,
  841. true);
  842. if (wcd9378->va_amic_en)
  843. wcd9378_micbias_control(component, w->shift,
  844. MICB_PULLUP_ENABLE, true);
  845. else
  846. wcd9378_micbias_control(component, w->shift,
  847. MICB_ENABLE, true);
  848. switch (w->shift) {
  849. case ADC1:
  850. /*SMP MIC0 IT11 USAGE SET*/
  851. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  852. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  853. /*Hold TXFE in Initialization During Startup*/
  854. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  855. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  856. /*Power up TX0 sequencer*/
  857. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  858. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  859. break;
  860. case ADC2:
  861. if (wcd9378->sjmic_support) {
  862. /*SMP JACK IT31 USAGE SET*/
  863. snd_soc_component_update_bits(component,
  864. WCD9378_IT31_USAGE,
  865. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  866. /*Power up TX1 sequencer*/
  867. snd_soc_component_update_bits(component,
  868. WCD9378_PDE34_REQ_PS,
  869. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  870. } else {
  871. /*SMP MIC1 IT11 USAGE SET*/
  872. snd_soc_component_update_bits(component,
  873. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  874. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  875. mode_val);
  876. /*Hold TXFE in Initialization During Startup*/
  877. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  878. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  879. /*Power up TX1 sequencer*/
  880. snd_soc_component_update_bits(component,
  881. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  882. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  883. 0x00);
  884. }
  885. break;
  886. case ADC3:
  887. /*SMP MIC2 IT11 USAGE SET*/
  888. snd_soc_component_update_bits(component,
  889. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  890. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  891. mode_val);
  892. /*Hold TXFE in Initialization During Startup*/
  893. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  894. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  895. /*Power up TX2 sequencer*/
  896. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  897. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  898. break;
  899. default:
  900. break;
  901. }
  902. /*default delay 800us*/
  903. usleep_range(800, 810);
  904. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  905. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  906. wcd9378->tx_swr_dev->dev_num,
  907. true);
  908. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  909. switch (w->shift) {
  910. case ADC1:
  911. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  912. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  913. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  914. if (act_ps)
  915. dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  916. __func__, act_ps);
  917. else
  918. dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  919. __func__, act_ps);
  920. break;
  921. case ADC2:
  922. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  923. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  924. if (wcd9378->sjmic_support)
  925. act_ps = snd_soc_component_read(component,
  926. WCD9378_PDE34_ACT_PS);
  927. else
  928. act_ps = snd_soc_component_read(component,
  929. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  930. if (act_ps)
  931. dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  932. __func__, act_ps);
  933. else
  934. dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  935. __func__, act_ps);
  936. break;
  937. case ADC3:
  938. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  939. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  940. act_ps = snd_soc_component_read(component,
  941. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  942. if (act_ps)
  943. dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
  944. __func__, act_ps);
  945. else
  946. dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
  947. __func__, act_ps);
  948. break;
  949. };
  950. break;
  951. case SND_SOC_DAPM_POST_PMD:
  952. wcd9378_tx_connect_port(component, w->shift, 0, false);
  953. if (w->shift == ADC2 &&
  954. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  955. wcd9378_tx_connect_port(component, MBHC, 0,
  956. false);
  957. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  958. }
  959. switch (w->shift) {
  960. case ADC1:
  961. /*Normal TXFE Startup*/
  962. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  963. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  964. /*tear down TX0 sequencer*/
  965. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  966. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  967. break;
  968. case ADC2:
  969. /*tear down TX1 sequencer*/
  970. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  971. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  972. /*Normal TXFE Startup*/
  973. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  974. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  975. /*tear down TX1 sequencer*/
  976. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  977. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  978. break;
  979. case ADC3:
  980. /*Normal TXFE Startup*/
  981. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  982. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  983. /*tear down TX2 sequencer*/
  984. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  985. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  986. break;
  987. default:
  988. break;
  989. }
  990. /*default delay 800us*/
  991. usleep_range(800, 810);
  992. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  993. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  994. wcd9378->tx_swr_dev->dev_num,
  995. false);
  996. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  997. if (wcd9378->va_amic_en)
  998. wcd9378_micbias_control(component, w->shift,
  999. MICB_PULLUP_DISABLE, true);
  1000. else
  1001. wcd9378_micbias_control(component, w->shift,
  1002. MICB_DISABLE, true);
  1003. break;
  1004. default:
  1005. break;
  1006. }
  1007. return ret;
  1008. }
  1009. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1010. struct snd_kcontrol *kcontrol,
  1011. int event)
  1012. {
  1013. struct snd_soc_component *component =
  1014. snd_soc_dapm_to_component(w->dapm);
  1015. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1016. int ret = 0;
  1017. switch (event) {
  1018. case SND_SOC_DAPM_PRE_PMU:
  1019. wcd9378_tx_connect_port(component, w->shift,
  1020. SWR_CLK_RATE_2P4MHZ, true);
  1021. break;
  1022. case SND_SOC_DAPM_POST_PMD:
  1023. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1024. wcd9378->tx_swr_dev->dev_num,
  1025. false);
  1026. break;
  1027. };
  1028. return ret;
  1029. }
  1030. static int wcd9378_tx_num_get(struct snd_soc_component *component,
  1031. int micb_num)
  1032. {
  1033. int sm_num = 0;
  1034. struct wcd9378_priv *wcd9378 =
  1035. snd_soc_component_get_drvdata(component);
  1036. for (sm_num = SIM_MIC0; sm_num <= SIM_MIC2; sm_num++) {
  1037. if (wcd9378->micb_sel[sm_num] == micb_num) {
  1038. if (sm_num == SIM_MIC0)
  1039. return ADC1;
  1040. else if (sm_num == SIM_MIC1)
  1041. return ADC2;
  1042. else if (sm_num == SIM_MIC2)
  1043. return ADC3;
  1044. else
  1045. return -EINVAL;
  1046. }
  1047. }
  1048. return -EINVAL;
  1049. }
  1050. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1051. struct snd_kcontrol *kcontrol,
  1052. int event)
  1053. {
  1054. struct snd_soc_component *component =
  1055. snd_soc_dapm_to_component(w->dapm);
  1056. int micb_num = 0, tx_num = 0;
  1057. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1058. __func__, w->name, event);
  1059. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1060. micb_num = MIC_BIAS_1;
  1061. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1062. micb_num = MIC_BIAS_2;
  1063. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1064. micb_num = MIC_BIAS_3;
  1065. else
  1066. return -EINVAL;
  1067. tx_num = wcd9378_tx_num_get(component, micb_num);
  1068. if (tx_num < 0)
  1069. pr_err("%s: SM MB SEL should be set properly\n", __func__);
  1070. switch (event) {
  1071. case SND_SOC_DAPM_PRE_PMU:
  1072. wcd9378_micbias_control(component, tx_num,
  1073. MICB_ENABLE, true);
  1074. break;
  1075. case SND_SOC_DAPM_POST_PMU:
  1076. usleep_range(1000, 1100);
  1077. break;
  1078. case SND_SOC_DAPM_POST_PMD:
  1079. wcd9378_micbias_control(component, tx_num,
  1080. MICB_DISABLE, true);
  1081. break;
  1082. };
  1083. return 0;
  1084. }
  1085. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1086. struct snd_kcontrol *kcontrol,
  1087. int event)
  1088. {
  1089. struct snd_soc_component *component =
  1090. snd_soc_dapm_to_component(w->dapm);
  1091. int micb_num = 0, tx_num = 0;
  1092. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1093. __func__, w->name, event);
  1094. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1095. micb_num = MIC_BIAS_1;
  1096. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1097. micb_num = MIC_BIAS_2;
  1098. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1099. micb_num = MIC_BIAS_3;
  1100. else
  1101. return -EINVAL;
  1102. tx_num = wcd9378_tx_num_get(component, micb_num);
  1103. if (tx_num < 0)
  1104. pr_err("%s: SM MB SEL should be set properly\n", __func__);
  1105. switch (event) {
  1106. case SND_SOC_DAPM_PRE_PMU:
  1107. wcd9378_micbias_control(component, tx_num,
  1108. MICB_PULLUP_ENABLE, true);
  1109. break;
  1110. case SND_SOC_DAPM_POST_PMU:
  1111. usleep_range(1000, 1100);
  1112. break;
  1113. case SND_SOC_DAPM_POST_PMD:
  1114. wcd9378_micbias_control(component, tx_num,
  1115. MICB_PULLUP_DISABLE, true);
  1116. break;
  1117. };
  1118. return 0;
  1119. }
  1120. /*
  1121. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1122. * @component: handle to snd_soc_component *
  1123. *
  1124. * return wcd9378_mbhc handle or error code in case of failure
  1125. */
  1126. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1127. {
  1128. struct wcd9378_priv *wcd9378;
  1129. if (!component) {
  1130. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1131. return NULL;
  1132. }
  1133. wcd9378 = snd_soc_component_get_drvdata(component);
  1134. if (!wcd9378) {
  1135. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1136. return NULL;
  1137. }
  1138. return wcd9378->mbhc;
  1139. }
  1140. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1141. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1142. struct snd_kcontrol *kcontrol,
  1143. int event)
  1144. {
  1145. struct snd_soc_component *component =
  1146. snd_soc_dapm_to_component(w->dapm);
  1147. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1148. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1149. w->name, event);
  1150. switch (event) {
  1151. case SND_SOC_DAPM_PRE_PMU:
  1152. /*HPHL ENABLE*/
  1153. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1154. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1155. wcd9378_rx_connect_port(component, HPH_L, true);
  1156. if (wcd9378->comp1_enable) {
  1157. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1158. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1159. wcd9378_rx_connect_port(component, COMP_L, true);
  1160. }
  1161. if (wcd9378->update_wcd_event)
  1162. wcd9378->update_wcd_event(wcd9378->handle,
  1163. SLV_BOLERO_EVT_RX_MUTE,
  1164. (WCD_RX1 << 0x10));
  1165. break;
  1166. case SND_SOC_DAPM_POST_PMD:
  1167. /*HPHL DISABLE*/
  1168. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1169. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1170. wcd9378_rx_connect_port(component, HPH_L, false);
  1171. if (wcd9378->comp1_enable) {
  1172. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1173. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1174. wcd9378_rx_connect_port(component, COMP_R, false);
  1175. }
  1176. break;
  1177. default:
  1178. break;
  1179. };
  1180. return 0;
  1181. }
  1182. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1183. struct snd_kcontrol *kcontrol,
  1184. int event)
  1185. {
  1186. struct snd_soc_component *component =
  1187. snd_soc_dapm_to_component(w->dapm);
  1188. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1189. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1190. w->name, event);
  1191. switch (event) {
  1192. case SND_SOC_DAPM_PRE_PMU:
  1193. /*HPHR ENABLE*/
  1194. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1195. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1196. wcd9378_rx_connect_port(component, HPH_R, true);
  1197. if (wcd9378->comp2_enable) {
  1198. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1199. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1200. wcd9378_rx_connect_port(component, COMP_R, true);
  1201. }
  1202. break;
  1203. case SND_SOC_DAPM_POST_PMD:
  1204. /*HPHR DISABLE*/
  1205. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1206. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1207. wcd9378_rx_connect_port(component, HPH_R, false);
  1208. if (wcd9378->comp2_enable) {
  1209. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1210. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1211. wcd9378_rx_connect_port(component, COMP_R, false);
  1212. }
  1213. break;
  1214. default:
  1215. break;
  1216. };
  1217. return 0;
  1218. }
  1219. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1220. struct snd_kcontrol *kcontrol,
  1221. int event)
  1222. {
  1223. struct snd_soc_component *component =
  1224. snd_soc_dapm_to_component(w->dapm);
  1225. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1226. int bank = 0;
  1227. int act_ps = 0;
  1228. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1229. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1230. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1231. w->name, event);
  1232. switch (event) {
  1233. case SND_SOC_DAPM_PRE_PMU:
  1234. if (wcd9378->update_wcd_event)
  1235. wcd9378->update_wcd_event(wcd9378->handle,
  1236. SLV_BOLERO_EVT_RX_MUTE,
  1237. (WCD_RX1 << 0x10 | 0x01));
  1238. if (wcd9378->update_wcd_event)
  1239. wcd9378->update_wcd_event(wcd9378->handle,
  1240. SLV_BOLERO_EVT_RX_MUTE,
  1241. (WCD_RX1 << 0x10));
  1242. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1243. if (act_ps)
  1244. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1245. __func__, act_ps);
  1246. else
  1247. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1248. __func__, act_ps);
  1249. break;
  1250. case SND_SOC_DAPM_POST_PMD:
  1251. if (wcd9378->update_wcd_event)
  1252. wcd9378->update_wcd_event(wcd9378->handle,
  1253. SLV_BOLERO_EVT_RX_MUTE,
  1254. (WCD_RX1 << 0x10 | 0x1));
  1255. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1256. wcd9378->update_wcd_event(wcd9378->handle,
  1257. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1258. (WCD_RX1 << 0x10));
  1259. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1260. WCD_EVENT_POST_HPHL_PA_OFF,
  1261. &wcd9378->mbhc->wcd_mbhc);
  1262. break;
  1263. default:
  1264. break;
  1265. };
  1266. return 0;
  1267. }
  1268. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1269. struct snd_kcontrol *kcontrol,
  1270. int event)
  1271. {
  1272. struct snd_soc_component *component =
  1273. snd_soc_dapm_to_component(w->dapm);
  1274. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1275. int act_ps = 0;
  1276. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1277. w->name, event);
  1278. switch (event) {
  1279. case SND_SOC_DAPM_PRE_PMU:
  1280. if (wcd9378->update_wcd_event)
  1281. wcd9378->update_wcd_event(wcd9378->handle,
  1282. SLV_BOLERO_EVT_RX_MUTE,
  1283. (WCD_RX2 << 0x10 | 0x1));
  1284. if (wcd9378->update_wcd_event)
  1285. wcd9378->update_wcd_event(wcd9378->handle,
  1286. SLV_BOLERO_EVT_RX_MUTE,
  1287. (WCD_RX2 << 0x10));
  1288. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1289. if (act_ps)
  1290. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1291. __func__, act_ps);
  1292. else
  1293. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1294. __func__, act_ps);
  1295. break;
  1296. case SND_SOC_DAPM_POST_PMD:
  1297. if (wcd9378->update_wcd_event)
  1298. wcd9378->update_wcd_event(wcd9378->handle,
  1299. SLV_BOLERO_EVT_RX_MUTE,
  1300. (WCD_RX2 << 0x10 | 0x1));
  1301. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1302. wcd9378->update_wcd_event(wcd9378->handle,
  1303. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1304. (WCD_RX2 << 0x10));
  1305. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1306. WCD_EVENT_POST_HPHR_PA_OFF,
  1307. &wcd9378->mbhc->wcd_mbhc);
  1308. break;
  1309. default:
  1310. break;
  1311. };
  1312. return 0;
  1313. }
  1314. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1315. struct snd_kcontrol *kcontrol,
  1316. int event)
  1317. {
  1318. struct snd_soc_component *component =
  1319. snd_soc_dapm_to_component(w->dapm);
  1320. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1321. int ret = 0;
  1322. int bank = 0;
  1323. int act_ps = 0;
  1324. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1325. w->name, event);
  1326. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1327. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1328. switch (event) {
  1329. case SND_SOC_DAPM_PRE_PMU:
  1330. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1331. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1332. wcd9378->rx_swr_dev->dev_num,
  1333. true);
  1334. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1335. wcd9378->aux_rx_path =
  1336. (snd_soc_component_read(
  1337. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1338. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK) >> 0x03;
  1339. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1340. if (wcd9378->update_wcd_event)
  1341. wcd9378->update_wcd_event(wcd9378->handle,
  1342. SLV_BOLERO_EVT_RX_MUTE,
  1343. (WCD_RX2 << 0x10));
  1344. } else {
  1345. if (wcd9378->update_wcd_event)
  1346. wcd9378->update_wcd_event(wcd9378->handle,
  1347. SLV_BOLERO_EVT_RX_MUTE,
  1348. (WCD_RX3 << 0x10));
  1349. }
  1350. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1351. if (act_ps)
  1352. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1353. __func__, act_ps);
  1354. else
  1355. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1356. __func__, act_ps);
  1357. break;
  1358. case SND_SOC_DAPM_POST_PMD:
  1359. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1360. if (wcd9378->update_wcd_event)
  1361. wcd9378->update_wcd_event(wcd9378->handle,
  1362. SLV_BOLERO_EVT_RX_MUTE,
  1363. (WCD_RX2 << 0x10 | 0x1));
  1364. } else {
  1365. if (wcd9378->update_wcd_event)
  1366. wcd9378->update_wcd_event(wcd9378->handle,
  1367. SLV_BOLERO_EVT_RX_MUTE,
  1368. (WCD_RX3 << 0x10 | 0x1));
  1369. }
  1370. break;
  1371. };
  1372. return ret;
  1373. }
  1374. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1375. struct snd_kcontrol *kcontrol,
  1376. int event)
  1377. {
  1378. struct snd_soc_component *component =
  1379. snd_soc_dapm_to_component(w->dapm);
  1380. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1381. int ret = 0, bank = 0;
  1382. int act_ps = 0;
  1383. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1384. w->name, event);
  1385. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1386. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1387. switch (event) {
  1388. case SND_SOC_DAPM_PRE_PMU:
  1389. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1390. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1391. wcd9378->rx_swr_dev->dev_num,
  1392. true);
  1393. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1394. wcd9378->ear_rx_path =
  1395. (snd_soc_component_read(
  1396. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1397. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK) >> 0x02;
  1398. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1399. if (wcd9378->update_wcd_event)
  1400. wcd9378->update_wcd_event(wcd9378->handle,
  1401. SLV_BOLERO_EVT_RX_MUTE,
  1402. (WCD_RX1 << 0x10));
  1403. } else {
  1404. if (wcd9378->update_wcd_event)
  1405. wcd9378->update_wcd_event(wcd9378->handle,
  1406. SLV_BOLERO_EVT_RX_MUTE,
  1407. (WCD_RX3 << 0x10));
  1408. }
  1409. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1410. if (act_ps)
  1411. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1412. __func__, act_ps);
  1413. else
  1414. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1415. __func__, act_ps);
  1416. break;
  1417. case SND_SOC_DAPM_POST_PMD:
  1418. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1419. if (wcd9378->update_wcd_event)
  1420. wcd9378->update_wcd_event(wcd9378->handle,
  1421. SLV_BOLERO_EVT_RX_MUTE,
  1422. (WCD_RX1 << 0x10 | 0x1));
  1423. } else {
  1424. if (wcd9378->update_wcd_event)
  1425. wcd9378->update_wcd_event(wcd9378->handle,
  1426. SLV_BOLERO_EVT_RX_MUTE,
  1427. (WCD_RX3 << 0x10 | 0x1));
  1428. }
  1429. break;
  1430. };
  1431. return ret;
  1432. }
  1433. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1434. {
  1435. switch (hph_mode) {
  1436. case CLS_H_LOHIFI:
  1437. case CLS_AB_LOHIFI:
  1438. return PWR_LEVEL_LOHIFI_VAL;
  1439. case CLS_H_LP:
  1440. case CLS_AB_LP:
  1441. return PWR_LEVEL_LP_VAL;
  1442. case CLS_H_HIFI:
  1443. case CLS_AB_HIFI:
  1444. return PWR_LEVEL_HIFI_VAL;
  1445. case CLS_H_ULP:
  1446. case CLS_AB:
  1447. case CLS_H_NORMAL:
  1448. default:
  1449. return PWR_LEVEL_ULP_VAL;
  1450. }
  1451. return PWR_LEVEL_ULP_VAL;
  1452. }
  1453. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1454. {
  1455. struct wcd9378_priv *wcd9378 =
  1456. snd_soc_component_get_drvdata(component);
  1457. if ((!wcd9378->comp1_enable) &&
  1458. (!wcd9378->comp2_enable)) {
  1459. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1460. snd_soc_component_update_bits(component,
  1461. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1462. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1463. wcd9378->hph_gain >> 8);
  1464. snd_soc_component_update_bits(component,
  1465. WCD9378_FU42_CH_VOL_CH1,
  1466. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1467. wcd9378->hph_gain & 0x00ff);
  1468. snd_soc_component_update_bits(component,
  1469. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1470. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1471. wcd9378->hph_gain >> 8);
  1472. snd_soc_component_update_bits(component,
  1473. WCD9378_FU42_CH_VOL_CH2,
  1474. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1475. wcd9378->hph_gain & 0x00ff);
  1476. }
  1477. }
  1478. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1479. {
  1480. u16 clk_scale_reg = 0;
  1481. u8 clk_rst = 0x00, scale_rst = 0x00;
  1482. u8 swr_base_clk = 0, swr_clk_scale = 0;
  1483. struct wcd9378_priv *wcd9378 = NULL;
  1484. struct swr_device *swr_dev = NULL;
  1485. wcd9378 = dev_get_drvdata(dev);
  1486. if (!wcd9378)
  1487. return -EINVAL;
  1488. if (path == RX_PATH) {
  1489. swr_dev = wcd9378->rx_swr_dev;
  1490. swr_base_clk = wcd9378->swr_base_clk;
  1491. swr_clk_scale = wcd9378->swr_clk_scale;
  1492. } else {
  1493. swr_dev = wcd9378->tx_swr_dev;
  1494. swr_base_clk = SWR_BASECLK_19P2MHZ;
  1495. swr_clk_scale = SWR_CLKSCALE_DIV2;
  1496. }
  1497. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1498. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1499. if (enable) {
  1500. swr_write(swr_dev, swr_dev->dev_num,
  1501. SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
  1502. swr_write(swr_dev, swr_dev->dev_num,
  1503. clk_scale_reg, &swr_clk_scale);
  1504. } else {
  1505. swr_write(swr_dev, swr_dev->dev_num,
  1506. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1507. swr_write(swr_dev, swr_dev->dev_num,
  1508. clk_scale_reg, &scale_rst);
  1509. }
  1510. return 0;
  1511. }
  1512. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1513. struct snd_kcontrol *kcontrol, int event)
  1514. {
  1515. struct snd_soc_component *component =
  1516. snd_soc_dapm_to_component(w->dapm);
  1517. struct wcd9378_priv *wcd9378 =
  1518. snd_soc_component_get_drvdata(component);
  1519. int power_level, bank = 0;
  1520. int ret = 0;
  1521. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1522. u8 scp_commit_val = 0x2;
  1523. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1524. w->name, event);
  1525. switch (event) {
  1526. case SND_SOC_DAPM_PRE_PMU:
  1527. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1528. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1529. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1530. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1531. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1532. }
  1533. if ((wcd9378->hph_mode == CLS_AB) ||
  1534. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1535. (wcd9378->hph_mode == CLS_AB_LP) ||
  1536. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1537. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1538. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1539. /*GET HPH_MODE*/
  1540. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1541. /*SET HPH_MODE*/
  1542. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1543. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1544. /*TURN ON HPH SEQUENCER*/
  1545. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1546. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1547. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1548. wcd9378_hph_set_channel_volume(component);
  1549. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1550. /*PA delay is 22400us*/
  1551. usleep_range(22500, 22510);
  1552. else
  1553. /*COMP delay is 9400us*/
  1554. usleep_range(9500, 9510);
  1555. /*RX0 unmute*/
  1556. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1557. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1558. /*RX1 unmute*/
  1559. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1560. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1561. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1562. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1563. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1564. wcd9378->rx_swr_dev->dev_num,
  1565. true);
  1566. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1567. break;
  1568. case SND_SOC_DAPM_POST_PMD:
  1569. /*RX0 mute*/
  1570. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1571. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1572. /*RX1 mute*/
  1573. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1574. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1575. /*TEAR DOWN HPH SEQUENCER*/
  1576. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1577. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1578. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1579. /*PA delay is 24250us*/
  1580. usleep_range(24300, 24310);
  1581. else
  1582. /*COMP delay is 11250us*/
  1583. usleep_range(11300, 11310);
  1584. break;
  1585. default:
  1586. break;
  1587. };
  1588. return ret;
  1589. }
  1590. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1591. struct snd_kcontrol *kcontrol,
  1592. int event)
  1593. {
  1594. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1595. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1596. int ear_rx0 = 0;
  1597. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1598. w->name, event);
  1599. ear_rx0 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1600. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK;
  1601. switch (event) {
  1602. case SND_SOC_DAPM_PRE_PMU:
  1603. /*CHECK IF EAR CONNET TO RX2*/
  1604. if (!ear_rx0) {
  1605. pr_debug("%s: ear rx2 enter\n", __func__);
  1606. /*FORCE CLASS_AB EN*/
  1607. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1608. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1609. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1610. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1611. /*RX2 ENABLE*/
  1612. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1613. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1614. if (wcd9378->rx2_clk_mode)
  1615. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1616. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1617. wcd9378_rx_connect_port(component, LO, true);
  1618. } else {
  1619. pr_debug("%s: ear rx0 enter\n", __func__);
  1620. if (wcd9378->comp1_enable) {
  1621. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1622. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1623. wcd9378_rx_connect_port(component, COMP_L, true);
  1624. }
  1625. wcd9378_rx_connect_port(component, HPH_L, true);
  1626. }
  1627. break;
  1628. case SND_SOC_DAPM_POST_PMD:
  1629. if (ear_rx0) {
  1630. /*RX0 DISABLE*/
  1631. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1632. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1633. wcd9378_rx_connect_port(component, HPH_L, false);
  1634. if (wcd9378->comp1_enable) {
  1635. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1636. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1637. wcd9378_rx_connect_port(component, COMP_L, false);
  1638. }
  1639. } else {
  1640. /*RX1 DISABLE*/
  1641. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1642. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1643. wcd9378_rx_connect_port(component, LO, false);
  1644. }
  1645. break;
  1646. };
  1647. return 0;
  1648. }
  1649. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1650. struct snd_kcontrol *kcontrol,
  1651. int event)
  1652. {
  1653. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1654. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1655. int aux_rx1 = 0;
  1656. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1657. w->name, event);
  1658. aux_rx1 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1659. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK;
  1660. switch (event) {
  1661. case SND_SOC_DAPM_PRE_PMU:
  1662. if (aux_rx1) {
  1663. wcd9378_rx_connect_port(component, HPH_R, true);
  1664. } else {
  1665. /*RX2 ENABLE*/
  1666. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1667. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1668. if (wcd9378->rx2_clk_mode)
  1669. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1670. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1671. wcd9378_rx_connect_port(component, LO, true);
  1672. }
  1673. break;
  1674. case SND_SOC_DAPM_POST_PMD:
  1675. if (aux_rx1) {
  1676. wcd9378_rx_connect_port(component, HPH_R, false);
  1677. } else {
  1678. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1679. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1680. wcd9378_rx_connect_port(component, LO, false);
  1681. }
  1682. break;
  1683. };
  1684. return 0;
  1685. }
  1686. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1687. struct snd_kcontrol *kcontrol, int event)
  1688. {
  1689. struct snd_soc_component *component =
  1690. snd_soc_dapm_to_component(w->dapm);
  1691. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1692. w->name, event);
  1693. switch (event) {
  1694. case SND_SOC_DAPM_PRE_PMU:
  1695. /*TURN ON AMP SEQUENCER*/
  1696. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1697. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1698. /*default delay 8550us*/
  1699. usleep_range(8600, 8610);
  1700. /*FU23 UNMUTE*/
  1701. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1702. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1703. break;
  1704. case SND_SOC_DAPM_POST_PMD:
  1705. /*FU23 MUTE*/
  1706. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1707. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1708. /*TEAR DOWN AMP SEQUENCER*/
  1709. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1710. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1711. /*default delay 1530us*/
  1712. usleep_range(15400, 15410);
  1713. break;
  1714. default:
  1715. break;
  1716. };
  1717. return 0;
  1718. }
  1719. int wcd9378_micbias_control(struct snd_soc_component *component,
  1720. unsigned char tx_path, int req, bool is_dapm)
  1721. {
  1722. struct wcd9378_priv *wcd9378 =
  1723. snd_soc_component_get_drvdata(component);
  1724. struct wcd9378_pdata *pdata =
  1725. dev_get_platdata(wcd9378->dev);
  1726. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1727. int micb_num = 0, micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1728. int pre_off_event = 0, post_off_event = 0;
  1729. int post_on_event = 0, post_dapm_off = 0;
  1730. int post_dapm_on = 0;
  1731. int pull_up_mask = 0, pull_up_en = 0;
  1732. int micb_index = 0, ret = 0;
  1733. switch (tx_path) {
  1734. case ADC1:
  1735. micb_num = wcd9378->micb_sel[0];
  1736. micb_usage = WCD9378_IT11_MICB;
  1737. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1738. break;
  1739. case ADC2:
  1740. if (wcd9378->sjmic_support) {
  1741. micb_num = MIC_BIAS_2;
  1742. micb_usage = WCD9378_IT31_MICB;
  1743. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  1744. } else {
  1745. micb_num = wcd9378->micb_sel[1];
  1746. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1747. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1748. }
  1749. break;
  1750. case ADC3:
  1751. micb_num = wcd9378->micb_sel[2];
  1752. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1753. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1754. break;
  1755. default:
  1756. pr_err("%s: unsupport tx path\n", __func__);
  1757. return -EINVAL;
  1758. }
  1759. switch (micb_num) {
  1760. case MIC_BIAS_1:
  1761. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1762. pull_up_en = 0x01;
  1763. micb_usage_val = mb->micb1_usage_val;
  1764. break;
  1765. case MIC_BIAS_2:
  1766. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1767. pull_up_en = 0x02;
  1768. micb_usage_val = mb->micb2_usage_val;
  1769. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1770. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1771. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1772. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1773. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1774. break;
  1775. case MIC_BIAS_3:
  1776. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1777. pull_up_en = 0x04;
  1778. micb_usage_val = mb->micb3_usage_val;
  1779. break;
  1780. default:
  1781. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1782. __func__, micb_num);
  1783. return -EINVAL;
  1784. }
  1785. mutex_lock(&wcd9378->micb_lock);
  1786. micb_index = micb_num - 1;
  1787. switch (req) {
  1788. case MICB_PULLUP_ENABLE:
  1789. wcd9378->pullup_ref[micb_index]++;
  1790. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1791. (wcd9378->micb_ref[micb_index] == 0)) {
  1792. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1793. pull_up_mask, pull_up_en);
  1794. snd_soc_component_update_bits(component,
  1795. micb_usage, micb_mask, 0x03);
  1796. }
  1797. break;
  1798. case MICB_PULLUP_DISABLE:
  1799. if (wcd9378->pullup_ref[micb_index] > 0)
  1800. wcd9378->pullup_ref[micb_index]--;
  1801. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1802. (wcd9378->micb_ref[micb_index] == 0))
  1803. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1804. break;
  1805. case MICB_ENABLE:
  1806. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1807. __func__);
  1808. if (!wcd9378->dev_up) {
  1809. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1810. __func__, req);
  1811. ret = -ENODEV;
  1812. goto done;
  1813. }
  1814. wcd9378->micb_ref[micb_index]++;
  1815. if (wcd9378->micb_ref[micb_index] == 1) {
  1816. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  1817. __func__, micb_usage, micb_usage_val);
  1818. snd_soc_component_update_bits(component,
  1819. micb_usage, micb_mask, micb_usage_val);
  1820. if (post_on_event)
  1821. blocking_notifier_call_chain(
  1822. &wcd9378->mbhc->notifier,
  1823. post_on_event,
  1824. &wcd9378->mbhc->wcd_mbhc);
  1825. }
  1826. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  1827. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1828. post_dapm_on,
  1829. &wcd9378->mbhc->wcd_mbhc);
  1830. break;
  1831. case MICB_DISABLE:
  1832. if (wcd9378->micb_ref[micb_index] > 0)
  1833. wcd9378->micb_ref[micb_index]--;
  1834. if ((wcd9378->micb_ref[micb_index] == 0) &&
  1835. (wcd9378->pullup_ref[micb_index] > 0)) {
  1836. /*PULL UP?*/
  1837. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1838. pull_up_mask, pull_up_en);
  1839. snd_soc_component_update_bits(component, micb_usage,
  1840. micb_mask, 0x03);
  1841. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  1842. (wcd9378->pullup_ref[micb_index] == 0)) {
  1843. if (pre_off_event && wcd9378->mbhc)
  1844. blocking_notifier_call_chain(
  1845. &wcd9378->mbhc->notifier,
  1846. pre_off_event,
  1847. &wcd9378->mbhc->wcd_mbhc);
  1848. snd_soc_component_update_bits(component, micb_usage,
  1849. micb_mask, 0x00);
  1850. if (post_off_event && wcd9378->mbhc)
  1851. blocking_notifier_call_chain(
  1852. &wcd9378->mbhc->notifier,
  1853. post_off_event,
  1854. &wcd9378->mbhc->wcd_mbhc);
  1855. }
  1856. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  1857. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1858. post_dapm_off,
  1859. &wcd9378->mbhc->wcd_mbhc);
  1860. break;
  1861. default:
  1862. dev_err(component->dev, "%s: Invalid req event: %d\n",
  1863. __func__, req);
  1864. return -EINVAL;
  1865. }
  1866. dev_dbg(component->dev,
  1867. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1868. __func__, micb_num, wcd9378->micb_ref[micb_index],
  1869. wcd9378->pullup_ref[micb_index]);
  1870. done:
  1871. mutex_unlock(&wcd9378->micb_lock);
  1872. return ret;
  1873. }
  1874. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  1875. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  1876. {
  1877. int ret = 0;
  1878. uint8_t devnum = 0;
  1879. int num_retry = NUM_ATTEMPTS;
  1880. do {
  1881. /* retry after 4ms */
  1882. usleep_range(4000, 4010);
  1883. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1884. } while (ret && --num_retry);
  1885. if (ret)
  1886. dev_err(&swr_dev->dev,
  1887. "%s get devnum %d for dev addr %llx failed\n",
  1888. __func__, devnum, swr_dev->addr);
  1889. swr_dev->dev_num = devnum;
  1890. return 0;
  1891. }
  1892. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1893. struct wcd_mbhc_config *mbhc_cfg)
  1894. {
  1895. if (mbhc_cfg->enable_usbc_analog) {
  1896. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  1897. & 0x20))
  1898. return true;
  1899. }
  1900. return false;
  1901. }
  1902. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  1903. struct notifier_block *nblock,
  1904. bool enable)
  1905. {
  1906. struct wcd9378_priv *wcd9378_priv = NULL;
  1907. if (component == NULL) {
  1908. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  1909. return -EINVAL;
  1910. }
  1911. wcd9378_priv = snd_soc_component_get_drvdata(component);
  1912. wcd9378_priv->notify_swr_dmic = enable;
  1913. if (enable)
  1914. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  1915. nblock);
  1916. else
  1917. return blocking_notifier_chain_unregister(
  1918. &wcd9378_priv->notifier, nblock);
  1919. }
  1920. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  1921. static int wcd9378_event_notify(struct notifier_block *block,
  1922. unsigned long val,
  1923. void *data)
  1924. {
  1925. u16 event = (val & 0xffff);
  1926. int ret = 0;
  1927. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  1928. struct snd_soc_component *component = wcd9378->component;
  1929. struct wcd_mbhc *mbhc;
  1930. int rx_clk_type;
  1931. switch (event) {
  1932. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1933. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  1934. snd_soc_component_update_bits(component,
  1935. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  1936. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  1937. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  1938. }
  1939. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  1940. snd_soc_component_update_bits(component,
  1941. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  1942. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  1943. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  1944. }
  1945. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  1946. snd_soc_component_update_bits(component,
  1947. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  1948. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  1949. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  1950. }
  1951. break;
  1952. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1953. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  1954. 0xC0, 0x00);
  1955. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1956. 0x80, 0x00);
  1957. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1958. 0x80, 0x00);
  1959. break;
  1960. case BOLERO_SLV_EVT_SSR_DOWN:
  1961. wcd9378->dev_up = false;
  1962. if (wcd9378->notify_swr_dmic)
  1963. blocking_notifier_call_chain(&wcd9378->notifier,
  1964. WCD9378_EVT_SSR_DOWN,
  1965. NULL);
  1966. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  1967. mbhc = &wcd9378->mbhc->wcd_mbhc;
  1968. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  1969. mbhc->mbhc_cfg);
  1970. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  1971. wcd9378_reset_low(wcd9378->dev);
  1972. break;
  1973. case BOLERO_SLV_EVT_SSR_UP:
  1974. wcd9378_reset(wcd9378->dev);
  1975. /* allow reset to take effect */
  1976. usleep_range(10000, 10010);
  1977. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  1978. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  1979. wcd9378->tx_swr_dev->scp1_val = 0;
  1980. wcd9378->tx_swr_dev->scp2_val = 0;
  1981. wcd9378->rx_swr_dev->scp1_val = 0;
  1982. wcd9378->rx_swr_dev->scp2_val = 0;
  1983. wcd9378_init_reg(component);
  1984. regcache_mark_dirty(wcd9378->regmap);
  1985. regcache_sync(wcd9378->regmap);
  1986. /* Initialize MBHC module */
  1987. mbhc = &wcd9378->mbhc->wcd_mbhc;
  1988. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  1989. if (ret) {
  1990. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1991. __func__);
  1992. } else {
  1993. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1994. }
  1995. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  1996. wcd9378->dev_up = true;
  1997. if (wcd9378->notify_swr_dmic)
  1998. blocking_notifier_call_chain(&wcd9378->notifier,
  1999. WCD9378_EVT_SSR_UP,
  2000. NULL);
  2001. if (wcd9378->usbc_hs_status)
  2002. mdelay(500);
  2003. break;
  2004. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2005. snd_soc_component_update_bits(component,
  2006. WCD9378_TOP_CLK_CFG, 0x06,
  2007. ((val >> 0x10) << 0x01));
  2008. rx_clk_type = (val >> 0x10);
  2009. switch (rx_clk_type) {
  2010. case RX_CLK_12P288MHZ:
  2011. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2012. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2013. break;
  2014. case RX_CLK_11P2896MHZ:
  2015. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2016. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2017. break;
  2018. default:
  2019. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2020. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2021. break;
  2022. }
  2023. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2024. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2025. break;
  2026. default:
  2027. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2028. break;
  2029. }
  2030. return 0;
  2031. }
  2032. static int wcd9378_wakeup(void *handle, bool enable)
  2033. {
  2034. struct wcd9378_priv *priv;
  2035. int ret = 0;
  2036. if (!handle) {
  2037. pr_err("%s: NULL handle\n", __func__);
  2038. return -EINVAL;
  2039. }
  2040. priv = (struct wcd9378_priv *)handle;
  2041. if (!priv->tx_swr_dev) {
  2042. pr_err("%s: tx swr dev is NULL\n", __func__);
  2043. return -EINVAL;
  2044. }
  2045. mutex_lock(&priv->wakeup_lock);
  2046. if (enable)
  2047. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2048. else
  2049. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2050. mutex_unlock(&priv->wakeup_lock);
  2051. return ret;
  2052. }
  2053. static inline int wcd9378_tx_path_get(const char *wname,
  2054. unsigned int *path_num)
  2055. {
  2056. int ret = 0;
  2057. char *widget_name = NULL;
  2058. char *w_name = NULL;
  2059. char *path_num_char = NULL;
  2060. char *path_name = NULL;
  2061. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2062. if (!widget_name)
  2063. return -EINVAL;
  2064. w_name = widget_name;
  2065. path_name = strsep(&widget_name, " ");
  2066. if (!path_name) {
  2067. pr_err("%s: Invalid widget name = %s\n",
  2068. __func__, widget_name);
  2069. ret = -EINVAL;
  2070. goto err;
  2071. }
  2072. path_num_char = strpbrk(path_name, "0123");
  2073. if (!path_num_char) {
  2074. pr_err("%s: tx path index not found\n",
  2075. __func__);
  2076. ret = -EINVAL;
  2077. goto err;
  2078. }
  2079. ret = kstrtouint(path_num_char, 10, path_num);
  2080. if (ret < 0)
  2081. pr_err("%s: Invalid tx path = %s\n",
  2082. __func__, w_name);
  2083. err:
  2084. kfree(w_name);
  2085. return ret;
  2086. }
  2087. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2088. struct snd_ctl_elem_value *ucontrol)
  2089. {
  2090. struct snd_soc_component *component =
  2091. snd_soc_kcontrol_component(kcontrol);
  2092. struct wcd9378_priv *wcd9378 = NULL;
  2093. int ret = 0;
  2094. unsigned int path = 0;
  2095. if (!component)
  2096. return -EINVAL;
  2097. wcd9378 = snd_soc_component_get_drvdata(component);
  2098. if (!wcd9378)
  2099. return -EINVAL;
  2100. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2101. if (ret < 0)
  2102. return ret;
  2103. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2104. return 0;
  2105. }
  2106. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2107. struct snd_ctl_elem_value *ucontrol)
  2108. {
  2109. struct snd_soc_component *component =
  2110. snd_soc_kcontrol_component(kcontrol);
  2111. struct wcd9378_priv *wcd9378 = NULL;
  2112. u32 mode_val;
  2113. unsigned int path = 0;
  2114. int ret = 0;
  2115. if (!component)
  2116. return -EINVAL;
  2117. wcd9378 = snd_soc_component_get_drvdata(component);
  2118. if (!wcd9378)
  2119. return -EINVAL;
  2120. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2121. if (ret)
  2122. return ret;
  2123. mode_val = ucontrol->value.enumerated.item[0];
  2124. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2125. wcd9378->tx_mode[path] = mode_val;
  2126. return 0;
  2127. }
  2128. static int wcd9378_sys_usage_get(struct snd_kcontrol *kcontrol,
  2129. struct snd_ctl_elem_value *ucontrol)
  2130. {
  2131. struct snd_soc_component *component =
  2132. snd_soc_kcontrol_component(kcontrol);
  2133. u32 sys_usage_val = 0;
  2134. if (!component)
  2135. return -EINVAL;
  2136. sys_usage_val = (snd_soc_component_read(component, WCD9378_SYS_USAGE_CTRL) &
  2137. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK);
  2138. ucontrol->value.integer.value[0] = sys_usage_val;
  2139. return 0;
  2140. }
  2141. static int wcd9378_sys_usage_put(struct snd_kcontrol *kcontrol,
  2142. struct snd_ctl_elem_value *ucontrol)
  2143. {
  2144. struct snd_soc_component *component =
  2145. snd_soc_kcontrol_component(kcontrol);
  2146. struct wcd9378_priv *wcd9378 = NULL;
  2147. u32 sys_usage_val = 0;
  2148. if (!component)
  2149. return -EINVAL;
  2150. wcd9378 = snd_soc_component_get_drvdata(component);
  2151. if (!wcd9378)
  2152. return -EINVAL;
  2153. sys_usage_val = ucontrol->value.enumerated.item[0];
  2154. if (sys_usage_val >= WCD_SYS_USAGE_MAX) {
  2155. dev_err(component->dev, "%s: unsupport sys_usage_val: %d\n",
  2156. __func__, sys_usage_val);
  2157. return -EINVAL;
  2158. }
  2159. if (wcd9378->sys_usage != sys_usage_val)
  2160. snd_soc_component_update_bits(component,
  2161. WCD9378_SYS_USAGE_CTRL,
  2162. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  2163. sys_usage_val);
  2164. wcd9378->sys_usage = sys_usage_val;
  2165. switch (wcd9378->sys_usage) {
  2166. case SJ_SA_AUX_2SM:
  2167. case SJ_SA_AUX_2SM_1HDR:
  2168. case SJ_SA_EAR_2SM:
  2169. case SJ_SA_EAR_2SM_1HDR:
  2170. case SJ_1HDR_SA_AUX_1SM:
  2171. case SJ_1HDR_SA_EAR_1SM:
  2172. wcd9378->sjmic_support = true;
  2173. break;
  2174. case NOSJ_SA_STEREO_3SM:
  2175. case NOSJ_SA_STEREO_3SM_1HDR:
  2176. case NOSJ_SA_EAR_3SM:
  2177. case NOSJ_SA_EAR_3SM_1HDR:
  2178. case SJ_NOMIC_SA_EAR_3SM:
  2179. case SJ_NOMIC_SA_AUX_3SM:
  2180. wcd9378->sjmic_support = false;
  2181. break;
  2182. default:
  2183. dev_err(component->dev, "%s: unsupport sys_usage: %d\n",
  2184. __func__, wcd9378->sys_usage);
  2185. return -EINVAL;
  2186. }
  2187. dev_err(component->dev, "%s: sys_usage_val: %d, sjmic_support: %d\n",
  2188. __func__, wcd9378->sys_usage, wcd9378->sjmic_support);
  2189. return 0;
  2190. }
  2191. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2192. struct snd_ctl_elem_value *ucontrol)
  2193. {
  2194. struct snd_soc_component *component =
  2195. snd_soc_kcontrol_component(kcontrol);
  2196. u32 loopback_mode = 0;
  2197. if (!component)
  2198. return -EINVAL;
  2199. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2200. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2201. ucontrol->value.integer.value[0] = loopback_mode;
  2202. return 0;
  2203. }
  2204. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2205. struct snd_ctl_elem_value *ucontrol)
  2206. {
  2207. struct snd_soc_component *component =
  2208. snd_soc_kcontrol_component(kcontrol);
  2209. u32 loopback_mode = 0;
  2210. if (!component)
  2211. return -EINVAL;
  2212. loopback_mode = ucontrol->value.enumerated.item[0];
  2213. snd_soc_component_update_bits(component,
  2214. WCD9378_LOOP_BACK_MODE,
  2215. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2216. loopback_mode);
  2217. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2218. __func__, loopback_mode);
  2219. return 0;
  2220. }
  2221. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2222. struct snd_ctl_elem_value *ucontrol)
  2223. {
  2224. struct snd_soc_component *component =
  2225. snd_soc_kcontrol_component(kcontrol);
  2226. u32 aux_dsm_in = 0;
  2227. if (!component)
  2228. return -EINVAL;
  2229. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2230. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2231. ucontrol->value.integer.value[0] = aux_dsm_in;
  2232. return 0;
  2233. }
  2234. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2235. struct snd_ctl_elem_value *ucontrol)
  2236. {
  2237. struct snd_soc_component *component =
  2238. snd_soc_kcontrol_component(kcontrol);
  2239. u32 aux_dsm_in = 0;
  2240. if (!component)
  2241. return -EINVAL;
  2242. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2243. snd_soc_component_update_bits(component,
  2244. WCD9378_LB_IN_SEL_CTL,
  2245. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2246. aux_dsm_in);
  2247. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2248. __func__, aux_dsm_in);
  2249. return 0;
  2250. }
  2251. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2252. struct snd_ctl_elem_value *ucontrol)
  2253. {
  2254. struct snd_soc_component *component =
  2255. snd_soc_kcontrol_component(kcontrol);
  2256. u32 hph_dsm_in = 0;
  2257. if (!component)
  2258. return -EINVAL;
  2259. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2260. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2261. ucontrol->value.integer.value[0] = hph_dsm_in;
  2262. return 0;
  2263. }
  2264. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2265. struct snd_ctl_elem_value *ucontrol)
  2266. {
  2267. struct snd_soc_component *component =
  2268. snd_soc_kcontrol_component(kcontrol);
  2269. u32 hph_dsm_in = 0;
  2270. if (!component)
  2271. return -EINVAL;
  2272. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2273. snd_soc_component_update_bits(component,
  2274. WCD9378_LB_IN_SEL_CTL,
  2275. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2276. hph_dsm_in);
  2277. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2278. __func__, hph_dsm_in);
  2279. return 0;
  2280. }
  2281. static inline int wcd9378_simple_mic_num_get(const char *wname,
  2282. unsigned int *sm_num)
  2283. {
  2284. int ret = 0;
  2285. char *widget_name = NULL;
  2286. char *w_name = NULL;
  2287. char *sm_num_char = NULL;
  2288. char *sm_name = NULL;
  2289. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2290. if (!widget_name)
  2291. return -EINVAL;
  2292. w_name = widget_name;
  2293. sm_name = strsep(&widget_name, " ");
  2294. if (!sm_name) {
  2295. pr_err("%s: Invalid widget name = %s\n",
  2296. __func__, widget_name);
  2297. ret = -EINVAL;
  2298. goto err;
  2299. }
  2300. sm_num_char = strpbrk(sm_name, "0123");
  2301. if (!sm_num_char) {
  2302. pr_err("%s: simple mic index not found\n",
  2303. __func__);
  2304. ret = -EINVAL;
  2305. goto err;
  2306. }
  2307. ret = kstrtouint(sm_num_char, 10, sm_num);
  2308. if (ret < 0)
  2309. pr_err("%s: Invalid micb num = %s\n",
  2310. __func__, w_name);
  2311. err:
  2312. kfree(w_name);
  2313. return ret;
  2314. }
  2315. static int wcd9378_mb_sel_get(struct snd_kcontrol *kcontrol,
  2316. struct snd_ctl_elem_value *ucontrol)
  2317. {
  2318. struct snd_soc_component *component =
  2319. snd_soc_kcontrol_component(kcontrol);
  2320. struct wcd9378_priv *wcd9378 = NULL;
  2321. int ret = 0;
  2322. unsigned int sm_num = 0;
  2323. if (!component)
  2324. return -EINVAL;
  2325. wcd9378 = snd_soc_component_get_drvdata(component);
  2326. if (!wcd9378)
  2327. return -EINVAL;
  2328. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2329. if (ret < 0)
  2330. return ret;
  2331. ucontrol->value.integer.value[0] = wcd9378->micb_sel[sm_num];
  2332. return 0;
  2333. }
  2334. static int wcd9378_mb_sel_put(struct snd_kcontrol *kcontrol,
  2335. struct snd_ctl_elem_value *ucontrol)
  2336. {
  2337. struct snd_soc_component *component =
  2338. snd_soc_kcontrol_component(kcontrol);
  2339. struct wcd9378_priv *wcd9378 = NULL;
  2340. u32 micb_num = 0, sm_sel = 0, sm_sel_mask = 0;
  2341. unsigned int sm_num = 0;
  2342. int ret = 0;
  2343. if (!component)
  2344. return -EINVAL;
  2345. wcd9378 = snd_soc_component_get_drvdata(component);
  2346. if (!wcd9378)
  2347. return -EINVAL;
  2348. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2349. if (ret)
  2350. return ret;
  2351. switch (sm_num) {
  2352. case SIM_MIC0:
  2353. sm_sel = WCD9378_SM0_MB_SEL;
  2354. sm_sel_mask = WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK;
  2355. break;
  2356. case SIM_MIC1:
  2357. sm_sel = WCD9378_SM1_MB_SEL;
  2358. sm_sel_mask = WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK;
  2359. break;
  2360. case SIM_MIC2:
  2361. sm_sel = WCD9378_SM2_MB_SEL;
  2362. sm_sel_mask = WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK;
  2363. break;
  2364. default:
  2365. pr_err("%s: unsupport sm_num: %d\n", __func__, sm_num);
  2366. return -EINVAL;
  2367. }
  2368. micb_num = ucontrol->value.enumerated.item[0];
  2369. if (micb_num >= MICB_NUM) {
  2370. pr_err("%s: unsupport micb num\n", __func__);
  2371. return -EINVAL;
  2372. }
  2373. snd_soc_component_update_bits(component, sm_sel,
  2374. sm_sel_mask, micb_num);
  2375. wcd9378->micb_sel[sm_num] = micb_num;
  2376. dev_err(component->dev, "%s: sm%d_mb_sel :%d\n",
  2377. __func__, sm_num, micb_num);
  2378. return 0;
  2379. }
  2380. /*TBD: NEED CHECK THE LOGIC*/
  2381. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2382. struct snd_ctl_elem_value *ucontrol)
  2383. {
  2384. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2385. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2386. u16 offset = ucontrol->value.enumerated.item[0];
  2387. u32 temp = 0;
  2388. temp = 0x00 - offset * 0x180;
  2389. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2390. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2391. return 0;
  2392. }
  2393. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2394. struct snd_ctl_elem_value *ucontrol)
  2395. {
  2396. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2397. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2398. u32 temp = 0;
  2399. u16 offset = 0;
  2400. temp = 0 - wcd9378->hph_gain;
  2401. offset = (u16)(temp & 0xffff);
  2402. offset /= 0x180;
  2403. ucontrol->value.enumerated.item[0] = offset;
  2404. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2405. return 0;
  2406. }
  2407. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2408. struct snd_ctl_elem_value *ucontrol)
  2409. {
  2410. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2411. struct wcd9378_priv *wcd9378 =
  2412. snd_soc_component_get_drvdata(component);
  2413. if (ucontrol->value.enumerated.item[0])
  2414. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2415. else
  2416. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2417. return 1;
  2418. }
  2419. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2420. struct snd_ctl_elem_value *ucontrol)
  2421. {
  2422. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2423. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2424. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2425. return 0;
  2426. }
  2427. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2428. struct snd_ctl_elem_value *ucontrol)
  2429. {
  2430. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2431. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2432. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2433. return 0;
  2434. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2435. return 1;
  2436. }
  2437. /* wcd9378_codec_get_dev_num - returns swr device number
  2438. * @component: Codec instance
  2439. *
  2440. * Return: swr device number on success or negative error
  2441. * code on failure.
  2442. */
  2443. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2444. {
  2445. struct wcd9378_priv *wcd9378;
  2446. if (!component)
  2447. return -EINVAL;
  2448. wcd9378 = snd_soc_component_get_drvdata(component);
  2449. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2450. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2451. return -EINVAL;
  2452. }
  2453. return wcd9378->rx_swr_dev->dev_num;
  2454. }
  2455. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2456. static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
  2457. struct snd_ctl_elem_value *ucontrol)
  2458. {
  2459. struct snd_soc_component *component =
  2460. snd_soc_kcontrol_component(kcontrol);
  2461. struct wcd9378_priv *wcd9378 =
  2462. snd_soc_component_get_drvdata(component);
  2463. if (wcd9378->comp1_enable) {
  2464. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2465. return -EINVAL;
  2466. }
  2467. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2468. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2469. ucontrol->value.integer.value[0]);
  2470. return 1;
  2471. }
  2472. static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
  2473. struct snd_ctl_elem_value *ucontrol)
  2474. {
  2475. struct snd_soc_component *component =
  2476. snd_soc_kcontrol_component(kcontrol);
  2477. struct wcd9378_priv *wcd9378 =
  2478. snd_soc_component_get_drvdata(component);
  2479. if (wcd9378->comp1_enable) {
  2480. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2481. return -EINVAL;
  2482. }
  2483. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2484. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2485. ucontrol->value.integer.value[0]);
  2486. return 1;
  2487. }
  2488. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2489. struct snd_ctl_elem_value *ucontrol)
  2490. {
  2491. struct snd_soc_component *component =
  2492. snd_soc_kcontrol_component(kcontrol);
  2493. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2494. bool hphr;
  2495. struct soc_multi_mixer_control *mc;
  2496. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2497. hphr = mc->shift;
  2498. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2499. wcd9378->comp1_enable;
  2500. return 0;
  2501. }
  2502. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2503. struct snd_ctl_elem_value *ucontrol)
  2504. {
  2505. struct snd_soc_component *component =
  2506. snd_soc_kcontrol_component(kcontrol);
  2507. struct wcd9378_priv *wcd9378 =
  2508. snd_soc_component_get_drvdata(component);
  2509. int value = ucontrol->value.integer.value[0];
  2510. bool hphr;
  2511. struct soc_multi_mixer_control *mc;
  2512. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2513. hphr = mc->shift;
  2514. if (hphr)
  2515. wcd9378->comp2_enable = value;
  2516. else
  2517. wcd9378->comp1_enable = value;
  2518. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2519. return 0;
  2520. }
  2521. static int wcd9378_get_va_amic_switch(struct snd_kcontrol *kcontrol,
  2522. struct snd_ctl_elem_value *ucontrol)
  2523. {
  2524. struct snd_soc_component *component =
  2525. snd_soc_kcontrol_component(kcontrol);
  2526. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2527. ucontrol->value.integer.value[0] = wcd9378->va_amic_en;
  2528. return 0;
  2529. }
  2530. static int wcd9378_set_va_amic_switch(struct snd_kcontrol *kcontrol,
  2531. struct snd_ctl_elem_value *ucontrol)
  2532. {
  2533. struct snd_soc_component *component =
  2534. snd_soc_kcontrol_component(kcontrol);
  2535. struct wcd9378_priv *wcd9378 =
  2536. snd_soc_component_get_drvdata(component);
  2537. int value = ucontrol->value.integer.value[0];
  2538. wcd9378->va_amic_en = value;
  2539. return 0;
  2540. }
  2541. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2542. struct snd_kcontrol *kcontrol,
  2543. int event)
  2544. {
  2545. struct snd_soc_component *component =
  2546. snd_soc_dapm_to_component(w->dapm);
  2547. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2548. struct wcd9378_pdata *pdata = NULL;
  2549. int ret = 0;
  2550. pdata = dev_get_platdata(wcd9378->dev);
  2551. if (!pdata) {
  2552. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2553. return -EINVAL;
  2554. }
  2555. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2556. wcd9378->supplies,
  2557. pdata->regulator,
  2558. pdata->num_supplies,
  2559. "cdc-vdd-buck"))
  2560. return 0;
  2561. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2562. w->name, event);
  2563. switch (event) {
  2564. case SND_SOC_DAPM_PRE_PMU:
  2565. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2566. dev_dbg(component->dev,
  2567. "%s: buck already in enabled state\n",
  2568. __func__);
  2569. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2570. return 0;
  2571. }
  2572. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2573. wcd9378->supplies,
  2574. pdata->regulator,
  2575. pdata->num_supplies,
  2576. "cdc-vdd-buck");
  2577. if (ret == -EINVAL) {
  2578. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2579. __func__);
  2580. return ret;
  2581. }
  2582. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2583. /*
  2584. * 200us sleep is required after LDO is enabled as per
  2585. * HW requirement
  2586. */
  2587. usleep_range(200, 250);
  2588. break;
  2589. case SND_SOC_DAPM_POST_PMD:
  2590. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2591. break;
  2592. }
  2593. return 0;
  2594. }
  2595. const char * const tx_master_ch_text[] = {
  2596. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2597. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2598. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2599. "SWRM_PCM_IN",
  2600. };
  2601. const struct soc_enum tx_master_ch_enum =
  2602. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2603. tx_master_ch_text);
  2604. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2605. {
  2606. u8 ch_type = 0;
  2607. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2608. ch_type = ADC1;
  2609. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2610. ch_type = ADC2;
  2611. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2612. ch_type = ADC3;
  2613. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2614. ch_type = ADC4;
  2615. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2616. ch_type = DMIC0;
  2617. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2618. ch_type = DMIC1;
  2619. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2620. ch_type = MBHC;
  2621. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2622. ch_type = DMIC2;
  2623. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2624. ch_type = DMIC3;
  2625. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2626. ch_type = DMIC4;
  2627. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2628. ch_type = DMIC5;
  2629. else
  2630. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2631. if (ch_type)
  2632. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2633. else
  2634. *ch_idx = -EINVAL;
  2635. }
  2636. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2637. struct snd_ctl_elem_value *ucontrol)
  2638. {
  2639. struct snd_soc_component *component =
  2640. snd_soc_kcontrol_component(kcontrol);
  2641. struct wcd9378_priv *wcd9378 = NULL;
  2642. int slave_ch_idx = -EINVAL;
  2643. if (component == NULL)
  2644. return -EINVAL;
  2645. wcd9378 = snd_soc_component_get_drvdata(component);
  2646. if (wcd9378 == NULL)
  2647. return -EINVAL;
  2648. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2649. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2650. return -EINVAL;
  2651. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2652. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2653. return 0;
  2654. }
  2655. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2656. struct snd_ctl_elem_value *ucontrol)
  2657. {
  2658. struct snd_soc_component *component =
  2659. snd_soc_kcontrol_component(kcontrol);
  2660. struct wcd9378_priv *wcd9378 = NULL;
  2661. int slave_ch_idx = -EINVAL, idx = 0;
  2662. if (component == NULL)
  2663. return -EINVAL;
  2664. wcd9378 = snd_soc_component_get_drvdata(component);
  2665. if (wcd9378 == NULL)
  2666. return -EINVAL;
  2667. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2668. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2669. return -EINVAL;
  2670. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2671. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2672. __func__, ucontrol->value.enumerated.item[0]);
  2673. idx = ucontrol->value.enumerated.item[0];
  2674. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2675. return -EINVAL;
  2676. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2677. return 0;
  2678. }
  2679. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2680. struct snd_ctl_elem_value *ucontrol)
  2681. {
  2682. struct snd_soc_component *component =
  2683. snd_soc_kcontrol_component(kcontrol);
  2684. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2685. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2686. return 0;
  2687. }
  2688. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2689. struct snd_ctl_elem_value *ucontrol)
  2690. {
  2691. struct snd_soc_component *component =
  2692. snd_soc_kcontrol_component(kcontrol);
  2693. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2694. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2695. return 0;
  2696. }
  2697. static const char * const sys_usage_text[] = {
  2698. "NOSJ_SA_STEREO_3SM", "SJ_SA_AUX_2SM", "NOSJ_SA_STEREO_3SM_1HDR",
  2699. "SJ_SA_AUX_2SM_1HDR", "NOSJ_SA_EAR_3SM", "SJ_SA_EAR_2SM", "NOSJ_SA_EAR_3SM_1HDR",
  2700. "SJ_SA_EAR_2SM_1HDR", "SJ_1HDR_SA_AUX_1SM", "SJ_1HDR_SA_EAR_1SM",
  2701. "SJ_SA_STEREO_2SM", "SJ_NOMIC_SA_EAR_3SM", "SJ_NOMIC_SA_AUX_3SM",
  2702. };
  2703. static const struct soc_enum sys_usage_enum =
  2704. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sys_usage_text),
  2705. sys_usage_text);
  2706. static const char * const loopback_mode_text[] = {
  2707. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2708. };
  2709. static const struct soc_enum loopback_mode_enum =
  2710. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2711. loopback_mode_text);
  2712. static const char * const aux_dsm_text[] = {
  2713. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2714. };
  2715. static const struct soc_enum aux_dsm_enum =
  2716. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2717. aux_dsm_text);
  2718. static const char * const hph_dsm_text[] = {
  2719. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2720. };
  2721. static const struct soc_enum hph_dsm_enum =
  2722. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2723. hph_dsm_text);
  2724. static const char * const tx_mode_mux_text[] = {
  2725. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2726. };
  2727. static const struct soc_enum tx_mode_mux_enum =
  2728. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2729. tx_mode_mux_text);
  2730. static const char * const micb_sel_text[] = {
  2731. "NO_MICB", "MICB1", "MICB2", "MICB3",
  2732. };
  2733. static const struct soc_enum sm_micb_enum =
  2734. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micb_sel_text),
  2735. micb_sel_text);
  2736. static const char * const rx2_mode_text[] = {
  2737. "HP", "NORMAL",
  2738. };
  2739. static const struct soc_enum rx2_mode_enum =
  2740. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2741. rx2_mode_text);
  2742. static const char * const rx_hph_mode_mux_text[] = {
  2743. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2744. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2745. };
  2746. static const struct soc_enum rx_hph_mode_mux_enum =
  2747. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2748. rx_hph_mode_mux_text);
  2749. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2750. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2751. wcd9378_get_compander, wcd9378_set_compander),
  2752. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2753. wcd9378_get_compander, wcd9378_set_compander),
  2754. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2755. wcd9378_bcs_get, wcd9378_bcs_put),
  2756. SOC_SINGLE_EXT("VA_AMIC_MIXER Switch", SND_SOC_NOPM, 0, 1, 0,
  2757. wcd9378_get_va_amic_switch, wcd9378_set_va_amic_switch),
  2758. SOC_ENUM_EXT("SYS_USAGE Mode", sys_usage_enum,
  2759. wcd9378_sys_usage_get, wcd9378_sys_usage_put),
  2760. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2761. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2762. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2763. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2764. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2765. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2766. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2767. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2768. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2769. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2770. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2771. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2772. SOC_ENUM_EXT("SM0 MICB SEL", sm_micb_enum,
  2773. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2774. SOC_ENUM_EXT("SM1 MICB SEL", sm_micb_enum,
  2775. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2776. SOC_ENUM_EXT("SM2 MICB SEL", sm_micb_enum,
  2777. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2778. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2779. NULL, wcd9378_rx2_mode_put),
  2780. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2781. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2782. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2783. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2784. WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
  2785. 2, 0x10, 0, ear_pa_gain),
  2786. WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
  2787. 0, 0x8, 0, aux_pa_gain),
  2788. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2789. analog_gain),
  2790. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2791. analog_gain),
  2792. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2793. analog_gain),
  2794. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2795. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2796. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2797. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2798. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2799. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2800. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2801. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2802. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2803. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2804. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2805. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2806. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2807. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2808. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2809. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2810. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2811. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2812. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2813. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2814. };
  2815. static const struct snd_kcontrol_new dmic1_switch[] = {
  2816. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2817. };
  2818. static const struct snd_kcontrol_new dmic2_switch[] = {
  2819. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2820. };
  2821. static const struct snd_kcontrol_new dmic3_switch[] = {
  2822. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2823. };
  2824. static const struct snd_kcontrol_new dmic4_switch[] = {
  2825. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2826. };
  2827. static const struct snd_kcontrol_new dmic5_switch[] = {
  2828. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2829. };
  2830. static const struct snd_kcontrol_new dmic6_switch[] = {
  2831. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2832. };
  2833. static const char * const adc1_mux_text[] = {
  2834. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2835. };
  2836. static const char * const adc2_mux_text[] = {
  2837. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2838. };
  2839. static const char * const adc3_mux_text[] = {
  2840. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC2", "CH3_AMIC3", "CH3_AMIC4"
  2841. };
  2842. static const char * const ear_mux_text[] = {
  2843. "RX2", "RX0"
  2844. };
  2845. static const char * const aux_mux_text[] = {
  2846. "RX2", "RX1"
  2847. };
  2848. static const struct soc_enum adc1_enum =
  2849. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2850. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2851. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2852. static const struct soc_enum adc2_enum =
  2853. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2854. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2855. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2856. static const struct soc_enum adc3_enum =
  2857. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2858. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2859. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2860. static const struct soc_enum ear_enum =
  2861. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2862. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT,
  2863. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2864. static const struct soc_enum aux_enum =
  2865. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2866. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT,
  2867. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2868. static const struct snd_kcontrol_new tx_adc1_mux =
  2869. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2870. static const struct snd_kcontrol_new tx_adc2_mux =
  2871. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2872. static const struct snd_kcontrol_new tx_adc3_mux =
  2873. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2874. static const struct snd_kcontrol_new ear_mux =
  2875. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2876. static const struct snd_kcontrol_new aux_mux =
  2877. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2878. static const struct snd_kcontrol_new dac1_switch[] = {
  2879. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2880. };
  2881. static const struct snd_kcontrol_new dac2_switch[] = {
  2882. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2883. };
  2884. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2885. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2886. };
  2887. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2888. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2889. };
  2890. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2891. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2892. };
  2893. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2894. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2895. };
  2896. static const struct snd_kcontrol_new rx0_switch[] = {
  2897. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2898. };
  2899. static const struct snd_kcontrol_new rx1_switch[] = {
  2900. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2901. };
  2902. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2903. /*input widgets*/
  2904. SND_SOC_DAPM_INPUT("AMIC1"),
  2905. SND_SOC_DAPM_INPUT("AMIC2"),
  2906. SND_SOC_DAPM_INPUT("AMIC3"),
  2907. SND_SOC_DAPM_INPUT("AMIC4"),
  2908. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2909. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2910. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2911. /*tx widgets*/
  2912. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  2913. NULL, 0, wcd9378_tx_sequencer_enable,
  2914. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2915. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  2916. NULL, 0, wcd9378_tx_sequencer_enable,
  2917. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2918. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  2919. NULL, 0, wcd9378_tx_sequencer_enable,
  2920. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2921. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  2922. &tx_adc1_mux),
  2923. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2924. &tx_adc2_mux),
  2925. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2926. &tx_adc3_mux),
  2927. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2928. wcd9378_codec_enable_dmic,
  2929. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2930. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2931. wcd9378_codec_enable_dmic,
  2932. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2933. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2934. wcd9378_codec_enable_dmic,
  2935. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2936. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2937. wcd9378_codec_enable_dmic,
  2938. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2939. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2940. wcd9378_codec_enable_dmic,
  2941. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2942. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2943. wcd9378_codec_enable_dmic,
  2944. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2945. /*rx widgets*/
  2946. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2947. wcd9378_codec_hphl_dac_event,
  2948. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2949. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2950. wcd9378_codec_hphr_dac_event,
  2951. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2952. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  2953. wcd9378_hph_sequencer_enable,
  2954. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2955. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2956. wcd9378_codec_enable_hphl_pa,
  2957. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2958. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2959. wcd9378_codec_enable_hphr_pa,
  2960. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2961. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  2962. NULL, 0, wcd9378_sa_sequencer_enable,
  2963. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2964. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2965. wcd9378_codec_ear_dac_event,
  2966. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2967. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2968. wcd9378_codec_aux_dac_event,
  2969. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2970. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2971. wcd9378_codec_enable_ear_pa,
  2972. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2973. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2974. wcd9378_codec_enable_aux_pa,
  2975. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2976. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2977. wcd9378_codec_enable_vdd_buck,
  2978. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2979. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2980. wcd9378_enable_clsh,
  2981. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2982. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2983. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2984. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2985. SND_SOC_DAPM_POST_PMD),
  2986. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2987. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2988. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2989. SND_SOC_DAPM_POST_PMD),
  2990. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2991. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2992. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2993. SND_SOC_DAPM_POST_PMD),
  2994. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2995. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2996. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2997. SND_SOC_DAPM_POST_PMD),
  2998. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2999. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3000. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3001. SND_SOC_DAPM_POST_PMD),
  3002. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3003. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3004. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3005. SND_SOC_DAPM_POST_PMD),
  3006. /* micbias widgets*/
  3007. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3008. wcd9378_codec_enable_micbias,
  3009. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3010. SND_SOC_DAPM_POST_PMD),
  3011. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3012. wcd9378_codec_enable_micbias,
  3013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3014. SND_SOC_DAPM_POST_PMD),
  3015. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3016. wcd9378_codec_enable_micbias,
  3017. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3018. SND_SOC_DAPM_POST_PMD),
  3019. /* micbias pull up widgets*/
  3020. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3021. wcd9378_codec_enable_micbias_pullup,
  3022. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3023. SND_SOC_DAPM_POST_PMD),
  3024. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3025. wcd9378_codec_enable_micbias_pullup,
  3026. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3027. SND_SOC_DAPM_POST_PMD),
  3028. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3029. wcd9378_codec_enable_micbias_pullup,
  3030. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3031. SND_SOC_DAPM_POST_PMD),
  3032. /* rx mixer widgets*/
  3033. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3034. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3035. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3036. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3037. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3038. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3039. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3040. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3041. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3042. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3043. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3044. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3045. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3046. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3047. /*output widgets tx*/
  3048. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3049. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3050. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3051. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3052. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3053. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3054. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3055. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3056. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3057. /*output widgets rx*/
  3058. SND_SOC_DAPM_OUTPUT("EAR"),
  3059. SND_SOC_DAPM_OUTPUT("AUX"),
  3060. SND_SOC_DAPM_OUTPUT("HPHL"),
  3061. SND_SOC_DAPM_OUTPUT("HPHR"),
  3062. };
  3063. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3064. /*ADC-1 (channel-1)*/
  3065. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3066. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3067. {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
  3068. {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
  3069. {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
  3070. {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
  3071. /*ADC-2 (channel-2)*/
  3072. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3073. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3074. {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
  3075. {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
  3076. {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
  3077. {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
  3078. /*ADC-3 (channel-3)*/
  3079. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3080. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3081. {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
  3082. {"ADC3 MUX", "CH3_AMIC2", "AMIC2"},
  3083. {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
  3084. {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
  3085. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3086. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3087. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3088. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3089. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3090. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3091. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3092. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3093. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3094. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3095. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3096. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3097. /*Headphone playback*/
  3098. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3099. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3100. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3101. {"RDAC1", NULL, "HPH SEQUENCER"},
  3102. {"HPHL_RDAC", "Switch", "RDAC1"},
  3103. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3104. {"HPHL", NULL, "HPHL PGA"},
  3105. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3106. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3107. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3108. {"RDAC2", NULL, "HPH SEQUENCER"},
  3109. {"HPHR_RDAC", "Switch", "RDAC2"},
  3110. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3111. {"HPHR", NULL, "HPHR PGA"},
  3112. /*Amplier playback*/
  3113. {"IN3_AUX", NULL, "VDD_BUCK"},
  3114. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3115. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3116. {"EAR_MUX", "RX2", "IN3_AUX"},
  3117. {"DAC1", "Switch", "EAR_MUX"},
  3118. {"EAR_RDAC", NULL, "DAC1"},
  3119. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3120. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3121. {"EAR PGA", NULL, "EAR_MIXER"},
  3122. {"EAR", NULL, "EAR PGA"},
  3123. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3124. {"AUX_MUX", "RX2", "IN3_AUX"},
  3125. {"DAC2", "Switch", "AUX_MUX"},
  3126. {"AUX_RDAC", NULL, "DAC2"},
  3127. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3128. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3129. {"AUX PGA", NULL, "AUX_MIXER"},
  3130. {"AUX", NULL, "AUX PGA"},
  3131. };
  3132. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3133. void *file_private_data,
  3134. struct file *file,
  3135. char __user *buf, size_t count,
  3136. loff_t pos)
  3137. {
  3138. struct wcd9378_priv *priv;
  3139. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3140. int len = 0;
  3141. priv = (struct wcd9378_priv *) entry->private_data;
  3142. if (!priv) {
  3143. pr_err("%s: wcd9378 priv is null\n", __func__);
  3144. return -EINVAL;
  3145. }
  3146. switch (priv->version) {
  3147. case WCD9378_VERSION_1_0:
  3148. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3149. break;
  3150. default:
  3151. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3152. }
  3153. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3154. }
  3155. static struct snd_info_entry_ops wcd9378_info_ops = {
  3156. .read = wcd9378_version_read,
  3157. };
  3158. /*
  3159. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3160. * @codec_root: The parent directory
  3161. * @component: component instance
  3162. *
  3163. * Creates wcd9378 module, version entry under the given
  3164. * parent directory.
  3165. *
  3166. * Return: 0 on success or negative error code on failure.
  3167. */
  3168. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3169. struct snd_soc_component *component)
  3170. {
  3171. struct snd_info_entry *version_entry;
  3172. struct wcd9378_priv *priv;
  3173. struct snd_soc_card *card;
  3174. if (!codec_root || !component)
  3175. return -EINVAL;
  3176. priv = snd_soc_component_get_drvdata(component);
  3177. if (priv->entry) {
  3178. dev_dbg(priv->dev,
  3179. "%s:wcd9378 module already created\n", __func__);
  3180. return 0;
  3181. }
  3182. card = component->card;
  3183. priv->entry = snd_info_create_module_entry(codec_root->module,
  3184. "wcd9378", codec_root);
  3185. if (!priv->entry) {
  3186. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3187. __func__);
  3188. return -ENOMEM;
  3189. }
  3190. priv->entry->mode = S_IFDIR | 0555;
  3191. if (snd_info_register(priv->entry) < 0) {
  3192. snd_info_free_entry(priv->entry);
  3193. return -ENOMEM;
  3194. }
  3195. version_entry = snd_info_create_card_entry(card->snd_card,
  3196. "version",
  3197. priv->entry);
  3198. if (!version_entry) {
  3199. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3200. __func__);
  3201. snd_info_free_entry(priv->entry);
  3202. return -ENOMEM;
  3203. }
  3204. version_entry->private_data = priv;
  3205. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3206. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3207. version_entry->c.ops = &wcd9378_info_ops;
  3208. if (snd_info_register(version_entry) < 0) {
  3209. snd_info_free_entry(version_entry);
  3210. snd_info_free_entry(priv->entry);
  3211. return -ENOMEM;
  3212. }
  3213. priv->version_entry = version_entry;
  3214. return 0;
  3215. }
  3216. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3217. static void wcd9378_class_load(struct snd_soc_component *component)
  3218. {
  3219. /*SMP AMP CLASS LOADING*/
  3220. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3221. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3222. usleep_range(20000, 20010);
  3223. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3224. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3225. /*SMP JACK CLASS LOADING*/
  3226. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3227. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3228. usleep_range(30000, 30010);
  3229. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3230. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3231. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3232. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3233. /*SMP MIC0 CLASS LOADING*/
  3234. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3235. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3236. usleep_range(5000, 5010);
  3237. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3238. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3239. /*SMP MIC1 CLASS LOADING*/
  3240. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3241. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3242. usleep_range(5000, 5010);
  3243. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3244. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3245. /*SMP MIC2 CLASS LOADING*/
  3246. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3247. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3248. usleep_range(5000, 5010);
  3249. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3250. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3251. }
  3252. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3253. {
  3254. struct wcd9378_priv *wcd9378 =
  3255. snd_soc_component_get_drvdata(component);
  3256. struct wcd9378_pdata *pdata =
  3257. dev_get_platdata(wcd9378->dev);
  3258. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3259. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3260. mb->micb1_mv, MIC_BIAS_1);
  3261. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3262. mb->micb2_mv, MIC_BIAS_2);
  3263. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3264. mb->micb3_mv, MIC_BIAS_3);
  3265. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3266. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3267. }
  3268. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3269. {
  3270. struct wcd9378_priv *wcd9378 =
  3271. snd_soc_component_get_drvdata(component);
  3272. if (snd_soc_component_read(component,
  3273. WCD9378_EFUSE_REG_29)
  3274. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3275. if (((snd_soc_component_read(component,
  3276. WCD9378_EFUSE_REG_29) &
  3277. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3278. return true;
  3279. else
  3280. return false;
  3281. } else {
  3282. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3283. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3284. return true;
  3285. else
  3286. return false;
  3287. }
  3288. return 0;
  3289. }
  3290. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3291. {
  3292. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3293. struct snd_soc_dapm_context *dapm =
  3294. snd_soc_component_get_dapm(component);
  3295. int ret = -EINVAL;
  3296. wcd9378 = snd_soc_component_get_drvdata(component);
  3297. if (!wcd9378)
  3298. return -EINVAL;
  3299. wcd9378->component = component;
  3300. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3301. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3302. ret = wcd9378_wcd_mode_check(component);
  3303. if (!ret) {
  3304. dev_err(component->dev, "wcd mode check failed\n");
  3305. ret = -EINVAL;
  3306. goto exit;
  3307. }
  3308. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3309. if (ret) {
  3310. pr_err("%s: mbhc initialization failed\n", __func__);
  3311. ret = -EINVAL;
  3312. goto exit;
  3313. }
  3314. dev_dbg(component->dev, "%s: mbhc init done\n", __func__);
  3315. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3316. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3317. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3318. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3319. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3320. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3321. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3322. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3323. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3324. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3325. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3326. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3327. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3328. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3329. snd_soc_dapm_sync(dapm);
  3330. wcd_cls_h_init(&wcd9378->clsh_info);
  3331. wcd9378_init_reg(component);
  3332. wcd9378_micb_value_convert(component);
  3333. wcd9378->version = WCD9378_VERSION_1_0;
  3334. /* Register event notifier */
  3335. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3336. if (wcd9378->register_notifier) {
  3337. ret = wcd9378->register_notifier(wcd9378->handle,
  3338. &wcd9378->nblock,
  3339. true);
  3340. if (ret) {
  3341. dev_err(component->dev,
  3342. "%s: Failed to register notifier %d\n",
  3343. __func__, ret);
  3344. return ret;
  3345. }
  3346. }
  3347. exit:
  3348. return ret;
  3349. }
  3350. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3351. {
  3352. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3353. if (!wcd9378) {
  3354. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3355. __func__);
  3356. return;
  3357. }
  3358. if (wcd9378->register_notifier)
  3359. wcd9378->register_notifier(wcd9378->handle,
  3360. &wcd9378->nblock,
  3361. false);
  3362. }
  3363. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3364. {
  3365. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3366. if (!wcd9378)
  3367. return 0;
  3368. wcd9378->dapm_bias_off = true;
  3369. return 0;
  3370. }
  3371. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3372. {
  3373. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3374. if (!wcd9378)
  3375. return 0;
  3376. wcd9378->dapm_bias_off = false;
  3377. return 0;
  3378. }
  3379. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3380. .name = WCD9378_DRV_NAME,
  3381. .probe = wcd9378_soc_codec_probe,
  3382. .remove = wcd9378_soc_codec_remove,
  3383. .controls = wcd9378_snd_controls,
  3384. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3385. .dapm_widgets = wcd9378_dapm_widgets,
  3386. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3387. .dapm_routes = wcd9378_audio_map,
  3388. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3389. .suspend = wcd9378_soc_codec_suspend,
  3390. .resume = wcd9378_soc_codec_resume,
  3391. };
  3392. static int wcd9378_reset(struct device *dev)
  3393. {
  3394. struct wcd9378_priv *wcd9378 = NULL;
  3395. int rc = 0;
  3396. int value = 0;
  3397. if (!dev)
  3398. return -ENODEV;
  3399. wcd9378 = dev_get_drvdata(dev);
  3400. if (!wcd9378)
  3401. return -EINVAL;
  3402. if (!wcd9378->rst_np) {
  3403. dev_err(dev, "%s: reset gpio device node not specified\n",
  3404. __func__);
  3405. return -EINVAL;
  3406. }
  3407. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3408. if (value > 0)
  3409. return 0;
  3410. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3411. if (rc) {
  3412. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3413. __func__);
  3414. return -EPROBE_DEFER;
  3415. }
  3416. /* 20us sleep required after pulling the reset gpio to LOW */
  3417. usleep_range(20, 30);
  3418. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3419. if (rc) {
  3420. dev_err(dev, "%s: wcd active state request fail!\n",
  3421. __func__);
  3422. return -EPROBE_DEFER;
  3423. }
  3424. /* 20us sleep required after pulling the reset gpio to HIGH */
  3425. usleep_range(20, 30);
  3426. return rc;
  3427. }
  3428. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3429. u32 *val)
  3430. {
  3431. int rc = 0;
  3432. rc = of_property_read_u32(dev->of_node, name, val);
  3433. if (rc)
  3434. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3435. __func__, name, dev->of_node->full_name);
  3436. return rc;
  3437. }
  3438. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3439. struct wcd9378_micbias_setting *mb)
  3440. {
  3441. u32 prop_val = 0;
  3442. int rc = 0;
  3443. /* MB1 */
  3444. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3445. NULL)) {
  3446. rc = wcd9378_read_of_property_u32(dev,
  3447. "qcom,cdc-micbias1-mv",
  3448. &prop_val);
  3449. if (!rc)
  3450. mb->micb1_mv = prop_val;
  3451. } else {
  3452. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3453. __func__);
  3454. }
  3455. /* MB2 */
  3456. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3457. NULL)) {
  3458. rc = wcd9378_read_of_property_u32(dev,
  3459. "qcom,cdc-micbias2-mv",
  3460. &prop_val);
  3461. if (!rc)
  3462. mb->micb2_mv = prop_val;
  3463. } else {
  3464. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3465. __func__);
  3466. }
  3467. /* MB3 */
  3468. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3469. NULL)) {
  3470. rc = wcd9378_read_of_property_u32(dev,
  3471. "qcom,cdc-micbias3-mv",
  3472. &prop_val);
  3473. if (!rc)
  3474. mb->micb3_mv = prop_val;
  3475. } else {
  3476. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3477. __func__);
  3478. }
  3479. }
  3480. static int wcd9378_reset_low(struct device *dev)
  3481. {
  3482. struct wcd9378_priv *wcd9378 = NULL;
  3483. int rc = 0;
  3484. if (!dev)
  3485. return -ENODEV;
  3486. wcd9378 = dev_get_drvdata(dev);
  3487. if (!wcd9378)
  3488. return -EINVAL;
  3489. if (!wcd9378->rst_np) {
  3490. dev_err(dev, "%s: reset gpio device node not specified\n",
  3491. __func__);
  3492. return -EINVAL;
  3493. }
  3494. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3495. if (rc) {
  3496. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3497. __func__);
  3498. return rc;
  3499. }
  3500. /* 20us sleep required after pulling the reset gpio to LOW */
  3501. usleep_range(20, 30);
  3502. return rc;
  3503. }
  3504. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3505. {
  3506. struct wcd9378_pdata *pdata = NULL;
  3507. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3508. GFP_KERNEL);
  3509. if (!pdata)
  3510. return NULL;
  3511. pdata->rst_np = of_parse_phandle(dev->of_node,
  3512. "qcom,wcd-rst-gpio-node", 0);
  3513. if (!pdata->rst_np) {
  3514. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3515. __func__, "qcom,wcd-rst-gpio-node",
  3516. dev->of_node->full_name);
  3517. return NULL;
  3518. }
  3519. /* Parse power supplies */
  3520. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3521. &pdata->num_supplies);
  3522. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3523. dev_err(dev, "%s: no power supplies defined for codec\n",
  3524. __func__);
  3525. return NULL;
  3526. }
  3527. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3528. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3529. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3530. return pdata;
  3531. }
  3532. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3533. {
  3534. .name = "wcd9378_cdc",
  3535. .playback = {
  3536. .stream_name = "WCD9378_AIF Playback",
  3537. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3538. .formats = WCD9378_FORMATS,
  3539. .rate_max = 384000,
  3540. .rate_min = 8000,
  3541. .channels_min = 1,
  3542. .channels_max = 4,
  3543. },
  3544. .capture = {
  3545. .stream_name = "WCD9378_AIF Capture",
  3546. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3547. .formats = WCD9378_FORMATS,
  3548. .rate_max = 384000,
  3549. .rate_min = 8000,
  3550. .channels_min = 1,
  3551. .channels_max = 4,
  3552. },
  3553. },
  3554. };
  3555. static int wcd9378_bind(struct device *dev)
  3556. {
  3557. int ret = 0;
  3558. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3559. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3560. /*
  3561. * Add 5msec delay to provide sufficient time for
  3562. * soundwire auto enumeration of slave devices as
  3563. * per HW requirement.
  3564. */
  3565. usleep_range(5000, 5010);
  3566. ret = component_bind_all(dev, wcd9378);
  3567. if (ret) {
  3568. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3569. __func__, ret);
  3570. return ret;
  3571. }
  3572. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3573. if (!wcd9378->rx_swr_dev) {
  3574. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3575. __func__);
  3576. ret = -ENODEV;
  3577. goto err;
  3578. }
  3579. wcd9378->rx_swr_dev->paging_support = true;
  3580. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3581. if (!wcd9378->tx_swr_dev) {
  3582. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3583. __func__);
  3584. ret = -ENODEV;
  3585. goto err;
  3586. }
  3587. wcd9378->tx_swr_dev->paging_support = true;
  3588. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3589. wcd9378->swr_tx_port_params);
  3590. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3591. &wcd9378_regmap_config);
  3592. if (!wcd9378->regmap) {
  3593. dev_err(dev, "%s: Regmap init failed\n",
  3594. __func__);
  3595. goto err;
  3596. }
  3597. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3598. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3599. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3600. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3601. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3602. wcd9378->irq_info.codec_name = "WCD9378";
  3603. wcd9378->irq_info.regmap = wcd9378->regmap;
  3604. wcd9378->irq_info.dev = dev;
  3605. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3606. if (ret) {
  3607. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3608. __func__, ret);
  3609. goto err;
  3610. }
  3611. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3612. __func__);
  3613. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3614. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3615. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3616. if (ret) {
  3617. dev_err(dev, "%s: Codec registration failed\n",
  3618. __func__);
  3619. goto err_irq;
  3620. }
  3621. wcd9378->dev_up = true;
  3622. return ret;
  3623. err_irq:
  3624. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3625. err:
  3626. component_unbind_all(dev, wcd9378);
  3627. return ret;
  3628. }
  3629. static void wcd9378_unbind(struct device *dev)
  3630. {
  3631. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3632. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3633. snd_soc_unregister_component(dev);
  3634. component_unbind_all(dev, wcd9378);
  3635. }
  3636. static const struct of_device_id wcd9378_dt_match[] = {
  3637. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3638. {}
  3639. };
  3640. static const struct component_master_ops wcd9378_comp_ops = {
  3641. .bind = wcd9378_bind,
  3642. .unbind = wcd9378_unbind,
  3643. };
  3644. static int wcd9378_compare_of(struct device *dev, void *data)
  3645. {
  3646. return dev->of_node == data;
  3647. }
  3648. static void wcd9378_release_of(struct device *dev, void *data)
  3649. {
  3650. of_node_put(data);
  3651. }
  3652. static int wcd9378_add_slave_components(struct device *dev,
  3653. struct component_match **matchptr)
  3654. {
  3655. struct device_node *np, *rx_node, *tx_node;
  3656. np = dev->of_node;
  3657. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3658. if (!rx_node) {
  3659. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3660. return -ENODEV;
  3661. }
  3662. of_node_get(rx_node);
  3663. component_match_add_release(dev, matchptr,
  3664. wcd9378_release_of,
  3665. wcd9378_compare_of,
  3666. rx_node);
  3667. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3668. if (!tx_node) {
  3669. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3670. return -ENODEV;
  3671. }
  3672. of_node_get(tx_node);
  3673. component_match_add_release(dev, matchptr,
  3674. wcd9378_release_of,
  3675. wcd9378_compare_of,
  3676. tx_node);
  3677. return 0;
  3678. }
  3679. static int wcd9378_probe(struct platform_device *pdev)
  3680. {
  3681. struct component_match *match = NULL;
  3682. struct wcd9378_priv *wcd9378 = NULL;
  3683. struct wcd9378_pdata *pdata = NULL;
  3684. struct wcd_ctrl_platform_data *plat_data = NULL;
  3685. struct device *dev = &pdev->dev;
  3686. int ret;
  3687. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3688. GFP_KERNEL);
  3689. if (!wcd9378)
  3690. return -ENOMEM;
  3691. dev_set_drvdata(dev, wcd9378);
  3692. wcd9378->dev = dev;
  3693. pdata = wcd9378_populate_dt_data(dev);
  3694. if (!pdata) {
  3695. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3696. return -EINVAL;
  3697. }
  3698. dev->platform_data = pdata;
  3699. wcd9378->rst_np = pdata->rst_np;
  3700. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3701. pdata->regulator, pdata->num_supplies);
  3702. if (!wcd9378->supplies) {
  3703. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3704. __func__);
  3705. return ret;
  3706. }
  3707. plat_data = dev_get_platdata(dev->parent);
  3708. if (!plat_data) {
  3709. dev_err(dev, "%s: platform data from parent is NULL\n",
  3710. __func__);
  3711. return -EINVAL;
  3712. }
  3713. wcd9378->handle = (void *)plat_data->handle;
  3714. if (!wcd9378->handle) {
  3715. dev_err(dev, "%s: handle is NULL\n", __func__);
  3716. return -EINVAL;
  3717. }
  3718. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3719. if (!wcd9378->update_wcd_event) {
  3720. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3721. __func__);
  3722. return -EINVAL;
  3723. }
  3724. wcd9378->register_notifier = plat_data->register_notifier;
  3725. if (!wcd9378->register_notifier) {
  3726. dev_err(dev, "%s: register_notifier api is null!\n",
  3727. __func__);
  3728. return -EINVAL;
  3729. }
  3730. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3731. &wcd9378->wcd_mode);
  3732. if (ret) {
  3733. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3734. __func__);
  3735. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3736. }
  3737. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3738. pdata->regulator,
  3739. pdata->num_supplies);
  3740. if (ret) {
  3741. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3742. __func__);
  3743. return ret;
  3744. }
  3745. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3746. CODEC_RX);
  3747. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3748. CODEC_TX);
  3749. if (ret) {
  3750. dev_err(dev, "Failed to read port mapping\n");
  3751. goto err;
  3752. }
  3753. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3754. CODEC_TX);
  3755. if (ret) {
  3756. dev_err(dev, "Failed to read port params\n");
  3757. goto err;
  3758. }
  3759. mutex_init(&wcd9378->wakeup_lock);
  3760. mutex_init(&wcd9378->micb_lock);
  3761. ret = wcd9378_add_slave_components(dev, &match);
  3762. if (ret)
  3763. goto err_lock_init;
  3764. ret = wcd9378_reset(dev);
  3765. if (ret == -EPROBE_DEFER) {
  3766. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3767. goto err_lock_init;
  3768. }
  3769. wcd9378->wakeup = wcd9378_wakeup;
  3770. return component_master_add_with_match(dev,
  3771. &wcd9378_comp_ops, match);
  3772. err_lock_init:
  3773. mutex_destroy(&wcd9378->micb_lock);
  3774. mutex_destroy(&wcd9378->wakeup_lock);
  3775. err:
  3776. return ret;
  3777. }
  3778. static int wcd9378_remove(struct platform_device *pdev)
  3779. {
  3780. struct wcd9378_priv *wcd9378 = NULL;
  3781. wcd9378 = platform_get_drvdata(pdev);
  3782. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3783. mutex_destroy(&wcd9378->micb_lock);
  3784. mutex_destroy(&wcd9378->wakeup_lock);
  3785. dev_set_drvdata(&pdev->dev, NULL);
  3786. return 0;
  3787. }
  3788. #ifdef CONFIG_PM_SLEEP
  3789. static int wcd9378_suspend(struct device *dev)
  3790. {
  3791. struct wcd9378_priv *wcd9378 = NULL;
  3792. int ret = 0;
  3793. struct wcd9378_pdata *pdata = NULL;
  3794. if (!dev)
  3795. return -ENODEV;
  3796. wcd9378 = dev_get_drvdata(dev);
  3797. if (!wcd9378)
  3798. return -EINVAL;
  3799. pdata = dev_get_platdata(wcd9378->dev);
  3800. if (!pdata) {
  3801. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3802. return -EINVAL;
  3803. }
  3804. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3805. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3806. wcd9378->supplies,
  3807. pdata->regulator,
  3808. pdata->num_supplies,
  3809. "cdc-vdd-buck");
  3810. if (ret == -EINVAL) {
  3811. dev_err(dev, "%s: vdd buck is not disabled\n",
  3812. __func__);
  3813. return 0;
  3814. }
  3815. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3816. }
  3817. if (wcd9378->dapm_bias_off) {
  3818. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3819. wcd9378->supplies,
  3820. pdata->regulator,
  3821. pdata->num_supplies,
  3822. true);
  3823. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3824. }
  3825. return 0;
  3826. }
  3827. static int wcd9378_resume(struct device *dev)
  3828. {
  3829. struct wcd9378_priv *wcd9378 = NULL;
  3830. struct wcd9378_pdata *pdata = NULL;
  3831. if (!dev)
  3832. return -ENODEV;
  3833. wcd9378 = dev_get_drvdata(dev);
  3834. if (!wcd9378)
  3835. return -EINVAL;
  3836. pdata = dev_get_platdata(wcd9378->dev);
  3837. if (!pdata) {
  3838. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3839. return -EINVAL;
  3840. }
  3841. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3842. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3843. wcd9378->supplies,
  3844. pdata->regulator,
  3845. pdata->num_supplies,
  3846. false);
  3847. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3848. }
  3849. return 0;
  3850. }
  3851. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3852. .suspend_late = wcd9378_suspend,
  3853. .resume_early = wcd9378_resume,
  3854. };
  3855. #endif
  3856. static struct platform_driver wcd9378_codec_driver = {
  3857. .probe = wcd9378_probe,
  3858. .remove = wcd9378_remove,
  3859. .driver = {
  3860. .name = "wcd9378_codec",
  3861. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3862. #ifdef CONFIG_PM_SLEEP
  3863. .pm = &wcd9378_dev_pm_ops,
  3864. #endif
  3865. .suppress_bind_attrs = true,
  3866. },
  3867. };
  3868. module_platform_driver(wcd9378_codec_driver);
  3869. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3870. MODULE_LICENSE("GPL");