605b42f92c
Kernel audio drivers can be categorised into below folders. asoc - ALSA based drivers, asoc/codecs - codec drivers, ipc - APR IPC communication drivers, dsp - DSP low level drivers/Audio ION/ADSP Loader, dsp/codecs - Native encoders and decoders, soc - SoC based drivers(pinctrl/regmap/soundwire) Restructure drivers to above folder format. Include directories also follow above format. Change-Id: I8fa0857baaacd47db126fb5c1f1f5ed7e886dbc0 Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
162 خطوط
5.6 KiB
C
162 خطوط
5.6 KiB
C
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/regmap.h>
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#include "msm_sdw.h"
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static const struct reg_default msm_sdw_defaults[] = {
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/* Page #10 registers */
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{ MSM_SDW_PAGE_REGISTER, 0x00 },
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{ MSM_SDW_TX9_SPKR_PROT_PATH_CTL, 0x02 },
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{ MSM_SDW_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
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{ MSM_SDW_TX10_SPKR_PROT_PATH_CTL, 0x02 },
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{ MSM_SDW_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
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{ MSM_SDW_TX11_SPKR_PROT_PATH_CTL, 0x02 },
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{ MSM_SDW_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
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{ MSM_SDW_TX12_SPKR_PROT_PATH_CTL, 0x02 },
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{ MSM_SDW_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
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/* Page #11 registers */
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{ MSM_SDW_COMPANDER7_CTL0, 0x60 },
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{ MSM_SDW_COMPANDER7_CTL1, 0xdb },
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{ MSM_SDW_COMPANDER7_CTL2, 0xff },
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{ MSM_SDW_COMPANDER7_CTL3, 0x35 },
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{ MSM_SDW_COMPANDER7_CTL4, 0xff },
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{ MSM_SDW_COMPANDER7_CTL5, 0x00 },
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{ MSM_SDW_COMPANDER7_CTL6, 0x01 },
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{ MSM_SDW_COMPANDER8_CTL0, 0x60 },
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{ MSM_SDW_COMPANDER8_CTL1, 0xdb },
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{ MSM_SDW_COMPANDER8_CTL2, 0xff },
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{ MSM_SDW_COMPANDER8_CTL3, 0x35 },
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{ MSM_SDW_COMPANDER8_CTL4, 0xff },
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{ MSM_SDW_COMPANDER8_CTL5, 0x00 },
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{ MSM_SDW_COMPANDER8_CTL6, 0x01 },
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{ MSM_SDW_RX7_RX_PATH_CTL, 0x04 },
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{ MSM_SDW_RX7_RX_PATH_CFG0, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_CFG2, 0x8f },
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{ MSM_SDW_RX7_RX_VOL_CTL, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_MIX_CTL, 0x04 },
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{ MSM_SDW_RX7_RX_VOL_MIX_CTL, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_SEC2, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_SEC3, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_SEC5, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_SEC6, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_SEC7, 0x00 },
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{ MSM_SDW_RX7_RX_PATH_MIX_SEC1, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_CTL, 0x04 },
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{ MSM_SDW_RX8_RX_PATH_CFG0, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_CFG2, 0x8f },
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{ MSM_SDW_RX8_RX_VOL_CTL, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_MIX_CTL, 0x04 },
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{ MSM_SDW_RX8_RX_VOL_MIX_CTL, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_SEC2, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_SEC3, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_SEC5, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_SEC6, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_SEC7, 0x00 },
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{ MSM_SDW_RX8_RX_PATH_MIX_SEC1, 0x00 },
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/* Page #12 registers */
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{ MSM_SDW_BOOST0_BOOST_PATH_CTL, 0x00 },
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{ MSM_SDW_BOOST0_BOOST_CTL, 0xb2 },
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{ MSM_SDW_BOOST0_BOOST_CFG1, 0x00 },
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{ MSM_SDW_BOOST0_BOOST_CFG2, 0x00 },
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{ MSM_SDW_BOOST1_BOOST_PATH_CTL, 0x00 },
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{ MSM_SDW_BOOST1_BOOST_CTL, 0xb2 },
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{ MSM_SDW_BOOST1_BOOST_CFG1, 0x00 },
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{ MSM_SDW_BOOST1_BOOST_CFG2, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_DATA_0, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_DATA_1, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_DATA_2, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_DATA_3, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_ADDR_0, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_ADDR_1, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_ADDR_2, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_WR_ADDR_3, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_ADDR_0, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_ADDR_1, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_ADDR_2, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_ADDR_3, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_DATA_0, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_DATA_1, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_DATA_2, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_RD_DATA_3, 0x00 },
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{ MSM_SDW_AHB_BRIDGE_ACCESS_CFG, 0x0f },
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{ MSM_SDW_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
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/* Page #13 registers */
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{ MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
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{ MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
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{ MSM_SDW_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
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{ MSM_SDW_TOP_TOP_CFG0, 0x00 },
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{ MSM_SDW_TOP_TOP_CFG1, 0x00 },
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{ MSM_SDW_TOP_RX_I2S_CTL, 0x0C },
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{ MSM_SDW_TOP_TX_I2S_CTL, 0x00 },
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{ MSM_SDW_TOP_I2S_CLK, 0x00 },
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{ MSM_SDW_TOP_RX7_PATH_INPUT0_MUX, 0x00 },
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{ MSM_SDW_TOP_RX7_PATH_INPUT1_MUX, 0x00 },
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{ MSM_SDW_TOP_RX8_PATH_INPUT0_MUX, 0x00 },
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{ MSM_SDW_TOP_RX8_PATH_INPUT1_MUX, 0x00 },
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{ MSM_SDW_TOP_FREQ_MCLK, 0x00 },
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{ MSM_SDW_TOP_DEBUG_BUS_SEL, 0x00 },
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{ MSM_SDW_TOP_DEBUG_EN, 0x00 },
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{ MSM_SDW_TOP_I2S_RESET, 0x00 },
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{ MSM_SDW_TOP_BLOCKS_RESET, 0x00 },
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};
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static bool msm_sdw_is_readable_register(struct device *dev, unsigned int reg)
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{
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return msm_sdw_reg_readable[reg];
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}
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static bool msm_sdw_is_writeable_register(struct device *dev, unsigned int reg)
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{
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return msm_sdw_reg_writeable[reg];
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}
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static bool msm_sdw_is_volatile_register(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case MSM_SDW_AHB_BRIDGE_WR_DATA_0:
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case MSM_SDW_AHB_BRIDGE_WR_DATA_1:
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case MSM_SDW_AHB_BRIDGE_WR_DATA_2:
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case MSM_SDW_AHB_BRIDGE_WR_DATA_3:
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case MSM_SDW_AHB_BRIDGE_WR_ADDR_0:
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case MSM_SDW_AHB_BRIDGE_WR_ADDR_1:
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case MSM_SDW_AHB_BRIDGE_WR_ADDR_2:
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case MSM_SDW_AHB_BRIDGE_WR_ADDR_3:
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case MSM_SDW_AHB_BRIDGE_RD_DATA_0:
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case MSM_SDW_AHB_BRIDGE_RD_DATA_1:
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case MSM_SDW_AHB_BRIDGE_RD_DATA_2:
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case MSM_SDW_AHB_BRIDGE_RD_DATA_3:
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case MSM_SDW_AHB_BRIDGE_RD_ADDR_0:
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case MSM_SDW_AHB_BRIDGE_RD_ADDR_1:
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case MSM_SDW_AHB_BRIDGE_RD_ADDR_2:
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case MSM_SDW_AHB_BRIDGE_RD_ADDR_3:
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case MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL:
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case MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL:
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return true;
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default:
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return false;
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}
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}
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const struct regmap_config msm_sdw_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.reg_stride = 4,
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.cache_type = REGCACHE_RBTREE,
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.reg_defaults = msm_sdw_defaults,
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.num_reg_defaults = ARRAY_SIZE(msm_sdw_defaults),
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.max_register = MSM_SDW_MAX_REGISTER,
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.writeable_reg = msm_sdw_is_writeable_register,
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.volatile_reg = msm_sdw_is_volatile_register,
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.readable_reg = msm_sdw_is_readable_register,
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};
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