cnss2.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _NET_CNSS2_H
  7. #define _NET_CNSS2_H
  8. #include <linux/pci.h>
  9. #define CNSS_MAX_FILE_NAME 20
  10. #define CNSS_MAX_TIMESTAMP_LEN 32
  11. #define CNSS_WLFW_MAX_BUILD_ID_LEN 128
  12. #define CNSS_MAX_DEV_MEM_NUM 4
  13. #define CNSS_CHIP_VER_ANY 0
  14. #define CNSS_SSR_DRIVER_DUMP_MAX_REGIONS 32
  15. enum cnss_bus_width_type {
  16. CNSS_BUS_WIDTH_NONE,
  17. CNSS_BUS_WIDTH_IDLE,
  18. CNSS_BUS_WIDTH_LOW,
  19. CNSS_BUS_WIDTH_MEDIUM,
  20. CNSS_BUS_WIDTH_HIGH,
  21. CNSS_BUS_WIDTH_VERY_HIGH,
  22. CNSS_BUS_WIDTH_LOW_LATENCY
  23. };
  24. enum cnss_platform_cap_flag {
  25. CNSS_HAS_EXTERNAL_SWREG = 0x01,
  26. CNSS_HAS_UART_ACCESS = 0x02,
  27. CNSS_HAS_DRV_SUPPORT = 0x04,
  28. };
  29. struct cnss_platform_cap {
  30. u32 cap_flag;
  31. };
  32. struct cnss_fw_files {
  33. char image_file[CNSS_MAX_FILE_NAME];
  34. char board_data[CNSS_MAX_FILE_NAME];
  35. char otp_data[CNSS_MAX_FILE_NAME];
  36. char utf_file[CNSS_MAX_FILE_NAME];
  37. char utf_board_data[CNSS_MAX_FILE_NAME];
  38. char epping_file[CNSS_MAX_FILE_NAME];
  39. char evicted_data[CNSS_MAX_FILE_NAME];
  40. };
  41. struct cnss_device_version {
  42. u32 family_number;
  43. u32 device_number;
  44. u32 major_version;
  45. u32 minor_version;
  46. };
  47. struct cnss_dev_mem_info {
  48. u64 start;
  49. u64 size;
  50. };
  51. struct cnss_soc_info {
  52. void __iomem *va;
  53. phys_addr_t pa;
  54. uint32_t chip_id;
  55. uint32_t chip_family;
  56. uint32_t board_id;
  57. uint32_t soc_id;
  58. uint32_t fw_version;
  59. char fw_build_timestamp[CNSS_MAX_TIMESTAMP_LEN + 1];
  60. struct cnss_device_version device_version;
  61. struct cnss_dev_mem_info dev_mem_info[CNSS_MAX_DEV_MEM_NUM];
  62. char fw_build_id[CNSS_WLFW_MAX_BUILD_ID_LEN + 1];
  63. };
  64. struct cnss_wlan_runtime_ops {
  65. int (*runtime_suspend)(struct pci_dev *pdev);
  66. int (*runtime_resume)(struct pci_dev *pdev);
  67. };
  68. enum cnss_driver_status {
  69. CNSS_UNINITIALIZED,
  70. CNSS_INITIALIZED,
  71. CNSS_LOAD_UNLOAD,
  72. CNSS_RECOVERY,
  73. CNSS_FW_DOWN,
  74. CNSS_HANG_EVENT,
  75. CNSS_BUS_EVENT,
  76. CNSS_SYS_REBOOT,
  77. };
  78. enum cnss_host_dump_type {
  79. CNSS_HOST_WLAN_LOGS = 0,
  80. CNSS_HOST_HTC_CREDIT = 1,
  81. CNSS_HOST_WMI_TX_CMP = 2,
  82. CNSS_HOST_WMI_COMMAND_LOG = 3,
  83. CNSS_HOST_WMI_EVENT_LOG = 4,
  84. CNSS_HOST_WMI_RX_EVENT = 5,
  85. CNSS_HOST_HAL_SOC = 6,
  86. CNSS_HOST_GWLAN_LOGGING = 7,
  87. CNSS_HOST_WMI_DEBUG_LOG_INFO = 8,
  88. CNSS_HOST_HTC_CREDIT_IDX = 9,
  89. CNSS_HOST_HTC_CREDIT_LEN = 10,
  90. CNSS_HOST_WMI_TX_CMP_IDX = 11,
  91. CNSS_HOST_WMI_COMMAND_LOG_IDX = 12,
  92. CNSS_HOST_WMI_EVENT_LOG_IDX = 13,
  93. CNSS_HOST_WMI_RX_EVENT_IDX = 14,
  94. CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF = 15,
  95. CNSS_HOST_HANG_EVENT_DATA = 16,
  96. CNSS_HOST_CE_DESC_HIST = 17,
  97. CNSS_HOST_CE_COUNT_MAX = 18,
  98. CNSS_HOST_CE_HISTORY_MAX = 19,
  99. CNSS_HOST_ONLY_FOR_CRIT_CE = 20,
  100. CNSS_HOST_HIF_EVENT_HISTORY = 21,
  101. CNSS_HOST_HIF_EVENT_HIST_MAX = 22,
  102. CNSS_HOST_DP_WBM_DESC_REL = 23,
  103. CNSS_HOST_DP_WBM_DESC_REL_HANDLE = 24,
  104. CNSS_HOST_DP_TCL_CMD = 25,
  105. CNSS_HOST_DP_TCL_CMD_HANDLE = 26,
  106. CNSS_HOST_DP_TCL_STATUS = 27,
  107. CNSS_HOST_DP_TCL_STATUS_HANDLE = 28,
  108. CNSS_HOST_DP_REO_REINJ = 29,
  109. CNSS_HOST_DP_REO_REINJ_HANDLE = 30,
  110. CNSS_HOST_DP_RX_REL = 31,
  111. CNSS_HOST_DP_RX_REL_HANDLE = 32,
  112. CNSS_HOST_DP_REO_EXP = 33,
  113. CNSS_HOST_DP_REO_EXP_HANDLE = 34,
  114. CNSS_HOST_DP_REO_CMD = 35,
  115. CNSS_HOST_DP_REO_CMD_HANDLE = 36,
  116. CNSS_HOST_DP_REO_STATUS = 37,
  117. CNSS_HOST_DP_REO_STATUS_HANDLE = 38,
  118. CNSS_HOST_DP_TCL_DATA_0 = 39,
  119. CNSS_HOST_DP_TCL_DATA_0_HANDLE = 40,
  120. CNSS_HOST_DP_TX_COMP_0 = 41,
  121. CNSS_HOST_DP_TX_COMP_0_HANDLE = 42,
  122. CNSS_HOST_DP_TCL_DATA_1 = 43,
  123. CNSS_HOST_DP_TCL_DATA_1_HANDLE = 44,
  124. CNSS_HOST_DP_TX_COMP_1 = 45,
  125. CNSS_HOST_DP_TX_COMP_1_HANDLE = 46,
  126. CNSS_HOST_DP_TCL_DATA_2 = 47,
  127. CNSS_HOST_DP_TCL_DATA_2_HANDLE = 48,
  128. CNSS_HOST_DP_TX_COMP_2 = 49,
  129. CNSS_HOST_DP_TX_COMP_2_HANDLE = 50,
  130. CNSS_HOST_DP_REO_DST_0 = 51,
  131. CNSS_HOST_DP_REO_DST_0_HANDLE = 52,
  132. CNSS_HOST_DP_REO_DST_1 = 53,
  133. CNSS_HOST_DP_REO_DST_1_HANDLE = 54,
  134. CNSS_HOST_DP_REO_DST_2 = 55,
  135. CNSS_HOST_DP_REO_DST_2_HANDLE = 56,
  136. CNSS_HOST_DP_REO_DST_3 = 57,
  137. CNSS_HOST_DP_REO_DST_3_HANDLE = 58,
  138. CNSS_HOST_DP_REO_DST_4 = 59,
  139. CNSS_HOST_DP_REO_DST_4_HANDLE = 60,
  140. CNSS_HOST_DP_REO_DST_5 = 61,
  141. CNSS_HOST_DP_REO_DST_5_HANDLE = 62,
  142. CNSS_HOST_DP_REO_DST_6 = 63,
  143. CNSS_HOST_DP_REO_DST_6_HANDLE = 64,
  144. CNSS_HOST_DP_REO_DST_7 = 65,
  145. CNSS_HOST_DP_REO_DST_7_HANDLE = 66,
  146. CNSS_HOST_DP_PDEV_0 = 67,
  147. CNSS_HOST_DP_WLAN_CFG_CTX = 68,
  148. CNSS_HOST_DP_SOC = 69,
  149. CNSS_HOST_HAL_RX_FST = 70,
  150. CNSS_HOST_DP_FISA = 71,
  151. CNSS_HOST_DP_FISA_HW_FSE_TABLE = 72,
  152. CNSS_HOST_DP_FISA_SW_FSE_TABLE = 73,
  153. CNSS_HOST_HIF = 74,
  154. CNSS_HOST_QDF_NBUF_HIST = 75,
  155. CNSS_HOST_TCL_WBM_MAP = 76,
  156. CNSS_HOST_RX_MAC_BUF_RING_0 = 77,
  157. CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE = 78,
  158. CNSS_HOST_RX_MAC_BUF_RING_1 = 79,
  159. CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE = 80,
  160. CNSS_HOST_RX_REFILL_0 = 81,
  161. CNSS_HOST_RX_REFILL_0_HANDLE = 82,
  162. CNSS_HOST_CE_0 = 83,
  163. CNSS_HOST_CE_0_SRC_RING = 84,
  164. CNSS_HOST_CE_0_SRC_RING_CTX = 85,
  165. CNSS_HOST_CE_1 = 86,
  166. CNSS_HOST_CE_1_STATUS_RING = 87,
  167. CNSS_HOST_CE_1_STATUS_RING_CTX = 88,
  168. CNSS_HOST_CE_1_DEST_RING = 89,
  169. CNSS_HOST_CE_1_DEST_RING_CTX = 90,
  170. CNSS_HOST_CE_2 = 91,
  171. CNSS_HOST_CE_2_STATUS_RING = 92,
  172. CNSS_HOST_CE_2_STATUS_RING_CTX = 93,
  173. CNSS_HOST_CE_2_DEST_RING = 94,
  174. CNSS_HOST_CE_2_DEST_RING_CTX = 95,
  175. CNSS_HOST_CE_3 = 96,
  176. CNSS_HOST_CE_3_SRC_RING = 97,
  177. CNSS_HOST_CE_3_SRC_RING_CTX = 98,
  178. CNSS_HOST_CE_4 = 99,
  179. CNSS_HOST_CE_4_SRC_RING = 100,
  180. CNSS_HOST_CE_4_SRC_RING_CTX = 101,
  181. CNSS_HOST_CE_5 = 102,
  182. CNSS_HOST_CE_6 = 103,
  183. CNSS_HOST_CE_7 = 104,
  184. CNSS_HOST_CE_7_STATUS_RING = 105,
  185. CNSS_HOST_CE_7_STATUS_RING_CTX = 106,
  186. CNSS_HOST_CE_7_DEST_RING = 107,
  187. CNSS_HOST_CE_7_DEST_RING_CTX = 108,
  188. CNSS_HOST_CE_8 = 109,
  189. CNSS_HOST_DP_TCL_DATA_3 = 110,
  190. CNSS_HOST_DP_TCL_DATA_3_HANDLE = 111,
  191. CNSS_HOST_DP_TX_COMP_3 = 112,
  192. CNSS_HOST_DP_TX_COMP_3_HANDLE = 113,
  193. CNSS_HOST_DUMP_TYPE_MAX = 114,
  194. };
  195. enum cnss_bus_event_type {
  196. BUS_EVENT_PCI_LINK_DOWN = 0,
  197. BUS_EVENT_PCI_LINK_RESUME_FAIL = 1,
  198. BUS_EVENT_INVALID = 0xFFFF,
  199. };
  200. enum cnss_wfc_mode {
  201. CNSS_WFC_MODE_OFF,
  202. CNSS_WFC_MODE_ON,
  203. };
  204. struct cnss_wfc_cfg {
  205. enum cnss_wfc_mode mode;
  206. };
  207. struct cnss_hang_event {
  208. void *hang_event_data;
  209. u16 hang_event_data_len;
  210. };
  211. struct cnss_bus_event {
  212. enum cnss_bus_event_type etype;
  213. void *event_data;
  214. };
  215. struct cnss_uevent_data {
  216. enum cnss_driver_status status;
  217. void *data;
  218. };
  219. struct cnss_ssr_driver_dump_entry {
  220. char region_name[CNSS_SSR_DRIVER_DUMP_MAX_REGIONS];
  221. void *buffer_pointer;
  222. size_t buffer_size;
  223. };
  224. struct cnss_wlan_driver {
  225. char *name;
  226. int (*probe)(struct pci_dev *pdev, const struct pci_device_id *id);
  227. void (*remove)(struct pci_dev *pdev);
  228. int (*idle_restart)(struct pci_dev *pdev,
  229. const struct pci_device_id *id);
  230. int (*idle_shutdown)(struct pci_dev *pdev);
  231. int (*reinit)(struct pci_dev *pdev, const struct pci_device_id *id);
  232. void (*shutdown)(struct pci_dev *pdev);
  233. void (*crash_shutdown)(struct pci_dev *pdev);
  234. int (*suspend)(struct pci_dev *pdev, pm_message_t state);
  235. int (*resume)(struct pci_dev *pdev);
  236. int (*suspend_noirq)(struct pci_dev *pdev);
  237. int (*resume_noirq)(struct pci_dev *pdev);
  238. void (*modem_status)(struct pci_dev *pdev, int state);
  239. void (*update_status)(struct pci_dev *pdev, uint32_t status);
  240. int (*update_event)(struct pci_dev *pdev,
  241. struct cnss_uevent_data *uevent);
  242. struct cnss_wlan_runtime_ops *runtime_ops;
  243. const struct pci_device_id *id_table;
  244. u32 chip_version;
  245. enum cnss_driver_mode (*get_driver_mode)(void);
  246. int (*collect_driver_dump)(struct pci_dev *pdev,
  247. struct cnss_ssr_driver_dump_entry *input_array,
  248. size_t *num_entries_loaded);
  249. int (*set_therm_cdev_state)(struct pci_dev *pci_dev,
  250. unsigned long thermal_state,
  251. int tcdev_id);
  252. };
  253. struct cnss_ce_tgt_pipe_cfg {
  254. u32 pipe_num;
  255. u32 pipe_dir;
  256. u32 nentries;
  257. u32 nbytes_max;
  258. u32 flags;
  259. u32 reserved;
  260. };
  261. struct cnss_ce_svc_pipe_cfg {
  262. u32 service_id;
  263. u32 pipe_dir;
  264. u32 pipe_num;
  265. };
  266. struct cnss_shadow_reg_cfg {
  267. u16 ce_id;
  268. u16 reg_offset;
  269. };
  270. struct cnss_shadow_reg_v2_cfg {
  271. u32 addr;
  272. };
  273. struct cnss_rri_over_ddr_cfg {
  274. u32 base_addr_low;
  275. u32 base_addr_high;
  276. };
  277. struct cnss_shadow_reg_v3_cfg {
  278. u32 addr;
  279. };
  280. struct cnss_wlan_enable_cfg {
  281. u32 num_ce_tgt_cfg;
  282. struct cnss_ce_tgt_pipe_cfg *ce_tgt_cfg;
  283. u32 num_ce_svc_pipe_cfg;
  284. struct cnss_ce_svc_pipe_cfg *ce_svc_cfg;
  285. u32 num_shadow_reg_cfg;
  286. struct cnss_shadow_reg_cfg *shadow_reg_cfg;
  287. u32 num_shadow_reg_v2_cfg;
  288. struct cnss_shadow_reg_v2_cfg *shadow_reg_v2_cfg;
  289. bool rri_over_ddr_cfg_valid;
  290. struct cnss_rri_over_ddr_cfg rri_over_ddr_cfg;
  291. u32 num_shadow_reg_v3_cfg;
  292. struct cnss_shadow_reg_v3_cfg *shadow_reg_v3_cfg;
  293. bool send_msi_ce;
  294. };
  295. enum cnss_driver_mode {
  296. CNSS_MISSION,
  297. CNSS_FTM,
  298. CNSS_EPPING,
  299. CNSS_WALTEST,
  300. CNSS_OFF,
  301. CNSS_CCPM,
  302. CNSS_QVIT,
  303. CNSS_CALIBRATION,
  304. };
  305. enum cnss_recovery_reason {
  306. CNSS_REASON_DEFAULT,
  307. CNSS_REASON_LINK_DOWN,
  308. CNSS_REASON_RDDM,
  309. CNSS_REASON_TIMEOUT,
  310. };
  311. enum cnss_fw_caps {
  312. CNSS_FW_CAP_DIRECT_LINK_SUPPORT,
  313. CNSS_FW_CAP_AUX_UC_SUPPORT,
  314. CNSS_FW_CAP_CALDB_SEG_DDR_SUPPORT,
  315. };
  316. enum cnss_remote_mem_type {
  317. CNSS_REMOTE_MEM_TYPE_FW,
  318. CNSS_REMOTE_MEM_TYPE_QDSS,
  319. CNSS_REMOTE_MEM_TYPE_MAX,
  320. };
  321. struct cnss_mem_segment {
  322. size_t size;
  323. void *va;
  324. phys_addr_t pa;
  325. };
  326. extern int cnss_wlan_register_driver(struct cnss_wlan_driver *driver);
  327. extern void cnss_wlan_unregister_driver(struct cnss_wlan_driver *driver);
  328. extern void cnss_device_crashed(struct device *dev);
  329. extern int cnss_pci_prevent_l1(struct device *dev);
  330. extern void cnss_pci_allow_l1(struct device *dev);
  331. extern int cnss_pci_link_down(struct device *dev);
  332. extern int cnss_pci_is_device_down(struct device *dev);
  333. extern void cnss_schedule_recovery(struct device *dev,
  334. enum cnss_recovery_reason reason);
  335. extern int cnss_self_recovery(struct device *dev,
  336. enum cnss_recovery_reason reason);
  337. extern int cnss_force_fw_assert(struct device *dev);
  338. extern int cnss_force_collect_rddm(struct device *dev);
  339. extern int cnss_qmi_send_get(struct device *dev);
  340. extern int cnss_qmi_send_put(struct device *dev);
  341. extern int cnss_qmi_send(struct device *dev, int type, void *cmd,
  342. int cmd_len, void *cb_ctx,
  343. int (*cb)(void *ctx, void *event, int event_len));
  344. extern void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size);
  345. extern int cnss_get_fw_files_for_target(struct device *dev,
  346. struct cnss_fw_files *pfw_files,
  347. u32 target_type, u32 target_version);
  348. extern int cnss_get_platform_cap(struct device *dev,
  349. struct cnss_platform_cap *cap);
  350. extern struct iommu_domain *cnss_smmu_get_domain(struct device *dev);
  351. extern int cnss_smmu_map(struct device *dev,
  352. phys_addr_t paddr, uint32_t *iova_addr, size_t size);
  353. extern int cnss_smmu_unmap(struct device *dev, uint32_t iova_addr, size_t size);
  354. extern int cnss_get_soc_info(struct device *dev, struct cnss_soc_info *info);
  355. extern int cnss_request_bus_bandwidth(struct device *dev, int bandwidth);
  356. extern int cnss_power_up(struct device *dev);
  357. extern int cnss_power_down(struct device *dev);
  358. extern int cnss_idle_restart(struct device *dev);
  359. extern int cnss_idle_shutdown(struct device *dev);
  360. extern void cnss_request_pm_qos(struct device *dev, u32 qos_val);
  361. extern void cnss_remove_pm_qos(struct device *dev);
  362. extern void cnss_lock_pm_sem(struct device *dev);
  363. extern void cnss_release_pm_sem(struct device *dev);
  364. extern void cnss_pci_lock_reg_window(struct device *dev, unsigned long *flags);
  365. extern void cnss_pci_unlock_reg_window(struct device *dev,
  366. unsigned long *flags);
  367. extern int cnss_wlan_pm_control(struct device *dev, bool vote);
  368. extern int cnss_auto_suspend(struct device *dev);
  369. extern int cnss_auto_resume(struct device *dev);
  370. extern int cnss_pci_is_drv_connected(struct device *dev);
  371. extern int cnss_pci_force_wake_request_sync(struct device *dev, int timeout);
  372. extern int cnss_pci_force_wake_request(struct device *dev);
  373. extern int cnss_pci_is_device_awake(struct device *dev);
  374. extern int cnss_pci_force_wake_release(struct device *dev);
  375. extern int cnss_get_user_msi_assignment(struct device *dev, char *user_name,
  376. int *num_vectors,
  377. uint32_t *user_base_data,
  378. uint32_t *base_vector);
  379. extern int cnss_get_msi_irq(struct device *dev, unsigned int vector);
  380. extern bool cnss_is_one_msi(struct device *dev);
  381. extern void cnss_get_msi_address(struct device *dev, uint32_t *msi_addr_low,
  382. uint32_t *msi_addr_high);
  383. extern int cnss_wlan_hw_enable(void);
  384. extern int cnss_wlan_enable(struct device *dev,
  385. struct cnss_wlan_enable_cfg *config,
  386. enum cnss_driver_mode mode,
  387. const char *host_version);
  388. extern int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode);
  389. extern unsigned int cnss_get_boot_timeout(struct device *dev);
  390. extern int cnss_athdiag_read(struct device *dev, uint32_t offset,
  391. uint32_t mem_type, uint32_t data_len,
  392. uint8_t *output);
  393. extern int cnss_athdiag_write(struct device *dev, uint32_t offset,
  394. uint32_t mem_type, uint32_t data_len,
  395. uint8_t *input);
  396. extern int cnss_set_fw_log_mode(struct device *dev, uint8_t fw_log_mode);
  397. extern int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed);
  398. extern int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg);
  399. extern int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  400. struct cnss_mem_segment segment[],
  401. u32 segment_count);
  402. extern bool cnss_get_audio_shared_iommu_group_cap(struct device *dev);
  403. extern int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
  404. dma_addr_t iova, size_t size);
  405. extern void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova,
  406. size_t size);
  407. extern int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova,
  408. size_t *size);
  409. extern int cnss_get_pci_slot(struct device *dev);
  410. extern int cnss_pci_get_reg_dump(struct device *dev, uint8_t *buffer,
  411. uint32_t len);
  412. extern struct kobject *cnss_get_wifi_kobj(struct device *dev);
  413. extern int cnss_send_buffer_to_afcmem(struct device *dev, const uint8_t *afcdb,
  414. uint32_t len, uint8_t slotid);
  415. extern int cnss_reset_afcmem(struct device *dev, uint8_t slotid);
  416. extern bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap);
  417. extern bool cnss_audio_is_direct_link_supported(struct device *dev);
  418. extern int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg);
  419. extern int cnss_thermal_cdev_register(struct device *dev,
  420. unsigned long max_state,
  421. int tcdev_id);
  422. extern void cnss_thermal_cdev_unregister(struct device *dev, int tcdev_id);
  423. extern int cnss_get_curr_therm_cdev_state(struct device *dev,
  424. unsigned long *thermal_state,
  425. int tcdev_id);
  426. extern int cnss_update_time_sync_period(struct device *dev,
  427. uint32_t time_sync_period);
  428. extern int cnss_reset_time_sync_period(struct device *dev);
  429. extern int cnss_register_driver_async_data_cb(struct device *dev, void *cb_ctx,
  430. int (*cb)(void *ctx,
  431. uint16_t type, void *event,
  432. int event_len));
  433. #endif /* _NET_CNSS2_H */