qmi.c 110 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  28. /*
  29. * Download QDSS config file based on build type. Add build type string to
  30. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  31. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  32. */
  33. #ifdef CONFIG_CNSS2_DEBUG
  34. #define QDSS_FILE_BUILD_STR "debug_"
  35. #else
  36. #define QDSS_FILE_BUILD_STR "perf_"
  37. #endif
  38. #define HW_V1_NUMBER "v1"
  39. #define HW_V2_NUMBER "v2"
  40. #define CE_MSI_NAME "CE"
  41. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  42. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  43. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  44. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  45. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  46. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  47. #define DMS_QMI_MAX_MSG_LEN SZ_256
  48. #define MAX_SHADOW_REG_RESERVED 2
  49. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  50. MAX_SHADOW_REG_RESERVED)
  51. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  52. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  53. // these error values are not defined in <linux/soc/qcom/qmi.h> and fw is sending as error response
  54. #define QMI_ERR_HARDWARE_RESTRICTED_V01 0x0053
  55. #define QMI_ERR_ENOMEM_V01 0x0002
  56. enum nm_modem_bit {
  57. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  58. HOST_CSTATE_BIT = BIT(2),
  59. };
  60. #ifdef CONFIG_CNSS2_DEBUG
  61. static bool ignore_qmi_failure;
  62. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  63. void cnss_ignore_qmi_failure(bool ignore)
  64. {
  65. ignore_qmi_failure = ignore;
  66. }
  67. #else
  68. #define CNSS_QMI_ASSERT() do { } while (0)
  69. void cnss_ignore_qmi_failure(bool ignore) { }
  70. #endif
  71. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  72. {
  73. switch (mode) {
  74. case CNSS_MISSION:
  75. return "MISSION";
  76. case CNSS_FTM:
  77. return "FTM";
  78. case CNSS_EPPING:
  79. return "EPPING";
  80. case CNSS_WALTEST:
  81. return "WALTEST";
  82. case CNSS_OFF:
  83. return "OFF";
  84. case CNSS_CCPM:
  85. return "CCPM";
  86. case CNSS_QVIT:
  87. return "QVIT";
  88. case CNSS_CALIBRATION:
  89. return "CALIBRATION";
  90. default:
  91. return "UNKNOWN";
  92. }
  93. }
  94. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  95. struct qmi_elem_info *req_ei,
  96. struct qmi_elem_info *rsp_ei,
  97. int req_id, size_t req_len,
  98. unsigned long timeout)
  99. {
  100. struct qmi_txn txn;
  101. int ret;
  102. char *err_msg;
  103. struct qmi_response_type_v01 *resp = rsp;
  104. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  105. if (ret < 0) {
  106. err_msg = "Qmi fail: fail to init txn,";
  107. goto out;
  108. }
  109. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  110. req_len, req_ei, req);
  111. if (ret < 0) {
  112. qmi_txn_cancel(&txn);
  113. err_msg = "Qmi fail: fail to send req,";
  114. goto out;
  115. }
  116. ret = qmi_txn_wait(&txn, timeout);
  117. if (ret < 0) {
  118. err_msg = "Qmi fail: wait timeout,";
  119. goto out;
  120. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  121. err_msg = "Qmi fail: request rejected,";
  122. cnss_pr_err("Qmi fail: respons with error:%d\n",
  123. resp->error);
  124. ret = -resp->result;
  125. goto out;
  126. }
  127. cnss_pr_dbg("req %x success\n", req_id);
  128. return 0;
  129. out:
  130. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  131. return ret;
  132. }
  133. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  134. {
  135. struct wlfw_ind_register_req_msg_v01 *req;
  136. struct wlfw_ind_register_resp_msg_v01 *resp;
  137. struct qmi_txn txn;
  138. int ret = 0;
  139. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  140. plat_priv->driver_state);
  141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  142. if (!req)
  143. return -ENOMEM;
  144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  145. if (!resp) {
  146. kfree(req);
  147. return -ENOMEM;
  148. }
  149. req->client_id_valid = 1;
  150. req->client_id = WLFW_CLIENT_ID;
  151. req->request_mem_enable_valid = 1;
  152. req->request_mem_enable = 1;
  153. req->fw_mem_ready_enable_valid = 1;
  154. req->fw_mem_ready_enable = 1;
  155. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  156. req->fw_init_done_enable_valid = 1;
  157. req->fw_init_done_enable = 1;
  158. req->pin_connect_result_enable_valid = 1;
  159. req->pin_connect_result_enable = 1;
  160. req->cal_done_enable_valid = 1;
  161. req->cal_done_enable = 1;
  162. req->qdss_trace_req_mem_enable_valid = 1;
  163. req->qdss_trace_req_mem_enable = 1;
  164. req->qdss_trace_save_enable_valid = 1;
  165. req->qdss_trace_save_enable = 1;
  166. req->qdss_trace_free_enable_valid = 1;
  167. req->qdss_trace_free_enable = 1;
  168. req->respond_get_info_enable_valid = 1;
  169. req->respond_get_info_enable = 1;
  170. req->wfc_call_twt_config_enable_valid = 1;
  171. req->wfc_call_twt_config_enable = 1;
  172. req->async_data_enable_valid = 1;
  173. req->async_data_enable = 1;
  174. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  175. wlfw_ind_register_resp_msg_v01_ei, resp);
  176. if (ret < 0) {
  177. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  178. ret);
  179. goto out;
  180. }
  181. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  182. QMI_WLFW_IND_REGISTER_REQ_V01,
  183. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  184. wlfw_ind_register_req_msg_v01_ei, req);
  185. if (ret < 0) {
  186. qmi_txn_cancel(&txn);
  187. cnss_pr_err("Failed to send indication register request, err: %d\n",
  188. ret);
  189. goto out;
  190. }
  191. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  192. if (ret < 0) {
  193. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  194. ret);
  195. goto out;
  196. }
  197. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  198. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  199. resp->resp.result, resp->resp.error);
  200. ret = -resp->resp.result;
  201. goto out;
  202. }
  203. if (resp->fw_status_valid) {
  204. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  205. ret = -EALREADY;
  206. goto qmi_registered;
  207. }
  208. }
  209. kfree(req);
  210. kfree(resp);
  211. return 0;
  212. out:
  213. CNSS_QMI_ASSERT();
  214. qmi_registered:
  215. kfree(req);
  216. kfree(resp);
  217. return ret;
  218. }
  219. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  220. struct wlfw_host_cap_req_msg_v01 *req)
  221. {
  222. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  223. plat_priv->device_id == MANGO_DEVICE_ID ||
  224. plat_priv->device_id == PEACH_DEVICE_ID) {
  225. req->mlo_capable_valid = 1;
  226. req->mlo_capable = 1;
  227. req->mlo_chip_id_valid = 1;
  228. req->mlo_chip_id = 0;
  229. req->mlo_group_id_valid = 1;
  230. req->mlo_group_id = 0;
  231. req->max_mlo_peer_valid = 1;
  232. /* Max peer number generally won't change for the same device
  233. * but needs to be synced with host driver.
  234. */
  235. req->max_mlo_peer = 32;
  236. req->mlo_num_chips_valid = 1;
  237. req->mlo_num_chips = 1;
  238. req->mlo_chip_info_valid = 1;
  239. req->mlo_chip_info[0].chip_id = 0;
  240. req->mlo_chip_info[0].num_local_links = 2;
  241. req->mlo_chip_info[0].hw_link_id[0] = 0;
  242. req->mlo_chip_info[0].hw_link_id[1] = 1;
  243. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  244. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  245. }
  246. }
  247. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  248. {
  249. struct wlfw_host_cap_req_msg_v01 *req;
  250. struct wlfw_host_cap_resp_msg_v01 *resp;
  251. struct qmi_txn txn;
  252. int ret = 0;
  253. u64 iova_start = 0, iova_size = 0,
  254. iova_ipa_start = 0, iova_ipa_size = 0;
  255. u64 feature_list = 0;
  256. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  257. plat_priv->driver_state);
  258. req = kzalloc(sizeof(*req), GFP_KERNEL);
  259. if (!req)
  260. return -ENOMEM;
  261. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  262. if (!resp) {
  263. kfree(req);
  264. return -ENOMEM;
  265. }
  266. req->num_clients_valid = 1;
  267. req->num_clients = 1;
  268. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  269. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  270. if (req->wake_msi) {
  271. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  272. req->wake_msi_valid = 1;
  273. }
  274. req->bdf_support_valid = 1;
  275. req->bdf_support = 1;
  276. req->m3_support_valid = 1;
  277. req->m3_support = 1;
  278. req->m3_cache_support_valid = 1;
  279. req->m3_cache_support = 1;
  280. req->cal_done_valid = 1;
  281. req->cal_done = plat_priv->cal_done;
  282. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  283. if (plat_priv->sleep_clk) {
  284. req->nm_modem_valid = 1;
  285. /* Notify firmware about the sleep clock selection,
  286. * nm_modem_bit[1] is used for this purpose.
  287. */
  288. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  289. }
  290. if (plat_priv->supported_link_speed) {
  291. req->pcie_link_info_valid = 1;
  292. req->pcie_link_info.pci_link_speed =
  293. plat_priv->supported_link_speed;
  294. cnss_pr_dbg("Supported link speed in Host Cap %d\n",
  295. plat_priv->supported_link_speed);
  296. }
  297. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  298. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  299. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  300. &iova_ipa_size)) {
  301. req->ddr_range_valid = 1;
  302. req->ddr_range[0].start = iova_start;
  303. req->ddr_range[0].size = iova_size + iova_ipa_size;
  304. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  305. req->ddr_range[0].start, req->ddr_range[0].size);
  306. }
  307. req->host_build_type_valid = 1;
  308. req->host_build_type = cnss_get_host_build_type();
  309. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  310. ret = cnss_get_feature_list(plat_priv, &feature_list);
  311. if (!ret) {
  312. req->feature_list_valid = 1;
  313. req->feature_list = feature_list;
  314. cnss_pr_dbg("Sending feature list 0x%llx\n",
  315. req->feature_list);
  316. }
  317. if (cnss_get_platform_name(plat_priv, req->platform_name,
  318. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  319. req->platform_name_valid = 1;
  320. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  321. wlfw_host_cap_resp_msg_v01_ei, resp);
  322. if (ret < 0) {
  323. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  324. ret);
  325. goto out;
  326. }
  327. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  328. QMI_WLFW_HOST_CAP_REQ_V01,
  329. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  330. wlfw_host_cap_req_msg_v01_ei, req);
  331. if (ret < 0) {
  332. qmi_txn_cancel(&txn);
  333. cnss_pr_err("Failed to send host capability request, err: %d\n",
  334. ret);
  335. goto out;
  336. }
  337. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  338. if (ret < 0) {
  339. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  340. ret);
  341. goto out;
  342. }
  343. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  344. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  345. resp->resp.result, resp->resp.error);
  346. ret = -resp->resp.result;
  347. goto out;
  348. }
  349. kfree(req);
  350. kfree(resp);
  351. return 0;
  352. out:
  353. CNSS_QMI_ASSERT();
  354. kfree(req);
  355. kfree(resp);
  356. return ret;
  357. }
  358. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  359. {
  360. struct wlfw_respond_mem_req_msg_v01 *req;
  361. struct wlfw_respond_mem_resp_msg_v01 *resp;
  362. struct qmi_txn txn;
  363. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  364. int ret = 0, i;
  365. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  366. plat_priv->driver_state);
  367. req = kzalloc(sizeof(*req), GFP_KERNEL);
  368. if (!req)
  369. return -ENOMEM;
  370. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  371. if (!resp) {
  372. kfree(req);
  373. return -ENOMEM;
  374. }
  375. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  376. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  377. ret = -EINVAL;
  378. goto out;
  379. }
  380. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  381. for (i = 0; i < req->mem_seg_len; i++) {
  382. if (!fw_mem[i].pa || !fw_mem[i].size) {
  383. if (fw_mem[i].type == 0) {
  384. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  385. i);
  386. ret = -EINVAL;
  387. goto out;
  388. }
  389. cnss_pr_err("Memory for FW is not available for type: %u\n",
  390. fw_mem[i].type);
  391. ret = -ENOMEM;
  392. goto out;
  393. }
  394. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  395. fw_mem[i].va, &fw_mem[i].pa,
  396. fw_mem[i].size, fw_mem[i].type);
  397. req->mem_seg[i].addr = fw_mem[i].pa;
  398. req->mem_seg[i].size = fw_mem[i].size;
  399. req->mem_seg[i].type = fw_mem[i].type;
  400. }
  401. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  402. wlfw_respond_mem_resp_msg_v01_ei, resp);
  403. if (ret < 0) {
  404. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  405. ret);
  406. goto out;
  407. }
  408. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  409. QMI_WLFW_RESPOND_MEM_REQ_V01,
  410. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  411. wlfw_respond_mem_req_msg_v01_ei, req);
  412. if (ret < 0) {
  413. qmi_txn_cancel(&txn);
  414. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  415. ret);
  416. goto out;
  417. }
  418. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  419. if (ret < 0) {
  420. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  421. ret);
  422. goto out;
  423. }
  424. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  425. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  426. resp->resp.result, resp->resp.error);
  427. ret = -resp->resp.result;
  428. goto out;
  429. }
  430. kfree(req);
  431. kfree(resp);
  432. return 0;
  433. out:
  434. CNSS_QMI_ASSERT();
  435. kfree(req);
  436. kfree(resp);
  437. return ret;
  438. }
  439. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  440. {
  441. struct wlfw_cap_req_msg_v01 *req;
  442. struct wlfw_cap_resp_msg_v01 *resp;
  443. struct qmi_txn txn;
  444. char *fw_build_timestamp;
  445. int ret = 0, i;
  446. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  447. plat_priv->driver_state);
  448. req = kzalloc(sizeof(*req), GFP_KERNEL);
  449. if (!req)
  450. return -ENOMEM;
  451. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  452. if (!resp) {
  453. kfree(req);
  454. return -ENOMEM;
  455. }
  456. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  457. wlfw_cap_resp_msg_v01_ei, resp);
  458. if (ret < 0) {
  459. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  460. ret);
  461. goto out;
  462. }
  463. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  464. QMI_WLFW_CAP_REQ_V01,
  465. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  466. wlfw_cap_req_msg_v01_ei, req);
  467. if (ret < 0) {
  468. qmi_txn_cancel(&txn);
  469. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  470. ret);
  471. goto out;
  472. }
  473. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  474. if (ret < 0) {
  475. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  476. ret);
  477. goto out;
  478. }
  479. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  480. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  481. resp->resp.result, resp->resp.error);
  482. ret = -resp->resp.result;
  483. goto out;
  484. }
  485. if (resp->chip_info_valid) {
  486. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  487. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  488. }
  489. if (resp->board_info_valid)
  490. plat_priv->board_info.board_id = resp->board_info.board_id;
  491. else
  492. plat_priv->board_info.board_id = 0xFF;
  493. if (resp->soc_info_valid)
  494. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  495. if (resp->fw_version_info_valid) {
  496. plat_priv->fw_version_info.fw_version =
  497. resp->fw_version_info.fw_version;
  498. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  499. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  500. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  501. resp->fw_version_info.fw_build_timestamp,
  502. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  503. }
  504. if (resp->fw_build_id_valid) {
  505. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  506. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  507. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  508. }
  509. /* FW will send aop retention volatage for qca6490 */
  510. if (resp->voltage_mv_valid) {
  511. plat_priv->cpr_info.voltage = resp->voltage_mv;
  512. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  513. plat_priv->cpr_info.voltage);
  514. cnss_update_cpr_info(plat_priv);
  515. }
  516. if (resp->time_freq_hz_valid) {
  517. plat_priv->device_freq_hz = resp->time_freq_hz;
  518. cnss_pr_dbg("Device frequency is %d HZ\n",
  519. plat_priv->device_freq_hz);
  520. }
  521. if (resp->otp_version_valid)
  522. plat_priv->otp_version = resp->otp_version;
  523. if (resp->dev_mem_info_valid) {
  524. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  525. plat_priv->dev_mem_info[i].start =
  526. resp->dev_mem_info[i].start;
  527. plat_priv->dev_mem_info[i].size =
  528. resp->dev_mem_info[i].size;
  529. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  530. i, plat_priv->dev_mem_info[i].start,
  531. plat_priv->dev_mem_info[i].size);
  532. }
  533. }
  534. if (resp->fw_caps_valid) {
  535. plat_priv->fw_pcie_gen_switch =
  536. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  537. plat_priv->fw_aux_uc_support =
  538. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  539. cnss_pr_dbg("FW aux uc support capability: %d\n",
  540. plat_priv->fw_aux_uc_support);
  541. plat_priv->fw_caps = resp->fw_caps;
  542. }
  543. if (resp->hang_data_length_valid &&
  544. resp->hang_data_length &&
  545. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  546. plat_priv->hang_event_data_len = resp->hang_data_length;
  547. else
  548. plat_priv->hang_event_data_len = 0;
  549. if (resp->hang_data_addr_offset_valid)
  550. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  551. else
  552. plat_priv->hang_data_addr_offset = 0;
  553. if (resp->hwid_bitmap_valid)
  554. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  555. if (resp->ol_cpr_cfg_valid)
  556. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  557. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  558. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  559. **/
  560. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  561. if (plat_priv->board_info.board_id ==
  562. plat_priv->on_chip_pmic_board_ids[i]) {
  563. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  564. plat_priv->board_info.board_id);
  565. ret = cnss_aop_send_msg(plat_priv,
  566. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  567. if (ret < 0)
  568. cnss_pr_dbg("Failed to Send AOP Msg");
  569. break;
  570. }
  571. }
  572. if (resp->serial_id_valid) {
  573. plat_priv->serial_id = resp->serial_id;
  574. cnss_pr_info("serial id 0x%x 0x%x\n",
  575. resp->serial_id.serial_id_msb,
  576. resp->serial_id.serial_id_lsb);
  577. }
  578. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  579. plat_priv->chip_info.chip_id,
  580. plat_priv->chip_info.chip_family,
  581. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  582. plat_priv->otp_version);
  583. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  584. plat_priv->fw_version_info.fw_version,
  585. plat_priv->fw_version_info.fw_build_timestamp,
  586. plat_priv->fw_build_id,
  587. plat_priv->hwid_bitmap);
  588. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  589. plat_priv->hang_event_data_len,
  590. plat_priv->hang_data_addr_offset);
  591. kfree(req);
  592. kfree(resp);
  593. return 0;
  594. out:
  595. CNSS_QMI_ASSERT();
  596. kfree(req);
  597. kfree(resp);
  598. return ret;
  599. }
  600. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  601. {
  602. switch (bdf_type) {
  603. case CNSS_BDF_BIN:
  604. case CNSS_BDF_ELF:
  605. return "BDF";
  606. case CNSS_BDF_REGDB:
  607. return "REGDB";
  608. case CNSS_BDF_HDS:
  609. return "HDS";
  610. default:
  611. return "UNKNOWN";
  612. }
  613. }
  614. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  615. u32 bdf_type, char *filename,
  616. u32 filename_len)
  617. {
  618. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  619. int ret = 0;
  620. switch (bdf_type) {
  621. case CNSS_BDF_ELF:
  622. /* Board ID will be equal or less than 0xFF in GF mask case */
  623. if (plat_priv->board_info.board_id == 0xFF) {
  624. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  625. snprintf(filename_tmp, filename_len,
  626. ELF_BDF_FILE_NAME_GF);
  627. else
  628. snprintf(filename_tmp, filename_len,
  629. ELF_BDF_FILE_NAME);
  630. } else if (plat_priv->board_info.board_id < 0xFF) {
  631. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  632. snprintf(filename_tmp, filename_len,
  633. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  634. plat_priv->board_info.board_id);
  635. else
  636. snprintf(filename_tmp, filename_len,
  637. ELF_BDF_FILE_NAME_PREFIX "%02x",
  638. plat_priv->board_info.board_id);
  639. } else {
  640. snprintf(filename_tmp, filename_len,
  641. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  642. plat_priv->board_info.board_id >> 8 & 0xFF,
  643. plat_priv->board_info.board_id & 0xFF);
  644. }
  645. break;
  646. case CNSS_BDF_BIN:
  647. if (plat_priv->board_info.board_id == 0xFF) {
  648. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  649. snprintf(filename_tmp, filename_len,
  650. BIN_BDF_FILE_NAME_GF);
  651. else
  652. snprintf(filename_tmp, filename_len,
  653. BIN_BDF_FILE_NAME);
  654. } else if (plat_priv->board_info.board_id < 0xFF) {
  655. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  656. snprintf(filename_tmp, filename_len,
  657. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  658. plat_priv->board_info.board_id);
  659. else
  660. snprintf(filename_tmp, filename_len,
  661. BIN_BDF_FILE_NAME_PREFIX "%02x",
  662. plat_priv->board_info.board_id);
  663. } else {
  664. snprintf(filename_tmp, filename_len,
  665. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  666. plat_priv->board_info.board_id >> 8 & 0xFF,
  667. plat_priv->board_info.board_id & 0xFF);
  668. }
  669. break;
  670. case CNSS_BDF_REGDB:
  671. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  672. break;
  673. case CNSS_BDF_HDS:
  674. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  675. break;
  676. default:
  677. cnss_pr_err("Invalid BDF type: %d\n",
  678. plat_priv->ctrl_params.bdf_type);
  679. ret = -EINVAL;
  680. break;
  681. }
  682. if (!ret)
  683. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  684. return ret;
  685. }
  686. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  687. u32 bdf_type)
  688. {
  689. struct wlfw_bdf_download_req_msg_v01 *req;
  690. struct wlfw_bdf_download_resp_msg_v01 *resp;
  691. struct qmi_txn txn;
  692. char filename[MAX_FIRMWARE_NAME_LEN];
  693. const struct firmware *fw_entry = NULL;
  694. const u8 *temp;
  695. unsigned int remaining;
  696. int ret = 0;
  697. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  698. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  699. req = kzalloc(sizeof(*req), GFP_KERNEL);
  700. if (!req)
  701. return -ENOMEM;
  702. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  703. if (!resp) {
  704. kfree(req);
  705. return -ENOMEM;
  706. }
  707. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  708. filename, sizeof(filename));
  709. if (ret)
  710. goto err_req_fw;
  711. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n", filename);
  712. if (bdf_type == CNSS_BDF_REGDB)
  713. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  714. filename);
  715. else
  716. ret = firmware_request_nowarn(&fw_entry, filename,
  717. &plat_priv->plat_dev->dev);
  718. if (ret) {
  719. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  720. cnss_bdf_type_to_str(bdf_type), filename, ret);
  721. goto err_req_fw;
  722. }
  723. temp = fw_entry->data;
  724. remaining = fw_entry->size;
  725. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  726. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  727. while (remaining) {
  728. req->valid = 1;
  729. req->file_id_valid = 1;
  730. req->file_id = plat_priv->board_info.board_id;
  731. req->total_size_valid = 1;
  732. req->total_size = remaining;
  733. req->seg_id_valid = 1;
  734. req->data_valid = 1;
  735. req->end_valid = 1;
  736. req->bdf_type_valid = 1;
  737. req->bdf_type = bdf_type;
  738. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  739. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  740. } else {
  741. req->data_len = remaining;
  742. req->end = 1;
  743. }
  744. memcpy(req->data, temp, req->data_len);
  745. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  746. wlfw_bdf_download_resp_msg_v01_ei, resp);
  747. if (ret < 0) {
  748. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  749. cnss_bdf_type_to_str(bdf_type), ret);
  750. goto err_send;
  751. }
  752. ret = qmi_send_request
  753. (&plat_priv->qmi_wlfw, NULL, &txn,
  754. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  755. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  756. wlfw_bdf_download_req_msg_v01_ei, req);
  757. if (ret < 0) {
  758. qmi_txn_cancel(&txn);
  759. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  760. cnss_bdf_type_to_str(bdf_type), ret);
  761. goto err_send;
  762. }
  763. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  764. if (ret < 0) {
  765. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  766. cnss_bdf_type_to_str(bdf_type), ret);
  767. goto err_send;
  768. }
  769. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  770. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  771. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  772. resp->resp.error);
  773. ret = -resp->resp.result;
  774. goto err_send;
  775. }
  776. remaining -= req->data_len;
  777. temp += req->data_len;
  778. req->seg_id++;
  779. }
  780. release_firmware(fw_entry);
  781. if (resp->host_bdf_data_valid) {
  782. /* QCA6490 enable S3E regulator for IPA configuration only */
  783. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  784. cnss_enable_int_pow_amp_vreg(plat_priv);
  785. plat_priv->cbc_file_download =
  786. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  787. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  788. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  789. plat_priv->cbc_file_download);
  790. }
  791. kfree(req);
  792. kfree(resp);
  793. return 0;
  794. err_send:
  795. release_firmware(fw_entry);
  796. err_req_fw:
  797. if (!(bdf_type == CNSS_BDF_REGDB ||
  798. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  799. ret == -EAGAIN))
  800. CNSS_QMI_ASSERT();
  801. kfree(req);
  802. kfree(resp);
  803. return ret;
  804. }
  805. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  806. enum wlfw_tme_lite_file_type_v01 file)
  807. {
  808. struct wlfw_tme_lite_info_req_msg_v01 *req;
  809. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  810. struct qmi_txn txn;
  811. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  812. int ret = 0;
  813. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  814. plat_priv->driver_state);
  815. if (plat_priv->device_id != PEACH_DEVICE_ID)
  816. return 0;
  817. req = kzalloc(sizeof(*req), GFP_KERNEL);
  818. if (!req)
  819. return -ENOMEM;
  820. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  821. if (!resp) {
  822. kfree(req);
  823. return -ENOMEM;
  824. }
  825. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  826. cnss_pr_err("Memory for TME patch is not available\n");
  827. ret = -ENOMEM;
  828. goto out;
  829. }
  830. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  831. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  832. req->tme_file = file;
  833. req->addr = plat_priv->tme_lite_mem.pa;
  834. req->size = plat_priv->tme_lite_mem.size;
  835. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  836. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  837. if (ret < 0) {
  838. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  839. ret);
  840. goto out;
  841. }
  842. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  843. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  844. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  845. wlfw_tme_lite_info_req_msg_v01_ei, req);
  846. if (ret < 0) {
  847. qmi_txn_cancel(&txn);
  848. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  849. ret);
  850. goto out;
  851. }
  852. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  853. if (ret < 0) {
  854. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  855. ret);
  856. goto out;
  857. }
  858. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  859. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  860. resp->resp.result, resp->resp.error);
  861. ret = -resp->resp.result;
  862. goto out;
  863. }
  864. kfree(req);
  865. kfree(resp);
  866. return 0;
  867. out:
  868. kfree(req);
  869. kfree(resp);
  870. return ret;
  871. }
  872. int cnss_wlfw_tme_opt_file_dnld_send_sync(struct cnss_plat_data *plat_priv,
  873. enum wlfw_tme_lite_file_type_v01 file)
  874. {
  875. struct wlfw_tme_lite_info_req_msg_v01 *req;
  876. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  877. struct qmi_txn txn;
  878. struct cnss_fw_mem *tme_opt_file_mem = NULL;
  879. char *file_name = NULL;
  880. int ret = 0;
  881. if (plat_priv->device_id != PEACH_DEVICE_ID)
  882. return 0;
  883. cnss_pr_dbg("Sending TME opt file information message, state: 0x%lx\n",
  884. plat_priv->driver_state);
  885. req = kzalloc(sizeof(*req), GFP_KERNEL);
  886. if (!req)
  887. return -ENOMEM;
  888. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  889. if (!resp) {
  890. kfree(req);
  891. return -ENOMEM;
  892. }
  893. if (file == WLFW_TME_LITE_OEM_FUSE_FILE_V01) {
  894. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[0];
  895. file_name = TME_OEM_FUSE_FILE_NAME;
  896. } else if (file == WLFW_TME_LITE_RPR_FILE_V01) {
  897. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[1];
  898. file_name = TME_RPR_FILE_NAME;
  899. } else if (file == WLFW_TME_LITE_DPR_FILE_V01) {
  900. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[2];
  901. file_name = TME_DPR_FILE_NAME;
  902. }
  903. if (!tme_opt_file_mem || !tme_opt_file_mem->pa ||
  904. !tme_opt_file_mem->size) {
  905. cnss_pr_err("Memory for TME opt file is not available\n");
  906. ret = -ENOMEM;
  907. goto out;
  908. }
  909. cnss_pr_dbg("TME opt file %s memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  910. file_name, tme_opt_file_mem->va, &tme_opt_file_mem->pa, tme_opt_file_mem->size);
  911. req->tme_file = file;
  912. req->addr = tme_opt_file_mem->pa;
  913. req->size = tme_opt_file_mem->size;
  914. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  915. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  916. if (ret < 0) {
  917. cnss_pr_err("Failed to initialize txn for TME opt file information request, err: %d\n",
  918. ret);
  919. goto out;
  920. }
  921. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  922. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  923. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  924. wlfw_tme_lite_info_req_msg_v01_ei, req);
  925. if (ret < 0) {
  926. qmi_txn_cancel(&txn);
  927. cnss_pr_err("Failed to send TME opt file information request, err: %d\n",
  928. ret);
  929. goto out;
  930. }
  931. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  932. if (ret < 0) {
  933. cnss_pr_err("Failed to wait for response of TME opt file information request, err: %d\n",
  934. ret);
  935. goto out;
  936. }
  937. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  938. ret = -resp->resp.result;
  939. if (resp->resp.error == QMI_ERR_HARDWARE_RESTRICTED_V01) {
  940. cnss_pr_err("TME Power On failed\n");
  941. goto out;
  942. } else if (resp->resp.error == QMI_ERR_ENOMEM_V01) {
  943. cnss_pr_err("malloc SRAM failed\n");
  944. goto out;
  945. }
  946. cnss_pr_err("TME opt file information request failed, result: %d, err: %d\n",
  947. resp->resp.result, resp->resp.error);
  948. goto out;
  949. }
  950. kfree(req);
  951. kfree(resp);
  952. return 0;
  953. out:
  954. CNSS_QMI_ASSERT();
  955. kfree(req);
  956. kfree(resp);
  957. return ret;
  958. }
  959. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  960. {
  961. struct wlfw_m3_info_req_msg_v01 *req;
  962. struct wlfw_m3_info_resp_msg_v01 *resp;
  963. struct qmi_txn txn;
  964. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  965. int ret = 0;
  966. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  967. plat_priv->driver_state);
  968. req = kzalloc(sizeof(*req), GFP_KERNEL);
  969. if (!req)
  970. return -ENOMEM;
  971. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  972. if (!resp) {
  973. kfree(req);
  974. return -ENOMEM;
  975. }
  976. if (!m3_mem->pa || !m3_mem->size) {
  977. cnss_pr_err("Memory for M3 is not available\n");
  978. ret = -ENOMEM;
  979. goto out;
  980. }
  981. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  982. m3_mem->va, &m3_mem->pa, m3_mem->size);
  983. req->addr = plat_priv->m3_mem.pa;
  984. req->size = plat_priv->m3_mem.size;
  985. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  986. wlfw_m3_info_resp_msg_v01_ei, resp);
  987. if (ret < 0) {
  988. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  989. ret);
  990. goto out;
  991. }
  992. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  993. QMI_WLFW_M3_INFO_REQ_V01,
  994. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  995. wlfw_m3_info_req_msg_v01_ei, req);
  996. if (ret < 0) {
  997. qmi_txn_cancel(&txn);
  998. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  999. ret);
  1000. goto out;
  1001. }
  1002. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1003. if (ret < 0) {
  1004. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  1005. ret);
  1006. goto out;
  1007. }
  1008. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1009. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  1010. resp->resp.result, resp->resp.error);
  1011. ret = -resp->resp.result;
  1012. goto out;
  1013. }
  1014. kfree(req);
  1015. kfree(resp);
  1016. return 0;
  1017. out:
  1018. CNSS_QMI_ASSERT();
  1019. kfree(req);
  1020. kfree(resp);
  1021. return ret;
  1022. }
  1023. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1024. {
  1025. struct wlfw_aux_uc_info_req_msg_v01 *req;
  1026. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  1027. struct qmi_txn txn;
  1028. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  1029. int ret = 0;
  1030. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  1031. plat_priv->driver_state);
  1032. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1033. if (!req)
  1034. return -ENOMEM;
  1035. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1036. if (!resp) {
  1037. kfree(req);
  1038. return -ENOMEM;
  1039. }
  1040. if (!aux_mem->pa || !aux_mem->size) {
  1041. cnss_pr_err("Memory for AUX is not available\n");
  1042. ret = -ENOMEM;
  1043. goto out;
  1044. }
  1045. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  1046. aux_mem->va, &aux_mem->pa, aux_mem->size);
  1047. req->addr = plat_priv->aux_mem.pa;
  1048. req->size = plat_priv->aux_mem.size;
  1049. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1050. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  1051. if (ret < 0) {
  1052. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1053. ret);
  1054. goto out;
  1055. }
  1056. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1057. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  1058. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1059. wlfw_aux_uc_info_req_msg_v01_ei, req);
  1060. if (ret < 0) {
  1061. qmi_txn_cancel(&txn);
  1062. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1063. ret);
  1064. goto out;
  1065. }
  1066. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1067. if (ret < 0) {
  1068. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1069. ret);
  1070. goto out;
  1071. }
  1072. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1073. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  1074. resp->resp.result, resp->resp.error);
  1075. ret = -resp->resp.result;
  1076. goto out;
  1077. }
  1078. kfree(req);
  1079. kfree(resp);
  1080. return 0;
  1081. out:
  1082. CNSS_QMI_ASSERT();
  1083. kfree(req);
  1084. kfree(resp);
  1085. return ret;
  1086. }
  1087. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  1088. u8 *mac, u32 mac_len)
  1089. {
  1090. struct wlfw_mac_addr_req_msg_v01 req;
  1091. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  1092. struct qmi_txn txn;
  1093. int ret;
  1094. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  1095. return -EINVAL;
  1096. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1097. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1098. if (ret < 0) {
  1099. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1100. ret);
  1101. ret = -EIO;
  1102. goto out;
  1103. }
  1104. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1105. mac, plat_priv->driver_state);
  1106. memcpy(req.mac_addr, mac, mac_len);
  1107. req.mac_addr_valid = 1;
  1108. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1109. QMI_WLFW_MAC_ADDR_REQ_V01,
  1110. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1111. wlfw_mac_addr_req_msg_v01_ei, &req);
  1112. if (ret < 0) {
  1113. qmi_txn_cancel(&txn);
  1114. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1115. ret = -EIO;
  1116. goto out;
  1117. }
  1118. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1119. if (ret < 0) {
  1120. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1121. ret);
  1122. ret = -EIO;
  1123. goto out;
  1124. }
  1125. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1126. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1127. resp.resp.result);
  1128. ret = -resp.resp.result;
  1129. }
  1130. out:
  1131. return ret;
  1132. }
  1133. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1134. u32 total_size)
  1135. {
  1136. int ret = 0;
  1137. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1138. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1139. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1140. unsigned int remaining;
  1141. struct qmi_txn txn;
  1142. cnss_pr_dbg("%s\n", __func__);
  1143. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1144. if (!req)
  1145. return -ENOMEM;
  1146. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1147. if (!resp) {
  1148. kfree(req);
  1149. return -ENOMEM;
  1150. }
  1151. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1152. if (!p_qdss_trace_data) {
  1153. ret = ENOMEM;
  1154. goto end;
  1155. }
  1156. remaining = total_size;
  1157. p_qdss_trace_data_temp = p_qdss_trace_data;
  1158. while (remaining && resp->end == 0) {
  1159. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1160. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1161. if (ret < 0) {
  1162. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1163. ret);
  1164. goto fail;
  1165. }
  1166. ret = qmi_send_request
  1167. (&plat_priv->qmi_wlfw, NULL, &txn,
  1168. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1169. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1170. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1171. if (ret < 0) {
  1172. qmi_txn_cancel(&txn);
  1173. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1174. ret);
  1175. goto fail;
  1176. }
  1177. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1178. if (ret < 0) {
  1179. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1180. ret);
  1181. goto fail;
  1182. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1183. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1184. resp->resp.result, resp->resp.error);
  1185. ret = -resp->resp.result;
  1186. goto fail;
  1187. } else {
  1188. ret = 0;
  1189. }
  1190. cnss_pr_dbg("%s: response total size %d data len %d",
  1191. __func__, resp->total_size, resp->data_len);
  1192. if ((resp->total_size_valid == 1 &&
  1193. resp->total_size == total_size) &&
  1194. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1195. (resp->data_valid == 1 &&
  1196. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1197. resp->data_len <= remaining) {
  1198. memcpy(p_qdss_trace_data_temp,
  1199. resp->data, resp->data_len);
  1200. } else {
  1201. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1202. __func__,
  1203. total_size, req->seg_id,
  1204. resp->total_size_valid,
  1205. resp->total_size,
  1206. resp->seg_id_valid,
  1207. resp->seg_id,
  1208. resp->data_valid,
  1209. resp->data_len);
  1210. ret = -1;
  1211. goto fail;
  1212. }
  1213. remaining -= resp->data_len;
  1214. p_qdss_trace_data_temp += resp->data_len;
  1215. req->seg_id++;
  1216. }
  1217. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1218. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1219. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1220. total_size);
  1221. if (ret < 0) {
  1222. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1223. ret);
  1224. ret = -1;
  1225. goto fail;
  1226. }
  1227. } else {
  1228. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1229. __func__,
  1230. remaining, resp->end_valid, resp->end);
  1231. ret = -1;
  1232. goto fail;
  1233. }
  1234. fail:
  1235. kfree(p_qdss_trace_data);
  1236. end:
  1237. kfree(req);
  1238. kfree(resp);
  1239. return ret;
  1240. }
  1241. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1242. char *filename, u32 filename_len,
  1243. bool fallback_file)
  1244. {
  1245. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1246. char *build_str = QDSS_FILE_BUILD_STR;
  1247. if (fallback_file)
  1248. build_str = "";
  1249. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1250. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1251. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1252. else
  1253. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1254. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1255. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1256. }
  1257. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1258. {
  1259. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1260. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1261. struct qmi_txn txn;
  1262. const struct firmware *fw_entry = NULL;
  1263. const u8 *temp;
  1264. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1265. unsigned int remaining;
  1266. int ret = 0;
  1267. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1268. plat_priv->driver_state);
  1269. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1270. if (!req)
  1271. return -ENOMEM;
  1272. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1273. if (!resp) {
  1274. kfree(req);
  1275. return -ENOMEM;
  1276. }
  1277. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1278. sizeof(qdss_cfg_filename), false);
  1279. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1280. qdss_cfg_filename);
  1281. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1282. qdss_cfg_filename);
  1283. if (ret) {
  1284. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1285. qdss_cfg_filename, ret);
  1286. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1287. sizeof(qdss_cfg_filename),
  1288. true);
  1289. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1290. qdss_cfg_filename);
  1291. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1292. qdss_cfg_filename);
  1293. if (ret) {
  1294. cnss_pr_err("Unable to load %s ret %d\n",
  1295. qdss_cfg_filename, ret);
  1296. goto err_req_fw;
  1297. }
  1298. }
  1299. temp = fw_entry->data;
  1300. remaining = fw_entry->size;
  1301. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1302. qdss_cfg_filename, remaining);
  1303. while (remaining) {
  1304. req->total_size_valid = 1;
  1305. req->total_size = remaining;
  1306. req->seg_id_valid = 1;
  1307. req->data_valid = 1;
  1308. req->end_valid = 1;
  1309. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1310. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1311. } else {
  1312. req->data_len = remaining;
  1313. req->end = 1;
  1314. }
  1315. memcpy(req->data, temp, req->data_len);
  1316. ret = qmi_txn_init
  1317. (&plat_priv->qmi_wlfw, &txn,
  1318. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1319. resp);
  1320. if (ret < 0) {
  1321. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1322. ret);
  1323. goto err_send;
  1324. }
  1325. ret = qmi_send_request
  1326. (&plat_priv->qmi_wlfw, NULL, &txn,
  1327. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1328. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1329. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1330. if (ret < 0) {
  1331. qmi_txn_cancel(&txn);
  1332. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1333. ret);
  1334. goto err_send;
  1335. }
  1336. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1337. if (ret < 0) {
  1338. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1339. ret);
  1340. goto err_send;
  1341. }
  1342. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1343. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1344. resp->resp.result, resp->resp.error);
  1345. ret = -resp->resp.result;
  1346. goto err_send;
  1347. }
  1348. remaining -= req->data_len;
  1349. temp += req->data_len;
  1350. req->seg_id++;
  1351. }
  1352. release_firmware(fw_entry);
  1353. kfree(req);
  1354. kfree(resp);
  1355. return 0;
  1356. err_send:
  1357. release_firmware(fw_entry);
  1358. err_req_fw:
  1359. kfree(req);
  1360. kfree(resp);
  1361. return ret;
  1362. }
  1363. static int wlfw_send_qdss_trace_mode_req
  1364. (struct cnss_plat_data *plat_priv,
  1365. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1366. unsigned long long option)
  1367. {
  1368. int rc = 0;
  1369. int tmp = 0;
  1370. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1371. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1372. struct qmi_txn txn;
  1373. if (!plat_priv)
  1374. return -ENODEV;
  1375. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1376. if (!req)
  1377. return -ENOMEM;
  1378. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1379. if (!resp) {
  1380. kfree(req);
  1381. return -ENOMEM;
  1382. }
  1383. req->mode_valid = 1;
  1384. req->mode = mode;
  1385. req->option_valid = 1;
  1386. req->option = option;
  1387. tmp = plat_priv->hw_trc_override;
  1388. req->hw_trc_disable_override_valid = 1;
  1389. req->hw_trc_disable_override =
  1390. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1391. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1392. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1393. __func__, mode, option, req->hw_trc_disable_override);
  1394. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1395. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1396. if (rc < 0) {
  1397. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1398. rc);
  1399. goto out;
  1400. }
  1401. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1402. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1403. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1404. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1405. if (rc < 0) {
  1406. qmi_txn_cancel(&txn);
  1407. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1408. goto out;
  1409. }
  1410. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1411. if (rc < 0) {
  1412. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1413. rc);
  1414. goto out;
  1415. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1416. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1417. resp->resp.result, resp->resp.error);
  1418. rc = -resp->resp.result;
  1419. goto out;
  1420. }
  1421. kfree(resp);
  1422. kfree(req);
  1423. return rc;
  1424. out:
  1425. kfree(resp);
  1426. kfree(req);
  1427. CNSS_QMI_ASSERT();
  1428. return rc;
  1429. }
  1430. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1431. {
  1432. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1433. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1434. }
  1435. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1436. {
  1437. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1438. option);
  1439. }
  1440. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1441. enum cnss_driver_mode mode)
  1442. {
  1443. struct wlfw_wlan_mode_req_msg_v01 *req;
  1444. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1445. struct qmi_txn txn;
  1446. int ret = 0;
  1447. if (!plat_priv)
  1448. return -ENODEV;
  1449. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1450. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1451. if (mode == CNSS_OFF &&
  1452. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1453. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1454. return 0;
  1455. }
  1456. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1457. if (!req)
  1458. return -ENOMEM;
  1459. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1460. if (!resp) {
  1461. kfree(req);
  1462. return -ENOMEM;
  1463. }
  1464. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1465. req->hw_debug_valid = 1;
  1466. req->hw_debug = 0;
  1467. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1468. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1469. if (ret < 0) {
  1470. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1471. cnss_qmi_mode_to_str(mode), mode, ret);
  1472. goto out;
  1473. }
  1474. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1475. QMI_WLFW_WLAN_MODE_REQ_V01,
  1476. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1477. wlfw_wlan_mode_req_msg_v01_ei, req);
  1478. if (ret < 0) {
  1479. qmi_txn_cancel(&txn);
  1480. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1481. cnss_qmi_mode_to_str(mode), mode, ret);
  1482. goto out;
  1483. }
  1484. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1485. if (ret < 0) {
  1486. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1487. cnss_qmi_mode_to_str(mode), mode, ret);
  1488. goto out;
  1489. }
  1490. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1491. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1492. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1493. resp->resp.error);
  1494. ret = -resp->resp.result;
  1495. goto out;
  1496. }
  1497. kfree(req);
  1498. kfree(resp);
  1499. return 0;
  1500. out:
  1501. if (mode == CNSS_OFF) {
  1502. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1503. ret = 0;
  1504. } else {
  1505. CNSS_QMI_ASSERT();
  1506. }
  1507. kfree(req);
  1508. kfree(resp);
  1509. return ret;
  1510. }
  1511. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1512. struct cnss_wlan_enable_cfg *config,
  1513. const char *host_version)
  1514. {
  1515. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1516. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1517. struct qmi_txn txn;
  1518. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1519. int ret = 0;
  1520. if (!plat_priv)
  1521. return -ENODEV;
  1522. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1523. plat_priv->driver_state);
  1524. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1525. if (!req)
  1526. return -ENOMEM;
  1527. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1528. if (!resp) {
  1529. kfree(req);
  1530. return -ENOMEM;
  1531. }
  1532. req->host_version_valid = 1;
  1533. strlcpy(req->host_version, host_version,
  1534. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1535. req->tgt_cfg_valid = 1;
  1536. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1537. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1538. else
  1539. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1540. for (i = 0; i < req->tgt_cfg_len; i++) {
  1541. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1542. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1543. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1544. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1545. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1546. }
  1547. req->svc_cfg_valid = 1;
  1548. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1549. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1550. else
  1551. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1552. for (i = 0; i < req->svc_cfg_len; i++) {
  1553. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1554. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1555. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1556. }
  1557. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1558. plat_priv->device_id != MANGO_DEVICE_ID &&
  1559. plat_priv->device_id != PEACH_DEVICE_ID) {
  1560. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1561. config->num_shadow_reg_cfg) {
  1562. req->shadow_reg_valid = 1;
  1563. if (config->num_shadow_reg_cfg >
  1564. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1565. req->shadow_reg_len =
  1566. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1567. else
  1568. req->shadow_reg_len =
  1569. config->num_shadow_reg_cfg;
  1570. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1571. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1572. req->shadow_reg_len);
  1573. } else {
  1574. req->shadow_reg_v2_valid = 1;
  1575. if (config->num_shadow_reg_v2_cfg >
  1576. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1577. req->shadow_reg_v2_len =
  1578. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1579. else
  1580. req->shadow_reg_v2_len =
  1581. config->num_shadow_reg_v2_cfg;
  1582. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1583. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1584. req->shadow_reg_v2_len);
  1585. }
  1586. } else {
  1587. req->shadow_reg_v3_valid = 1;
  1588. if (config->num_shadow_reg_v3_cfg >
  1589. MAX_NUM_SHADOW_REG_V3)
  1590. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1591. else
  1592. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1593. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1594. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1595. plat_priv->num_shadow_regs_v3);
  1596. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1597. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1598. req->shadow_reg_v3_len);
  1599. }
  1600. if (config->rri_over_ddr_cfg_valid) {
  1601. req->rri_over_ddr_cfg_valid = 1;
  1602. req->rri_over_ddr_cfg.base_addr_low =
  1603. config->rri_over_ddr_cfg.base_addr_low;
  1604. req->rri_over_ddr_cfg.base_addr_high =
  1605. config->rri_over_ddr_cfg.base_addr_high;
  1606. }
  1607. if (config->send_msi_ce) {
  1608. ret = cnss_bus_get_msi_assignment(plat_priv,
  1609. CE_MSI_NAME,
  1610. &num_vectors,
  1611. &user_base_data,
  1612. &base_vector);
  1613. if (!ret) {
  1614. req->msi_cfg_valid = 1;
  1615. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1616. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1617. ce_id++) {
  1618. req->msi_cfg[ce_id].ce_id = ce_id;
  1619. req->msi_cfg[ce_id].msi_vector =
  1620. (ce_id % num_vectors) + base_vector;
  1621. }
  1622. }
  1623. }
  1624. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1625. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1626. if (ret < 0) {
  1627. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1628. ret);
  1629. goto out;
  1630. }
  1631. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1632. QMI_WLFW_WLAN_CFG_REQ_V01,
  1633. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1634. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1635. if (ret < 0) {
  1636. qmi_txn_cancel(&txn);
  1637. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1638. ret);
  1639. goto out;
  1640. }
  1641. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1642. if (ret < 0) {
  1643. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1644. ret);
  1645. goto out;
  1646. }
  1647. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1648. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1649. resp->resp.result, resp->resp.error);
  1650. ret = -resp->resp.result;
  1651. goto out;
  1652. }
  1653. kfree(req);
  1654. kfree(resp);
  1655. return 0;
  1656. out:
  1657. CNSS_QMI_ASSERT();
  1658. kfree(req);
  1659. kfree(resp);
  1660. return ret;
  1661. }
  1662. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1663. u32 offset, u32 mem_type,
  1664. u32 data_len, u8 *data)
  1665. {
  1666. struct wlfw_athdiag_read_req_msg_v01 *req;
  1667. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1668. struct qmi_txn txn;
  1669. int ret = 0;
  1670. if (!plat_priv)
  1671. return -ENODEV;
  1672. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1673. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1674. data, data_len);
  1675. return -EINVAL;
  1676. }
  1677. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1678. plat_priv->driver_state, offset, mem_type, data_len);
  1679. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1680. if (!req)
  1681. return -ENOMEM;
  1682. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1683. if (!resp) {
  1684. kfree(req);
  1685. return -ENOMEM;
  1686. }
  1687. req->offset = offset;
  1688. req->mem_type = mem_type;
  1689. req->data_len = data_len;
  1690. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1691. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1692. if (ret < 0) {
  1693. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1694. ret);
  1695. goto out;
  1696. }
  1697. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1698. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1699. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1700. wlfw_athdiag_read_req_msg_v01_ei, req);
  1701. if (ret < 0) {
  1702. qmi_txn_cancel(&txn);
  1703. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1704. ret);
  1705. goto out;
  1706. }
  1707. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1708. if (ret < 0) {
  1709. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1710. ret);
  1711. goto out;
  1712. }
  1713. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1714. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1715. resp->resp.result, resp->resp.error);
  1716. ret = -resp->resp.result;
  1717. goto out;
  1718. }
  1719. if (!resp->data_valid || resp->data_len != data_len) {
  1720. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1721. resp->data_valid, resp->data_len);
  1722. ret = -EINVAL;
  1723. goto out;
  1724. }
  1725. memcpy(data, resp->data, resp->data_len);
  1726. kfree(req);
  1727. kfree(resp);
  1728. return 0;
  1729. out:
  1730. kfree(req);
  1731. kfree(resp);
  1732. return ret;
  1733. }
  1734. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1735. u32 offset, u32 mem_type,
  1736. u32 data_len, u8 *data)
  1737. {
  1738. struct wlfw_athdiag_write_req_msg_v01 *req;
  1739. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1740. struct qmi_txn txn;
  1741. int ret = 0;
  1742. if (!plat_priv)
  1743. return -ENODEV;
  1744. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1745. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1746. data, data_len);
  1747. return -EINVAL;
  1748. }
  1749. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1750. plat_priv->driver_state, offset, mem_type, data_len, data);
  1751. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1752. if (!req)
  1753. return -ENOMEM;
  1754. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1755. if (!resp) {
  1756. kfree(req);
  1757. return -ENOMEM;
  1758. }
  1759. req->offset = offset;
  1760. req->mem_type = mem_type;
  1761. req->data_len = data_len;
  1762. memcpy(req->data, data, data_len);
  1763. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1764. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1765. if (ret < 0) {
  1766. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1767. ret);
  1768. goto out;
  1769. }
  1770. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1771. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1772. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1773. wlfw_athdiag_write_req_msg_v01_ei, req);
  1774. if (ret < 0) {
  1775. qmi_txn_cancel(&txn);
  1776. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1777. ret);
  1778. goto out;
  1779. }
  1780. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1781. if (ret < 0) {
  1782. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1783. ret);
  1784. goto out;
  1785. }
  1786. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1787. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1788. resp->resp.result, resp->resp.error);
  1789. ret = -resp->resp.result;
  1790. goto out;
  1791. }
  1792. kfree(req);
  1793. kfree(resp);
  1794. return 0;
  1795. out:
  1796. kfree(req);
  1797. kfree(resp);
  1798. return ret;
  1799. }
  1800. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1801. u8 fw_log_mode)
  1802. {
  1803. struct wlfw_ini_req_msg_v01 *req;
  1804. struct wlfw_ini_resp_msg_v01 *resp;
  1805. struct qmi_txn txn;
  1806. int ret = 0;
  1807. if (!plat_priv)
  1808. return -ENODEV;
  1809. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1810. plat_priv->driver_state, fw_log_mode);
  1811. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1812. if (!req)
  1813. return -ENOMEM;
  1814. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1815. if (!resp) {
  1816. kfree(req);
  1817. return -ENOMEM;
  1818. }
  1819. req->enablefwlog_valid = 1;
  1820. req->enablefwlog = fw_log_mode;
  1821. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1822. wlfw_ini_resp_msg_v01_ei, resp);
  1823. if (ret < 0) {
  1824. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1825. fw_log_mode, ret);
  1826. goto out;
  1827. }
  1828. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1829. QMI_WLFW_INI_REQ_V01,
  1830. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1831. wlfw_ini_req_msg_v01_ei, req);
  1832. if (ret < 0) {
  1833. qmi_txn_cancel(&txn);
  1834. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1835. fw_log_mode, ret);
  1836. goto out;
  1837. }
  1838. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1839. if (ret < 0) {
  1840. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1841. fw_log_mode, ret);
  1842. goto out;
  1843. }
  1844. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1845. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1846. fw_log_mode, resp->resp.result, resp->resp.error);
  1847. ret = -resp->resp.result;
  1848. goto out;
  1849. }
  1850. kfree(req);
  1851. kfree(resp);
  1852. return 0;
  1853. out:
  1854. kfree(req);
  1855. kfree(resp);
  1856. return ret;
  1857. }
  1858. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1859. {
  1860. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1861. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1862. struct qmi_txn txn;
  1863. int ret = 0;
  1864. if (!plat_priv)
  1865. return -ENODEV;
  1866. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1867. !plat_priv->fw_pcie_gen_switch) {
  1868. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1869. return 0;
  1870. }
  1871. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1872. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1873. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1874. plat_priv->pcie_gen_speed;
  1875. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1876. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1877. if (ret < 0) {
  1878. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1879. ret);
  1880. goto out;
  1881. }
  1882. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1883. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1884. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1885. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1886. if (ret < 0) {
  1887. qmi_txn_cancel(&txn);
  1888. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1889. goto out;
  1890. }
  1891. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1892. if (ret < 0) {
  1893. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1894. ret);
  1895. goto out;
  1896. }
  1897. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1898. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1899. plat_priv->pcie_gen_speed, resp.resp.result,
  1900. resp.resp.error);
  1901. ret = -resp.resp.result;
  1902. }
  1903. out:
  1904. /* Reset PCIE Gen speed after one time use */
  1905. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1906. return ret;
  1907. }
  1908. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1909. {
  1910. struct wlfw_antenna_switch_req_msg_v01 *req;
  1911. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1912. struct qmi_txn txn;
  1913. int ret = 0;
  1914. if (!plat_priv)
  1915. return -ENODEV;
  1916. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1917. plat_priv->driver_state);
  1918. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1919. if (!req)
  1920. return -ENOMEM;
  1921. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1922. if (!resp) {
  1923. kfree(req);
  1924. return -ENOMEM;
  1925. }
  1926. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1927. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1928. if (ret < 0) {
  1929. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1930. ret);
  1931. goto out;
  1932. }
  1933. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1934. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1935. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1936. wlfw_antenna_switch_req_msg_v01_ei, req);
  1937. if (ret < 0) {
  1938. qmi_txn_cancel(&txn);
  1939. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1940. ret);
  1941. goto out;
  1942. }
  1943. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1944. if (ret < 0) {
  1945. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1946. ret);
  1947. goto out;
  1948. }
  1949. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1950. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1951. resp->resp.result, resp->resp.error);
  1952. ret = -resp->resp.result;
  1953. goto out;
  1954. }
  1955. if (resp->antenna_valid)
  1956. plat_priv->antenna = resp->antenna;
  1957. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1958. resp->antenna_valid, resp->antenna);
  1959. kfree(req);
  1960. kfree(resp);
  1961. return 0;
  1962. out:
  1963. kfree(req);
  1964. kfree(resp);
  1965. return ret;
  1966. }
  1967. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1968. {
  1969. struct wlfw_antenna_grant_req_msg_v01 *req;
  1970. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1971. struct qmi_txn txn;
  1972. int ret = 0;
  1973. if (!plat_priv)
  1974. return -ENODEV;
  1975. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1976. plat_priv->driver_state, plat_priv->grant);
  1977. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1978. if (!req)
  1979. return -ENOMEM;
  1980. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1981. if (!resp) {
  1982. kfree(req);
  1983. return -ENOMEM;
  1984. }
  1985. req->grant_valid = 1;
  1986. req->grant = plat_priv->grant;
  1987. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1988. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1989. if (ret < 0) {
  1990. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1991. ret);
  1992. goto out;
  1993. }
  1994. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1995. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1996. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  1997. wlfw_antenna_grant_req_msg_v01_ei, req);
  1998. if (ret < 0) {
  1999. qmi_txn_cancel(&txn);
  2000. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  2001. ret);
  2002. goto out;
  2003. }
  2004. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2005. if (ret < 0) {
  2006. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  2007. ret);
  2008. goto out;
  2009. }
  2010. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2011. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  2012. resp->resp.result, resp->resp.error);
  2013. ret = -resp->resp.result;
  2014. goto out;
  2015. }
  2016. kfree(req);
  2017. kfree(resp);
  2018. return 0;
  2019. out:
  2020. kfree(req);
  2021. kfree(resp);
  2022. return ret;
  2023. }
  2024. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  2025. {
  2026. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  2027. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  2028. struct qmi_txn txn;
  2029. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  2030. int ret = 0;
  2031. int i;
  2032. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  2033. plat_priv->driver_state);
  2034. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2035. if (!req)
  2036. return -ENOMEM;
  2037. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2038. if (!resp) {
  2039. kfree(req);
  2040. return -ENOMEM;
  2041. }
  2042. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2043. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  2044. ret = -EINVAL;
  2045. goto out;
  2046. }
  2047. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  2048. for (i = 0; i < req->mem_seg_len; i++) {
  2049. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  2050. qdss_mem[i].va, &qdss_mem[i].pa,
  2051. qdss_mem[i].size, qdss_mem[i].type);
  2052. req->mem_seg[i].addr = qdss_mem[i].pa;
  2053. req->mem_seg[i].size = qdss_mem[i].size;
  2054. req->mem_seg[i].type = qdss_mem[i].type;
  2055. }
  2056. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2057. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  2058. if (ret < 0) {
  2059. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  2060. ret);
  2061. goto out;
  2062. }
  2063. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2064. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  2065. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2066. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  2067. if (ret < 0) {
  2068. qmi_txn_cancel(&txn);
  2069. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  2070. ret);
  2071. goto out;
  2072. }
  2073. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2074. if (ret < 0) {
  2075. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  2076. ret);
  2077. goto out;
  2078. }
  2079. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2080. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  2081. resp->resp.result, resp->resp.error);
  2082. ret = -resp->resp.result;
  2083. goto out;
  2084. }
  2085. kfree(req);
  2086. kfree(resp);
  2087. return 0;
  2088. out:
  2089. kfree(req);
  2090. kfree(resp);
  2091. return ret;
  2092. }
  2093. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  2094. struct cnss_wfc_cfg cfg)
  2095. {
  2096. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2097. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2098. struct qmi_txn txn;
  2099. int ret = 0;
  2100. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2101. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2102. return -EINVAL;
  2103. }
  2104. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2105. if (!req)
  2106. return -ENOMEM;
  2107. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2108. if (!resp) {
  2109. kfree(req);
  2110. return -ENOMEM;
  2111. }
  2112. req->wfc_call_active_valid = 1;
  2113. req->wfc_call_active = cfg.mode;
  2114. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2115. plat_priv->driver_state);
  2116. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2117. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2118. if (ret < 0) {
  2119. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2120. ret);
  2121. goto out;
  2122. }
  2123. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2124. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2125. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2126. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2127. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2128. if (ret < 0) {
  2129. qmi_txn_cancel(&txn);
  2130. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2131. ret);
  2132. goto out;
  2133. }
  2134. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2135. if (ret < 0) {
  2136. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2137. ret);
  2138. goto out;
  2139. }
  2140. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2141. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2142. resp->resp.result, resp->resp.error);
  2143. ret = -EINVAL;
  2144. goto out;
  2145. }
  2146. ret = 0;
  2147. out:
  2148. kfree(req);
  2149. kfree(resp);
  2150. return ret;
  2151. }
  2152. static int cnss_wlfw_wfc_call_status_send_sync
  2153. (struct cnss_plat_data *plat_priv,
  2154. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2155. {
  2156. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2157. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2158. struct qmi_txn txn;
  2159. int ret = 0;
  2160. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2161. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2162. return -EINVAL;
  2163. }
  2164. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2165. if (!req)
  2166. return -ENOMEM;
  2167. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2168. if (!resp) {
  2169. kfree(req);
  2170. return -ENOMEM;
  2171. }
  2172. /**
  2173. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2174. * But in r2 update QMI structure is expanded and as an effect qmi
  2175. * decoded structures have padding. Thus we cannot use buffer design.
  2176. * For backward compatibility for r1 design copy only wfc_call_active
  2177. * value in hex buffer.
  2178. */
  2179. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2180. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2181. /* wfc_call_active is mandatory in IMS indication */
  2182. req->wfc_call_active_valid = 1;
  2183. req->wfc_call_active = ind_msg->wfc_call_active;
  2184. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2185. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2186. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2187. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2188. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2189. req->twt_ims_start = ind_msg->twt_ims_start;
  2190. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2191. req->twt_ims_int = ind_msg->twt_ims_int;
  2192. req->media_quality_valid = ind_msg->media_quality_valid;
  2193. req->media_quality =
  2194. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2195. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2196. plat_priv->driver_state);
  2197. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2198. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2199. if (ret < 0) {
  2200. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2201. ret);
  2202. goto out;
  2203. }
  2204. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2205. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2206. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2207. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2208. if (ret < 0) {
  2209. qmi_txn_cancel(&txn);
  2210. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2211. ret);
  2212. goto out;
  2213. }
  2214. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2215. if (ret < 0) {
  2216. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2217. ret);
  2218. goto out;
  2219. }
  2220. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2221. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2222. resp->resp.result, resp->resp.error);
  2223. ret = -resp->resp.result;
  2224. goto out;
  2225. }
  2226. ret = 0;
  2227. out:
  2228. kfree(req);
  2229. kfree(resp);
  2230. return ret;
  2231. }
  2232. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2233. {
  2234. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2235. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2236. struct qmi_txn txn;
  2237. int ret = 0;
  2238. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2239. plat_priv->dynamic_feature,
  2240. plat_priv->driver_state);
  2241. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2242. if (!req)
  2243. return -ENOMEM;
  2244. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2245. if (!resp) {
  2246. kfree(req);
  2247. return -ENOMEM;
  2248. }
  2249. req->mask_valid = 1;
  2250. req->mask = plat_priv->dynamic_feature;
  2251. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2252. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2253. if (ret < 0) {
  2254. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2255. ret);
  2256. goto out;
  2257. }
  2258. ret = qmi_send_request
  2259. (&plat_priv->qmi_wlfw, NULL, &txn,
  2260. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2261. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2262. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2263. if (ret < 0) {
  2264. qmi_txn_cancel(&txn);
  2265. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2266. ret);
  2267. goto out;
  2268. }
  2269. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2270. if (ret < 0) {
  2271. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2272. ret);
  2273. goto out;
  2274. }
  2275. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2276. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2277. resp->resp.result, resp->resp.error);
  2278. ret = -resp->resp.result;
  2279. goto out;
  2280. }
  2281. out:
  2282. kfree(req);
  2283. kfree(resp);
  2284. return ret;
  2285. }
  2286. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2287. void *cmd, int cmd_len)
  2288. {
  2289. struct wlfw_get_info_req_msg_v01 *req;
  2290. struct wlfw_get_info_resp_msg_v01 *resp;
  2291. struct qmi_txn txn;
  2292. int ret = 0;
  2293. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2294. type, cmd_len, plat_priv->driver_state);
  2295. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2296. return -EINVAL;
  2297. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2298. if (!req)
  2299. return -ENOMEM;
  2300. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2301. if (!resp) {
  2302. kfree(req);
  2303. return -ENOMEM;
  2304. }
  2305. req->type = type;
  2306. req->data_len = cmd_len;
  2307. memcpy(req->data, cmd, req->data_len);
  2308. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2309. wlfw_get_info_resp_msg_v01_ei, resp);
  2310. if (ret < 0) {
  2311. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2312. ret);
  2313. goto out;
  2314. }
  2315. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2316. QMI_WLFW_GET_INFO_REQ_V01,
  2317. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2318. wlfw_get_info_req_msg_v01_ei, req);
  2319. if (ret < 0) {
  2320. qmi_txn_cancel(&txn);
  2321. cnss_pr_err("Failed to send get info request, err: %d\n",
  2322. ret);
  2323. goto out;
  2324. }
  2325. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2326. if (ret < 0) {
  2327. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2328. ret);
  2329. goto out;
  2330. }
  2331. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2332. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2333. resp->resp.result, resp->resp.error);
  2334. ret = -resp->resp.result;
  2335. goto out;
  2336. }
  2337. kfree(req);
  2338. kfree(resp);
  2339. return 0;
  2340. out:
  2341. kfree(req);
  2342. kfree(resp);
  2343. return ret;
  2344. }
  2345. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2346. {
  2347. return QMI_WLFW_TIMEOUT_MS;
  2348. }
  2349. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2350. struct sockaddr_qrtr *sq,
  2351. struct qmi_txn *txn, const void *data)
  2352. {
  2353. struct cnss_plat_data *plat_priv =
  2354. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2355. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2356. int i;
  2357. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2358. if (!txn) {
  2359. cnss_pr_err("Spurious indication\n");
  2360. return;
  2361. }
  2362. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2363. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2364. return;
  2365. }
  2366. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2367. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2368. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2369. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2370. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2371. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2372. if (!plat_priv->fw_mem[i].va &&
  2373. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2374. plat_priv->fw_mem[i].attrs |=
  2375. DMA_ATTR_FORCE_CONTIGUOUS;
  2376. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2377. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2378. }
  2379. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2380. 0, NULL);
  2381. }
  2382. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2383. struct sockaddr_qrtr *sq,
  2384. struct qmi_txn *txn, const void *data)
  2385. {
  2386. struct cnss_plat_data *plat_priv =
  2387. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2388. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2389. if (!txn) {
  2390. cnss_pr_err("Spurious indication\n");
  2391. return;
  2392. }
  2393. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2394. 0, NULL);
  2395. }
  2396. /**
  2397. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2398. *
  2399. * This event is not required for HST/ HSP as FW calibration done is
  2400. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2401. */
  2402. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2403. struct sockaddr_qrtr *sq,
  2404. struct qmi_txn *txn, const void *data)
  2405. {
  2406. struct cnss_plat_data *plat_priv =
  2407. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2408. struct cnss_cal_info *cal_info;
  2409. if (!txn) {
  2410. cnss_pr_err("Spurious indication\n");
  2411. return;
  2412. }
  2413. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2414. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2415. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2416. return;
  2417. }
  2418. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2419. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2420. if (!cal_info)
  2421. return;
  2422. cal_info->cal_status = CNSS_CAL_DONE;
  2423. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2424. 0, cal_info);
  2425. }
  2426. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2427. struct sockaddr_qrtr *sq,
  2428. struct qmi_txn *txn, const void *data)
  2429. {
  2430. struct cnss_plat_data *plat_priv =
  2431. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2432. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2433. if (!txn) {
  2434. cnss_pr_err("Spurious indication\n");
  2435. return;
  2436. }
  2437. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2438. }
  2439. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2440. struct sockaddr_qrtr *sq,
  2441. struct qmi_txn *txn, const void *data)
  2442. {
  2443. struct cnss_plat_data *plat_priv =
  2444. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2445. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2446. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2447. if (!txn) {
  2448. cnss_pr_err("Spurious indication\n");
  2449. return;
  2450. }
  2451. if (ind_msg->pwr_pin_result_valid)
  2452. plat_priv->pin_result.fw_pwr_pin_result =
  2453. ind_msg->pwr_pin_result;
  2454. if (ind_msg->phy_io_pin_result_valid)
  2455. plat_priv->pin_result.fw_phy_io_pin_result =
  2456. ind_msg->phy_io_pin_result;
  2457. if (ind_msg->rf_pin_result_valid)
  2458. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2459. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2460. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2461. ind_msg->rf_pin_result);
  2462. }
  2463. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2464. u32 cal_file_download_size)
  2465. {
  2466. struct wlfw_cal_report_req_msg_v01 req = {0};
  2467. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2468. struct qmi_txn txn;
  2469. int ret = 0;
  2470. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2471. cal_file_download_size, plat_priv->driver_state);
  2472. req.cal_file_download_size_valid = 1;
  2473. req.cal_file_download_size = cal_file_download_size;
  2474. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2475. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2476. if (ret < 0) {
  2477. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2478. ret);
  2479. goto out;
  2480. }
  2481. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2482. QMI_WLFW_CAL_REPORT_REQ_V01,
  2483. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2484. wlfw_cal_report_req_msg_v01_ei, &req);
  2485. if (ret < 0) {
  2486. qmi_txn_cancel(&txn);
  2487. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2488. ret);
  2489. goto out;
  2490. }
  2491. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2492. if (ret < 0) {
  2493. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2494. ret);
  2495. goto out;
  2496. }
  2497. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2498. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2499. resp.resp.result, resp.resp.error);
  2500. ret = -resp.resp.result;
  2501. goto out;
  2502. }
  2503. out:
  2504. return ret;
  2505. }
  2506. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2507. struct sockaddr_qrtr *sq,
  2508. struct qmi_txn *txn, const void *data)
  2509. {
  2510. struct cnss_plat_data *plat_priv =
  2511. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2512. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2513. struct cnss_cal_info *cal_info;
  2514. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2515. ind->cal_file_upload_size);
  2516. cnss_pr_info("Calibration took %d ms\n",
  2517. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2518. if (!txn) {
  2519. cnss_pr_err("Spurious indication\n");
  2520. return;
  2521. }
  2522. if (ind->cal_file_upload_size_valid)
  2523. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2524. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2525. if (!cal_info)
  2526. return;
  2527. cal_info->cal_status = CNSS_CAL_DONE;
  2528. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2529. 0, cal_info);
  2530. }
  2531. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2532. struct sockaddr_qrtr *sq,
  2533. struct qmi_txn *txn,
  2534. const void *data)
  2535. {
  2536. struct cnss_plat_data *plat_priv =
  2537. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2538. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2539. int i;
  2540. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2541. if (!txn) {
  2542. cnss_pr_err("Spurious indication\n");
  2543. return;
  2544. }
  2545. if (plat_priv->qdss_mem_seg_len) {
  2546. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2547. plat_priv->qdss_mem_seg_len);
  2548. return;
  2549. }
  2550. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2551. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2552. return;
  2553. }
  2554. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2555. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2556. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2557. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2558. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2559. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2560. }
  2561. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2562. 0, NULL);
  2563. }
  2564. /**
  2565. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2566. *
  2567. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2568. * fw memory segment for dumping to file system. Only one type of mem can be
  2569. * saved per indication and is provided in mem seg index 0.
  2570. *
  2571. * Return: None
  2572. */
  2573. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2574. struct sockaddr_qrtr *sq,
  2575. struct qmi_txn *txn,
  2576. const void *data)
  2577. {
  2578. struct cnss_plat_data *plat_priv =
  2579. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2580. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2581. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2582. int i = 0;
  2583. if (!txn || !data) {
  2584. cnss_pr_err("Spurious indication\n");
  2585. return;
  2586. }
  2587. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2588. ind_msg->source, ind_msg->mem_seg_valid,
  2589. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2590. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2591. if (!event_data)
  2592. return;
  2593. event_data->mem_type = ind_msg->mem_seg[0].type;
  2594. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2595. event_data->total_size = ind_msg->total_size;
  2596. if (ind_msg->mem_seg_valid) {
  2597. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2598. cnss_pr_err("Invalid seg len indication\n");
  2599. goto free_event_data;
  2600. }
  2601. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2602. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2603. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2604. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2605. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2606. goto free_event_data;
  2607. }
  2608. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2609. i, ind_msg->mem_seg[i].addr,
  2610. ind_msg->mem_seg[i].size);
  2611. }
  2612. }
  2613. if (ind_msg->file_name_valid)
  2614. strlcpy(event_data->file_name, ind_msg->file_name,
  2615. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2616. if (ind_msg->source == 1) {
  2617. if (!ind_msg->file_name_valid)
  2618. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2619. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2620. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2621. 0, event_data);
  2622. } else {
  2623. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2624. if (!ind_msg->file_name_valid)
  2625. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2626. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2627. } else {
  2628. if (!ind_msg->file_name_valid)
  2629. strlcpy(event_data->file_name, "fw_mem_dump",
  2630. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2631. }
  2632. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2633. 0, event_data);
  2634. }
  2635. return;
  2636. free_event_data:
  2637. kfree(event_data);
  2638. }
  2639. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2640. struct sockaddr_qrtr *sq,
  2641. struct qmi_txn *txn,
  2642. const void *data)
  2643. {
  2644. struct cnss_plat_data *plat_priv =
  2645. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2646. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2647. 0, NULL);
  2648. }
  2649. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2650. struct sockaddr_qrtr *sq,
  2651. struct qmi_txn *txn,
  2652. const void *data)
  2653. {
  2654. struct cnss_plat_data *plat_priv =
  2655. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2656. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2657. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2658. if (!txn) {
  2659. cnss_pr_err("Spurious indication\n");
  2660. return;
  2661. }
  2662. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2663. ind_msg->data_len, ind_msg->type,
  2664. ind_msg->is_last, ind_msg->seq_no);
  2665. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2666. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2667. (void *)ind_msg->data,
  2668. ind_msg->data_len);
  2669. }
  2670. static void cnss_wlfw_driver_async_data_ind_cb(struct qmi_handle *qmi_wlfw,
  2671. struct sockaddr_qrtr *sq,
  2672. struct qmi_txn *txn,
  2673. const void *data)
  2674. {
  2675. struct cnss_plat_data *plat_priv =
  2676. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2677. const struct wlfw_driver_async_data_ind_msg_v01 *ind_msg = data;
  2678. cnss_pr_buf("Received QMI WLFW driver async data indication\n");
  2679. if (!txn) {
  2680. cnss_pr_err("Spurious indication\n");
  2681. return;
  2682. }
  2683. cnss_pr_buf("Extract message with event length: %d, type: %d\n",
  2684. ind_msg->data_len, ind_msg->type);
  2685. if (plat_priv->get_driver_async_data_ctx &&
  2686. plat_priv->get_driver_async_data_cb)
  2687. plat_priv->get_driver_async_data_cb(
  2688. plat_priv->get_driver_async_data_ctx, ind_msg->type,
  2689. (void *)ind_msg->data, ind_msg->data_len);
  2690. }
  2691. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2692. (struct cnss_plat_data *plat_priv,
  2693. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2694. {
  2695. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2696. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2697. struct qmi_txn txn;
  2698. int ret = 0;
  2699. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2700. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2701. return -EINVAL;
  2702. }
  2703. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2704. if (!req)
  2705. return -ENOMEM;
  2706. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2707. if (!resp) {
  2708. kfree(req);
  2709. return -ENOMEM;
  2710. }
  2711. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2712. req->twt_sta_start = ind_msg->twt_sta_start;
  2713. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2714. req->twt_sta_int = ind_msg->twt_sta_int;
  2715. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2716. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2717. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2718. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2719. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2720. req->twt_sta_dl = req->twt_sta_dl;
  2721. req->twt_sta_config_changed_valid =
  2722. ind_msg->twt_sta_config_changed_valid;
  2723. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2724. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2725. plat_priv->driver_state);
  2726. ret =
  2727. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2728. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2729. resp);
  2730. if (ret < 0) {
  2731. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2732. ret);
  2733. goto out;
  2734. }
  2735. ret =
  2736. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2737. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2738. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2739. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2740. if (ret < 0) {
  2741. qmi_txn_cancel(&txn);
  2742. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2743. goto out;
  2744. }
  2745. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2746. if (ret < 0) {
  2747. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2748. goto out;
  2749. }
  2750. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2751. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2752. resp->resp.result, resp->resp.error);
  2753. ret = -resp->resp.result;
  2754. goto out;
  2755. }
  2756. ret = 0;
  2757. out:
  2758. kfree(req);
  2759. kfree(resp);
  2760. return ret;
  2761. }
  2762. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2763. void *data)
  2764. {
  2765. int ret;
  2766. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2767. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2768. kfree(data);
  2769. return ret;
  2770. }
  2771. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2772. struct sockaddr_qrtr *sq,
  2773. struct qmi_txn *txn,
  2774. const void *data)
  2775. {
  2776. struct cnss_plat_data *plat_priv =
  2777. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2778. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2779. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2780. if (!txn) {
  2781. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2782. return;
  2783. }
  2784. if (!ind_msg) {
  2785. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2786. return;
  2787. }
  2788. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2789. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2790. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2791. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2792. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2793. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2794. ind_msg->twt_sta_config_changed_valid,
  2795. ind_msg->twt_sta_config_changed);
  2796. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2797. if (!event_data)
  2798. return;
  2799. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2800. event_data);
  2801. }
  2802. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2803. {
  2804. .type = QMI_INDICATION,
  2805. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2806. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2807. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2808. .fn = cnss_wlfw_request_mem_ind_cb
  2809. },
  2810. {
  2811. .type = QMI_INDICATION,
  2812. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2813. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2814. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2815. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2816. },
  2817. {
  2818. .type = QMI_INDICATION,
  2819. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2820. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2821. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2822. .fn = cnss_wlfw_fw_ready_ind_cb
  2823. },
  2824. {
  2825. .type = QMI_INDICATION,
  2826. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2827. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2828. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2829. .fn = cnss_wlfw_fw_init_done_ind_cb
  2830. },
  2831. {
  2832. .type = QMI_INDICATION,
  2833. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2834. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2835. .decoded_size =
  2836. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2837. .fn = cnss_wlfw_pin_result_ind_cb
  2838. },
  2839. {
  2840. .type = QMI_INDICATION,
  2841. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2842. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2843. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2844. .fn = cnss_wlfw_cal_done_ind_cb
  2845. },
  2846. {
  2847. .type = QMI_INDICATION,
  2848. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2849. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2850. .decoded_size =
  2851. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2852. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2853. },
  2854. {
  2855. .type = QMI_INDICATION,
  2856. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2857. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2858. .decoded_size =
  2859. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2860. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2861. },
  2862. {
  2863. .type = QMI_INDICATION,
  2864. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2865. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2866. .decoded_size =
  2867. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2868. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2869. },
  2870. {
  2871. .type = QMI_INDICATION,
  2872. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2873. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2874. .decoded_size =
  2875. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2876. .fn = cnss_wlfw_respond_get_info_ind_cb
  2877. },
  2878. {
  2879. .type = QMI_INDICATION,
  2880. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2881. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2882. .decoded_size =
  2883. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2884. .fn = cnss_wlfw_process_twt_cfg_ind
  2885. },
  2886. {
  2887. .type = QMI_INDICATION,
  2888. .msg_id = QMI_WLFW_DRIVER_ASYNC_DATA_IND_V01,
  2889. .ei = wlfw_driver_async_data_ind_msg_v01_ei,
  2890. .decoded_size =
  2891. sizeof(struct wlfw_driver_async_data_ind_msg_v01),
  2892. .fn = cnss_wlfw_driver_async_data_ind_cb
  2893. },
  2894. {}
  2895. };
  2896. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2897. void *data)
  2898. {
  2899. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2900. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2901. struct sockaddr_qrtr sq = { 0 };
  2902. int ret = 0;
  2903. if (!event_data)
  2904. return -EINVAL;
  2905. sq.sq_family = AF_QIPCRTR;
  2906. sq.sq_node = event_data->node;
  2907. sq.sq_port = event_data->port;
  2908. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2909. sizeof(sq), 0);
  2910. if (ret < 0) {
  2911. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2912. goto out;
  2913. }
  2914. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2915. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2916. plat_priv->driver_state);
  2917. kfree(data);
  2918. return 0;
  2919. out:
  2920. CNSS_QMI_ASSERT();
  2921. kfree(data);
  2922. return ret;
  2923. }
  2924. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2925. {
  2926. int ret = 0;
  2927. if (!plat_priv)
  2928. return -ENODEV;
  2929. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2930. cnss_pr_err("Unexpected WLFW server arrive\n");
  2931. CNSS_ASSERT(0);
  2932. return -EINVAL;
  2933. }
  2934. cnss_ignore_qmi_failure(false);
  2935. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2936. if (ret < 0)
  2937. goto out;
  2938. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2939. if (ret < 0) {
  2940. if (ret == -EALREADY)
  2941. ret = 0;
  2942. goto out;
  2943. }
  2944. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2945. if (ret < 0)
  2946. goto out;
  2947. return 0;
  2948. out:
  2949. return ret;
  2950. }
  2951. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2952. {
  2953. int ret;
  2954. if (!plat_priv)
  2955. return -ENODEV;
  2956. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2957. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2958. plat_priv->driver_state);
  2959. cnss_qmi_deinit(plat_priv);
  2960. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2961. ret = cnss_qmi_init(plat_priv);
  2962. if (ret < 0) {
  2963. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2964. CNSS_ASSERT(0);
  2965. }
  2966. return 0;
  2967. }
  2968. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2969. struct qmi_service *service)
  2970. {
  2971. struct cnss_plat_data *plat_priv =
  2972. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2973. struct cnss_qmi_event_server_arrive_data *event_data;
  2974. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2975. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2976. plat_priv->driver_state);
  2977. return 0;
  2978. }
  2979. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2980. service->node, service->port);
  2981. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2982. if (!event_data)
  2983. return -ENOMEM;
  2984. event_data->node = service->node;
  2985. event_data->port = service->port;
  2986. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2987. 0, event_data);
  2988. return 0;
  2989. }
  2990. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2991. struct qmi_service *service)
  2992. {
  2993. struct cnss_plat_data *plat_priv =
  2994. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2995. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2996. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2997. plat_priv->driver_state);
  2998. return;
  2999. }
  3000. cnss_pr_dbg("WLFW server exiting\n");
  3001. if (plat_priv) {
  3002. cnss_ignore_qmi_failure(true);
  3003. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  3004. }
  3005. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  3006. 0, NULL);
  3007. }
  3008. static struct qmi_ops qmi_wlfw_ops = {
  3009. .new_server = wlfw_new_server,
  3010. .del_server = wlfw_del_server,
  3011. };
  3012. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  3013. {
  3014. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  3015. /* In order to support dual wlan card attach case,
  3016. * need separate qmi service instance id for each dev
  3017. */
  3018. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  3019. plat_priv->wlfw_service_instance_id != 0)
  3020. id = plat_priv->wlfw_service_instance_id;
  3021. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  3022. WLFW_SERVICE_VERS_V01, id);
  3023. }
  3024. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  3025. {
  3026. int ret = 0;
  3027. cnss_get_qrtr_info(plat_priv);
  3028. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  3029. QMI_WLFW_MAX_RECV_BUF_SIZE,
  3030. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  3031. if (ret < 0) {
  3032. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  3033. ret);
  3034. goto out;
  3035. }
  3036. ret = cnss_qmi_add_lookup(plat_priv);
  3037. if (ret < 0)
  3038. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  3039. out:
  3040. return ret;
  3041. }
  3042. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  3043. {
  3044. qmi_handle_release(&plat_priv->qmi_wlfw);
  3045. }
  3046. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  3047. {
  3048. struct dms_get_mac_address_req_msg_v01 req;
  3049. struct dms_get_mac_address_resp_msg_v01 resp;
  3050. struct qmi_txn txn;
  3051. int ret = 0;
  3052. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  3053. cnss_pr_err("DMS QMI connection not established\n");
  3054. return -EINVAL;
  3055. }
  3056. cnss_pr_dbg("Requesting DMS MAC address");
  3057. memset(&resp, 0, sizeof(resp));
  3058. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  3059. dms_get_mac_address_resp_msg_v01_ei, &resp);
  3060. if (ret < 0) {
  3061. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  3062. ret);
  3063. goto out;
  3064. }
  3065. req.device = DMS_DEVICE_MAC_WLAN_V01;
  3066. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  3067. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  3068. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  3069. dms_get_mac_address_req_msg_v01_ei, &req);
  3070. if (ret < 0) {
  3071. qmi_txn_cancel(&txn);
  3072. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  3073. ret);
  3074. goto out;
  3075. }
  3076. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  3077. if (ret < 0) {
  3078. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  3079. ret);
  3080. goto out;
  3081. }
  3082. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  3083. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  3084. resp.resp.result, resp.resp.error);
  3085. ret = -resp.resp.result;
  3086. goto out;
  3087. }
  3088. if (!resp.mac_address_valid ||
  3089. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  3090. cnss_pr_err("Invalid MAC address received from DMS\n");
  3091. plat_priv->dms.mac_valid = false;
  3092. goto out;
  3093. }
  3094. plat_priv->dms.mac_valid = true;
  3095. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  3096. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  3097. out:
  3098. return ret;
  3099. }
  3100. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  3101. unsigned int node, unsigned int port)
  3102. {
  3103. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  3104. struct sockaddr_qrtr sq = {0};
  3105. int ret = 0;
  3106. sq.sq_family = AF_QIPCRTR;
  3107. sq.sq_node = node;
  3108. sq.sq_port = port;
  3109. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  3110. sizeof(sq), 0);
  3111. if (ret < 0) {
  3112. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  3113. node, port);
  3114. goto out;
  3115. }
  3116. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3117. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  3118. plat_priv->driver_state);
  3119. out:
  3120. return ret;
  3121. }
  3122. static int dms_new_server(struct qmi_handle *qmi_dms,
  3123. struct qmi_service *service)
  3124. {
  3125. struct cnss_plat_data *plat_priv =
  3126. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3127. if (!service)
  3128. return -EINVAL;
  3129. return cnss_dms_connect_to_server(plat_priv, service->node,
  3130. service->port);
  3131. }
  3132. static void cnss_dms_server_exit_work(struct work_struct *work)
  3133. {
  3134. int ret;
  3135. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3136. cnss_dms_deinit(plat_priv);
  3137. cnss_pr_info("QMI DMS Server Exit");
  3138. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3139. ret = cnss_dms_init(plat_priv);
  3140. if (ret < 0)
  3141. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3142. }
  3143. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3144. static void dms_del_server(struct qmi_handle *qmi_dms,
  3145. struct qmi_service *service)
  3146. {
  3147. struct cnss_plat_data *plat_priv =
  3148. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3149. if (!plat_priv)
  3150. return;
  3151. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3152. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3153. plat_priv->driver_state);
  3154. return;
  3155. }
  3156. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3157. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3158. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3159. plat_priv->driver_state);
  3160. schedule_work(&cnss_dms_del_work);
  3161. }
  3162. void cnss_cancel_dms_work(void)
  3163. {
  3164. cancel_work_sync(&cnss_dms_del_work);
  3165. }
  3166. static struct qmi_ops qmi_dms_ops = {
  3167. .new_server = dms_new_server,
  3168. .del_server = dms_del_server,
  3169. };
  3170. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3171. {
  3172. int ret = 0;
  3173. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3174. &qmi_dms_ops, NULL);
  3175. if (ret < 0) {
  3176. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3177. goto out;
  3178. }
  3179. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3180. DMS_SERVICE_VERS_V01, 0);
  3181. if (ret < 0)
  3182. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3183. out:
  3184. return ret;
  3185. }
  3186. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3187. {
  3188. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3189. qmi_handle_release(&plat_priv->qmi_dms);
  3190. }
  3191. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3192. {
  3193. int ret;
  3194. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3195. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3196. struct qmi_txn txn;
  3197. if (!plat_priv)
  3198. return -ENODEV;
  3199. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3200. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3201. if (!req)
  3202. return -ENOMEM;
  3203. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3204. if (!resp) {
  3205. kfree(req);
  3206. return -ENOMEM;
  3207. }
  3208. req->antenna = plat_priv->antenna;
  3209. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3210. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3211. if (ret < 0) {
  3212. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3213. ret);
  3214. goto out;
  3215. }
  3216. ret = qmi_send_request
  3217. (&plat_priv->coex_qmi, NULL, &txn,
  3218. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3219. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3220. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3221. if (ret < 0) {
  3222. qmi_txn_cancel(&txn);
  3223. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3224. ret);
  3225. goto out;
  3226. }
  3227. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3228. if (ret < 0) {
  3229. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3230. ret);
  3231. goto out;
  3232. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3233. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3234. resp->resp.result, resp->resp.error);
  3235. ret = -resp->resp.result;
  3236. goto out;
  3237. }
  3238. if (resp->grant_valid)
  3239. plat_priv->grant = resp->grant;
  3240. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3241. kfree(resp);
  3242. kfree(req);
  3243. return 0;
  3244. out:
  3245. kfree(resp);
  3246. kfree(req);
  3247. return ret;
  3248. }
  3249. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3250. {
  3251. int ret;
  3252. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3253. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3254. struct qmi_txn txn;
  3255. if (!plat_priv)
  3256. return -ENODEV;
  3257. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3258. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3259. if (!req)
  3260. return -ENOMEM;
  3261. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3262. if (!resp) {
  3263. kfree(req);
  3264. return -ENOMEM;
  3265. }
  3266. req->antenna = plat_priv->antenna;
  3267. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3268. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3269. if (ret < 0) {
  3270. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3271. ret);
  3272. goto out;
  3273. }
  3274. ret = qmi_send_request
  3275. (&plat_priv->coex_qmi, NULL, &txn,
  3276. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3277. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3278. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3279. if (ret < 0) {
  3280. qmi_txn_cancel(&txn);
  3281. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3282. ret);
  3283. goto out;
  3284. }
  3285. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3286. if (ret < 0) {
  3287. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3288. ret);
  3289. goto out;
  3290. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3291. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3292. resp->resp.result, resp->resp.error);
  3293. ret = -resp->resp.result;
  3294. goto out;
  3295. }
  3296. kfree(resp);
  3297. kfree(req);
  3298. return 0;
  3299. out:
  3300. kfree(resp);
  3301. kfree(req);
  3302. return ret;
  3303. }
  3304. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3305. {
  3306. int ret;
  3307. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3308. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3309. u8 pcss_enabled;
  3310. if (!plat_priv)
  3311. return -ENODEV;
  3312. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3313. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3314. return 0;
  3315. }
  3316. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3317. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3318. req.restart_level_type_valid = 1;
  3319. req.restart_level_type = pcss_enabled;
  3320. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3321. wlfw_subsys_restart_level_req_msg_v01_ei,
  3322. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3323. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3324. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3325. QMI_WLFW_TIMEOUT_JF);
  3326. if (ret < 0)
  3327. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3328. return ret;
  3329. }
  3330. static int coex_new_server(struct qmi_handle *qmi,
  3331. struct qmi_service *service)
  3332. {
  3333. struct cnss_plat_data *plat_priv =
  3334. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3335. struct sockaddr_qrtr sq = { 0 };
  3336. int ret = 0;
  3337. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3338. service->node, service->port);
  3339. sq.sq_family = AF_QIPCRTR;
  3340. sq.sq_node = service->node;
  3341. sq.sq_port = service->port;
  3342. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3343. if (ret < 0) {
  3344. cnss_pr_err("Fail to connect to remote service port\n");
  3345. return ret;
  3346. }
  3347. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3348. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3349. plat_priv->driver_state);
  3350. return 0;
  3351. }
  3352. static void coex_del_server(struct qmi_handle *qmi,
  3353. struct qmi_service *service)
  3354. {
  3355. struct cnss_plat_data *plat_priv =
  3356. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3357. cnss_pr_dbg("COEX server exit\n");
  3358. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3359. }
  3360. static struct qmi_ops coex_qmi_ops = {
  3361. .new_server = coex_new_server,
  3362. .del_server = coex_del_server,
  3363. };
  3364. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3365. { int ret;
  3366. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3367. COEX_SERVICE_MAX_MSG_LEN,
  3368. &coex_qmi_ops, NULL);
  3369. if (ret < 0)
  3370. return ret;
  3371. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3372. COEX_SERVICE_VERS_V01, 0);
  3373. return ret;
  3374. }
  3375. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3376. {
  3377. qmi_handle_release(&plat_priv->coex_qmi);
  3378. }
  3379. /* IMS Service */
  3380. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3381. {
  3382. int ret;
  3383. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3384. struct qmi_txn *txn;
  3385. if (!plat_priv)
  3386. return -ENODEV;
  3387. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3388. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3389. if (!req)
  3390. return -ENOMEM;
  3391. req->wfc_call_status_valid = 1;
  3392. req->wfc_call_status = 1;
  3393. txn = &plat_priv->txn;
  3394. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3395. if (ret < 0) {
  3396. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3397. ret);
  3398. goto out;
  3399. }
  3400. ret = qmi_send_request
  3401. (&plat_priv->ims_qmi, NULL, txn,
  3402. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3403. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3404. ims_private_service_subscribe_ind_req_msg_v01_ei, req);
  3405. if (ret < 0) {
  3406. qmi_txn_cancel(txn);
  3407. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3408. ret);
  3409. goto out;
  3410. }
  3411. kfree(req);
  3412. return 0;
  3413. out:
  3414. kfree(req);
  3415. return ret;
  3416. }
  3417. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3418. struct sockaddr_qrtr *sq,
  3419. struct qmi_txn *txn,
  3420. const void *data)
  3421. {
  3422. const
  3423. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3424. data;
  3425. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3426. if (!txn) {
  3427. cnss_pr_err("spurious response\n");
  3428. return;
  3429. }
  3430. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3431. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3432. resp->resp.result, resp->resp.error);
  3433. txn->result = -resp->resp.result;
  3434. }
  3435. }
  3436. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3437. void *data)
  3438. {
  3439. int ret;
  3440. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3441. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3442. kfree(data);
  3443. return ret;
  3444. }
  3445. static void
  3446. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3447. struct sockaddr_qrtr *sq,
  3448. struct qmi_txn *txn, const void *data)
  3449. {
  3450. struct cnss_plat_data *plat_priv =
  3451. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3452. const
  3453. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3454. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3455. if (!txn) {
  3456. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3457. return;
  3458. }
  3459. if (!ind_msg) {
  3460. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3461. return;
  3462. }
  3463. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3464. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3465. ind_msg->all_wfc_calls_held,
  3466. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3467. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3468. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3469. ind_msg->media_quality_valid, ind_msg->media_quality);
  3470. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3471. if (!event_data)
  3472. return;
  3473. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3474. 0, event_data);
  3475. }
  3476. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3477. {
  3478. .type = QMI_RESPONSE,
  3479. .msg_id =
  3480. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3481. .ei =
  3482. ims_private_service_subscribe_ind_rsp_msg_v01_ei,
  3483. .decoded_size = sizeof(struct
  3484. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3485. .fn = ims_subscribe_for_indication_resp_cb
  3486. },
  3487. {
  3488. .type = QMI_INDICATION,
  3489. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3490. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3491. .decoded_size =
  3492. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3493. .fn = cnss_ims_process_wfc_call_ind_cb
  3494. },
  3495. {}
  3496. };
  3497. static int ims_new_server(struct qmi_handle *qmi,
  3498. struct qmi_service *service)
  3499. {
  3500. struct cnss_plat_data *plat_priv =
  3501. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3502. struct sockaddr_qrtr sq = { 0 };
  3503. int ret = 0;
  3504. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3505. service->node, service->port);
  3506. sq.sq_family = AF_QIPCRTR;
  3507. sq.sq_node = service->node;
  3508. sq.sq_port = service->port;
  3509. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3510. if (ret < 0) {
  3511. cnss_pr_err("Fail to connect to remote service port\n");
  3512. return ret;
  3513. }
  3514. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3515. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3516. plat_priv->driver_state);
  3517. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3518. return ret;
  3519. }
  3520. static void ims_del_server(struct qmi_handle *qmi,
  3521. struct qmi_service *service)
  3522. {
  3523. struct cnss_plat_data *plat_priv =
  3524. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3525. cnss_pr_dbg("IMS server exit\n");
  3526. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3527. }
  3528. static struct qmi_ops ims_qmi_ops = {
  3529. .new_server = ims_new_server,
  3530. .del_server = ims_del_server,
  3531. };
  3532. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3533. { int ret;
  3534. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3535. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3536. &ims_qmi_ops, qmi_ims_msg_handlers);
  3537. if (ret < 0)
  3538. return ret;
  3539. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3540. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3541. return ret;
  3542. }
  3543. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3544. {
  3545. qmi_handle_release(&plat_priv->ims_qmi);
  3546. }