bus.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "bus.h"
  7. #include "debug.h"
  8. #include "pci.h"
  9. enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev)
  10. {
  11. if (!dev)
  12. return CNSS_BUS_NONE;
  13. if (!dev->bus)
  14. return CNSS_BUS_NONE;
  15. if (memcmp(dev->bus->name, "pci", 3) == 0)
  16. return CNSS_BUS_PCI;
  17. else
  18. return CNSS_BUS_NONE;
  19. }
  20. enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv)
  21. {
  22. int ret;
  23. struct device *dev;
  24. u32 bus_type_dt = CNSS_BUS_NONE;
  25. if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
  26. dev = &plat_priv->plat_dev->dev;
  27. ret = of_property_read_u32(dev->of_node, "qcom,bus-type",
  28. &bus_type_dt);
  29. if (!ret)
  30. if (bus_type_dt < CNSS_BUS_MAX)
  31. cnss_pr_dbg("Got bus type[%u] from dt\n",
  32. bus_type_dt);
  33. else
  34. bus_type_dt = CNSS_BUS_NONE;
  35. else
  36. cnss_pr_err("No bus type for multi-exchg dt\n");
  37. return bus_type_dt;
  38. }
  39. switch (plat_priv->device_id) {
  40. case QCA6174_DEVICE_ID:
  41. case QCA6290_DEVICE_ID:
  42. case QCA6390_DEVICE_ID:
  43. case QCN7605_DEVICE_ID:
  44. case QCA6490_DEVICE_ID:
  45. case KIWI_DEVICE_ID:
  46. case MANGO_DEVICE_ID:
  47. case PEACH_DEVICE_ID:
  48. return CNSS_BUS_PCI;
  49. default:
  50. cnss_pr_err("Unknown device_id: 0x%lx\n", plat_priv->device_id);
  51. return CNSS_BUS_NONE;
  52. }
  53. }
  54. void *cnss_bus_dev_to_bus_priv(struct device *dev)
  55. {
  56. if (!dev)
  57. return NULL;
  58. switch (cnss_get_dev_bus_type(dev)) {
  59. case CNSS_BUS_PCI:
  60. return cnss_get_pci_priv(to_pci_dev(dev));
  61. default:
  62. return NULL;
  63. }
  64. }
  65. struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev)
  66. {
  67. void *bus_priv;
  68. if (!dev)
  69. return cnss_get_plat_priv(NULL);
  70. bus_priv = cnss_bus_dev_to_bus_priv(dev);
  71. if (!bus_priv)
  72. return NULL;
  73. switch (cnss_get_dev_bus_type(dev)) {
  74. case CNSS_BUS_PCI:
  75. return cnss_pci_priv_to_plat_priv(bus_priv);
  76. default:
  77. return NULL;
  78. }
  79. }
  80. int cnss_bus_init(struct cnss_plat_data *plat_priv)
  81. {
  82. if (!plat_priv)
  83. return -ENODEV;
  84. switch (plat_priv->bus_type) {
  85. case CNSS_BUS_PCI:
  86. return cnss_pci_init(plat_priv);
  87. default:
  88. cnss_pr_err("Unsupported bus type: %d\n",
  89. plat_priv->bus_type);
  90. return -EINVAL;
  91. }
  92. }
  93. void cnss_bus_deinit(struct cnss_plat_data *plat_priv)
  94. {
  95. if (!plat_priv)
  96. return;
  97. switch (plat_priv->bus_type) {
  98. case CNSS_BUS_PCI:
  99. return cnss_pci_deinit(plat_priv);
  100. default:
  101. cnss_pr_err("Unsupported bus type: %d\n",
  102. plat_priv->bus_type);
  103. return;
  104. }
  105. }
  106. void cnss_bus_add_fw_prefix_name(struct cnss_plat_data *plat_priv,
  107. char *prefix_name, char *name)
  108. {
  109. if (!plat_priv)
  110. return;
  111. switch (plat_priv->bus_type) {
  112. case CNSS_BUS_PCI:
  113. return cnss_pci_add_fw_prefix_name(plat_priv->bus_priv,
  114. prefix_name, name);
  115. default:
  116. cnss_pr_err("Unsupported bus type: %d\n",
  117. plat_priv->bus_type);
  118. return;
  119. }
  120. }
  121. int cnss_bus_load_tme_patch(struct cnss_plat_data *plat_priv)
  122. {
  123. if (!plat_priv)
  124. return -ENODEV;
  125. switch (plat_priv->bus_type) {
  126. case CNSS_BUS_PCI:
  127. return cnss_pci_load_tme_patch(plat_priv->bus_priv);
  128. default:
  129. cnss_pr_err("Unsupported bus type: %d\n",
  130. plat_priv->bus_type);
  131. return -EINVAL;
  132. }
  133. }
  134. int cnss_bus_load_tme_opt_file(struct cnss_plat_data *plat_priv,
  135. enum wlfw_tme_lite_file_type_v01 file)
  136. {
  137. if (!plat_priv)
  138. return -ENODEV;
  139. switch (plat_priv->bus_type) {
  140. case CNSS_BUS_PCI:
  141. return cnss_pci_load_tme_opt_file(plat_priv->bus_priv, file);
  142. default:
  143. cnss_pr_err("Unsupported bus type: %d\n",
  144. plat_priv->bus_type);
  145. return -EINVAL;
  146. }
  147. }
  148. int cnss_bus_load_m3(struct cnss_plat_data *plat_priv)
  149. {
  150. if (!plat_priv)
  151. return -ENODEV;
  152. switch (plat_priv->bus_type) {
  153. case CNSS_BUS_PCI:
  154. return cnss_pci_load_m3(plat_priv->bus_priv);
  155. default:
  156. cnss_pr_err("Unsupported bus type: %d\n",
  157. plat_priv->bus_type);
  158. return -EINVAL;
  159. }
  160. }
  161. int cnss_bus_load_aux(struct cnss_plat_data *plat_priv)
  162. {
  163. if (!plat_priv)
  164. return -ENODEV;
  165. switch (plat_priv->bus_type) {
  166. case CNSS_BUS_PCI:
  167. return cnss_pci_load_aux(plat_priv->bus_priv);
  168. default:
  169. cnss_pr_err("Unsupported bus type: %d\n",
  170. plat_priv->bus_type);
  171. return -EINVAL;
  172. }
  173. }
  174. int cnss_bus_handle_dev_sol_irq(struct cnss_plat_data *plat_priv)
  175. {
  176. if (!plat_priv)
  177. return -ENODEV;
  178. switch (plat_priv->bus_type) {
  179. case CNSS_BUS_PCI:
  180. return cnss_pci_handle_dev_sol_irq(plat_priv->bus_priv);
  181. default:
  182. cnss_pr_err("Unsupported bus type: %d\n",
  183. plat_priv->bus_type);
  184. return -EINVAL;
  185. }
  186. }
  187. int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv)
  188. {
  189. if (!plat_priv)
  190. return -ENODEV;
  191. switch (plat_priv->bus_type) {
  192. case CNSS_BUS_PCI:
  193. return cnss_pci_alloc_fw_mem(plat_priv->bus_priv);
  194. default:
  195. cnss_pr_err("Unsupported bus type: %d\n",
  196. plat_priv->bus_type);
  197. return -EINVAL;
  198. }
  199. }
  200. int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv)
  201. {
  202. if (!plat_priv)
  203. return -ENODEV;
  204. switch (plat_priv->bus_type) {
  205. case CNSS_BUS_PCI:
  206. return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv);
  207. default:
  208. cnss_pr_err("Unsupported bus type: %d\n",
  209. plat_priv->bus_type);
  210. return -EINVAL;
  211. }
  212. }
  213. void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv)
  214. {
  215. if (!plat_priv)
  216. return;
  217. switch (plat_priv->bus_type) {
  218. case CNSS_BUS_PCI:
  219. cnss_pci_free_qdss_mem(plat_priv->bus_priv);
  220. return;
  221. default:
  222. cnss_pr_err("Unsupported bus type: %d\n",
  223. plat_priv->bus_type);
  224. return;
  225. }
  226. }
  227. u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv)
  228. {
  229. if (!plat_priv)
  230. return -ENODEV;
  231. switch (plat_priv->bus_type) {
  232. case CNSS_BUS_PCI:
  233. return cnss_pci_get_wake_msi(plat_priv->bus_priv);
  234. default:
  235. cnss_pr_err("Unsupported bus type: %d\n",
  236. plat_priv->bus_type);
  237. return -EINVAL;
  238. }
  239. }
  240. int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv)
  241. {
  242. if (!plat_priv)
  243. return -ENODEV;
  244. switch (plat_priv->bus_type) {
  245. case CNSS_BUS_PCI:
  246. return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv);
  247. default:
  248. cnss_pr_err("Unsupported bus type: %d\n",
  249. plat_priv->bus_type);
  250. return -EINVAL;
  251. }
  252. }
  253. int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv)
  254. {
  255. if (!plat_priv)
  256. return -ENODEV;
  257. switch (plat_priv->bus_type) {
  258. case CNSS_BUS_PCI:
  259. return cnss_pci_qmi_send_get(plat_priv->bus_priv);
  260. default:
  261. cnss_pr_err("Unsupported bus type: %d\n",
  262. plat_priv->bus_type);
  263. return -EINVAL;
  264. }
  265. }
  266. int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv)
  267. {
  268. if (!plat_priv)
  269. return -ENODEV;
  270. switch (plat_priv->bus_type) {
  271. case CNSS_BUS_PCI:
  272. return cnss_pci_qmi_send_put(plat_priv->bus_priv);
  273. default:
  274. cnss_pr_err("Unsupported bus type: %d\n",
  275. plat_priv->bus_type);
  276. return -EINVAL;
  277. }
  278. }
  279. void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t)
  280. {
  281. struct cnss_plat_data *plat_priv =
  282. from_timer(plat_priv, t, fw_boot_timer);
  283. if (!plat_priv)
  284. return;
  285. switch (plat_priv->bus_type) {
  286. case CNSS_BUS_PCI:
  287. return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv);
  288. default:
  289. cnss_pr_err("Unsupported bus type: %d\n",
  290. plat_priv->bus_type);
  291. return;
  292. }
  293. }
  294. void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic)
  295. {
  296. if (!plat_priv)
  297. return;
  298. switch (plat_priv->bus_type) {
  299. case CNSS_BUS_PCI:
  300. return cnss_pci_collect_dump_info(plat_priv->bus_priv,
  301. in_panic);
  302. default:
  303. cnss_pr_err("Unsupported bus type: %d\n",
  304. plat_priv->bus_type);
  305. return;
  306. }
  307. }
  308. void cnss_bus_device_crashed(struct cnss_plat_data *plat_priv)
  309. {
  310. if (!plat_priv)
  311. return;
  312. switch (plat_priv->bus_type) {
  313. case CNSS_BUS_PCI:
  314. return cnss_pci_device_crashed(plat_priv->bus_priv);
  315. default:
  316. cnss_pr_err("Unsupported bus type: %d\n",
  317. plat_priv->bus_type);
  318. return;
  319. }
  320. }
  321. int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv)
  322. {
  323. if (!plat_priv)
  324. return -ENODEV;
  325. switch (plat_priv->bus_type) {
  326. case CNSS_BUS_PCI:
  327. return cnss_pci_call_driver_probe(plat_priv->bus_priv);
  328. default:
  329. cnss_pr_err("Unsupported bus type: %d\n",
  330. plat_priv->bus_type);
  331. return -EINVAL;
  332. }
  333. }
  334. int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv)
  335. {
  336. if (!plat_priv)
  337. return -ENODEV;
  338. switch (plat_priv->bus_type) {
  339. case CNSS_BUS_PCI:
  340. return cnss_pci_call_driver_remove(plat_priv->bus_priv);
  341. default:
  342. cnss_pr_err("Unsupported bus type: %d\n",
  343. plat_priv->bus_type);
  344. return -EINVAL;
  345. }
  346. }
  347. int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv)
  348. {
  349. if (!plat_priv)
  350. return -ENODEV;
  351. switch (plat_priv->bus_type) {
  352. case CNSS_BUS_PCI:
  353. return cnss_pci_dev_powerup(plat_priv->bus_priv);
  354. default:
  355. cnss_pr_err("Unsupported bus type: %d\n",
  356. plat_priv->bus_type);
  357. return -EINVAL;
  358. }
  359. }
  360. int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv)
  361. {
  362. if (!plat_priv)
  363. return -ENODEV;
  364. switch (plat_priv->bus_type) {
  365. case CNSS_BUS_PCI:
  366. return cnss_pci_dev_shutdown(plat_priv->bus_priv);
  367. default:
  368. cnss_pr_err("Unsupported bus type: %d\n",
  369. plat_priv->bus_type);
  370. return -EINVAL;
  371. }
  372. }
  373. int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv)
  374. {
  375. if (!plat_priv)
  376. return -ENODEV;
  377. switch (plat_priv->bus_type) {
  378. case CNSS_BUS_PCI:
  379. return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv);
  380. default:
  381. cnss_pr_err("Unsupported bus type: %d\n",
  382. plat_priv->bus_type);
  383. return -EINVAL;
  384. }
  385. }
  386. int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv)
  387. {
  388. if (!plat_priv)
  389. return -ENODEV;
  390. switch (plat_priv->bus_type) {
  391. case CNSS_BUS_PCI:
  392. return cnss_pci_dev_ramdump(plat_priv->bus_priv);
  393. default:
  394. cnss_pr_err("Unsupported bus type: %d\n",
  395. plat_priv->bus_type);
  396. return -EINVAL;
  397. }
  398. }
  399. int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data)
  400. {
  401. if (!plat_priv)
  402. return -ENODEV;
  403. switch (plat_priv->bus_type) {
  404. case CNSS_BUS_PCI:
  405. return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data);
  406. default:
  407. cnss_pr_err("Unsupported bus type: %d\n",
  408. plat_priv->bus_type);
  409. return -EINVAL;
  410. }
  411. }
  412. int cnss_bus_runtime_pm_get_sync(struct cnss_plat_data *plat_priv)
  413. {
  414. if (!plat_priv)
  415. return -ENODEV;
  416. switch (plat_priv->bus_type) {
  417. case CNSS_BUS_PCI:
  418. return cnss_pci_pm_runtime_get_sync(plat_priv->bus_priv, RTPM_ID_CNSS);
  419. default:
  420. cnss_pr_err("Unsupported bus type: %d\n",
  421. plat_priv->bus_type);
  422. return -EINVAL;
  423. }
  424. }
  425. void cnss_bus_runtime_pm_put(struct cnss_plat_data *plat_priv)
  426. {
  427. if (!plat_priv)
  428. return;
  429. switch (plat_priv->bus_type) {
  430. case CNSS_BUS_PCI:
  431. cnss_pci_pm_runtime_mark_last_busy(plat_priv->bus_priv);
  432. cnss_pci_pm_runtime_put_autosuspend(plat_priv->bus_priv, RTPM_ID_CNSS);
  433. break;
  434. default:
  435. cnss_pr_err("Unsupported bus type: %d\n",
  436. plat_priv->bus_type);
  437. }
  438. }
  439. int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv)
  440. {
  441. if (!plat_priv)
  442. return -ENODEV;
  443. switch (plat_priv->bus_type) {
  444. case CNSS_BUS_PCI:
  445. return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv);
  446. default:
  447. cnss_pr_err("Unsupported bus type: %d\n",
  448. plat_priv->bus_type);
  449. return -EINVAL;
  450. }
  451. }
  452. int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv,
  453. int modem_current_status)
  454. {
  455. if (!plat_priv)
  456. return -ENODEV;
  457. switch (plat_priv->bus_type) {
  458. case CNSS_BUS_PCI:
  459. return cnss_pci_call_driver_modem_status(plat_priv->bus_priv,
  460. modem_current_status);
  461. default:
  462. cnss_pr_err("Unsupported bus type: %d\n",
  463. plat_priv->bus_type);
  464. return -EINVAL;
  465. }
  466. }
  467. int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
  468. enum cnss_driver_status status)
  469. {
  470. if (!plat_priv)
  471. return -ENODEV;
  472. switch (plat_priv->bus_type) {
  473. case CNSS_BUS_PCI:
  474. return cnss_pci_update_status(plat_priv->bus_priv, status);
  475. default:
  476. cnss_pr_err("Unsupported bus type: %d\n",
  477. plat_priv->bus_type);
  478. return -EINVAL;
  479. }
  480. }
  481. int cnss_bus_update_uevent(struct cnss_plat_data *plat_priv,
  482. enum cnss_driver_status status, void *data)
  483. {
  484. if (!plat_priv)
  485. return -ENODEV;
  486. switch (plat_priv->bus_type) {
  487. case CNSS_BUS_PCI:
  488. return cnss_pci_call_driver_uevent(plat_priv->bus_priv,
  489. status, data);
  490. default:
  491. cnss_pr_err("Unsupported bus type: %d\n",
  492. plat_priv->bus_type);
  493. return -EINVAL;
  494. }
  495. }
  496. int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv)
  497. {
  498. if (!plat_priv)
  499. return -ENODEV;
  500. switch (plat_priv->bus_type) {
  501. case CNSS_BUS_PCI:
  502. return cnss_pcie_is_device_down(plat_priv->bus_priv);
  503. default:
  504. cnss_pr_dbg("Unsupported bus type: %d\n",
  505. plat_priv->bus_type);
  506. return 0;
  507. }
  508. }
  509. int cnss_bus_shutdown_cleanup(struct cnss_plat_data *plat_priv)
  510. {
  511. if (!plat_priv)
  512. return -ENODEV;
  513. switch (plat_priv->bus_type) {
  514. case CNSS_BUS_PCI:
  515. return cnss_pci_shutdown_cleanup(plat_priv->bus_priv);
  516. default:
  517. cnss_pr_dbg("Unsupported bus type: %d\n",
  518. plat_priv->bus_type);
  519. return 0;
  520. }
  521. }
  522. int cnss_bus_check_link_status(struct cnss_plat_data *plat_priv)
  523. {
  524. if (!plat_priv)
  525. return -ENODEV;
  526. switch (plat_priv->bus_type) {
  527. case CNSS_BUS_PCI:
  528. return cnss_pci_check_link_status(plat_priv->bus_priv);
  529. default:
  530. cnss_pr_dbg("Unsupported bus type: %d\n",
  531. plat_priv->bus_type);
  532. return 0;
  533. }
  534. }
  535. int cnss_bus_recover_link_down(struct cnss_plat_data *plat_priv)
  536. {
  537. if (!plat_priv)
  538. return -ENODEV;
  539. switch (plat_priv->bus_type) {
  540. case CNSS_BUS_PCI:
  541. return cnss_pci_recover_link_down(plat_priv->bus_priv);
  542. default:
  543. cnss_pr_dbg("Unsupported bus type: %d\n",
  544. plat_priv->bus_type);
  545. return -EINVAL;
  546. }
  547. }
  548. int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
  549. u32 *val, bool raw_access)
  550. {
  551. if (!plat_priv)
  552. return -ENODEV;
  553. switch (plat_priv->bus_type) {
  554. case CNSS_BUS_PCI:
  555. return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset,
  556. val, raw_access);
  557. default:
  558. cnss_pr_dbg("Unsupported bus type: %d\n",
  559. plat_priv->bus_type);
  560. return 0;
  561. }
  562. }
  563. int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
  564. u32 val, bool raw_access)
  565. {
  566. if (!plat_priv)
  567. return -ENODEV;
  568. switch (plat_priv->bus_type) {
  569. case CNSS_BUS_PCI:
  570. return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset,
  571. val, raw_access);
  572. default:
  573. cnss_pr_dbg("Unsupported bus type: %d\n",
  574. plat_priv->bus_type);
  575. return 0;
  576. }
  577. }
  578. int cnss_bus_get_iova(struct cnss_plat_data *plat_priv, u64 *addr, u64 *size)
  579. {
  580. if (!plat_priv)
  581. return -ENODEV;
  582. switch (plat_priv->bus_type) {
  583. case CNSS_BUS_PCI:
  584. return cnss_pci_get_iova(plat_priv->bus_priv, addr, size);
  585. default:
  586. cnss_pr_err("Unsupported bus type: %d\n",
  587. plat_priv->bus_type);
  588. return -EINVAL;
  589. }
  590. }
  591. int cnss_bus_get_iova_ipa(struct cnss_plat_data *plat_priv, u64 *addr,
  592. u64 *size)
  593. {
  594. if (!plat_priv)
  595. return -ENODEV;
  596. switch (plat_priv->bus_type) {
  597. case CNSS_BUS_PCI:
  598. return cnss_pci_get_iova_ipa(plat_priv->bus_priv, addr, size);
  599. default:
  600. cnss_pr_err("Unsupported bus type: %d\n",
  601. plat_priv->bus_type);
  602. return -EINVAL;
  603. }
  604. }
  605. bool cnss_bus_is_smmu_s1_enabled(struct cnss_plat_data *plat_priv)
  606. {
  607. if (!plat_priv)
  608. return false;
  609. switch (plat_priv->bus_type) {
  610. case CNSS_BUS_PCI:
  611. return cnss_pci_is_smmu_s1_enabled(plat_priv->bus_priv);
  612. default:
  613. cnss_pr_err("Unsupported bus type: %d\n",
  614. plat_priv->bus_type);
  615. return false;
  616. }
  617. }
  618. int cnss_bus_update_time_sync_period(struct cnss_plat_data *plat_priv,
  619. unsigned int time_sync_period)
  620. {
  621. if (!plat_priv)
  622. return -ENODEV;
  623. switch (plat_priv->bus_type) {
  624. case CNSS_BUS_PCI:
  625. return cnss_pci_update_time_sync_period(plat_priv->bus_priv,
  626. time_sync_period);
  627. default:
  628. cnss_pr_err("Unsupported bus type: %d\n",
  629. plat_priv->bus_type);
  630. return -EINVAL;
  631. }
  632. }
  633. int cnss_bus_set_therm_cdev_state(struct cnss_plat_data *plat_priv,
  634. unsigned long thermal_state,
  635. int tcdev_id)
  636. {
  637. if (!plat_priv)
  638. return -ENODEV;
  639. switch (plat_priv->bus_type) {
  640. case CNSS_BUS_PCI:
  641. return cnss_pci_set_therm_cdev_state(plat_priv->bus_priv,
  642. thermal_state,
  643. tcdev_id);
  644. default:
  645. cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type);
  646. return -EINVAL;
  647. }
  648. }
  649. int cnss_bus_get_msi_assignment(struct cnss_plat_data *plat_priv,
  650. char *msi_name,
  651. int *num_vectors,
  652. u32 *user_base_data,
  653. u32 *base_vector)
  654. {
  655. if (!plat_priv)
  656. return -ENODEV;
  657. switch (plat_priv->bus_type) {
  658. case CNSS_BUS_PCI:
  659. return cnss_pci_get_user_msi_assignment(plat_priv->bus_priv,
  660. msi_name,
  661. num_vectors,
  662. user_base_data,
  663. base_vector);
  664. default:
  665. cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type);
  666. return -EINVAL;
  667. }
  668. }
  669. #if IS_ENABLED(CONFIG_MHI_BUS_MISC)
  670. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *plat_priv)
  671. {
  672. struct cnss_pci_data *pci_priv;
  673. pci_priv = plat_priv->bus_priv;
  674. if (!pci_priv) {
  675. cnss_pr_err("mhi satellite could not be disabled since pci_priv is NULL\n");
  676. return;
  677. }
  678. switch (plat_priv->bus_type) {
  679. case CNSS_BUS_PCI:
  680. /* MHI satellite configuration is only for KIWI V2 and
  681. * that too only in DRV mode.
  682. */
  683. if (plat_priv->device_id == KIWI_DEVICE_ID &&
  684. plat_priv->device_version.major_version == FW_V2_NUMBER) {
  685. cnss_pr_dbg("Remove MHI satellite configuration\n");
  686. return cnss_mhi_controller_set_base(pci_priv, 0);
  687. }
  688. break;
  689. default:
  690. cnss_pr_dbg("Unsupported bus type: %d, ignore disable mhi satellite cfg\n",
  691. plat_priv->bus_type);
  692. return;
  693. }
  694. return;
  695. }
  696. #else
  697. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *pci_priv)
  698. {
  699. }
  700. #endif