In current case when RRI on DDR feature is enabled then host
programs CE control register, but there is chance of F.W also
programming the CE control register around same time this leads
to race and chance of either host/F.W value getting over written.
So to avoid this while programming the CE control register for
RRI on DDR enablement, update it with F.W programming value also
i.e DMA length. So if incase register value over written due to
race proper value will be updated to register either by host/F.W.
Change-Id: I2560c74726b21128d1cd50805d987fda1b2a1230
CRs-Fixed: 3561689
b965b762b1