dp_umac_reset.h 12 KB

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  1. /*
  2. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _DP_UMAC_RESET_H_
  17. #define _DP_UMAC_RESET_H_
  18. #include <qdf_types.h>
  19. struct dp_soc;
  20. /**
  21. * enum umac_reset_action - Actions supported by the UMAC reset
  22. * @UMAC_RESET_ACTION_NONE: No action
  23. * @UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY: Trigger umac recovery
  24. * @UMAC_RESET_ACTION_DO_PRE_RESET: DO_PRE_RESET
  25. * @UMAC_RESET_ACTION_DO_POST_RESET_START: DO_POST_RESET_START
  26. * @UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE: DO_POST_RESET_COMPLETE
  27. * @UMAC_RESET_ACTION_ABORT: Abort the current Umac reset session
  28. * @UMAC_RESET_ACTION_MAX: Maximum actions
  29. */
  30. enum umac_reset_action {
  31. UMAC_RESET_ACTION_NONE,
  32. UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY,
  33. UMAC_RESET_ACTION_DO_PRE_RESET,
  34. UMAC_RESET_ACTION_DO_POST_RESET_START,
  35. UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE,
  36. UMAC_RESET_ACTION_ABORT,
  37. UMAC_RESET_ACTION_MAX
  38. };
  39. #ifdef DP_UMAC_HW_RESET_SUPPORT
  40. #define dp_umac_reset_alert(params...) \
  41. QDF_TRACE_FATAL(QDF_MODULE_ID_DP_UMAC_RESET, params)
  42. #define dp_umac_reset_err(params...) \
  43. QDF_TRACE_ERROR(QDF_MODULE_ID_DP_UMAC_RESET, params)
  44. #define dp_umac_reset_warn(params...) \
  45. QDF_TRACE_WARN(QDF_MODULE_ID_DP_UMAC_RESET, params)
  46. #define dp_umac_reset_notice(params...) \
  47. QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params)
  48. #define dp_umac_reset_info(params...) \
  49. QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params)
  50. #define dp_umac_reset_debug(params...) \
  51. QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_UMAC_RESET, params)
  52. #define DP_UMAC_RESET_PRINT_STATS(fmt, args ...)\
  53. QDF_TRACE(QDF_MODULE_ID_DP_UMAC_RESET, QDF_TRACE_LEVEL_FATAL,\
  54. fmt, ## args)
  55. #define DP_UMAC_RESET_SHMEM_ALIGN 8
  56. #define DP_UMAC_RESET_SHMEM_MAGIC_NUM (0xDEADBEEF)
  57. /**
  58. * enum umac_reset_state - States required by the UMAC reset state machine
  59. * @UMAC_RESET_STATE_WAIT_FOR_TRIGGER: Waiting for trigger event
  60. * @UMAC_RESET_STATE_DO_TRIGGER_RECEIVED: Received the DO_TRIGGER event
  61. * @UMAC_RESET_STATE_HOST_TRIGGER_DONE: Host completed handling Trigger event
  62. * @UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET: Waiting for the DO_PRE_RESET event
  63. * @UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED: Received the DO_PRE_RESET event
  64. * @UMAC_RESET_STATE_HOST_PRE_RESET_DONE: Host has completed handling the
  65. * PRE_RESET event
  66. * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START: Waiting for the
  67. * DO_POST_RESET_START event
  68. * @UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED: Received the
  69. * DO_POST_RESET_START event
  70. * @UMAC_RESET_STATE_HOST_POST_RESET_START_DONE: Host has completed handling the
  71. * POST_RESET_START event
  72. * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE: Waiting for the
  73. * DO_POST_RESET_COMPLETE event
  74. * @UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED: Received the
  75. * DO_POST_RESET_COMPLETE event
  76. * @UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE: Host has completed handling
  77. * the DO_POST_RESET_COMPLETE event
  78. */
  79. enum umac_reset_state {
  80. UMAC_RESET_STATE_WAIT_FOR_TRIGGER = 0,
  81. UMAC_RESET_STATE_DO_TRIGGER_RECEIVED,
  82. UMAC_RESET_STATE_HOST_TRIGGER_DONE,
  83. UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET,
  84. UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED,
  85. UMAC_RESET_STATE_HOST_PRE_RESET_DONE,
  86. UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START,
  87. UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED,
  88. UMAC_RESET_STATE_HOST_POST_RESET_START_DONE,
  89. UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE,
  90. UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED,
  91. UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE,
  92. };
  93. /**
  94. * enum umac_reset_rx_event - Rx events deduced by the UMAC reset
  95. * @UMAC_RESET_RX_EVENT_NONE: No event
  96. * @UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY: ACTION_DO_TRIGGER_RECOVERY event
  97. * @UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC: ACTION_DO_TRIGGER_RECOVERY event
  98. * @UMAC_RESET_RX_EVENT_DO_PRE_RESET: DO_PRE_RESET event
  99. * @UMAC_RESET_RX_EVENT_DO_POST_RESET_START: DO_POST_RESET_START event
  100. * @UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE: DO_POST_RESET_COMPELTE event
  101. * @UMAC_RESET_RX_EVENT_ERROR: Error while processing the Rx event
  102. */
  103. enum umac_reset_rx_event {
  104. UMAC_RESET_RX_EVENT_NONE = 0x0,
  105. UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY,
  106. UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC,
  107. UMAC_RESET_RX_EVENT_DO_PRE_RESET,
  108. UMAC_RESET_RX_EVENT_DO_POST_RESET_START,
  109. UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE,
  110. UMAC_RESET_RX_EVENT_ERROR = 0xFFFFFFFF,
  111. };
  112. /**
  113. * enum umac_reset_tx_cmd: UMAC reset Tx command
  114. * @UMAC_RESET_TX_CMD_TRIGGER_DONE: TRIGGER_DONE
  115. * @UMAC_RESET_TX_CMD_PRE_RESET_DONE: PRE_RESET_DONE
  116. * @UMAC_RESET_TX_CMD_POST_RESET_START_DONE: POST_RESET_START_DONE
  117. * @UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE: POST_RESET_COMPLETE_DONE
  118. */
  119. enum umac_reset_tx_cmd {
  120. UMAC_RESET_TX_CMD_TRIGGER_DONE,
  121. UMAC_RESET_TX_CMD_PRE_RESET_DONE,
  122. UMAC_RESET_TX_CMD_POST_RESET_START_DONE,
  123. UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE,
  124. };
  125. /**
  126. * struct umac_reset_rx_actions - callbacks for handling UMAC reset actions
  127. * @cb: Array of pointers where each pointer contains callback for each UMAC
  128. * reset action for that index
  129. */
  130. struct umac_reset_rx_actions {
  131. QDF_STATUS (*cb[UMAC_RESET_ACTION_MAX])(struct dp_soc *soc);
  132. };
  133. /**
  134. * struct reset_ts - timestamps of for umac reset events for debug
  135. * @trigger_start: Umac reset trigger event timestamp
  136. * @trigger_done: Umac reset trigger done timestamp
  137. * @pre_reset_start: Umac prereset start event timestamp
  138. * @pre_reset_done: Umac prereset done timestamp
  139. * @post_reset_start: Umac postreset start event timestamp
  140. * @post_reset_done: Umac postreset done timestamp
  141. * @post_reset_complete_start: Umac postreset complete event timestamp
  142. * @post_reset_complete_done: Umac postreset complete done timestamp
  143. */
  144. struct reset_ts {
  145. uint64_t trigger_start;
  146. uint64_t trigger_done;
  147. uint64_t pre_reset_start;
  148. uint64_t pre_reset_done;
  149. uint64_t post_reset_start;
  150. uint64_t post_reset_done;
  151. uint64_t post_reset_complete_start;
  152. uint64_t post_reset_complete_done;
  153. };
  154. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  155. /**
  156. * struct dp_soc_mlo_umac_reset_ctx - UMAC reset context at mlo group level
  157. * @partner_map: Partner soc map
  158. * @request_map: Partner soc request map
  159. * @response_map: Partner soc response map
  160. * @grp_ctx_lock: lock for accessing group level umac reset context
  161. * @umac_reset_in_progress: Flag to indicate if umac reset is in progress
  162. * @is_target_recovery: Flag to indicate if this is for target recovery
  163. * @initiator_chip_id: chip id of the Umac reset initiator
  164. * @umac_reset_count: Number of times Umac reset happened on this MLO group
  165. */
  166. struct dp_soc_mlo_umac_reset_ctx {
  167. unsigned long partner_map;
  168. unsigned long request_map;
  169. unsigned long response_map;
  170. qdf_spinlock_t grp_ctx_lock;
  171. uint8_t umac_reset_in_progress:1,
  172. is_target_recovery:1;
  173. uint8_t initiator_chip_id;
  174. uint32_t umac_reset_count;
  175. };
  176. #endif
  177. /**
  178. * struct dp_soc_umac_reset_ctx - UMAC reset context at soc level
  179. * @shmem_paddr_unaligned: Physical address of the shared memory (unaligned)
  180. * @shmem_vaddr_unaligned: Virtual address of the shared memory (unaligned)
  181. * @shmem_paddr_aligned: Physical address of the shared memory (aligned)
  182. * @shmem_vaddr_aligned: Virtual address of the shared memory (aligned)
  183. * @shmem_size: Size of the shared memory
  184. * @intr_offset: Offset of the UMAC reset interrupt w.r.t DP base interrupt
  185. * @current_state: current state of the UMAC reset state machine
  186. * @shmem_exp_magic_num: Expected magic number in the shared memory
  187. * @rx_actions: callbacks for handling UMAC reset actions
  188. * @pending_action: Action pending to be executed.
  189. * @intr_ctx_bkp: DP Interrupts ring masks backup
  190. * @nbuf_list: skb list for delayed free
  191. * @skel_enable: Enable skeleton code for umac reset
  192. * @ts: timestamps debug
  193. */
  194. struct dp_soc_umac_reset_ctx {
  195. qdf_dma_addr_t shmem_paddr_unaligned;
  196. void *shmem_vaddr_unaligned;
  197. qdf_dma_addr_t shmem_paddr_aligned;
  198. htt_umac_hang_recovery_msg_shmem_t *shmem_vaddr_aligned;
  199. size_t shmem_size;
  200. int intr_offset;
  201. enum umac_reset_state current_state;
  202. uint32_t shmem_exp_magic_num;
  203. struct umac_reset_rx_actions rx_actions;
  204. enum umac_reset_action pending_action;
  205. struct dp_intr_bkp *intr_ctx_bkp;
  206. qdf_nbuf_t nbuf_list;
  207. bool skel_enable;
  208. struct reset_ts ts;
  209. };
  210. /**
  211. * dp_soc_umac_reset_init() - Initialize UMAC reset context
  212. * @txrx_soc: DP soc object
  213. *
  214. * Return: QDF status of operation
  215. */
  216. QDF_STATUS dp_soc_umac_reset_init(struct cdp_soc_t *txrx_soc);
  217. /**
  218. * dp_soc_umac_reset_deinit() - De-initialize UMAC reset context
  219. * @txrx_soc: DP soc object
  220. *
  221. * Return: QDF status of operation
  222. */
  223. QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc);
  224. /**
  225. * dp_umac_reset_interrupt_attach() - Register handlers for UMAC reset interrupt
  226. * @soc: DP soc object
  227. *
  228. * Return: QDF status of operation
  229. */
  230. QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc);
  231. /**
  232. * dp_umac_reset_interrupt_detach() - Unregister UMAC reset interrupt handlers
  233. * @soc: DP soc object
  234. *
  235. * Return: QDF status of operation
  236. */
  237. QDF_STATUS dp_umac_reset_interrupt_detach(struct dp_soc *soc);
  238. /**
  239. * dp_umac_reset_register_rx_action_callback() - Register a callback for a given
  240. * UMAC reset action
  241. * @soc: DP soc object
  242. * @handler: callback handler to be registered
  243. * @action: UMAC reset action for which @handler needs to be registered
  244. *
  245. * Return: QDF status of operation
  246. */
  247. QDF_STATUS dp_umac_reset_register_rx_action_callback(
  248. struct dp_soc *soc,
  249. QDF_STATUS (*handler)(struct dp_soc *soc),
  250. enum umac_reset_action action);
  251. /**
  252. * dp_umac_reset_notify_action_completion() - Notify that a given action has
  253. * been completed
  254. * @soc: DP soc object
  255. * @action: UMAC reset action that got completed
  256. *
  257. * Return: QDF status of operation
  258. */
  259. QDF_STATUS dp_umac_reset_notify_action_completion(
  260. struct dp_soc *soc,
  261. enum umac_reset_action action);
  262. /**
  263. * dp_umac_reset_post_tx_cmd_via_shmem() - Post Tx command using shared memory
  264. * @soc: DP soc object
  265. * @ctxt: Tx command to be posted
  266. * @chip_id: Chip id of the mlo soc
  267. *
  268. * Return: None
  269. */
  270. void dp_umac_reset_post_tx_cmd_via_shmem(struct dp_soc *soc, void *ctxt,
  271. int chip_id);
  272. /**
  273. * dp_check_umac_reset_in_progress() - Check if Umac reset is in progress
  274. * @soc: dp soc handle
  275. *
  276. * Return: true if Umac reset is in progress or false otherwise
  277. */
  278. bool dp_check_umac_reset_in_progress(struct dp_soc *soc);
  279. /**
  280. * dp_umac_reset_stats_print - API to print UMAC reset stats
  281. * @soc: dp soc handle
  282. *
  283. * Return: QDF_STATUS
  284. */
  285. QDF_STATUS dp_umac_reset_stats_print(struct dp_soc *soc);
  286. /**
  287. * dp_umac_reset_validate_n_update_state_machine_on_rx() - Validate the state
  288. * machine for a given rx event and update the state machine
  289. * @umac_reset_ctx: UMAC reset context
  290. * @rx_event: Rx event
  291. * @current_exp_state: Expected state
  292. * @next_state: The state to which the state machine needs to be updated
  293. *
  294. * Return: QDF_STATUS of operation
  295. */
  296. QDF_STATUS
  297. dp_umac_reset_validate_n_update_state_machine_on_rx(
  298. struct dp_soc_umac_reset_ctx *umac_reset_ctx,
  299. enum umac_reset_rx_event rx_event,
  300. enum umac_reset_state current_exp_state,
  301. enum umac_reset_state next_state);
  302. #else
  303. static inline bool dp_check_umac_reset_in_progress(struct dp_soc *soc)
  304. {
  305. return false;
  306. }
  307. static inline
  308. QDF_STATUS dp_soc_umac_reset_init(struct cdp_soc_t *txrx_soc)
  309. {
  310. return QDF_STATUS_SUCCESS;
  311. }
  312. static inline
  313. QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc)
  314. {
  315. return QDF_STATUS_SUCCESS;
  316. }
  317. static inline
  318. QDF_STATUS dp_umac_reset_register_rx_action_callback(
  319. struct dp_soc *soc,
  320. QDF_STATUS (*handler)(struct dp_soc *soc),
  321. enum umac_reset_action action)
  322. {
  323. return QDF_STATUS_SUCCESS;
  324. }
  325. static inline
  326. QDF_STATUS dp_umac_reset_notify_action_completion(
  327. struct dp_soc *soc,
  328. enum umac_reset_action action)
  329. {
  330. return QDF_STATUS_SUCCESS;
  331. }
  332. static inline
  333. QDF_STATUS dp_umac_reset_stats_print(struct dp_soc *soc)
  334. {
  335. return QDF_STATUS_SUCCESS;
  336. }
  337. #endif /* DP_UMAC_HW_RESET_SUPPORT */
  338. #endif /* _DP_UMAC_RESET_H_ */