dp_rx.c 96 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_hw_headers.h"
  20. #include "dp_types.h"
  21. #include "dp_rx.h"
  22. #include "dp_tx.h"
  23. #include "dp_peer.h"
  24. #include "hal_rx.h"
  25. #include "hal_api.h"
  26. #include "qdf_nbuf.h"
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #include "dp_internal.h"
  31. #include "dp_ipa.h"
  32. #include "dp_hist.h"
  33. #include "dp_rx_buffer_pool.h"
  34. #ifdef WIFI_MONITOR_SUPPORT
  35. #include "dp_htt.h"
  36. #include <dp_mon.h>
  37. #endif
  38. #ifdef FEATURE_WDS
  39. #include "dp_txrx_wds.h"
  40. #endif
  41. #ifdef DP_RATETABLE_SUPPORT
  42. #include "dp_ratetable.h"
  43. #endif
  44. #include "enet.h"
  45. #ifndef WLAN_SOFTUMAC_SUPPORT /* WLAN_SOFTUMAC_SUPPORT */
  46. #ifdef DUP_RX_DESC_WAR
  47. void dp_rx_dump_info_and_assert(struct dp_soc *soc,
  48. hal_ring_handle_t hal_ring,
  49. hal_ring_desc_t ring_desc,
  50. struct dp_rx_desc *rx_desc)
  51. {
  52. void *hal_soc = soc->hal_soc;
  53. hal_srng_dump_ring_desc(hal_soc, hal_ring, ring_desc);
  54. dp_rx_desc_dump(rx_desc);
  55. }
  56. #else
  57. void dp_rx_dump_info_and_assert(struct dp_soc *soc,
  58. hal_ring_handle_t hal_ring_hdl,
  59. hal_ring_desc_t ring_desc,
  60. struct dp_rx_desc *rx_desc)
  61. {
  62. hal_soc_handle_t hal_soc = soc->hal_soc;
  63. dp_rx_desc_dump(rx_desc);
  64. hal_srng_dump_ring_desc(hal_soc, hal_ring_hdl, ring_desc);
  65. hal_srng_dump_ring(hal_soc, hal_ring_hdl);
  66. qdf_assert_always(0);
  67. }
  68. #endif
  69. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  70. #ifdef RX_DESC_SANITY_WAR
  71. QDF_STATUS dp_rx_desc_sanity(struct dp_soc *soc, hal_soc_handle_t hal_soc,
  72. hal_ring_handle_t hal_ring_hdl,
  73. hal_ring_desc_t ring_desc,
  74. struct dp_rx_desc *rx_desc)
  75. {
  76. uint8_t return_buffer_manager;
  77. if (qdf_unlikely(!rx_desc)) {
  78. /*
  79. * This is an unlikely case where the cookie obtained
  80. * from the ring_desc is invalid and hence we are not
  81. * able to find the corresponding rx_desc
  82. */
  83. goto fail;
  84. }
  85. return_buffer_manager = hal_rx_ret_buf_manager_get(hal_soc, ring_desc);
  86. if (qdf_unlikely(!(return_buffer_manager ==
  87. HAL_RX_BUF_RBM_SW1_BM(soc->wbm_sw0_bm_id) ||
  88. return_buffer_manager ==
  89. HAL_RX_BUF_RBM_SW3_BM(soc->wbm_sw0_bm_id)))) {
  90. goto fail;
  91. }
  92. return QDF_STATUS_SUCCESS;
  93. fail:
  94. DP_STATS_INC(soc, rx.err.invalid_cookie, 1);
  95. dp_err("Ring Desc:");
  96. hal_srng_dump_ring_desc(hal_soc, hal_ring_hdl,
  97. ring_desc);
  98. return QDF_STATUS_E_NULL_VALUE;
  99. }
  100. #endif
  101. uint32_t dp_rx_srng_get_num_pending(hal_soc_handle_t hal_soc,
  102. hal_ring_handle_t hal_ring_hdl,
  103. uint32_t num_entries,
  104. bool *near_full)
  105. {
  106. uint32_t num_pending = 0;
  107. num_pending = hal_srng_dst_num_valid_locked(hal_soc,
  108. hal_ring_hdl,
  109. true);
  110. if (num_entries && (num_pending >= num_entries >> 1))
  111. *near_full = true;
  112. else
  113. *near_full = false;
  114. return num_pending;
  115. }
  116. #ifdef RX_DESC_DEBUG_CHECK
  117. QDF_STATUS dp_rx_desc_nbuf_sanity_check(struct dp_soc *soc,
  118. hal_ring_desc_t ring_desc,
  119. struct dp_rx_desc *rx_desc)
  120. {
  121. struct hal_buf_info hbi;
  122. hal_rx_reo_buf_paddr_get(soc->hal_soc, ring_desc, &hbi);
  123. /* Sanity check for possible buffer paddr corruption */
  124. if (dp_rx_desc_paddr_sanity_check(rx_desc, (&hbi)->paddr))
  125. return QDF_STATUS_SUCCESS;
  126. return QDF_STATUS_E_FAILURE;
  127. }
  128. /**
  129. * dp_rx_desc_nbuf_len_sanity_check - Add sanity check to catch Rx buffer
  130. * out of bound access from H.W
  131. *
  132. * @soc: DP soc
  133. * @pkt_len: Packet length received from H.W
  134. *
  135. * Return: NONE
  136. */
  137. static inline void
  138. dp_rx_desc_nbuf_len_sanity_check(struct dp_soc *soc,
  139. uint32_t pkt_len)
  140. {
  141. struct rx_desc_pool *rx_desc_pool;
  142. rx_desc_pool = &soc->rx_desc_buf[0];
  143. qdf_assert_always(pkt_len <= rx_desc_pool->buf_size);
  144. }
  145. #else
  146. static inline void
  147. dp_rx_desc_nbuf_len_sanity_check(struct dp_soc *soc, uint32_t pkt_len) { }
  148. #endif
  149. #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY
  150. void
  151. dp_rx_ring_record_entry(struct dp_soc *soc, uint8_t ring_num,
  152. hal_ring_desc_t ring_desc)
  153. {
  154. struct dp_buf_info_record *record;
  155. struct hal_buf_info hbi;
  156. uint32_t idx;
  157. if (qdf_unlikely(!soc->rx_ring_history[ring_num]))
  158. return;
  159. hal_rx_reo_buf_paddr_get(soc->hal_soc, ring_desc, &hbi);
  160. /* buffer_addr_info is the first element of ring_desc */
  161. hal_rx_buf_cookie_rbm_get(soc->hal_soc, (uint32_t *)ring_desc,
  162. &hbi);
  163. idx = dp_history_get_next_index(&soc->rx_ring_history[ring_num]->index,
  164. DP_RX_HIST_MAX);
  165. /* No NULL check needed for record since its an array */
  166. record = &soc->rx_ring_history[ring_num]->entry[idx];
  167. record->timestamp = qdf_get_log_timestamp();
  168. record->hbi.paddr = hbi.paddr;
  169. record->hbi.sw_cookie = hbi.sw_cookie;
  170. record->hbi.rbm = hbi.rbm;
  171. }
  172. #endif
  173. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  174. void dp_rx_mark_first_packet_after_wow_wakeup(struct dp_pdev *pdev,
  175. uint8_t *rx_tlv,
  176. qdf_nbuf_t nbuf)
  177. {
  178. struct dp_soc *soc;
  179. if (!pdev->is_first_wakeup_packet)
  180. return;
  181. soc = pdev->soc;
  182. if (hal_get_first_wow_wakeup_packet(soc->hal_soc, rx_tlv)) {
  183. qdf_nbuf_mark_wakeup_frame(nbuf);
  184. dp_info("First packet after WOW Wakeup rcvd");
  185. }
  186. }
  187. #endif
  188. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  189. #endif /* WLAN_SOFTUMAC_SUPPORT */
  190. /**
  191. * dp_pdev_frag_alloc_and_map() - Allocate frag for desc buffer and map
  192. *
  193. * @dp_soc: struct dp_soc *
  194. * @nbuf_frag_info_t: nbuf frag info
  195. * @dp_pdev: struct dp_pdev *
  196. * @rx_desc_pool: Rx desc pool
  197. *
  198. * Return: QDF_STATUS
  199. */
  200. #ifdef DP_RX_MON_MEM_FRAG
  201. static inline QDF_STATUS
  202. dp_pdev_frag_alloc_and_map(struct dp_soc *dp_soc,
  203. struct dp_rx_nbuf_frag_info *nbuf_frag_info_t,
  204. struct dp_pdev *dp_pdev,
  205. struct rx_desc_pool *rx_desc_pool)
  206. {
  207. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  208. (nbuf_frag_info_t->virt_addr).vaddr =
  209. qdf_frag_alloc(NULL, rx_desc_pool->buf_size);
  210. if (!((nbuf_frag_info_t->virt_addr).vaddr)) {
  211. dp_err("Frag alloc failed");
  212. DP_STATS_INC(dp_pdev, replenish.frag_alloc_fail, 1);
  213. return QDF_STATUS_E_NOMEM;
  214. }
  215. ret = qdf_mem_map_page(dp_soc->osdev,
  216. (nbuf_frag_info_t->virt_addr).vaddr,
  217. QDF_DMA_FROM_DEVICE,
  218. rx_desc_pool->buf_size,
  219. &nbuf_frag_info_t->paddr);
  220. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret))) {
  221. qdf_frag_free((nbuf_frag_info_t->virt_addr).vaddr);
  222. dp_err("Frag map failed");
  223. DP_STATS_INC(dp_pdev, replenish.map_err, 1);
  224. return QDF_STATUS_E_FAULT;
  225. }
  226. return QDF_STATUS_SUCCESS;
  227. }
  228. #else
  229. static inline QDF_STATUS
  230. dp_pdev_frag_alloc_and_map(struct dp_soc *dp_soc,
  231. struct dp_rx_nbuf_frag_info *nbuf_frag_info_t,
  232. struct dp_pdev *dp_pdev,
  233. struct rx_desc_pool *rx_desc_pool)
  234. {
  235. return QDF_STATUS_SUCCESS;
  236. }
  237. #endif /* DP_RX_MON_MEM_FRAG */
  238. #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY
  239. /**
  240. * dp_rx_refill_ring_record_entry() - Record an entry into refill_ring history
  241. * @soc: Datapath soc structure
  242. * @ring_num: Refill ring number
  243. * @hal_ring_hdl:
  244. * @num_req: number of buffers requested for refill
  245. * @num_refill: number of buffers refilled
  246. *
  247. * Return: None
  248. */
  249. static inline void
  250. dp_rx_refill_ring_record_entry(struct dp_soc *soc, uint8_t ring_num,
  251. hal_ring_handle_t hal_ring_hdl,
  252. uint32_t num_req, uint32_t num_refill)
  253. {
  254. struct dp_refill_info_record *record;
  255. uint32_t idx;
  256. uint32_t tp;
  257. uint32_t hp;
  258. if (qdf_unlikely(ring_num >= MAX_PDEV_CNT ||
  259. !soc->rx_refill_ring_history[ring_num]))
  260. return;
  261. idx = dp_history_get_next_index(&soc->rx_refill_ring_history[ring_num]->index,
  262. DP_RX_REFILL_HIST_MAX);
  263. /* No NULL check needed for record since its an array */
  264. record = &soc->rx_refill_ring_history[ring_num]->entry[idx];
  265. hal_get_sw_hptp(soc->hal_soc, hal_ring_hdl, &tp, &hp);
  266. record->timestamp = qdf_get_log_timestamp();
  267. record->num_req = num_req;
  268. record->num_refill = num_refill;
  269. record->hp = hp;
  270. record->tp = tp;
  271. }
  272. #else
  273. static inline void
  274. dp_rx_refill_ring_record_entry(struct dp_soc *soc, uint8_t ring_num,
  275. hal_ring_handle_t hal_ring_hdl,
  276. uint32_t num_req, uint32_t num_refill)
  277. {
  278. }
  279. #endif
  280. /**
  281. * dp_pdev_nbuf_alloc_and_map_replenish() - Allocate nbuf for desc buffer and
  282. * map
  283. * @dp_soc: struct dp_soc *
  284. * @mac_id: Mac id
  285. * @num_entries_avail: num_entries_avail
  286. * @nbuf_frag_info_t: nbuf frag info
  287. * @dp_pdev: struct dp_pdev *
  288. * @rx_desc_pool: Rx desc pool
  289. *
  290. * Return: QDF_STATUS
  291. */
  292. static inline QDF_STATUS
  293. dp_pdev_nbuf_alloc_and_map_replenish(struct dp_soc *dp_soc,
  294. uint32_t mac_id,
  295. uint32_t num_entries_avail,
  296. struct dp_rx_nbuf_frag_info *nbuf_frag_info_t,
  297. struct dp_pdev *dp_pdev,
  298. struct rx_desc_pool *rx_desc_pool)
  299. {
  300. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  301. (nbuf_frag_info_t->virt_addr).nbuf =
  302. dp_rx_buffer_pool_nbuf_alloc(dp_soc,
  303. mac_id,
  304. rx_desc_pool,
  305. num_entries_avail);
  306. if (!((nbuf_frag_info_t->virt_addr).nbuf)) {
  307. dp_err("nbuf alloc failed");
  308. DP_STATS_INC(dp_pdev, replenish.nbuf_alloc_fail, 1);
  309. return QDF_STATUS_E_NOMEM;
  310. }
  311. ret = dp_rx_buffer_pool_nbuf_map(dp_soc, rx_desc_pool,
  312. nbuf_frag_info_t);
  313. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret))) {
  314. dp_rx_buffer_pool_nbuf_free(dp_soc,
  315. (nbuf_frag_info_t->virt_addr).nbuf, mac_id);
  316. dp_err("nbuf map failed");
  317. DP_STATS_INC(dp_pdev, replenish.map_err, 1);
  318. return QDF_STATUS_E_FAULT;
  319. }
  320. nbuf_frag_info_t->paddr =
  321. qdf_nbuf_get_frag_paddr((nbuf_frag_info_t->virt_addr).nbuf, 0);
  322. if (qdf_atomic_read(&dp_soc->ipa_mapped))
  323. dp_ipa_handle_rx_buf_smmu_mapping(dp_soc, (qdf_nbuf_t)(
  324. (nbuf_frag_info_t->virt_addr).nbuf),
  325. rx_desc_pool->buf_size,
  326. true, __func__, __LINE__);
  327. ret = dp_check_paddr(dp_soc, &((nbuf_frag_info_t->virt_addr).nbuf),
  328. &nbuf_frag_info_t->paddr,
  329. rx_desc_pool);
  330. if (ret == QDF_STATUS_E_FAILURE) {
  331. DP_STATS_INC(dp_pdev, replenish.x86_fail, 1);
  332. return QDF_STATUS_E_ADDRNOTAVAIL;
  333. }
  334. return QDF_STATUS_SUCCESS;
  335. }
  336. #if defined(QCA_DP_RX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  337. QDF_STATUS
  338. __dp_rx_buffers_no_map_lt_replenish(struct dp_soc *soc, uint32_t mac_id,
  339. struct dp_srng *dp_rxdma_srng,
  340. struct rx_desc_pool *rx_desc_pool)
  341. {
  342. struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  343. uint32_t count;
  344. void *rxdma_ring_entry;
  345. union dp_rx_desc_list_elem_t *next = NULL;
  346. void *rxdma_srng;
  347. qdf_nbuf_t nbuf;
  348. qdf_dma_addr_t paddr;
  349. uint16_t num_entries_avail = 0;
  350. uint16_t num_alloc_desc = 0;
  351. union dp_rx_desc_list_elem_t *desc_list = NULL;
  352. union dp_rx_desc_list_elem_t *tail = NULL;
  353. int sync_hw_ptr = 0;
  354. rxdma_srng = dp_rxdma_srng->hal_srng;
  355. if (qdf_unlikely(!dp_pdev)) {
  356. dp_rx_err("%pK: pdev is null for mac_id = %d", soc, mac_id);
  357. return QDF_STATUS_E_FAILURE;
  358. }
  359. if (qdf_unlikely(!rxdma_srng)) {
  360. dp_rx_debug("%pK: rxdma srng not initialized", soc);
  361. return QDF_STATUS_E_FAILURE;
  362. }
  363. hal_srng_access_start(soc->hal_soc, rxdma_srng);
  364. num_entries_avail = hal_srng_src_num_avail(soc->hal_soc,
  365. rxdma_srng,
  366. sync_hw_ptr);
  367. dp_rx_debug("%pK: no of available entries in rxdma ring: %d",
  368. soc, num_entries_avail);
  369. if (qdf_unlikely(num_entries_avail <
  370. ((dp_rxdma_srng->num_entries * 3) / 4))) {
  371. hal_srng_access_end(soc->hal_soc, rxdma_srng);
  372. return QDF_STATUS_E_FAILURE;
  373. }
  374. DP_STATS_INC(dp_pdev, replenish.low_thresh_intrs, 1);
  375. num_alloc_desc = dp_rx_get_free_desc_list(soc, mac_id,
  376. rx_desc_pool,
  377. num_entries_avail,
  378. &desc_list,
  379. &tail);
  380. if (!num_alloc_desc) {
  381. dp_rx_err("%pK: no free rx_descs in freelist", soc);
  382. DP_STATS_INC(dp_pdev, err.desc_lt_alloc_fail,
  383. num_entries_avail);
  384. hal_srng_access_end(soc->hal_soc, rxdma_srng);
  385. return QDF_STATUS_E_NOMEM;
  386. }
  387. for (count = 0; count < num_alloc_desc; count++) {
  388. next = desc_list->next;
  389. qdf_prefetch(next);
  390. nbuf = dp_rx_nbuf_alloc(soc, rx_desc_pool);
  391. if (qdf_unlikely(!nbuf)) {
  392. DP_STATS_INC(dp_pdev, replenish.nbuf_alloc_fail, 1);
  393. break;
  394. }
  395. paddr = dp_rx_nbuf_sync_no_dsb(soc, nbuf,
  396. rx_desc_pool->buf_size);
  397. rxdma_ring_entry = hal_srng_src_get_next(soc->hal_soc,
  398. rxdma_srng);
  399. qdf_assert_always(rxdma_ring_entry);
  400. desc_list->rx_desc.nbuf = nbuf;
  401. dp_rx_set_reuse_nbuf(&desc_list->rx_desc, nbuf);
  402. desc_list->rx_desc.rx_buf_start = nbuf->data;
  403. desc_list->rx_desc.paddr_buf_start = paddr;
  404. desc_list->rx_desc.unmapped = 0;
  405. /* rx_desc.in_use should be zero at this time*/
  406. qdf_assert_always(desc_list->rx_desc.in_use == 0);
  407. desc_list->rx_desc.in_use = 1;
  408. desc_list->rx_desc.in_err_state = 0;
  409. hal_rxdma_buff_addr_info_set(soc->hal_soc, rxdma_ring_entry,
  410. paddr,
  411. desc_list->rx_desc.cookie,
  412. rx_desc_pool->owner);
  413. desc_list = next;
  414. }
  415. qdf_dsb();
  416. hal_srng_access_end(soc->hal_soc, rxdma_srng);
  417. /* No need to count the number of bytes received during replenish.
  418. * Therefore set replenish.pkts.bytes as 0.
  419. */
  420. DP_STATS_INC_PKT(dp_pdev, replenish.pkts, count, 0);
  421. DP_STATS_INC(dp_pdev, buf_freelist, (num_alloc_desc - count));
  422. /*
  423. * add any available free desc back to the free list
  424. */
  425. if (desc_list)
  426. dp_rx_add_desc_list_to_free_list(soc, &desc_list, &tail,
  427. mac_id, rx_desc_pool);
  428. return QDF_STATUS_SUCCESS;
  429. }
  430. QDF_STATUS
  431. __dp_rx_buffers_no_map_replenish(struct dp_soc *soc, uint32_t mac_id,
  432. struct dp_srng *dp_rxdma_srng,
  433. struct rx_desc_pool *rx_desc_pool,
  434. uint32_t num_req_buffers,
  435. union dp_rx_desc_list_elem_t **desc_list,
  436. union dp_rx_desc_list_elem_t **tail)
  437. {
  438. struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  439. uint32_t count;
  440. void *rxdma_ring_entry;
  441. union dp_rx_desc_list_elem_t *next;
  442. void *rxdma_srng;
  443. qdf_nbuf_t nbuf;
  444. qdf_nbuf_t nbuf_next;
  445. qdf_nbuf_t nbuf_head = NULL;
  446. qdf_nbuf_t nbuf_tail = NULL;
  447. qdf_dma_addr_t paddr;
  448. rxdma_srng = dp_rxdma_srng->hal_srng;
  449. if (qdf_unlikely(!dp_pdev)) {
  450. dp_rx_err("%pK: pdev is null for mac_id = %d",
  451. soc, mac_id);
  452. return QDF_STATUS_E_FAILURE;
  453. }
  454. if (qdf_unlikely(!rxdma_srng)) {
  455. dp_rx_debug("%pK: rxdma srng not initialized", soc);
  456. DP_STATS_INC(dp_pdev, replenish.rxdma_err, num_req_buffers);
  457. return QDF_STATUS_E_FAILURE;
  458. }
  459. /* Allocate required number of nbufs */
  460. for (count = 0; count < num_req_buffers; count++) {
  461. nbuf = dp_rx_nbuf_alloc(soc, rx_desc_pool);
  462. if (qdf_unlikely(!nbuf)) {
  463. DP_STATS_INC(dp_pdev, replenish.nbuf_alloc_fail, 1);
  464. /* Update num_req_buffers to nbufs allocated count */
  465. num_req_buffers = count;
  466. break;
  467. }
  468. paddr = dp_rx_nbuf_sync_no_dsb(soc, nbuf,
  469. rx_desc_pool->buf_size);
  470. QDF_NBUF_CB_PADDR(nbuf) = paddr;
  471. DP_RX_LIST_APPEND(nbuf_head,
  472. nbuf_tail,
  473. nbuf);
  474. }
  475. qdf_dsb();
  476. nbuf = nbuf_head;
  477. hal_srng_access_start(soc->hal_soc, rxdma_srng);
  478. for (count = 0; count < num_req_buffers; count++) {
  479. next = (*desc_list)->next;
  480. nbuf_next = nbuf->next;
  481. qdf_prefetch(next);
  482. rxdma_ring_entry = (struct dp_buffer_addr_info *)
  483. hal_srng_src_get_next(soc->hal_soc, rxdma_srng);
  484. if (!rxdma_ring_entry)
  485. break;
  486. (*desc_list)->rx_desc.nbuf = nbuf;
  487. dp_rx_set_reuse_nbuf(&(*desc_list)->rx_desc, nbuf);
  488. (*desc_list)->rx_desc.rx_buf_start = nbuf->data;
  489. (*desc_list)->rx_desc.paddr_buf_start = QDF_NBUF_CB_PADDR(nbuf);
  490. (*desc_list)->rx_desc.unmapped = 0;
  491. /* rx_desc.in_use should be zero at this time*/
  492. qdf_assert_always((*desc_list)->rx_desc.in_use == 0);
  493. (*desc_list)->rx_desc.in_use = 1;
  494. (*desc_list)->rx_desc.in_err_state = 0;
  495. hal_rxdma_buff_addr_info_set(soc->hal_soc, rxdma_ring_entry,
  496. QDF_NBUF_CB_PADDR(nbuf),
  497. (*desc_list)->rx_desc.cookie,
  498. rx_desc_pool->owner);
  499. *desc_list = next;
  500. nbuf = nbuf_next;
  501. }
  502. hal_srng_access_end(soc->hal_soc, rxdma_srng);
  503. /* No need to count the number of bytes received during replenish.
  504. * Therefore set replenish.pkts.bytes as 0.
  505. */
  506. DP_STATS_INC_PKT(dp_pdev, replenish.pkts, count, 0);
  507. DP_STATS_INC(dp_pdev, buf_freelist, (num_req_buffers - count));
  508. /*
  509. * add any available free desc back to the free list
  510. */
  511. if (*desc_list)
  512. dp_rx_add_desc_list_to_free_list(soc, desc_list, tail,
  513. mac_id, rx_desc_pool);
  514. while (nbuf) {
  515. nbuf_next = nbuf->next;
  516. dp_rx_nbuf_unmap_pool(soc, rx_desc_pool, nbuf);
  517. qdf_nbuf_free(nbuf);
  518. nbuf = nbuf_next;
  519. }
  520. return QDF_STATUS_SUCCESS;
  521. }
  522. #ifdef WLAN_SUPPORT_PPEDS
  523. QDF_STATUS
  524. __dp_rx_comp2refill_replenish(struct dp_soc *soc, uint32_t mac_id,
  525. struct dp_srng *dp_rxdma_srng,
  526. struct rx_desc_pool *rx_desc_pool,
  527. uint32_t num_req_buffers,
  528. union dp_rx_desc_list_elem_t **desc_list,
  529. union dp_rx_desc_list_elem_t **tail)
  530. {
  531. struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  532. uint32_t count;
  533. void *rxdma_ring_entry;
  534. union dp_rx_desc_list_elem_t *next;
  535. union dp_rx_desc_list_elem_t *cur;
  536. void *rxdma_srng;
  537. qdf_nbuf_t nbuf;
  538. rxdma_srng = dp_rxdma_srng->hal_srng;
  539. if (qdf_unlikely(!dp_pdev)) {
  540. dp_rx_err("%pK: pdev is null for mac_id = %d",
  541. soc, mac_id);
  542. return QDF_STATUS_E_FAILURE;
  543. }
  544. if (qdf_unlikely(!rxdma_srng)) {
  545. dp_rx_debug("%pK: rxdma srng not initialized", soc);
  546. DP_STATS_INC(dp_pdev, replenish.rxdma_err, num_req_buffers);
  547. return QDF_STATUS_E_FAILURE;
  548. }
  549. hal_srng_access_start(soc->hal_soc, rxdma_srng);
  550. for (count = 0; count < num_req_buffers; count++) {
  551. next = (*desc_list)->next;
  552. qdf_prefetch(next);
  553. rxdma_ring_entry = (struct dp_buffer_addr_info *)
  554. hal_srng_src_get_next(soc->hal_soc, rxdma_srng);
  555. if (!rxdma_ring_entry)
  556. break;
  557. (*desc_list)->rx_desc.in_use = 1;
  558. (*desc_list)->rx_desc.in_err_state = 0;
  559. (*desc_list)->rx_desc.nbuf = (*desc_list)->rx_desc.reuse_nbuf;
  560. hal_rxdma_buff_addr_info_set(soc->hal_soc, rxdma_ring_entry,
  561. (*desc_list)->rx_desc.paddr_buf_start,
  562. (*desc_list)->rx_desc.cookie,
  563. rx_desc_pool->owner);
  564. *desc_list = next;
  565. }
  566. hal_srng_access_end(soc->hal_soc, rxdma_srng);
  567. /* No need to count the number of bytes received during replenish.
  568. * Therefore set replenish.pkts.bytes as 0.
  569. */
  570. DP_STATS_INC_PKT(dp_pdev, replenish.pkts, count, 0);
  571. DP_STATS_INC(dp_pdev, buf_freelist, (num_req_buffers - count));
  572. /*
  573. * add any available free desc back to the free list
  574. */
  575. cur = *desc_list;
  576. for ( ; count < num_req_buffers; count++) {
  577. next = cur->next;
  578. qdf_prefetch(next);
  579. nbuf = cur->rx_desc.reuse_nbuf;
  580. cur->rx_desc.nbuf = NULL;
  581. cur->rx_desc.in_use = 0;
  582. cur->rx_desc.has_reuse_nbuf = false;
  583. cur->rx_desc.reuse_nbuf = NULL;
  584. if (!nbuf->recycled_for_ds)
  585. dp_rx_nbuf_unmap_pool(soc, rx_desc_pool, nbuf);
  586. nbuf->recycled_for_ds = 0;
  587. nbuf->fast_recycled = 0;
  588. qdf_nbuf_free(nbuf);
  589. cur = next;
  590. }
  591. if (*desc_list)
  592. dp_rx_add_desc_list_to_free_list(soc, desc_list, tail,
  593. mac_id, rx_desc_pool);
  594. return QDF_STATUS_SUCCESS;
  595. }
  596. #endif
  597. QDF_STATUS __dp_pdev_rx_buffers_no_map_attach(struct dp_soc *soc,
  598. uint32_t mac_id,
  599. struct dp_srng *dp_rxdma_srng,
  600. struct rx_desc_pool *rx_desc_pool,
  601. uint32_t num_req_buffers)
  602. {
  603. struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  604. uint32_t count;
  605. uint32_t nr_descs = 0;
  606. void *rxdma_ring_entry;
  607. union dp_rx_desc_list_elem_t *next;
  608. void *rxdma_srng;
  609. qdf_nbuf_t nbuf;
  610. qdf_dma_addr_t paddr;
  611. union dp_rx_desc_list_elem_t *desc_list = NULL;
  612. union dp_rx_desc_list_elem_t *tail = NULL;
  613. rxdma_srng = dp_rxdma_srng->hal_srng;
  614. if (qdf_unlikely(!dp_pdev)) {
  615. dp_rx_err("%pK: pdev is null for mac_id = %d",
  616. soc, mac_id);
  617. return QDF_STATUS_E_FAILURE;
  618. }
  619. if (qdf_unlikely(!rxdma_srng)) {
  620. dp_rx_debug("%pK: rxdma srng not initialized", soc);
  621. DP_STATS_INC(dp_pdev, replenish.rxdma_err, num_req_buffers);
  622. return QDF_STATUS_E_FAILURE;
  623. }
  624. dp_rx_debug("%pK: requested %d buffers for replenish",
  625. soc, num_req_buffers);
  626. nr_descs = dp_rx_get_free_desc_list(soc, mac_id, rx_desc_pool,
  627. num_req_buffers, &desc_list, &tail);
  628. if (!nr_descs) {
  629. dp_err("no free rx_descs in freelist");
  630. DP_STATS_INC(dp_pdev, err.desc_alloc_fail, num_req_buffers);
  631. return QDF_STATUS_E_NOMEM;
  632. }
  633. dp_debug("got %u RX descs for driver attach", nr_descs);
  634. hal_srng_access_start(soc->hal_soc, rxdma_srng);
  635. for (count = 0; count < nr_descs; count++) {
  636. next = desc_list->next;
  637. qdf_prefetch(next);
  638. nbuf = dp_rx_nbuf_alloc(soc, rx_desc_pool);
  639. if (qdf_unlikely(!nbuf)) {
  640. DP_STATS_INC(dp_pdev, replenish.nbuf_alloc_fail, 1);
  641. break;
  642. }
  643. paddr = dp_rx_nbuf_sync_no_dsb(soc, nbuf,
  644. rx_desc_pool->buf_size);
  645. rxdma_ring_entry = (struct dp_buffer_addr_info *)
  646. hal_srng_src_get_next(soc->hal_soc, rxdma_srng);
  647. if (!rxdma_ring_entry)
  648. break;
  649. qdf_assert_always(rxdma_ring_entry);
  650. desc_list->rx_desc.nbuf = nbuf;
  651. dp_rx_set_reuse_nbuf(&desc_list->rx_desc, nbuf);
  652. desc_list->rx_desc.rx_buf_start = nbuf->data;
  653. desc_list->rx_desc.paddr_buf_start = paddr;
  654. desc_list->rx_desc.unmapped = 0;
  655. /* rx_desc.in_use should be zero at this time*/
  656. qdf_assert_always(desc_list->rx_desc.in_use == 0);
  657. desc_list->rx_desc.in_use = 1;
  658. desc_list->rx_desc.in_err_state = 0;
  659. hal_rxdma_buff_addr_info_set(soc->hal_soc, rxdma_ring_entry,
  660. paddr,
  661. desc_list->rx_desc.cookie,
  662. rx_desc_pool->owner);
  663. desc_list = next;
  664. }
  665. qdf_dsb();
  666. hal_srng_access_end(soc->hal_soc, rxdma_srng);
  667. /* No need to count the number of bytes received during replenish.
  668. * Therefore set replenish.pkts.bytes as 0.
  669. */
  670. DP_STATS_INC_PKT(dp_pdev, replenish.pkts, count, 0);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #endif
  674. #ifdef DP_UMAC_HW_RESET_SUPPORT
  675. #if defined(QCA_DP_RX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  676. static inline
  677. qdf_dma_addr_t dp_rx_rep_retrieve_paddr(struct dp_soc *dp_soc, qdf_nbuf_t nbuf,
  678. uint32_t buf_size)
  679. {
  680. return dp_rx_nbuf_sync_no_dsb(dp_soc, nbuf, buf_size);
  681. }
  682. #else
  683. static inline
  684. qdf_dma_addr_t dp_rx_rep_retrieve_paddr(struct dp_soc *dp_soc, qdf_nbuf_t nbuf,
  685. uint32_t buf_size)
  686. {
  687. return qdf_nbuf_get_frag_paddr(nbuf, 0);
  688. }
  689. #endif
  690. /**
  691. * dp_rx_desc_replenish() - Replenish the rx descriptors one at a time
  692. * @soc: core txrx main context
  693. * @dp_rxdma_srng: rxdma ring
  694. * @rx_desc_pool: rx descriptor pool
  695. * @rx_desc:rx descriptor
  696. *
  697. * Return: void
  698. */
  699. static inline
  700. void dp_rx_desc_replenish(struct dp_soc *soc, struct dp_srng *dp_rxdma_srng,
  701. struct rx_desc_pool *rx_desc_pool,
  702. struct dp_rx_desc *rx_desc)
  703. {
  704. void *rxdma_srng;
  705. void *rxdma_ring_entry;
  706. qdf_dma_addr_t paddr;
  707. rxdma_srng = dp_rxdma_srng->hal_srng;
  708. /* No one else should be accessing the srng at this point */
  709. hal_srng_access_start_unlocked(soc->hal_soc, rxdma_srng);
  710. rxdma_ring_entry = hal_srng_src_get_next(soc->hal_soc, rxdma_srng);
  711. qdf_assert_always(rxdma_ring_entry);
  712. rx_desc->in_err_state = 0;
  713. paddr = dp_rx_rep_retrieve_paddr(soc, rx_desc->nbuf,
  714. rx_desc_pool->buf_size);
  715. hal_rxdma_buff_addr_info_set(soc->hal_soc, rxdma_ring_entry, paddr,
  716. rx_desc->cookie, rx_desc_pool->owner);
  717. hal_srng_access_end_unlocked(soc->hal_soc, rxdma_srng);
  718. }
  719. void dp_rx_desc_reuse(struct dp_soc *soc, qdf_nbuf_t *nbuf_list)
  720. {
  721. int mac_id, i, j;
  722. union dp_rx_desc_list_elem_t *head = NULL;
  723. union dp_rx_desc_list_elem_t *tail = NULL;
  724. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  725. struct dp_srng *dp_rxdma_srng =
  726. &soc->rx_refill_buf_ring[mac_id];
  727. struct rx_desc_pool *rx_desc_pool = &soc->rx_desc_buf[mac_id];
  728. uint32_t rx_sw_desc_num = rx_desc_pool->pool_size;
  729. /* Only fill up 1/3 of the ring size */
  730. uint32_t num_req_decs;
  731. if (!dp_rxdma_srng || !dp_rxdma_srng->hal_srng ||
  732. !rx_desc_pool->array)
  733. continue;
  734. num_req_decs = dp_rxdma_srng->num_entries / 3;
  735. for (i = 0, j = 0; i < rx_sw_desc_num; i++) {
  736. struct dp_rx_desc *rx_desc =
  737. (struct dp_rx_desc *)&rx_desc_pool->array[i];
  738. if (rx_desc->in_use) {
  739. if (j < (dp_rxdma_srng->num_entries - 1)) {
  740. dp_rx_desc_replenish(soc, dp_rxdma_srng,
  741. rx_desc_pool,
  742. rx_desc);
  743. } else {
  744. dp_rx_nbuf_unmap(soc, rx_desc, 0);
  745. rx_desc->unmapped = 0;
  746. rx_desc->nbuf->next = *nbuf_list;
  747. *nbuf_list = rx_desc->nbuf;
  748. dp_rx_add_to_free_desc_list(&head,
  749. &tail,
  750. rx_desc);
  751. }
  752. j++;
  753. }
  754. }
  755. if (head)
  756. dp_rx_add_desc_list_to_free_list(soc, &head, &tail,
  757. mac_id, rx_desc_pool);
  758. /* If num of descs in use were less, then we need to replenish
  759. * the ring with some buffers
  760. */
  761. head = NULL;
  762. tail = NULL;
  763. if (j < (num_req_decs - 1))
  764. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  765. rx_desc_pool,
  766. ((num_req_decs - 1) - j),
  767. &head, &tail, true);
  768. }
  769. }
  770. #endif
  771. QDF_STATUS __dp_rx_buffers_replenish(struct dp_soc *dp_soc, uint32_t mac_id,
  772. struct dp_srng *dp_rxdma_srng,
  773. struct rx_desc_pool *rx_desc_pool,
  774. uint32_t num_req_buffers,
  775. union dp_rx_desc_list_elem_t **desc_list,
  776. union dp_rx_desc_list_elem_t **tail,
  777. bool req_only, const char *func_name)
  778. {
  779. uint32_t num_alloc_desc;
  780. uint16_t num_desc_to_free = 0;
  781. struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(dp_soc, mac_id);
  782. uint32_t num_entries_avail;
  783. uint32_t count;
  784. uint32_t extra_buffers;
  785. int sync_hw_ptr = 1;
  786. struct dp_rx_nbuf_frag_info nbuf_frag_info = {0};
  787. void *rxdma_ring_entry;
  788. union dp_rx_desc_list_elem_t *next;
  789. QDF_STATUS ret;
  790. void *rxdma_srng;
  791. union dp_rx_desc_list_elem_t *desc_list_append = NULL;
  792. union dp_rx_desc_list_elem_t *tail_append = NULL;
  793. union dp_rx_desc_list_elem_t *temp_list = NULL;
  794. rxdma_srng = dp_rxdma_srng->hal_srng;
  795. if (qdf_unlikely(!dp_pdev)) {
  796. dp_rx_err("%pK: pdev is null for mac_id = %d",
  797. dp_soc, mac_id);
  798. return QDF_STATUS_E_FAILURE;
  799. }
  800. if (qdf_unlikely(!rxdma_srng)) {
  801. dp_rx_debug("%pK: rxdma srng not initialized", dp_soc);
  802. DP_STATS_INC(dp_pdev, replenish.rxdma_err, num_req_buffers);
  803. return QDF_STATUS_E_FAILURE;
  804. }
  805. dp_verbose_debug("%pK: requested %d buffers for replenish",
  806. dp_soc, num_req_buffers);
  807. hal_srng_access_start(dp_soc->hal_soc, rxdma_srng);
  808. num_entries_avail = hal_srng_src_num_avail(dp_soc->hal_soc,
  809. rxdma_srng,
  810. sync_hw_ptr);
  811. dp_verbose_debug("%pK: no of available entries in rxdma ring: %d",
  812. dp_soc, num_entries_avail);
  813. if (!req_only && !(*desc_list) && (num_entries_avail >
  814. ((dp_rxdma_srng->num_entries * 3) / 4))) {
  815. num_req_buffers = num_entries_avail;
  816. DP_STATS_INC(dp_pdev, replenish.low_thresh_intrs, 1);
  817. } else if (num_entries_avail < num_req_buffers) {
  818. num_desc_to_free = num_req_buffers - num_entries_avail;
  819. num_req_buffers = num_entries_avail;
  820. } else if ((*desc_list) &&
  821. dp_rxdma_srng->num_entries - num_entries_avail <
  822. CRITICAL_BUFFER_THRESHOLD) {
  823. /* set extra buffers to CRITICAL_BUFFER_THRESHOLD only if
  824. * total buff requested after adding extra buffers is less
  825. * than or equal to num entries available, else set it to max
  826. * possible additional buffers available at that moment
  827. */
  828. extra_buffers =
  829. ((num_req_buffers + CRITICAL_BUFFER_THRESHOLD) > num_entries_avail) ?
  830. (num_entries_avail - num_req_buffers) :
  831. CRITICAL_BUFFER_THRESHOLD;
  832. /* Append some free descriptors to tail */
  833. num_alloc_desc =
  834. dp_rx_get_free_desc_list(dp_soc, mac_id,
  835. rx_desc_pool,
  836. extra_buffers,
  837. &desc_list_append,
  838. &tail_append);
  839. if (num_alloc_desc) {
  840. temp_list = *desc_list;
  841. *desc_list = desc_list_append;
  842. tail_append->next = temp_list;
  843. num_req_buffers += num_alloc_desc;
  844. DP_STATS_DEC(dp_pdev,
  845. replenish.free_list,
  846. num_alloc_desc);
  847. } else
  848. dp_err_rl("%pK: no free rx_descs in freelist", dp_soc);
  849. }
  850. if (qdf_unlikely(!num_req_buffers)) {
  851. num_desc_to_free = num_req_buffers;
  852. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  853. goto free_descs;
  854. }
  855. /*
  856. * if desc_list is NULL, allocate the descs from freelist
  857. */
  858. if (!(*desc_list)) {
  859. num_alloc_desc = dp_rx_get_free_desc_list(dp_soc, mac_id,
  860. rx_desc_pool,
  861. num_req_buffers,
  862. desc_list,
  863. tail);
  864. if (!num_alloc_desc) {
  865. dp_rx_err("%pK: no free rx_descs in freelist", dp_soc);
  866. DP_STATS_INC(dp_pdev, err.desc_alloc_fail,
  867. num_req_buffers);
  868. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  869. return QDF_STATUS_E_NOMEM;
  870. }
  871. dp_verbose_debug("%pK: %d rx desc allocated", dp_soc,
  872. num_alloc_desc);
  873. num_req_buffers = num_alloc_desc;
  874. }
  875. count = 0;
  876. while (count < num_req_buffers) {
  877. /* Flag is set while pdev rx_desc_pool initialization */
  878. if (qdf_unlikely(rx_desc_pool->rx_mon_dest_frag_enable))
  879. ret = dp_pdev_frag_alloc_and_map(dp_soc,
  880. &nbuf_frag_info,
  881. dp_pdev,
  882. rx_desc_pool);
  883. else
  884. ret = dp_pdev_nbuf_alloc_and_map_replenish(dp_soc,
  885. mac_id,
  886. num_entries_avail, &nbuf_frag_info,
  887. dp_pdev, rx_desc_pool);
  888. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret))) {
  889. if (qdf_unlikely(ret == QDF_STATUS_E_FAULT))
  890. continue;
  891. break;
  892. }
  893. count++;
  894. rxdma_ring_entry = hal_srng_src_get_next(dp_soc->hal_soc,
  895. rxdma_srng);
  896. qdf_assert_always(rxdma_ring_entry);
  897. next = (*desc_list)->next;
  898. /* Flag is set while pdev rx_desc_pool initialization */
  899. if (qdf_unlikely(rx_desc_pool->rx_mon_dest_frag_enable))
  900. dp_rx_desc_frag_prep(&((*desc_list)->rx_desc),
  901. &nbuf_frag_info);
  902. else
  903. dp_rx_desc_prep(&((*desc_list)->rx_desc),
  904. &nbuf_frag_info);
  905. /* rx_desc.in_use should be zero at this time*/
  906. qdf_assert_always((*desc_list)->rx_desc.in_use == 0);
  907. (*desc_list)->rx_desc.in_use = 1;
  908. (*desc_list)->rx_desc.in_err_state = 0;
  909. dp_rx_desc_update_dbg_info(&(*desc_list)->rx_desc,
  910. func_name, RX_DESC_REPLENISHED);
  911. dp_verbose_debug("rx_netbuf=%pK, paddr=0x%llx, cookie=%d",
  912. nbuf_frag_info.virt_addr.nbuf,
  913. (unsigned long long)(nbuf_frag_info.paddr),
  914. (*desc_list)->rx_desc.cookie);
  915. hal_rxdma_buff_addr_info_set(dp_soc->hal_soc, rxdma_ring_entry,
  916. nbuf_frag_info.paddr,
  917. (*desc_list)->rx_desc.cookie,
  918. rx_desc_pool->owner);
  919. *desc_list = next;
  920. }
  921. dp_rx_refill_ring_record_entry(dp_soc, dp_pdev->lmac_id, rxdma_srng,
  922. num_req_buffers, count);
  923. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  924. dp_rx_schedule_refill_thread(dp_soc);
  925. dp_verbose_debug("replenished buffers %d, rx desc added back to free list %u",
  926. count, num_desc_to_free);
  927. /* No need to count the number of bytes received during replenish.
  928. * Therefore set replenish.pkts.bytes as 0.
  929. */
  930. DP_STATS_INC_PKT(dp_pdev, replenish.pkts, count, 0);
  931. DP_STATS_INC(dp_pdev, replenish.free_list, num_req_buffers - count);
  932. free_descs:
  933. DP_STATS_INC(dp_pdev, buf_freelist, num_desc_to_free);
  934. /*
  935. * add any available free desc back to the free list
  936. */
  937. if (*desc_list)
  938. dp_rx_add_desc_list_to_free_list(dp_soc, desc_list, tail,
  939. mac_id, rx_desc_pool);
  940. return QDF_STATUS_SUCCESS;
  941. }
  942. qdf_export_symbol(__dp_rx_buffers_replenish);
  943. void
  944. dp_rx_deliver_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf_list,
  945. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  946. {
  947. qdf_nbuf_t deliver_list_head = NULL;
  948. qdf_nbuf_t deliver_list_tail = NULL;
  949. qdf_nbuf_t nbuf;
  950. nbuf = nbuf_list;
  951. while (nbuf) {
  952. qdf_nbuf_t next = qdf_nbuf_next(nbuf);
  953. DP_RX_LIST_APPEND(deliver_list_head, deliver_list_tail, nbuf);
  954. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  955. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.raw, 1,
  956. qdf_nbuf_len(nbuf), link_id);
  957. /*
  958. * reset the chfrag_start and chfrag_end bits in nbuf cb
  959. * as this is a non-amsdu pkt and RAW mode simulation expects
  960. * these bit s to be 0 for non-amsdu pkt.
  961. */
  962. if (qdf_nbuf_is_rx_chfrag_start(nbuf) &&
  963. qdf_nbuf_is_rx_chfrag_end(nbuf)) {
  964. qdf_nbuf_set_rx_chfrag_start(nbuf, 0);
  965. qdf_nbuf_set_rx_chfrag_end(nbuf, 0);
  966. }
  967. nbuf = next;
  968. }
  969. vdev->osif_rsim_rx_decap(vdev->osif_vdev, &deliver_list_head,
  970. &deliver_list_tail);
  971. vdev->osif_rx(vdev->osif_vdev, deliver_list_head);
  972. }
  973. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  974. #ifndef FEATURE_WDS
  975. void dp_rx_da_learn(struct dp_soc *soc, uint8_t *rx_tlv_hdr,
  976. struct dp_txrx_peer *ta_peer, qdf_nbuf_t nbuf)
  977. {
  978. }
  979. #endif
  980. #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES
  981. /**
  982. * dp_classify_critical_pkts() - API for marking critical packets
  983. * @soc: dp_soc context
  984. * @vdev: vdev on which packet is to be sent
  985. * @nbuf: nbuf that has to be classified
  986. *
  987. * The function parses the packet, identifies whether its a critical frame and
  988. * marks QDF_NBUF_CB_TX_EXTRA_IS_CRITICAL bit in qdf_nbuf_cb for the nbuf.
  989. * Code for marking which frames are CRITICAL is accessed via callback.
  990. * EAPOL, ARP, DHCP, DHCPv6, ICMPv6 NS/NA are the typical critical frames.
  991. *
  992. * Return: None
  993. */
  994. static
  995. void dp_classify_critical_pkts(struct dp_soc *soc, struct dp_vdev *vdev,
  996. qdf_nbuf_t nbuf)
  997. {
  998. if (vdev->tx_classify_critical_pkt_cb)
  999. vdev->tx_classify_critical_pkt_cb(vdev->osif_vdev, nbuf);
  1000. }
  1001. #else
  1002. static inline
  1003. void dp_classify_critical_pkts(struct dp_soc *soc, struct dp_vdev *vdev,
  1004. qdf_nbuf_t nbuf)
  1005. {
  1006. }
  1007. #endif
  1008. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  1009. static inline
  1010. void dp_rx_nbuf_queue_mapping_set(qdf_nbuf_t nbuf, uint8_t ring_id)
  1011. {
  1012. qdf_nbuf_set_queue_mapping(nbuf, ring_id);
  1013. }
  1014. #else
  1015. static inline
  1016. void dp_rx_nbuf_queue_mapping_set(qdf_nbuf_t nbuf, uint8_t ring_id)
  1017. {
  1018. }
  1019. #endif
  1020. bool dp_rx_intrabss_mcbc_fwd(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
  1021. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1022. struct cdp_tid_rx_stats *tid_stats,
  1023. uint8_t link_id)
  1024. {
  1025. uint16_t len;
  1026. qdf_nbuf_t nbuf_copy;
  1027. if (dp_rx_intrabss_eapol_drop_check(soc, ta_peer, rx_tlv_hdr,
  1028. nbuf))
  1029. return true;
  1030. if (!dp_rx_check_ndi_mdns_fwding(ta_peer, nbuf, link_id))
  1031. return false;
  1032. /* If the source peer in the isolation list
  1033. * then dont forward instead push to bridge stack
  1034. */
  1035. if (dp_get_peer_isolation(ta_peer))
  1036. return false;
  1037. nbuf_copy = qdf_nbuf_copy(nbuf);
  1038. if (!nbuf_copy)
  1039. return false;
  1040. len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  1041. qdf_mem_set(nbuf_copy->cb, 0x0, sizeof(nbuf_copy->cb));
  1042. dp_classify_critical_pkts(soc, ta_peer->vdev, nbuf_copy);
  1043. if (soc->arch_ops.dp_rx_intrabss_mcast_handler(soc, ta_peer,
  1044. nbuf_copy,
  1045. tid_stats,
  1046. link_id))
  1047. return false;
  1048. /* Don't send packets if tx is paused */
  1049. if (!soc->is_tx_pause &&
  1050. !dp_tx_send((struct cdp_soc_t *)soc,
  1051. ta_peer->vdev->vdev_id, nbuf_copy)) {
  1052. DP_PEER_PER_PKT_STATS_INC_PKT(ta_peer, rx.intra_bss.pkts, 1,
  1053. len, link_id);
  1054. tid_stats->intrabss_cnt++;
  1055. } else {
  1056. DP_PEER_PER_PKT_STATS_INC_PKT(ta_peer, rx.intra_bss.fail, 1,
  1057. len, link_id);
  1058. tid_stats->fail_cnt[INTRABSS_DROP]++;
  1059. dp_rx_nbuf_free(nbuf_copy);
  1060. }
  1061. return false;
  1062. }
  1063. bool dp_rx_intrabss_ucast_fwd(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
  1064. uint8_t tx_vdev_id,
  1065. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1066. struct cdp_tid_rx_stats *tid_stats,
  1067. uint8_t link_id)
  1068. {
  1069. uint16_t len;
  1070. len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  1071. /* linearize the nbuf just before we send to
  1072. * dp_tx_send()
  1073. */
  1074. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  1075. if (qdf_nbuf_linearize(nbuf) == -ENOMEM)
  1076. return false;
  1077. nbuf = qdf_nbuf_unshare(nbuf);
  1078. if (!nbuf) {
  1079. DP_PEER_PER_PKT_STATS_INC_PKT(ta_peer,
  1080. rx.intra_bss.fail,
  1081. 1, len, link_id);
  1082. /* return true even though the pkt is
  1083. * not forwarded. Basically skb_unshare
  1084. * failed and we want to continue with
  1085. * next nbuf.
  1086. */
  1087. tid_stats->fail_cnt[INTRABSS_DROP]++;
  1088. return false;
  1089. }
  1090. }
  1091. qdf_mem_set(nbuf->cb, 0x0, sizeof(nbuf->cb));
  1092. dp_classify_critical_pkts(soc, ta_peer->vdev, nbuf);
  1093. /* Don't send packets if tx is paused */
  1094. if (!soc->is_tx_pause && !dp_tx_send((struct cdp_soc_t *)soc,
  1095. tx_vdev_id, nbuf)) {
  1096. DP_PEER_PER_PKT_STATS_INC_PKT(ta_peer, rx.intra_bss.pkts, 1,
  1097. len, link_id);
  1098. } else {
  1099. DP_PEER_PER_PKT_STATS_INC_PKT(ta_peer, rx.intra_bss.fail, 1,
  1100. len, link_id);
  1101. tid_stats->fail_cnt[INTRABSS_DROP]++;
  1102. return false;
  1103. }
  1104. return true;
  1105. }
  1106. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  1107. #ifdef MESH_MODE_SUPPORT
  1108. void dp_rx_fill_mesh_stats(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1109. uint8_t *rx_tlv_hdr,
  1110. struct dp_txrx_peer *txrx_peer)
  1111. {
  1112. struct mesh_recv_hdr_s *rx_info = NULL;
  1113. uint32_t pkt_type;
  1114. uint32_t nss;
  1115. uint32_t rate_mcs;
  1116. uint32_t bw;
  1117. uint8_t primary_chan_num;
  1118. uint32_t center_chan_freq;
  1119. struct dp_soc *soc = vdev->pdev->soc;
  1120. struct dp_peer *peer;
  1121. struct dp_peer *primary_link_peer;
  1122. struct dp_soc *link_peer_soc;
  1123. cdp_peer_stats_param_t buf = {0};
  1124. /* fill recv mesh stats */
  1125. rx_info = qdf_mem_malloc(sizeof(struct mesh_recv_hdr_s));
  1126. /* upper layers are responsible to free this memory */
  1127. if (!rx_info) {
  1128. dp_rx_err("%pK: Memory allocation failed for mesh rx stats",
  1129. vdev->pdev->soc);
  1130. DP_STATS_INC(vdev->pdev, mesh_mem_alloc, 1);
  1131. return;
  1132. }
  1133. rx_info->rs_flags = MESH_RXHDR_VER1;
  1134. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  1135. rx_info->rs_flags |= MESH_RX_FIRST_MSDU;
  1136. if (qdf_nbuf_is_rx_chfrag_end(nbuf))
  1137. rx_info->rs_flags |= MESH_RX_LAST_MSDU;
  1138. peer = dp_peer_get_ref_by_id(soc, txrx_peer->peer_id, DP_MOD_ID_MESH);
  1139. if (peer) {
  1140. if (hal_rx_tlv_get_is_decrypted(soc->hal_soc, rx_tlv_hdr)) {
  1141. rx_info->rs_flags |= MESH_RX_DECRYPTED;
  1142. rx_info->rs_keyix = hal_rx_msdu_get_keyid(soc->hal_soc,
  1143. rx_tlv_hdr);
  1144. if (vdev->osif_get_key)
  1145. vdev->osif_get_key(vdev->osif_vdev,
  1146. &rx_info->rs_decryptkey[0],
  1147. &peer->mac_addr.raw[0],
  1148. rx_info->rs_keyix);
  1149. }
  1150. dp_peer_unref_delete(peer, DP_MOD_ID_MESH);
  1151. }
  1152. primary_link_peer = dp_get_primary_link_peer_by_id(soc,
  1153. txrx_peer->peer_id,
  1154. DP_MOD_ID_MESH);
  1155. if (qdf_likely(primary_link_peer)) {
  1156. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  1157. dp_monitor_peer_get_stats_param(link_peer_soc,
  1158. primary_link_peer,
  1159. cdp_peer_rx_snr, &buf);
  1160. rx_info->rs_snr = buf.rx_snr;
  1161. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_MESH);
  1162. }
  1163. rx_info->rs_rssi = rx_info->rs_snr + DP_DEFAULT_NOISEFLOOR;
  1164. soc = vdev->pdev->soc;
  1165. primary_chan_num = hal_rx_tlv_get_freq(soc->hal_soc, rx_tlv_hdr);
  1166. center_chan_freq = hal_rx_tlv_get_freq(soc->hal_soc, rx_tlv_hdr) >> 16;
  1167. if (soc->cdp_soc.ol_ops && soc->cdp_soc.ol_ops->freq_to_band) {
  1168. rx_info->rs_band = soc->cdp_soc.ol_ops->freq_to_band(
  1169. soc->ctrl_psoc,
  1170. vdev->pdev->pdev_id,
  1171. center_chan_freq);
  1172. }
  1173. rx_info->rs_channel = primary_chan_num;
  1174. pkt_type = hal_rx_tlv_get_pkt_type(soc->hal_soc, rx_tlv_hdr);
  1175. rate_mcs = hal_rx_tlv_rate_mcs_get(soc->hal_soc, rx_tlv_hdr);
  1176. bw = hal_rx_tlv_bw_get(soc->hal_soc, rx_tlv_hdr);
  1177. nss = hal_rx_msdu_start_nss_get(soc->hal_soc, rx_tlv_hdr);
  1178. /*
  1179. * The MCS index does not start with 0 when NSS>1 in HT mode.
  1180. * MCS params for optional 20/40MHz, NSS=1~3, EQM(NSS>1):
  1181. * ------------------------------------------------------
  1182. * NSS | 1 | 2 | 3 | 4
  1183. * ------------------------------------------------------
  1184. * MCS index: HT20 | 0 ~ 7 | 8 ~ 15 | 16 ~ 23 | 24 ~ 31
  1185. * ------------------------------------------------------
  1186. * MCS index: HT40 | 0 ~ 7 | 8 ~ 15 | 16 ~ 23 | 24 ~ 31
  1187. * ------------------------------------------------------
  1188. * Currently, the MAX_NSS=2. If NSS>2, MCS index = 8 * (NSS-1)
  1189. */
  1190. if ((pkt_type == DOT11_N) && (nss == 2))
  1191. rate_mcs += 8;
  1192. rx_info->rs_ratephy1 = rate_mcs | (nss << 0x8) | (pkt_type << 16) |
  1193. (bw << 24);
  1194. qdf_nbuf_set_rx_fctx_type(nbuf, (void *)rx_info, CB_FTYPE_MESH_RX_INFO);
  1195. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO_MED,
  1196. FL("Mesh rx stats: flags %x, rssi %x, chn %x, rate %x, kix %x, snr %x"),
  1197. rx_info->rs_flags,
  1198. rx_info->rs_rssi,
  1199. rx_info->rs_channel,
  1200. rx_info->rs_ratephy1,
  1201. rx_info->rs_keyix,
  1202. rx_info->rs_snr);
  1203. }
  1204. QDF_STATUS dp_rx_filter_mesh_packets(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1205. uint8_t *rx_tlv_hdr)
  1206. {
  1207. union dp_align_mac_addr mac_addr;
  1208. struct dp_soc *soc = vdev->pdev->soc;
  1209. if (qdf_unlikely(vdev->mesh_rx_filter)) {
  1210. if (vdev->mesh_rx_filter & MESH_FILTER_OUT_FROMDS)
  1211. if (hal_rx_mpdu_get_fr_ds(soc->hal_soc,
  1212. rx_tlv_hdr))
  1213. return QDF_STATUS_SUCCESS;
  1214. if (vdev->mesh_rx_filter & MESH_FILTER_OUT_TODS)
  1215. if (hal_rx_mpdu_get_to_ds(soc->hal_soc,
  1216. rx_tlv_hdr))
  1217. return QDF_STATUS_SUCCESS;
  1218. if (vdev->mesh_rx_filter & MESH_FILTER_OUT_NODS)
  1219. if (!hal_rx_mpdu_get_fr_ds(soc->hal_soc,
  1220. rx_tlv_hdr) &&
  1221. !hal_rx_mpdu_get_to_ds(soc->hal_soc,
  1222. rx_tlv_hdr))
  1223. return QDF_STATUS_SUCCESS;
  1224. if (vdev->mesh_rx_filter & MESH_FILTER_OUT_RA) {
  1225. if (hal_rx_mpdu_get_addr1(soc->hal_soc,
  1226. rx_tlv_hdr,
  1227. &mac_addr.raw[0]))
  1228. return QDF_STATUS_E_FAILURE;
  1229. if (!qdf_mem_cmp(&mac_addr.raw[0],
  1230. &vdev->mac_addr.raw[0],
  1231. QDF_MAC_ADDR_SIZE))
  1232. return QDF_STATUS_SUCCESS;
  1233. }
  1234. if (vdev->mesh_rx_filter & MESH_FILTER_OUT_TA) {
  1235. if (hal_rx_mpdu_get_addr2(soc->hal_soc,
  1236. rx_tlv_hdr,
  1237. &mac_addr.raw[0]))
  1238. return QDF_STATUS_E_FAILURE;
  1239. if (!qdf_mem_cmp(&mac_addr.raw[0],
  1240. &vdev->mac_addr.raw[0],
  1241. QDF_MAC_ADDR_SIZE))
  1242. return QDF_STATUS_SUCCESS;
  1243. }
  1244. }
  1245. return QDF_STATUS_E_FAILURE;
  1246. }
  1247. #else
  1248. void dp_rx_fill_mesh_stats(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1249. uint8_t *rx_tlv_hdr, struct dp_txrx_peer *peer)
  1250. {
  1251. }
  1252. QDF_STATUS dp_rx_filter_mesh_packets(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1253. uint8_t *rx_tlv_hdr)
  1254. {
  1255. return QDF_STATUS_E_FAILURE;
  1256. }
  1257. #endif
  1258. #ifdef RX_PEER_INVALID_ENH
  1259. uint8_t dp_rx_process_invalid_peer(struct dp_soc *soc, qdf_nbuf_t mpdu,
  1260. uint8_t mac_id)
  1261. {
  1262. struct dp_invalid_peer_msg msg;
  1263. struct dp_vdev *vdev = NULL;
  1264. struct dp_pdev *pdev = NULL;
  1265. struct ieee80211_frame *wh;
  1266. qdf_nbuf_t curr_nbuf, next_nbuf;
  1267. uint8_t *rx_tlv_hdr = qdf_nbuf_data(mpdu);
  1268. uint8_t *rx_pkt_hdr = NULL;
  1269. int i = 0;
  1270. uint32_t nbuf_len;
  1271. if (!HAL_IS_DECAP_FORMAT_RAW(soc->hal_soc, rx_tlv_hdr)) {
  1272. dp_rx_debug("%pK: Drop decapped frames", soc);
  1273. goto free;
  1274. }
  1275. /* In RAW packet, packet header will be part of data */
  1276. rx_pkt_hdr = rx_tlv_hdr + soc->rx_pkt_tlv_size;
  1277. wh = (struct ieee80211_frame *)rx_pkt_hdr;
  1278. if (!DP_FRAME_IS_DATA(wh)) {
  1279. dp_rx_debug("%pK: NAWDS valid only for data frames", soc);
  1280. goto free;
  1281. }
  1282. nbuf_len = qdf_nbuf_len(mpdu);
  1283. if (nbuf_len < sizeof(struct ieee80211_frame)) {
  1284. dp_rx_err("%pK: Invalid nbuf length: %u", soc, nbuf_len);
  1285. goto free;
  1286. }
  1287. /* In DMAC case the rx_desc_pools are common across PDEVs
  1288. * so PDEV cannot be derived from the pool_id.
  1289. *
  1290. * link_id need to derived from the TLV tag word which is
  1291. * disabled by default. For now adding a WAR to get vdev
  1292. * with brute force this need to fixed with word based subscription
  1293. * support is added by enabling TLV tag word
  1294. */
  1295. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1296. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1297. pdev = soc->pdev_list[i];
  1298. if (!pdev || qdf_unlikely(pdev->is_pdev_down))
  1299. continue;
  1300. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  1301. if (qdf_mem_cmp(wh->i_addr1, vdev->mac_addr.raw,
  1302. QDF_MAC_ADDR_SIZE) == 0) {
  1303. goto out;
  1304. }
  1305. }
  1306. }
  1307. } else {
  1308. pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  1309. if (!pdev || qdf_unlikely(pdev->is_pdev_down)) {
  1310. dp_rx_err("%pK: PDEV %s",
  1311. soc, !pdev ? "not found" : "down");
  1312. goto free;
  1313. }
  1314. if (dp_monitor_filter_neighbour_peer(pdev, rx_pkt_hdr) ==
  1315. QDF_STATUS_SUCCESS)
  1316. return 0;
  1317. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  1318. if (qdf_mem_cmp(wh->i_addr1, vdev->mac_addr.raw,
  1319. QDF_MAC_ADDR_SIZE) == 0) {
  1320. goto out;
  1321. }
  1322. }
  1323. }
  1324. if (!vdev) {
  1325. dp_rx_err("%pK: VDEV not found", soc);
  1326. goto free;
  1327. }
  1328. out:
  1329. msg.wh = wh;
  1330. qdf_nbuf_pull_head(mpdu, soc->rx_pkt_tlv_size);
  1331. msg.nbuf = mpdu;
  1332. msg.vdev_id = vdev->vdev_id;
  1333. /*
  1334. * NOTE: Only valid for HKv1.
  1335. * If smart monitor mode is enabled on RE, we are getting invalid
  1336. * peer frames with RA as STA mac of RE and the TA not matching
  1337. * with any NAC list or the the BSSID.Such frames need to dropped
  1338. * in order to avoid HM_WDS false addition.
  1339. */
  1340. if (pdev->soc->cdp_soc.ol_ops->rx_invalid_peer) {
  1341. if (dp_monitor_drop_inv_peer_pkts(vdev) == QDF_STATUS_SUCCESS) {
  1342. dp_rx_warn("%pK: Drop inv peer pkts with STA RA:%pm",
  1343. soc, wh->i_addr1);
  1344. goto free;
  1345. }
  1346. pdev->soc->cdp_soc.ol_ops->rx_invalid_peer(
  1347. (struct cdp_ctrl_objmgr_psoc *)soc->ctrl_psoc,
  1348. pdev->pdev_id, &msg);
  1349. }
  1350. free:
  1351. /* Drop and free packet */
  1352. curr_nbuf = mpdu;
  1353. while (curr_nbuf) {
  1354. next_nbuf = qdf_nbuf_next(curr_nbuf);
  1355. dp_rx_nbuf_free(curr_nbuf);
  1356. curr_nbuf = next_nbuf;
  1357. }
  1358. return 0;
  1359. }
  1360. void dp_rx_process_invalid_peer_wrapper(struct dp_soc *soc,
  1361. qdf_nbuf_t mpdu, bool mpdu_done,
  1362. uint8_t mac_id)
  1363. {
  1364. /* Only trigger the process when mpdu is completed */
  1365. if (mpdu_done)
  1366. dp_rx_process_invalid_peer(soc, mpdu, mac_id);
  1367. }
  1368. #else
  1369. uint8_t dp_rx_process_invalid_peer(struct dp_soc *soc, qdf_nbuf_t mpdu,
  1370. uint8_t mac_id)
  1371. {
  1372. qdf_nbuf_t curr_nbuf, next_nbuf;
  1373. struct dp_pdev *pdev;
  1374. struct dp_vdev *vdev = NULL;
  1375. struct ieee80211_frame *wh;
  1376. struct dp_peer *peer = NULL;
  1377. uint8_t *rx_tlv_hdr = qdf_nbuf_data(mpdu);
  1378. uint8_t *rx_pkt_hdr = hal_rx_pkt_hdr_get(soc->hal_soc, rx_tlv_hdr);
  1379. uint32_t nbuf_len;
  1380. wh = (struct ieee80211_frame *)rx_pkt_hdr;
  1381. if (!DP_FRAME_IS_DATA(wh)) {
  1382. QDF_TRACE_ERROR_RL(QDF_MODULE_ID_DP,
  1383. "only for data frames");
  1384. goto free;
  1385. }
  1386. nbuf_len = qdf_nbuf_len(mpdu);
  1387. if (nbuf_len < sizeof(struct ieee80211_frame)) {
  1388. dp_rx_info_rl("%pK: Invalid nbuf length: %u", soc, nbuf_len);
  1389. goto free;
  1390. }
  1391. pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  1392. if (!pdev) {
  1393. dp_rx_info_rl("%pK: PDEV not found", soc);
  1394. goto free;
  1395. }
  1396. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  1397. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1398. if (qdf_mem_cmp(wh->i_addr1, vdev->mac_addr.raw,
  1399. QDF_MAC_ADDR_SIZE) == 0) {
  1400. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  1401. goto out;
  1402. }
  1403. }
  1404. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  1405. if (!vdev) {
  1406. dp_rx_info_rl("%pK: VDEV not found", soc);
  1407. goto free;
  1408. }
  1409. out:
  1410. if (vdev->opmode == wlan_op_mode_ap) {
  1411. peer = dp_peer_find_hash_find(soc, wh->i_addr2, 0,
  1412. vdev->vdev_id,
  1413. DP_MOD_ID_RX_ERR);
  1414. /* If SA is a valid peer in vdev,
  1415. * don't send disconnect
  1416. */
  1417. if (peer) {
  1418. dp_peer_unref_delete(peer, DP_MOD_ID_RX_ERR);
  1419. DP_STATS_INC(soc, rx.err.decrypt_err_drop, 1);
  1420. dp_err_rl("invalid peer frame with correct SA/RA is freed");
  1421. goto free;
  1422. }
  1423. }
  1424. if (soc->cdp_soc.ol_ops->rx_invalid_peer)
  1425. soc->cdp_soc.ol_ops->rx_invalid_peer(vdev->vdev_id, wh);
  1426. free:
  1427. /* Drop and free packet */
  1428. curr_nbuf = mpdu;
  1429. while (curr_nbuf) {
  1430. next_nbuf = qdf_nbuf_next(curr_nbuf);
  1431. dp_rx_nbuf_free(curr_nbuf);
  1432. curr_nbuf = next_nbuf;
  1433. }
  1434. /* Reset the head and tail pointers */
  1435. pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
  1436. if (pdev) {
  1437. pdev->invalid_peer_head_msdu = NULL;
  1438. pdev->invalid_peer_tail_msdu = NULL;
  1439. }
  1440. return 0;
  1441. }
  1442. void dp_rx_process_invalid_peer_wrapper(struct dp_soc *soc,
  1443. qdf_nbuf_t mpdu, bool mpdu_done,
  1444. uint8_t mac_id)
  1445. {
  1446. /* Process the nbuf */
  1447. dp_rx_process_invalid_peer(soc, mpdu, mac_id);
  1448. }
  1449. #endif
  1450. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1451. #ifdef RECEIVE_OFFLOAD
  1452. /**
  1453. * dp_rx_print_offload_info() - Print offload info from RX TLV
  1454. * @soc: dp soc handle
  1455. * @msdu: MSDU for which the offload info is to be printed
  1456. *
  1457. * Return: None
  1458. */
  1459. static void dp_rx_print_offload_info(struct dp_soc *soc,
  1460. qdf_nbuf_t msdu)
  1461. {
  1462. dp_verbose_debug("----------------------RX DESC LRO/GRO----------------------");
  1463. dp_verbose_debug("lro_eligible 0x%x",
  1464. QDF_NBUF_CB_RX_LRO_ELIGIBLE(msdu));
  1465. dp_verbose_debug("pure_ack 0x%x", QDF_NBUF_CB_RX_TCP_PURE_ACK(msdu));
  1466. dp_verbose_debug("chksum 0x%x", QDF_NBUF_CB_RX_TCP_CHKSUM(msdu));
  1467. dp_verbose_debug("TCP seq num 0x%x", QDF_NBUF_CB_RX_TCP_SEQ_NUM(msdu));
  1468. dp_verbose_debug("TCP ack num 0x%x", QDF_NBUF_CB_RX_TCP_ACK_NUM(msdu));
  1469. dp_verbose_debug("TCP window 0x%x", QDF_NBUF_CB_RX_TCP_WIN(msdu));
  1470. dp_verbose_debug("TCP protocol 0x%x", QDF_NBUF_CB_RX_TCP_PROTO(msdu));
  1471. dp_verbose_debug("TCP offset 0x%x", QDF_NBUF_CB_RX_TCP_OFFSET(msdu));
  1472. dp_verbose_debug("toeplitz 0x%x", QDF_NBUF_CB_RX_FLOW_ID(msdu));
  1473. dp_verbose_debug("---------------------------------------------------------");
  1474. }
  1475. void dp_rx_fill_gro_info(struct dp_soc *soc, uint8_t *rx_tlv,
  1476. qdf_nbuf_t msdu, uint32_t *rx_ol_pkt_cnt)
  1477. {
  1478. struct hal_offload_info offload_info;
  1479. if (!wlan_cfg_is_gro_enabled(soc->wlan_cfg_ctx))
  1480. return;
  1481. if (hal_rx_tlv_get_offload_info(soc->hal_soc, rx_tlv, &offload_info))
  1482. return;
  1483. *rx_ol_pkt_cnt = *rx_ol_pkt_cnt + 1;
  1484. QDF_NBUF_CB_RX_LRO_ELIGIBLE(msdu) = offload_info.lro_eligible;
  1485. QDF_NBUF_CB_RX_TCP_PURE_ACK(msdu) = offload_info.tcp_pure_ack;
  1486. QDF_NBUF_CB_RX_TCP_CHKSUM(msdu) =
  1487. hal_rx_tlv_get_tcp_chksum(soc->hal_soc,
  1488. rx_tlv);
  1489. QDF_NBUF_CB_RX_TCP_SEQ_NUM(msdu) = offload_info.tcp_seq_num;
  1490. QDF_NBUF_CB_RX_TCP_ACK_NUM(msdu) = offload_info.tcp_ack_num;
  1491. QDF_NBUF_CB_RX_TCP_WIN(msdu) = offload_info.tcp_win;
  1492. QDF_NBUF_CB_RX_TCP_PROTO(msdu) = offload_info.tcp_proto;
  1493. QDF_NBUF_CB_RX_IPV6_PROTO(msdu) = offload_info.ipv6_proto;
  1494. QDF_NBUF_CB_RX_TCP_OFFSET(msdu) = offload_info.tcp_offset;
  1495. QDF_NBUF_CB_RX_FLOW_ID(msdu) = offload_info.flow_id;
  1496. dp_rx_print_offload_info(soc, msdu);
  1497. }
  1498. #endif /* RECEIVE_OFFLOAD */
  1499. /**
  1500. * dp_rx_adjust_nbuf_len() - set appropriate msdu length in nbuf.
  1501. *
  1502. * @soc: DP soc handle
  1503. * @nbuf: pointer to msdu.
  1504. * @mpdu_len: mpdu length
  1505. * @l3_pad_len: L3 padding length by HW
  1506. *
  1507. * Return: returns true if nbuf is last msdu of mpdu else returns false.
  1508. */
  1509. static inline bool dp_rx_adjust_nbuf_len(struct dp_soc *soc,
  1510. qdf_nbuf_t nbuf,
  1511. uint16_t *mpdu_len,
  1512. uint32_t l3_pad_len)
  1513. {
  1514. bool last_nbuf;
  1515. uint32_t pkt_hdr_size;
  1516. pkt_hdr_size = soc->rx_pkt_tlv_size + l3_pad_len;
  1517. if ((*mpdu_len + pkt_hdr_size) > RX_DATA_BUFFER_SIZE) {
  1518. qdf_nbuf_set_pktlen(nbuf, RX_DATA_BUFFER_SIZE);
  1519. last_nbuf = false;
  1520. *mpdu_len -= (RX_DATA_BUFFER_SIZE - pkt_hdr_size);
  1521. } else {
  1522. qdf_nbuf_set_pktlen(nbuf, (*mpdu_len + pkt_hdr_size));
  1523. last_nbuf = true;
  1524. *mpdu_len = 0;
  1525. }
  1526. return last_nbuf;
  1527. }
  1528. /**
  1529. * dp_get_l3_hdr_pad_len() - get L3 header padding length.
  1530. *
  1531. * @soc: DP soc handle
  1532. * @nbuf: pointer to msdu.
  1533. *
  1534. * Return: returns padding length in bytes.
  1535. */
  1536. static inline uint32_t dp_get_l3_hdr_pad_len(struct dp_soc *soc,
  1537. qdf_nbuf_t nbuf)
  1538. {
  1539. uint32_t l3_hdr_pad = 0;
  1540. uint8_t *rx_tlv_hdr;
  1541. struct hal_rx_msdu_metadata msdu_metadata;
  1542. while (nbuf) {
  1543. if (!qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  1544. /* scattered msdu end with continuation is 0 */
  1545. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  1546. hal_rx_msdu_metadata_get(soc->hal_soc,
  1547. rx_tlv_hdr,
  1548. &msdu_metadata);
  1549. l3_hdr_pad = msdu_metadata.l3_hdr_pad;
  1550. break;
  1551. }
  1552. nbuf = nbuf->next;
  1553. }
  1554. return l3_hdr_pad;
  1555. }
  1556. qdf_nbuf_t dp_rx_sg_create(struct dp_soc *soc, qdf_nbuf_t nbuf)
  1557. {
  1558. qdf_nbuf_t parent, frag_list, next = NULL;
  1559. uint16_t frag_list_len = 0;
  1560. uint16_t mpdu_len;
  1561. bool last_nbuf;
  1562. uint32_t l3_hdr_pad_offset = 0;
  1563. /*
  1564. * Use msdu len got from REO entry descriptor instead since
  1565. * there is case the RX PKT TLV is corrupted while msdu_len
  1566. * from REO descriptor is right for non-raw RX scatter msdu.
  1567. */
  1568. mpdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  1569. /*
  1570. * this is a case where the complete msdu fits in one single nbuf.
  1571. * in this case HW sets both start and end bit and we only need to
  1572. * reset these bits for RAW mode simulator to decap the pkt
  1573. */
  1574. if (qdf_nbuf_is_rx_chfrag_start(nbuf) &&
  1575. qdf_nbuf_is_rx_chfrag_end(nbuf)) {
  1576. qdf_nbuf_set_pktlen(nbuf, mpdu_len + soc->rx_pkt_tlv_size);
  1577. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  1578. return nbuf;
  1579. }
  1580. l3_hdr_pad_offset = dp_get_l3_hdr_pad_len(soc, nbuf);
  1581. /*
  1582. * This is a case where we have multiple msdus (A-MSDU) spread across
  1583. * multiple nbufs. here we create a fraglist out of these nbufs.
  1584. *
  1585. * the moment we encounter a nbuf with continuation bit set we
  1586. * know for sure we have an MSDU which is spread across multiple
  1587. * nbufs. We loop through and reap nbufs till we reach last nbuf.
  1588. */
  1589. parent = nbuf;
  1590. frag_list = nbuf->next;
  1591. nbuf = nbuf->next;
  1592. /*
  1593. * set the start bit in the first nbuf we encounter with continuation
  1594. * bit set. This has the proper mpdu length set as it is the first
  1595. * msdu of the mpdu. this becomes the parent nbuf and the subsequent
  1596. * nbufs will form the frag_list of the parent nbuf.
  1597. */
  1598. qdf_nbuf_set_rx_chfrag_start(parent, 1);
  1599. /*
  1600. * L3 header padding is only needed for the 1st buffer
  1601. * in a scattered msdu
  1602. */
  1603. last_nbuf = dp_rx_adjust_nbuf_len(soc, parent, &mpdu_len,
  1604. l3_hdr_pad_offset);
  1605. /*
  1606. * MSDU cont bit is set but reported MPDU length can fit
  1607. * in to single buffer
  1608. *
  1609. * Increment error stats and avoid SG list creation
  1610. */
  1611. if (last_nbuf) {
  1612. DP_STATS_INC(soc, rx.err.msdu_continuation_err, 1);
  1613. qdf_nbuf_pull_head(parent,
  1614. soc->rx_pkt_tlv_size + l3_hdr_pad_offset);
  1615. return parent;
  1616. }
  1617. /*
  1618. * this is where we set the length of the fragments which are
  1619. * associated to the parent nbuf. We iterate through the frag_list
  1620. * till we hit the last_nbuf of the list.
  1621. */
  1622. do {
  1623. last_nbuf = dp_rx_adjust_nbuf_len(soc, nbuf, &mpdu_len, 0);
  1624. qdf_nbuf_pull_head(nbuf,
  1625. soc->rx_pkt_tlv_size);
  1626. frag_list_len += qdf_nbuf_len(nbuf);
  1627. if (last_nbuf) {
  1628. next = nbuf->next;
  1629. nbuf->next = NULL;
  1630. break;
  1631. } else if (qdf_nbuf_is_rx_chfrag_end(nbuf)) {
  1632. dp_err("Invalid packet length");
  1633. qdf_assert_always(0);
  1634. }
  1635. nbuf = nbuf->next;
  1636. } while (!last_nbuf);
  1637. qdf_nbuf_set_rx_chfrag_start(nbuf, 0);
  1638. qdf_nbuf_append_ext_list(parent, frag_list, frag_list_len);
  1639. parent->next = next;
  1640. qdf_nbuf_pull_head(parent,
  1641. soc->rx_pkt_tlv_size + l3_hdr_pad_offset);
  1642. return parent;
  1643. }
  1644. #ifdef DP_RX_SG_FRAME_SUPPORT
  1645. bool dp_rx_is_sg_supported(void)
  1646. {
  1647. return true;
  1648. }
  1649. #else
  1650. bool dp_rx_is_sg_supported(void)
  1651. {
  1652. return false;
  1653. }
  1654. #endif
  1655. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  1656. #ifdef QCA_PEER_EXT_STATS
  1657. void dp_rx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  1658. qdf_nbuf_t nbuf)
  1659. {
  1660. struct cdp_delay_rx_stats *rx_delay = &stats->rx_delay;
  1661. uint32_t to_stack = qdf_nbuf_get_timedelta_ms(nbuf);
  1662. dp_hist_update_stats(&rx_delay->to_stack_delay, to_stack);
  1663. }
  1664. #endif /* QCA_PEER_EXT_STATS */
  1665. void dp_rx_compute_delay(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1666. {
  1667. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1668. int64_t current_ts = qdf_ktime_to_ms(qdf_ktime_get());
  1669. uint32_t to_stack = qdf_nbuf_get_timedelta_ms(nbuf);
  1670. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1671. uint32_t interframe_delay =
  1672. (uint32_t)(current_ts - vdev->prev_rx_deliver_tstamp);
  1673. struct cdp_tid_rx_stats *rstats =
  1674. &vdev->pdev->stats.tid_stats.tid_rx_stats[ring_id][tid];
  1675. dp_update_delay_stats(NULL, rstats, to_stack, tid,
  1676. CDP_DELAY_STATS_REAP_STACK, ring_id, false);
  1677. /*
  1678. * Update interframe delay stats calculated at deliver_data_ol point.
  1679. * Value of vdev->prev_rx_deliver_tstamp will be 0 for 1st frame, so
  1680. * interframe delay will not be calculate correctly for 1st frame.
  1681. * On the other side, this will help in avoiding extra per packet check
  1682. * of vdev->prev_rx_deliver_tstamp.
  1683. */
  1684. dp_update_delay_stats(NULL, rstats, interframe_delay, tid,
  1685. CDP_DELAY_STATS_RX_INTERFRAME, ring_id, false);
  1686. vdev->prev_rx_deliver_tstamp = current_ts;
  1687. }
  1688. /**
  1689. * dp_rx_drop_nbuf_list() - drop an nbuf list
  1690. * @pdev: dp pdev reference
  1691. * @buf_list: buffer list to be dropepd
  1692. *
  1693. * Return: int (number of bufs dropped)
  1694. */
  1695. static inline int dp_rx_drop_nbuf_list(struct dp_pdev *pdev,
  1696. qdf_nbuf_t buf_list)
  1697. {
  1698. struct cdp_tid_rx_stats *stats = NULL;
  1699. uint8_t tid = 0, ring_id = 0;
  1700. int num_dropped = 0;
  1701. qdf_nbuf_t buf, next_buf;
  1702. buf = buf_list;
  1703. while (buf) {
  1704. ring_id = QDF_NBUF_CB_RX_CTX_ID(buf);
  1705. next_buf = qdf_nbuf_queue_next(buf);
  1706. tid = qdf_nbuf_get_tid_val(buf);
  1707. if (qdf_likely(pdev)) {
  1708. stats = &pdev->stats.tid_stats.tid_rx_stats[ring_id][tid];
  1709. stats->fail_cnt[INVALID_PEER_VDEV]++;
  1710. stats->delivered_to_stack--;
  1711. }
  1712. dp_rx_nbuf_free(buf);
  1713. buf = next_buf;
  1714. num_dropped++;
  1715. }
  1716. return num_dropped;
  1717. }
  1718. #ifdef QCA_SUPPORT_WDS_EXTENDED
  1719. /**
  1720. * dp_rx_deliver_to_stack_ext() - Deliver to netdev per sta
  1721. * @soc: core txrx main context
  1722. * @vdev: vdev
  1723. * @txrx_peer: txrx peer
  1724. * @nbuf_head: skb list head
  1725. *
  1726. * Return: true if packet is delivered to netdev per STA.
  1727. */
  1728. static inline bool
  1729. dp_rx_deliver_to_stack_ext(struct dp_soc *soc, struct dp_vdev *vdev,
  1730. struct dp_txrx_peer *txrx_peer, qdf_nbuf_t nbuf_head)
  1731. {
  1732. /*
  1733. * When extended WDS is disabled, frames are sent to AP netdevice.
  1734. */
  1735. if (qdf_likely(!vdev->wds_ext_enabled))
  1736. return false;
  1737. /*
  1738. * There can be 2 cases:
  1739. * 1. Send frame to parent netdev if its not for netdev per STA
  1740. * 2. If frame is meant for netdev per STA:
  1741. * a. Send frame to appropriate netdev using registered fp.
  1742. * b. If fp is NULL, drop the frames.
  1743. */
  1744. if (!txrx_peer->wds_ext.init)
  1745. return false;
  1746. if (txrx_peer->osif_rx)
  1747. txrx_peer->osif_rx(txrx_peer->wds_ext.osif_peer, nbuf_head);
  1748. else
  1749. dp_rx_drop_nbuf_list(vdev->pdev, nbuf_head);
  1750. return true;
  1751. }
  1752. #else
  1753. static inline bool
  1754. dp_rx_deliver_to_stack_ext(struct dp_soc *soc, struct dp_vdev *vdev,
  1755. struct dp_txrx_peer *txrx_peer, qdf_nbuf_t nbuf_head)
  1756. {
  1757. return false;
  1758. }
  1759. #endif
  1760. #ifdef PEER_CACHE_RX_PKTS
  1761. void dp_rx_flush_rx_cached(struct dp_peer *peer, bool drop)
  1762. {
  1763. struct dp_peer_cached_bufq *bufqi;
  1764. struct dp_rx_cached_buf *cache_buf = NULL;
  1765. ol_txrx_rx_fp data_rx = NULL;
  1766. int num_buff_elem;
  1767. QDF_STATUS status;
  1768. /*
  1769. * Flush dp cached frames only for mld peers and legacy peers, as
  1770. * link peers don't store cached frames
  1771. */
  1772. if (IS_MLO_DP_LINK_PEER(peer))
  1773. return;
  1774. if (!peer->txrx_peer) {
  1775. dp_err("txrx_peer NULL!! peer mac_addr("QDF_MAC_ADDR_FMT")",
  1776. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1777. return;
  1778. }
  1779. if (qdf_atomic_inc_return(&peer->txrx_peer->flush_in_progress) > 1) {
  1780. qdf_atomic_dec(&peer->txrx_peer->flush_in_progress);
  1781. return;
  1782. }
  1783. qdf_spin_lock_bh(&peer->peer_info_lock);
  1784. if (peer->state >= OL_TXRX_PEER_STATE_CONN && peer->vdev->osif_rx)
  1785. data_rx = peer->vdev->osif_rx;
  1786. else
  1787. drop = true;
  1788. qdf_spin_unlock_bh(&peer->peer_info_lock);
  1789. bufqi = &peer->txrx_peer->bufq_info;
  1790. qdf_spin_lock_bh(&bufqi->bufq_lock);
  1791. qdf_list_remove_front(&bufqi->cached_bufq,
  1792. (qdf_list_node_t **)&cache_buf);
  1793. while (cache_buf) {
  1794. num_buff_elem = QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(
  1795. cache_buf->buf);
  1796. bufqi->entries -= num_buff_elem;
  1797. qdf_spin_unlock_bh(&bufqi->bufq_lock);
  1798. if (drop) {
  1799. bufqi->dropped = dp_rx_drop_nbuf_list(peer->vdev->pdev,
  1800. cache_buf->buf);
  1801. } else {
  1802. /* Flush the cached frames to OSIF DEV */
  1803. status = data_rx(peer->vdev->osif_vdev, cache_buf->buf);
  1804. if (status != QDF_STATUS_SUCCESS)
  1805. bufqi->dropped = dp_rx_drop_nbuf_list(
  1806. peer->vdev->pdev,
  1807. cache_buf->buf);
  1808. }
  1809. qdf_mem_free(cache_buf);
  1810. cache_buf = NULL;
  1811. qdf_spin_lock_bh(&bufqi->bufq_lock);
  1812. qdf_list_remove_front(&bufqi->cached_bufq,
  1813. (qdf_list_node_t **)&cache_buf);
  1814. }
  1815. qdf_spin_unlock_bh(&bufqi->bufq_lock);
  1816. qdf_atomic_dec(&peer->txrx_peer->flush_in_progress);
  1817. }
  1818. /**
  1819. * dp_rx_enqueue_rx() - cache rx frames
  1820. * @peer: peer
  1821. * @txrx_peer: DP txrx_peer
  1822. * @rx_buf_list: cache buffer list
  1823. *
  1824. * Return: None
  1825. */
  1826. static QDF_STATUS
  1827. dp_rx_enqueue_rx(struct dp_peer *peer,
  1828. struct dp_txrx_peer *txrx_peer,
  1829. qdf_nbuf_t rx_buf_list)
  1830. {
  1831. struct dp_rx_cached_buf *cache_buf;
  1832. struct dp_peer_cached_bufq *bufqi = &txrx_peer->bufq_info;
  1833. int num_buff_elem;
  1834. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  1835. struct dp_soc *soc = txrx_peer->vdev->pdev->soc;
  1836. struct dp_peer *ta_peer = NULL;
  1837. /*
  1838. * If peer id is invalid which likely peer map has not completed,
  1839. * then need caller provide dp_peer pointer, else it's ok to use
  1840. * txrx_peer->peer_id to get dp_peer.
  1841. */
  1842. if (peer) {
  1843. if (QDF_STATUS_SUCCESS ==
  1844. dp_peer_get_ref(soc, peer, DP_MOD_ID_RX))
  1845. ta_peer = peer;
  1846. } else {
  1847. ta_peer = dp_peer_get_ref_by_id(soc, txrx_peer->peer_id,
  1848. DP_MOD_ID_RX);
  1849. }
  1850. if (!ta_peer) {
  1851. bufqi->dropped = dp_rx_drop_nbuf_list(txrx_peer->vdev->pdev,
  1852. rx_buf_list);
  1853. return QDF_STATUS_E_INVAL;
  1854. }
  1855. dp_debug_rl("bufq->curr %d bufq->drops %d", bufqi->entries,
  1856. bufqi->dropped);
  1857. if (!ta_peer->valid) {
  1858. bufqi->dropped = dp_rx_drop_nbuf_list(txrx_peer->vdev->pdev,
  1859. rx_buf_list);
  1860. ret = QDF_STATUS_E_INVAL;
  1861. goto fail;
  1862. }
  1863. qdf_spin_lock_bh(&bufqi->bufq_lock);
  1864. if (bufqi->entries >= bufqi->thresh) {
  1865. bufqi->dropped = dp_rx_drop_nbuf_list(txrx_peer->vdev->pdev,
  1866. rx_buf_list);
  1867. qdf_spin_unlock_bh(&bufqi->bufq_lock);
  1868. ret = QDF_STATUS_E_RESOURCES;
  1869. goto fail;
  1870. }
  1871. qdf_spin_unlock_bh(&bufqi->bufq_lock);
  1872. num_buff_elem = QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(rx_buf_list);
  1873. cache_buf = qdf_mem_malloc_atomic(sizeof(*cache_buf));
  1874. if (!cache_buf) {
  1875. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1876. "Failed to allocate buf to cache rx frames");
  1877. bufqi->dropped = dp_rx_drop_nbuf_list(txrx_peer->vdev->pdev,
  1878. rx_buf_list);
  1879. ret = QDF_STATUS_E_NOMEM;
  1880. goto fail;
  1881. }
  1882. cache_buf->buf = rx_buf_list;
  1883. qdf_spin_lock_bh(&bufqi->bufq_lock);
  1884. qdf_list_insert_back(&bufqi->cached_bufq,
  1885. &cache_buf->node);
  1886. bufqi->entries += num_buff_elem;
  1887. qdf_spin_unlock_bh(&bufqi->bufq_lock);
  1888. fail:
  1889. dp_peer_unref_delete(ta_peer, DP_MOD_ID_RX);
  1890. return ret;
  1891. }
  1892. static inline
  1893. bool dp_rx_is_peer_cache_bufq_supported(void)
  1894. {
  1895. return true;
  1896. }
  1897. #else
  1898. static inline
  1899. bool dp_rx_is_peer_cache_bufq_supported(void)
  1900. {
  1901. return false;
  1902. }
  1903. static inline QDF_STATUS
  1904. dp_rx_enqueue_rx(struct dp_peer *peer,
  1905. struct dp_txrx_peer *txrx_peer,
  1906. qdf_nbuf_t rx_buf_list)
  1907. {
  1908. return QDF_STATUS_SUCCESS;
  1909. }
  1910. #endif
  1911. #ifndef DELIVERY_TO_STACK_STATUS_CHECK
  1912. /**
  1913. * dp_rx_check_delivery_to_stack() - Deliver pkts to network
  1914. * using the appropriate call back functions.
  1915. * @soc: soc
  1916. * @vdev: vdev
  1917. * @txrx_peer: peer
  1918. * @nbuf_head: skb list head
  1919. *
  1920. * Return: None
  1921. */
  1922. static void dp_rx_check_delivery_to_stack(struct dp_soc *soc,
  1923. struct dp_vdev *vdev,
  1924. struct dp_txrx_peer *txrx_peer,
  1925. qdf_nbuf_t nbuf_head)
  1926. {
  1927. if (qdf_unlikely(dp_rx_deliver_to_stack_ext(soc, vdev,
  1928. txrx_peer, nbuf_head)))
  1929. return;
  1930. /* Function pointer initialized only when FISA is enabled */
  1931. if (vdev->osif_fisa_rx)
  1932. /* on failure send it via regular path */
  1933. vdev->osif_fisa_rx(soc, vdev, nbuf_head);
  1934. else
  1935. vdev->osif_rx(vdev->osif_vdev, nbuf_head);
  1936. }
  1937. #else
  1938. /**
  1939. * dp_rx_check_delivery_to_stack() - Deliver pkts to network
  1940. * using the appropriate call back functions.
  1941. * @soc: soc
  1942. * @vdev: vdev
  1943. * @txrx_peer: txrx peer
  1944. * @nbuf_head: skb list head
  1945. *
  1946. * Check the return status of the call back function and drop
  1947. * the packets if the return status indicates a failure.
  1948. *
  1949. * Return: None
  1950. */
  1951. static void dp_rx_check_delivery_to_stack(struct dp_soc *soc,
  1952. struct dp_vdev *vdev,
  1953. struct dp_txrx_peer *txrx_peer,
  1954. qdf_nbuf_t nbuf_head)
  1955. {
  1956. int num_nbuf = 0;
  1957. QDF_STATUS ret_val = QDF_STATUS_E_FAILURE;
  1958. /* Function pointer initialized only when FISA is enabled */
  1959. if (vdev->osif_fisa_rx)
  1960. /* on failure send it via regular path */
  1961. ret_val = vdev->osif_fisa_rx(soc, vdev, nbuf_head);
  1962. else if (vdev->osif_rx)
  1963. ret_val = vdev->osif_rx(vdev->osif_vdev, nbuf_head);
  1964. if (!QDF_IS_STATUS_SUCCESS(ret_val)) {
  1965. num_nbuf = dp_rx_drop_nbuf_list(vdev->pdev, nbuf_head);
  1966. DP_STATS_INC(soc, rx.err.rejected, num_nbuf);
  1967. if (txrx_peer)
  1968. DP_PEER_STATS_FLAT_DEC(txrx_peer, to_stack.num,
  1969. num_nbuf);
  1970. }
  1971. }
  1972. #endif /* ifdef DELIVERY_TO_STACK_STATUS_CHECK */
  1973. /**
  1974. * dp_rx_validate_rx_callbacks() - validate rx callbacks
  1975. * @soc: DP soc
  1976. * @vdev: DP vdev handle
  1977. * @txrx_peer: pointer to the txrx peer object
  1978. * @nbuf_head: skb list head
  1979. *
  1980. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  1981. * QDF_STATUS_E_FAILURE
  1982. */
  1983. static inline QDF_STATUS
  1984. dp_rx_validate_rx_callbacks(struct dp_soc *soc,
  1985. struct dp_vdev *vdev,
  1986. struct dp_txrx_peer *txrx_peer,
  1987. qdf_nbuf_t nbuf_head)
  1988. {
  1989. int num_nbuf;
  1990. if (qdf_unlikely(!vdev || vdev->delete.pending)) {
  1991. num_nbuf = dp_rx_drop_nbuf_list(NULL, nbuf_head);
  1992. /*
  1993. * This is a special case where vdev is invalid,
  1994. * so we cannot know the pdev to which this packet
  1995. * belonged. Hence we update the soc rx error stats.
  1996. */
  1997. DP_STATS_INC(soc, rx.err.invalid_vdev, num_nbuf);
  1998. return QDF_STATUS_E_FAILURE;
  1999. }
  2000. /*
  2001. * highly unlikely to have a vdev without a registered rx
  2002. * callback function. if so let us free the nbuf_list.
  2003. */
  2004. if (qdf_unlikely(!vdev->osif_rx)) {
  2005. if (txrx_peer && dp_rx_is_peer_cache_bufq_supported()) {
  2006. dp_rx_enqueue_rx(NULL, txrx_peer, nbuf_head);
  2007. } else {
  2008. num_nbuf = dp_rx_drop_nbuf_list(vdev->pdev,
  2009. nbuf_head);
  2010. DP_PEER_TO_STACK_DECC(txrx_peer, num_nbuf,
  2011. vdev->pdev->enhanced_stats_en);
  2012. }
  2013. return QDF_STATUS_E_FAILURE;
  2014. }
  2015. return QDF_STATUS_SUCCESS;
  2016. }
  2017. #if defined(WLAN_FEATURE_11BE_MLO) && defined(RAW_PKT_MLD_ADDR_CONVERSION)
  2018. static void dp_rx_raw_pkt_mld_addr_conv(struct dp_soc *soc,
  2019. struct dp_vdev *vdev,
  2020. struct dp_txrx_peer *txrx_peer,
  2021. qdf_nbuf_t nbuf_head)
  2022. {
  2023. qdf_nbuf_t nbuf, next;
  2024. struct dp_peer *peer = NULL;
  2025. struct ieee80211_frame *wh = NULL;
  2026. if (vdev->rx_decap_type == htt_cmn_pkt_type_native_wifi)
  2027. return;
  2028. peer = dp_peer_get_ref_by_id(soc, txrx_peer->peer_id,
  2029. DP_MOD_ID_RX);
  2030. if (!peer)
  2031. return;
  2032. if (!IS_MLO_DP_MLD_PEER(peer)) {
  2033. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  2034. return;
  2035. }
  2036. nbuf = nbuf_head;
  2037. while (nbuf) {
  2038. next = nbuf->next;
  2039. wh = (struct ieee80211_frame *)qdf_nbuf_data(nbuf);
  2040. qdf_mem_copy(wh->i_addr1, vdev->mld_mac_addr.raw,
  2041. QDF_MAC_ADDR_SIZE);
  2042. qdf_mem_copy(wh->i_addr2, peer->mac_addr.raw,
  2043. QDF_MAC_ADDR_SIZE);
  2044. nbuf = next;
  2045. }
  2046. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  2047. }
  2048. #else
  2049. static inline
  2050. void dp_rx_raw_pkt_mld_addr_conv(struct dp_soc *soc,
  2051. struct dp_vdev *vdev,
  2052. struct dp_txrx_peer *txrx_peer,
  2053. qdf_nbuf_t nbuf_head)
  2054. { }
  2055. #endif
  2056. QDF_STATUS dp_rx_deliver_to_stack(struct dp_soc *soc,
  2057. struct dp_vdev *vdev,
  2058. struct dp_txrx_peer *txrx_peer,
  2059. qdf_nbuf_t nbuf_head,
  2060. qdf_nbuf_t nbuf_tail)
  2061. {
  2062. if (dp_rx_validate_rx_callbacks(soc, vdev, txrx_peer, nbuf_head) !=
  2063. QDF_STATUS_SUCCESS)
  2064. return QDF_STATUS_E_FAILURE;
  2065. if (qdf_unlikely(vdev->rx_decap_type == htt_cmn_pkt_type_raw) ||
  2066. (vdev->rx_decap_type == htt_cmn_pkt_type_native_wifi)) {
  2067. dp_rx_raw_pkt_mld_addr_conv(soc, vdev, txrx_peer, nbuf_head);
  2068. vdev->osif_rsim_rx_decap(vdev->osif_vdev, &nbuf_head,
  2069. &nbuf_tail);
  2070. }
  2071. dp_rx_check_delivery_to_stack(soc, vdev, txrx_peer, nbuf_head);
  2072. return QDF_STATUS_SUCCESS;
  2073. }
  2074. #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT
  2075. QDF_STATUS dp_rx_eapol_deliver_to_stack(struct dp_soc *soc,
  2076. struct dp_vdev *vdev,
  2077. struct dp_txrx_peer *txrx_peer,
  2078. qdf_nbuf_t nbuf_head,
  2079. qdf_nbuf_t nbuf_tail)
  2080. {
  2081. if (dp_rx_validate_rx_callbacks(soc, vdev, txrx_peer, nbuf_head) !=
  2082. QDF_STATUS_SUCCESS)
  2083. return QDF_STATUS_E_FAILURE;
  2084. vdev->osif_rx_eapol(vdev->osif_vdev, nbuf_head);
  2085. return QDF_STATUS_SUCCESS;
  2086. }
  2087. #endif
  2088. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2089. #ifdef VDEV_PEER_PROTOCOL_COUNT
  2090. #define dp_rx_msdu_stats_update_prot_cnts(vdev_hdl, nbuf, txrx_peer) \
  2091. { \
  2092. qdf_nbuf_t nbuf_local; \
  2093. struct dp_txrx_peer *txrx_peer_local; \
  2094. struct dp_vdev *vdev_local = vdev_hdl; \
  2095. do { \
  2096. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  2097. break; \
  2098. nbuf_local = nbuf; \
  2099. txrx_peer_local = txrx_peer; \
  2100. if (qdf_unlikely(qdf_nbuf_is_frag((nbuf_local)))) \
  2101. break; \
  2102. else if (qdf_unlikely(qdf_nbuf_is_raw_frame((nbuf_local)))) \
  2103. break; \
  2104. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  2105. (nbuf_local), \
  2106. (txrx_peer_local), 0, 1); \
  2107. } while (0); \
  2108. }
  2109. #else
  2110. #define dp_rx_msdu_stats_update_prot_cnts(vdev_hdl, nbuf, txrx_peer)
  2111. #endif
  2112. #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER
  2113. /**
  2114. * dp_rx_rates_stats_update() - update rate stats
  2115. * from rx msdu.
  2116. * @soc: datapath soc handle
  2117. * @nbuf: received msdu buffer
  2118. * @rx_tlv_hdr: rx tlv header
  2119. * @txrx_peer: datapath txrx_peer handle
  2120. * @sgi: Short Guard Interval
  2121. * @mcs: Modulation and Coding Set
  2122. * @nss: Number of Spatial Streams
  2123. * @bw: BandWidth
  2124. * @pkt_type: Corresponds to preamble
  2125. * @link_id: Link Id on which packet is received
  2126. *
  2127. * To be precisely record rates, following factors are considered:
  2128. * Exclude specific frames, ARP, DHCP, ssdp, etc.
  2129. * Make sure to affect rx throughput as least as possible.
  2130. *
  2131. * Return: void
  2132. */
  2133. static void
  2134. dp_rx_rates_stats_update(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2135. uint8_t *rx_tlv_hdr, struct dp_txrx_peer *txrx_peer,
  2136. uint32_t sgi, uint32_t mcs,
  2137. uint32_t nss, uint32_t bw, uint32_t pkt_type,
  2138. uint8_t link_id)
  2139. {
  2140. uint32_t rix;
  2141. uint16_t ratecode;
  2142. uint32_t avg_rx_rate;
  2143. uint32_t ratekbps;
  2144. enum cdp_punctured_modes punc_mode = NO_PUNCTURE;
  2145. if (soc->high_throughput ||
  2146. dp_rx_data_is_specific(soc->hal_soc, rx_tlv_hdr, nbuf)) {
  2147. return;
  2148. }
  2149. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.rx_rate, mcs, link_id);
  2150. /* In 11b mode, the nss we get from tlv is 0, invalid and should be 1 */
  2151. if (qdf_unlikely(pkt_type == DOT11_B))
  2152. nss = 1;
  2153. /* here pkt_type corresponds to preamble */
  2154. ratekbps = dp_getrateindex(sgi,
  2155. mcs,
  2156. nss - 1,
  2157. pkt_type,
  2158. bw,
  2159. punc_mode,
  2160. &rix,
  2161. &ratecode);
  2162. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.last_rx_rate, ratekbps, link_id);
  2163. avg_rx_rate =
  2164. dp_ath_rate_lpf(
  2165. txrx_peer->stats[link_id].extd_stats.rx.avg_rx_rate,
  2166. ratekbps);
  2167. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.avg_rx_rate, avg_rx_rate, link_id);
  2168. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.nss_info, nss, link_id);
  2169. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.mcs_info, mcs, link_id);
  2170. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.bw_info, bw, link_id);
  2171. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.gi_info, sgi, link_id);
  2172. DP_PEER_EXTD_STATS_UPD(txrx_peer, rx.preamble_info, pkt_type, link_id);
  2173. }
  2174. #else
  2175. static inline void
  2176. dp_rx_rates_stats_update(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2177. uint8_t *rx_tlv_hdr, struct dp_txrx_peer *txrx_peer,
  2178. uint32_t sgi, uint32_t mcs,
  2179. uint32_t nss, uint32_t bw, uint32_t pkt_type,
  2180. uint8_t link_id)
  2181. {
  2182. }
  2183. #endif /* FEATURE_RX_LINKSPEED_ROAM_TRIGGER */
  2184. #ifndef QCA_ENHANCED_STATS_SUPPORT
  2185. /**
  2186. * dp_rx_msdu_extd_stats_update(): Update Rx extended path stats for peer
  2187. *
  2188. * @soc: datapath soc handle
  2189. * @nbuf: received msdu buffer
  2190. * @rx_tlv_hdr: rx tlv header
  2191. * @txrx_peer: datapath txrx_peer handle
  2192. * @link_id: link id on which the packet is received
  2193. *
  2194. * Return: void
  2195. */
  2196. static inline
  2197. void dp_rx_msdu_extd_stats_update(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2198. uint8_t *rx_tlv_hdr,
  2199. struct dp_txrx_peer *txrx_peer,
  2200. uint8_t link_id)
  2201. {
  2202. bool is_ampdu;
  2203. uint32_t sgi, mcs, tid, nss, bw, reception_type, pkt_type;
  2204. uint8_t dst_mcs_idx;
  2205. /*
  2206. * TODO - For KIWI this field is present in ring_desc
  2207. * Try to use ring desc instead of tlv.
  2208. */
  2209. is_ampdu = hal_rx_mpdu_info_ampdu_flag_get(soc->hal_soc, rx_tlv_hdr);
  2210. DP_PEER_EXTD_STATS_INCC(txrx_peer, rx.ampdu_cnt, 1, is_ampdu, link_id);
  2211. DP_PEER_EXTD_STATS_INCC(txrx_peer, rx.non_ampdu_cnt, 1, !(is_ampdu),
  2212. link_id);
  2213. sgi = hal_rx_tlv_sgi_get(soc->hal_soc, rx_tlv_hdr);
  2214. mcs = hal_rx_tlv_rate_mcs_get(soc->hal_soc, rx_tlv_hdr);
  2215. tid = qdf_nbuf_get_tid_val(nbuf);
  2216. bw = hal_rx_tlv_bw_get(soc->hal_soc, rx_tlv_hdr);
  2217. reception_type = hal_rx_msdu_start_reception_type_get(soc->hal_soc,
  2218. rx_tlv_hdr);
  2219. nss = hal_rx_msdu_start_nss_get(soc->hal_soc, rx_tlv_hdr);
  2220. pkt_type = hal_rx_tlv_get_pkt_type(soc->hal_soc, rx_tlv_hdr);
  2221. /* do HW to SW pkt type conversion */
  2222. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  2223. hal_2_dp_pkt_type_map[pkt_type]);
  2224. /*
  2225. * The MCS index does not start with 0 when NSS>1 in HT mode.
  2226. * MCS params for optional 20/40MHz, NSS=1~3, EQM(NSS>1):
  2227. * ------------------------------------------------------
  2228. * NSS | 1 | 2 | 3 | 4
  2229. * ------------------------------------------------------
  2230. * MCS index: HT20 | 0 ~ 7 | 8 ~ 15 | 16 ~ 23 | 24 ~ 31
  2231. * ------------------------------------------------------
  2232. * MCS index: HT40 | 0 ~ 7 | 8 ~ 15 | 16 ~ 23 | 24 ~ 31
  2233. * ------------------------------------------------------
  2234. * Currently, the MAX_NSS=2. If NSS>2, MCS index = 8 * (NSS-1)
  2235. */
  2236. if ((pkt_type == DOT11_N) && (nss == 2))
  2237. mcs += 8;
  2238. DP_PEER_EXTD_STATS_INCC(txrx_peer, rx.rx_mpdu_cnt[mcs], 1,
  2239. ((mcs < MAX_MCS) && QDF_NBUF_CB_RX_CHFRAG_START(nbuf)),
  2240. link_id);
  2241. DP_PEER_EXTD_STATS_INCC(txrx_peer, rx.rx_mpdu_cnt[MAX_MCS - 1], 1,
  2242. ((mcs >= MAX_MCS) && QDF_NBUF_CB_RX_CHFRAG_START(nbuf)),
  2243. link_id);
  2244. DP_PEER_EXTD_STATS_INC(txrx_peer, rx.bw[bw], 1, link_id);
  2245. /*
  2246. * only if nss > 0 and pkt_type is 11N/AC/AX,
  2247. * then increase index [nss - 1] in array counter.
  2248. */
  2249. if (nss > 0 && CDP_IS_PKT_TYPE_SUPPORT_NSS(pkt_type))
  2250. DP_PEER_EXTD_STATS_INC(txrx_peer, rx.nss[nss - 1], 1, link_id);
  2251. DP_PEER_EXTD_STATS_INC(txrx_peer, rx.sgi_count[sgi], 1, link_id);
  2252. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, rx.err.mic_err, 1,
  2253. hal_rx_tlv_mic_err_get(soc->hal_soc,
  2254. rx_tlv_hdr), link_id);
  2255. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, rx.err.decrypt_err, 1,
  2256. hal_rx_tlv_decrypt_err_get(soc->hal_soc,
  2257. rx_tlv_hdr), link_id);
  2258. DP_PEER_EXTD_STATS_INC(txrx_peer, rx.wme_ac_type[TID_TO_WME_AC(tid)], 1,
  2259. link_id);
  2260. DP_PEER_EXTD_STATS_INC(txrx_peer, rx.reception_type[reception_type], 1,
  2261. link_id);
  2262. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  2263. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  2264. DP_PEER_EXTD_STATS_INC(txrx_peer,
  2265. rx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  2266. 1, link_id);
  2267. dp_rx_rates_stats_update(soc, nbuf, rx_tlv_hdr, txrx_peer,
  2268. sgi, mcs, nss, bw, pkt_type, link_id);
  2269. }
  2270. #else
  2271. static inline
  2272. void dp_rx_msdu_extd_stats_update(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2273. uint8_t *rx_tlv_hdr,
  2274. struct dp_txrx_peer *txrx_peer,
  2275. uint8_t link_id)
  2276. {
  2277. }
  2278. #endif
  2279. #if defined(DP_PKT_STATS_PER_LMAC) && defined(WLAN_FEATURE_11BE_MLO)
  2280. static inline void
  2281. dp_peer_update_rx_pkt_per_lmac(struct dp_txrx_peer *txrx_peer,
  2282. qdf_nbuf_t nbuf, uint8_t link_id)
  2283. {
  2284. uint8_t lmac_id = qdf_nbuf_get_lmac_id(nbuf);
  2285. if (qdf_unlikely(lmac_id >= CDP_MAX_LMACS)) {
  2286. dp_err_rl("Invalid lmac_id: %u vdev_id: %u",
  2287. lmac_id, QDF_NBUF_CB_RX_VDEV_ID(nbuf));
  2288. if (qdf_likely(txrx_peer))
  2289. dp_err_rl("peer_id: %u", txrx_peer->peer_id);
  2290. return;
  2291. }
  2292. /* only count stats per lmac for MLO connection*/
  2293. DP_PEER_PER_PKT_STATS_INCC_PKT(txrx_peer, rx.rx_lmac[lmac_id], 1,
  2294. QDF_NBUF_CB_RX_PKT_LEN(nbuf),
  2295. txrx_peer->is_mld_peer, link_id);
  2296. }
  2297. #else
  2298. static inline void
  2299. dp_peer_update_rx_pkt_per_lmac(struct dp_txrx_peer *txrx_peer,
  2300. qdf_nbuf_t nbuf, uint8_t link_id)
  2301. {
  2302. }
  2303. #endif
  2304. void dp_rx_msdu_stats_update(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2305. uint8_t *rx_tlv_hdr,
  2306. struct dp_txrx_peer *txrx_peer,
  2307. uint8_t ring_id,
  2308. struct cdp_tid_rx_stats *tid_stats,
  2309. uint8_t link_id)
  2310. {
  2311. bool is_not_amsdu;
  2312. struct dp_vdev *vdev = txrx_peer->vdev;
  2313. uint8_t enh_flag;
  2314. qdf_ether_header_t *eh;
  2315. uint16_t msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  2316. dp_rx_msdu_stats_update_prot_cnts(vdev, nbuf, txrx_peer);
  2317. is_not_amsdu = qdf_nbuf_is_rx_chfrag_start(nbuf) &
  2318. qdf_nbuf_is_rx_chfrag_end(nbuf);
  2319. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.rcvd_reo[ring_id], 1,
  2320. msdu_len, link_id);
  2321. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, rx.non_amsdu_cnt, 1,
  2322. is_not_amsdu, link_id);
  2323. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, rx.amsdu_cnt, 1,
  2324. !is_not_amsdu, link_id);
  2325. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, rx.rx_retries, 1,
  2326. qdf_nbuf_is_rx_retry_flag(nbuf), link_id);
  2327. dp_peer_update_rx_pkt_per_lmac(txrx_peer, nbuf, link_id);
  2328. tid_stats->msdu_cnt++;
  2329. enh_flag = vdev->pdev->enhanced_stats_en;
  2330. if (qdf_unlikely(qdf_nbuf_is_da_mcbc(nbuf) &&
  2331. (vdev->rx_decap_type == htt_cmn_pkt_type_ethernet))) {
  2332. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2333. DP_PEER_MC_INCC_PKT(txrx_peer, 1, msdu_len, enh_flag, link_id);
  2334. tid_stats->mcast_msdu_cnt++;
  2335. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2336. DP_PEER_BC_INCC_PKT(txrx_peer, 1, msdu_len,
  2337. enh_flag, link_id);
  2338. tid_stats->bcast_msdu_cnt++;
  2339. }
  2340. } else {
  2341. DP_PEER_UC_INCC_PKT(txrx_peer, 1, msdu_len,
  2342. enh_flag, link_id);
  2343. }
  2344. txrx_peer->stats[link_id].per_pkt_stats.rx.last_rx_ts =
  2345. qdf_system_ticks();
  2346. dp_rx_msdu_extd_stats_update(soc, nbuf, rx_tlv_hdr,
  2347. txrx_peer, link_id);
  2348. }
  2349. #ifndef WDS_VENDOR_EXTENSION
  2350. int dp_wds_rx_policy_check(uint8_t *rx_tlv_hdr,
  2351. struct dp_vdev *vdev,
  2352. struct dp_txrx_peer *txrx_peer)
  2353. {
  2354. return 1;
  2355. }
  2356. #endif
  2357. #ifdef DP_RX_PKT_NO_PEER_DELIVER
  2358. #ifdef DP_RX_UDP_OVER_PEER_ROAM
  2359. /**
  2360. * dp_rx_is_udp_allowed_over_roam_peer() - check if udp data received
  2361. * during roaming
  2362. * @vdev: dp_vdev pointer
  2363. * @rx_tlv_hdr: rx tlv header
  2364. * @nbuf: pkt skb pointer
  2365. *
  2366. * This function will check if rx udp data is received from authorised
  2367. * roamed peer before peer map indication is received from FW after
  2368. * roaming. This is needed for VoIP scenarios in which packet loss
  2369. * expected during roaming is minimal.
  2370. *
  2371. * Return: bool
  2372. */
  2373. static bool dp_rx_is_udp_allowed_over_roam_peer(struct dp_vdev *vdev,
  2374. uint8_t *rx_tlv_hdr,
  2375. qdf_nbuf_t nbuf)
  2376. {
  2377. char *hdr_desc;
  2378. struct ieee80211_frame *wh = NULL;
  2379. hdr_desc = hal_rx_desc_get_80211_hdr(vdev->pdev->soc->hal_soc,
  2380. rx_tlv_hdr);
  2381. wh = (struct ieee80211_frame *)hdr_desc;
  2382. if (vdev->roaming_peer_status ==
  2383. WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED &&
  2384. !qdf_mem_cmp(vdev->roaming_peer_mac.raw, wh->i_addr2,
  2385. QDF_MAC_ADDR_SIZE) && (qdf_nbuf_is_ipv4_udp_pkt(nbuf) ||
  2386. qdf_nbuf_is_ipv6_udp_pkt(nbuf)))
  2387. return true;
  2388. return false;
  2389. }
  2390. #else
  2391. static bool dp_rx_is_udp_allowed_over_roam_peer(struct dp_vdev *vdev,
  2392. uint8_t *rx_tlv_hdr,
  2393. qdf_nbuf_t nbuf)
  2394. {
  2395. return false;
  2396. }
  2397. #endif
  2398. void dp_rx_deliver_to_stack_no_peer(struct dp_soc *soc, qdf_nbuf_t nbuf)
  2399. {
  2400. uint16_t peer_id;
  2401. uint8_t vdev_id;
  2402. struct dp_vdev *vdev = NULL;
  2403. uint32_t l2_hdr_offset = 0;
  2404. uint16_t msdu_len = 0;
  2405. uint32_t pkt_len = 0;
  2406. uint8_t *rx_tlv_hdr;
  2407. uint32_t frame_mask = FRAME_MASK_IPV4_ARP | FRAME_MASK_IPV4_DHCP |
  2408. FRAME_MASK_IPV4_EAPOL | FRAME_MASK_IPV6_DHCP;
  2409. bool is_special_frame = false;
  2410. struct dp_peer *peer = NULL;
  2411. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  2412. if (peer_id > soc->max_peer_id)
  2413. goto deliver_fail;
  2414. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  2415. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_RX);
  2416. if (!vdev || vdev->delete.pending)
  2417. goto deliver_fail;
  2418. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf)))
  2419. goto deliver_fail;
  2420. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  2421. l2_hdr_offset =
  2422. hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc, rx_tlv_hdr);
  2423. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  2424. pkt_len = msdu_len + l2_hdr_offset + soc->rx_pkt_tlv_size;
  2425. QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(nbuf) = 1;
  2426. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  2427. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size + l2_hdr_offset);
  2428. is_special_frame = dp_rx_is_special_frame(nbuf, frame_mask);
  2429. if (qdf_likely(vdev->osif_rx)) {
  2430. if (is_special_frame ||
  2431. dp_rx_is_udp_allowed_over_roam_peer(vdev, rx_tlv_hdr,
  2432. nbuf)) {
  2433. qdf_nbuf_set_exc_frame(nbuf, 1);
  2434. if (QDF_STATUS_SUCCESS !=
  2435. vdev->osif_rx(vdev->osif_vdev, nbuf))
  2436. goto deliver_fail;
  2437. DP_STATS_INC(soc, rx.err.pkt_delivered_no_peer, 1);
  2438. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_RX);
  2439. return;
  2440. }
  2441. } else if (is_special_frame) {
  2442. /*
  2443. * If MLO connection, txrx_peer for link peer does not exist,
  2444. * try to store these RX packets to txrx_peer's bufq of MLD
  2445. * peer until vdev->osif_rx is registered from CP and flush
  2446. * them to stack.
  2447. */
  2448. peer = dp_peer_get_tgt_peer_by_id(soc, peer_id,
  2449. DP_MOD_ID_RX);
  2450. if (!peer)
  2451. goto deliver_fail;
  2452. /* only check for MLO connection */
  2453. if (IS_MLO_DP_MLD_PEER(peer) && peer->txrx_peer &&
  2454. dp_rx_is_peer_cache_bufq_supported()) {
  2455. qdf_nbuf_set_exc_frame(nbuf, 1);
  2456. if (QDF_STATUS_SUCCESS ==
  2457. dp_rx_enqueue_rx(peer, peer->txrx_peer, nbuf)) {
  2458. DP_STATS_INC(soc,
  2459. rx.err.pkt_delivered_no_peer,
  2460. 1);
  2461. } else {
  2462. DP_STATS_INC(soc,
  2463. rx.err.rx_invalid_peer.num,
  2464. 1);
  2465. }
  2466. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_RX);
  2467. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  2468. return;
  2469. }
  2470. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  2471. }
  2472. deliver_fail:
  2473. DP_STATS_INC_PKT(soc, rx.err.rx_invalid_peer, 1,
  2474. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  2475. dp_rx_nbuf_free(nbuf);
  2476. if (vdev)
  2477. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_RX);
  2478. }
  2479. #else
  2480. void dp_rx_deliver_to_stack_no_peer(struct dp_soc *soc, qdf_nbuf_t nbuf)
  2481. {
  2482. DP_STATS_INC_PKT(soc, rx.err.rx_invalid_peer, 1,
  2483. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  2484. dp_rx_nbuf_free(nbuf);
  2485. }
  2486. #endif
  2487. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  2488. #ifdef WLAN_SUPPORT_RX_FISA
  2489. QDF_STATUS dp_fisa_config(ol_txrx_soc_handle cdp_soc, uint8_t pdev_id,
  2490. enum cdp_fisa_config_id config_id,
  2491. union cdp_fisa_config *cfg)
  2492. {
  2493. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2494. struct dp_pdev *pdev;
  2495. QDF_STATUS status;
  2496. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2497. if (!pdev) {
  2498. dp_err("pdev is NULL for pdev_id %u", pdev_id);
  2499. return QDF_STATUS_E_INVAL;
  2500. }
  2501. switch (config_id) {
  2502. case CDP_FISA_HTT_RX_FISA_CFG:
  2503. status = dp_htt_rx_fisa_config(pdev, cfg->fisa_config);
  2504. break;
  2505. case CDP_FISA_HTT_RX_FSE_OP_CFG:
  2506. status = dp_htt_rx_flow_fse_operation(pdev, cfg->fse_op_cmd);
  2507. break;
  2508. case CDP_FISA_HTT_RX_FSE_SETUP_CFG:
  2509. status = dp_htt_rx_flow_fst_setup(pdev, cfg->fse_setup_info);
  2510. break;
  2511. default:
  2512. status = QDF_STATUS_E_INVAL;
  2513. }
  2514. return status;
  2515. }
  2516. void dp_rx_skip_tlvs(struct dp_soc *soc, qdf_nbuf_t nbuf, uint32_t l3_padding)
  2517. {
  2518. QDF_NBUF_CB_RX_PACKET_L3_HDR_PAD(nbuf) = l3_padding;
  2519. qdf_nbuf_pull_head(nbuf, l3_padding + soc->rx_pkt_tlv_size);
  2520. }
  2521. #else
  2522. void dp_rx_skip_tlvs(struct dp_soc *soc, qdf_nbuf_t nbuf, uint32_t l3_padding)
  2523. {
  2524. qdf_nbuf_pull_head(nbuf, l3_padding + soc->rx_pkt_tlv_size);
  2525. }
  2526. #endif
  2527. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2528. #ifdef DP_RX_DROP_RAW_FRM
  2529. bool dp_rx_is_raw_frame_dropped(qdf_nbuf_t nbuf)
  2530. {
  2531. if (qdf_nbuf_is_raw_frame(nbuf)) {
  2532. dp_rx_nbuf_free(nbuf);
  2533. return true;
  2534. }
  2535. return false;
  2536. }
  2537. #endif
  2538. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  2539. void dp_rx_update_stats(struct dp_soc *soc, qdf_nbuf_t nbuf)
  2540. {
  2541. DP_STATS_INC_PKT(soc, rx.ingress, 1,
  2542. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  2543. }
  2544. #endif
  2545. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  2546. void dp_rx_deliver_to_pkt_capture(struct dp_soc *soc, struct dp_pdev *pdev,
  2547. uint16_t peer_id, uint32_t is_offload,
  2548. qdf_nbuf_t netbuf)
  2549. {
  2550. if (wlan_cfg_get_pkt_capture_mode(soc->wlan_cfg_ctx))
  2551. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_RX_DATA, soc, netbuf,
  2552. peer_id, is_offload, pdev->pdev_id);
  2553. }
  2554. void dp_rx_deliver_to_pkt_capture_no_peer(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2555. uint32_t is_offload)
  2556. {
  2557. if (wlan_cfg_get_pkt_capture_mode(soc->wlan_cfg_ctx))
  2558. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_RX_DATA_NO_PEER,
  2559. soc, nbuf, HTT_INVALID_VDEV,
  2560. is_offload, 0);
  2561. }
  2562. #endif
  2563. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  2564. QDF_STATUS dp_rx_vdev_detach(struct dp_vdev *vdev)
  2565. {
  2566. QDF_STATUS ret;
  2567. if (vdev->osif_rx_flush) {
  2568. ret = vdev->osif_rx_flush(vdev->osif_vdev, vdev->vdev_id);
  2569. if (!QDF_IS_STATUS_SUCCESS(ret)) {
  2570. dp_err("Failed to flush rx pkts for vdev %d",
  2571. vdev->vdev_id);
  2572. return ret;
  2573. }
  2574. }
  2575. return QDF_STATUS_SUCCESS;
  2576. }
  2577. static QDF_STATUS
  2578. dp_pdev_nbuf_alloc_and_map(struct dp_soc *dp_soc,
  2579. struct dp_rx_nbuf_frag_info *nbuf_frag_info_t,
  2580. struct dp_pdev *dp_pdev,
  2581. struct rx_desc_pool *rx_desc_pool,
  2582. bool dp_buf_page_frag_alloc_enable)
  2583. {
  2584. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  2585. if (dp_buf_page_frag_alloc_enable) {
  2586. (nbuf_frag_info_t->virt_addr).nbuf =
  2587. qdf_nbuf_frag_alloc(dp_soc->osdev,
  2588. rx_desc_pool->buf_size,
  2589. RX_BUFFER_RESERVATION,
  2590. rx_desc_pool->buf_alignment, FALSE);
  2591. } else {
  2592. (nbuf_frag_info_t->virt_addr).nbuf =
  2593. qdf_nbuf_alloc(dp_soc->osdev, rx_desc_pool->buf_size,
  2594. RX_BUFFER_RESERVATION,
  2595. rx_desc_pool->buf_alignment, FALSE);
  2596. }
  2597. if (!((nbuf_frag_info_t->virt_addr).nbuf)) {
  2598. dp_err("nbuf alloc failed");
  2599. DP_STATS_INC(dp_pdev, replenish.nbuf_alloc_fail, 1);
  2600. return ret;
  2601. }
  2602. ret = qdf_nbuf_map_nbytes_single(dp_soc->osdev,
  2603. (nbuf_frag_info_t->virt_addr).nbuf,
  2604. QDF_DMA_FROM_DEVICE,
  2605. rx_desc_pool->buf_size);
  2606. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret))) {
  2607. qdf_nbuf_free((nbuf_frag_info_t->virt_addr).nbuf);
  2608. dp_err("nbuf map failed");
  2609. DP_STATS_INC(dp_pdev, replenish.map_err, 1);
  2610. return ret;
  2611. }
  2612. nbuf_frag_info_t->paddr =
  2613. qdf_nbuf_get_frag_paddr((nbuf_frag_info_t->virt_addr).nbuf, 0);
  2614. ret = dp_check_paddr(dp_soc, &((nbuf_frag_info_t->virt_addr).nbuf),
  2615. &nbuf_frag_info_t->paddr,
  2616. rx_desc_pool);
  2617. if (ret == QDF_STATUS_E_FAILURE) {
  2618. dp_err("nbuf check x86 failed");
  2619. DP_STATS_INC(dp_pdev, replenish.x86_fail, 1);
  2620. return ret;
  2621. }
  2622. return QDF_STATUS_SUCCESS;
  2623. }
  2624. QDF_STATUS
  2625. dp_pdev_rx_buffers_attach(struct dp_soc *dp_soc, uint32_t mac_id,
  2626. struct dp_srng *dp_rxdma_srng,
  2627. struct rx_desc_pool *rx_desc_pool,
  2628. uint32_t num_req_buffers)
  2629. {
  2630. struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(dp_soc, mac_id);
  2631. hal_ring_handle_t rxdma_srng = dp_rxdma_srng->hal_srng;
  2632. union dp_rx_desc_list_elem_t *next;
  2633. void *rxdma_ring_entry;
  2634. qdf_dma_addr_t paddr;
  2635. struct dp_rx_nbuf_frag_info *nf_info;
  2636. uint32_t nr_descs, nr_nbuf = 0, nr_nbuf_total = 0;
  2637. uint32_t buffer_index, nbuf_ptrs_per_page;
  2638. qdf_nbuf_t nbuf;
  2639. QDF_STATUS ret;
  2640. int page_idx, total_pages;
  2641. union dp_rx_desc_list_elem_t *desc_list = NULL;
  2642. union dp_rx_desc_list_elem_t *tail = NULL;
  2643. int sync_hw_ptr = 1;
  2644. uint32_t num_entries_avail;
  2645. bool dp_buf_page_frag_alloc_enable;
  2646. if (qdf_unlikely(!dp_pdev)) {
  2647. dp_rx_err("%pK: pdev is null for mac_id = %d",
  2648. dp_soc, mac_id);
  2649. return QDF_STATUS_E_FAILURE;
  2650. }
  2651. dp_buf_page_frag_alloc_enable =
  2652. wlan_cfg_is_dp_buf_page_frag_alloc_enable(dp_soc->wlan_cfg_ctx);
  2653. if (qdf_unlikely(!rxdma_srng)) {
  2654. DP_STATS_INC(dp_pdev, replenish.rxdma_err, num_req_buffers);
  2655. return QDF_STATUS_E_FAILURE;
  2656. }
  2657. dp_debug("requested %u RX buffers for driver attach", num_req_buffers);
  2658. hal_srng_access_start(dp_soc->hal_soc, rxdma_srng);
  2659. num_entries_avail = hal_srng_src_num_avail(dp_soc->hal_soc,
  2660. rxdma_srng,
  2661. sync_hw_ptr);
  2662. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  2663. if (!num_entries_avail) {
  2664. dp_err("Num of available entries is zero, nothing to do");
  2665. return QDF_STATUS_E_NOMEM;
  2666. }
  2667. if (num_entries_avail < num_req_buffers)
  2668. num_req_buffers = num_entries_avail;
  2669. nr_descs = dp_rx_get_free_desc_list(dp_soc, mac_id, rx_desc_pool,
  2670. num_req_buffers, &desc_list, &tail);
  2671. if (!nr_descs) {
  2672. dp_err("no free rx_descs in freelist");
  2673. DP_STATS_INC(dp_pdev, err.desc_alloc_fail, num_req_buffers);
  2674. return QDF_STATUS_E_NOMEM;
  2675. }
  2676. dp_debug("got %u RX descs for driver attach", nr_descs);
  2677. /*
  2678. * Try to allocate pointers to the nbuf one page at a time.
  2679. * Take pointers that can fit in one page of memory and
  2680. * iterate through the total descriptors that need to be
  2681. * allocated in order of pages. Reuse the pointers that
  2682. * have been allocated to fit in one page across each
  2683. * iteration to index into the nbuf.
  2684. */
  2685. total_pages = (nr_descs * sizeof(*nf_info)) / DP_BLOCKMEM_SIZE;
  2686. /*
  2687. * Add an extra page to store the remainder if any
  2688. */
  2689. if ((nr_descs * sizeof(*nf_info)) % DP_BLOCKMEM_SIZE)
  2690. total_pages++;
  2691. nf_info = qdf_mem_malloc(DP_BLOCKMEM_SIZE);
  2692. if (!nf_info) {
  2693. dp_err("failed to allocate nbuf array");
  2694. DP_STATS_INC(dp_pdev, replenish.rxdma_err, num_req_buffers);
  2695. QDF_BUG(0);
  2696. return QDF_STATUS_E_NOMEM;
  2697. }
  2698. nbuf_ptrs_per_page = DP_BLOCKMEM_SIZE / sizeof(*nf_info);
  2699. for (page_idx = 0; page_idx < total_pages; page_idx++) {
  2700. qdf_mem_zero(nf_info, DP_BLOCKMEM_SIZE);
  2701. for (nr_nbuf = 0; nr_nbuf < nbuf_ptrs_per_page; nr_nbuf++) {
  2702. /*
  2703. * The last page of buffer pointers may not be required
  2704. * completely based on the number of descriptors. Below
  2705. * check will ensure we are allocating only the
  2706. * required number of descriptors.
  2707. */
  2708. if (nr_nbuf_total >= nr_descs)
  2709. break;
  2710. /* Flag is set while pdev rx_desc_pool initialization */
  2711. if (qdf_unlikely(rx_desc_pool->rx_mon_dest_frag_enable))
  2712. ret = dp_pdev_frag_alloc_and_map(dp_soc,
  2713. &nf_info[nr_nbuf], dp_pdev,
  2714. rx_desc_pool);
  2715. else
  2716. ret = dp_pdev_nbuf_alloc_and_map(dp_soc,
  2717. &nf_info[nr_nbuf], dp_pdev,
  2718. rx_desc_pool,
  2719. dp_buf_page_frag_alloc_enable);
  2720. if (QDF_IS_STATUS_ERROR(ret))
  2721. break;
  2722. nr_nbuf_total++;
  2723. }
  2724. hal_srng_access_start(dp_soc->hal_soc, rxdma_srng);
  2725. for (buffer_index = 0; buffer_index < nr_nbuf; buffer_index++) {
  2726. rxdma_ring_entry =
  2727. hal_srng_src_get_next(dp_soc->hal_soc,
  2728. rxdma_srng);
  2729. qdf_assert_always(rxdma_ring_entry);
  2730. next = desc_list->next;
  2731. paddr = nf_info[buffer_index].paddr;
  2732. nbuf = nf_info[buffer_index].virt_addr.nbuf;
  2733. /* Flag is set while pdev rx_desc_pool initialization */
  2734. if (qdf_unlikely(rx_desc_pool->rx_mon_dest_frag_enable))
  2735. dp_rx_desc_frag_prep(&desc_list->rx_desc,
  2736. &nf_info[buffer_index]);
  2737. else
  2738. dp_rx_desc_prep(&desc_list->rx_desc,
  2739. &nf_info[buffer_index]);
  2740. desc_list->rx_desc.in_use = 1;
  2741. dp_rx_desc_alloc_dbg_info(&desc_list->rx_desc);
  2742. dp_rx_desc_update_dbg_info(&desc_list->rx_desc,
  2743. __func__,
  2744. RX_DESC_REPLENISHED);
  2745. hal_rxdma_buff_addr_info_set(dp_soc->hal_soc ,rxdma_ring_entry, paddr,
  2746. desc_list->rx_desc.cookie,
  2747. rx_desc_pool->owner);
  2748. if (qdf_atomic_read(&dp_soc->ipa_mapped))
  2749. dp_ipa_handle_rx_buf_smmu_mapping(
  2750. dp_soc, nbuf,
  2751. rx_desc_pool->buf_size, true,
  2752. __func__, __LINE__);
  2753. dp_audio_smmu_map(dp_soc->osdev,
  2754. qdf_mem_paddr_from_dmaaddr(dp_soc->osdev,
  2755. QDF_NBUF_CB_PADDR(nbuf)),
  2756. QDF_NBUF_CB_PADDR(nbuf),
  2757. rx_desc_pool->buf_size);
  2758. desc_list = next;
  2759. }
  2760. dp_rx_refill_ring_record_entry(dp_soc, dp_pdev->lmac_id,
  2761. rxdma_srng, nr_nbuf, nr_nbuf);
  2762. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  2763. }
  2764. dp_info("filled %u RX buffers for driver attach", nr_nbuf_total);
  2765. qdf_mem_free(nf_info);
  2766. if (!nr_nbuf_total) {
  2767. dp_err("No nbuf's allocated");
  2768. QDF_BUG(0);
  2769. return QDF_STATUS_E_RESOURCES;
  2770. }
  2771. /* No need to count the number of bytes received during replenish.
  2772. * Therefore set replenish.pkts.bytes as 0.
  2773. */
  2774. DP_STATS_INC_PKT(dp_pdev, replenish.pkts, nr_nbuf, 0);
  2775. return QDF_STATUS_SUCCESS;
  2776. }
  2777. qdf_export_symbol(dp_pdev_rx_buffers_attach);
  2778. #ifdef DP_RX_MON_MEM_FRAG
  2779. void dp_rx_enable_mon_dest_frag(struct rx_desc_pool *rx_desc_pool,
  2780. bool is_mon_dest_desc)
  2781. {
  2782. rx_desc_pool->rx_mon_dest_frag_enable = is_mon_dest_desc;
  2783. if (is_mon_dest_desc)
  2784. dp_alert("Feature DP_RX_MON_MEM_FRAG for mon_dest is enabled");
  2785. }
  2786. #else
  2787. void dp_rx_enable_mon_dest_frag(struct rx_desc_pool *rx_desc_pool,
  2788. bool is_mon_dest_desc)
  2789. {
  2790. rx_desc_pool->rx_mon_dest_frag_enable = false;
  2791. if (is_mon_dest_desc)
  2792. dp_alert("Feature DP_RX_MON_MEM_FRAG for mon_dest is disabled");
  2793. }
  2794. #endif
  2795. qdf_export_symbol(dp_rx_enable_mon_dest_frag);
  2796. QDF_STATUS
  2797. dp_rx_pdev_desc_pool_alloc(struct dp_pdev *pdev)
  2798. {
  2799. struct dp_soc *soc = pdev->soc;
  2800. uint32_t rxdma_entries;
  2801. uint32_t rx_sw_desc_num;
  2802. struct dp_srng *dp_rxdma_srng;
  2803. struct rx_desc_pool *rx_desc_pool;
  2804. uint32_t status = QDF_STATUS_SUCCESS;
  2805. int mac_for_pdev;
  2806. mac_for_pdev = pdev->lmac_id;
  2807. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2808. dp_rx_info("%pK: nss-wifi<4> skip Rx refil %d",
  2809. soc, mac_for_pdev);
  2810. return status;
  2811. }
  2812. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_for_pdev];
  2813. rxdma_entries = dp_rxdma_srng->num_entries;
  2814. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  2815. rx_sw_desc_num = wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  2816. rx_desc_pool->desc_type = QDF_DP_RX_DESC_BUF_TYPE;
  2817. status = dp_rx_desc_pool_alloc(soc,
  2818. rx_sw_desc_num,
  2819. rx_desc_pool);
  2820. if (status != QDF_STATUS_SUCCESS)
  2821. return status;
  2822. return status;
  2823. }
  2824. void dp_rx_pdev_desc_pool_free(struct dp_pdev *pdev)
  2825. {
  2826. int mac_for_pdev = pdev->lmac_id;
  2827. struct dp_soc *soc = pdev->soc;
  2828. struct rx_desc_pool *rx_desc_pool;
  2829. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  2830. dp_rx_desc_pool_free(soc, rx_desc_pool);
  2831. }
  2832. QDF_STATUS dp_rx_pdev_desc_pool_init(struct dp_pdev *pdev)
  2833. {
  2834. int mac_for_pdev = pdev->lmac_id;
  2835. struct dp_soc *soc = pdev->soc;
  2836. uint32_t rxdma_entries;
  2837. uint32_t rx_sw_desc_num;
  2838. struct dp_srng *dp_rxdma_srng;
  2839. struct rx_desc_pool *rx_desc_pool;
  2840. uint32_t target_type = hal_get_target_type(soc->hal_soc);
  2841. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  2842. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2843. /*
  2844. * If NSS is enabled, rx_desc_pool is already filled.
  2845. * Hence, just disable desc_pool frag flag.
  2846. */
  2847. dp_rx_enable_mon_dest_frag(rx_desc_pool, false);
  2848. dp_rx_info("%pK: nss-wifi<4> skip Rx refil %d",
  2849. soc, mac_for_pdev);
  2850. return QDF_STATUS_SUCCESS;
  2851. }
  2852. if (dp_rx_desc_pool_is_allocated(rx_desc_pool) == QDF_STATUS_E_NOMEM)
  2853. return QDF_STATUS_E_NOMEM;
  2854. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_for_pdev];
  2855. rxdma_entries = dp_rxdma_srng->num_entries;
  2856. soc->process_rx_status = CONFIG_PROCESS_RX_STATUS;
  2857. rx_sw_desc_num =
  2858. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  2859. rx_desc_pool->owner = dp_rx_get_rx_bm_id(soc);
  2860. rx_desc_pool->buf_size = RX_DATA_BUFFER_SIZE;
  2861. rx_desc_pool->buf_alignment = RX_DATA_BUFFER_ALIGNMENT;
  2862. /* Disable monitor dest processing via frag */
  2863. if (target_type == TARGET_TYPE_QCN9160) {
  2864. rx_desc_pool->buf_size = RX_MONITOR_BUFFER_SIZE;
  2865. rx_desc_pool->buf_alignment = RX_MONITOR_BUFFER_ALIGNMENT;
  2866. dp_rx_enable_mon_dest_frag(rx_desc_pool, true);
  2867. } else {
  2868. dp_rx_enable_mon_dest_frag(rx_desc_pool, false);
  2869. }
  2870. dp_rx_desc_pool_init(soc, mac_for_pdev,
  2871. rx_sw_desc_num, rx_desc_pool);
  2872. return QDF_STATUS_SUCCESS;
  2873. }
  2874. void dp_rx_pdev_desc_pool_deinit(struct dp_pdev *pdev)
  2875. {
  2876. int mac_for_pdev = pdev->lmac_id;
  2877. struct dp_soc *soc = pdev->soc;
  2878. struct rx_desc_pool *rx_desc_pool;
  2879. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  2880. dp_rx_desc_pool_deinit(soc, rx_desc_pool, mac_for_pdev);
  2881. }
  2882. QDF_STATUS
  2883. dp_rx_pdev_buffers_alloc(struct dp_pdev *pdev)
  2884. {
  2885. int mac_for_pdev = pdev->lmac_id;
  2886. struct dp_soc *soc = pdev->soc;
  2887. struct dp_srng *dp_rxdma_srng;
  2888. struct rx_desc_pool *rx_desc_pool;
  2889. uint32_t rxdma_entries;
  2890. uint32_t target_type = hal_get_target_type(soc->hal_soc);
  2891. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_for_pdev];
  2892. rxdma_entries = dp_rxdma_srng->num_entries;
  2893. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  2894. /* Initialize RX buffer pool which will be
  2895. * used during low memory conditions
  2896. */
  2897. dp_rx_buffer_pool_init(soc, mac_for_pdev);
  2898. if (target_type == TARGET_TYPE_QCN9160)
  2899. return dp_pdev_rx_buffers_attach(soc, mac_for_pdev,
  2900. dp_rxdma_srng,
  2901. rx_desc_pool,
  2902. rxdma_entries - 1);
  2903. else
  2904. return dp_pdev_rx_buffers_attach_simple(soc, mac_for_pdev,
  2905. dp_rxdma_srng,
  2906. rx_desc_pool,
  2907. rxdma_entries - 1);
  2908. }
  2909. void
  2910. dp_rx_pdev_buffers_free(struct dp_pdev *pdev)
  2911. {
  2912. int mac_for_pdev = pdev->lmac_id;
  2913. struct dp_soc *soc = pdev->soc;
  2914. struct rx_desc_pool *rx_desc_pool;
  2915. uint32_t target_type = hal_get_target_type(soc->hal_soc);
  2916. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  2917. if (target_type == TARGET_TYPE_QCN9160)
  2918. dp_rx_desc_frag_free(soc, rx_desc_pool);
  2919. else
  2920. dp_rx_desc_nbuf_free(soc, rx_desc_pool, false);
  2921. dp_rx_buffer_pool_deinit(soc, mac_for_pdev);
  2922. }
  2923. #ifdef DP_RX_SPECIAL_FRAME_NEED
  2924. bool dp_rx_deliver_special_frame(struct dp_soc *soc,
  2925. struct dp_txrx_peer *txrx_peer,
  2926. qdf_nbuf_t nbuf, uint32_t frame_mask,
  2927. uint8_t *rx_tlv_hdr)
  2928. {
  2929. uint32_t l2_hdr_offset = 0;
  2930. uint16_t msdu_len = 0;
  2931. uint32_t skip_len;
  2932. l2_hdr_offset =
  2933. hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc, rx_tlv_hdr);
  2934. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  2935. skip_len = l2_hdr_offset;
  2936. } else {
  2937. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  2938. skip_len = l2_hdr_offset + soc->rx_pkt_tlv_size;
  2939. qdf_nbuf_set_pktlen(nbuf, msdu_len + skip_len);
  2940. }
  2941. QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(nbuf) = 1;
  2942. dp_rx_set_hdr_pad(nbuf, l2_hdr_offset);
  2943. qdf_nbuf_pull_head(nbuf, skip_len);
  2944. if (txrx_peer->vdev) {
  2945. dp_rx_send_pktlog(soc, txrx_peer->vdev->pdev, nbuf,
  2946. QDF_TX_RX_STATUS_OK);
  2947. }
  2948. if (dp_rx_is_special_frame(nbuf, frame_mask)) {
  2949. dp_info("special frame, mpdu sn 0x%x",
  2950. hal_rx_get_rx_sequence(soc->hal_soc, rx_tlv_hdr));
  2951. qdf_nbuf_set_exc_frame(nbuf, 1);
  2952. dp_rx_deliver_to_stack(soc, txrx_peer->vdev, txrx_peer,
  2953. nbuf, NULL);
  2954. return true;
  2955. }
  2956. return false;
  2957. }
  2958. #endif
  2959. #ifdef QCA_MULTIPASS_SUPPORT
  2960. bool dp_rx_multipass_process(struct dp_txrx_peer *txrx_peer, qdf_nbuf_t nbuf,
  2961. uint8_t tid)
  2962. {
  2963. struct vlan_ethhdr *vethhdrp;
  2964. if (qdf_unlikely(!txrx_peer->vlan_id))
  2965. return true;
  2966. vethhdrp = (struct vlan_ethhdr *)qdf_nbuf_data(nbuf);
  2967. /*
  2968. * h_vlan_proto & h_vlan_TCI should be 0x8100 & zero respectively
  2969. * as it is expected to be padded by 0
  2970. * return false if frame doesn't have above tag so that caller will
  2971. * drop the frame.
  2972. */
  2973. if (qdf_unlikely(vethhdrp->h_vlan_proto != htons(QDF_ETH_TYPE_8021Q)) ||
  2974. qdf_unlikely(vethhdrp->h_vlan_TCI != 0))
  2975. return false;
  2976. vethhdrp->h_vlan_TCI = htons(((tid & 0x7) << VLAN_PRIO_SHIFT) |
  2977. (txrx_peer->vlan_id & VLAN_VID_MASK));
  2978. if (vethhdrp->h_vlan_encapsulated_proto == htons(ETHERTYPE_PAE))
  2979. dp_tx_remove_vlan_tag(txrx_peer->vdev, nbuf);
  2980. return true;
  2981. }
  2982. #endif /* QCA_MULTIPASS_SUPPORT */