dp_be.c 87 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include "dp_rings.h"
  22. #include <dp_htt.h>
  23. #include "dp_be.h"
  24. #include "dp_be_tx.h"
  25. #include "dp_be_rx.h"
  26. #ifdef WIFI_MONITOR_SUPPORT
  27. #if !defined(DISABLE_MON_CONFIG) && (defined(WLAN_PKT_CAPTURE_TX_2_0) || \
  28. defined(WLAN_PKT_CAPTURE_RX_2_0))
  29. #include "dp_mon_2.0.h"
  30. #endif
  31. #include "dp_mon.h"
  32. #endif
  33. #include <hal_be_api.h>
  34. #ifdef WLAN_SUPPORT_PPEDS
  35. #include "be/dp_ppeds.h"
  36. #include <ppe_vp_public.h>
  37. #include <ppe_drv_sc.h>
  38. #endif
  39. #ifdef WLAN_SUPPORT_PPEDS
  40. static const char *ring_usage_dump[RING_USAGE_MAX] = {
  41. "100%",
  42. "Greater than 90%",
  43. "70 to 90%",
  44. "50 to 70%",
  45. "Less than 50%"
  46. };
  47. #endif
  48. /* Generic AST entry aging timer value */
  49. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  50. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  51. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  52. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  53. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  54. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  55. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  56. #ifdef QCA_WIFI_KIWI_V2
  57. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  58. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  59. #else
  60. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  61. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  62. #endif
  63. };
  64. #else
  65. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  66. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  67. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  68. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  69. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  70. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  71. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  72. };
  73. #endif
  74. #ifdef WLAN_SUPPORT_PPEDS
  75. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  76. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  77. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  78. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  79. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  80. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  81. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  82. .ppeds_vp_setup_recovery = dp_ppeds_vp_setup_on_fw_recovery,
  83. .ppeds_stats_sync = dp_ppeds_stats_sync_be,
  84. };
  85. static void dp_ppeds_rings_status(struct dp_soc *soc)
  86. {
  87. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  88. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  89. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  90. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  91. WBM2SW_RELEASE);
  92. }
  93. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  94. {
  95. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  96. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  97. be_soc->ppeds_tx_desc.num_allocated,
  98. be_soc->ppeds_tx_desc.num_free);
  99. DP_PRINT_STATS("PPE-DS Tx desc alloc failed %u",
  100. be_soc->ppeds_stats.tx.desc_alloc_failed);
  101. }
  102. static void dp_ppeds_clear_stats(struct dp_soc *soc)
  103. {
  104. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  105. be_soc->ppeds_stats.tx.desc_alloc_failed = 0;
  106. }
  107. static void dp_ppeds_rings_stats(struct dp_soc *soc)
  108. {
  109. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  110. int i = 0;
  111. DP_PRINT_STATS("Ring utilization statistics");
  112. DP_PRINT_STATS("WBM2SW_RELEASE");
  113. for (i = 0; i < RING_USAGE_MAX; i++)
  114. DP_PRINT_STATS("\t %s utilized %d instances",
  115. ring_usage_dump[i],
  116. be_soc->ppeds_wbm_release_ring.stats.util[i]);
  117. DP_PRINT_STATS("PPE2TCL");
  118. for (i = 0; i < RING_USAGE_MAX; i++)
  119. DP_PRINT_STATS("\t %s utilized %d instances",
  120. ring_usage_dump[i],
  121. be_soc->ppe2tcl_ring.stats.util[i]);
  122. }
  123. static void dp_ppeds_clear_rings_stats(struct dp_soc *soc)
  124. {
  125. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  126. memset(&be_soc->ppeds_wbm_release_ring.stats, 0,
  127. sizeof(struct ring_util_stats));
  128. memset(&be_soc->ppe2tcl_ring.stats, 0, sizeof(struct ring_util_stats));
  129. }
  130. #endif
  131. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  132. {
  133. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  134. dp_soc_cfg_attach(soc);
  135. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  136. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  137. /* this is used only when dmac mode is enabled */
  138. soc->num_rx_refill_buf_rings = 1;
  139. soc->wlan_cfg_ctx->notify_frame_support =
  140. DP_MARK_NOTIFY_FRAME_SUPPORT;
  141. }
  142. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  143. {
  144. switch (context_type) {
  145. case DP_CONTEXT_TYPE_SOC:
  146. return sizeof(struct dp_soc_be);
  147. case DP_CONTEXT_TYPE_PDEV:
  148. return sizeof(struct dp_pdev_be);
  149. case DP_CONTEXT_TYPE_VDEV:
  150. return sizeof(struct dp_vdev_be);
  151. case DP_CONTEXT_TYPE_PEER:
  152. return sizeof(struct dp_peer_be);
  153. default:
  154. return 0;
  155. }
  156. }
  157. #if defined(DP_FEATURE_HW_COOKIE_CONVERSION) || defined(WLAN_SUPPORT_RX_FISA)
  158. static uint64_t dp_get_cmem_chunk(struct dp_soc *soc, uint64_t size,
  159. enum CMEM_MEM_CLIENTS client)
  160. {
  161. uint64_t cmem_chunk;
  162. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  163. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  164. /* Check if requested cmem space is available */
  165. if (soc->cmem_avail_size < size) {
  166. dp_err("cmem_size 0x%llx bytes < requested size 0x%llx bytes",
  167. soc->cmem_avail_size, size);
  168. return 0;
  169. }
  170. cmem_chunk = soc->cmem_base +
  171. (soc->cmem_total_size - soc->cmem_avail_size);
  172. soc->cmem_avail_size -= size;
  173. dp_info("Reserved cmem space 0x%llx, size 0x%llx for client %d",
  174. cmem_chunk, size, client);
  175. return cmem_chunk;
  176. }
  177. #endif
  178. #ifdef WLAN_SUPPORT_RX_FISA
  179. static uint64_t dp_get_fst_cmem_base_be(struct dp_soc *soc, uint64_t size)
  180. {
  181. return dp_get_cmem_chunk(soc, size, FISA_FST);
  182. }
  183. static void dp_initialize_arch_ops_be_fisa(struct dp_arch_ops *arch_ops)
  184. {
  185. arch_ops->dp_get_fst_cmem_base = dp_get_fst_cmem_base_be;
  186. }
  187. #else
  188. static void dp_initialize_arch_ops_be_fisa(struct dp_arch_ops *arch_ops)
  189. {
  190. }
  191. #endif
  192. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  193. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  194. /**
  195. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  196. * per wbm2sw ring
  197. *
  198. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  199. *
  200. * Return: None
  201. */
  202. #ifdef IPA_OPT_WIFI_DP
  203. static inline
  204. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  205. {
  206. cc_cfg->wbm2sw6_cc_en = 1;
  207. cc_cfg->wbm2sw5_cc_en = 0;
  208. cc_cfg->wbm2sw4_cc_en = 1;
  209. cc_cfg->wbm2sw3_cc_en = 1;
  210. cc_cfg->wbm2sw2_cc_en = 1;
  211. /* disable wbm2sw1 hw cc as it's for FW */
  212. cc_cfg->wbm2sw1_cc_en = 0;
  213. cc_cfg->wbm2sw0_cc_en = 1;
  214. cc_cfg->wbm2fw_cc_en = 0;
  215. }
  216. #else
  217. static inline
  218. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  219. {
  220. cc_cfg->wbm2sw6_cc_en = 1;
  221. cc_cfg->wbm2sw5_cc_en = 1;
  222. cc_cfg->wbm2sw4_cc_en = 1;
  223. cc_cfg->wbm2sw3_cc_en = 1;
  224. cc_cfg->wbm2sw2_cc_en = 1;
  225. /* disable wbm2sw1 hw cc as it's for FW */
  226. cc_cfg->wbm2sw1_cc_en = 0;
  227. cc_cfg->wbm2sw0_cc_en = 1;
  228. cc_cfg->wbm2fw_cc_en = 0;
  229. }
  230. #endif
  231. #else
  232. static inline
  233. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  234. {
  235. cc_cfg->wbm2sw6_cc_en = 1;
  236. cc_cfg->wbm2sw5_cc_en = 1;
  237. cc_cfg->wbm2sw4_cc_en = 1;
  238. cc_cfg->wbm2sw3_cc_en = 1;
  239. cc_cfg->wbm2sw2_cc_en = 1;
  240. cc_cfg->wbm2sw1_cc_en = 1;
  241. cc_cfg->wbm2sw0_cc_en = 1;
  242. cc_cfg->wbm2fw_cc_en = 0;
  243. }
  244. #endif
  245. /**
  246. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  247. * conversion register
  248. *
  249. * @soc: SOC handle
  250. * @is_4k_align: page address 4k aligned
  251. *
  252. * Return: None
  253. */
  254. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  255. bool is_4k_align)
  256. {
  257. struct hal_hw_cc_config cc_cfg = { 0 };
  258. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  259. if (soc->cdp_soc.ol_ops->get_con_mode &&
  260. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  261. return;
  262. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  263. dp_info("INI skip HW CC register setting");
  264. return;
  265. }
  266. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  267. cc_cfg.cc_global_en = true;
  268. cc_cfg.page_4k_align = is_4k_align;
  269. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  270. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  271. /* 36th bit should be 1 then HW know this is CMEM address */
  272. cc_cfg.lut_base_addr_39_32 = 0x10;
  273. cc_cfg.error_path_cookie_conv_en = true;
  274. cc_cfg.release_path_cookie_conv_en = true;
  275. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  276. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  277. }
  278. /**
  279. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  280. * @hal_soc_hdl: HAL SOC handle
  281. * @offset: CMEM address
  282. * @value: value to write
  283. *
  284. * Return: None.
  285. */
  286. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  287. uint32_t offset,
  288. uint32_t value)
  289. {
  290. hal_cmem_write(hal_soc_hdl, offset, value);
  291. }
  292. /**
  293. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  294. * HW cookie conversion
  295. *
  296. * @soc: SOC handle
  297. *
  298. * Return: 0 in case of success, else error value
  299. */
  300. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  301. {
  302. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  303. be_soc->cc_cmem_base = dp_get_cmem_chunk(soc, DP_CC_PPT_MEM_SIZE,
  304. COOKIE_CONVERSION);
  305. return QDF_STATUS_SUCCESS;
  306. }
  307. #else
  308. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  309. bool is_4k_align) {}
  310. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  311. uint32_t offset,
  312. uint32_t value)
  313. { }
  314. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  315. {
  316. return QDF_STATUS_SUCCESS;
  317. }
  318. #endif
  319. #if defined(DP_FEATURE_HW_COOKIE_CONVERSION) || defined(WLAN_SUPPORT_RX_FISA)
  320. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  321. uint8_t for_feature)
  322. {
  323. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  324. switch (for_feature) {
  325. case COOKIE_CONVERSION:
  326. status = dp_hw_cc_cmem_addr_init(soc);
  327. break;
  328. default:
  329. dp_err("Invalid CMEM request");
  330. }
  331. return status;
  332. }
  333. #else
  334. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  335. uint8_t for_feature)
  336. {
  337. return QDF_STATUS_SUCCESS;
  338. }
  339. #endif
  340. QDF_STATUS
  341. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  342. struct dp_hw_cookie_conversion_t *cc_ctx,
  343. uint32_t num_descs,
  344. enum qdf_dp_desc_type desc_type,
  345. uint8_t desc_pool_id)
  346. {
  347. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  348. uint32_t num_spt_pages, i = 0;
  349. struct dp_spt_page_desc *spt_desc;
  350. struct qdf_mem_dma_page_t *dma_page;
  351. uint8_t chip_id;
  352. /* estimate how many SPT DDR pages needed */
  353. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  354. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  355. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  356. dp_info("num_spt_pages needed %d", num_spt_pages);
  357. dp_desc_multi_pages_mem_alloc(soc, QDF_DP_HW_CC_SPT_PAGE_TYPE,
  358. &cc_ctx->page_pool, qdf_page_size,
  359. num_spt_pages, 0, false);
  360. if (!cc_ctx->page_pool.dma_pages) {
  361. dp_err("spt ddr pages allocation failed");
  362. return QDF_STATUS_E_RESOURCES;
  363. }
  364. cc_ctx->page_desc_base = qdf_mem_malloc(
  365. num_spt_pages * sizeof(struct dp_spt_page_desc));
  366. if (!cc_ctx->page_desc_base) {
  367. dp_err("spt page descs allocation failed");
  368. goto fail_0;
  369. }
  370. chip_id = dp_mlo_get_chip_id(soc);
  371. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  372. desc_type);
  373. /* initial page desc */
  374. spt_desc = cc_ctx->page_desc_base;
  375. dma_page = cc_ctx->page_pool.dma_pages;
  376. while (i < num_spt_pages) {
  377. /* check if page address 4K aligned */
  378. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  379. dp_err("non-4k aligned pages addr %pK",
  380. (void *)dma_page[i].page_p_addr);
  381. goto fail_1;
  382. }
  383. spt_desc[i].page_v_addr =
  384. dma_page[i].page_v_addr_start;
  385. spt_desc[i].page_p_addr =
  386. dma_page[i].page_p_addr;
  387. i++;
  388. }
  389. cc_ctx->total_page_num = num_spt_pages;
  390. qdf_spinlock_create(&cc_ctx->cc_lock);
  391. return QDF_STATUS_SUCCESS;
  392. fail_1:
  393. qdf_mem_free(cc_ctx->page_desc_base);
  394. cc_ctx->page_desc_base = NULL;
  395. fail_0:
  396. dp_desc_multi_pages_mem_free(soc, QDF_DP_HW_CC_SPT_PAGE_TYPE,
  397. &cc_ctx->page_pool, 0, false);
  398. return QDF_STATUS_E_FAILURE;
  399. }
  400. QDF_STATUS
  401. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  402. struct dp_hw_cookie_conversion_t *cc_ctx)
  403. {
  404. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  405. dp_desc_multi_pages_mem_free(soc, QDF_DP_HW_CC_SPT_PAGE_TYPE,
  406. &cc_ctx->page_pool, 0, false);
  407. if (cc_ctx->page_desc_base)
  408. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  409. qdf_mem_free(cc_ctx->page_desc_base);
  410. cc_ctx->page_desc_base = NULL;
  411. return QDF_STATUS_SUCCESS;
  412. }
  413. QDF_STATUS
  414. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  415. struct dp_hw_cookie_conversion_t *cc_ctx)
  416. {
  417. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  418. uint32_t i = 0;
  419. struct dp_spt_page_desc *spt_desc;
  420. uint32_t ppt_index;
  421. uint32_t ppt_id_start;
  422. if (!cc_ctx->total_page_num) {
  423. dp_err("total page num is 0");
  424. return QDF_STATUS_E_INVAL;
  425. }
  426. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  427. spt_desc = cc_ctx->page_desc_base;
  428. while (i < cc_ctx->total_page_num) {
  429. /* write page PA to CMEM */
  430. dp_hw_cc_cmem_write(soc->hal_soc,
  431. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  432. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  433. (spt_desc[i].page_p_addr >>
  434. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  435. ppt_index = ppt_id_start + i;
  436. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  437. qdf_assert_always(0);
  438. spt_desc[i].ppt_index = ppt_index;
  439. be_soc->page_desc_base[ppt_index].page_v_addr =
  440. spt_desc[i].page_v_addr;
  441. i++;
  442. }
  443. return QDF_STATUS_SUCCESS;
  444. }
  445. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  446. QDF_STATUS
  447. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  448. struct dp_hw_cookie_conversion_t *cc_ctx)
  449. {
  450. uint32_t ppt_index;
  451. struct dp_spt_page_desc *spt_desc;
  452. int i = 0;
  453. spt_desc = cc_ctx->page_desc_base;
  454. while (i < cc_ctx->total_page_num) {
  455. ppt_index = spt_desc[i].ppt_index;
  456. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  457. i++;
  458. }
  459. return QDF_STATUS_SUCCESS;
  460. }
  461. #else
  462. QDF_STATUS
  463. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  464. struct dp_hw_cookie_conversion_t *cc_ctx)
  465. {
  466. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  467. uint32_t ppt_index;
  468. struct dp_spt_page_desc *spt_desc;
  469. int i = 0;
  470. spt_desc = cc_ctx->page_desc_base;
  471. while (i < cc_ctx->total_page_num) {
  472. /* reset PA in CMEM to NULL */
  473. dp_hw_cc_cmem_write(soc->hal_soc,
  474. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  475. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  476. 0);
  477. ppt_index = spt_desc[i].ppt_index;
  478. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  479. i++;
  480. }
  481. return QDF_STATUS_SUCCESS;
  482. }
  483. #endif
  484. #ifdef WLAN_SUPPORT_PPEDS
  485. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  486. {
  487. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  488. int target_type = hal_get_target_type(soc->hal_soc);
  489. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  490. /*
  491. * Check if PPE DS is enabled and wlan soc supports it.
  492. */
  493. if (!wlan_cfg_get_dp_soc_ppeds_enable(soc->wlan_cfg_ctx) ||
  494. !dp_ppeds_target_supported(target_type))
  495. return QDF_STATUS_SUCCESS;
  496. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  497. return QDF_STATUS_SUCCESS;
  498. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  499. return QDF_STATUS_SUCCESS;
  500. }
  501. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  502. {
  503. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  504. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  505. if (!be_soc->ppeds_handle)
  506. return QDF_STATUS_E_FAILURE;
  507. dp_ppeds_detach_soc_be(be_soc);
  508. cdp_ops->ppeds_ops = NULL;
  509. return QDF_STATUS_SUCCESS;
  510. }
  511. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  512. struct dp_peer_be *be_peer,
  513. uint8_t vdev_id,
  514. uint16_t src_info)
  515. {
  516. uint16_t service_code;
  517. uint8_t priority_valid;
  518. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  519. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  520. QDF_STATUS status = QDF_STATUS_SUCCESS;
  521. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  522. struct dp_vdev_be *be_vdev;
  523. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  524. /*
  525. * Program service code bypass to avoid L2 new mac address
  526. * learning exception when fdb learning is disabled.
  527. */
  528. service_code = PPE_DRV_SC_SPF_BYPASS;
  529. priority_valid = be_peer->priority_valid;
  530. /*
  531. * if FST is enabled then let flow rule take the decision of
  532. * routing the pkt to DS or host
  533. */
  534. if (wlan_cfg_is_rx_flow_tag_enabled(cfg))
  535. use_ppe_ds = 0;
  536. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  537. status =
  538. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  539. (soc->ctrl_psoc,
  540. be_peer->peer.mac_addr.raw,
  541. service_code, priority_valid,
  542. src_info, vdev_id, use_ppe_ds,
  543. peer_routing_enabled);
  544. if (status != QDF_STATUS_SUCCESS) {
  545. dp_err("vdev_id: %d, PPE peer routing mac:"
  546. QDF_MAC_ADDR_FMT, vdev_id,
  547. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  548. return QDF_STATUS_E_FAILURE;
  549. }
  550. }
  551. return QDF_STATUS_SUCCESS;
  552. }
  553. #ifdef WLAN_FEATURE_11BE_MLO
  554. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  555. struct dp_peer *peer,
  556. struct dp_vdev_be *be_vdev,
  557. void *args)
  558. {
  559. struct dp_peer *mld_peer;
  560. struct dp_soc *mld_soc;
  561. struct dp_soc_be *be_soc;
  562. struct cdp_soc_t *cdp_soc;
  563. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  564. struct cdp_ds_vp_params vp_params = {0};
  565. struct dp_ppe_vp_profile *ppe_vp_profile = (struct dp_ppe_vp_profile *)args;
  566. uint16_t src_info = ppe_vp_profile->vp_num;
  567. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  568. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  569. if (!be_peer) {
  570. dp_err("BE peer is null");
  571. return QDF_STATUS_E_NULL_VALUE;
  572. }
  573. if (IS_DP_LEGACY_PEER(peer)) {
  574. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  575. vdev_id, src_info);
  576. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  577. int i;
  578. struct dp_peer *link_peer = NULL;
  579. struct dp_mld_link_peers link_peers_info;
  580. /* get link peers with reference */
  581. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  582. DP_MOD_ID_DS);
  583. for (i = 0; i < link_peers_info.num_links; i++) {
  584. link_peer = link_peers_info.link_peers[i];
  585. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  586. if (!be_peer) {
  587. dp_err("BE peer is null");
  588. continue;
  589. }
  590. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  591. if (!be_vdev) {
  592. dp_err("BE vap is null for peer id %d ",
  593. link_peer->peer_id);
  594. continue;
  595. }
  596. vdev_id = be_vdev->vdev.vdev_id;
  597. soc = link_peer->vdev->pdev->soc;
  598. qdf_status = dp_peer_ppeds_default_route_be(soc,
  599. be_peer,
  600. vdev_id,
  601. src_info);
  602. }
  603. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  604. } else {
  605. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  606. if (!mld_peer)
  607. return qdf_status;
  608. /*
  609. * In case of MLO link peer,
  610. * Fetch the VP profile from the mld vdev.
  611. */
  612. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  613. if (!be_vdev) {
  614. dp_err("BE vap is null");
  615. return QDF_STATUS_E_NULL_VALUE;
  616. }
  617. /*
  618. * Extract the VP profile from the vap
  619. * in case of MLO peer, we have to get the profile from
  620. * the MLD vdev's osif handle and not the link peer.
  621. */
  622. mld_soc = mld_peer->vdev->pdev->soc;
  623. cdp_soc = &mld_soc->cdp_soc;
  624. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  625. dp_err("%pK: Register PPEDS profile info API before use", cdp_soc);
  626. return QDF_STATUS_E_NULL_VALUE;
  627. }
  628. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(mld_soc->ctrl_psoc,
  629. mld_peer->vdev->vdev_id,
  630. &vp_params);
  631. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  632. dp_err("%pK: Failed to get ppeds profile for mld soc", mld_soc);
  633. return qdf_status;
  634. }
  635. /*
  636. * Check if PPE DS routing is enabled on
  637. * the associated vap.
  638. */
  639. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  640. return qdf_status;
  641. be_soc = dp_get_be_soc_from_dp_soc(mld_soc);
  642. ppe_vp_profile = &be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx];
  643. src_info = ppe_vp_profile->vp_num;
  644. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  645. vdev_id, src_info);
  646. }
  647. return qdf_status;
  648. }
  649. #else
  650. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  651. struct dp_peer *peer,
  652. struct dp_vdev_be *be_vdev
  653. void *args)
  654. {
  655. struct dp_ppe_vp_profile *vp_profile = (struct dp_ppe_vp_profile *)args;
  656. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  657. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  658. if (!be_peer) {
  659. dp_err("BE peer is null");
  660. return QDF_STATUS_E_NULL_VALUE;
  661. }
  662. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  663. be_vdev->vdev.vdev_id,
  664. vp_profile->vp_num);
  665. return qdf_status;
  666. }
  667. #endif
  668. #else
  669. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  670. {
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  674. {
  675. return QDF_STATUS_SUCCESS;
  676. }
  677. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  678. {
  679. return QDF_STATUS_SUCCESS;
  680. }
  681. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  682. {
  683. return QDF_STATUS_SUCCESS;
  684. }
  685. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  686. struct dp_vdev_be *be_vdev,
  687. void *args)
  688. {
  689. return QDF_STATUS_SUCCESS;
  690. }
  691. static inline void dp_ppeds_stop_soc_be(struct dp_soc *soc)
  692. {
  693. }
  694. #endif /* WLAN_SUPPORT_PPEDS */
  695. void dp_reo_shared_qaddr_detach(struct dp_soc *soc)
  696. {
  697. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  698. REO_QUEUE_REF_ML_TABLE_SIZE,
  699. soc->reo_qref.mlo_reo_qref_table_vaddr,
  700. soc->reo_qref.mlo_reo_qref_table_paddr, 0);
  701. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  702. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  703. soc->reo_qref.non_mlo_reo_qref_table_vaddr,
  704. soc->reo_qref.non_mlo_reo_qref_table_paddr, 0);
  705. }
  706. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  707. {
  708. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  709. int i = 0;
  710. dp_soc_ppeds_detach_be(soc);
  711. dp_reo_shared_qaddr_detach(soc);
  712. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  713. dp_hw_cookie_conversion_detach(be_soc,
  714. &be_soc->tx_cc_ctx[i]);
  715. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  716. dp_hw_cookie_conversion_detach(be_soc,
  717. &be_soc->rx_cc_ctx[i]);
  718. qdf_mem_free(be_soc->page_desc_base);
  719. be_soc->page_desc_base = NULL;
  720. return QDF_STATUS_SUCCESS;
  721. }
  722. #ifdef QCA_SUPPORT_DP_GLOBAL_CTX
  723. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  724. {
  725. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  726. if (dp_global)
  727. dp_global->fst_ctx = fst;
  728. }
  729. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  730. {
  731. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  732. if (dp_global)
  733. return dp_global->fst_ctx;
  734. return NULL;
  735. }
  736. static uint32_t dp_rx_fst_release_ref_be(void)
  737. {
  738. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  739. uint32_t rx_fst_ref_cnt;
  740. if (dp_global) {
  741. rx_fst_ref_cnt = qdf_atomic_read(&dp_global->rx_fst_ref_cnt);
  742. qdf_atomic_dec(&dp_global->rx_fst_ref_cnt);
  743. return rx_fst_ref_cnt;
  744. }
  745. return 1;
  746. }
  747. static void dp_rx_fst_get_ref_be(void)
  748. {
  749. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  750. if (dp_global)
  751. qdf_atomic_inc(&dp_global->rx_fst_ref_cnt);
  752. }
  753. #else
  754. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  755. {
  756. }
  757. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  758. {
  759. return NULL;
  760. }
  761. static uint32_t dp_rx_fst_release_ref_be(void)
  762. {
  763. return 1;
  764. }
  765. static void dp_rx_fst_get_ref_be(void)
  766. {
  767. }
  768. #endif
  769. #ifdef WLAN_MLO_MULTI_CHIP
  770. #ifdef WLAN_MCAST_MLO
  771. static inline void
  772. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  773. {
  774. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  775. be_vdev->mcast_primary = false;
  776. be_vdev->seq_num = 0;
  777. hal_tx_mcast_mlo_reinject_routing_set(
  778. soc->hal_soc,
  779. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  780. if (vdev->opmode == wlan_op_mode_ap) {
  781. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  782. vdev->vdev_id,
  783. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  784. }
  785. }
  786. static inline void
  787. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  788. {
  789. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  790. be_vdev->seq_num = 0;
  791. be_vdev->mcast_primary = false;
  792. vdev->mlo_vdev = 0;
  793. }
  794. #else
  795. static inline void
  796. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  797. {
  798. }
  799. static inline void
  800. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  801. {
  802. }
  803. #endif
  804. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  805. {
  806. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  807. qdf_mem_set(be_vdev->partner_vdev_list,
  808. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  809. CDP_INVALID_VDEV_ID);
  810. qdf_mem_set(be_vdev->bridge_vdev_list,
  811. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  812. CDP_INVALID_VDEV_ID);
  813. }
  814. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  815. struct cdp_lro_hash_config *lro_hash)
  816. {
  817. dp_mlo_get_rx_hash_key(soc, lro_hash);
  818. }
  819. #else
  820. static inline void
  821. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  822. {
  823. }
  824. static inline void
  825. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  826. {
  827. }
  828. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  829. {
  830. }
  831. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  832. struct cdp_lro_hash_config *lro_hash)
  833. {
  834. dp_get_rx_hash_key_bytes(lro_hash);
  835. }
  836. #endif
  837. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  838. struct cdp_soc_attach_params *params)
  839. {
  840. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  841. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  842. uint32_t max_tx_rx_desc_num, num_spt_pages;
  843. uint32_t num_entries;
  844. int i = 0;
  845. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  846. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  847. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  848. /* estimate how many SPT DDR pages needed */
  849. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  850. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  851. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  852. be_soc->page_desc_base = qdf_mem_malloc(
  853. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  854. if (!be_soc->page_desc_base) {
  855. dp_err("spt page descs allocation failed");
  856. return QDF_STATUS_E_NOMEM;
  857. }
  858. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  859. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  860. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  861. goto fail;
  862. dp_soc_mlo_fill_params(soc, params);
  863. qdf_status = dp_soc_ppeds_attach_be(soc);
  864. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  865. goto fail;
  866. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  867. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  868. qdf_status =
  869. dp_hw_cookie_conversion_attach(be_soc,
  870. &be_soc->tx_cc_ctx[i],
  871. num_entries,
  872. QDF_DP_TX_DESC_TYPE, i);
  873. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  874. goto fail;
  875. }
  876. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  877. num_entries =
  878. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  879. qdf_status =
  880. dp_hw_cookie_conversion_attach(be_soc,
  881. &be_soc->rx_cc_ctx[i],
  882. num_entries,
  883. QDF_DP_RX_DESC_BUF_TYPE,
  884. i);
  885. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  886. goto fail;
  887. }
  888. return qdf_status;
  889. fail:
  890. dp_soc_detach_be(soc);
  891. return qdf_status;
  892. }
  893. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  894. {
  895. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  896. int i = 0;
  897. qdf_atomic_set(&soc->cmn_init_done, 0);
  898. dp_ppeds_stop_soc_be(soc);
  899. dp_tx_deinit_bank_profiles(be_soc);
  900. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  901. dp_hw_cookie_conversion_deinit(be_soc,
  902. &be_soc->tx_cc_ctx[i]);
  903. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  904. dp_hw_cookie_conversion_deinit(be_soc,
  905. &be_soc->rx_cc_ctx[i]);
  906. dp_ppeds_deinit_soc_be(soc);
  907. return QDF_STATUS_SUCCESS;
  908. }
  909. static QDF_STATUS dp_soc_deinit_be_wrapper(struct dp_soc *soc)
  910. {
  911. QDF_STATUS qdf_status;
  912. qdf_status = dp_soc_deinit_be(soc);
  913. if (QDF_IS_STATUS_ERROR(qdf_status))
  914. return qdf_status;
  915. dp_soc_deinit(soc);
  916. return QDF_STATUS_SUCCESS;
  917. }
  918. static void *dp_soc_init_be(struct dp_soc *soc, HTC_HANDLE htc_handle,
  919. struct hif_opaque_softc *hif_handle)
  920. {
  921. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  922. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  923. int i = 0;
  924. void *ret_addr;
  925. wlan_minidump_log(soc, sizeof(*soc), soc->ctrl_psoc,
  926. WLAN_MD_DP_SOC, "dp_soc");
  927. soc->hif_handle = hif_handle;
  928. soc->hal_soc = hif_get_hal_handle(soc->hif_handle);
  929. if (!soc->hal_soc)
  930. return NULL;
  931. dp_ppeds_init_soc_be(soc);
  932. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  933. qdf_status =
  934. dp_hw_cookie_conversion_init(be_soc,
  935. &be_soc->tx_cc_ctx[i]);
  936. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  937. goto fail;
  938. }
  939. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  940. qdf_status =
  941. dp_hw_cookie_conversion_init(be_soc,
  942. &be_soc->rx_cc_ctx[i]);
  943. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  944. goto fail;
  945. }
  946. /* route vdev_id mismatch notification via FW completion */
  947. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  948. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  949. qdf_status = dp_tx_init_bank_profiles(be_soc);
  950. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  951. goto fail;
  952. /* write WBM/REO cookie conversion CFG register */
  953. dp_cc_reg_cfg_init(soc, true);
  954. ret_addr = dp_soc_init(soc, htc_handle, hif_handle);
  955. if (!ret_addr)
  956. goto fail;
  957. return ret_addr;
  958. fail:
  959. dp_soc_deinit_be(soc);
  960. return NULL;
  961. }
  962. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  963. struct cdp_pdev_attach_params *params)
  964. {
  965. dp_pdev_mlo_fill_params(pdev, params);
  966. return QDF_STATUS_SUCCESS;
  967. }
  968. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  969. {
  970. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  971. return QDF_STATUS_SUCCESS;
  972. }
  973. #ifdef INTRA_BSS_FWD_OFFLOAD
  974. static
  975. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  976. {
  977. soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id,
  978. enable);
  979. }
  980. #else
  981. static
  982. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  983. {
  984. }
  985. #endif
  986. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  987. {
  988. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  989. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  990. struct dp_pdev *pdev = vdev->pdev;
  991. if (vdev->opmode == wlan_op_mode_monitor)
  992. return QDF_STATUS_SUCCESS;
  993. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  994. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  995. vdev->bank_id = be_vdev->bank_id;
  996. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  997. QDF_BUG(0);
  998. return QDF_STATUS_E_FAULT;
  999. }
  1000. if (vdev->opmode == wlan_op_mode_sta) {
  1001. if (soc->cdp_soc.ol_ops->set_mec_timer)
  1002. soc->cdp_soc.ol_ops->set_mec_timer(
  1003. soc->ctrl_psoc,
  1004. vdev->vdev_id,
  1005. DP_AST_AGING_TIMER_DEFAULT_MS);
  1006. if (pdev->isolation)
  1007. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  1008. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1009. else
  1010. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  1011. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1012. } else if (vdev->ap_bridge_enabled) {
  1013. dp_vdev_set_intra_bss(soc, vdev->vdev_id, true);
  1014. }
  1015. dp_mlo_mcast_init(soc, vdev);
  1016. dp_mlo_init_ptnr_list(vdev);
  1017. return QDF_STATUS_SUCCESS;
  1018. }
  1019. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1020. {
  1021. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1022. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1023. if (vdev->opmode == wlan_op_mode_monitor)
  1024. return QDF_STATUS_SUCCESS;
  1025. if (vdev->opmode == wlan_op_mode_ap)
  1026. dp_mlo_mcast_deinit(soc, vdev);
  1027. dp_tx_put_bank_profile(be_soc, be_vdev);
  1028. dp_clr_mlo_ptnr_list(soc, vdev);
  1029. return QDF_STATUS_SUCCESS;
  1030. }
  1031. #ifdef WLAN_SUPPORT_PPEDS
  1032. static void dp_soc_txrx_peer_setup_be(struct dp_soc *soc, uint8_t vdev_id,
  1033. uint8_t *peer_mac)
  1034. {
  1035. struct dp_vdev_be *be_vdev;
  1036. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  1037. struct dp_soc_be *be_soc;
  1038. struct cdp_ds_vp_params vp_params = {0};
  1039. struct cdp_soc_t *cdp_soc;
  1040. enum wlan_op_mode vdev_opmode;
  1041. struct dp_peer *peer;
  1042. struct dp_peer *tgt_peer = NULL;
  1043. struct dp_soc *tgt_soc = NULL;
  1044. peer = dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id, DP_MOD_ID_CDP);
  1045. if (!peer)
  1046. return;
  1047. vdev_opmode = peer->vdev->opmode;
  1048. if (vdev_opmode != wlan_op_mode_ap &&
  1049. vdev_opmode != wlan_op_mode_sta) {
  1050. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  1051. return;
  1052. }
  1053. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1054. tgt_soc = tgt_peer->vdev->pdev->soc;
  1055. be_soc = dp_get_be_soc_from_dp_soc(tgt_soc);
  1056. cdp_soc = &tgt_soc->cdp_soc;
  1057. be_vdev = dp_get_be_vdev_from_dp_vdev(tgt_peer->vdev);
  1058. if (!be_vdev) {
  1059. qdf_err("BE vap is null");
  1060. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1061. goto fail;
  1062. }
  1063. /*
  1064. * Extract the VP profile from the VAP
  1065. */
  1066. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  1067. dp_err("%pK: Register get ppeds profile info first", cdp_soc);
  1068. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1069. goto fail;
  1070. }
  1071. /*
  1072. * Check if PPE DS routing is enabled on the associated vap.
  1073. */
  1074. qdf_status =
  1075. cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(tgt_soc->ctrl_psoc,
  1076. tgt_peer->vdev->vdev_id,
  1077. &vp_params);
  1078. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  1079. dp_err("%pK: Could not find ppeds profile info vdev", be_vdev);
  1080. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1081. goto fail;
  1082. }
  1083. if (vp_params.ppe_vp_type == PPE_VP_USER_TYPE_DS) {
  1084. qdf_status = dp_peer_setup_ppeds_be(tgt_soc, tgt_peer, be_vdev,
  1085. (void *)&be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx]);
  1086. }
  1087. fail:
  1088. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  1089. if (!QDF_IS_STATUS_SUCCESS(qdf_status)) {
  1090. dp_err("Unable to do ppeds peer setup");
  1091. qdf_assert_always(0);
  1092. }
  1093. }
  1094. #else
  1095. static inline
  1096. void dp_soc_txrx_peer_setup_be(struct dp_soc *soc, uint8_t vdev_id,
  1097. uint8_t *peer_mac)
  1098. {
  1099. }
  1100. #endif
  1101. static QDF_STATUS dp_peer_setup_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1102. uint8_t *peer_mac,
  1103. struct cdp_peer_setup_info *setup_info)
  1104. {
  1105. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  1106. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  1107. qdf_status = dp_peer_setup_wifi3(soc_hdl, vdev_id, peer_mac,
  1108. setup_info);
  1109. if (!QDF_IS_STATUS_SUCCESS(qdf_status)) {
  1110. dp_err("Unable to dp peer setup");
  1111. return qdf_status;
  1112. }
  1113. dp_soc_txrx_peer_setup_be(soc, vdev_id, peer_mac);
  1114. return QDF_STATUS_SUCCESS;
  1115. }
  1116. qdf_size_t dp_get_soc_context_size_be(void)
  1117. {
  1118. return sizeof(struct dp_soc_be);
  1119. }
  1120. #ifdef CONFIG_WORD_BASED_TLV
  1121. /**
  1122. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  1123. * @soc: Common DP soc handle
  1124. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  1125. *
  1126. * Return: none
  1127. */
  1128. static inline void
  1129. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1130. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1131. {
  1132. htt_tlv_filter->rx_msdu_end_wmask =
  1133. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  1134. htt_tlv_filter->rx_mpdu_start_wmask =
  1135. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  1136. }
  1137. #else
  1138. static inline void
  1139. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1140. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1141. {
  1142. }
  1143. #endif
  1144. #ifdef WLAN_SUPPORT_PPEDS
  1145. static
  1146. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1147. int ring_type, int ring_num)
  1148. {
  1149. if (srng->irq >= 0) {
  1150. qdf_dev_clear_irq_status_flags(srng->irq, IRQ_DISABLE_UNLAZY);
  1151. if (ring_type == WBM2SW_RELEASE &&
  1152. ring_num == WBM2_SW_PPE_REL_RING_ID)
  1153. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  1154. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  1155. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  1156. dp_get_ppe_ds_ctxt(soc));
  1157. }
  1158. }
  1159. static
  1160. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1161. int vector, int ring_type, int ring_num)
  1162. {
  1163. int irq = -1, ret = 0;
  1164. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1165. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  1166. srng->irq = -1;
  1167. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  1168. qdf_dev_set_irq_status_flags(irq, IRQ_DISABLE_UNLAZY);
  1169. if (ring_type == WBM2SW_RELEASE &&
  1170. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  1171. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  1172. "pci%d_ppe_wbm_rel", pci_slot);
  1173. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1174. dp_ppeds_handle_tx_comp,
  1175. IRQF_SHARED | IRQF_NO_SUSPEND,
  1176. be_soc->irq_name[2], (void *)soc);
  1177. if (ret)
  1178. goto fail;
  1179. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  1180. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  1181. "pci%d_reo2ppe", pci_slot);
  1182. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1183. dp_ppe_ds_reo2ppe_irq_handler,
  1184. IRQF_SHARED | IRQF_NO_SUSPEND,
  1185. be_soc->irq_name[0],
  1186. dp_get_ppe_ds_ctxt(soc));
  1187. if (ret)
  1188. goto fail;
  1189. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  1190. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  1191. "pci%d_ppe2tcl", pci_slot);
  1192. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1193. dp_ppe_ds_ppe2tcl_irq_handler,
  1194. IRQF_NO_SUSPEND,
  1195. be_soc->irq_name[1],
  1196. dp_get_ppe_ds_ctxt(soc));
  1197. if (ret)
  1198. goto fail;
  1199. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  1200. } else {
  1201. return 0;
  1202. }
  1203. srng->irq = irq;
  1204. dp_info("Registered irq %d for soc %pK ring type %d",
  1205. irq, soc, ring_type);
  1206. return 0;
  1207. fail:
  1208. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  1209. ring_type, irq, vector);
  1210. qdf_dev_clear_irq_status_flags(irq, IRQ_DISABLE_UNLAZY);
  1211. return ret;
  1212. }
  1213. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1214. {
  1215. if (srng->irq >= 0)
  1216. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  1217. }
  1218. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1219. {
  1220. if (srng->irq >= 0)
  1221. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  1222. }
  1223. #endif
  1224. #ifdef NO_RX_PKT_HDR_TLV
  1225. /**
  1226. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1227. * @soc: Common DP soc handle
  1228. *
  1229. * Return: QDF_STATUS
  1230. */
  1231. static QDF_STATUS
  1232. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1233. {
  1234. int i;
  1235. int mac_id;
  1236. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1237. struct dp_srng *rx_mac_srng;
  1238. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1239. /*
  1240. * In Beryllium chipset msdu_start, mpdu_end
  1241. * and rx_attn are part of msdu_end/mpdu_start
  1242. */
  1243. htt_tlv_filter.msdu_start = 0;
  1244. htt_tlv_filter.mpdu_end = 0;
  1245. htt_tlv_filter.attention = 0;
  1246. htt_tlv_filter.mpdu_start = 1;
  1247. htt_tlv_filter.msdu_end = 1;
  1248. htt_tlv_filter.packet = 1;
  1249. htt_tlv_filter.packet_header = 0;
  1250. htt_tlv_filter.ppdu_start = 0;
  1251. htt_tlv_filter.ppdu_end = 0;
  1252. htt_tlv_filter.ppdu_end_user_stats = 0;
  1253. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1254. htt_tlv_filter.ppdu_end_status_done = 0;
  1255. htt_tlv_filter.enable_fp = 1;
  1256. htt_tlv_filter.enable_md = 0;
  1257. htt_tlv_filter.enable_md = 0;
  1258. htt_tlv_filter.enable_mo = 0;
  1259. htt_tlv_filter.fp_mgmt_filter = 0;
  1260. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1261. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1262. FILTER_DATA_DATA);
  1263. htt_tlv_filter.fp_data_filter |=
  1264. hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
  1265. FILTER_DATA_MCAST : 0;
  1266. htt_tlv_filter.mo_mgmt_filter = 0;
  1267. htt_tlv_filter.mo_ctrl_filter = 0;
  1268. htt_tlv_filter.mo_data_filter = 0;
  1269. htt_tlv_filter.md_data_filter = 0;
  1270. htt_tlv_filter.offset_valid = true;
  1271. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1272. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1273. htt_tlv_filter.rx_msdu_start_offset = 0;
  1274. htt_tlv_filter.rx_attn_offset = 0;
  1275. /*
  1276. * For monitor mode, the packet hdr tlv is enabled later during
  1277. * filter update
  1278. */
  1279. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1280. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1281. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1282. else
  1283. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1284. /*Not subscribing rx_pkt_header*/
  1285. htt_tlv_filter.rx_header_offset = 0;
  1286. htt_tlv_filter.rx_mpdu_start_offset =
  1287. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1288. htt_tlv_filter.rx_msdu_end_offset =
  1289. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1290. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1291. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1292. struct dp_pdev *pdev = soc->pdev_list[i];
  1293. if (!pdev)
  1294. continue;
  1295. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1296. int mac_for_pdev =
  1297. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1298. /*
  1299. * Obtain lmac id from pdev to access the LMAC ring
  1300. * in soc context
  1301. */
  1302. int lmac_id =
  1303. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1304. pdev->pdev_id);
  1305. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1306. if (!rx_mac_srng->hal_srng)
  1307. continue;
  1308. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1309. rx_mac_srng->hal_srng,
  1310. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1311. &htt_tlv_filter);
  1312. }
  1313. }
  1314. return status;
  1315. }
  1316. #else
  1317. /**
  1318. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1319. * @soc: Common DP soc handle
  1320. *
  1321. * Return: QDF_STATUS
  1322. */
  1323. static QDF_STATUS
  1324. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1325. {
  1326. int i;
  1327. int mac_id;
  1328. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1329. struct dp_srng *rx_mac_srng;
  1330. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1331. /*
  1332. * In Beryllium chipset msdu_start, mpdu_end
  1333. * and rx_attn are part of msdu_end/mpdu_start
  1334. */
  1335. htt_tlv_filter.msdu_start = 0;
  1336. htt_tlv_filter.mpdu_end = 0;
  1337. htt_tlv_filter.attention = 0;
  1338. htt_tlv_filter.mpdu_start = 1;
  1339. htt_tlv_filter.msdu_end = 1;
  1340. htt_tlv_filter.packet = 1;
  1341. htt_tlv_filter.packet_header = 1;
  1342. htt_tlv_filter.ppdu_start = 0;
  1343. htt_tlv_filter.ppdu_end = 0;
  1344. htt_tlv_filter.ppdu_end_user_stats = 0;
  1345. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1346. htt_tlv_filter.ppdu_end_status_done = 0;
  1347. htt_tlv_filter.enable_fp = 1;
  1348. htt_tlv_filter.enable_md = 0;
  1349. htt_tlv_filter.enable_md = 0;
  1350. htt_tlv_filter.enable_mo = 0;
  1351. htt_tlv_filter.fp_mgmt_filter = 0;
  1352. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1353. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1354. FILTER_DATA_DATA);
  1355. htt_tlv_filter.fp_data_filter |=
  1356. hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
  1357. FILTER_DATA_MCAST : 0;
  1358. htt_tlv_filter.mo_mgmt_filter = 0;
  1359. htt_tlv_filter.mo_ctrl_filter = 0;
  1360. htt_tlv_filter.mo_data_filter = 0;
  1361. htt_tlv_filter.md_data_filter = 0;
  1362. htt_tlv_filter.offset_valid = true;
  1363. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1364. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1365. htt_tlv_filter.rx_msdu_start_offset = 0;
  1366. htt_tlv_filter.rx_attn_offset = 0;
  1367. /*
  1368. * For monitor mode, the packet hdr tlv is enabled later during
  1369. * filter update
  1370. */
  1371. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1372. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1373. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1374. else
  1375. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1376. htt_tlv_filter.rx_header_offset =
  1377. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1378. htt_tlv_filter.rx_mpdu_start_offset =
  1379. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1380. htt_tlv_filter.rx_msdu_end_offset =
  1381. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1382. dp_info("TLV subscription\n"
  1383. "msdu_start %d, mpdu_end %d, attention %d"
  1384. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1385. "TLV offsets\n"
  1386. "msdu_start %d, mpdu_end %d, attention %d"
  1387. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1388. htt_tlv_filter.msdu_start,
  1389. htt_tlv_filter.mpdu_end,
  1390. htt_tlv_filter.attention,
  1391. htt_tlv_filter.mpdu_start,
  1392. htt_tlv_filter.msdu_end,
  1393. htt_tlv_filter.packet_header,
  1394. htt_tlv_filter.packet,
  1395. htt_tlv_filter.rx_msdu_start_offset,
  1396. htt_tlv_filter.rx_mpdu_end_offset,
  1397. htt_tlv_filter.rx_attn_offset,
  1398. htt_tlv_filter.rx_mpdu_start_offset,
  1399. htt_tlv_filter.rx_msdu_end_offset,
  1400. htt_tlv_filter.rx_header_offset,
  1401. htt_tlv_filter.rx_packet_offset);
  1402. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1403. struct dp_pdev *pdev = soc->pdev_list[i];
  1404. if (!pdev)
  1405. continue;
  1406. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1407. int mac_for_pdev =
  1408. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1409. /*
  1410. * Obtain lmac id from pdev to access the LMAC ring
  1411. * in soc context
  1412. */
  1413. int lmac_id =
  1414. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1415. pdev->pdev_id);
  1416. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1417. if (!rx_mac_srng->hal_srng)
  1418. continue;
  1419. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1420. rx_mac_srng->hal_srng,
  1421. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1422. &htt_tlv_filter);
  1423. }
  1424. }
  1425. return status;
  1426. }
  1427. #endif
  1428. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1429. /**
  1430. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1431. * near-full IRQs.
  1432. * @soc: Datapath SoC handle
  1433. * @int_ctx: Interrupt context
  1434. * @dp_budget: Budget of the work that can be done in the bottom half
  1435. *
  1436. * Return: work done in the handler
  1437. */
  1438. static uint32_t
  1439. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1440. uint32_t dp_budget)
  1441. {
  1442. int ring = 0;
  1443. int budget = dp_budget;
  1444. uint32_t work_done = 0;
  1445. uint32_t remaining_quota = dp_budget;
  1446. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1447. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1448. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1449. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1450. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1451. rx_near_full_grp_2_mask;
  1452. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1453. rx_near_full_mask,
  1454. tx_ring_near_full_mask);
  1455. if (rx_near_full_mask) {
  1456. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1457. if (!(rx_near_full_mask & (1 << ring)))
  1458. continue;
  1459. work_done = dp_rx_nf_process(int_ctx,
  1460. soc->reo_dest_ring[ring].hal_srng,
  1461. ring, remaining_quota);
  1462. if (work_done) {
  1463. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1464. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1465. rx_near_full_mask, ring,
  1466. work_done,
  1467. budget);
  1468. budget -= work_done;
  1469. if (budget <= 0)
  1470. goto budget_done;
  1471. remaining_quota = budget;
  1472. }
  1473. }
  1474. }
  1475. if (tx_ring_near_full_mask) {
  1476. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1477. if (!(tx_ring_near_full_mask & (1 << ring)))
  1478. continue;
  1479. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1480. soc->tx_comp_ring[ring].hal_srng,
  1481. ring, remaining_quota);
  1482. if (work_done) {
  1483. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1484. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1485. tx_ring_near_full_mask, ring,
  1486. work_done, budget);
  1487. budget -= work_done;
  1488. if (budget <= 0)
  1489. break;
  1490. remaining_quota = budget;
  1491. }
  1492. }
  1493. }
  1494. intr_stats->num_near_full_masks++;
  1495. budget_done:
  1496. return dp_budget - budget;
  1497. }
  1498. /**
  1499. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1500. * state and set the reap_limit appropriately
  1501. * as per the near full state
  1502. * @soc: Datapath soc handle
  1503. * @dp_srng: Datapath handle for SRNG
  1504. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1505. * the srng near-full state
  1506. *
  1507. * Return: 1, if the srng is in near-full state
  1508. * 0, if the srng is not in near-full state
  1509. */
  1510. static int
  1511. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1512. struct dp_srng *dp_srng,
  1513. int *max_reap_limit)
  1514. {
  1515. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1516. }
  1517. /**
  1518. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1519. * near full IRQ handling operations.
  1520. * @arch_ops: arch ops handle
  1521. *
  1522. * Return: none
  1523. */
  1524. static inline void
  1525. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1526. {
  1527. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1528. arch_ops->dp_srng_test_and_update_nf_params =
  1529. dp_srng_test_and_update_nf_params_be;
  1530. }
  1531. #else
  1532. static inline void
  1533. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1534. {
  1535. }
  1536. #endif
  1537. static inline
  1538. QDF_STATUS dp_srng_init_be(struct dp_soc *soc, struct dp_srng *srng,
  1539. int ring_type, int ring_num, int mac_id)
  1540. {
  1541. return dp_srng_init_idx(soc, srng, ring_type, ring_num, mac_id, 0);
  1542. }
  1543. #ifdef WLAN_SUPPORT_PPEDS
  1544. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1545. {
  1546. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1547. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1548. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1549. if (!be_soc->ppeds_handle)
  1550. return;
  1551. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1552. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1553. be_soc->ppe2tcl_ring.alloc_size,
  1554. soc->ctrl_psoc,
  1555. WLAN_MD_DP_SRNG_PPE2TCL,
  1556. "ppe2tcl_ring");
  1557. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1558. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1559. be_soc->reo2ppe_ring.alloc_size,
  1560. soc->ctrl_psoc,
  1561. WLAN_MD_DP_SRNG_REO2PPE,
  1562. "reo2ppe_ring");
  1563. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1564. WBM2_SW_PPE_REL_RING_ID);
  1565. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1566. be_soc->ppeds_wbm_release_ring.alloc_size,
  1567. soc->ctrl_psoc,
  1568. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1569. "ppeds_wbm_release_ring");
  1570. }
  1571. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1572. {
  1573. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1574. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1575. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1576. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1577. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1578. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1579. }
  1580. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1581. {
  1582. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1583. uint32_t entries;
  1584. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1585. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1586. if (!be_soc->ppeds_handle)
  1587. return QDF_STATUS_SUCCESS;
  1588. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1589. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1590. entries, 0)) {
  1591. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1592. goto fail;
  1593. }
  1594. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1595. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1596. entries, 0)) {
  1597. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1598. goto fail;
  1599. }
  1600. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1601. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1602. entries, 1)) {
  1603. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1604. soc);
  1605. goto fail;
  1606. }
  1607. return QDF_STATUS_SUCCESS;
  1608. fail:
  1609. dp_soc_ppeds_srng_free(soc);
  1610. return QDF_STATUS_E_NOMEM;
  1611. }
  1612. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1613. {
  1614. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1615. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1616. hal_soc_handle_t hal_soc = soc->hal_soc;
  1617. struct dp_ppe_ds_idxs idx = {0};
  1618. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1619. if (!be_soc->ppeds_handle)
  1620. return QDF_STATUS_SUCCESS;
  1621. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1622. dp_err("%pK: ppeds registration failed", soc);
  1623. goto fail;
  1624. }
  1625. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1626. idx.reo2ppe_start_idx)) {
  1627. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1628. goto fail;
  1629. }
  1630. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1631. be_soc->reo2ppe_ring.alloc_size,
  1632. soc->ctrl_psoc,
  1633. WLAN_MD_DP_SRNG_REO2PPE,
  1634. "reo2ppe_ring");
  1635. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1636. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1637. idx.ppe2tcl_start_idx)) {
  1638. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1639. goto fail;
  1640. }
  1641. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1642. be_soc->ppe2tcl_ring.alloc_size,
  1643. soc->ctrl_psoc,
  1644. WLAN_MD_DP_SRNG_PPE2TCL,
  1645. "ppe2tcl_ring");
  1646. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1647. be_soc->ppe2tcl_ring.hal_srng,
  1648. WBM2_SW_PPE_REL_MAP_ID);
  1649. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1650. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1651. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1652. soc);
  1653. goto fail;
  1654. }
  1655. wlan_minidump_log(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1656. be_soc->ppeds_wbm_release_ring.alloc_size,
  1657. soc->ctrl_psoc, WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1658. "ppeds_wbm_release_ring");
  1659. return QDF_STATUS_SUCCESS;
  1660. fail:
  1661. dp_soc_ppeds_srng_deinit(soc);
  1662. return QDF_STATUS_E_NOMEM;
  1663. }
  1664. #else
  1665. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1666. {
  1667. }
  1668. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1669. {
  1670. }
  1671. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1672. {
  1673. return QDF_STATUS_SUCCESS;
  1674. }
  1675. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1676. {
  1677. return QDF_STATUS_SUCCESS;
  1678. }
  1679. #endif
  1680. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1681. {
  1682. uint32_t i;
  1683. dp_soc_ppeds_srng_deinit(soc);
  1684. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1685. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1686. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1687. RXDMA_BUF, 0);
  1688. }
  1689. }
  1690. }
  1691. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1692. {
  1693. uint32_t i;
  1694. dp_soc_ppeds_srng_free(soc);
  1695. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1696. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1697. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1698. }
  1699. }
  1700. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1701. {
  1702. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1703. uint32_t ring_size;
  1704. uint32_t i;
  1705. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1706. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1707. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1708. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1709. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1710. RXDMA_BUF, ring_size, 0)) {
  1711. dp_err("%pK: dp_srng_alloc failed refill ring",
  1712. soc);
  1713. goto fail;
  1714. }
  1715. }
  1716. }
  1717. if (dp_soc_ppeds_srng_alloc(soc)) {
  1718. dp_err("%pK: ppe rings alloc failed",
  1719. soc);
  1720. goto fail;
  1721. }
  1722. return QDF_STATUS_SUCCESS;
  1723. fail:
  1724. dp_soc_srng_free_be(soc);
  1725. return QDF_STATUS_E_NOMEM;
  1726. }
  1727. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1728. {
  1729. int i = 0;
  1730. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1731. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1732. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1733. RXDMA_BUF, 0, 0)) {
  1734. dp_err("%pK: dp_srng_init failed refill ring",
  1735. soc);
  1736. goto fail;
  1737. }
  1738. }
  1739. }
  1740. if (dp_soc_ppeds_srng_init(soc)) {
  1741. dp_err("%pK: ppe ds rings init failed",
  1742. soc);
  1743. goto fail;
  1744. }
  1745. return QDF_STATUS_SUCCESS;
  1746. fail:
  1747. dp_soc_srng_deinit_be(soc);
  1748. return QDF_STATUS_E_NOMEM;
  1749. }
  1750. #ifdef WLAN_FEATURE_11BE_MLO
  1751. static inline unsigned
  1752. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1753. union dp_align_mac_addr *mac_addr)
  1754. {
  1755. uint32_t index;
  1756. index =
  1757. mac_addr->align2.bytes_ab ^
  1758. mac_addr->align2.bytes_cd ^
  1759. mac_addr->align2.bytes_ef;
  1760. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1761. index &= mld_hash_obj->mld_peer_hash.mask;
  1762. return index;
  1763. }
  1764. QDF_STATUS
  1765. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1766. int hash_elems)
  1767. {
  1768. int i, log2;
  1769. if (!mld_hash_obj)
  1770. return QDF_STATUS_E_FAILURE;
  1771. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1772. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1773. log2 = dp_log2_ceil(hash_elems);
  1774. hash_elems = 1 << log2;
  1775. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1776. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1777. /* allocate an array of TAILQ peer object lists */
  1778. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1779. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1780. if (!mld_hash_obj->mld_peer_hash.bins)
  1781. return QDF_STATUS_E_NOMEM;
  1782. for (i = 0; i < hash_elems; i++)
  1783. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1784. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1785. return QDF_STATUS_SUCCESS;
  1786. }
  1787. void
  1788. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1789. {
  1790. if (!mld_hash_obj)
  1791. return;
  1792. if (mld_hash_obj->mld_peer_hash.bins) {
  1793. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1794. mld_hash_obj->mld_peer_hash.bins = NULL;
  1795. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1796. }
  1797. }
  1798. #ifdef WLAN_MLO_MULTI_CHIP
  1799. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1800. {
  1801. /* In case of MULTI chip MLO peer hash table when MLO global object
  1802. * is created, avoid from SOC attach path
  1803. */
  1804. return QDF_STATUS_SUCCESS;
  1805. }
  1806. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1807. {
  1808. }
  1809. #else
  1810. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1811. {
  1812. dp_mld_peer_hash_obj_t mld_hash_obj;
  1813. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1814. if (!mld_hash_obj)
  1815. return QDF_STATUS_E_FAILURE;
  1816. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1817. }
  1818. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1819. {
  1820. dp_mld_peer_hash_obj_t mld_hash_obj;
  1821. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1822. if (!mld_hash_obj)
  1823. return;
  1824. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1825. }
  1826. #endif
  1827. #ifdef QCA_ENHANCED_STATS_SUPPORT
  1828. static uint8_t
  1829. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1830. {
  1831. struct dp_pdev_be *be_pdev = dp_get_be_pdev_from_dp_pdev(pdev);
  1832. return be_pdev->mlo_link_id;
  1833. }
  1834. #else
  1835. static uint8_t
  1836. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1837. {
  1838. return 0;
  1839. }
  1840. #endif /* QCA_ENHANCED_STATS_SUPPORT */
  1841. static struct dp_peer *
  1842. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1843. uint8_t *peer_mac_addr,
  1844. int mac_addr_is_aligned,
  1845. enum dp_mod_id mod_id,
  1846. uint8_t vdev_id)
  1847. {
  1848. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1849. uint32_t index;
  1850. struct dp_peer *peer;
  1851. struct dp_vdev *vdev;
  1852. dp_mld_peer_hash_obj_t mld_hash_obj;
  1853. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1854. if (!mld_hash_obj)
  1855. return NULL;
  1856. if (!mld_hash_obj->mld_peer_hash.bins)
  1857. return NULL;
  1858. if (mac_addr_is_aligned) {
  1859. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1860. } else {
  1861. qdf_mem_copy(
  1862. &local_mac_addr_aligned.raw[0],
  1863. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1864. mac_addr = &local_mac_addr_aligned;
  1865. }
  1866. if (vdev_id != DP_VDEV_ALL) {
  1867. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1868. if (!vdev) {
  1869. dp_err("vdev is null");
  1870. return NULL;
  1871. }
  1872. } else {
  1873. vdev = NULL;
  1874. }
  1875. /* search mld peer table if no link peer for given mac address */
  1876. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1877. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1878. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1879. hash_list_elem) {
  1880. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1881. if ((vdev_id == DP_VDEV_ALL) || (
  1882. dp_peer_find_mac_addr_cmp(
  1883. &peer->vdev->mld_mac_addr,
  1884. &vdev->mld_mac_addr) == 0)) {
  1885. /* take peer reference before returning */
  1886. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1887. QDF_STATUS_SUCCESS)
  1888. peer = NULL;
  1889. if (vdev)
  1890. dp_vdev_unref_delete(soc, vdev, mod_id);
  1891. qdf_spin_unlock_bh(
  1892. &mld_hash_obj->mld_peer_hash_lock);
  1893. return peer;
  1894. }
  1895. }
  1896. }
  1897. if (vdev)
  1898. dp_vdev_unref_delete(soc, vdev, mod_id);
  1899. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1900. return NULL; /* failure */
  1901. }
  1902. static void
  1903. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1904. {
  1905. uint32_t index;
  1906. struct dp_peer *tmppeer = NULL;
  1907. int found = 0;
  1908. dp_mld_peer_hash_obj_t mld_hash_obj;
  1909. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1910. if (!mld_hash_obj)
  1911. return;
  1912. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1913. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1914. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1915. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1916. hash_list_elem) {
  1917. if (tmppeer == peer) {
  1918. found = 1;
  1919. break;
  1920. }
  1921. }
  1922. QDF_ASSERT(found);
  1923. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1924. hash_list_elem);
  1925. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)",
  1926. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found);
  1927. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1928. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1929. }
  1930. static void
  1931. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1932. {
  1933. uint32_t index;
  1934. dp_mld_peer_hash_obj_t mld_hash_obj;
  1935. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1936. if (!mld_hash_obj)
  1937. return;
  1938. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1939. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1940. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1941. DP_MOD_ID_CONFIG))) {
  1942. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1943. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1944. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1945. return;
  1946. }
  1947. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1948. hash_list_elem);
  1949. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1950. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added",
  1951. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1952. }
  1953. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1954. {
  1955. uint32_t index;
  1956. struct dp_peer *peer;
  1957. dp_mld_peer_hash_obj_t mld_hash_obj;
  1958. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1959. if (!mld_hash_obj)
  1960. return;
  1961. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1962. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1963. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1964. hash_list_elem) {
  1965. dp_print_peer_ast_entries(soc, peer, NULL);
  1966. }
  1967. }
  1968. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1969. }
  1970. #endif
  1971. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1972. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1973. struct dp_vdev *vdev)
  1974. {
  1975. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1976. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1977. hal_soc_handle_t hal_soc = soc->hal_soc;
  1978. uint8_t vdev_id = vdev->vdev_id;
  1979. if (vdev->opmode == wlan_op_mode_sta) {
  1980. if (vdev->pdev->isolation)
  1981. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1982. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1983. else
  1984. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1985. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1986. } else if (vdev->opmode == wlan_op_mode_ap) {
  1987. hal_tx_mcast_mlo_reinject_routing_set(
  1988. hal_soc,
  1989. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1990. if (vdev->mlo_vdev) {
  1991. hal_tx_vdev_mcast_ctrl_set(
  1992. hal_soc,
  1993. vdev_id,
  1994. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1995. } else {
  1996. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1997. vdev_id,
  1998. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1999. }
  2000. }
  2001. }
  2002. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  2003. {
  2004. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2005. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2006. union hal_tx_bank_config *bank_config;
  2007. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  2008. return;
  2009. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  2010. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  2011. be_vdev->bank_id);
  2012. }
  2013. #endif
  2014. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  2015. defined(WLAN_MCAST_MLO)
  2016. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  2017. struct dp_vdev *ptnr_vdev,
  2018. void *arg)
  2019. {
  2020. struct dp_vdev_be *be_ptnr_vdev =
  2021. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  2022. be_ptnr_vdev->mcast_primary = false;
  2023. }
  2024. #if defined(CONFIG_MLO_SINGLE_DEV)
  2025. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  2026. struct dp_vdev *vdev,
  2027. cdp_config_param_type val)
  2028. {
  2029. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2030. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  2031. be_vdev->vdev.pdev->soc);
  2032. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  2033. vdev->mlo_vdev = 1;
  2034. if (be_vdev->mcast_primary) {
  2035. struct cdp_txrx_peer_params_update params = {0};
  2036. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  2037. dp_mlo_mcast_reset_pri_mcast,
  2038. (void *)&be_vdev->mcast_primary,
  2039. DP_MOD_ID_TX_MCAST,
  2040. DP_LINK_VDEV_ITER);
  2041. params.chip_id = be_soc->mlo_chip_id;
  2042. params.pdev_id = be_vdev->vdev.pdev->pdev_id;
  2043. params.osif_vdev = be_vdev->vdev.osif_vdev;
  2044. dp_wdi_event_handler(
  2045. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  2046. be_vdev->vdev.pdev->soc,
  2047. (void *)&params, CDP_INVALID_PEER,
  2048. WDI_NO_VAL, params.pdev_id);
  2049. }
  2050. }
  2051. static
  2052. void dp_get_vdev_stats_for_unmap_peer_be(struct dp_vdev *vdev,
  2053. struct dp_peer *peer,
  2054. struct cdp_vdev_stats **vdev_stats)
  2055. {
  2056. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2057. if (!IS_DP_LEGACY_PEER(peer))
  2058. *vdev_stats = &be_vdev->mlo_stats;
  2059. }
  2060. #else
  2061. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  2062. struct dp_vdev *vdev,
  2063. cdp_config_param_type val)
  2064. {
  2065. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2066. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  2067. be_vdev->vdev.pdev->soc);
  2068. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  2069. vdev->mlo_vdev = 1;
  2070. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  2071. vdev->vdev_id,
  2072. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  2073. if (be_vdev->mcast_primary) {
  2074. struct cdp_txrx_peer_params_update params = {0};
  2075. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  2076. dp_mlo_mcast_reset_pri_mcast,
  2077. (void *)&be_vdev->mcast_primary,
  2078. DP_MOD_ID_TX_MCAST,
  2079. DP_LINK_VDEV_ITER);
  2080. params.chip_id = be_soc->mlo_chip_id;
  2081. params.pdev_id = vdev->pdev->pdev_id;
  2082. params.osif_vdev = vdev->osif_vdev;
  2083. dp_wdi_event_handler(
  2084. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  2085. vdev->pdev->soc,
  2086. (void *)&params, CDP_INVALID_PEER,
  2087. WDI_NO_VAL, params.pdev_id);
  2088. }
  2089. }
  2090. #endif
  2091. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  2092. struct dp_vdev *vdev,
  2093. cdp_config_param_type val)
  2094. {
  2095. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2096. be_vdev->mcast_primary = false;
  2097. vdev->mlo_vdev = 0;
  2098. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  2099. vdev->vdev_id,
  2100. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  2101. }
  2102. /**
  2103. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  2104. * params related to multicast
  2105. * @soc: DP soc handle
  2106. * @vdev: pointer to vdev structure
  2107. * @val: buffer address
  2108. *
  2109. * Return: QDF_STATUS
  2110. */
  2111. static
  2112. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  2113. struct dp_vdev *vdev,
  2114. cdp_config_param_type *val)
  2115. {
  2116. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2117. if (be_vdev->mcast_primary)
  2118. val->cdp_vdev_param_mcast_vdev = true;
  2119. else
  2120. val->cdp_vdev_param_mcast_vdev = false;
  2121. return QDF_STATUS_SUCCESS;
  2122. }
  2123. #else
  2124. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  2125. struct dp_vdev *vdev,
  2126. cdp_config_param_type val)
  2127. {
  2128. }
  2129. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  2130. struct dp_vdev *vdev,
  2131. cdp_config_param_type val)
  2132. {
  2133. }
  2134. static
  2135. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  2136. struct dp_vdev *vdev,
  2137. cdp_config_param_type *val)
  2138. {
  2139. return QDF_STATUS_SUCCESS;
  2140. }
  2141. static
  2142. void dp_get_vdev_stats_for_unmap_peer_be(struct dp_vdev *vdev,
  2143. struct dp_peer *peer,
  2144. struct cdp_vdev_stats **vdev_stats)
  2145. {
  2146. }
  2147. #endif
  2148. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  2149. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  2150. uint8_t tx_ring_id,
  2151. uint8_t bm_id)
  2152. {
  2153. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  2154. soc->tcl_data_ring[tx_ring_id].hal_srng,
  2155. bm_id);
  2156. }
  2157. #else
  2158. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  2159. uint8_t tx_ring_id,
  2160. uint8_t bm_id)
  2161. {
  2162. }
  2163. #endif
  2164. /**
  2165. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  2166. * @soc: DP soc handle
  2167. * @vdev: pointer to vdev structure
  2168. * @param: parameter type to get value
  2169. * @val: value
  2170. *
  2171. * Return: QDF_STATUS
  2172. */
  2173. static
  2174. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  2175. struct dp_vdev *vdev,
  2176. enum cdp_vdev_param_type param,
  2177. cdp_config_param_type val)
  2178. {
  2179. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2180. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2181. switch (param) {
  2182. case CDP_TX_ENCAP_TYPE:
  2183. case CDP_UPDATE_DSCP_TO_TID_MAP:
  2184. case CDP_UPDATE_TDLS_FLAGS:
  2185. dp_tx_update_bank_profile(be_soc, be_vdev);
  2186. break;
  2187. case CDP_ENABLE_CIPHER:
  2188. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  2189. dp_tx_update_bank_profile(be_soc, be_vdev);
  2190. break;
  2191. case CDP_SET_MCAST_VDEV:
  2192. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  2193. break;
  2194. case CDP_RESET_MLO_MCAST_VDEV:
  2195. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  2196. break;
  2197. default:
  2198. dp_warn("invalid param %d", param);
  2199. break;
  2200. }
  2201. return QDF_STATUS_SUCCESS;
  2202. }
  2203. #ifdef WLAN_FEATURE_11BE_MLO
  2204. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  2205. static inline void
  2206. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2207. {
  2208. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  2209. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  2210. /*
  2211. * Double the peers since we use ML indication bit
  2212. * alongwith peer_id to find peers.
  2213. */
  2214. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  2215. }
  2216. #else
  2217. static inline void
  2218. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2219. {
  2220. soc->max_peer_id =
  2221. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  2222. }
  2223. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  2224. #else
  2225. static inline void
  2226. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2227. {
  2228. soc->max_peer_id = soc->max_peers;
  2229. }
  2230. #endif /* WLAN_FEATURE_11BE_MLO */
  2231. static void dp_peer_map_detach_be(struct dp_soc *soc)
  2232. {
  2233. if (soc->host_ast_db_enable)
  2234. dp_peer_ast_hash_detach(soc);
  2235. }
  2236. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  2237. {
  2238. QDF_STATUS status;
  2239. if (soc->host_ast_db_enable) {
  2240. status = dp_peer_ast_hash_attach(soc);
  2241. if (QDF_IS_STATUS_ERROR(status))
  2242. return status;
  2243. }
  2244. dp_soc_max_peer_id_set(soc);
  2245. return QDF_STATUS_SUCCESS;
  2246. }
  2247. #ifdef WLAN_FEATURE_11BE_MLO
  2248. #ifdef WLAN_MCAST_MLO
  2249. static inline void
  2250. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2251. {
  2252. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  2253. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  2254. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  2255. }
  2256. #else /* WLAN_MCAST_MLO */
  2257. static inline void
  2258. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2259. {
  2260. }
  2261. #endif /* WLAN_MCAST_MLO */
  2262. #ifdef WLAN_MLO_MULTI_CHIP
  2263. static inline void
  2264. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2265. {
  2266. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  2267. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  2268. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  2269. }
  2270. #else
  2271. static inline void
  2272. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2273. {
  2274. }
  2275. #endif
  2276. static inline void
  2277. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2278. {
  2279. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  2280. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  2281. arch_ops->mlo_peer_find_hash_detach =
  2282. dp_mlo_peer_find_hash_detach_wrapper;
  2283. arch_ops->mlo_peer_find_hash_attach =
  2284. dp_mlo_peer_find_hash_attach_wrapper;
  2285. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  2286. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  2287. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  2288. arch_ops->get_hw_link_id = dp_get_hw_link_id_be;
  2289. }
  2290. #else /* WLAN_FEATURE_11BE_MLO */
  2291. static inline void
  2292. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2293. {
  2294. }
  2295. #endif /* WLAN_FEATURE_11BE_MLO */
  2296. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  2297. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  2298. #define DP_LMAC_PEER_ID_MSB_MLO 3
  2299. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2300. struct cdp_peer_setup_info *setup_info,
  2301. enum cdp_host_reo_dest_ring *reo_dest,
  2302. bool *hash_based,
  2303. uint8_t *lmac_peer_id_msb)
  2304. {
  2305. struct dp_soc *soc = vdev->pdev->soc;
  2306. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2307. if (!be_soc->mlo_enabled)
  2308. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  2309. hash_based);
  2310. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2311. *reo_dest = vdev->pdev->reo_dest;
  2312. /* Not a ML link peer use non-mlo */
  2313. if (!setup_info) {
  2314. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2315. return;
  2316. }
  2317. /* For STA ML VAP we do not have num links info at this point
  2318. * use MLO case always
  2319. */
  2320. if (vdev->opmode == wlan_op_mode_sta) {
  2321. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2322. return;
  2323. }
  2324. /* For AP ML VAP consider the peer as ML only it associates with
  2325. * multiple links
  2326. */
  2327. if (setup_info->num_links == 1) {
  2328. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2329. return;
  2330. }
  2331. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2332. }
  2333. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2334. uint32_t *remap0,
  2335. uint32_t *remap1,
  2336. uint32_t *remap2)
  2337. {
  2338. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2339. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2340. uint32_t reo_mlo_config =
  2341. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2342. if (!be_soc->mlo_enabled)
  2343. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2344. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2345. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2346. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2347. return true;
  2348. }
  2349. #else
  2350. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2351. struct cdp_peer_setup_info *setup_info,
  2352. enum cdp_host_reo_dest_ring *reo_dest,
  2353. bool *hash_based,
  2354. uint8_t *lmac_peer_id_msb)
  2355. {
  2356. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2357. }
  2358. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2359. uint32_t *remap0,
  2360. uint32_t *remap1,
  2361. uint32_t *remap2)
  2362. {
  2363. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2364. }
  2365. #endif
  2366. #ifdef CONFIG_MLO_SINGLE_DEV
  2367. static inline
  2368. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2369. {
  2370. arch_ops->dp_tx_mlo_mcast_send = dp_tx_mlo_mcast_send_be;
  2371. }
  2372. #else
  2373. static inline
  2374. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2375. {
  2376. }
  2377. #endif
  2378. #ifdef IPA_OFFLOAD
  2379. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2380. {
  2381. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2382. return be_soc->ipa_bank_id;
  2383. }
  2384. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  2385. static void dp_ipa_get_wdi_version_be(uint8_t *wdi_ver)
  2386. {
  2387. *wdi_ver = IPA_WDI_4;
  2388. }
  2389. #else
  2390. static inline void dp_ipa_get_wdi_version_be(uint8_t *wdi_ver)
  2391. {
  2392. }
  2393. #endif
  2394. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2395. {
  2396. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2397. arch_ops->ipa_get_wdi_ver = dp_ipa_get_wdi_version_be;
  2398. }
  2399. #else /* !IPA_OFFLOAD */
  2400. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2401. {
  2402. }
  2403. #endif /* IPA_OFFLOAD */
  2404. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2405. {
  2406. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2407. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2408. arch_ops->dp_rx_process = dp_rx_process_be;
  2409. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2410. arch_ops->tx_comp_get_params_from_hal_desc =
  2411. dp_tx_comp_get_params_from_hal_desc_be;
  2412. arch_ops->dp_tx_process_htt_completion =
  2413. dp_tx_process_htt_completion_be;
  2414. arch_ops->dp_tx_desc_pool_alloc = dp_tx_desc_pool_alloc_be;
  2415. arch_ops->dp_tx_desc_pool_free = dp_tx_desc_pool_free_be;
  2416. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2417. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2418. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2419. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2420. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2421. dp_wbm_get_rx_desc_from_hal_desc_be;
  2422. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2423. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2424. arch_ops->dp_rx_wbm_err_reap_desc = dp_rx_wbm_err_reap_desc_be;
  2425. arch_ops->dp_rx_null_q_desc_handle = dp_rx_null_q_desc_handle_be;
  2426. #endif
  2427. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2428. #ifdef WIFI_MONITOR_SUPPORT
  2429. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2430. #endif
  2431. arch_ops->dp_rx_desc_cookie_2_va =
  2432. dp_rx_desc_cookie_2_va_be;
  2433. arch_ops->dp_rx_intrabss_mcast_handler =
  2434. dp_rx_intrabss_mcast_handler_be;
  2435. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2436. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2437. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2438. arch_ops->txrx_soc_init = dp_soc_init_be;
  2439. arch_ops->txrx_soc_deinit = dp_soc_deinit_be_wrapper;
  2440. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2441. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2442. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2443. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2444. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2445. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2446. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2447. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2448. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2449. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2450. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2451. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2452. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2453. dp_rx_peer_metadata_peer_id_get_be;
  2454. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2455. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2456. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2457. dp_initialize_arch_ops_be_mlo(arch_ops);
  2458. #ifdef WLAN_MLO_MULTI_CHIP
  2459. arch_ops->dp_get_soc_by_chip_id = dp_get_soc_by_chip_id_be;
  2460. #endif
  2461. arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be;
  2462. arch_ops->dp_peer_rx_reorder_queue_setup =
  2463. dp_peer_rx_reorder_queue_setup_be;
  2464. arch_ops->dp_rx_peer_set_link_id = dp_rx_set_link_id_be;
  2465. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2466. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2467. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2468. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2469. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2470. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2471. #endif
  2472. #ifdef WLAN_SUPPORT_PPEDS
  2473. arch_ops->ppeds_handle_attached = dp_ppeds_handle_attached;
  2474. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2475. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2476. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2477. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2478. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2479. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2480. arch_ops->dp_ppeds_clear_stats = dp_ppeds_clear_stats;
  2481. arch_ops->dp_txrx_ppeds_rings_stats = dp_ppeds_rings_stats;
  2482. arch_ops->dp_txrx_ppeds_clear_rings_stats = dp_ppeds_clear_rings_stats;
  2483. arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
  2484. dp_tx_ppeds_cfg_astidx_cache_mapping;
  2485. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2486. arch_ops->txrx_soc_ppeds_interrupt_stop = dp_ppeds_interrupt_stop_be;
  2487. arch_ops->txrx_soc_ppeds_interrupt_start = dp_ppeds_interrupt_start_be;
  2488. arch_ops->txrx_soc_ppeds_service_status_update =
  2489. dp_ppeds_service_status_update_be;
  2490. arch_ops->txrx_soc_ppeds_enabled_check = dp_ppeds_is_enabled_on_soc;
  2491. arch_ops->txrx_soc_ppeds_txdesc_pool_reset =
  2492. dp_ppeds_tx_desc_pool_reset;
  2493. #endif
  2494. #endif
  2495. dp_init_near_full_arch_ops_be(arch_ops);
  2496. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2497. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2498. arch_ops->dp_set_rx_fst = dp_set_rx_fst_be;
  2499. arch_ops->dp_get_rx_fst = dp_get_rx_fst_be;
  2500. arch_ops->dp_rx_fst_deref = dp_rx_fst_release_ref_be;
  2501. arch_ops->dp_rx_fst_ref = dp_rx_fst_get_ref_be;
  2502. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2503. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2504. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2505. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2506. arch_ops->txrx_srng_init = dp_srng_init_be;
  2507. arch_ops->dp_get_vdev_stats_for_unmap_peer =
  2508. dp_get_vdev_stats_for_unmap_peer_be;
  2509. #ifdef WLAN_MLO_MULTI_CHIP
  2510. arch_ops->dp_get_interface_stats = dp_get_interface_stats_be;
  2511. #endif
  2512. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  2513. arch_ops->dp_update_ring_hptp = dp_update_ring_hptp;
  2514. #endif
  2515. arch_ops->dp_flush_tx_ring = dp_flush_tcl_ring;
  2516. dp_initialize_arch_ops_be_ipa(arch_ops);
  2517. dp_initialize_arch_ops_be_single_dev(arch_ops);
  2518. dp_initialize_arch_ops_be_fisa(arch_ops);
  2519. }
  2520. #ifdef QCA_SUPPORT_PRIMARY_LINK_MIGRATE
  2521. static void
  2522. dp_primary_link_migration(struct dp_soc *soc, void *cb_ctxt,
  2523. union hal_reo_status *reo_status)
  2524. {
  2525. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2526. struct dp_mlo_ctxt *dp_mlo = be_soc->ml_ctxt;
  2527. struct dp_soc *pr_soc = NULL;
  2528. struct dp_peer_info *pr_peer_info = (struct dp_peer_info *)cb_ctxt;
  2529. struct dp_peer *new_primary_peer = NULL;
  2530. struct dp_peer *mld_peer = NULL;
  2531. uint8_t primary_vdev_id;
  2532. struct cdp_txrx_peer_params_update params = {0};
  2533. uint8_t tid;
  2534. uint8_t is_wds = 0;
  2535. uint16_t hw_peer_id;
  2536. uint16_t ast_hash;
  2537. pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, pr_peer_info->chip_id);
  2538. if (!pr_soc) {
  2539. dp_htt_err("Invalid soc");
  2540. qdf_mem_free(pr_peer_info);
  2541. return;
  2542. }
  2543. new_primary_peer = pr_soc->peer_id_to_obj_map[
  2544. pr_peer_info->primary_peer_id];
  2545. if (!new_primary_peer) {
  2546. dp_htt_err("New primary peer is NULL");
  2547. qdf_mem_free(pr_peer_info);
  2548. return;
  2549. }
  2550. mld_peer = DP_GET_MLD_PEER_FROM_PEER(new_primary_peer);
  2551. if (!mld_peer) {
  2552. dp_htt_err("MLD peer is NULL");
  2553. qdf_mem_free(pr_peer_info);
  2554. return;
  2555. }
  2556. new_primary_peer->primary_link = 1;
  2557. hw_peer_id = pr_peer_info->hw_peer_id;
  2558. ast_hash = pr_peer_info->ast_hash;
  2559. /* Add ast enteries for new primary peer */
  2560. if (pr_soc->ast_offload_support && pr_soc->host_ast_db_enable) {
  2561. dp_peer_host_add_map_ast(pr_soc, mld_peer->peer_id, mld_peer->mac_addr.raw,
  2562. hw_peer_id, new_primary_peer->vdev->vdev_id,
  2563. ast_hash, is_wds);
  2564. }
  2565. /*
  2566. * Check if reo_qref_table_en is set and if
  2567. * rx_tid qdesc for tid 0 is already setup and perform
  2568. * qref write to LUT for Tid 0 and 16.
  2569. *
  2570. */
  2571. if (hal_reo_shared_qaddr_is_enable(pr_soc->hal_soc) &&
  2572. mld_peer->rx_tid[0].hw_qdesc_vaddr_unaligned) {
  2573. for (tid = 0; tid < DP_MAX_TIDS; tid++)
  2574. hal_reo_shared_qaddr_write(pr_soc->hal_soc,
  2575. mld_peer->peer_id,
  2576. tid,
  2577. mld_peer->rx_tid[tid].hw_qdesc_paddr);
  2578. }
  2579. if (pr_soc && pr_soc->cdp_soc.ol_ops->update_primary_link)
  2580. pr_soc->cdp_soc.ol_ops->update_primary_link(pr_soc->ctrl_psoc,
  2581. new_primary_peer->mac_addr.raw);
  2582. primary_vdev_id = new_primary_peer->vdev->vdev_id;
  2583. dp_vdev_unref_delete(soc, mld_peer->vdev, DP_MOD_ID_CHILD);
  2584. mld_peer->vdev = dp_vdev_get_ref_by_id(pr_soc, primary_vdev_id,
  2585. DP_MOD_ID_CHILD);
  2586. mld_peer->txrx_peer->vdev = mld_peer->vdev;
  2587. params.osif_vdev = (void *)new_primary_peer->vdev->osif_vdev;
  2588. params.peer_mac = mld_peer->mac_addr.raw;
  2589. params.chip_id = pr_peer_info->chip_id;
  2590. params.pdev_id = new_primary_peer->vdev->pdev->pdev_id;
  2591. if (new_primary_peer->vdev->opmode == wlan_op_mode_sta) {
  2592. dp_wdi_event_handler(
  2593. WDI_EVENT_STA_PRIMARY_UMAC_UPDATE,
  2594. pr_soc, (void *)&params,
  2595. new_primary_peer->peer_id,
  2596. WDI_NO_VAL, params.pdev_id);
  2597. } else {
  2598. dp_wdi_event_handler(
  2599. WDI_EVENT_PEER_PRIMARY_UMAC_UPDATE,
  2600. pr_soc, (void *)&params,
  2601. new_primary_peer->peer_id,
  2602. WDI_NO_VAL, params.pdev_id);
  2603. }
  2604. qdf_mem_free(pr_peer_info);
  2605. }
  2606. #ifdef WLAN_SUPPORT_PPEDS
  2607. static QDF_STATUS dp_get_ppe_info_for_vap(struct dp_soc *pr_soc,
  2608. struct dp_peer *pr_peer,
  2609. uint16_t *src_info)
  2610. {
  2611. struct dp_soc_be *be_soc_mld = NULL;
  2612. struct cdp_ds_vp_params vp_params = {0};
  2613. struct dp_ppe_vp_profile *ppe_vp_profile;
  2614. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  2615. struct cdp_soc_t *cdp_soc = &pr_soc->cdp_soc;
  2616. /*
  2617. * Extract the VP profile from the VAP
  2618. */
  2619. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  2620. dp_err("%pK: Register get ppeds profile info first", cdp_soc);
  2621. return QDF_STATUS_E_NULL_VALUE;
  2622. }
  2623. /*
  2624. * Check if PPE DS routing is enabled on the associated vap.
  2625. */
  2626. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(
  2627. pr_soc->ctrl_psoc,
  2628. pr_peer->vdev->vdev_id,
  2629. &vp_params);
  2630. if (QDF_IS_STATUS_ERROR(qdf_status)) {
  2631. dp_err("Could not find ppeds profile info");
  2632. return QDF_STATUS_E_NULL_VALUE;
  2633. }
  2634. /* Check if PPE DS routing is enabled on
  2635. * the associated vap.
  2636. */
  2637. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  2638. return qdf_status;
  2639. be_soc_mld = dp_get_be_soc_from_dp_soc(pr_soc);
  2640. ppe_vp_profile = &be_soc_mld->ppe_vp_profile[
  2641. vp_params.ppe_vp_profile_idx];
  2642. *src_info = ppe_vp_profile->vp_num;
  2643. return qdf_status;
  2644. }
  2645. #else
  2646. static QDF_STATUS dp_get_ppe_info_for_vap(struct dp_soc *pr_soc,
  2647. struct dp_peer *pr_peer,
  2648. uint16_t *src_info)
  2649. {
  2650. return QDF_STATUS_E_NOSUPPORT;
  2651. }
  2652. #endif
  2653. QDF_STATUS dp_htt_reo_migration(struct dp_soc *soc, uint16_t peer_id,
  2654. uint16_t ml_peer_id, uint16_t vdev_id,
  2655. uint8_t pdev_id, uint8_t chip_id)
  2656. {
  2657. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2658. struct dp_mlo_ctxt *dp_mlo = be_soc->ml_ctxt;
  2659. uint16_t mld_peer_id = dp_gen_ml_peer_id(soc, ml_peer_id);
  2660. struct dp_soc *pr_soc = NULL;
  2661. struct dp_soc *current_pr_soc = NULL;
  2662. struct hal_reo_cmd_params params;
  2663. struct dp_rx_tid *rx_tid;
  2664. struct dp_peer *pr_peer = NULL;
  2665. struct dp_peer *mld_peer = NULL;
  2666. struct dp_soc *mld_soc = NULL;
  2667. struct dp_peer *current_pr_peer = NULL;
  2668. struct dp_peer_info *peer_info;
  2669. struct dp_vdev_be *be_vdev;
  2670. uint16_t src_info = 0;
  2671. QDF_STATUS status;
  2672. struct dp_ast_entry *ast_entry;
  2673. uint16_t hw_peer_id;
  2674. uint16_t ast_hash;
  2675. if (!dp_mlo) {
  2676. dp_htt_err("Invalid dp_mlo ctxt");
  2677. return QDF_STATUS_E_FAILURE;
  2678. }
  2679. pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, chip_id);
  2680. if (!pr_soc) {
  2681. dp_htt_err("Invalid soc");
  2682. return QDF_STATUS_E_FAILURE;
  2683. }
  2684. pr_peer = pr_soc->peer_id_to_obj_map[peer_id];
  2685. if (!pr_peer || !(IS_MLO_DP_LINK_PEER(pr_peer))) {
  2686. dp_htt_err("Invalid peer");
  2687. return QDF_STATUS_E_FAILURE;
  2688. }
  2689. mld_peer = DP_GET_MLD_PEER_FROM_PEER(pr_peer);
  2690. if (!mld_peer || (mld_peer->peer_id != mld_peer_id)) {
  2691. dp_htt_err("Invalid mld peer");
  2692. return QDF_STATUS_E_FAILURE;
  2693. }
  2694. be_vdev = dp_get_be_vdev_from_dp_vdev(pr_peer->vdev);
  2695. if (!be_vdev) {
  2696. dp_htt_err("Invalid be vdev");
  2697. return QDF_STATUS_E_FAILURE;
  2698. }
  2699. mld_soc = mld_peer->vdev->pdev->soc;
  2700. status = dp_get_ppe_info_for_vap(pr_soc, pr_peer, &src_info);
  2701. if (status == QDF_STATUS_E_NULL_VALUE) {
  2702. dp_htt_err("Invalid ppe info for the vdev");
  2703. return QDF_STATUS_E_FAILURE;
  2704. }
  2705. current_pr_peer = dp_get_primary_link_peer_by_id(
  2706. pr_soc,
  2707. mld_peer->peer_id,
  2708. DP_MOD_ID_HTT);
  2709. /* Making existing primary peer as non primary */
  2710. if (current_pr_peer) {
  2711. current_pr_peer->primary_link = 0;
  2712. dp_peer_unref_delete(current_pr_peer, DP_MOD_ID_HTT);
  2713. }
  2714. current_pr_soc = mld_peer->vdev->pdev->soc;
  2715. dp_peer_rx_reo_shared_qaddr_delete(current_pr_soc, mld_peer);
  2716. /* delete ast entry for current primary peer */
  2717. qdf_spin_lock_bh(&current_pr_soc->ast_lock);
  2718. ast_entry = dp_peer_ast_hash_find_soc(current_pr_soc, mld_peer->mac_addr.raw);
  2719. if (!ast_entry) {
  2720. dp_htt_err("Invalid ast entry");
  2721. qdf_spin_unlock_bh(&current_pr_soc->ast_lock);
  2722. return QDF_STATUS_E_FAILURE;
  2723. }
  2724. hw_peer_id = ast_entry->ast_idx;
  2725. ast_hash = ast_entry->ast_hash_value;
  2726. dp_peer_unlink_ast_entry(current_pr_soc, ast_entry, mld_peer);
  2727. if (ast_entry->is_mapped)
  2728. current_pr_soc->ast_table[ast_entry->ast_idx] = NULL;
  2729. dp_peer_free_ast_entry(current_pr_soc, ast_entry);
  2730. mld_peer->self_ast_entry = NULL;
  2731. qdf_spin_unlock_bh(&current_pr_soc->ast_lock);
  2732. peer_info = qdf_mem_malloc(sizeof(struct dp_peer_info));
  2733. if (!peer_info) {
  2734. dp_htt_err("Malloc failed");
  2735. return QDF_STATUS_E_FAILURE;
  2736. }
  2737. peer_info->primary_peer_id = peer_id;
  2738. peer_info->chip_id = chip_id;
  2739. peer_info->hw_peer_id = hw_peer_id;
  2740. peer_info->ast_hash = ast_hash;
  2741. qdf_mem_zero(&params, sizeof(params));
  2742. rx_tid = &mld_peer->rx_tid[0];
  2743. params.std.need_status = 1;
  2744. params.std.addr_lo = rx_tid->hw_qdesc_paddr & 0xffffffff;
  2745. params.std.addr_hi = (uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
  2746. params.u.fl_cache_params.flush_no_inval = 0;
  2747. params.u.fl_cache_params.flush_entire_cache = 1;
  2748. status = dp_reo_send_cmd(current_pr_soc, CMD_FLUSH_CACHE, &params,
  2749. dp_primary_link_migration,
  2750. (void *)peer_info);
  2751. if (status != QDF_STATUS_SUCCESS) {
  2752. dp_htt_err("Reo flush failed");
  2753. qdf_mem_free(peer_info);
  2754. dp_h2t_ptqm_migration_msg_send(pr_soc, vdev_id, pdev_id,
  2755. chip_id, peer_id, ml_peer_id,
  2756. src_info, QDF_STATUS_E_FAILURE);
  2757. }
  2758. qdf_mem_zero(&params, sizeof(params));
  2759. params.std.need_status = 0;
  2760. params.std.addr_lo = rx_tid->hw_qdesc_paddr & 0xffffffff;
  2761. params.std.addr_hi = (uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
  2762. params.u.unblk_cache_params.type = UNBLOCK_CACHE;
  2763. dp_reo_send_cmd(current_pr_soc, CMD_UNBLOCK_CACHE, &params, NULL, NULL);
  2764. dp_h2t_ptqm_migration_msg_send(pr_soc, vdev_id, pdev_id,
  2765. chip_id, peer_id, ml_peer_id,
  2766. src_info, QDF_STATUS_SUCCESS);
  2767. return QDF_STATUS_SUCCESS;
  2768. }
  2769. #endif