hal_api_mon.h 15 KB

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  1. /*
  2. * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #include <target_type.h>
  23. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  24. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  25. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  26. #define HAL_RX_GET(_ptr, block, field) \
  27. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  28. HAL_RX_MASk(block, field)) >> \
  29. HAL_RX_LSB(block, field))
  30. #define HAL_RX_PHY_DATA_RADAR 0x01
  31. #define HAL_SU_MU_CODING_LDPC 0x01
  32. #define HAL_RX_FCS_LEN (4)
  33. #define KEY_EXTIV 0x20
  34. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  35. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  36. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  37. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  38. #define HAL_RX_USER_TLV32_LEN_LSB 10
  39. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  40. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  41. #define HAL_RX_USER_TLV32_USERID_LSB 26
  42. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  43. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  44. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  45. #define HAL_RX_TLV32_HDR_SIZE 4
  46. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  47. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  48. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  49. HAL_RX_USER_TLV32_TYPE_LSB)
  50. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  51. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  52. HAL_RX_USER_TLV32_LEN_MASK) >> \
  53. HAL_RX_USER_TLV32_LEN_LSB)
  54. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  55. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  56. HAL_RX_USER_TLV32_USERID_MASK) >> \
  57. HAL_RX_USER_TLV32_USERID_LSB)
  58. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  59. #define HAL_TLV_STATUS_PPDU_DONE 1
  60. #define HAL_TLV_STATUS_BUF_DONE 2
  61. #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
  62. #define HAL_MAX_UL_MU_USERS 8
  63. #define HAL_RX_PKT_TYPE_11A 0
  64. #define HAL_RX_PKT_TYPE_11B 1
  65. #define HAL_RX_PKT_TYPE_11N 2
  66. #define HAL_RX_PKT_TYPE_11AC 3
  67. #define HAL_RX_PKT_TYPE_11AX 4
  68. #define HAL_RX_RECEPTION_TYPE_SU 0
  69. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  70. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  71. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  72. /* Multiply rate by 2 to avoid float point
  73. * and get rate in units of 500kbps
  74. */
  75. #define HAL_11B_RATE_0MCS 11*2
  76. #define HAL_11B_RATE_1MCS 5.5*2
  77. #define HAL_11B_RATE_2MCS 2*2
  78. #define HAL_11B_RATE_3MCS 1*2
  79. #define HAL_11B_RATE_4MCS 11*2
  80. #define HAL_11B_RATE_5MCS 5.5*2
  81. #define HAL_11B_RATE_6MCS 2*2
  82. #define HAL_11A_RATE_0MCS 48*2
  83. #define HAL_11A_RATE_1MCS 24*2
  84. #define HAL_11A_RATE_2MCS 12*2
  85. #define HAL_11A_RATE_3MCS 6*2
  86. #define HAL_11A_RATE_4MCS 54*2
  87. #define HAL_11A_RATE_5MCS 36*2
  88. #define HAL_11A_RATE_6MCS 18*2
  89. #define HAL_11A_RATE_7MCS 9*2
  90. #define HAL_LEGACY_MCS0 0
  91. #define HAL_LEGACY_MCS1 1
  92. #define HAL_LEGACY_MCS2 2
  93. #define HAL_LEGACY_MCS3 3
  94. #define HAL_LEGACY_MCS4 4
  95. #define HAL_LEGACY_MCS5 5
  96. #define HAL_LEGACY_MCS6 6
  97. #define HAL_LEGACY_MCS7 7
  98. #define HE_GI_0_8 0
  99. #define HE_GI_0_4 1
  100. #define HE_GI_1_6 2
  101. #define HE_GI_3_2 3
  102. #define HT_SGI_PRESENT 0x80
  103. #define HE_LTF_1_X 0
  104. #define HE_LTF_2_X 1
  105. #define HE_LTF_4_X 2
  106. #define VHT_SIG_SU_NSS_MASK 0x7
  107. #define HAL_TID_INVALID 31
  108. #define HAL_AST_IDX_INVALID 0xFFFF
  109. #ifdef GET_MSDU_AGGREGATION
  110. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  111. {\
  112. struct rx_msdu_end *rx_msdu_end;\
  113. bool first_msdu, last_msdu; \
  114. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  115. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  116. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  117. if (first_msdu && last_msdu)\
  118. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  119. else\
  120. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  121. } \
  122. #else
  123. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  124. #endif
  125. #define HAL_MAC_ADDR_LEN 6
  126. enum {
  127. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  128. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  129. HAL_HW_RX_DECAP_FORMAT_ETH2,
  130. HAL_HW_RX_DECAP_FORMAT_8023,
  131. };
  132. enum {
  133. DP_PPDU_STATUS_START,
  134. DP_PPDU_STATUS_DONE,
  135. };
  136. static inline
  137. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  138. {
  139. /* return the HW_RX_DESC size */
  140. return sizeof(struct rx_pkt_tlvs);
  141. }
  142. static inline
  143. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  144. {
  145. return data;
  146. }
  147. static inline
  148. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  149. {
  150. struct rx_attention *rx_attn;
  151. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  152. rx_attn = &rx_desc->attn_tlv.rx_attn;
  153. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  154. }
  155. static inline
  156. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  157. {
  158. struct rx_attention *rx_attn;
  159. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  160. rx_attn = &rx_desc->attn_tlv.rx_attn;
  161. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  162. }
  163. static inline
  164. uint32_t
  165. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  166. struct rx_msdu_start *rx_msdu_start;
  167. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  168. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  169. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  170. }
  171. static inline
  172. uint8_t *
  173. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  174. uint8_t *rx_pkt_hdr;
  175. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  176. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  177. return rx_pkt_hdr;
  178. }
  179. /*
  180. * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU
  181. * start TLV of Hardware TLV descriptor
  182. * @hw_desc_addr: Hardware desciptor address
  183. *
  184. * Return: bool: if TLV tag match
  185. */
  186. static inline
  187. bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr)
  188. {
  189. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  190. uint32_t tlv_tag;
  191. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(
  192. &rx_desc->mpdu_start_tlv);
  193. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  194. }
  195. static inline
  196. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  197. {
  198. struct rx_mpdu_info *rx_mpdu_info;
  199. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  200. rx_mpdu_info =
  201. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  202. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  203. }
  204. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  205. static inline
  206. uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
  207. {
  208. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  209. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  210. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  211. }
  212. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  213. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  214. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  215. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  216. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  217. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  218. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  219. (((struct reo_entrance_ring *)reo_ent_desc) \
  220. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  221. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  222. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  223. (((struct reo_entrance_ring *)reo_ent_desc) \
  224. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  225. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  226. (HAL_RX_BUF_COOKIE_GET(& \
  227. (((struct reo_entrance_ring *)reo_ent_desc) \
  228. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  229. /**
  230. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  231. * cookie from the REO entrance ring element
  232. *
  233. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  234. * the current descriptor
  235. * @ buf_info: structure to return the buffer information
  236. * @ msdu_cnt: pointer to msdu count in MPDU
  237. * Return: void
  238. */
  239. static inline
  240. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  241. struct hal_buf_info *buf_info,
  242. void **pp_buf_addr_info,
  243. uint32_t *msdu_cnt
  244. )
  245. {
  246. struct reo_entrance_ring *reo_ent_ring =
  247. (struct reo_entrance_ring *)rx_desc;
  248. struct buffer_addr_info *buf_addr_info;
  249. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  250. uint32_t loop_cnt;
  251. rx_mpdu_desc_info_details =
  252. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  253. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  254. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  255. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  256. buf_addr_info =
  257. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  258. buf_info->paddr =
  259. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  260. ((uint64_t)
  261. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  262. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  263. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  264. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d",
  265. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  266. (unsigned long long)buf_info->paddr, loop_cnt);
  267. *pp_buf_addr_info = (void *)buf_addr_info;
  268. }
  269. static inline
  270. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  271. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  272. {
  273. struct rx_msdu_link *msdu_link =
  274. (struct rx_msdu_link *)rx_msdu_link_desc;
  275. struct buffer_addr_info *buf_addr_info;
  276. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  277. buf_info->paddr =
  278. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  279. ((uint64_t)
  280. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  281. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  282. *pp_buf_addr_info = (void *)buf_addr_info;
  283. }
  284. /**
  285. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  286. *
  287. * @ soc : HAL version of the SOC pointer
  288. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  289. * @ buf_addr_info : void pointer to the buffer_addr_info
  290. *
  291. * Return: void
  292. */
  293. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  294. void *src_srng_desc, void *buf_addr_info)
  295. {
  296. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  297. (struct buffer_addr_info *)src_srng_desc;
  298. uint64_t paddr;
  299. struct buffer_addr_info *p_buffer_addr_info =
  300. (struct buffer_addr_info *)buf_addr_info;
  301. paddr =
  302. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  303. ((uint64_t)
  304. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  305. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  306. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx",
  307. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  308. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  309. /* Structure copy !!! */
  310. *wbm_srng_buffer_addr_info =
  311. *((struct buffer_addr_info *)buf_addr_info);
  312. }
  313. static inline
  314. uint32 hal_get_rx_msdu_link_desc_size(void)
  315. {
  316. return sizeof(struct rx_msdu_link);
  317. }
  318. enum {
  319. HAL_PKT_TYPE_OFDM = 0,
  320. HAL_PKT_TYPE_CCK,
  321. HAL_PKT_TYPE_HT,
  322. HAL_PKT_TYPE_VHT,
  323. HAL_PKT_TYPE_HE,
  324. };
  325. enum {
  326. HAL_SGI_0_8_US,
  327. HAL_SGI_0_4_US,
  328. HAL_SGI_1_6_US,
  329. HAL_SGI_3_2_US,
  330. };
  331. enum {
  332. HAL_FULL_RX_BW_20,
  333. HAL_FULL_RX_BW_40,
  334. HAL_FULL_RX_BW_80,
  335. HAL_FULL_RX_BW_160,
  336. };
  337. enum {
  338. HAL_RX_TYPE_SU,
  339. HAL_RX_TYPE_MU_MIMO,
  340. HAL_RX_TYPE_MU_OFDMA,
  341. HAL_RX_TYPE_MU_OFDMA_MIMO,
  342. };
  343. /**
  344. * enum
  345. * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
  346. * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
  347. */
  348. enum {
  349. HAL_RX_MON_PPDU_START = 0,
  350. HAL_RX_MON_PPDU_END,
  351. };
  352. struct hal_rx_ppdu_user_info {
  353. };
  354. struct hal_rx_ppdu_common_info {
  355. uint32_t ppdu_id;
  356. uint32_t ppdu_timestamp;
  357. uint32_t mpdu_cnt_fcs_ok;
  358. uint32_t mpdu_cnt_fcs_err;
  359. };
  360. struct hal_rx_msdu_payload_info {
  361. uint8_t *first_msdu_payload;
  362. uint32_t payload_len;
  363. };
  364. /**
  365. * struct hal_rx_nac_info - struct for neighbour info
  366. * @fc_valid: flag indicate if it has valid frame control information
  367. * @to_ds_flag: flag indicate to_ds bit
  368. * @mac_addr2_valid: flag indicate if mac_addr2 is valid
  369. * @mac_addr2: mac address2 in wh
  370. */
  371. struct hal_rx_nac_info {
  372. uint8_t fc_valid;
  373. uint8_t to_ds_flag;
  374. uint8_t mac_addr2_valid;
  375. uint8_t mac_addr2[HAL_MAC_ADDR_LEN];
  376. };
  377. struct hal_rx_ppdu_info {
  378. struct hal_rx_ppdu_common_info com_info;
  379. struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS];
  380. struct mon_rx_status rx_status;
  381. struct hal_rx_msdu_payload_info msdu_info;
  382. struct hal_rx_nac_info nac_info;
  383. /* status ring PPDU start and end state */
  384. uint32_t rx_state;
  385. };
  386. static inline uint32_t
  387. hal_get_rx_status_buf_size(void) {
  388. /* RX status buffer size is hard coded for now */
  389. return 2048;
  390. }
  391. static inline uint8_t*
  392. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  393. uint32_t tlv_len, tlv_tag;
  394. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  395. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  396. /* The actual length of PPDU_END is the combined length of many PHY
  397. * TLVs that follow. Skip the TLV header and
  398. * rx_rxpcu_classification_overview that follows the header to get to
  399. * next TLV.
  400. */
  401. if (tlv_tag == WIFIRX_PPDU_END_E)
  402. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  403. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  404. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  405. }
  406. /**
  407. * hal_rx_proc_phyrx_other_receive_info_tlv()
  408. * - process other receive info TLV
  409. * @rx_tlv_hdr: pointer to TLV header
  410. * @ppdu_info: pointer to ppdu_info
  411. *
  412. * Return: None
  413. */
  414. static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
  415. void *rx_tlv_hdr,
  416. struct hal_rx_ppdu_info
  417. *ppdu_info)
  418. {
  419. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr,
  420. (void *)ppdu_info);
  421. }
  422. /**
  423. * hal_rx_status_get_tlv_info() - process receive info TLV
  424. * @rx_tlv_hdr: pointer to TLV header
  425. * @ppdu_info: pointer to ppdu_info
  426. *
  427. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  428. */
  429. static inline uint32_t
  430. hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info,
  431. struct hal_soc *hal_soc)
  432. {
  433. return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr,
  434. ppdu_info, hal_soc);
  435. }
  436. static inline
  437. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  438. {
  439. return HAL_RX_TLV32_HDR_SIZE;
  440. }
  441. static inline QDF_STATUS
  442. hal_get_rx_status_done(uint8_t *rx_tlv)
  443. {
  444. uint32_t tlv_tag;
  445. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  446. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  447. return QDF_STATUS_SUCCESS;
  448. else
  449. return QDF_STATUS_E_EMPTY;
  450. }
  451. static inline QDF_STATUS
  452. hal_clear_rx_status_done(uint8_t *rx_tlv)
  453. {
  454. *(uint32_t *)rx_tlv = 0;
  455. return QDF_STATUS_SUCCESS;
  456. }
  457. #endif