msm_vidc_state.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _MSM_VIDC_STATE_H_
  7. #define _MSM_VIDC_STATE_H_
  8. #include "msm_vidc_internal.h"
  9. struct msm_vidc_core;
  10. #define FOREACH_CORE_STATE(CORE_STATE) { \
  11. CORE_STATE(CORE_DEINIT) \
  12. CORE_STATE(CORE_INIT_WAIT) \
  13. CORE_STATE(CORE_INIT) \
  14. CORE_STATE(CORE_ERROR) \
  15. }
  16. #define FOREACH_EVENT(EVENT) { \
  17. EVENT(TRY_FMT) \
  18. EVENT(S_FMT) \
  19. EVENT(REQBUFS) \
  20. EVENT(S_CTRL) \
  21. EVENT(STREAMON) \
  22. EVENT(STREAMOFF) \
  23. EVENT(CMD_START) \
  24. EVENT(CMD_STOP) \
  25. EVENT(BUF_QUEUE) \
  26. }
  27. enum msm_vidc_core_state FOREACH_CORE_STATE(GENERATE_MSM_VIDC_ENUM);
  28. enum msm_vidc_core_sub_state {
  29. CORE_SUBSTATE_NONE = 0x0,
  30. CORE_SUBSTATE_POWER_ENABLE = BIT(0),
  31. CORE_SUBSTATE_GDSC_HANDOFF = BIT(1),
  32. CORE_SUBSTATE_PM_SUSPEND = BIT(2),
  33. CORE_SUBSTATE_FW_PWR_CTRL = BIT(3),
  34. CORE_SUBSTATE_PAGE_FAULT = BIT(4),
  35. CORE_SUBSTATE_CPU_WATCHDOG = BIT(5),
  36. CORE_SUBSTATE_VIDEO_UNRESPONSIVE = BIT(6),
  37. CORE_SUBSTATE_MAX = BIT(7),
  38. };
  39. enum msm_vidc_core_event_type {
  40. CORE_EVENT_NONE = BIT(0),
  41. CORE_EVENT_UPDATE_SUB_STATE = BIT(1),
  42. };
  43. #define FOREACH_STATE(STATE) { \
  44. STATE(OPEN) \
  45. STATE(INPUT_STREAMING) \
  46. STATE(OUTPUT_STREAMING) \
  47. STATE(STREAMING) \
  48. STATE(CLOSE) \
  49. STATE(ERROR) \
  50. }
  51. enum msm_vidc_state FOREACH_STATE(GENERATE_MSM_VIDC_ENUM);
  52. #define MSM_VIDC_SUB_STATE_NONE 0
  53. #define MSM_VIDC_MAX_SUB_STATES 7
  54. /*
  55. * max value of inst->sub_state if all
  56. * the 6 valid bits are set i.e 111111==>63
  57. */
  58. #define MSM_VIDC_MAX_SUB_STATE_VALUE ((1 << MSM_VIDC_MAX_SUB_STATES) - 1)
  59. enum msm_vidc_sub_state {
  60. MSM_VIDC_DRAIN = BIT(0),
  61. MSM_VIDC_DRC = BIT(1),
  62. MSM_VIDC_DRAIN_LAST_BUFFER = BIT(2),
  63. MSM_VIDC_DRC_LAST_BUFFER = BIT(3),
  64. MSM_VIDC_INPUT_PAUSE = BIT(4),
  65. MSM_VIDC_OUTPUT_PAUSE = BIT(5),
  66. MSM_VIDC_FIRST_IPSC = BIT(6),
  67. };
  68. enum msm_vidc_event FOREACH_EVENT(GENERATE_MSM_VIDC_ENUM);
  69. /* core statemachine functions */
  70. enum msm_vidc_allow
  71. msm_vidc_allow_core_state_change(struct msm_vidc_core *core,
  72. enum msm_vidc_core_state req_state);
  73. int msm_vidc_update_core_state(struct msm_vidc_core *core,
  74. enum msm_vidc_core_state request_state,
  75. const char *func);
  76. bool core_in_valid_state(struct msm_vidc_core *core);
  77. bool is_core_state(struct msm_vidc_core *core, enum msm_vidc_core_state state);
  78. bool is_core_sub_state(struct msm_vidc_core *core,
  79. enum msm_vidc_core_sub_state sub_state);
  80. const char *core_state_name(enum msm_vidc_core_state state);
  81. const char *core_sub_state_name(enum msm_vidc_core_sub_state sub_state);
  82. /* inst statemachine functions */
  83. bool is_drc_pending(struct msm_vidc_inst *inst);
  84. bool is_drain_pending(struct msm_vidc_inst *inst);
  85. int msm_vidc_update_state(struct msm_vidc_inst *inst,
  86. enum msm_vidc_state request_state,
  87. const char *func);
  88. int msm_vidc_change_state(struct msm_vidc_inst *inst,
  89. enum msm_vidc_state request_state,
  90. const char *func);
  91. int msm_vidc_change_sub_state(struct msm_vidc_inst *inst,
  92. enum msm_vidc_sub_state clear_sub_state,
  93. enum msm_vidc_sub_state set_sub_state,
  94. const char *func);
  95. const char *state_name(enum msm_vidc_state state);
  96. const char *sub_state_name(enum msm_vidc_sub_state sub_state);
  97. bool is_state(struct msm_vidc_inst *inst, enum msm_vidc_state state);
  98. bool is_sub_state(struct msm_vidc_inst *inst,
  99. enum msm_vidc_sub_state sub_state);
  100. #endif // _MSM_VIDC_STATE_H_