dp_tx.c 108 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #include "dp_internal.h"
  34. #ifdef FEATURE_WDS
  35. #include "dp_txrx_wds.h"
  36. #endif
  37. #ifdef ATH_SUPPORT_IQUE
  38. #include "dp_txrx_me.h"
  39. #endif
  40. /* TODO Add support in TSO */
  41. #define DP_DESC_NUM_FRAG(x) 0
  42. /* disable TQM_BYPASS */
  43. #define TQM_BYPASS_WAR 0
  44. /* invalid peer id for reinject*/
  45. #define DP_INVALID_PEER 0XFFFE
  46. /*mapping between hal encrypt type and cdp_sec_type*/
  47. #define MAX_CDP_SEC_TYPE 12
  48. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  49. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  50. HAL_TX_ENCRYPT_TYPE_WEP_128,
  51. HAL_TX_ENCRYPT_TYPE_WEP_104,
  52. HAL_TX_ENCRYPT_TYPE_WEP_40,
  53. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  55. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  56. HAL_TX_ENCRYPT_TYPE_WAPI,
  57. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  58. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  60. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  61. #if defined(FEATURE_TSO)
  62. /**
  63. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  64. *
  65. * @soc - core txrx main context
  66. * @seg_desc - tso segment descriptor
  67. * @num_seg_desc - tso number segment descriptor
  68. */
  69. static void dp_tx_tso_unmap_segment(
  70. struct dp_soc *soc,
  71. struct qdf_tso_seg_elem_t *seg_desc,
  72. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  73. {
  74. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  75. if (qdf_unlikely(!seg_desc)) {
  76. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  77. __func__, __LINE__);
  78. qdf_assert(0);
  79. } else if (qdf_unlikely(!num_seg_desc)) {
  80. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  81. __func__, __LINE__);
  82. qdf_assert(0);
  83. } else {
  84. bool is_last_seg;
  85. /* no tso segment left to do dma unmap */
  86. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  87. return;
  88. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  89. true : false;
  90. qdf_nbuf_unmap_tso_segment(soc->osdev,
  91. seg_desc, is_last_seg);
  92. num_seg_desc->num_seg.tso_cmn_num_seg--;
  93. }
  94. }
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  97. * back to the freelist
  98. *
  99. * @soc - soc device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  119. /* Add the tso num segment into the free list */
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  121. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  122. tx_desc->tso_num_desc);
  123. tx_desc->tso_num_desc = NULL;
  124. }
  125. /* Add the tso segment into the free list*/
  126. dp_tx_tso_desc_free(soc,
  127. tx_desc->pool_id, tx_desc->tso_desc);
  128. tx_desc->tso_desc = NULL;
  129. }
  130. }
  131. #else
  132. static void dp_tx_tso_unmap_segment(
  133. struct dp_soc *soc,
  134. struct qdf_tso_seg_elem_t *seg_desc,
  135. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  136. {
  137. }
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. }
  142. #endif
  143. /**
  144. * dp_tx_desc_release() - Release Tx Descriptor
  145. * @tx_desc : Tx Descriptor
  146. * @desc_pool_id: Descriptor Pool ID
  147. *
  148. * Deallocate all resources attached to Tx descriptor and free the Tx
  149. * descriptor.
  150. *
  151. * Return:
  152. */
  153. static void
  154. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  155. {
  156. struct dp_pdev *pdev = tx_desc->pdev;
  157. struct dp_soc *soc;
  158. uint8_t comp_status = 0;
  159. qdf_assert(pdev);
  160. soc = pdev->soc;
  161. if (tx_desc->frm_type == dp_tx_frm_tso)
  162. dp_tx_tso_desc_release(soc, tx_desc);
  163. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  164. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  165. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  166. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  167. qdf_atomic_dec(&pdev->num_tx_outstanding);
  168. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  169. qdf_atomic_dec(&pdev->num_tx_exception);
  170. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  171. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  172. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  173. soc->hal_soc);
  174. else
  175. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  177. "Tx Completion Release desc %d status %d outstanding %d",
  178. tx_desc->id, comp_status,
  179. qdf_atomic_read(&pdev->num_tx_outstanding));
  180. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  181. return;
  182. }
  183. /**
  184. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  185. * @vdev: DP vdev Handle
  186. * @nbuf: skb
  187. * @msdu_info: msdu_info required to create HTT metadata
  188. *
  189. * Prepares and fills HTT metadata in the frame pre-header for special frames
  190. * that should be transmitted using varying transmit parameters.
  191. * There are 2 VDEV modes that currently needs this special metadata -
  192. * 1) Mesh Mode
  193. * 2) DSRC Mode
  194. *
  195. * Return: HTT metadata size
  196. *
  197. */
  198. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  199. struct dp_tx_msdu_info_s *msdu_info)
  200. {
  201. uint32_t *meta_data = msdu_info->meta_data;
  202. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  203. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  204. uint8_t htt_desc_size;
  205. /* Size rounded of multiple of 8 bytes */
  206. uint8_t htt_desc_size_aligned;
  207. uint8_t *hdr = NULL;
  208. /*
  209. * Metadata - HTT MSDU Extension header
  210. */
  211. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  212. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  213. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer) {
  214. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  215. htt_desc_size_aligned)) {
  216. DP_STATS_INC(vdev,
  217. tx_i.dropped.headroom_insufficient, 1);
  218. return 0;
  219. }
  220. /* Fill and add HTT metaheader */
  221. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  222. if (!hdr) {
  223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  224. "Error in filling HTT metadata");
  225. return 0;
  226. }
  227. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  228. } else if (vdev->opmode == wlan_op_mode_ocb) {
  229. /* Todo - Add support for DSRC */
  230. }
  231. return htt_desc_size_aligned;
  232. }
  233. /**
  234. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  235. * @tso_seg: TSO segment to process
  236. * @ext_desc: Pointer to MSDU extension descriptor
  237. *
  238. * Return: void
  239. */
  240. #if defined(FEATURE_TSO)
  241. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  242. void *ext_desc)
  243. {
  244. uint8_t num_frag;
  245. uint32_t tso_flags;
  246. /*
  247. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  248. * tcp_flag_mask
  249. *
  250. * Checksum enable flags are set in TCL descriptor and not in Extension
  251. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  252. */
  253. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  254. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  255. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  256. tso_seg->tso_flags.ip_len);
  257. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  258. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  259. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  260. uint32_t lo = 0;
  261. uint32_t hi = 0;
  262. qdf_dmaaddr_to_32s(
  263. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  264. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  265. tso_seg->tso_frags[num_frag].length);
  266. }
  267. return;
  268. }
  269. #else
  270. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  271. void *ext_desc)
  272. {
  273. return;
  274. }
  275. #endif
  276. #if defined(FEATURE_TSO)
  277. /**
  278. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  279. * allocated and free them
  280. *
  281. * @soc: soc handle
  282. * @free_seg: list of tso segments
  283. * @msdu_info: msdu descriptor
  284. *
  285. * Return - void
  286. */
  287. static void dp_tx_free_tso_seg_list(
  288. struct dp_soc *soc,
  289. struct qdf_tso_seg_elem_t *free_seg,
  290. struct dp_tx_msdu_info_s *msdu_info)
  291. {
  292. struct qdf_tso_seg_elem_t *next_seg;
  293. while (free_seg) {
  294. next_seg = free_seg->next;
  295. dp_tx_tso_desc_free(soc,
  296. msdu_info->tx_queue.desc_pool_id,
  297. free_seg);
  298. free_seg = next_seg;
  299. }
  300. }
  301. /**
  302. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  303. * allocated and free them
  304. *
  305. * @soc: soc handle
  306. * @free_num_seg: list of tso number segments
  307. * @msdu_info: msdu descriptor
  308. * Return - void
  309. */
  310. static void dp_tx_free_tso_num_seg_list(
  311. struct dp_soc *soc,
  312. struct qdf_tso_num_seg_elem_t *free_num_seg,
  313. struct dp_tx_msdu_info_s *msdu_info)
  314. {
  315. struct qdf_tso_num_seg_elem_t *next_num_seg;
  316. while (free_num_seg) {
  317. next_num_seg = free_num_seg->next;
  318. dp_tso_num_seg_free(soc,
  319. msdu_info->tx_queue.desc_pool_id,
  320. free_num_seg);
  321. free_num_seg = next_num_seg;
  322. }
  323. }
  324. /**
  325. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  326. * do dma unmap for each segment
  327. *
  328. * @soc: soc handle
  329. * @free_seg: list of tso segments
  330. * @num_seg_desc: tso number segment descriptor
  331. *
  332. * Return - void
  333. */
  334. static void dp_tx_unmap_tso_seg_list(
  335. struct dp_soc *soc,
  336. struct qdf_tso_seg_elem_t *free_seg,
  337. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  338. {
  339. struct qdf_tso_seg_elem_t *next_seg;
  340. if (qdf_unlikely(!num_seg_desc)) {
  341. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  342. return;
  343. }
  344. while (free_seg) {
  345. next_seg = free_seg->next;
  346. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  347. free_seg = next_seg;
  348. }
  349. }
  350. /**
  351. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  352. * free the tso segments descriptor and
  353. * tso num segments descriptor
  354. *
  355. * @soc: soc handle
  356. * @msdu_info: msdu descriptor
  357. * @tso_seg_unmap: flag to show if dma unmap is necessary
  358. *
  359. * Return - void
  360. */
  361. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  362. struct dp_tx_msdu_info_s *msdu_info,
  363. bool tso_seg_unmap)
  364. {
  365. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  366. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  367. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  368. tso_info->tso_num_seg_list;
  369. /* do dma unmap for each segment */
  370. if (tso_seg_unmap)
  371. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  372. /* free all tso number segment descriptor though looks only have 1 */
  373. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  374. /* free all tso segment descriptor */
  375. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  376. }
  377. /**
  378. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  379. * @vdev: virtual device handle
  380. * @msdu: network buffer
  381. * @msdu_info: meta data associated with the msdu
  382. *
  383. * Return: QDF_STATUS_SUCCESS success
  384. */
  385. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  386. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  387. {
  388. struct qdf_tso_seg_elem_t *tso_seg;
  389. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  390. struct dp_soc *soc = vdev->pdev->soc;
  391. struct qdf_tso_info_t *tso_info;
  392. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  393. tso_info = &msdu_info->u.tso_info;
  394. tso_info->curr_seg = NULL;
  395. tso_info->tso_seg_list = NULL;
  396. tso_info->num_segs = num_seg;
  397. msdu_info->frm_type = dp_tx_frm_tso;
  398. tso_info->tso_num_seg_list = NULL;
  399. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  400. while (num_seg) {
  401. tso_seg = dp_tx_tso_desc_alloc(
  402. soc, msdu_info->tx_queue.desc_pool_id);
  403. if (tso_seg) {
  404. tso_seg->next = tso_info->tso_seg_list;
  405. tso_info->tso_seg_list = tso_seg;
  406. num_seg--;
  407. } else {
  408. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  409. __func__);
  410. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  411. return QDF_STATUS_E_NOMEM;
  412. }
  413. }
  414. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  415. tso_num_seg = dp_tso_num_seg_alloc(soc,
  416. msdu_info->tx_queue.desc_pool_id);
  417. if (tso_num_seg) {
  418. tso_num_seg->next = tso_info->tso_num_seg_list;
  419. tso_info->tso_num_seg_list = tso_num_seg;
  420. } else {
  421. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  422. __func__);
  423. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  424. return QDF_STATUS_E_NOMEM;
  425. }
  426. msdu_info->num_seg =
  427. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  428. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  429. msdu_info->num_seg);
  430. if (!(msdu_info->num_seg)) {
  431. /*
  432. * Free allocated TSO seg desc and number seg desc,
  433. * do unmap for segments if dma map has done.
  434. */
  435. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  436. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  437. return QDF_STATUS_E_INVAL;
  438. }
  439. tso_info->curr_seg = tso_info->tso_seg_list;
  440. return QDF_STATUS_SUCCESS;
  441. }
  442. #else
  443. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  444. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  445. {
  446. return QDF_STATUS_E_NOMEM;
  447. }
  448. #endif
  449. /**
  450. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  451. * @vdev: DP Vdev handle
  452. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  453. * @desc_pool_id: Descriptor Pool ID
  454. *
  455. * Return:
  456. */
  457. static
  458. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  459. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  460. {
  461. uint8_t i;
  462. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  463. struct dp_tx_seg_info_s *seg_info;
  464. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  465. struct dp_soc *soc = vdev->pdev->soc;
  466. /* Allocate an extension descriptor */
  467. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  468. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  469. if (!msdu_ext_desc) {
  470. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  471. return NULL;
  472. }
  473. if (msdu_info->exception_fw &&
  474. qdf_unlikely(vdev->mesh_vdev)) {
  475. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  476. &msdu_info->meta_data[0],
  477. sizeof(struct htt_tx_msdu_desc_ext2_t));
  478. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  479. }
  480. switch (msdu_info->frm_type) {
  481. case dp_tx_frm_sg:
  482. case dp_tx_frm_me:
  483. case dp_tx_frm_raw:
  484. seg_info = msdu_info->u.sg_info.curr_seg;
  485. /* Update the buffer pointers in MSDU Extension Descriptor */
  486. for (i = 0; i < seg_info->frag_cnt; i++) {
  487. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  488. seg_info->frags[i].paddr_lo,
  489. seg_info->frags[i].paddr_hi,
  490. seg_info->frags[i].len);
  491. }
  492. break;
  493. case dp_tx_frm_tso:
  494. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  495. &cached_ext_desc[0]);
  496. break;
  497. default:
  498. break;
  499. }
  500. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  501. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  502. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  503. msdu_ext_desc->vaddr);
  504. return msdu_ext_desc;
  505. }
  506. /**
  507. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  508. *
  509. * @skb: skb to be traced
  510. * @msdu_id: msdu_id of the packet
  511. * @vdev_id: vdev_id of the packet
  512. *
  513. * Return: None
  514. */
  515. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  516. uint8_t vdev_id)
  517. {
  518. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  519. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  520. DPTRACE(qdf_dp_trace_ptr(skb,
  521. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  522. QDF_TRACE_DEFAULT_PDEV_ID,
  523. qdf_nbuf_data_addr(skb),
  524. sizeof(qdf_nbuf_data(skb)),
  525. msdu_id, vdev_id));
  526. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  527. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  528. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  529. msdu_id, QDF_TX));
  530. }
  531. #ifdef QCA_512M_CONFIG
  532. /**
  533. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  534. * tx descriptor configured value
  535. * @vdev: DP vdev handle
  536. *
  537. * Return: true if allocated tx descriptors reached max configured value, else
  538. * false.
  539. */
  540. static inline bool
  541. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  542. {
  543. struct dp_pdev *pdev = vdev->pdev;
  544. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  545. pdev->num_tx_allowed) {
  546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  547. "%s: queued packets are more than max tx, drop the frame",
  548. __func__);
  549. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  550. return true;
  551. }
  552. return false;
  553. }
  554. #else
  555. static inline bool
  556. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  557. {
  558. return false;
  559. }
  560. #endif
  561. /**
  562. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  563. * @vdev: DP vdev handle
  564. * @nbuf: skb
  565. * @desc_pool_id: Descriptor pool ID
  566. * @meta_data: Metadata to the fw
  567. * @tx_exc_metadata: Handle that holds exception path metadata
  568. * Allocate and prepare Tx descriptor with msdu information.
  569. *
  570. * Return: Pointer to Tx Descriptor on success,
  571. * NULL on failure
  572. */
  573. static
  574. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  575. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  576. struct dp_tx_msdu_info_s *msdu_info,
  577. struct cdp_tx_exception_metadata *tx_exc_metadata)
  578. {
  579. uint8_t align_pad;
  580. uint8_t is_exception = 0;
  581. uint8_t htt_hdr_size;
  582. qdf_ether_header_t *eh;
  583. struct dp_tx_desc_s *tx_desc;
  584. struct dp_pdev *pdev = vdev->pdev;
  585. struct dp_soc *soc = pdev->soc;
  586. if (dp_tx_pdev_pflow_control(vdev))
  587. return NULL;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (qdf_unlikely(!tx_desc)) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = dp_tx_frm_std;
  599. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  600. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  601. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  602. tx_desc->vdev = vdev;
  603. tx_desc->pdev = pdev;
  604. tx_desc->msdu_ext_desc = NULL;
  605. tx_desc->pkt_offset = 0;
  606. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  607. /*
  608. * For special modes (vdev_type == ocb or mesh), data frames should be
  609. * transmitted using varying transmit parameters (tx spec) which include
  610. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  611. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  612. * These frames are sent as exception packets to firmware.
  613. *
  614. * HW requirement is that metadata should always point to a
  615. * 8-byte aligned address. So we add alignment pad to start of buffer.
  616. * HTT Metadata should be ensured to be multiple of 8-bytes,
  617. * to get 8-byte aligned start address along with align_pad added
  618. *
  619. * |-----------------------------|
  620. * | |
  621. * |-----------------------------| <-----Buffer Pointer Address given
  622. * | | ^ in HW descriptor (aligned)
  623. * | HTT Metadata | |
  624. * | | |
  625. * | | | Packet Offset given in descriptor
  626. * | | |
  627. * |-----------------------------| |
  628. * | Alignment Pad | v
  629. * |-----------------------------| <----- Actual buffer start address
  630. * | SKB Data | (Unaligned)
  631. * | |
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * |-----------------------------|
  637. */
  638. if (qdf_unlikely((msdu_info->exception_fw)) ||
  639. (vdev->opmode == wlan_op_mode_ocb) ||
  640. (tx_exc_metadata &&
  641. tx_exc_metadata->is_tx_sniffer)) {
  642. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  643. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  644. DP_STATS_INC(vdev,
  645. tx_i.dropped.headroom_insufficient, 1);
  646. goto failure;
  647. }
  648. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  650. "qdf_nbuf_push_head failed");
  651. goto failure;
  652. }
  653. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  654. msdu_info);
  655. if (htt_hdr_size == 0)
  656. goto failure;
  657. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  658. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  659. is_exception = 1;
  660. }
  661. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  662. qdf_nbuf_map(soc->osdev, nbuf,
  663. QDF_DMA_TO_DEVICE))) {
  664. /* Handle failure */
  665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  666. "qdf_nbuf_map failed");
  667. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  668. goto failure;
  669. }
  670. if (qdf_unlikely(vdev->nawds_enabled)) {
  671. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  672. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  673. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  674. is_exception = 1;
  675. }
  676. }
  677. #if !TQM_BYPASS_WAR
  678. if (is_exception || tx_exc_metadata)
  679. #endif
  680. {
  681. /* Temporary WAR due to TQM VP issues */
  682. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  683. qdf_atomic_inc(&pdev->num_tx_exception);
  684. }
  685. return tx_desc;
  686. failure:
  687. dp_tx_desc_release(tx_desc, desc_pool_id);
  688. return NULL;
  689. }
  690. /**
  691. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  692. * @vdev: DP vdev handle
  693. * @nbuf: skb
  694. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  695. * @desc_pool_id : Descriptor Pool ID
  696. *
  697. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  698. * information. For frames wth fragments, allocate and prepare
  699. * an MSDU extension descriptor
  700. *
  701. * Return: Pointer to Tx Descriptor on success,
  702. * NULL on failure
  703. */
  704. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  705. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  706. uint8_t desc_pool_id)
  707. {
  708. struct dp_tx_desc_s *tx_desc;
  709. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  710. struct dp_pdev *pdev = vdev->pdev;
  711. struct dp_soc *soc = pdev->soc;
  712. if (dp_tx_pdev_pflow_control(vdev))
  713. return NULL;
  714. /* Allocate software Tx descriptor */
  715. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  716. if (!tx_desc) {
  717. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  718. return NULL;
  719. }
  720. /* Flow control/Congestion Control counters */
  721. qdf_atomic_inc(&pdev->num_tx_outstanding);
  722. /* Initialize the SW tx descriptor */
  723. tx_desc->nbuf = nbuf;
  724. tx_desc->frm_type = msdu_info->frm_type;
  725. tx_desc->tx_encap_type = vdev->tx_encap_type;
  726. tx_desc->vdev = vdev;
  727. tx_desc->pdev = pdev;
  728. tx_desc->pkt_offset = 0;
  729. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  730. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  731. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  732. /* Handle scattered frames - TSO/SG/ME */
  733. /* Allocate and prepare an extension descriptor for scattered frames */
  734. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  735. if (!msdu_ext_desc) {
  736. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  737. "%s Tx Extension Descriptor Alloc Fail",
  738. __func__);
  739. goto failure;
  740. }
  741. #if TQM_BYPASS_WAR
  742. /* Temporary WAR due to TQM VP issues */
  743. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  744. qdf_atomic_inc(&pdev->num_tx_exception);
  745. #endif
  746. if (qdf_unlikely(msdu_info->exception_fw))
  747. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  748. tx_desc->msdu_ext_desc = msdu_ext_desc;
  749. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  750. return tx_desc;
  751. failure:
  752. dp_tx_desc_release(tx_desc, desc_pool_id);
  753. return NULL;
  754. }
  755. /**
  756. * dp_tx_prepare_raw() - Prepare RAW packet TX
  757. * @vdev: DP vdev handle
  758. * @nbuf: buffer pointer
  759. * @seg_info: Pointer to Segment info Descriptor to be prepared
  760. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  761. * descriptor
  762. *
  763. * Return:
  764. */
  765. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  766. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  767. {
  768. qdf_nbuf_t curr_nbuf = NULL;
  769. uint16_t total_len = 0;
  770. qdf_dma_addr_t paddr;
  771. int32_t i;
  772. int32_t mapped_buf_num = 0;
  773. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  774. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  775. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  776. /* Continue only if frames are of DATA type */
  777. if (!DP_FRAME_IS_DATA(qos_wh)) {
  778. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  780. "Pkt. recd is of not data type");
  781. goto error;
  782. }
  783. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  784. if (vdev->raw_mode_war &&
  785. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  786. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  787. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  788. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  789. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  790. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  791. QDF_DMA_TO_DEVICE)) {
  792. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  793. "%s dma map error ", __func__);
  794. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  795. mapped_buf_num = i;
  796. goto error;
  797. }
  798. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  799. seg_info->frags[i].paddr_lo = paddr;
  800. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  801. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  802. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  803. total_len += qdf_nbuf_len(curr_nbuf);
  804. }
  805. seg_info->frag_cnt = i;
  806. seg_info->total_len = total_len;
  807. seg_info->next = NULL;
  808. sg_info->curr_seg = seg_info;
  809. msdu_info->frm_type = dp_tx_frm_raw;
  810. msdu_info->num_seg = 1;
  811. return nbuf;
  812. error:
  813. i = 0;
  814. while (nbuf) {
  815. curr_nbuf = nbuf;
  816. if (i < mapped_buf_num) {
  817. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  818. i++;
  819. }
  820. nbuf = qdf_nbuf_next(nbuf);
  821. qdf_nbuf_free(curr_nbuf);
  822. }
  823. return NULL;
  824. }
  825. /**
  826. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  827. * @soc: DP Soc Handle
  828. * @vdev: DP vdev handle
  829. * @tx_desc: Tx Descriptor Handle
  830. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  831. * @fw_metadata: Metadata to send to Target Firmware along with frame
  832. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  833. * @tx_exc_metadata: Handle that holds exception path meta data
  834. *
  835. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  836. * from software Tx descriptor
  837. *
  838. * Return:
  839. */
  840. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  841. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  842. uint16_t fw_metadata, uint8_t ring_id,
  843. struct cdp_tx_exception_metadata
  844. *tx_exc_metadata)
  845. {
  846. uint8_t type;
  847. uint16_t length;
  848. void *hal_tx_desc, *hal_tx_desc_cached;
  849. qdf_dma_addr_t dma_addr;
  850. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  851. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  852. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  853. tx_exc_metadata->sec_type : vdev->sec_type);
  854. /* Return Buffer Manager ID */
  855. uint8_t bm_id = ring_id;
  856. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  857. hal_tx_desc_cached = (void *) cached_desc;
  858. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  859. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  860. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  861. type = HAL_TX_BUF_TYPE_EXT_DESC;
  862. dma_addr = tx_desc->msdu_ext_desc->paddr;
  863. } else {
  864. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  865. type = HAL_TX_BUF_TYPE_BUFFER;
  866. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  867. }
  868. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  869. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  870. dma_addr, bm_id, tx_desc->id,
  871. type, soc->hal_soc);
  872. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  873. return QDF_STATUS_E_RESOURCES;
  874. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  875. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  876. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  877. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  878. vdev->pdev->lmac_id);
  879. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  880. vdev->search_type);
  881. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  882. vdev->bss_ast_hash);
  883. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  884. vdev->dscp_tid_map_id);
  885. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  886. sec_type_map[sec_type]);
  887. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  888. length, type, (uint64_t)dma_addr,
  889. tx_desc->pkt_offset, tx_desc->id);
  890. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  891. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  892. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  893. vdev->hal_desc_addr_search_flags);
  894. /* verify checksum offload configuration*/
  895. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  896. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  897. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  898. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  899. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  900. }
  901. if (tid != HTT_TX_EXT_TID_INVALID)
  902. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  903. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  904. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  905. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  906. /* Sync cached descriptor with HW */
  907. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  908. if (!hal_tx_desc) {
  909. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  910. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  911. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  912. return QDF_STATUS_E_RESOURCES;
  913. }
  914. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  915. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  916. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  917. return QDF_STATUS_SUCCESS;
  918. }
  919. /**
  920. * dp_cce_classify() - Classify the frame based on CCE rules
  921. * @vdev: DP vdev handle
  922. * @nbuf: skb
  923. *
  924. * Classify frames based on CCE rules
  925. * Return: bool( true if classified,
  926. * else false)
  927. */
  928. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  929. {
  930. qdf_ether_header_t *eh = NULL;
  931. uint16_t ether_type;
  932. qdf_llc_t *llcHdr;
  933. qdf_nbuf_t nbuf_clone = NULL;
  934. qdf_dot3_qosframe_t *qos_wh = NULL;
  935. /* for mesh packets don't do any classification */
  936. if (qdf_unlikely(vdev->mesh_vdev))
  937. return false;
  938. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  939. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  940. ether_type = eh->ether_type;
  941. llcHdr = (qdf_llc_t *)(nbuf->data +
  942. sizeof(qdf_ether_header_t));
  943. } else {
  944. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  945. /* For encrypted packets don't do any classification */
  946. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  947. return false;
  948. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  949. if (qdf_unlikely(
  950. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  951. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  952. ether_type = *(uint16_t *)(nbuf->data
  953. + QDF_IEEE80211_4ADDR_HDR_LEN
  954. + sizeof(qdf_llc_t)
  955. - sizeof(ether_type));
  956. llcHdr = (qdf_llc_t *)(nbuf->data +
  957. QDF_IEEE80211_4ADDR_HDR_LEN);
  958. } else {
  959. ether_type = *(uint16_t *)(nbuf->data
  960. + QDF_IEEE80211_3ADDR_HDR_LEN
  961. + sizeof(qdf_llc_t)
  962. - sizeof(ether_type));
  963. llcHdr = (qdf_llc_t *)(nbuf->data +
  964. QDF_IEEE80211_3ADDR_HDR_LEN);
  965. }
  966. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  967. && (ether_type ==
  968. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  969. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  970. return true;
  971. }
  972. }
  973. return false;
  974. }
  975. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  976. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  977. sizeof(*llcHdr));
  978. nbuf_clone = qdf_nbuf_clone(nbuf);
  979. if (qdf_unlikely(nbuf_clone)) {
  980. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  981. if (ether_type == htons(ETHERTYPE_VLAN)) {
  982. qdf_nbuf_pull_head(nbuf_clone,
  983. sizeof(qdf_net_vlanhdr_t));
  984. }
  985. }
  986. } else {
  987. if (ether_type == htons(ETHERTYPE_VLAN)) {
  988. nbuf_clone = qdf_nbuf_clone(nbuf);
  989. if (qdf_unlikely(nbuf_clone)) {
  990. qdf_nbuf_pull_head(nbuf_clone,
  991. sizeof(qdf_net_vlanhdr_t));
  992. }
  993. }
  994. }
  995. if (qdf_unlikely(nbuf_clone))
  996. nbuf = nbuf_clone;
  997. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  998. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  999. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1000. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1001. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1002. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1003. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1004. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1005. if (qdf_unlikely(nbuf_clone))
  1006. qdf_nbuf_free(nbuf_clone);
  1007. return true;
  1008. }
  1009. if (qdf_unlikely(nbuf_clone))
  1010. qdf_nbuf_free(nbuf_clone);
  1011. return false;
  1012. }
  1013. /**
  1014. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1015. * @vdev: DP vdev handle
  1016. * @nbuf: skb
  1017. *
  1018. * Extract the DSCP or PCP information from frame and map into TID value.
  1019. *
  1020. * Return: void
  1021. */
  1022. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1023. struct dp_tx_msdu_info_s *msdu_info)
  1024. {
  1025. uint8_t tos = 0, dscp_tid_override = 0;
  1026. uint8_t *hdr_ptr, *L3datap;
  1027. uint8_t is_mcast = 0;
  1028. qdf_ether_header_t *eh = NULL;
  1029. qdf_ethervlan_header_t *evh = NULL;
  1030. uint16_t ether_type;
  1031. qdf_llc_t *llcHdr;
  1032. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1033. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1034. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1035. eh = (qdf_ether_header_t *)nbuf->data;
  1036. hdr_ptr = eh->ether_dhost;
  1037. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1038. } else {
  1039. qdf_dot3_qosframe_t *qos_wh =
  1040. (qdf_dot3_qosframe_t *) nbuf->data;
  1041. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1042. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1043. return;
  1044. }
  1045. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1046. ether_type = eh->ether_type;
  1047. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1048. /*
  1049. * Check if packet is dot3 or eth2 type.
  1050. */
  1051. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1052. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1053. sizeof(*llcHdr));
  1054. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1055. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1056. sizeof(*llcHdr);
  1057. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1058. + sizeof(*llcHdr) +
  1059. sizeof(qdf_net_vlanhdr_t));
  1060. } else {
  1061. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1062. sizeof(*llcHdr);
  1063. }
  1064. } else {
  1065. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1066. evh = (qdf_ethervlan_header_t *) eh;
  1067. ether_type = evh->ether_type;
  1068. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1069. }
  1070. }
  1071. /*
  1072. * Find priority from IP TOS DSCP field
  1073. */
  1074. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1075. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1076. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1077. /* Only for unicast frames */
  1078. if (!is_mcast) {
  1079. /* send it on VO queue */
  1080. msdu_info->tid = DP_VO_TID;
  1081. }
  1082. } else {
  1083. /*
  1084. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1085. * from TOS byte.
  1086. */
  1087. tos = ip->ip_tos;
  1088. dscp_tid_override = 1;
  1089. }
  1090. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1091. /* TODO
  1092. * use flowlabel
  1093. *igmpmld cases to be handled in phase 2
  1094. */
  1095. unsigned long ver_pri_flowlabel;
  1096. unsigned long pri;
  1097. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1098. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1099. DP_IPV6_PRIORITY_SHIFT;
  1100. tos = pri;
  1101. dscp_tid_override = 1;
  1102. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1103. msdu_info->tid = DP_VO_TID;
  1104. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1105. /* Only for unicast frames */
  1106. if (!is_mcast) {
  1107. /* send ucast arp on VO queue */
  1108. msdu_info->tid = DP_VO_TID;
  1109. }
  1110. }
  1111. /*
  1112. * Assign all MCAST packets to BE
  1113. */
  1114. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1115. if (is_mcast) {
  1116. tos = 0;
  1117. dscp_tid_override = 1;
  1118. }
  1119. }
  1120. if (dscp_tid_override == 1) {
  1121. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1122. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1123. }
  1124. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1125. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1126. return;
  1127. }
  1128. /**
  1129. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1130. * @vdev: DP vdev handle
  1131. * @nbuf: skb
  1132. *
  1133. * Software based TID classification is required when more than 2 DSCP-TID
  1134. * mapping tables are needed.
  1135. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1136. *
  1137. * Return: void
  1138. */
  1139. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1140. struct dp_tx_msdu_info_s *msdu_info)
  1141. {
  1142. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1143. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1144. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1145. return;
  1146. /* for mesh packets don't do any classification */
  1147. if (qdf_unlikely(vdev->mesh_vdev))
  1148. return;
  1149. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1150. }
  1151. #ifdef FEATURE_WLAN_TDLS
  1152. /**
  1153. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1154. * @tx_desc: TX descriptor
  1155. *
  1156. * Return: None
  1157. */
  1158. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1159. {
  1160. if (tx_desc->vdev) {
  1161. if (tx_desc->vdev->is_tdls_frame) {
  1162. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1163. tx_desc->vdev->is_tdls_frame = false;
  1164. }
  1165. }
  1166. }
  1167. /**
  1168. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1169. * @tx_desc: TX descriptor
  1170. * @vdev: datapath vdev handle
  1171. *
  1172. * Return: None
  1173. */
  1174. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1175. struct dp_vdev *vdev)
  1176. {
  1177. struct hal_tx_completion_status ts = {0};
  1178. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1179. if (qdf_unlikely(!vdev)) {
  1180. dp_err("vdev is null!");
  1181. return;
  1182. }
  1183. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1184. if (vdev->tx_non_std_data_callback.func) {
  1185. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1186. vdev->tx_non_std_data_callback.func(
  1187. vdev->tx_non_std_data_callback.ctxt,
  1188. nbuf, ts.status);
  1189. return;
  1190. }
  1191. }
  1192. #else
  1193. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1194. {
  1195. }
  1196. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1197. struct dp_vdev *vdev)
  1198. {
  1199. }
  1200. #endif
  1201. /**
  1202. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1203. * @vdev: DP vdev handle
  1204. * @nbuf: skb
  1205. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1206. * @meta_data: Metadata to the fw
  1207. * @tx_q: Tx queue to be used for this Tx frame
  1208. * @peer_id: peer_id of the peer in case of NAWDS frames
  1209. * @tx_exc_metadata: Handle that holds exception path metadata
  1210. *
  1211. * Return: NULL on success,
  1212. * nbuf when it fails to send
  1213. */
  1214. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1215. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1216. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1217. {
  1218. struct dp_pdev *pdev = vdev->pdev;
  1219. struct dp_soc *soc = pdev->soc;
  1220. struct dp_tx_desc_s *tx_desc;
  1221. QDF_STATUS status;
  1222. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1223. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1224. uint16_t htt_tcl_metadata = 0;
  1225. uint8_t tid = msdu_info->tid;
  1226. struct cdp_tid_tx_stats *tid_stats = NULL;
  1227. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1228. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1229. msdu_info, tx_exc_metadata);
  1230. if (!tx_desc) {
  1231. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1232. vdev, tx_q->desc_pool_id);
  1233. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1234. tid_stats = &pdev->stats.tid_stats.
  1235. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1236. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1237. return nbuf;
  1238. }
  1239. if (qdf_unlikely(soc->cce_disable)) {
  1240. if (dp_cce_classify(vdev, nbuf) == true) {
  1241. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1242. tid = DP_VO_TID;
  1243. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1244. }
  1245. }
  1246. dp_tx_update_tdls_flags(tx_desc);
  1247. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1248. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1249. "%s %d : HAL RING Access Failed -- %pK",
  1250. __func__, __LINE__, hal_srng);
  1251. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1252. tid_stats = &pdev->stats.tid_stats.
  1253. tid_tx_stats[tx_q->ring_id][tid];
  1254. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1255. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1256. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1257. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1258. goto fail_return;
  1259. }
  1260. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1261. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1262. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1263. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1264. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1265. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1266. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1267. peer_id);
  1268. } else
  1269. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1270. if (msdu_info->exception_fw) {
  1271. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1272. }
  1273. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1274. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1275. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1276. if (status != QDF_STATUS_SUCCESS) {
  1277. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1278. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1279. __func__, tx_desc, tx_q->ring_id);
  1280. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1281. tid_stats = &pdev->stats.tid_stats.
  1282. tid_tx_stats[tx_q->ring_id][tid];
  1283. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1284. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1285. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1286. goto fail_return;
  1287. }
  1288. nbuf = NULL;
  1289. fail_return:
  1290. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1291. hal_srng_access_end(soc->hal_soc, hal_srng);
  1292. hif_pm_runtime_put(soc->hif_handle);
  1293. } else {
  1294. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1295. }
  1296. return nbuf;
  1297. }
  1298. /**
  1299. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1300. * @vdev: DP vdev handle
  1301. * @nbuf: skb
  1302. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1303. *
  1304. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1305. *
  1306. * Return: NULL on success,
  1307. * nbuf when it fails to send
  1308. */
  1309. #if QDF_LOCK_STATS
  1310. noinline
  1311. #else
  1312. #endif
  1313. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1314. struct dp_tx_msdu_info_s *msdu_info)
  1315. {
  1316. uint8_t i;
  1317. struct dp_pdev *pdev = vdev->pdev;
  1318. struct dp_soc *soc = pdev->soc;
  1319. struct dp_tx_desc_s *tx_desc;
  1320. bool is_cce_classified = false;
  1321. QDF_STATUS status;
  1322. uint16_t htt_tcl_metadata = 0;
  1323. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1324. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1325. struct cdp_tid_tx_stats *tid_stats = NULL;
  1326. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1327. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1328. "%s %d : HAL RING Access Failed -- %pK",
  1329. __func__, __LINE__, hal_srng);
  1330. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1331. tid_stats = &pdev->stats.tid_stats.
  1332. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1333. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1334. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1335. return nbuf;
  1336. }
  1337. if (qdf_unlikely(soc->cce_disable)) {
  1338. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1339. if (is_cce_classified) {
  1340. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1341. msdu_info->tid = DP_VO_TID;
  1342. }
  1343. }
  1344. if (msdu_info->frm_type == dp_tx_frm_me)
  1345. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1346. i = 0;
  1347. /* Print statement to track i and num_seg */
  1348. /*
  1349. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1350. * descriptors using information in msdu_info
  1351. */
  1352. while (i < msdu_info->num_seg) {
  1353. /*
  1354. * Setup Tx descriptor for an MSDU, and MSDU extension
  1355. * descriptor
  1356. */
  1357. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1358. tx_q->desc_pool_id);
  1359. if (!tx_desc) {
  1360. if (msdu_info->frm_type == dp_tx_frm_me) {
  1361. dp_tx_me_free_buf(pdev,
  1362. (void *)(msdu_info->u.sg_info
  1363. .curr_seg->frags[0].vaddr));
  1364. }
  1365. goto done;
  1366. }
  1367. if (msdu_info->frm_type == dp_tx_frm_me) {
  1368. tx_desc->me_buffer =
  1369. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1370. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1371. }
  1372. if (is_cce_classified)
  1373. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1374. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1375. if (msdu_info->exception_fw) {
  1376. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1377. }
  1378. /*
  1379. * Enqueue the Tx MSDU descriptor to HW for transmit
  1380. */
  1381. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1382. htt_tcl_metadata, tx_q->ring_id, NULL);
  1383. if (status != QDF_STATUS_SUCCESS) {
  1384. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1385. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1386. __func__, tx_desc, tx_q->ring_id);
  1387. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1388. tid_stats = &pdev->stats.tid_stats.
  1389. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1390. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1391. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1392. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1393. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1394. goto done;
  1395. }
  1396. /*
  1397. * TODO
  1398. * if tso_info structure can be modified to have curr_seg
  1399. * as first element, following 2 blocks of code (for TSO and SG)
  1400. * can be combined into 1
  1401. */
  1402. /*
  1403. * For frames with multiple segments (TSO, ME), jump to next
  1404. * segment.
  1405. */
  1406. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1407. if (msdu_info->u.tso_info.curr_seg->next) {
  1408. msdu_info->u.tso_info.curr_seg =
  1409. msdu_info->u.tso_info.curr_seg->next;
  1410. /*
  1411. * If this is a jumbo nbuf, then increment the number of
  1412. * nbuf users for each additional segment of the msdu.
  1413. * This will ensure that the skb is freed only after
  1414. * receiving tx completion for all segments of an nbuf
  1415. */
  1416. qdf_nbuf_inc_users(nbuf);
  1417. /* Check with MCL if this is needed */
  1418. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1419. }
  1420. }
  1421. /*
  1422. * For Multicast-Unicast converted packets,
  1423. * each converted frame (for a client) is represented as
  1424. * 1 segment
  1425. */
  1426. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1427. (msdu_info->frm_type == dp_tx_frm_me)) {
  1428. if (msdu_info->u.sg_info.curr_seg->next) {
  1429. msdu_info->u.sg_info.curr_seg =
  1430. msdu_info->u.sg_info.curr_seg->next;
  1431. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1432. }
  1433. }
  1434. i++;
  1435. }
  1436. nbuf = NULL;
  1437. done:
  1438. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1439. hal_srng_access_end(soc->hal_soc, hal_srng);
  1440. hif_pm_runtime_put(soc->hif_handle);
  1441. } else {
  1442. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1443. }
  1444. return nbuf;
  1445. }
  1446. /**
  1447. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1448. * for SG frames
  1449. * @vdev: DP vdev handle
  1450. * @nbuf: skb
  1451. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1452. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1453. *
  1454. * Return: NULL on success,
  1455. * nbuf when it fails to send
  1456. */
  1457. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1458. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1459. {
  1460. uint32_t cur_frag, nr_frags;
  1461. qdf_dma_addr_t paddr;
  1462. struct dp_tx_sg_info_s *sg_info;
  1463. sg_info = &msdu_info->u.sg_info;
  1464. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1465. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1466. QDF_DMA_TO_DEVICE)) {
  1467. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1468. "dma map error");
  1469. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1470. qdf_nbuf_free(nbuf);
  1471. return NULL;
  1472. }
  1473. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1474. seg_info->frags[0].paddr_lo = paddr;
  1475. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1476. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1477. seg_info->frags[0].vaddr = (void *) nbuf;
  1478. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1479. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1480. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1482. "frag dma map error");
  1483. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1484. qdf_nbuf_free(nbuf);
  1485. return NULL;
  1486. }
  1487. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1488. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1489. seg_info->frags[cur_frag + 1].paddr_hi =
  1490. ((uint64_t) paddr) >> 32;
  1491. seg_info->frags[cur_frag + 1].len =
  1492. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1493. }
  1494. seg_info->frag_cnt = (cur_frag + 1);
  1495. seg_info->total_len = qdf_nbuf_len(nbuf);
  1496. seg_info->next = NULL;
  1497. sg_info->curr_seg = seg_info;
  1498. msdu_info->frm_type = dp_tx_frm_sg;
  1499. msdu_info->num_seg = 1;
  1500. return nbuf;
  1501. }
  1502. /**
  1503. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1504. * @vdev: DP vdev handle
  1505. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1506. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1507. *
  1508. * Return: NULL on failure,
  1509. * nbuf when extracted successfully
  1510. */
  1511. static
  1512. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1513. struct dp_tx_msdu_info_s *msdu_info,
  1514. uint16_t ppdu_cookie)
  1515. {
  1516. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1517. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1518. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1519. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1520. (msdu_info->meta_data[5], 1);
  1521. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1522. (msdu_info->meta_data[5], 1);
  1523. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1524. (msdu_info->meta_data[6], ppdu_cookie);
  1525. msdu_info->exception_fw = 1;
  1526. msdu_info->is_tx_sniffer = 1;
  1527. }
  1528. #ifdef MESH_MODE_SUPPORT
  1529. /**
  1530. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1531. and prepare msdu_info for mesh frames.
  1532. * @vdev: DP vdev handle
  1533. * @nbuf: skb
  1534. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1535. *
  1536. * Return: NULL on failure,
  1537. * nbuf when extracted successfully
  1538. */
  1539. static
  1540. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1541. struct dp_tx_msdu_info_s *msdu_info)
  1542. {
  1543. struct meta_hdr_s *mhdr;
  1544. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1545. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1546. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1547. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1548. msdu_info->exception_fw = 0;
  1549. goto remove_meta_hdr;
  1550. }
  1551. msdu_info->exception_fw = 1;
  1552. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1553. meta_data->host_tx_desc_pool = 1;
  1554. meta_data->update_peer_cache = 1;
  1555. meta_data->learning_frame = 1;
  1556. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1557. meta_data->power = mhdr->power;
  1558. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1559. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1560. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1561. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1562. meta_data->dyn_bw = 1;
  1563. meta_data->valid_pwr = 1;
  1564. meta_data->valid_mcs_mask = 1;
  1565. meta_data->valid_nss_mask = 1;
  1566. meta_data->valid_preamble_type = 1;
  1567. meta_data->valid_retries = 1;
  1568. meta_data->valid_bw_info = 1;
  1569. }
  1570. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1571. meta_data->encrypt_type = 0;
  1572. meta_data->valid_encrypt_type = 1;
  1573. meta_data->learning_frame = 0;
  1574. }
  1575. meta_data->valid_key_flags = 1;
  1576. meta_data->key_flags = (mhdr->keyix & 0x3);
  1577. remove_meta_hdr:
  1578. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1579. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1580. "qdf_nbuf_pull_head failed");
  1581. qdf_nbuf_free(nbuf);
  1582. return NULL;
  1583. }
  1584. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1586. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1587. " tid %d to_fw %d",
  1588. __func__, msdu_info->meta_data[0],
  1589. msdu_info->meta_data[1],
  1590. msdu_info->meta_data[2],
  1591. msdu_info->meta_data[3],
  1592. msdu_info->meta_data[4],
  1593. msdu_info->meta_data[5],
  1594. msdu_info->tid, msdu_info->exception_fw);
  1595. return nbuf;
  1596. }
  1597. #else
  1598. static
  1599. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1600. struct dp_tx_msdu_info_s *msdu_info)
  1601. {
  1602. return nbuf;
  1603. }
  1604. #endif
  1605. /**
  1606. * dp_check_exc_metadata() - Checks if parameters are valid
  1607. * @tx_exc - holds all exception path parameters
  1608. *
  1609. * Returns true when all the parameters are valid else false
  1610. *
  1611. */
  1612. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1613. {
  1614. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1615. HTT_INVALID_TID);
  1616. bool invalid_encap_type = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1617. HTT_INVALID_TID);
  1618. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1619. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1620. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1621. tx_exc->ppdu_cookie == 0);
  1622. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1623. invalid_cookie) {
  1624. return false;
  1625. }
  1626. return true;
  1627. }
  1628. /**
  1629. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1630. * @vap_dev: DP vdev handle
  1631. * @nbuf: skb
  1632. * @tx_exc_metadata: Handle that holds exception path meta data
  1633. *
  1634. * Entry point for Core Tx layer (DP_TX) invoked from
  1635. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1636. *
  1637. * Return: NULL on success,
  1638. * nbuf when it fails to send
  1639. */
  1640. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1641. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1642. {
  1643. qdf_ether_header_t *eh = NULL;
  1644. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1645. struct dp_tx_msdu_info_s msdu_info;
  1646. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1647. if (!tx_exc_metadata)
  1648. goto fail;
  1649. msdu_info.tid = tx_exc_metadata->tid;
  1650. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1651. dp_verbose_debug("skb %pM", nbuf->data);
  1652. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1653. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1655. "Invalid parameters in exception path");
  1656. goto fail;
  1657. }
  1658. /* Basic sanity checks for unsupported packets */
  1659. /* MESH mode */
  1660. if (qdf_unlikely(vdev->mesh_vdev)) {
  1661. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1662. "Mesh mode is not supported in exception path");
  1663. goto fail;
  1664. }
  1665. /* TSO or SG */
  1666. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1667. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1669. "TSO and SG are not supported in exception path");
  1670. goto fail;
  1671. }
  1672. /* RAW */
  1673. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1675. "Raw frame is not supported in exception path");
  1676. goto fail;
  1677. }
  1678. /* Mcast enhancement*/
  1679. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1680. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1681. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1683. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1684. }
  1685. }
  1686. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1687. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1688. qdf_nbuf_len(nbuf));
  1689. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1690. tx_exc_metadata->ppdu_cookie);
  1691. }
  1692. /*
  1693. * Get HW Queue to use for this frame.
  1694. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1695. * dedicated for data and 1 for command.
  1696. * "queue_id" maps to one hardware ring.
  1697. * With each ring, we also associate a unique Tx descriptor pool
  1698. * to minimize lock contention for these resources.
  1699. */
  1700. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1701. /* Single linear frame */
  1702. /*
  1703. * If nbuf is a simple linear frame, use send_single function to
  1704. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1705. * SRNG. There is no need to setup a MSDU extension descriptor.
  1706. */
  1707. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1708. tx_exc_metadata->peer_id, tx_exc_metadata);
  1709. return nbuf;
  1710. fail:
  1711. dp_verbose_debug("pkt send failed");
  1712. return nbuf;
  1713. }
  1714. /**
  1715. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1716. * @vap_dev: DP vdev handle
  1717. * @nbuf: skb
  1718. *
  1719. * Entry point for Core Tx layer (DP_TX) invoked from
  1720. * hard_start_xmit in OSIF/HDD
  1721. *
  1722. * Return: NULL on success,
  1723. * nbuf when it fails to send
  1724. */
  1725. #ifdef MESH_MODE_SUPPORT
  1726. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1727. {
  1728. struct meta_hdr_s *mhdr;
  1729. qdf_nbuf_t nbuf_mesh = NULL;
  1730. qdf_nbuf_t nbuf_clone = NULL;
  1731. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1732. uint8_t no_enc_frame = 0;
  1733. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1734. if (!nbuf_mesh) {
  1735. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1736. "qdf_nbuf_unshare failed");
  1737. return nbuf;
  1738. }
  1739. nbuf = nbuf_mesh;
  1740. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1741. if ((vdev->sec_type != cdp_sec_type_none) &&
  1742. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1743. no_enc_frame = 1;
  1744. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1745. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1746. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1747. !no_enc_frame) {
  1748. nbuf_clone = qdf_nbuf_clone(nbuf);
  1749. if (!nbuf_clone) {
  1750. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1751. "qdf_nbuf_clone failed");
  1752. return nbuf;
  1753. }
  1754. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1755. }
  1756. if (nbuf_clone) {
  1757. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1758. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1759. } else {
  1760. qdf_nbuf_free(nbuf_clone);
  1761. }
  1762. }
  1763. if (no_enc_frame)
  1764. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1765. else
  1766. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1767. nbuf = dp_tx_send(vap_dev, nbuf);
  1768. if ((!nbuf) && no_enc_frame) {
  1769. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1770. }
  1771. return nbuf;
  1772. }
  1773. #else
  1774. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1775. {
  1776. return dp_tx_send(vap_dev, nbuf);
  1777. }
  1778. #endif
  1779. /**
  1780. * dp_tx_send() - Transmit a frame on a given VAP
  1781. * @vap_dev: DP vdev handle
  1782. * @nbuf: skb
  1783. *
  1784. * Entry point for Core Tx layer (DP_TX) invoked from
  1785. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1786. * cases
  1787. *
  1788. * Return: NULL on success,
  1789. * nbuf when it fails to send
  1790. */
  1791. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1792. {
  1793. qdf_ether_header_t *eh = NULL;
  1794. struct dp_tx_msdu_info_s msdu_info;
  1795. struct dp_tx_seg_info_s seg_info;
  1796. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1797. uint16_t peer_id = HTT_INVALID_PEER;
  1798. qdf_nbuf_t nbuf_mesh = NULL;
  1799. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1800. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1801. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1802. dp_verbose_debug("skb %pM", nbuf->data);
  1803. /*
  1804. * Set Default Host TID value to invalid TID
  1805. * (TID override disabled)
  1806. */
  1807. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1808. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1809. if (qdf_unlikely(vdev->mesh_vdev)) {
  1810. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1811. &msdu_info);
  1812. if (!nbuf_mesh) {
  1813. dp_verbose_debug("Extracting mesh metadata failed");
  1814. return nbuf;
  1815. }
  1816. nbuf = nbuf_mesh;
  1817. }
  1818. /*
  1819. * Get HW Queue to use for this frame.
  1820. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1821. * dedicated for data and 1 for command.
  1822. * "queue_id" maps to one hardware ring.
  1823. * With each ring, we also associate a unique Tx descriptor pool
  1824. * to minimize lock contention for these resources.
  1825. */
  1826. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1827. /*
  1828. * TCL H/W supports 2 DSCP-TID mapping tables.
  1829. * Table 1 - Default DSCP-TID mapping table
  1830. * Table 2 - 1 DSCP-TID override table
  1831. *
  1832. * If we need a different DSCP-TID mapping for this vap,
  1833. * call tid_classify to extract DSCP/ToS from frame and
  1834. * map to a TID and store in msdu_info. This is later used
  1835. * to fill in TCL Input descriptor (per-packet TID override).
  1836. */
  1837. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1838. /*
  1839. * Classify the frame and call corresponding
  1840. * "prepare" function which extracts the segment (TSO)
  1841. * and fragmentation information (for TSO , SG, ME, or Raw)
  1842. * into MSDU_INFO structure which is later used to fill
  1843. * SW and HW descriptors.
  1844. */
  1845. if (qdf_nbuf_is_tso(nbuf)) {
  1846. dp_verbose_debug("TSO frame %pK", vdev);
  1847. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1848. qdf_nbuf_len(nbuf));
  1849. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1850. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1851. qdf_nbuf_len(nbuf));
  1852. return nbuf;
  1853. }
  1854. goto send_multiple;
  1855. }
  1856. /* SG */
  1857. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1858. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1859. if (!nbuf)
  1860. return NULL;
  1861. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1862. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1863. qdf_nbuf_len(nbuf));
  1864. goto send_multiple;
  1865. }
  1866. #ifdef ATH_SUPPORT_IQUE
  1867. /* Mcast to Ucast Conversion*/
  1868. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1869. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1870. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1871. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1872. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1873. DP_STATS_INC_PKT(vdev,
  1874. tx_i.mcast_en.mcast_pkt, 1,
  1875. qdf_nbuf_len(nbuf));
  1876. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1877. QDF_STATUS_SUCCESS) {
  1878. return NULL;
  1879. }
  1880. }
  1881. }
  1882. #endif
  1883. /* RAW */
  1884. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1885. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1886. if (!nbuf)
  1887. return NULL;
  1888. dp_verbose_debug("Raw frame %pK", vdev);
  1889. goto send_multiple;
  1890. }
  1891. /* Single linear frame */
  1892. /*
  1893. * If nbuf is a simple linear frame, use send_single function to
  1894. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1895. * SRNG. There is no need to setup a MSDU extension descriptor.
  1896. */
  1897. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1898. return nbuf;
  1899. send_multiple:
  1900. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1901. return nbuf;
  1902. }
  1903. /**
  1904. * dp_tx_reinject_handler() - Tx Reinject Handler
  1905. * @tx_desc: software descriptor head pointer
  1906. * @status : Tx completion status from HTT descriptor
  1907. *
  1908. * This function reinjects frames back to Target.
  1909. * Todo - Host queue needs to be added
  1910. *
  1911. * Return: none
  1912. */
  1913. static
  1914. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1915. {
  1916. struct dp_vdev *vdev;
  1917. struct dp_peer *peer = NULL;
  1918. uint32_t peer_id = HTT_INVALID_PEER;
  1919. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1920. qdf_nbuf_t nbuf_copy = NULL;
  1921. struct dp_tx_msdu_info_s msdu_info;
  1922. struct dp_peer *sa_peer = NULL;
  1923. struct dp_ast_entry *ast_entry = NULL;
  1924. struct dp_soc *soc = NULL;
  1925. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1926. #ifdef WDS_VENDOR_EXTENSION
  1927. int is_mcast = 0, is_ucast = 0;
  1928. int num_peers_3addr = 0;
  1929. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1930. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1931. #endif
  1932. vdev = tx_desc->vdev;
  1933. soc = vdev->pdev->soc;
  1934. qdf_assert(vdev);
  1935. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1936. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1937. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1938. "%s Tx reinject path", __func__);
  1939. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1940. qdf_nbuf_len(tx_desc->nbuf));
  1941. qdf_spin_lock_bh(&(soc->ast_lock));
  1942. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1943. (soc,
  1944. (uint8_t *)(eh->ether_shost),
  1945. vdev->pdev->pdev_id);
  1946. if (ast_entry)
  1947. sa_peer = ast_entry->peer;
  1948. qdf_spin_unlock_bh(&(soc->ast_lock));
  1949. #ifdef WDS_VENDOR_EXTENSION
  1950. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1951. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1952. } else {
  1953. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1954. }
  1955. is_ucast = !is_mcast;
  1956. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1957. if (peer->bss_peer)
  1958. continue;
  1959. /* Detect wds peers that use 3-addr framing for mcast.
  1960. * if there are any, the bss_peer is used to send the
  1961. * the mcast frame using 3-addr format. all wds enabled
  1962. * peers that use 4-addr framing for mcast frames will
  1963. * be duplicated and sent as 4-addr frames below.
  1964. */
  1965. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1966. num_peers_3addr = 1;
  1967. break;
  1968. }
  1969. }
  1970. #endif
  1971. if (qdf_unlikely(vdev->mesh_vdev)) {
  1972. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1973. } else {
  1974. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1975. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1976. #ifdef WDS_VENDOR_EXTENSION
  1977. /*
  1978. * . if 3-addr STA, then send on BSS Peer
  1979. * . if Peer WDS enabled and accept 4-addr mcast,
  1980. * send mcast on that peer only
  1981. * . if Peer WDS enabled and accept 4-addr ucast,
  1982. * send ucast on that peer only
  1983. */
  1984. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1985. (peer->wds_enabled &&
  1986. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1987. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1988. #else
  1989. ((peer->bss_peer &&
  1990. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1991. peer->nawds_enabled)) {
  1992. #endif
  1993. peer_id = DP_INVALID_PEER;
  1994. if (peer->nawds_enabled) {
  1995. peer_id = peer->peer_ids[0];
  1996. if (sa_peer == peer) {
  1997. QDF_TRACE(
  1998. QDF_MODULE_ID_DP,
  1999. QDF_TRACE_LEVEL_DEBUG,
  2000. " %s: multicast packet",
  2001. __func__);
  2002. DP_STATS_INC(peer,
  2003. tx.nawds_mcast_drop, 1);
  2004. continue;
  2005. }
  2006. }
  2007. nbuf_copy = qdf_nbuf_copy(nbuf);
  2008. if (!nbuf_copy) {
  2009. QDF_TRACE(QDF_MODULE_ID_DP,
  2010. QDF_TRACE_LEVEL_DEBUG,
  2011. FL("nbuf copy failed"));
  2012. break;
  2013. }
  2014. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2015. nbuf_copy,
  2016. &msdu_info,
  2017. peer_id,
  2018. NULL);
  2019. if (nbuf_copy) {
  2020. QDF_TRACE(QDF_MODULE_ID_DP,
  2021. QDF_TRACE_LEVEL_DEBUG,
  2022. FL("pkt send failed"));
  2023. qdf_nbuf_free(nbuf_copy);
  2024. } else {
  2025. if (peer_id != DP_INVALID_PEER)
  2026. DP_STATS_INC_PKT(peer,
  2027. tx.nawds_mcast,
  2028. 1, qdf_nbuf_len(nbuf));
  2029. }
  2030. }
  2031. }
  2032. }
  2033. if (vdev->nawds_enabled) {
  2034. peer_id = DP_INVALID_PEER;
  2035. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2036. 1, qdf_nbuf_len(nbuf));
  2037. nbuf = dp_tx_send_msdu_single(vdev,
  2038. nbuf,
  2039. &msdu_info,
  2040. peer_id, NULL);
  2041. if (nbuf) {
  2042. QDF_TRACE(QDF_MODULE_ID_DP,
  2043. QDF_TRACE_LEVEL_DEBUG,
  2044. FL("pkt send failed"));
  2045. qdf_nbuf_free(nbuf);
  2046. }
  2047. } else
  2048. qdf_nbuf_free(nbuf);
  2049. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2050. }
  2051. /**
  2052. * dp_tx_inspect_handler() - Tx Inspect Handler
  2053. * @tx_desc: software descriptor head pointer
  2054. * @status : Tx completion status from HTT descriptor
  2055. *
  2056. * Handles Tx frames sent back to Host for inspection
  2057. * (ProxyARP)
  2058. *
  2059. * Return: none
  2060. */
  2061. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2062. {
  2063. struct dp_soc *soc;
  2064. struct dp_pdev *pdev = tx_desc->pdev;
  2065. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2066. "%s Tx inspect path",
  2067. __func__);
  2068. qdf_assert(pdev);
  2069. soc = pdev->soc;
  2070. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2071. qdf_nbuf_len(tx_desc->nbuf));
  2072. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2073. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2074. }
  2075. #ifdef FEATURE_PERPKT_INFO
  2076. /**
  2077. * dp_get_completion_indication_for_stack() - send completion to stack
  2078. * @soc : dp_soc handle
  2079. * @pdev: dp_pdev handle
  2080. * @peer: dp peer handle
  2081. * @ts: transmit completion status structure
  2082. * @netbuf: Buffer pointer for free
  2083. *
  2084. * This function is used for indication whether buffer needs to be
  2085. * sent to stack for freeing or not
  2086. */
  2087. QDF_STATUS
  2088. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2089. struct dp_pdev *pdev,
  2090. struct dp_peer *peer,
  2091. struct hal_tx_completion_status *ts,
  2092. qdf_nbuf_t netbuf,
  2093. uint64_t time_latency)
  2094. {
  2095. struct tx_capture_hdr *ppdu_hdr;
  2096. uint16_t peer_id = ts->peer_id;
  2097. uint32_t ppdu_id = ts->ppdu_id;
  2098. uint8_t first_msdu = ts->first_msdu;
  2099. uint8_t last_msdu = ts->last_msdu;
  2100. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2101. !pdev->latency_capture_enable))
  2102. return QDF_STATUS_E_NOSUPPORT;
  2103. if (!peer) {
  2104. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2105. FL("Peer Invalid"));
  2106. return QDF_STATUS_E_INVAL;
  2107. }
  2108. if (pdev->mcopy_mode) {
  2109. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2110. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2111. return QDF_STATUS_E_INVAL;
  2112. }
  2113. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2114. pdev->m_copy_id.tx_peer_id = peer_id;
  2115. }
  2116. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2117. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2118. FL("No headroom"));
  2119. return QDF_STATUS_E_NOMEM;
  2120. }
  2121. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2122. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2123. QDF_MAC_ADDR_SIZE);
  2124. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2125. QDF_MAC_ADDR_SIZE);
  2126. ppdu_hdr->ppdu_id = ppdu_id;
  2127. ppdu_hdr->peer_id = peer_id;
  2128. ppdu_hdr->first_msdu = first_msdu;
  2129. ppdu_hdr->last_msdu = last_msdu;
  2130. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2131. ppdu_hdr->tsf = ts->tsf;
  2132. ppdu_hdr->time_latency = time_latency;
  2133. }
  2134. return QDF_STATUS_SUCCESS;
  2135. }
  2136. /**
  2137. * dp_send_completion_to_stack() - send completion to stack
  2138. * @soc : dp_soc handle
  2139. * @pdev: dp_pdev handle
  2140. * @peer_id: peer_id of the peer for which completion came
  2141. * @ppdu_id: ppdu_id
  2142. * @netbuf: Buffer pointer for free
  2143. *
  2144. * This function is used to send completion to stack
  2145. * to free buffer
  2146. */
  2147. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2148. uint16_t peer_id, uint32_t ppdu_id,
  2149. qdf_nbuf_t netbuf)
  2150. {
  2151. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2152. netbuf, peer_id,
  2153. WDI_NO_VAL, pdev->pdev_id);
  2154. }
  2155. #else
  2156. static QDF_STATUS
  2157. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2158. struct dp_pdev *pdev,
  2159. struct dp_peer *peer,
  2160. struct hal_tx_completion_status *ts,
  2161. qdf_nbuf_t netbuf,
  2162. uint64_t time_latency)
  2163. {
  2164. return QDF_STATUS_E_NOSUPPORT;
  2165. }
  2166. static void
  2167. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2168. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2169. {
  2170. }
  2171. #endif
  2172. /**
  2173. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2174. * @soc: Soc handle
  2175. * @desc: software Tx descriptor to be processed
  2176. *
  2177. * Return: none
  2178. */
  2179. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2180. struct dp_tx_desc_s *desc)
  2181. {
  2182. struct dp_vdev *vdev = desc->vdev;
  2183. qdf_nbuf_t nbuf = desc->nbuf;
  2184. /* nbuf already freed in vdev detach path */
  2185. if (!nbuf)
  2186. return;
  2187. /* If it is TDLS mgmt, don't unmap or free the frame */
  2188. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2189. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2190. /* 0 : MSDU buffer, 1 : MLE */
  2191. if (desc->msdu_ext_desc) {
  2192. /* TSO free */
  2193. if (hal_tx_ext_desc_get_tso_enable(
  2194. desc->msdu_ext_desc->vaddr)) {
  2195. /* unmap eash TSO seg before free the nbuf */
  2196. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2197. desc->tso_num_desc);
  2198. qdf_nbuf_free(nbuf);
  2199. return;
  2200. }
  2201. }
  2202. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2203. if (qdf_unlikely(!vdev)) {
  2204. qdf_nbuf_free(nbuf);
  2205. return;
  2206. }
  2207. if (qdf_likely(!vdev->mesh_vdev))
  2208. qdf_nbuf_free(nbuf);
  2209. else {
  2210. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2211. qdf_nbuf_free(nbuf);
  2212. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2213. } else
  2214. vdev->osif_tx_free_ext((nbuf));
  2215. }
  2216. }
  2217. #ifdef MESH_MODE_SUPPORT
  2218. /**
  2219. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2220. * in mesh meta header
  2221. * @tx_desc: software descriptor head pointer
  2222. * @ts: pointer to tx completion stats
  2223. * Return: none
  2224. */
  2225. static
  2226. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2227. struct hal_tx_completion_status *ts)
  2228. {
  2229. struct meta_hdr_s *mhdr;
  2230. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2231. if (!tx_desc->msdu_ext_desc) {
  2232. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2234. "netbuf %pK offset %d",
  2235. netbuf, tx_desc->pkt_offset);
  2236. return;
  2237. }
  2238. }
  2239. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2240. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2241. "netbuf %pK offset %lu", netbuf,
  2242. sizeof(struct meta_hdr_s));
  2243. return;
  2244. }
  2245. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2246. mhdr->rssi = ts->ack_frame_rssi;
  2247. mhdr->channel = tx_desc->pdev->operating_channel;
  2248. }
  2249. #else
  2250. static
  2251. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2252. struct hal_tx_completion_status *ts)
  2253. {
  2254. }
  2255. #endif
  2256. /**
  2257. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2258. * to pass in correct fields
  2259. *
  2260. * @vdev: pdev handle
  2261. * @tx_desc: tx descriptor
  2262. * @tid: tid value
  2263. * @ring_id: TCL or WBM ring number for transmit path
  2264. * Return: none
  2265. */
  2266. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2267. struct dp_tx_desc_s *tx_desc,
  2268. uint8_t tid, uint8_t ring_id)
  2269. {
  2270. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2271. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2272. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2273. return;
  2274. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2275. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2276. timestamp_hw_enqueue = tx_desc->timestamp;
  2277. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2278. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2279. timestamp_hw_enqueue);
  2280. interframe_delay = (uint32_t)(timestamp_ingress -
  2281. vdev->prev_tx_enq_tstamp);
  2282. /*
  2283. * Delay in software enqueue
  2284. */
  2285. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2286. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2287. /*
  2288. * Delay between packet enqueued to HW and Tx completion
  2289. */
  2290. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2291. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2292. /*
  2293. * Update interframe delay stats calculated at hardstart receive point.
  2294. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2295. * interframe delay will not be calculate correctly for 1st frame.
  2296. * On the other side, this will help in avoiding extra per packet check
  2297. * of !vdev->prev_tx_enq_tstamp.
  2298. */
  2299. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2300. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2301. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2302. }
  2303. /**
  2304. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2305. * per wbm ring
  2306. *
  2307. * @tx_desc: software descriptor head pointer
  2308. * @ts: Tx completion status
  2309. * @peer: peer handle
  2310. * @ring_id: ring number
  2311. *
  2312. * Return: None
  2313. */
  2314. static inline void
  2315. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2316. struct hal_tx_completion_status *ts,
  2317. struct dp_peer *peer, uint8_t ring_id)
  2318. {
  2319. struct dp_pdev *pdev = peer->vdev->pdev;
  2320. struct dp_soc *soc = NULL;
  2321. uint8_t mcs, pkt_type;
  2322. uint8_t tid = ts->tid;
  2323. uint32_t length;
  2324. struct cdp_tid_tx_stats *tid_stats;
  2325. if (!pdev)
  2326. return;
  2327. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2328. tid = CDP_MAX_DATA_TIDS - 1;
  2329. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2330. soc = pdev->soc;
  2331. mcs = ts->mcs;
  2332. pkt_type = ts->pkt_type;
  2333. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2334. dp_err("Release source is not from TQM");
  2335. return;
  2336. }
  2337. length = qdf_nbuf_len(tx_desc->nbuf);
  2338. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2339. if (qdf_unlikely(pdev->delay_stats_flag))
  2340. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2341. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2342. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2343. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2344. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2345. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2346. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2347. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2348. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2349. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2350. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2351. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2352. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2353. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2354. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2355. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2356. tid_stats->comp_fail_cnt++;
  2357. return;
  2358. }
  2359. tid_stats->success_cnt++;
  2360. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2361. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2362. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2363. /*
  2364. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2365. * Return from here if HTT PPDU events are enabled.
  2366. */
  2367. if (!(soc->process_tx_status))
  2368. return;
  2369. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2370. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2371. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2372. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2373. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2374. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2375. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2376. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2377. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2378. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2379. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2380. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2381. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2382. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2383. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2384. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2385. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2386. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2387. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2388. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2389. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2390. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2391. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2392. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2393. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2394. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2395. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2396. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2397. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2398. &peer->stats, ts->peer_id,
  2399. UPDATE_PEER_STATS, pdev->pdev_id);
  2400. #endif
  2401. }
  2402. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2403. /**
  2404. * dp_tx_flow_pool_lock() - take flow pool lock
  2405. * @soc: core txrx main context
  2406. * @tx_desc: tx desc
  2407. *
  2408. * Return: None
  2409. */
  2410. static inline
  2411. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2412. struct dp_tx_desc_s *tx_desc)
  2413. {
  2414. struct dp_tx_desc_pool_s *pool;
  2415. uint8_t desc_pool_id;
  2416. desc_pool_id = tx_desc->pool_id;
  2417. pool = &soc->tx_desc[desc_pool_id];
  2418. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2419. }
  2420. /**
  2421. * dp_tx_flow_pool_unlock() - release flow pool lock
  2422. * @soc: core txrx main context
  2423. * @tx_desc: tx desc
  2424. *
  2425. * Return: None
  2426. */
  2427. static inline
  2428. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2429. struct dp_tx_desc_s *tx_desc)
  2430. {
  2431. struct dp_tx_desc_pool_s *pool;
  2432. uint8_t desc_pool_id;
  2433. desc_pool_id = tx_desc->pool_id;
  2434. pool = &soc->tx_desc[desc_pool_id];
  2435. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2436. }
  2437. #else
  2438. static inline
  2439. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2440. {
  2441. }
  2442. static inline
  2443. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2444. {
  2445. }
  2446. #endif
  2447. /**
  2448. * dp_tx_notify_completion() - Notify tx completion for this desc
  2449. * @soc: core txrx main context
  2450. * @tx_desc: tx desc
  2451. * @netbuf: buffer
  2452. *
  2453. * Return: none
  2454. */
  2455. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2456. struct dp_tx_desc_s *tx_desc,
  2457. qdf_nbuf_t netbuf)
  2458. {
  2459. void *osif_dev;
  2460. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2461. qdf_assert(tx_desc);
  2462. dp_tx_flow_pool_lock(soc, tx_desc);
  2463. if (!tx_desc->vdev ||
  2464. !tx_desc->vdev->osif_vdev) {
  2465. dp_tx_flow_pool_unlock(soc, tx_desc);
  2466. return;
  2467. }
  2468. osif_dev = tx_desc->vdev->osif_vdev;
  2469. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2470. dp_tx_flow_pool_unlock(soc, tx_desc);
  2471. if (tx_compl_cbk)
  2472. tx_compl_cbk(netbuf, osif_dev);
  2473. }
  2474. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2475. * @pdev: pdev handle
  2476. * @tid: tid value
  2477. * @txdesc_ts: timestamp from txdesc
  2478. * @ppdu_id: ppdu id
  2479. *
  2480. * Return: none
  2481. */
  2482. #ifdef FEATURE_PERPKT_INFO
  2483. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2484. struct dp_peer *peer,
  2485. uint8_t tid,
  2486. uint64_t txdesc_ts,
  2487. uint32_t ppdu_id)
  2488. {
  2489. uint64_t delta_ms;
  2490. struct cdp_tx_sojourn_stats *sojourn_stats;
  2491. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2492. return;
  2493. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2494. tid >= CDP_DATA_TID_MAX))
  2495. return;
  2496. if (qdf_unlikely(!pdev->sojourn_buf))
  2497. return;
  2498. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2499. qdf_nbuf_data(pdev->sojourn_buf);
  2500. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2501. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2502. txdesc_ts;
  2503. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2504. delta_ms);
  2505. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2506. sojourn_stats->num_msdus[tid] = 1;
  2507. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2508. peer->avg_sojourn_msdu[tid].internal;
  2509. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2510. pdev->sojourn_buf, HTT_INVALID_PEER,
  2511. WDI_NO_VAL, pdev->pdev_id);
  2512. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2513. sojourn_stats->num_msdus[tid] = 0;
  2514. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2515. }
  2516. #else
  2517. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2518. uint8_t tid,
  2519. uint64_t txdesc_ts,
  2520. uint32_t ppdu_id)
  2521. {
  2522. }
  2523. #endif
  2524. /**
  2525. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2526. * @soc: DP Soc handle
  2527. * @tx_desc: software Tx descriptor
  2528. * @ts : Tx completion status from HAL/HTT descriptor
  2529. *
  2530. * Return: none
  2531. */
  2532. static inline void
  2533. dp_tx_comp_process_desc(struct dp_soc *soc,
  2534. struct dp_tx_desc_s *desc,
  2535. struct hal_tx_completion_status *ts,
  2536. struct dp_peer *peer)
  2537. {
  2538. uint64_t time_latency = 0;
  2539. /*
  2540. * m_copy/tx_capture modes are not supported for
  2541. * scatter gather packets
  2542. */
  2543. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2544. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2545. desc->timestamp);
  2546. }
  2547. if (!(desc->msdu_ext_desc)) {
  2548. if (QDF_STATUS_SUCCESS ==
  2549. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2550. return;
  2551. }
  2552. if (QDF_STATUS_SUCCESS ==
  2553. dp_get_completion_indication_for_stack(soc,
  2554. desc->pdev,
  2555. peer, ts,
  2556. desc->nbuf,
  2557. time_latency)) {
  2558. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2559. QDF_DMA_TO_DEVICE);
  2560. dp_send_completion_to_stack(soc,
  2561. desc->pdev,
  2562. ts->peer_id,
  2563. ts->ppdu_id,
  2564. desc->nbuf);
  2565. return;
  2566. }
  2567. }
  2568. dp_tx_comp_free_buf(soc, desc);
  2569. }
  2570. /**
  2571. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2572. * @tx_desc: software descriptor head pointer
  2573. * @ts: Tx completion status
  2574. * @peer: peer handle
  2575. * @ring_id: ring number
  2576. *
  2577. * Return: none
  2578. */
  2579. static inline
  2580. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2581. struct hal_tx_completion_status *ts,
  2582. struct dp_peer *peer, uint8_t ring_id)
  2583. {
  2584. uint32_t length;
  2585. qdf_ether_header_t *eh;
  2586. struct dp_soc *soc = NULL;
  2587. struct dp_vdev *vdev = tx_desc->vdev;
  2588. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2589. if (!vdev || !nbuf) {
  2590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2591. "invalid tx descriptor. vdev or nbuf NULL");
  2592. goto out;
  2593. }
  2594. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2595. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2596. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2597. QDF_TRACE_DEFAULT_PDEV_ID,
  2598. qdf_nbuf_data_addr(nbuf),
  2599. sizeof(qdf_nbuf_data(nbuf)),
  2600. tx_desc->id,
  2601. ts->status));
  2602. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2603. "-------------------- \n"
  2604. "Tx Completion Stats: \n"
  2605. "-------------------- \n"
  2606. "ack_frame_rssi = %d \n"
  2607. "first_msdu = %d \n"
  2608. "last_msdu = %d \n"
  2609. "msdu_part_of_amsdu = %d \n"
  2610. "rate_stats valid = %d \n"
  2611. "bw = %d \n"
  2612. "pkt_type = %d \n"
  2613. "stbc = %d \n"
  2614. "ldpc = %d \n"
  2615. "sgi = %d \n"
  2616. "mcs = %d \n"
  2617. "ofdma = %d \n"
  2618. "tones_in_ru = %d \n"
  2619. "tsf = %d \n"
  2620. "ppdu_id = %d \n"
  2621. "transmit_cnt = %d \n"
  2622. "tid = %d \n"
  2623. "peer_id = %d\n",
  2624. ts->ack_frame_rssi, ts->first_msdu,
  2625. ts->last_msdu, ts->msdu_part_of_amsdu,
  2626. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2627. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2628. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2629. ts->transmit_cnt, ts->tid, ts->peer_id);
  2630. soc = vdev->pdev->soc;
  2631. /* Update SoC level stats */
  2632. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2633. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2634. /* Update per-packet stats for mesh mode */
  2635. if (qdf_unlikely(vdev->mesh_vdev) &&
  2636. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2637. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2638. length = qdf_nbuf_len(nbuf);
  2639. /* Update peer level stats */
  2640. if (!peer) {
  2641. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2642. "peer is null or deletion in progress");
  2643. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2644. goto out;
  2645. }
  2646. if (qdf_likely(!peer->bss_peer)) {
  2647. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2648. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2649. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2650. } else {
  2651. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2652. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2653. if ((peer->vdev->tx_encap_type ==
  2654. htt_cmn_pkt_type_ethernet) &&
  2655. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2656. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2657. }
  2658. }
  2659. }
  2660. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2661. #ifdef QCA_SUPPORT_RDK_STATS
  2662. if (soc->wlanstats_enabled)
  2663. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2664. tx_desc->timestamp,
  2665. ts->ppdu_id);
  2666. #endif
  2667. out:
  2668. return;
  2669. }
  2670. /**
  2671. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2672. * @soc: core txrx main context
  2673. * @comp_head: software descriptor head pointer
  2674. * @ring_id: ring number
  2675. *
  2676. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2677. * and release the software descriptors after processing is complete
  2678. *
  2679. * Return: none
  2680. */
  2681. static void
  2682. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2683. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2684. {
  2685. struct dp_tx_desc_s *desc;
  2686. struct dp_tx_desc_s *next;
  2687. struct hal_tx_completion_status ts = {0};
  2688. struct dp_peer *peer;
  2689. qdf_nbuf_t netbuf;
  2690. desc = comp_head;
  2691. while (desc) {
  2692. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2693. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2694. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2695. netbuf = desc->nbuf;
  2696. /* check tx complete notification */
  2697. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2698. dp_tx_notify_completion(soc, desc, netbuf);
  2699. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2700. if (peer)
  2701. dp_peer_unref_del_find_by_id(peer);
  2702. next = desc->next;
  2703. dp_tx_desc_release(desc, desc->pool_id);
  2704. desc = next;
  2705. }
  2706. }
  2707. /**
  2708. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2709. * @tx_desc: software descriptor head pointer
  2710. * @status : Tx completion status from HTT descriptor
  2711. * @ring_id: ring number
  2712. *
  2713. * This function will process HTT Tx indication messages from Target
  2714. *
  2715. * Return: none
  2716. */
  2717. static
  2718. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2719. uint8_t ring_id)
  2720. {
  2721. uint8_t tx_status;
  2722. struct dp_pdev *pdev;
  2723. struct dp_vdev *vdev;
  2724. struct dp_soc *soc;
  2725. struct hal_tx_completion_status ts = {0};
  2726. uint32_t *htt_desc = (uint32_t *)status;
  2727. struct dp_peer *peer;
  2728. struct cdp_tid_tx_stats *tid_stats = NULL;
  2729. qdf_assert(tx_desc->pdev);
  2730. pdev = tx_desc->pdev;
  2731. vdev = tx_desc->vdev;
  2732. soc = pdev->soc;
  2733. if (!vdev)
  2734. return;
  2735. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2736. switch (tx_status) {
  2737. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2738. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2739. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2740. {
  2741. uint8_t tid;
  2742. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2743. ts.peer_id =
  2744. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2745. htt_desc[2]);
  2746. ts.tid =
  2747. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2748. htt_desc[2]);
  2749. } else {
  2750. ts.peer_id = HTT_INVALID_PEER;
  2751. ts.tid = HTT_INVALID_TID;
  2752. }
  2753. ts.ppdu_id =
  2754. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2755. htt_desc[1]);
  2756. ts.ack_frame_rssi =
  2757. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2758. htt_desc[1]);
  2759. ts.first_msdu = 1;
  2760. ts.last_msdu = 1;
  2761. tid = ts.tid;
  2762. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2763. tid = CDP_MAX_DATA_TIDS - 1;
  2764. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2765. if (qdf_unlikely(pdev->delay_stats_flag))
  2766. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2767. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2768. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2769. tid_stats->comp_fail_cnt++;
  2770. } else {
  2771. tid_stats->success_cnt++;
  2772. }
  2773. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2774. if (qdf_likely(peer))
  2775. dp_peer_unref_del_find_by_id(peer);
  2776. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2777. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2778. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2779. break;
  2780. }
  2781. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2782. {
  2783. dp_tx_reinject_handler(tx_desc, status);
  2784. break;
  2785. }
  2786. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2787. {
  2788. dp_tx_inspect_handler(tx_desc, status);
  2789. break;
  2790. }
  2791. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2792. {
  2793. dp_tx_mec_handler(vdev, status);
  2794. break;
  2795. }
  2796. default:
  2797. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2798. "%s Invalid HTT tx_status %d\n",
  2799. __func__, tx_status);
  2800. break;
  2801. }
  2802. }
  2803. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2804. static inline
  2805. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2806. {
  2807. bool limit_hit = false;
  2808. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2809. limit_hit =
  2810. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2811. if (limit_hit)
  2812. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2813. return limit_hit;
  2814. }
  2815. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2816. {
  2817. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2818. }
  2819. #else
  2820. static inline
  2821. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2822. {
  2823. return false;
  2824. }
  2825. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2826. {
  2827. return false;
  2828. }
  2829. #endif
  2830. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2831. void *hal_srng, uint8_t ring_id, uint32_t quota)
  2832. {
  2833. void *tx_comp_hal_desc;
  2834. uint8_t buffer_src;
  2835. uint8_t pool_id;
  2836. uint32_t tx_desc_id;
  2837. struct dp_tx_desc_s *tx_desc = NULL;
  2838. struct dp_tx_desc_s *head_desc = NULL;
  2839. struct dp_tx_desc_s *tail_desc = NULL;
  2840. uint32_t num_processed = 0;
  2841. uint32_t count = 0;
  2842. bool force_break = false;
  2843. DP_HIST_INIT();
  2844. more_data:
  2845. /* Re-initialize local variables to be re-used */
  2846. head_desc = NULL;
  2847. tail_desc = NULL;
  2848. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2849. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2850. "%s %d : HAL RING Access Failed -- %pK",
  2851. __func__, __LINE__, hal_srng);
  2852. return 0;
  2853. }
  2854. /* Find head descriptor from completion ring */
  2855. while (qdf_likely(tx_comp_hal_desc =
  2856. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2857. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2858. /* If this buffer was not released by TQM or FW, then it is not
  2859. * Tx completion indication, assert */
  2860. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2861. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2862. QDF_TRACE(QDF_MODULE_ID_DP,
  2863. QDF_TRACE_LEVEL_FATAL,
  2864. "Tx comp release_src != TQM | FW but from %d",
  2865. buffer_src);
  2866. hal_dump_comp_desc(tx_comp_hal_desc);
  2867. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2868. qdf_assert_always(0);
  2869. }
  2870. /* Get descriptor id */
  2871. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2872. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2873. DP_TX_DESC_ID_POOL_OS;
  2874. /* Find Tx descriptor */
  2875. tx_desc = dp_tx_desc_find(soc, pool_id,
  2876. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2877. DP_TX_DESC_ID_PAGE_OS,
  2878. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2879. DP_TX_DESC_ID_OFFSET_OS);
  2880. /*
  2881. * If the descriptor is already freed in vdev_detach,
  2882. * continue to next descriptor
  2883. */
  2884. if (!tx_desc->vdev && !tx_desc->flags) {
  2885. QDF_TRACE(QDF_MODULE_ID_DP,
  2886. QDF_TRACE_LEVEL_INFO,
  2887. "Descriptor freed in vdev_detach %d",
  2888. tx_desc_id);
  2889. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2890. count++;
  2891. continue;
  2892. }
  2893. /*
  2894. * If the release source is FW, process the HTT status
  2895. */
  2896. if (qdf_unlikely(buffer_src ==
  2897. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2898. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2899. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2900. htt_tx_status);
  2901. dp_tx_process_htt_completion(tx_desc,
  2902. htt_tx_status, ring_id);
  2903. } else {
  2904. /* Pool id is not matching. Error */
  2905. if (tx_desc->pool_id != pool_id) {
  2906. QDF_TRACE(QDF_MODULE_ID_DP,
  2907. QDF_TRACE_LEVEL_FATAL,
  2908. "Tx Comp pool id %d not matched %d",
  2909. pool_id, tx_desc->pool_id);
  2910. qdf_assert_always(0);
  2911. }
  2912. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2913. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2914. QDF_TRACE(QDF_MODULE_ID_DP,
  2915. QDF_TRACE_LEVEL_FATAL,
  2916. "Txdesc invalid, flgs = %x,id = %d",
  2917. tx_desc->flags, tx_desc_id);
  2918. qdf_assert_always(0);
  2919. }
  2920. /* First ring descriptor on the cycle */
  2921. if (!head_desc) {
  2922. head_desc = tx_desc;
  2923. tail_desc = tx_desc;
  2924. }
  2925. tail_desc->next = tx_desc;
  2926. tx_desc->next = NULL;
  2927. tail_desc = tx_desc;
  2928. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2929. /* Collect hw completion contents */
  2930. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2931. &tx_desc->comp, 1);
  2932. }
  2933. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2934. /*
  2935. * Processed packet count is more than given quota
  2936. * stop to processing
  2937. */
  2938. if (num_processed >= quota) {
  2939. force_break = true;
  2940. break;
  2941. }
  2942. count++;
  2943. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2944. break;
  2945. }
  2946. hal_srng_access_end(soc->hal_soc, hal_srng);
  2947. /* Process the reaped descriptors */
  2948. if (head_desc)
  2949. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  2950. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2951. if (!force_break &&
  2952. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2953. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2954. if (!hif_exec_should_yield(soc->hif_handle,
  2955. int_ctx->dp_intr_id))
  2956. goto more_data;
  2957. }
  2958. }
  2959. DP_TX_HIST_STATS_PER_PDEV();
  2960. return num_processed;
  2961. }
  2962. #ifdef FEATURE_WLAN_TDLS
  2963. /**
  2964. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2965. *
  2966. * @data_vdev - which vdev should transmit the tx data frames
  2967. * @tx_spec - what non-standard handling to apply to the tx data frames
  2968. * @msdu_list - NULL-terminated list of tx MSDUs
  2969. *
  2970. * Return: NULL on success,
  2971. * nbuf when it fails to send
  2972. */
  2973. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2974. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2975. {
  2976. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2977. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2978. vdev->is_tdls_frame = true;
  2979. return dp_tx_send(vdev_handle, msdu_list);
  2980. }
  2981. #endif
  2982. /**
  2983. * dp_tx_vdev_attach() - attach vdev to dp tx
  2984. * @vdev: virtual device instance
  2985. *
  2986. * Return: QDF_STATUS_SUCCESS: success
  2987. * QDF_STATUS_E_RESOURCES: Error return
  2988. */
  2989. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2990. {
  2991. /*
  2992. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2993. */
  2994. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2995. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2996. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2997. vdev->vdev_id);
  2998. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2999. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3000. /*
  3001. * Set HTT Extension Valid bit to 0 by default
  3002. */
  3003. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3004. dp_tx_vdev_update_search_flags(vdev);
  3005. return QDF_STATUS_SUCCESS;
  3006. }
  3007. #ifndef FEATURE_WDS
  3008. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3009. {
  3010. return false;
  3011. }
  3012. #endif
  3013. /**
  3014. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3015. * @vdev: virtual device instance
  3016. *
  3017. * Return: void
  3018. *
  3019. */
  3020. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3021. {
  3022. struct dp_soc *soc = vdev->pdev->soc;
  3023. /*
  3024. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3025. * for TDLS link
  3026. *
  3027. * Enable AddrY (SA based search) only for non-WDS STA and
  3028. * ProxySTA VAP (in HKv1) modes.
  3029. *
  3030. * In all other VAP modes, only DA based search should be
  3031. * enabled
  3032. */
  3033. if (vdev->opmode == wlan_op_mode_sta &&
  3034. vdev->tdls_link_connected)
  3035. vdev->hal_desc_addr_search_flags =
  3036. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3037. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3038. !dp_tx_da_search_override(vdev))
  3039. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3040. else
  3041. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3042. /* Set search type only when peer map v2 messaging is enabled
  3043. * as we will have the search index (AST hash) only when v2 is
  3044. * enabled
  3045. */
  3046. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3047. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3048. else
  3049. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3050. }
  3051. static inline bool
  3052. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3053. struct dp_vdev *vdev,
  3054. struct dp_tx_desc_s *tx_desc)
  3055. {
  3056. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3057. return false;
  3058. /*
  3059. * if vdev is given, then only check whether desc
  3060. * vdev match. if vdev is NULL, then check whether
  3061. * desc pdev match.
  3062. */
  3063. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3064. }
  3065. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3066. /**
  3067. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3068. *
  3069. * @soc: Handle to DP SoC structure
  3070. * @tx_desc: pointer of one TX desc
  3071. * @desc_pool_id: TX Desc pool id
  3072. */
  3073. static inline void
  3074. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3075. uint8_t desc_pool_id)
  3076. {
  3077. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3078. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3079. tx_desc->vdev = NULL;
  3080. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3081. }
  3082. /**
  3083. * dp_tx_desc_flush() - release resources associated
  3084. * to TX Desc
  3085. *
  3086. * @dp_pdev: Handle to DP pdev structure
  3087. * @vdev: virtual device instance
  3088. * NULL: no specific Vdev is required and check all allcated TX desc
  3089. * on this pdev.
  3090. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3091. *
  3092. * @force_free:
  3093. * true: flush the TX desc.
  3094. * false: only reset the Vdev in each allocated TX desc
  3095. * that associated to current Vdev.
  3096. *
  3097. * This function will go through the TX desc pool to flush
  3098. * the outstanding TX data or reset Vdev to NULL in associated TX
  3099. * Desc.
  3100. */
  3101. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3102. struct dp_vdev *vdev,
  3103. bool force_free)
  3104. {
  3105. uint8_t i;
  3106. uint32_t j;
  3107. uint32_t num_desc, page_id, offset;
  3108. uint16_t num_desc_per_page;
  3109. struct dp_soc *soc = pdev->soc;
  3110. struct dp_tx_desc_s *tx_desc = NULL;
  3111. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3112. if (!vdev && !force_free) {
  3113. dp_err("Reset TX desc vdev, Vdev param is required!");
  3114. return;
  3115. }
  3116. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3117. tx_desc_pool = &soc->tx_desc[i];
  3118. if (!(tx_desc_pool->pool_size) ||
  3119. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3120. !(tx_desc_pool->desc_pages.cacheable_pages))
  3121. continue;
  3122. num_desc = tx_desc_pool->pool_size;
  3123. num_desc_per_page =
  3124. tx_desc_pool->desc_pages.num_element_per_page;
  3125. for (j = 0; j < num_desc; j++) {
  3126. page_id = j / num_desc_per_page;
  3127. offset = j % num_desc_per_page;
  3128. if (qdf_unlikely(!(tx_desc_pool->
  3129. desc_pages.cacheable_pages)))
  3130. break;
  3131. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3132. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3133. /*
  3134. * Free TX desc if force free is
  3135. * required, otherwise only reset vdev
  3136. * in this TX desc.
  3137. */
  3138. if (force_free) {
  3139. dp_tx_comp_free_buf(soc, tx_desc);
  3140. dp_tx_desc_release(tx_desc, i);
  3141. } else {
  3142. dp_tx_desc_reset_vdev(soc, tx_desc,
  3143. i);
  3144. }
  3145. }
  3146. }
  3147. }
  3148. }
  3149. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3150. static inline void
  3151. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3152. uint8_t desc_pool_id)
  3153. {
  3154. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3155. tx_desc->vdev = NULL;
  3156. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3157. }
  3158. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3159. struct dp_vdev *vdev,
  3160. bool force_free)
  3161. {
  3162. uint8_t i, num_pool;
  3163. uint32_t j;
  3164. uint32_t num_desc, page_id, offset;
  3165. uint16_t num_desc_per_page;
  3166. struct dp_soc *soc = pdev->soc;
  3167. struct dp_tx_desc_s *tx_desc = NULL;
  3168. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3169. if (!vdev && !force_free) {
  3170. dp_err("Reset TX desc vdev, Vdev param is required!");
  3171. return;
  3172. }
  3173. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3174. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3175. for (i = 0; i < num_pool; i++) {
  3176. tx_desc_pool = &soc->tx_desc[i];
  3177. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3178. continue;
  3179. num_desc_per_page =
  3180. tx_desc_pool->desc_pages.num_element_per_page;
  3181. for (j = 0; j < num_desc; j++) {
  3182. page_id = j / num_desc_per_page;
  3183. offset = j % num_desc_per_page;
  3184. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3185. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3186. if (force_free) {
  3187. dp_tx_comp_free_buf(soc, tx_desc);
  3188. dp_tx_desc_release(tx_desc, i);
  3189. } else {
  3190. dp_tx_desc_reset_vdev(soc, tx_desc,
  3191. i);
  3192. }
  3193. }
  3194. }
  3195. }
  3196. }
  3197. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3198. /**
  3199. * dp_tx_vdev_detach() - detach vdev from dp tx
  3200. * @vdev: virtual device instance
  3201. *
  3202. * Return: QDF_STATUS_SUCCESS: success
  3203. * QDF_STATUS_E_RESOURCES: Error return
  3204. */
  3205. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3206. {
  3207. struct dp_pdev *pdev = vdev->pdev;
  3208. /* Reset TX desc associated to this Vdev as NULL */
  3209. dp_tx_desc_flush(pdev, vdev, false);
  3210. return QDF_STATUS_SUCCESS;
  3211. }
  3212. /**
  3213. * dp_tx_pdev_attach() - attach pdev to dp tx
  3214. * @pdev: physical device instance
  3215. *
  3216. * Return: QDF_STATUS_SUCCESS: success
  3217. * QDF_STATUS_E_RESOURCES: Error return
  3218. */
  3219. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3220. {
  3221. struct dp_soc *soc = pdev->soc;
  3222. /* Initialize Flow control counters */
  3223. qdf_atomic_init(&pdev->num_tx_exception);
  3224. qdf_atomic_init(&pdev->num_tx_outstanding);
  3225. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3226. /* Initialize descriptors in TCL Ring */
  3227. hal_tx_init_data_ring(soc->hal_soc,
  3228. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3229. }
  3230. return QDF_STATUS_SUCCESS;
  3231. }
  3232. /**
  3233. * dp_tx_pdev_detach() - detach pdev from dp tx
  3234. * @pdev: physical device instance
  3235. *
  3236. * Return: QDF_STATUS_SUCCESS: success
  3237. * QDF_STATUS_E_RESOURCES: Error return
  3238. */
  3239. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3240. {
  3241. /* flush TX outstanding data per pdev */
  3242. dp_tx_desc_flush(pdev, NULL, true);
  3243. dp_tx_me_exit(pdev);
  3244. return QDF_STATUS_SUCCESS;
  3245. }
  3246. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3247. /* Pools will be allocated dynamically */
  3248. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3249. int num_desc)
  3250. {
  3251. uint8_t i;
  3252. for (i = 0; i < num_pool; i++) {
  3253. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3254. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3255. }
  3256. return 0;
  3257. }
  3258. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3259. {
  3260. uint8_t i;
  3261. for (i = 0; i < num_pool; i++)
  3262. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3263. }
  3264. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3265. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3266. int num_desc)
  3267. {
  3268. uint8_t i;
  3269. /* Allocate software Tx descriptor pools */
  3270. for (i = 0; i < num_pool; i++) {
  3271. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3273. "%s Tx Desc Pool alloc %d failed %pK",
  3274. __func__, i, soc);
  3275. return ENOMEM;
  3276. }
  3277. }
  3278. return 0;
  3279. }
  3280. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3281. {
  3282. uint8_t i;
  3283. for (i = 0; i < num_pool; i++) {
  3284. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3285. if (dp_tx_desc_pool_free(soc, i)) {
  3286. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3287. "%s Tx Desc Pool Free failed", __func__);
  3288. }
  3289. }
  3290. }
  3291. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3292. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3293. /**
  3294. * dp_tso_attach_wifi3() - TSO attach handler
  3295. * @txrx_soc: Opaque Dp handle
  3296. *
  3297. * Reserve TSO descriptor buffers
  3298. *
  3299. * Return: QDF_STATUS_E_FAILURE on failure or
  3300. * QDF_STATUS_SUCCESS on success
  3301. */
  3302. static
  3303. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3304. {
  3305. return dp_tso_soc_attach(txrx_soc);
  3306. }
  3307. /**
  3308. * dp_tso_detach_wifi3() - TSO Detach handler
  3309. * @txrx_soc: Opaque Dp handle
  3310. *
  3311. * Deallocate TSO descriptor buffers
  3312. *
  3313. * Return: QDF_STATUS_E_FAILURE on failure or
  3314. * QDF_STATUS_SUCCESS on success
  3315. */
  3316. static
  3317. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3318. {
  3319. return dp_tso_soc_detach(txrx_soc);
  3320. }
  3321. #else
  3322. static
  3323. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3324. {
  3325. return QDF_STATUS_SUCCESS;
  3326. }
  3327. static
  3328. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3329. {
  3330. return QDF_STATUS_SUCCESS;
  3331. }
  3332. #endif
  3333. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3334. {
  3335. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3336. uint8_t i;
  3337. uint8_t num_pool;
  3338. uint32_t num_desc;
  3339. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3340. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3341. for (i = 0; i < num_pool; i++)
  3342. dp_tx_tso_desc_pool_free(soc, i);
  3343. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3344. __func__, num_pool, num_desc);
  3345. for (i = 0; i < num_pool; i++)
  3346. dp_tx_tso_num_seg_pool_free(soc, i);
  3347. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3348. __func__, num_pool, num_desc);
  3349. return QDF_STATUS_SUCCESS;
  3350. }
  3351. /**
  3352. * dp_tso_attach() - TSO attach handler
  3353. * @txrx_soc: Opaque Dp handle
  3354. *
  3355. * Reserve TSO descriptor buffers
  3356. *
  3357. * Return: QDF_STATUS_E_FAILURE on failure or
  3358. * QDF_STATUS_SUCCESS on success
  3359. */
  3360. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3361. {
  3362. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3363. uint8_t i;
  3364. uint8_t num_pool;
  3365. uint32_t num_desc;
  3366. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3367. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3368. for (i = 0; i < num_pool; i++) {
  3369. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3370. dp_err("TSO Desc Pool alloc %d failed %pK",
  3371. i, soc);
  3372. return QDF_STATUS_E_FAILURE;
  3373. }
  3374. }
  3375. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3376. __func__, num_pool, num_desc);
  3377. for (i = 0; i < num_pool; i++) {
  3378. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3379. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3380. i, soc);
  3381. return QDF_STATUS_E_FAILURE;
  3382. }
  3383. }
  3384. return QDF_STATUS_SUCCESS;
  3385. }
  3386. /**
  3387. * dp_tx_soc_detach() - detach soc from dp tx
  3388. * @soc: core txrx main context
  3389. *
  3390. * This function will detach dp tx into main device context
  3391. * will free dp tx resource and initialize resources
  3392. *
  3393. * Return: QDF_STATUS_SUCCESS: success
  3394. * QDF_STATUS_E_RESOURCES: Error return
  3395. */
  3396. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3397. {
  3398. uint8_t num_pool;
  3399. uint16_t num_desc;
  3400. uint16_t num_ext_desc;
  3401. uint8_t i;
  3402. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3403. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3404. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3405. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3406. dp_tx_flow_control_deinit(soc);
  3407. dp_tx_delete_static_pools(soc, num_pool);
  3408. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3409. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3410. __func__, num_pool, num_desc);
  3411. for (i = 0; i < num_pool; i++) {
  3412. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3413. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3414. "%s Tx Ext Desc Pool Free failed",
  3415. __func__);
  3416. return QDF_STATUS_E_RESOURCES;
  3417. }
  3418. }
  3419. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3420. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3421. __func__, num_pool, num_ext_desc);
  3422. status = dp_tso_detach_wifi3(soc);
  3423. if (status != QDF_STATUS_SUCCESS)
  3424. return status;
  3425. return QDF_STATUS_SUCCESS;
  3426. }
  3427. /**
  3428. * dp_tx_soc_attach() - attach soc to dp tx
  3429. * @soc: core txrx main context
  3430. *
  3431. * This function will attach dp tx into main device context
  3432. * will allocate dp tx resource and initialize resources
  3433. *
  3434. * Return: QDF_STATUS_SUCCESS: success
  3435. * QDF_STATUS_E_RESOURCES: Error return
  3436. */
  3437. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3438. {
  3439. uint8_t i;
  3440. uint8_t num_pool;
  3441. uint32_t num_desc;
  3442. uint32_t num_ext_desc;
  3443. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3444. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3445. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3446. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3447. if (num_pool > MAX_TXDESC_POOLS)
  3448. goto fail;
  3449. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3450. goto fail;
  3451. dp_tx_flow_control_init(soc);
  3452. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3453. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3454. __func__, num_pool, num_desc);
  3455. /* Allocate extension tx descriptor pools */
  3456. for (i = 0; i < num_pool; i++) {
  3457. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3458. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3459. "MSDU Ext Desc Pool alloc %d failed %pK",
  3460. i, soc);
  3461. goto fail;
  3462. }
  3463. }
  3464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3465. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3466. __func__, num_pool, num_ext_desc);
  3467. status = dp_tso_attach_wifi3((void *)soc);
  3468. if (status != QDF_STATUS_SUCCESS)
  3469. goto fail;
  3470. /* Initialize descriptors in TCL Rings */
  3471. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3472. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3473. hal_tx_init_data_ring(soc->hal_soc,
  3474. soc->tcl_data_ring[i].hal_srng);
  3475. }
  3476. }
  3477. /*
  3478. * todo - Add a runtime config option to enable this.
  3479. */
  3480. /*
  3481. * Due to multiple issues on NPR EMU, enable it selectively
  3482. * only for NPR EMU, should be removed, once NPR platforms
  3483. * are stable.
  3484. */
  3485. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3486. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3487. "%s HAL Tx init Success", __func__);
  3488. return QDF_STATUS_SUCCESS;
  3489. fail:
  3490. /* Detach will take care of freeing only allocated resources */
  3491. dp_tx_soc_detach(soc);
  3492. return QDF_STATUS_E_RESOURCES;
  3493. }