sde_kms.c 93 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <drm/drm_atomic_uapi.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "dp_mst_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_reg_dma.h"
  45. #include "sde_connector.h"
  46. #include <linux/qcom_scm.h>
  47. #include "soc/qcom/secure_buffer.h"
  48. #include <linux/qtee_shmbridge.h>
  49. #define CREATE_TRACE_POINTS
  50. #include "sde_trace.h"
  51. /* defines for secure channel call */
  52. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  53. #define MDP_DEVICE_ID 0x1A
  54. EXPORT_TRACEPOINT_SYMBOL(sde_drm_tracing_mark_write);
  55. static const char * const iommu_ports[] = {
  56. "mdp_0",
  57. };
  58. /**
  59. * Controls size of event log buffer. Specified as a power of 2.
  60. */
  61. #define SDE_EVTLOG_SIZE 1024
  62. /*
  63. * To enable overall DRM driver logging
  64. * # echo 0x2 > /sys/module/drm/parameters/debug
  65. *
  66. * To enable DRM driver h/w logging
  67. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  68. *
  69. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  70. */
  71. #define SDE_DEBUGFS_DIR "msm_sde"
  72. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  73. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  74. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  75. /**
  76. * sdecustom - enable certain driver customizations for sde clients
  77. * Enabling this modifies the standard DRM behavior slightly and assumes
  78. * that the clients have specific knowledge about the modifications that
  79. * are involved, so don't enable this unless you know what you're doing.
  80. *
  81. * Parts of the driver that are affected by this setting may be located by
  82. * searching for invocations of the 'sde_is_custom_client()' function.
  83. *
  84. * This is disabled by default.
  85. */
  86. static bool sdecustom = true;
  87. module_param(sdecustom, bool, 0400);
  88. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  89. static int sde_kms_hw_init(struct msm_kms *kms);
  90. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  91. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  92. static int _sde_kms_register_events(struct msm_kms *kms,
  93. struct drm_mode_object *obj, u32 event, bool en);
  94. bool sde_is_custom_client(void)
  95. {
  96. return sdecustom;
  97. }
  98. #ifdef CONFIG_DEBUG_FS
  99. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  100. {
  101. struct msm_drm_private *priv;
  102. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  103. return NULL;
  104. priv = sde_kms->dev->dev_private;
  105. return priv->debug_root;
  106. }
  107. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  108. {
  109. void *p;
  110. int rc;
  111. void *debugfs_root;
  112. p = sde_hw_util_get_log_mask_ptr();
  113. if (!sde_kms || !p)
  114. return -EINVAL;
  115. debugfs_root = sde_debugfs_get_root(sde_kms);
  116. if (!debugfs_root)
  117. return -EINVAL;
  118. /* allow debugfs_root to be NULL */
  119. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  120. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  121. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  122. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  123. if (rc) {
  124. SDE_ERROR("failed to init perf %d\n", rc);
  125. return rc;
  126. }
  127. if (sde_kms->catalog->qdss_count)
  128. debugfs_create_u32("qdss", 0600, debugfs_root,
  129. (u32 *)&sde_kms->qdss_enabled);
  130. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  131. (u32 *)&sde_kms->pm_suspend_clk_dump);
  132. return 0;
  133. }
  134. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  135. {
  136. /* don't need to NULL check debugfs_root */
  137. if (sde_kms) {
  138. sde_debugfs_vbif_destroy(sde_kms);
  139. sde_debugfs_core_irq_destroy(sde_kms);
  140. }
  141. }
  142. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  143. {
  144. int i;
  145. struct device *dev = sde_kms->dev->dev;
  146. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  147. for (i = 0; i < sde_kms->dsi_display_count; i++)
  148. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  149. return 0;
  150. }
  151. #else
  152. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  153. {
  154. return 0;
  155. }
  156. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  157. {
  158. }
  159. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  160. {
  161. return 0;
  162. }
  163. #endif
  164. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  165. {
  166. int ret = 0;
  167. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  168. ret = sde_crtc_vblank(crtc, true);
  169. SDE_ATRACE_END("sde_kms_enable_vblank");
  170. return ret;
  171. }
  172. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  173. {
  174. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  175. sde_crtc_vblank(crtc, false);
  176. SDE_ATRACE_END("sde_kms_disable_vblank");
  177. }
  178. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  179. struct drm_crtc *crtc)
  180. {
  181. struct drm_encoder *encoder;
  182. struct drm_device *dev;
  183. int ret;
  184. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  185. SDE_ERROR("invalid params\n");
  186. return;
  187. }
  188. if (!crtc->state->enable) {
  189. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  190. return;
  191. }
  192. if (!crtc->state->active) {
  193. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  194. return;
  195. }
  196. dev = crtc->dev;
  197. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  198. if (encoder->crtc != crtc)
  199. continue;
  200. /*
  201. * Video Mode - Wait for VSYNC
  202. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  203. * complete
  204. */
  205. SDE_EVT32_VERBOSE(DRMID(crtc));
  206. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  207. if (ret && ret != -EWOULDBLOCK) {
  208. SDE_ERROR(
  209. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  210. crtc->base.id, encoder->base.id, ret);
  211. break;
  212. }
  213. }
  214. }
  215. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  216. struct drm_crtc *crtc, bool enable)
  217. {
  218. struct drm_device *dev;
  219. struct msm_drm_private *priv;
  220. struct sde_mdss_cfg *sde_cfg;
  221. struct drm_plane *plane;
  222. int i, ret;
  223. dev = sde_kms->dev;
  224. priv = dev->dev_private;
  225. sde_cfg = sde_kms->catalog;
  226. ret = sde_vbif_halt_xin_mask(sde_kms,
  227. sde_cfg->sui_block_xin_mask, enable);
  228. if (ret) {
  229. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  230. return ret;
  231. }
  232. if (enable) {
  233. for (i = 0; i < priv->num_planes; i++) {
  234. plane = priv->planes[i];
  235. sde_plane_secure_ctrl_xin_client(plane, crtc);
  236. }
  237. }
  238. return 0;
  239. }
  240. /**
  241. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  242. * @sde_kms: Pointer to sde_kms struct
  243. * @vimd: switch the stage 2 translation to this VMID
  244. */
  245. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  246. {
  247. struct device dummy = {};
  248. dma_addr_t dma_handle;
  249. uint32_t num_sids;
  250. uint32_t *sec_sid;
  251. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  252. int ret = 0, i;
  253. struct qtee_shm shm;
  254. bool qtee_en = qtee_shmbridge_is_enabled();
  255. phys_addr_t mem_addr;
  256. u64 mem_size;
  257. num_sids = sde_cfg->sec_sid_mask_count;
  258. if (!num_sids) {
  259. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  260. return -EINVAL;
  261. }
  262. if (qtee_en) {
  263. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  264. &shm);
  265. if (ret)
  266. return -ENOMEM;
  267. sec_sid = (uint32_t *) shm.vaddr;
  268. mem_addr = shm.paddr;
  269. /**
  270. * SMMUSecureModeSwitch requires the size to be number of SID's
  271. * but shm allocates size in pages. Modify the args as per
  272. * client requirement.
  273. */
  274. mem_size = sizeof(uint32_t) * num_sids;
  275. } else {
  276. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  277. if (!sec_sid)
  278. return -ENOMEM;
  279. mem_addr = virt_to_phys(sec_sid);
  280. mem_size = sizeof(uint32_t) * num_sids;
  281. }
  282. for (i = 0; i < num_sids; i++) {
  283. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  284. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  285. }
  286. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  287. if (ret) {
  288. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  289. goto map_error;
  290. }
  291. set_dma_ops(&dummy, NULL);
  292. dma_handle = dma_map_single(&dummy, sec_sid,
  293. num_sids *sizeof(uint32_t), DMA_TO_DEVICE);
  294. if (dma_mapping_error(&dummy, dma_handle)) {
  295. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  296. vmid);
  297. goto map_error;
  298. }
  299. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  300. vmid, num_sids, qtee_en);
  301. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  302. mem_size, vmid);
  303. if (ret)
  304. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  305. vmid, ret);
  306. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  307. vmid, qtee_en, num_sids, ret);
  308. dma_unmap_single(&dummy, dma_handle,
  309. num_sids *sizeof(uint32_t), DMA_TO_DEVICE);
  310. map_error:
  311. if (qtee_en)
  312. qtee_shmbridge_free_shm(&shm);
  313. else
  314. kfree(sec_sid);
  315. return ret;
  316. }
  317. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  318. {
  319. u32 ret;
  320. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  321. return 0;
  322. /* detach_all_contexts */
  323. ret = sde_kms_mmu_detach(sde_kms, false);
  324. if (ret) {
  325. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  326. goto mmu_error;
  327. }
  328. ret = _sde_kms_scm_call(sde_kms, vmid);
  329. if (ret) {
  330. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  331. goto scm_error;
  332. }
  333. return 0;
  334. scm_error:
  335. sde_kms_mmu_attach(sde_kms, false);
  336. mmu_error:
  337. atomic_dec(&sde_kms->detach_all_cb);
  338. return ret;
  339. }
  340. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  341. u32 old_vmid)
  342. {
  343. u32 ret;
  344. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  345. return 0;
  346. ret = _sde_kms_scm_call(sde_kms, vmid);
  347. if (ret) {
  348. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  349. goto scm_error;
  350. }
  351. /* attach_all_contexts */
  352. ret = sde_kms_mmu_attach(sde_kms, false);
  353. if (ret) {
  354. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  355. goto mmu_error;
  356. }
  357. return 0;
  358. mmu_error:
  359. _sde_kms_scm_call(sde_kms, old_vmid);
  360. scm_error:
  361. atomic_inc(&sde_kms->detach_all_cb);
  362. return ret;
  363. }
  364. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  365. {
  366. u32 ret;
  367. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  368. return 0;
  369. /* detach secure_context */
  370. ret = sde_kms_mmu_detach(sde_kms, true);
  371. if (ret) {
  372. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  373. goto mmu_error;
  374. }
  375. ret = _sde_kms_scm_call(sde_kms, vmid);
  376. if (ret) {
  377. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  378. goto scm_error;
  379. }
  380. return 0;
  381. scm_error:
  382. sde_kms_mmu_attach(sde_kms, true);
  383. mmu_error:
  384. atomic_dec(&sde_kms->detach_sec_cb);
  385. return ret;
  386. }
  387. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  388. u32 old_vmid)
  389. {
  390. u32 ret;
  391. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  392. return 0;
  393. ret = _sde_kms_scm_call(sde_kms, vmid);
  394. if (ret) {
  395. goto scm_error;
  396. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  397. }
  398. ret = sde_kms_mmu_attach(sde_kms, true);
  399. if (ret) {
  400. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  401. goto mmu_error;
  402. }
  403. return 0;
  404. mmu_error:
  405. _sde_kms_scm_call(sde_kms, old_vmid);
  406. scm_error:
  407. atomic_inc(&sde_kms->detach_sec_cb);
  408. return ret;
  409. }
  410. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  411. struct drm_crtc *crtc, bool enable)
  412. {
  413. int ret;
  414. if (enable) {
  415. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  416. if (ret < 0) {
  417. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  418. return ret;
  419. }
  420. sde_crtc_misr_setup(crtc, true, 1);
  421. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  422. if (ret) {
  423. sde_crtc_misr_setup(crtc, false, 0);
  424. pm_runtime_put_sync(sde_kms->dev->dev);
  425. return ret;
  426. }
  427. } else {
  428. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  429. sde_crtc_misr_setup(crtc, false, 0);
  430. pm_runtime_put_sync(sde_kms->dev->dev);
  431. }
  432. return 0;
  433. }
  434. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  435. bool post_commit)
  436. {
  437. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  438. int old_smmu_state = smmu_state->state;
  439. int ret = 0;
  440. u32 vmid;
  441. if (!sde_kms || !crtc) {
  442. SDE_ERROR("invalid argument(s)\n");
  443. return -EINVAL;
  444. }
  445. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  446. post_commit, smmu_state->sui_misr_state,
  447. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  448. if ((!smmu_state->transition_type) ||
  449. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  450. /* Bail out */
  451. return 0;
  452. /* enable sui misr if requested, before the transition */
  453. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  454. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  455. if (ret) {
  456. smmu_state->sui_misr_state = NONE;
  457. goto end;
  458. }
  459. }
  460. mutex_lock(&sde_kms->secure_transition_lock);
  461. switch (smmu_state->state) {
  462. case DETACH_ALL_REQ:
  463. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  464. if (!ret)
  465. smmu_state->state = DETACHED;
  466. break;
  467. case ATTACH_ALL_REQ:
  468. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  469. VMID_CP_SEC_DISPLAY);
  470. if (!ret) {
  471. smmu_state->state = ATTACHED;
  472. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  473. }
  474. break;
  475. case DETACH_SEC_REQ:
  476. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  477. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  478. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  479. if (!ret)
  480. smmu_state->state = DETACHED_SEC;
  481. break;
  482. case ATTACH_SEC_REQ:
  483. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  484. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  485. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  486. if (!ret) {
  487. smmu_state->state = ATTACHED;
  488. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  489. }
  490. break;
  491. default:
  492. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  493. DRMID(crtc), smmu_state->state,
  494. smmu_state->transition_type);
  495. ret = -EINVAL;
  496. break;
  497. }
  498. mutex_unlock(&sde_kms->secure_transition_lock);
  499. /* disable sui misr if requested, after the transition */
  500. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  501. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  502. if (ret)
  503. goto end;
  504. }
  505. end:
  506. smmu_state->transition_error = false;
  507. if (ret) {
  508. smmu_state->transition_error = true;
  509. SDE_ERROR(
  510. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  511. DRMID(crtc), old_smmu_state, smmu_state->state,
  512. smmu_state->secure_level, ret);
  513. smmu_state->state = smmu_state->prev_state;
  514. smmu_state->secure_level = smmu_state->prev_secure_level;
  515. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  516. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  517. }
  518. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  519. DRMID(crtc), old_smmu_state, smmu_state->state,
  520. smmu_state->secure_level, ret);
  521. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  522. smmu_state->transition_type,
  523. smmu_state->transition_error,
  524. smmu_state->secure_level, smmu_state->prev_secure_level,
  525. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  526. smmu_state->sui_misr_state = NONE;
  527. smmu_state->transition_type = NONE;
  528. return ret;
  529. }
  530. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  531. struct drm_atomic_state *state)
  532. {
  533. struct drm_crtc *crtc;
  534. struct drm_crtc_state *old_crtc_state;
  535. struct drm_plane_state *old_plane_state, *new_plane_state;
  536. struct drm_plane *plane;
  537. struct drm_plane_state *plane_state;
  538. struct sde_kms *sde_kms = to_sde_kms(kms);
  539. struct drm_device *dev = sde_kms->dev;
  540. int i, ops = 0, ret = 0;
  541. bool old_valid_fb = false;
  542. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  543. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  544. if (!crtc->state || !crtc->state->active)
  545. continue;
  546. /*
  547. * It is safe to assume only one active crtc,
  548. * and compatible translation modes on the
  549. * planes staged on this crtc.
  550. * otherwise validation would have failed.
  551. * For this CRTC,
  552. */
  553. /*
  554. * 1. Check if old state on the CRTC has planes
  555. * staged with valid fbs
  556. */
  557. for_each_old_plane_in_state(state, plane, plane_state, i) {
  558. if (!plane_state->crtc)
  559. continue;
  560. if (plane_state->fb) {
  561. old_valid_fb = true;
  562. break;
  563. }
  564. }
  565. /*
  566. * 2.Get the operations needed to be performed before
  567. * secure transition can be initiated.
  568. */
  569. ops = sde_crtc_get_secure_transition_ops(crtc,
  570. old_crtc_state, old_valid_fb);
  571. if (ops < 0) {
  572. SDE_ERROR("invalid secure operations %x\n", ops);
  573. return ops;
  574. }
  575. if (!ops) {
  576. smmu_state->transition_error = false;
  577. goto no_ops;
  578. }
  579. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  580. crtc->base.id, ops, crtc->state);
  581. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  582. /* 3. Perform operations needed for secure transition */
  583. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  584. SDE_DEBUG("wait_for_transfer_done\n");
  585. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  586. }
  587. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  588. SDE_DEBUG("cleanup planes\n");
  589. drm_atomic_helper_cleanup_planes(dev, state);
  590. for_each_oldnew_plane_in_state(state, plane,
  591. old_plane_state, new_plane_state, i)
  592. sde_plane_destroy_fb(old_plane_state);
  593. }
  594. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  595. SDE_DEBUG("secure ctrl\n");
  596. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  597. }
  598. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  599. SDE_DEBUG("prepare planes %d",
  600. crtc->state->plane_mask);
  601. drm_atomic_crtc_for_each_plane(plane,
  602. crtc) {
  603. const struct drm_plane_helper_funcs *funcs;
  604. plane_state = plane->state;
  605. funcs = plane->helper_private;
  606. SDE_DEBUG("psde:%d FB[%u]\n",
  607. plane->base.id,
  608. plane->fb->base.id);
  609. if (!funcs)
  610. continue;
  611. if (funcs->prepare_fb(plane, plane_state)) {
  612. ret = funcs->prepare_fb(plane,
  613. plane_state);
  614. if (ret)
  615. return ret;
  616. }
  617. }
  618. }
  619. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  620. SDE_DEBUG("secure operations completed\n");
  621. }
  622. no_ops:
  623. return 0;
  624. }
  625. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  626. unsigned int splash_buffer_size,
  627. unsigned int ramdump_base,
  628. unsigned int ramdump_buffer_size)
  629. {
  630. unsigned long pfn_start, pfn_end, pfn_idx;
  631. int ret = 0;
  632. if (!mem_addr || !splash_buffer_size) {
  633. SDE_ERROR("invalid params\n");
  634. return -EINVAL;
  635. }
  636. /* leave ramdump memory only if base address matches */
  637. if (ramdump_base == mem_addr &&
  638. ramdump_buffer_size <= splash_buffer_size) {
  639. mem_addr += ramdump_buffer_size;
  640. splash_buffer_size -= ramdump_buffer_size;
  641. }
  642. pfn_start = mem_addr >> PAGE_SHIFT;
  643. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  644. if (ret) {
  645. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  646. return ret;
  647. }
  648. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  649. free_reserved_page(pfn_to_page(pfn_idx));
  650. return ret;
  651. }
  652. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  653. struct sde_splash_mem *splash)
  654. {
  655. struct msm_mmu *mmu = NULL;
  656. int ret = 0;
  657. if (!sde_kms->aspace[0]) {
  658. SDE_ERROR("aspace not found for sde kms node\n");
  659. return -EINVAL;
  660. }
  661. mmu = sde_kms->aspace[0]->mmu;
  662. if (!mmu) {
  663. SDE_ERROR("mmu not found for aspace\n");
  664. return -EINVAL;
  665. }
  666. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  667. SDE_ERROR("invalid input params for map\n");
  668. return -EINVAL;
  669. }
  670. if (!splash->ref_cnt) {
  671. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  672. splash->splash_buf_base,
  673. splash->splash_buf_size,
  674. IOMMU_READ | IOMMU_NOEXEC);
  675. if (ret)
  676. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  677. }
  678. splash->ref_cnt++;
  679. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  680. splash->splash_buf_base,
  681. splash->splash_buf_size,
  682. splash->ref_cnt);
  683. return ret;
  684. }
  685. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  686. {
  687. int i = 0;
  688. int ret = 0;
  689. if (!sde_kms)
  690. return -EINVAL;
  691. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  692. ret = _sde_kms_splash_mem_get(sde_kms,
  693. sde_kms->splash_data.splash_display[i].splash);
  694. if (ret)
  695. return ret;
  696. }
  697. return ret;
  698. }
  699. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  700. struct sde_splash_mem *splash)
  701. {
  702. struct msm_mmu *mmu = NULL;
  703. int rc = 0;
  704. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  705. SDE_ERROR("invalid params\n");
  706. return -EINVAL;
  707. }
  708. mmu = sde_kms->aspace[0]->mmu;
  709. if (!splash || !splash->ref_cnt ||
  710. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  711. return -EINVAL;
  712. splash->ref_cnt--;
  713. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  714. splash->splash_buf_base, splash->ref_cnt);
  715. if (!splash->ref_cnt) {
  716. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  717. splash->splash_buf_size);
  718. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  719. splash->splash_buf_size, splash->ramdump_base,
  720. splash->ramdump_size);
  721. splash->splash_buf_base = 0;
  722. splash->splash_buf_size = 0;
  723. }
  724. return rc;
  725. }
  726. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  727. {
  728. int i = 0;
  729. int ret = 0;
  730. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  731. return -EINVAL;
  732. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  733. ret = _sde_kms_splash_mem_put(sde_kms,
  734. sde_kms->splash_data.splash_display[i].splash);
  735. if (ret)
  736. return ret;
  737. }
  738. return ret;
  739. }
  740. static void sde_kms_prepare_commit(struct msm_kms *kms,
  741. struct drm_atomic_state *state)
  742. {
  743. struct sde_kms *sde_kms;
  744. struct msm_drm_private *priv;
  745. struct drm_device *dev;
  746. struct drm_encoder *encoder;
  747. struct drm_crtc *crtc;
  748. struct drm_crtc_state *crtc_state;
  749. int i, rc;
  750. if (!kms)
  751. return;
  752. sde_kms = to_sde_kms(kms);
  753. dev = sde_kms->dev;
  754. if (!dev || !dev->dev_private)
  755. return;
  756. priv = dev->dev_private;
  757. SDE_ATRACE_BEGIN("prepare_commit");
  758. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  759. if (rc < 0) {
  760. SDE_ERROR("failed to enable power resources %d\n", rc);
  761. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  762. goto end;
  763. }
  764. if (sde_kms->first_kickoff) {
  765. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  766. sde_kms->first_kickoff = false;
  767. }
  768. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  769. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  770. head) {
  771. if (encoder->crtc != crtc)
  772. continue;
  773. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  774. SDE_ERROR("crtc:%d, initiating hw reset\n",
  775. DRMID(crtc));
  776. sde_encoder_needs_hw_reset(encoder);
  777. sde_crtc_set_needs_hw_reset(crtc);
  778. }
  779. }
  780. }
  781. /*
  782. * NOTE: for secure use cases we want to apply the new HW
  783. * configuration only after completing preparation for secure
  784. * transitions prepare below if any transtions is required.
  785. */
  786. sde_kms_prepare_secure_transition(kms, state);
  787. end:
  788. SDE_ATRACE_END("prepare_commit");
  789. }
  790. static void sde_kms_commit(struct msm_kms *kms,
  791. struct drm_atomic_state *old_state)
  792. {
  793. struct sde_kms *sde_kms;
  794. struct drm_crtc *crtc;
  795. struct drm_crtc_state *old_crtc_state;
  796. int i;
  797. if (!kms || !old_state)
  798. return;
  799. sde_kms = to_sde_kms(kms);
  800. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  801. SDE_ERROR("power resource is not enabled\n");
  802. return;
  803. }
  804. SDE_ATRACE_BEGIN("sde_kms_commit");
  805. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  806. if (crtc->state->active) {
  807. SDE_EVT32(DRMID(crtc));
  808. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  809. }
  810. }
  811. SDE_ATRACE_END("sde_kms_commit");
  812. }
  813. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  814. struct sde_splash_display *splash_display)
  815. {
  816. if (!sde_kms || !splash_display ||
  817. !sde_kms->splash_data.num_splash_displays)
  818. return;
  819. if (sde_kms->splash_data.num_splash_regions)
  820. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  821. sde_kms->splash_data.num_splash_displays--;
  822. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  823. sde_kms->splash_data.num_splash_displays);
  824. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  825. }
  826. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  827. struct drm_crtc *crtc)
  828. {
  829. struct msm_drm_private *priv;
  830. struct sde_splash_display *splash_display;
  831. int i;
  832. if (!sde_kms || !crtc)
  833. return;
  834. priv = sde_kms->dev->dev_private;
  835. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  836. return;
  837. SDE_EVT32(DRMID(crtc), crtc->state->active,
  838. sde_kms->splash_data.num_splash_displays);
  839. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  840. splash_display = &sde_kms->splash_data.splash_display[i];
  841. if (splash_display->encoder &&
  842. crtc == splash_display->encoder->crtc)
  843. break;
  844. }
  845. if (i >= MAX_DSI_DISPLAYS)
  846. return;
  847. if (splash_display->cont_splash_enabled) {
  848. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  849. splash_display, false);
  850. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  851. }
  852. /* remove the votes if all displays are done with splash */
  853. if (!sde_kms->splash_data.num_splash_displays) {
  854. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  855. sde_power_data_bus_set_quota(&priv->phandle, i,
  856. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  857. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  858. pm_runtime_put_sync(sde_kms->dev->dev);
  859. }
  860. }
  861. static void sde_kms_complete_commit(struct msm_kms *kms,
  862. struct drm_atomic_state *old_state)
  863. {
  864. struct sde_kms *sde_kms;
  865. struct msm_drm_private *priv;
  866. struct drm_crtc *crtc;
  867. struct drm_crtc_state *old_crtc_state;
  868. struct drm_connector *connector;
  869. struct drm_connector_state *old_conn_state;
  870. struct msm_display_conn_params params;
  871. int i, rc = 0;
  872. if (!kms || !old_state)
  873. return;
  874. sde_kms = to_sde_kms(kms);
  875. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  876. return;
  877. priv = sde_kms->dev->dev_private;
  878. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  879. SDE_ERROR("power resource is not enabled\n");
  880. return;
  881. }
  882. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  883. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  884. sde_crtc_complete_commit(crtc, old_crtc_state);
  885. /* complete secure transitions if any */
  886. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  887. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  888. }
  889. for_each_old_connector_in_state(old_state, connector,
  890. old_conn_state, i) {
  891. struct sde_connector *c_conn;
  892. c_conn = to_sde_connector(connector);
  893. if (!c_conn->ops.post_kickoff)
  894. continue;
  895. memset(&params, 0, sizeof(params));
  896. sde_connector_complete_qsync_commit(connector, &params);
  897. rc = c_conn->ops.post_kickoff(connector, &params);
  898. if (rc) {
  899. pr_err("Connector Post kickoff failed rc=%d\n",
  900. rc);
  901. }
  902. }
  903. pm_runtime_put_sync(sde_kms->dev->dev);
  904. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  905. _sde_kms_release_splash_resource(sde_kms, crtc);
  906. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  907. SDE_ATRACE_END("sde_kms_complete_commit");
  908. }
  909. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  910. struct drm_crtc *crtc)
  911. {
  912. struct drm_encoder *encoder;
  913. struct drm_device *dev;
  914. int ret;
  915. if (!kms || !crtc || !crtc->state) {
  916. SDE_ERROR("invalid params\n");
  917. return;
  918. }
  919. dev = crtc->dev;
  920. if (!crtc->state->enable) {
  921. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  922. return;
  923. }
  924. if (!crtc->state->active) {
  925. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  926. return;
  927. }
  928. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  929. SDE_ERROR("power resource is not enabled\n");
  930. return;
  931. }
  932. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  933. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  934. if (encoder->crtc != crtc)
  935. continue;
  936. /*
  937. * Wait for post-flush if necessary to delay before
  938. * plane_cleanup. For example, wait for vsync in case of video
  939. * mode panels. This may be a no-op for command mode panels.
  940. */
  941. SDE_EVT32_VERBOSE(DRMID(crtc));
  942. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  943. if (ret && ret != -EWOULDBLOCK) {
  944. SDE_ERROR("wait for commit done returned %d\n", ret);
  945. sde_crtc_request_frame_reset(crtc);
  946. break;
  947. }
  948. sde_crtc_complete_flip(crtc, NULL);
  949. }
  950. sde_crtc_static_cache_read_kickoff(crtc);
  951. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  952. }
  953. static void sde_kms_prepare_fence(struct msm_kms *kms,
  954. struct drm_atomic_state *old_state)
  955. {
  956. struct drm_crtc *crtc;
  957. struct drm_crtc_state *old_crtc_state;
  958. int i, rc;
  959. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  960. SDE_ERROR("invalid argument(s)\n");
  961. return;
  962. }
  963. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  964. retry:
  965. /* attempt to acquire ww mutex for connection */
  966. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  967. old_state->acquire_ctx);
  968. if (rc == -EDEADLK) {
  969. drm_modeset_backoff(old_state->acquire_ctx);
  970. goto retry;
  971. }
  972. /* old_state actually contains updated crtc pointers */
  973. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  974. if (crtc->state->active || crtc->state->active_changed)
  975. sde_crtc_prepare_commit(crtc, old_crtc_state);
  976. }
  977. SDE_ATRACE_END("sde_kms_prepare_fence");
  978. }
  979. /**
  980. * _sde_kms_get_displays - query for underlying display handles and cache them
  981. * @sde_kms: Pointer to sde kms structure
  982. * Returns: Zero on success
  983. */
  984. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  985. {
  986. int rc = -ENOMEM;
  987. if (!sde_kms) {
  988. SDE_ERROR("invalid sde kms\n");
  989. return -EINVAL;
  990. }
  991. /* dsi */
  992. sde_kms->dsi_displays = NULL;
  993. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  994. if (sde_kms->dsi_display_count) {
  995. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  996. sizeof(void *),
  997. GFP_KERNEL);
  998. if (!sde_kms->dsi_displays) {
  999. SDE_ERROR("failed to allocate dsi displays\n");
  1000. goto exit_deinit_dsi;
  1001. }
  1002. sde_kms->dsi_display_count =
  1003. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1004. sde_kms->dsi_display_count);
  1005. }
  1006. /* wb */
  1007. sde_kms->wb_displays = NULL;
  1008. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1009. if (sde_kms->wb_display_count) {
  1010. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1011. sizeof(void *),
  1012. GFP_KERNEL);
  1013. if (!sde_kms->wb_displays) {
  1014. SDE_ERROR("failed to allocate wb displays\n");
  1015. goto exit_deinit_wb;
  1016. }
  1017. sde_kms->wb_display_count =
  1018. wb_display_get_displays(sde_kms->wb_displays,
  1019. sde_kms->wb_display_count);
  1020. }
  1021. /* dp */
  1022. sde_kms->dp_displays = NULL;
  1023. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1024. if (sde_kms->dp_display_count) {
  1025. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1026. sizeof(void *), GFP_KERNEL);
  1027. if (!sde_kms->dp_displays) {
  1028. SDE_ERROR("failed to allocate dp displays\n");
  1029. goto exit_deinit_dp;
  1030. }
  1031. sde_kms->dp_display_count =
  1032. dp_display_get_displays(sde_kms->dp_displays,
  1033. sde_kms->dp_display_count);
  1034. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1035. }
  1036. return 0;
  1037. exit_deinit_dp:
  1038. kfree(sde_kms->dp_displays);
  1039. sde_kms->dp_stream_count = 0;
  1040. sde_kms->dp_display_count = 0;
  1041. sde_kms->dp_displays = NULL;
  1042. exit_deinit_wb:
  1043. kfree(sde_kms->wb_displays);
  1044. sde_kms->wb_display_count = 0;
  1045. sde_kms->wb_displays = NULL;
  1046. exit_deinit_dsi:
  1047. kfree(sde_kms->dsi_displays);
  1048. sde_kms->dsi_display_count = 0;
  1049. sde_kms->dsi_displays = NULL;
  1050. return rc;
  1051. }
  1052. /**
  1053. * _sde_kms_release_displays - release cache of underlying display handles
  1054. * @sde_kms: Pointer to sde kms structure
  1055. */
  1056. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1057. {
  1058. if (!sde_kms) {
  1059. SDE_ERROR("invalid sde kms\n");
  1060. return;
  1061. }
  1062. kfree(sde_kms->wb_displays);
  1063. sde_kms->wb_displays = NULL;
  1064. sde_kms->wb_display_count = 0;
  1065. kfree(sde_kms->dsi_displays);
  1066. sde_kms->dsi_displays = NULL;
  1067. sde_kms->dsi_display_count = 0;
  1068. }
  1069. /**
  1070. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1071. * for underlying displays
  1072. * @dev: Pointer to drm device structure
  1073. * @priv: Pointer to private drm device data
  1074. * @sde_kms: Pointer to sde kms structure
  1075. * Returns: Zero on success
  1076. */
  1077. static int _sde_kms_setup_displays(struct drm_device *dev,
  1078. struct msm_drm_private *priv,
  1079. struct sde_kms *sde_kms)
  1080. {
  1081. static const struct sde_connector_ops dsi_ops = {
  1082. .set_info_blob = dsi_conn_set_info_blob,
  1083. .detect = dsi_conn_detect,
  1084. .get_modes = dsi_connector_get_modes,
  1085. .pre_destroy = dsi_connector_put_modes,
  1086. .mode_valid = dsi_conn_mode_valid,
  1087. .get_info = dsi_display_get_info,
  1088. .set_backlight = dsi_display_set_backlight,
  1089. .soft_reset = dsi_display_soft_reset,
  1090. .pre_kickoff = dsi_conn_pre_kickoff,
  1091. .clk_ctrl = dsi_display_clk_ctrl,
  1092. .set_power = dsi_display_set_power,
  1093. .get_mode_info = dsi_conn_get_mode_info,
  1094. .get_dst_format = dsi_display_get_dst_format,
  1095. .post_kickoff = dsi_conn_post_kickoff,
  1096. .check_status = dsi_display_check_status,
  1097. .enable_event = dsi_conn_enable_event,
  1098. .cmd_transfer = dsi_display_cmd_transfer,
  1099. .cont_splash_config = dsi_display_cont_splash_config,
  1100. .get_panel_vfp = dsi_display_get_panel_vfp,
  1101. .get_default_lms = dsi_display_get_default_lms,
  1102. .cmd_receive = dsi_display_cmd_receive,
  1103. };
  1104. static const struct sde_connector_ops wb_ops = {
  1105. .post_init = sde_wb_connector_post_init,
  1106. .set_info_blob = sde_wb_connector_set_info_blob,
  1107. .detect = sde_wb_connector_detect,
  1108. .get_modes = sde_wb_connector_get_modes,
  1109. .set_property = sde_wb_connector_set_property,
  1110. .get_info = sde_wb_get_info,
  1111. .soft_reset = NULL,
  1112. .get_mode_info = sde_wb_get_mode_info,
  1113. .get_dst_format = NULL,
  1114. .check_status = NULL,
  1115. .cmd_transfer = NULL,
  1116. .cont_splash_config = NULL,
  1117. .get_panel_vfp = NULL,
  1118. .cmd_receive = NULL,
  1119. };
  1120. static const struct sde_connector_ops dp_ops = {
  1121. .post_init = dp_connector_post_init,
  1122. .detect = dp_connector_detect,
  1123. .get_modes = dp_connector_get_modes,
  1124. .atomic_check = dp_connector_atomic_check,
  1125. .mode_valid = dp_connector_mode_valid,
  1126. .get_info = dp_connector_get_info,
  1127. .get_mode_info = dp_connector_get_mode_info,
  1128. .post_open = dp_connector_post_open,
  1129. .check_status = NULL,
  1130. .set_colorspace = dp_connector_set_colorspace,
  1131. .config_hdr = dp_connector_config_hdr,
  1132. .cmd_transfer = NULL,
  1133. .cont_splash_config = NULL,
  1134. .get_panel_vfp = NULL,
  1135. .update_pps = dp_connector_update_pps,
  1136. .cmd_receive = NULL,
  1137. };
  1138. struct msm_display_info info;
  1139. struct drm_encoder *encoder;
  1140. void *display, *connector;
  1141. int i, max_encoders;
  1142. int rc = 0;
  1143. u32 dsc_count = 0, mixer_count = 0;
  1144. u32 max_dp_dsc_count, max_dp_mixer_count;
  1145. if (!dev || !priv || !sde_kms) {
  1146. SDE_ERROR("invalid argument(s)\n");
  1147. return -EINVAL;
  1148. }
  1149. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1150. sde_kms->dp_display_count +
  1151. sde_kms->dp_stream_count;
  1152. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1153. max_encoders = ARRAY_SIZE(priv->encoders);
  1154. SDE_ERROR("capping number of displays to %d", max_encoders);
  1155. }
  1156. /* wb */
  1157. for (i = 0; i < sde_kms->wb_display_count &&
  1158. priv->num_encoders < max_encoders; ++i) {
  1159. display = sde_kms->wb_displays[i];
  1160. encoder = NULL;
  1161. memset(&info, 0x0, sizeof(info));
  1162. rc = sde_wb_get_info(NULL, &info, display);
  1163. if (rc) {
  1164. SDE_ERROR("wb get_info %d failed\n", i);
  1165. continue;
  1166. }
  1167. encoder = sde_encoder_init(dev, &info);
  1168. if (IS_ERR_OR_NULL(encoder)) {
  1169. SDE_ERROR("encoder init failed for wb %d\n", i);
  1170. continue;
  1171. }
  1172. rc = sde_wb_drm_init(display, encoder);
  1173. if (rc) {
  1174. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1175. sde_encoder_destroy(encoder);
  1176. continue;
  1177. }
  1178. connector = sde_connector_init(dev,
  1179. encoder,
  1180. 0,
  1181. display,
  1182. &wb_ops,
  1183. DRM_CONNECTOR_POLL_HPD,
  1184. DRM_MODE_CONNECTOR_VIRTUAL);
  1185. if (connector) {
  1186. priv->encoders[priv->num_encoders++] = encoder;
  1187. priv->connectors[priv->num_connectors++] = connector;
  1188. } else {
  1189. SDE_ERROR("wb %d connector init failed\n", i);
  1190. sde_wb_drm_deinit(display);
  1191. sde_encoder_destroy(encoder);
  1192. }
  1193. }
  1194. /* dsi */
  1195. for (i = 0; i < sde_kms->dsi_display_count &&
  1196. priv->num_encoders < max_encoders; ++i) {
  1197. display = sde_kms->dsi_displays[i];
  1198. encoder = NULL;
  1199. memset(&info, 0x0, sizeof(info));
  1200. rc = dsi_display_get_info(NULL, &info, display);
  1201. if (rc) {
  1202. SDE_ERROR("dsi get_info %d failed\n", i);
  1203. continue;
  1204. }
  1205. encoder = sde_encoder_init(dev, &info);
  1206. if (IS_ERR_OR_NULL(encoder)) {
  1207. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1208. continue;
  1209. }
  1210. rc = dsi_display_drm_bridge_init(display, encoder);
  1211. if (rc) {
  1212. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1213. sde_encoder_destroy(encoder);
  1214. continue;
  1215. }
  1216. connector = sde_connector_init(dev,
  1217. encoder,
  1218. dsi_display_get_drm_panel(display),
  1219. display,
  1220. &dsi_ops,
  1221. DRM_CONNECTOR_POLL_HPD,
  1222. DRM_MODE_CONNECTOR_DSI);
  1223. if (connector) {
  1224. priv->encoders[priv->num_encoders++] = encoder;
  1225. priv->connectors[priv->num_connectors++] = connector;
  1226. } else {
  1227. SDE_ERROR("dsi %d connector init failed\n", i);
  1228. dsi_display_drm_bridge_deinit(display);
  1229. sde_encoder_destroy(encoder);
  1230. continue;
  1231. }
  1232. rc = dsi_display_drm_ext_bridge_init(display,
  1233. encoder, connector);
  1234. if (rc) {
  1235. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1236. dsi_display_drm_bridge_deinit(display);
  1237. sde_connector_destroy(connector);
  1238. sde_encoder_destroy(encoder);
  1239. }
  1240. dsc_count += info.dsc_count;
  1241. mixer_count += info.lm_count;
  1242. }
  1243. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1244. sde_kms->catalog->mixer_count - mixer_count : 0;
  1245. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1246. sde_kms->catalog->dsc_count - dsc_count : 0;
  1247. /* dp */
  1248. for (i = 0; i < sde_kms->dp_display_count &&
  1249. priv->num_encoders < max_encoders; ++i) {
  1250. int idx;
  1251. display = sde_kms->dp_displays[i];
  1252. encoder = NULL;
  1253. memset(&info, 0x0, sizeof(info));
  1254. rc = dp_connector_get_info(NULL, &info, display);
  1255. if (rc) {
  1256. SDE_ERROR("dp get_info %d failed\n", i);
  1257. continue;
  1258. }
  1259. encoder = sde_encoder_init(dev, &info);
  1260. if (IS_ERR_OR_NULL(encoder)) {
  1261. SDE_ERROR("dp encoder init failed %d\n", i);
  1262. continue;
  1263. }
  1264. rc = dp_drm_bridge_init(display, encoder,
  1265. max_dp_mixer_count, max_dp_dsc_count);
  1266. if (rc) {
  1267. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1268. sde_encoder_destroy(encoder);
  1269. continue;
  1270. }
  1271. connector = sde_connector_init(dev,
  1272. encoder,
  1273. NULL,
  1274. display,
  1275. &dp_ops,
  1276. DRM_CONNECTOR_POLL_HPD,
  1277. DRM_MODE_CONNECTOR_DisplayPort);
  1278. if (connector) {
  1279. priv->encoders[priv->num_encoders++] = encoder;
  1280. priv->connectors[priv->num_connectors++] = connector;
  1281. } else {
  1282. SDE_ERROR("dp %d connector init failed\n", i);
  1283. dp_drm_bridge_deinit(display);
  1284. sde_encoder_destroy(encoder);
  1285. }
  1286. /* update display cap to MST_MODE for DP MST encoders */
  1287. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1288. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1289. priv->num_encoders < max_encoders; idx++) {
  1290. info.h_tile_instance[0] = idx;
  1291. encoder = sde_encoder_init(dev, &info);
  1292. if (IS_ERR_OR_NULL(encoder)) {
  1293. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1294. continue;
  1295. }
  1296. rc = dp_mst_drm_bridge_init(display, encoder);
  1297. if (rc) {
  1298. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1299. i, rc);
  1300. sde_encoder_destroy(encoder);
  1301. continue;
  1302. }
  1303. priv->encoders[priv->num_encoders++] = encoder;
  1304. }
  1305. }
  1306. return 0;
  1307. }
  1308. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1309. {
  1310. struct msm_drm_private *priv;
  1311. int i;
  1312. if (!sde_kms) {
  1313. SDE_ERROR("invalid sde_kms\n");
  1314. return;
  1315. } else if (!sde_kms->dev) {
  1316. SDE_ERROR("invalid dev\n");
  1317. return;
  1318. } else if (!sde_kms->dev->dev_private) {
  1319. SDE_ERROR("invalid dev_private\n");
  1320. return;
  1321. }
  1322. priv = sde_kms->dev->dev_private;
  1323. for (i = 0; i < priv->num_crtcs; i++)
  1324. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1325. priv->num_crtcs = 0;
  1326. for (i = 0; i < priv->num_planes; i++)
  1327. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1328. priv->num_planes = 0;
  1329. for (i = 0; i < priv->num_connectors; i++)
  1330. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1331. priv->num_connectors = 0;
  1332. for (i = 0; i < priv->num_encoders; i++)
  1333. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1334. priv->num_encoders = 0;
  1335. _sde_kms_release_displays(sde_kms);
  1336. }
  1337. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1338. {
  1339. struct drm_device *dev;
  1340. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1341. struct drm_crtc *crtc;
  1342. struct msm_drm_private *priv;
  1343. struct sde_mdss_cfg *catalog;
  1344. int primary_planes_idx = 0, i, ret;
  1345. int max_crtc_count;
  1346. u32 sspp_id[MAX_PLANES];
  1347. u32 master_plane_id[MAX_PLANES];
  1348. u32 num_virt_planes = 0;
  1349. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1350. SDE_ERROR("invalid sde_kms\n");
  1351. return -EINVAL;
  1352. }
  1353. dev = sde_kms->dev;
  1354. priv = dev->dev_private;
  1355. catalog = sde_kms->catalog;
  1356. ret = sde_core_irq_domain_add(sde_kms);
  1357. if (ret)
  1358. goto fail_irq;
  1359. /*
  1360. * Query for underlying display drivers, and create connectors,
  1361. * bridges and encoders for them.
  1362. */
  1363. if (!_sde_kms_get_displays(sde_kms))
  1364. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1365. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1366. /* Create the planes */
  1367. for (i = 0; i < catalog->sspp_count; i++) {
  1368. bool primary = true;
  1369. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1370. || primary_planes_idx >= max_crtc_count)
  1371. primary = false;
  1372. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1373. (1UL << max_crtc_count) - 1, 0);
  1374. if (IS_ERR(plane)) {
  1375. SDE_ERROR("sde_plane_init failed\n");
  1376. ret = PTR_ERR(plane);
  1377. goto fail;
  1378. }
  1379. priv->planes[priv->num_planes++] = plane;
  1380. if (primary)
  1381. primary_planes[primary_planes_idx++] = plane;
  1382. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1383. sde_is_custom_client()) {
  1384. int priority =
  1385. catalog->sspp[i].sblk->smart_dma_priority;
  1386. sspp_id[priority - 1] = catalog->sspp[i].id;
  1387. master_plane_id[priority - 1] = plane->base.id;
  1388. num_virt_planes++;
  1389. }
  1390. }
  1391. /* Initialize smart DMA virtual planes */
  1392. for (i = 0; i < num_virt_planes; i++) {
  1393. plane = sde_plane_init(dev, sspp_id[i], false,
  1394. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1395. if (IS_ERR(plane)) {
  1396. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1397. ret = PTR_ERR(plane);
  1398. goto fail;
  1399. }
  1400. priv->planes[priv->num_planes++] = plane;
  1401. }
  1402. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1403. /* Create one CRTC per encoder */
  1404. for (i = 0; i < max_crtc_count; i++) {
  1405. crtc = sde_crtc_init(dev, primary_planes[i]);
  1406. if (IS_ERR(crtc)) {
  1407. ret = PTR_ERR(crtc);
  1408. goto fail;
  1409. }
  1410. priv->crtcs[priv->num_crtcs++] = crtc;
  1411. }
  1412. if (sde_is_custom_client()) {
  1413. /* All CRTCs are compatible with all planes */
  1414. for (i = 0; i < priv->num_planes; i++)
  1415. priv->planes[i]->possible_crtcs =
  1416. (1 << priv->num_crtcs) - 1;
  1417. }
  1418. /* All CRTCs are compatible with all encoders */
  1419. for (i = 0; i < priv->num_encoders; i++)
  1420. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1421. return 0;
  1422. fail:
  1423. _sde_kms_drm_obj_destroy(sde_kms);
  1424. fail_irq:
  1425. sde_core_irq_domain_fini(sde_kms);
  1426. return ret;
  1427. }
  1428. /**
  1429. * sde_kms_timeline_status - provides current timeline status
  1430. * This API should be called without mode config lock.
  1431. * @dev: Pointer to drm device
  1432. */
  1433. void sde_kms_timeline_status(struct drm_device *dev)
  1434. {
  1435. struct drm_crtc *crtc;
  1436. struct drm_connector *conn;
  1437. struct drm_connector_list_iter conn_iter;
  1438. if (!dev) {
  1439. SDE_ERROR("invalid drm device node\n");
  1440. return;
  1441. }
  1442. drm_for_each_crtc(crtc, dev)
  1443. sde_crtc_timeline_status(crtc);
  1444. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1445. /*
  1446. *Probably locked from last close dumping status anyway
  1447. */
  1448. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1449. drm_connector_list_iter_begin(dev, &conn_iter);
  1450. drm_for_each_connector_iter(conn, &conn_iter)
  1451. sde_conn_timeline_status(conn);
  1452. drm_connector_list_iter_end(&conn_iter);
  1453. return;
  1454. }
  1455. mutex_lock(&dev->mode_config.mutex);
  1456. drm_connector_list_iter_begin(dev, &conn_iter);
  1457. drm_for_each_connector_iter(conn, &conn_iter)
  1458. sde_conn_timeline_status(conn);
  1459. drm_connector_list_iter_end(&conn_iter);
  1460. mutex_unlock(&dev->mode_config.mutex);
  1461. }
  1462. static int sde_kms_postinit(struct msm_kms *kms)
  1463. {
  1464. struct sde_kms *sde_kms = to_sde_kms(kms);
  1465. struct drm_device *dev;
  1466. struct drm_crtc *crtc;
  1467. int rc;
  1468. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1469. SDE_ERROR("invalid sde_kms\n");
  1470. return -EINVAL;
  1471. }
  1472. dev = sde_kms->dev;
  1473. rc = _sde_debugfs_init(sde_kms);
  1474. if (rc)
  1475. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1476. drm_for_each_crtc(crtc, dev)
  1477. sde_crtc_post_init(dev, crtc);
  1478. return rc;
  1479. }
  1480. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1481. struct drm_encoder *encoder)
  1482. {
  1483. return rate;
  1484. }
  1485. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1486. struct platform_device *pdev)
  1487. {
  1488. struct drm_device *dev;
  1489. struct msm_drm_private *priv;
  1490. int i;
  1491. if (!sde_kms || !pdev)
  1492. return;
  1493. dev = sde_kms->dev;
  1494. if (!dev)
  1495. return;
  1496. priv = dev->dev_private;
  1497. if (!priv)
  1498. return;
  1499. if (sde_kms->genpd_init) {
  1500. sde_kms->genpd_init = false;
  1501. pm_genpd_remove(&sde_kms->genpd);
  1502. of_genpd_del_provider(pdev->dev.of_node);
  1503. }
  1504. if (sde_kms->hw_intr)
  1505. sde_hw_intr_destroy(sde_kms->hw_intr);
  1506. sde_kms->hw_intr = NULL;
  1507. if (sde_kms->power_event)
  1508. sde_power_handle_unregister_event(
  1509. &priv->phandle, sde_kms->power_event);
  1510. _sde_kms_release_displays(sde_kms);
  1511. _sde_kms_unmap_all_splash_regions(sde_kms);
  1512. /* safe to call these more than once during shutdown */
  1513. _sde_debugfs_destroy(sde_kms);
  1514. _sde_kms_mmu_destroy(sde_kms);
  1515. if (sde_kms->catalog) {
  1516. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1517. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1518. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1519. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1520. }
  1521. }
  1522. if (sde_kms->rm_init)
  1523. sde_rm_destroy(&sde_kms->rm);
  1524. sde_kms->rm_init = false;
  1525. if (sde_kms->catalog)
  1526. sde_hw_catalog_deinit(sde_kms->catalog);
  1527. sde_kms->catalog = NULL;
  1528. if (sde_kms->sid)
  1529. msm_iounmap(pdev, sde_kms->sid);
  1530. sde_kms->sid = NULL;
  1531. if (sde_kms->reg_dma)
  1532. msm_iounmap(pdev, sde_kms->reg_dma);
  1533. sde_kms->reg_dma = NULL;
  1534. if (sde_kms->vbif[VBIF_NRT])
  1535. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1536. sde_kms->vbif[VBIF_NRT] = NULL;
  1537. if (sde_kms->vbif[VBIF_RT])
  1538. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1539. sde_kms->vbif[VBIF_RT] = NULL;
  1540. if (sde_kms->mmio)
  1541. msm_iounmap(pdev, sde_kms->mmio);
  1542. sde_kms->mmio = NULL;
  1543. sde_reg_dma_deinit();
  1544. }
  1545. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1546. {
  1547. int i;
  1548. if (!sde_kms)
  1549. return -EINVAL;
  1550. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1551. struct msm_mmu *mmu;
  1552. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1553. if (!aspace)
  1554. continue;
  1555. mmu = sde_kms->aspace[i]->mmu;
  1556. if (secure_only &&
  1557. !aspace->mmu->funcs->is_domain_secure(mmu))
  1558. continue;
  1559. /* cleanup aspace before detaching */
  1560. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1561. SDE_DEBUG("Detaching domain:%d\n", i);
  1562. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1563. ARRAY_SIZE(iommu_ports));
  1564. aspace->domain_attached = false;
  1565. }
  1566. return 0;
  1567. }
  1568. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1569. {
  1570. int i;
  1571. if (!sde_kms)
  1572. return -EINVAL;
  1573. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1574. struct msm_mmu *mmu;
  1575. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1576. if (!aspace)
  1577. continue;
  1578. mmu = sde_kms->aspace[i]->mmu;
  1579. if (secure_only &&
  1580. !aspace->mmu->funcs->is_domain_secure(mmu))
  1581. continue;
  1582. SDE_DEBUG("Attaching domain:%d\n", i);
  1583. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1584. ARRAY_SIZE(iommu_ports));
  1585. aspace->domain_attached = true;
  1586. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1587. }
  1588. return 0;
  1589. }
  1590. static void sde_kms_destroy(struct msm_kms *kms)
  1591. {
  1592. struct sde_kms *sde_kms;
  1593. struct drm_device *dev;
  1594. if (!kms) {
  1595. SDE_ERROR("invalid kms\n");
  1596. return;
  1597. }
  1598. sde_kms = to_sde_kms(kms);
  1599. dev = sde_kms->dev;
  1600. if (!dev || !dev->dev) {
  1601. SDE_ERROR("invalid device\n");
  1602. return;
  1603. }
  1604. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1605. kfree(sde_kms);
  1606. }
  1607. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1608. struct drm_atomic_state *state)
  1609. {
  1610. struct drm_device *dev = sde_kms->dev;
  1611. struct drm_plane *plane;
  1612. struct drm_plane_state *plane_state;
  1613. struct drm_crtc *crtc;
  1614. struct drm_crtc_state *crtc_state;
  1615. struct drm_connector *conn;
  1616. struct drm_connector_state *conn_state;
  1617. struct drm_connector_list_iter conn_iter;
  1618. int ret = 0;
  1619. drm_for_each_plane(plane, dev) {
  1620. plane_state = drm_atomic_get_plane_state(state, plane);
  1621. if (IS_ERR(plane_state)) {
  1622. ret = PTR_ERR(plane_state);
  1623. SDE_ERROR("error %d getting plane %d state\n",
  1624. ret, DRMID(plane));
  1625. return ret;
  1626. }
  1627. ret = sde_plane_helper_reset_custom_properties(plane,
  1628. plane_state);
  1629. if (ret) {
  1630. SDE_ERROR("error %d resetting plane props %d\n",
  1631. ret, DRMID(plane));
  1632. return ret;
  1633. }
  1634. }
  1635. drm_for_each_crtc(crtc, dev) {
  1636. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1637. if (IS_ERR(crtc_state)) {
  1638. ret = PTR_ERR(crtc_state);
  1639. SDE_ERROR("error %d getting crtc %d state\n",
  1640. ret, DRMID(crtc));
  1641. return ret;
  1642. }
  1643. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1644. if (ret) {
  1645. SDE_ERROR("error %d resetting crtc props %d\n",
  1646. ret, DRMID(crtc));
  1647. return ret;
  1648. }
  1649. }
  1650. drm_connector_list_iter_begin(dev, &conn_iter);
  1651. drm_for_each_connector_iter(conn, &conn_iter) {
  1652. conn_state = drm_atomic_get_connector_state(state, conn);
  1653. if (IS_ERR(conn_state)) {
  1654. ret = PTR_ERR(conn_state);
  1655. SDE_ERROR("error %d getting connector %d state\n",
  1656. ret, DRMID(conn));
  1657. return ret;
  1658. }
  1659. ret = sde_connector_helper_reset_custom_properties(conn,
  1660. conn_state);
  1661. if (ret) {
  1662. SDE_ERROR("error %d resetting connector props %d\n",
  1663. ret, DRMID(conn));
  1664. return ret;
  1665. }
  1666. }
  1667. drm_connector_list_iter_end(&conn_iter);
  1668. return ret;
  1669. }
  1670. static void sde_kms_lastclose(struct msm_kms *kms)
  1671. {
  1672. struct sde_kms *sde_kms;
  1673. struct drm_device *dev;
  1674. struct drm_atomic_state *state;
  1675. struct drm_modeset_acquire_ctx ctx;
  1676. int ret;
  1677. if (!kms) {
  1678. SDE_ERROR("invalid argument\n");
  1679. return;
  1680. }
  1681. sde_kms = to_sde_kms(kms);
  1682. dev = sde_kms->dev;
  1683. drm_modeset_acquire_init(&ctx, 0);
  1684. state = drm_atomic_state_alloc(dev);
  1685. if (!state) {
  1686. ret = -ENOMEM;
  1687. goto out_ctx;
  1688. }
  1689. state->acquire_ctx = &ctx;
  1690. retry:
  1691. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1692. if (ret)
  1693. goto out_state;
  1694. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1695. if (ret)
  1696. goto out_state;
  1697. ret = drm_atomic_commit(state);
  1698. out_state:
  1699. if (ret == -EDEADLK)
  1700. goto backoff;
  1701. drm_atomic_state_put(state);
  1702. out_ctx:
  1703. drm_modeset_drop_locks(&ctx);
  1704. drm_modeset_acquire_fini(&ctx);
  1705. if (ret)
  1706. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1707. return;
  1708. backoff:
  1709. drm_atomic_state_clear(state);
  1710. drm_modeset_backoff(&ctx);
  1711. goto retry;
  1712. }
  1713. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1714. struct drm_atomic_state *state)
  1715. {
  1716. struct sde_kms *sde_kms;
  1717. struct drm_device *dev;
  1718. struct drm_crtc *crtc;
  1719. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1720. struct drm_crtc_state *crtc_state;
  1721. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1722. bool sec_session = false, global_sec_session = false;
  1723. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1724. int i;
  1725. if (!kms || !state) {
  1726. return -EINVAL;
  1727. SDE_ERROR("invalid arguments\n");
  1728. }
  1729. sde_kms = to_sde_kms(kms);
  1730. dev = sde_kms->dev;
  1731. /* iterate state object for active secure/non-secure crtc */
  1732. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1733. if (!crtc_state->active)
  1734. continue;
  1735. active_crtc_cnt++;
  1736. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1737. &fb_sec, &fb_sec_dir);
  1738. if (fb_sec_dir)
  1739. sec_session = true;
  1740. cur_crtc = crtc;
  1741. }
  1742. /* iterate global list for active and secure/non-secure crtc */
  1743. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1744. if (!crtc->state->active)
  1745. continue;
  1746. global_active_crtc_cnt++;
  1747. /* update only when crtc is not the same as current crtc */
  1748. if (crtc != cur_crtc) {
  1749. fb_ns = fb_sec = fb_sec_dir = 0;
  1750. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1751. &fb_sec, &fb_sec_dir);
  1752. if (fb_sec_dir)
  1753. global_sec_session = true;
  1754. global_crtc = crtc;
  1755. }
  1756. }
  1757. if (!global_sec_session && !sec_session)
  1758. return 0;
  1759. /*
  1760. * - fail crtc commit, if secure-camera/secure-ui session is
  1761. * in-progress in any other display
  1762. * - fail secure-camera/secure-ui crtc commit, if any other display
  1763. * session is in-progress
  1764. */
  1765. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1766. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1767. SDE_ERROR(
  1768. "crtc%d secure check failed global_active:%d active:%d\n",
  1769. cur_crtc ? cur_crtc->base.id : -1,
  1770. global_active_crtc_cnt, active_crtc_cnt);
  1771. return -EPERM;
  1772. /*
  1773. * As only one crtc is allowed during secure session, the crtc
  1774. * in this commit should match with the global crtc
  1775. */
  1776. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1777. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1778. cur_crtc->base.id, sec_session,
  1779. global_crtc->base.id, global_sec_session);
  1780. return -EPERM;
  1781. }
  1782. return 0;
  1783. }
  1784. static int sde_kms_atomic_check(struct msm_kms *kms,
  1785. struct drm_atomic_state *state)
  1786. {
  1787. struct sde_kms *sde_kms;
  1788. struct drm_device *dev;
  1789. int ret;
  1790. if (!kms || !state)
  1791. return -EINVAL;
  1792. sde_kms = to_sde_kms(kms);
  1793. dev = sde_kms->dev;
  1794. SDE_ATRACE_BEGIN("atomic_check");
  1795. if (sde_kms_is_suspend_blocked(dev)) {
  1796. SDE_DEBUG("suspended, skip atomic_check\n");
  1797. ret = -EBUSY;
  1798. goto end;
  1799. }
  1800. ret = drm_atomic_helper_check(dev, state);
  1801. if (ret)
  1802. goto end;
  1803. /*
  1804. * Check if any secure transition(moving CRTC between secure and
  1805. * non-secure state and vice-versa) is allowed or not. when moving
  1806. * to secure state, planes with fb_mode set to dir_translated only can
  1807. * be staged on the CRTC, and only one CRTC can be active during
  1808. * Secure state
  1809. */
  1810. ret = sde_kms_check_secure_transition(kms, state);
  1811. end:
  1812. SDE_ATRACE_END("atomic_check");
  1813. return ret;
  1814. }
  1815. static struct msm_gem_address_space*
  1816. _sde_kms_get_address_space(struct msm_kms *kms,
  1817. unsigned int domain)
  1818. {
  1819. struct sde_kms *sde_kms;
  1820. if (!kms) {
  1821. SDE_ERROR("invalid kms\n");
  1822. return NULL;
  1823. }
  1824. sde_kms = to_sde_kms(kms);
  1825. if (!sde_kms) {
  1826. SDE_ERROR("invalid sde_kms\n");
  1827. return NULL;
  1828. }
  1829. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1830. return NULL;
  1831. return (sde_kms->aspace[domain] &&
  1832. sde_kms->aspace[domain]->domain_attached) ?
  1833. sde_kms->aspace[domain] : NULL;
  1834. }
  1835. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1836. unsigned int domain)
  1837. {
  1838. struct sde_kms *sde_kms;
  1839. struct msm_gem_address_space *aspace;
  1840. if (!kms) {
  1841. SDE_ERROR("invalid kms\n");
  1842. return NULL;
  1843. }
  1844. sde_kms = to_sde_kms(kms);
  1845. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1846. SDE_ERROR("invalid params\n");
  1847. return NULL;
  1848. }
  1849. aspace = _sde_kms_get_address_space(kms, domain);
  1850. return (aspace && aspace->domain_attached) ?
  1851. msm_gem_get_aspace_device(aspace) : NULL;
  1852. }
  1853. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1854. {
  1855. struct drm_device *dev = NULL;
  1856. struct sde_kms *sde_kms = NULL;
  1857. struct drm_connector *connector = NULL;
  1858. struct drm_connector_list_iter conn_iter;
  1859. struct sde_connector *sde_conn = NULL;
  1860. if (!kms) {
  1861. SDE_ERROR("invalid kms\n");
  1862. return;
  1863. }
  1864. sde_kms = to_sde_kms(kms);
  1865. dev = sde_kms->dev;
  1866. if (!dev) {
  1867. SDE_ERROR("invalid device\n");
  1868. return;
  1869. }
  1870. if (!dev->mode_config.poll_enabled)
  1871. return;
  1872. mutex_lock(&dev->mode_config.mutex);
  1873. drm_connector_list_iter_begin(dev, &conn_iter);
  1874. drm_for_each_connector_iter(connector, &conn_iter) {
  1875. /* Only handle HPD capable connectors. */
  1876. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1877. continue;
  1878. sde_conn = to_sde_connector(connector);
  1879. if (sde_conn->ops.post_open)
  1880. sde_conn->ops.post_open(&sde_conn->base,
  1881. sde_conn->display);
  1882. }
  1883. drm_connector_list_iter_end(&conn_iter);
  1884. mutex_unlock(&dev->mode_config.mutex);
  1885. }
  1886. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1887. struct sde_splash_display *splash_display,
  1888. struct drm_crtc *crtc)
  1889. {
  1890. struct msm_drm_private *priv;
  1891. struct drm_plane *plane;
  1892. struct sde_splash_mem *splash;
  1893. enum sde_sspp plane_id;
  1894. bool is_virtual;
  1895. int i, j;
  1896. if (!sde_kms || !splash_display || !crtc) {
  1897. SDE_ERROR("invalid input args\n");
  1898. return -EINVAL;
  1899. }
  1900. priv = sde_kms->dev->dev_private;
  1901. for (i = 0; i < priv->num_planes; i++) {
  1902. plane = priv->planes[i];
  1903. plane_id = sde_plane_pipe(plane);
  1904. is_virtual = is_sde_plane_virtual(plane);
  1905. splash = splash_display->splash;
  1906. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1907. if ((plane_id != splash_display->pipes[j].sspp) ||
  1908. (splash_display->pipes[j].is_virtual
  1909. != is_virtual))
  1910. continue;
  1911. if (splash && sde_plane_validate_src_addr(plane,
  1912. splash->splash_buf_base,
  1913. splash->splash_buf_size)) {
  1914. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1915. plane_id, crtc->base.id);
  1916. }
  1917. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1918. crtc->base.id, plane_id, is_virtual);
  1919. }
  1920. }
  1921. return 0;
  1922. }
  1923. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1924. {
  1925. void *display;
  1926. struct dsi_display *dsi_display;
  1927. struct msm_display_info info;
  1928. struct drm_encoder *encoder = NULL;
  1929. struct drm_crtc *crtc = NULL;
  1930. int i, rc = 0;
  1931. struct drm_display_mode *drm_mode = NULL;
  1932. struct drm_device *dev;
  1933. struct msm_drm_private *priv;
  1934. struct sde_kms *sde_kms;
  1935. struct drm_connector_list_iter conn_iter;
  1936. struct drm_connector *connector = NULL;
  1937. struct sde_connector *sde_conn = NULL;
  1938. struct sde_splash_display *splash_display;
  1939. if (!kms) {
  1940. SDE_ERROR("invalid kms\n");
  1941. return -EINVAL;
  1942. }
  1943. sde_kms = to_sde_kms(kms);
  1944. dev = sde_kms->dev;
  1945. if (!dev) {
  1946. SDE_ERROR("invalid device\n");
  1947. return -EINVAL;
  1948. }
  1949. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  1950. && (!sde_kms->splash_data.num_splash_regions)) ||
  1951. !sde_kms->splash_data.num_splash_displays) {
  1952. DRM_INFO("cont_splash feature not enabled\n");
  1953. return rc;
  1954. }
  1955. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1956. sde_kms->splash_data.num_splash_displays,
  1957. sde_kms->dsi_display_count);
  1958. /* dsi */
  1959. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1960. display = sde_kms->dsi_displays[i];
  1961. dsi_display = (struct dsi_display *)display;
  1962. splash_display = &sde_kms->splash_data.splash_display[i];
  1963. if (!splash_display->cont_splash_enabled) {
  1964. SDE_DEBUG("display->name = %s splash not enabled\n",
  1965. dsi_display->name);
  1966. continue;
  1967. }
  1968. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1969. if (dsi_display->bridge->base.encoder) {
  1970. encoder = dsi_display->bridge->base.encoder;
  1971. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1972. }
  1973. memset(&info, 0x0, sizeof(info));
  1974. rc = dsi_display_get_info(NULL, &info, display);
  1975. if (rc) {
  1976. SDE_ERROR("dsi get_info %d failed\n", i);
  1977. encoder = NULL;
  1978. continue;
  1979. }
  1980. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  1981. ((info.is_connected) ? "true" : "false"),
  1982. info.display_type);
  1983. if (!encoder) {
  1984. SDE_ERROR("encoder not initialized\n");
  1985. return -EINVAL;
  1986. }
  1987. priv = sde_kms->dev->dev_private;
  1988. encoder->crtc = priv->crtcs[i];
  1989. crtc = encoder->crtc;
  1990. splash_display->encoder = encoder;
  1991. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1992. i, crtc->base.id, encoder->base.id);
  1993. mutex_lock(&dev->mode_config.mutex);
  1994. drm_connector_list_iter_begin(dev, &conn_iter);
  1995. drm_for_each_connector_iter(connector, &conn_iter) {
  1996. /**
  1997. * SDE_KMS doesn't attach more than one encoder to
  1998. * a DSI connector. So it is safe to check only with
  1999. * the first encoder entry. Revisit this logic if we
  2000. * ever have to support continuous splash for
  2001. * external displays in MST configuration.
  2002. */
  2003. if (connector->encoder_ids[0] == encoder->base.id)
  2004. break;
  2005. }
  2006. drm_connector_list_iter_end(&conn_iter);
  2007. if (!connector) {
  2008. SDE_ERROR("connector not initialized\n");
  2009. mutex_unlock(&dev->mode_config.mutex);
  2010. return -EINVAL;
  2011. }
  2012. if (connector->funcs->fill_modes) {
  2013. connector->funcs->fill_modes(connector,
  2014. dev->mode_config.max_width,
  2015. dev->mode_config.max_height);
  2016. } else {
  2017. SDE_ERROR("fill_modes api not defined\n");
  2018. mutex_unlock(&dev->mode_config.mutex);
  2019. return -EINVAL;
  2020. }
  2021. mutex_unlock(&dev->mode_config.mutex);
  2022. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2023. /* currently consider modes[0] as the preferred mode */
  2024. drm_mode = list_first_entry(&connector->modes,
  2025. struct drm_display_mode, head);
  2026. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2027. drm_mode->name, drm_mode->type,
  2028. drm_mode->flags);
  2029. /* Update CRTC drm structure */
  2030. crtc->state->active = true;
  2031. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2032. if (rc) {
  2033. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2034. return rc;
  2035. }
  2036. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2037. drm_mode_copy(&crtc->mode, drm_mode);
  2038. /* Update encoder structure */
  2039. sde_encoder_update_caps_for_cont_splash(encoder,
  2040. splash_display, true);
  2041. sde_crtc_update_cont_splash_settings(crtc);
  2042. sde_conn = to_sde_connector(connector);
  2043. if (sde_conn && sde_conn->ops.cont_splash_config)
  2044. sde_conn->ops.cont_splash_config(sde_conn->display);
  2045. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2046. splash_display, crtc);
  2047. if (rc) {
  2048. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2049. return rc;
  2050. }
  2051. }
  2052. return rc;
  2053. }
  2054. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2055. {
  2056. struct sde_kms *sde_kms;
  2057. if (!kms) {
  2058. SDE_ERROR("invalid kms\n");
  2059. return false;
  2060. }
  2061. sde_kms = to_sde_kms(kms);
  2062. return sde_kms->splash_data.num_splash_displays;
  2063. }
  2064. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2065. const struct drm_display_mode *mode,
  2066. const struct msm_resource_caps_info *res, u32 *num_lm)
  2067. {
  2068. struct sde_kms *sde_kms;
  2069. s64 mode_clock_hz = 0;
  2070. s64 max_mdp_clock_hz = 0;
  2071. s64 max_lm_width = 0;
  2072. s64 hdisplay_fp = 0;
  2073. s64 htotal_fp = 0;
  2074. s64 vtotal_fp = 0;
  2075. s64 vrefresh_fp = 0;
  2076. s64 mdp_fudge_factor = 0;
  2077. s64 num_lm_fp = 0;
  2078. s64 lm_clk_fp = 0;
  2079. s64 lm_width_fp = 0;
  2080. int rc = 0;
  2081. if (!num_lm) {
  2082. SDE_ERROR("invalid num_lm pointer\n");
  2083. return -EINVAL;
  2084. }
  2085. /* default to 1 layer mixer */
  2086. *num_lm = 1;
  2087. if (!kms || !mode || !res) {
  2088. SDE_ERROR("invalid input args\n");
  2089. return -EINVAL;
  2090. }
  2091. sde_kms = to_sde_kms(kms);
  2092. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2093. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2094. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2095. htotal_fp = drm_int2fixp(mode->htotal);
  2096. vtotal_fp = drm_int2fixp(mode->vtotal);
  2097. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2098. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2099. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2100. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2101. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2102. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2103. if (mode_clock_hz > max_mdp_clock_hz ||
  2104. hdisplay_fp > max_lm_width) {
  2105. *num_lm = 0;
  2106. do {
  2107. *num_lm += 2;
  2108. num_lm_fp = drm_int2fixp(*num_lm);
  2109. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2110. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2111. if (*num_lm > 4) {
  2112. rc = -EINVAL;
  2113. goto error;
  2114. }
  2115. } while (lm_clk_fp > max_mdp_clock_hz ||
  2116. lm_width_fp > max_lm_width);
  2117. mode_clock_hz = lm_clk_fp;
  2118. }
  2119. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2120. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2121. *num_lm, drm_fixp2int(mode_clock_hz),
  2122. sde_kms->perf.max_core_clk_rate);
  2123. return 0;
  2124. error:
  2125. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2126. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2127. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2128. *num_lm, drm_fixp2int(mode_clock_hz),
  2129. sde_kms->perf.max_core_clk_rate);
  2130. return rc;
  2131. }
  2132. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2133. u32 hdisplay, u32 *num_dsc)
  2134. {
  2135. struct sde_kms *sde_kms;
  2136. uint32_t max_dsc_width;
  2137. if (!num_dsc) {
  2138. SDE_ERROR("invalid num_dsc pointer\n");
  2139. return -EINVAL;
  2140. }
  2141. *num_dsc = 0;
  2142. if (!kms || !hdisplay) {
  2143. SDE_ERROR("invalid input args\n");
  2144. return -EINVAL;
  2145. }
  2146. sde_kms = to_sde_kms(kms);
  2147. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2148. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2149. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2150. hdisplay, max_dsc_width,
  2151. *num_dsc);
  2152. return 0;
  2153. }
  2154. static void _sde_kms_null_commit(struct drm_device *dev,
  2155. struct drm_encoder *enc)
  2156. {
  2157. struct drm_modeset_acquire_ctx ctx;
  2158. struct drm_connector *conn = NULL;
  2159. struct drm_connector *tmp_conn = NULL;
  2160. struct drm_connector_list_iter conn_iter;
  2161. struct drm_atomic_state *state = NULL;
  2162. struct drm_crtc_state *crtc_state = NULL;
  2163. struct drm_connector_state *conn_state = NULL;
  2164. int retry_cnt = 0;
  2165. int ret = 0;
  2166. drm_modeset_acquire_init(&ctx, 0);
  2167. retry:
  2168. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2169. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2170. drm_modeset_backoff(&ctx);
  2171. retry_cnt++;
  2172. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2173. goto retry;
  2174. } else if (WARN_ON(ret)) {
  2175. goto end;
  2176. }
  2177. state = drm_atomic_state_alloc(dev);
  2178. if (!state) {
  2179. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2180. goto end;
  2181. }
  2182. state->acquire_ctx = &ctx;
  2183. drm_connector_list_iter_begin(dev, &conn_iter);
  2184. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2185. if (enc == tmp_conn->state->best_encoder) {
  2186. conn = tmp_conn;
  2187. break;
  2188. }
  2189. }
  2190. drm_connector_list_iter_end(&conn_iter);
  2191. if (!conn) {
  2192. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2193. goto end;
  2194. }
  2195. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2196. conn_state = drm_atomic_get_connector_state(state, conn);
  2197. if (IS_ERR(conn_state)) {
  2198. SDE_ERROR("error %d getting connector %d state\n",
  2199. ret, DRMID(conn));
  2200. goto end;
  2201. }
  2202. crtc_state->active = true;
  2203. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2204. if (ret)
  2205. SDE_ERROR("error %d setting the crtc\n", ret);
  2206. ret = drm_atomic_commit(state);
  2207. if (ret)
  2208. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2209. end:
  2210. if (state)
  2211. drm_atomic_state_put(state);
  2212. drm_modeset_drop_locks(&ctx);
  2213. drm_modeset_acquire_fini(&ctx);
  2214. }
  2215. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2216. struct device *dev)
  2217. {
  2218. int i, ret, crtc_id = 0;
  2219. struct drm_device *ddev = dev_get_drvdata(dev);
  2220. struct drm_connector *conn;
  2221. struct drm_connector_list_iter conn_iter;
  2222. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2223. drm_connector_list_iter_begin(ddev, &conn_iter);
  2224. drm_for_each_connector_iter(conn, &conn_iter) {
  2225. uint64_t lp;
  2226. lp = sde_connector_get_lp(conn);
  2227. if (lp != SDE_MODE_DPMS_LP2)
  2228. continue;
  2229. if (sde_encoder_in_clone_mode(conn->encoder))
  2230. continue;
  2231. ret = sde_encoder_wait_for_event(conn->encoder,
  2232. MSM_ENC_TX_COMPLETE);
  2233. if (ret && ret != -EWOULDBLOCK) {
  2234. SDE_ERROR(
  2235. "[conn: %d] wait for commit done returned %d\n",
  2236. conn->base.id, ret);
  2237. } else if (!ret) {
  2238. crtc_id = drm_crtc_index(conn->state->crtc);
  2239. if (priv->event_thread[crtc_id].thread)
  2240. kthread_flush_worker(
  2241. &priv->event_thread[crtc_id].worker);
  2242. sde_encoder_idle_request(conn->encoder);
  2243. }
  2244. }
  2245. drm_connector_list_iter_end(&conn_iter);
  2246. for (i = 0; i < priv->num_crtcs; i++) {
  2247. if (priv->disp_thread[i].thread)
  2248. kthread_flush_worker(
  2249. &priv->disp_thread[i].worker);
  2250. if (priv->event_thread[i].thread)
  2251. kthread_flush_worker(
  2252. &priv->event_thread[i].worker);
  2253. }
  2254. kthread_flush_worker(&priv->pp_event_worker);
  2255. }
  2256. static int sde_kms_pm_suspend(struct device *dev)
  2257. {
  2258. struct drm_device *ddev;
  2259. struct drm_modeset_acquire_ctx ctx;
  2260. struct drm_connector *conn;
  2261. struct drm_encoder *enc;
  2262. struct drm_connector_list_iter conn_iter;
  2263. struct drm_atomic_state *state = NULL;
  2264. struct sde_kms *sde_kms;
  2265. int ret = 0, num_crtcs = 0;
  2266. if (!dev)
  2267. return -EINVAL;
  2268. ddev = dev_get_drvdata(dev);
  2269. if (!ddev || !ddev_to_msm_kms(ddev))
  2270. return -EINVAL;
  2271. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2272. SDE_EVT32(0);
  2273. /* disable hot-plug polling */
  2274. drm_kms_helper_poll_disable(ddev);
  2275. /* if a display stuck in CS trigger a null commit to complete handoff */
  2276. drm_for_each_encoder(enc, ddev) {
  2277. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2278. _sde_kms_null_commit(ddev, enc);
  2279. }
  2280. /* acquire modeset lock(s) */
  2281. drm_modeset_acquire_init(&ctx, 0);
  2282. retry:
  2283. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2284. if (ret)
  2285. goto unlock;
  2286. /* save current state for resume */
  2287. if (sde_kms->suspend_state)
  2288. drm_atomic_state_put(sde_kms->suspend_state);
  2289. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2290. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2291. ret = PTR_ERR(sde_kms->suspend_state);
  2292. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2293. sde_kms->suspend_state = NULL;
  2294. goto unlock;
  2295. }
  2296. /* create atomic state to disable all CRTCs */
  2297. state = drm_atomic_state_alloc(ddev);
  2298. if (!state) {
  2299. ret = -ENOMEM;
  2300. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2301. goto unlock;
  2302. }
  2303. state->acquire_ctx = &ctx;
  2304. drm_connector_list_iter_begin(ddev, &conn_iter);
  2305. drm_for_each_connector_iter(conn, &conn_iter) {
  2306. struct drm_crtc_state *crtc_state;
  2307. uint64_t lp;
  2308. if (!conn->state || !conn->state->crtc ||
  2309. conn->dpms != DRM_MODE_DPMS_ON ||
  2310. sde_encoder_in_clone_mode(conn->encoder))
  2311. continue;
  2312. lp = sde_connector_get_lp(conn);
  2313. if (lp == SDE_MODE_DPMS_LP1) {
  2314. /* transition LP1->LP2 on pm suspend */
  2315. ret = sde_connector_set_property_for_commit(conn, state,
  2316. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2317. if (ret) {
  2318. DRM_ERROR("failed to set lp2 for conn %d\n",
  2319. conn->base.id);
  2320. drm_connector_list_iter_end(&conn_iter);
  2321. goto unlock;
  2322. }
  2323. }
  2324. if (lp != SDE_MODE_DPMS_LP2) {
  2325. /* force CRTC to be inactive */
  2326. crtc_state = drm_atomic_get_crtc_state(state,
  2327. conn->state->crtc);
  2328. if (IS_ERR_OR_NULL(crtc_state)) {
  2329. DRM_ERROR("failed to get crtc %d state\n",
  2330. conn->state->crtc->base.id);
  2331. drm_connector_list_iter_end(&conn_iter);
  2332. goto unlock;
  2333. }
  2334. if (lp != SDE_MODE_DPMS_LP1)
  2335. crtc_state->active = false;
  2336. ++num_crtcs;
  2337. }
  2338. }
  2339. drm_connector_list_iter_end(&conn_iter);
  2340. /* check for nothing to do */
  2341. if (num_crtcs == 0) {
  2342. DRM_DEBUG("all crtcs are already in the off state\n");
  2343. sde_kms->suspend_block = true;
  2344. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2345. goto unlock;
  2346. }
  2347. /* commit the "disable all" state */
  2348. ret = drm_atomic_commit(state);
  2349. if (ret < 0) {
  2350. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2351. goto unlock;
  2352. }
  2353. sde_kms->suspend_block = true;
  2354. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2355. unlock:
  2356. if (state) {
  2357. drm_atomic_state_put(state);
  2358. state = NULL;
  2359. }
  2360. if (ret == -EDEADLK) {
  2361. drm_modeset_backoff(&ctx);
  2362. goto retry;
  2363. }
  2364. drm_modeset_drop_locks(&ctx);
  2365. drm_modeset_acquire_fini(&ctx);
  2366. /*
  2367. * pm runtime driver avoids multiple runtime_suspend API call by
  2368. * checking runtime_status. However, this call helps when there is a
  2369. * race condition between pm_suspend call and doze_suspend/power_off
  2370. * commit. It removes the extra vote from suspend and adds it back
  2371. * later to allow power collapse during pm_suspend call
  2372. */
  2373. pm_runtime_put_sync(dev);
  2374. pm_runtime_get_noresume(dev);
  2375. /* dump clock state before entering suspend */
  2376. if (sde_kms->pm_suspend_clk_dump)
  2377. _sde_kms_dump_clks_state(sde_kms);
  2378. return ret;
  2379. }
  2380. static int sde_kms_pm_resume(struct device *dev)
  2381. {
  2382. struct drm_device *ddev;
  2383. struct sde_kms *sde_kms;
  2384. struct drm_modeset_acquire_ctx ctx;
  2385. int ret, i;
  2386. if (!dev)
  2387. return -EINVAL;
  2388. ddev = dev_get_drvdata(dev);
  2389. if (!ddev || !ddev_to_msm_kms(ddev))
  2390. return -EINVAL;
  2391. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2392. SDE_EVT32(sde_kms->suspend_state != NULL);
  2393. drm_mode_config_reset(ddev);
  2394. drm_modeset_acquire_init(&ctx, 0);
  2395. retry:
  2396. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2397. if (ret == -EDEADLK) {
  2398. drm_modeset_backoff(&ctx);
  2399. goto retry;
  2400. } else if (WARN_ON(ret)) {
  2401. goto end;
  2402. }
  2403. sde_kms->suspend_block = false;
  2404. if (sde_kms->suspend_state) {
  2405. sde_kms->suspend_state->acquire_ctx = &ctx;
  2406. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2407. ret = drm_atomic_helper_commit_duplicated_state(
  2408. sde_kms->suspend_state, &ctx);
  2409. if (ret != -EDEADLK)
  2410. break;
  2411. drm_modeset_backoff(&ctx);
  2412. }
  2413. if (ret < 0)
  2414. DRM_ERROR("failed to restore state, %d\n", ret);
  2415. drm_atomic_state_put(sde_kms->suspend_state);
  2416. sde_kms->suspend_state = NULL;
  2417. }
  2418. end:
  2419. drm_modeset_drop_locks(&ctx);
  2420. drm_modeset_acquire_fini(&ctx);
  2421. /* enable hot-plug polling */
  2422. drm_kms_helper_poll_enable(ddev);
  2423. return 0;
  2424. }
  2425. static const struct msm_kms_funcs kms_funcs = {
  2426. .hw_init = sde_kms_hw_init,
  2427. .postinit = sde_kms_postinit,
  2428. .irq_preinstall = sde_irq_preinstall,
  2429. .irq_postinstall = sde_irq_postinstall,
  2430. .irq_uninstall = sde_irq_uninstall,
  2431. .irq = sde_irq,
  2432. .lastclose = sde_kms_lastclose,
  2433. .prepare_fence = sde_kms_prepare_fence,
  2434. .prepare_commit = sde_kms_prepare_commit,
  2435. .commit = sde_kms_commit,
  2436. .complete_commit = sde_kms_complete_commit,
  2437. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2438. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2439. .enable_vblank = sde_kms_enable_vblank,
  2440. .disable_vblank = sde_kms_disable_vblank,
  2441. .check_modified_format = sde_format_check_modified_format,
  2442. .atomic_check = sde_kms_atomic_check,
  2443. .get_format = sde_get_msm_format,
  2444. .round_pixclk = sde_kms_round_pixclk,
  2445. .pm_suspend = sde_kms_pm_suspend,
  2446. .pm_resume = sde_kms_pm_resume,
  2447. .destroy = sde_kms_destroy,
  2448. .cont_splash_config = sde_kms_cont_splash_config,
  2449. .register_events = _sde_kms_register_events,
  2450. .get_address_space = _sde_kms_get_address_space,
  2451. .get_address_space_device = _sde_kms_get_address_space_device,
  2452. .postopen = _sde_kms_post_open,
  2453. .check_for_splash = sde_kms_check_for_splash,
  2454. .get_mixer_count = sde_kms_get_mixer_count,
  2455. .get_dsc_count = sde_kms_get_dsc_count,
  2456. };
  2457. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2458. {
  2459. int i;
  2460. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2461. if (!sde_kms->aspace[i])
  2462. continue;
  2463. msm_gem_address_space_put(sde_kms->aspace[i]);
  2464. sde_kms->aspace[i] = NULL;
  2465. }
  2466. return 0;
  2467. }
  2468. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2469. {
  2470. struct msm_mmu *mmu;
  2471. int i, ret;
  2472. int early_map = 0;
  2473. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2474. return -EINVAL;
  2475. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2476. struct msm_gem_address_space *aspace;
  2477. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2478. if (IS_ERR(mmu)) {
  2479. ret = PTR_ERR(mmu);
  2480. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2481. i, ret);
  2482. continue;
  2483. }
  2484. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2485. mmu, "sde");
  2486. if (IS_ERR(aspace)) {
  2487. ret = PTR_ERR(aspace);
  2488. goto fail;
  2489. }
  2490. sde_kms->aspace[i] = aspace;
  2491. aspace->domain_attached = true;
  2492. /* Mapping splash memory block */
  2493. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2494. sde_kms->splash_data.num_splash_regions) {
  2495. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2496. if (ret) {
  2497. SDE_ERROR("failed to map ret:%d\n", ret);
  2498. goto fail;
  2499. }
  2500. }
  2501. /*
  2502. * disable early-map which would have been enabled during
  2503. * bootup by smmu through the device-tree hint for cont-spash
  2504. */
  2505. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2506. &early_map);
  2507. if (ret) {
  2508. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2509. ret, early_map);
  2510. goto early_map_fail;
  2511. }
  2512. }
  2513. sde_kms->base.aspace = sde_kms->aspace[0];
  2514. return 0;
  2515. early_map_fail:
  2516. _sde_kms_unmap_all_splash_regions(sde_kms);
  2517. fail:
  2518. mmu->funcs->destroy(mmu);
  2519. _sde_kms_mmu_destroy(sde_kms);
  2520. return ret;
  2521. }
  2522. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2523. {
  2524. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2525. return;
  2526. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2527. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2528. sde_kms->catalog);
  2529. if (sde_kms->sid)
  2530. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  2531. }
  2532. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2533. {
  2534. struct sde_vbif_set_qos_params qos_params;
  2535. struct sde_mdss_cfg *catalog;
  2536. if (!sde_kms->catalog)
  2537. return;
  2538. catalog = sde_kms->catalog;
  2539. memset(&qos_params, 0, sizeof(qos_params));
  2540. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2541. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2542. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2543. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2544. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2545. }
  2546. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2547. {
  2548. struct sde_hw_uidle *uidle;
  2549. if (!sde_kms) {
  2550. SDE_ERROR("invalid kms\n");
  2551. return -EINVAL;
  2552. }
  2553. uidle = sde_kms->hw_uidle;
  2554. if (uidle && uidle->ops.active_override_enable)
  2555. uidle->ops.active_override_enable(uidle, enable);
  2556. return 0;
  2557. }
  2558. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2559. {
  2560. struct device *cpu_dev;
  2561. int cpu = 0;
  2562. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  2563. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2564. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2565. return;
  2566. }
  2567. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2568. cpu_dev = get_cpu_device(cpu);
  2569. if (!cpu_dev) {
  2570. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2571. cpu);
  2572. continue;
  2573. }
  2574. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2575. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2576. cpu_irq_latency);
  2577. else
  2578. dev_pm_qos_add_request(cpu_dev,
  2579. &sde_kms->pm_qos_irq_req[cpu],
  2580. DEV_PM_QOS_RESUME_LATENCY,
  2581. cpu_irq_latency);
  2582. }
  2583. }
  2584. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2585. {
  2586. struct device *cpu_dev;
  2587. int cpu = 0;
  2588. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2589. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2590. return;
  2591. }
  2592. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2593. cpu_dev = get_cpu_device(cpu);
  2594. if (!cpu_dev) {
  2595. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2596. cpu);
  2597. continue;
  2598. }
  2599. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2600. dev_pm_qos_remove_request(
  2601. &sde_kms->pm_qos_irq_req[cpu]);
  2602. }
  2603. }
  2604. void sde_kms_irq_enable_notify(struct sde_kms *sde_kms, bool enable)
  2605. {
  2606. if (enable)
  2607. _sde_kms_update_pm_qos_irq_request(sde_kms);
  2608. else
  2609. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  2610. }
  2611. static void sde_kms_irq_affinity_notify(
  2612. struct irq_affinity_notify *affinity_notify,
  2613. const cpumask_t *mask)
  2614. {
  2615. struct msm_drm_private *priv;
  2616. struct sde_kms *sde_kms = container_of(affinity_notify,
  2617. struct sde_kms, affinity_notify);
  2618. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2619. return;
  2620. priv = sde_kms->dev->dev_private;
  2621. mutex_lock(&priv->phandle.phandle_lock);
  2622. // save irq cpu mask
  2623. sde_kms->irq_cpu_mask = *mask;
  2624. // request vote with updated irq cpu mask
  2625. if (sde_kms->irq_enabled)
  2626. _sde_kms_update_pm_qos_irq_request(sde_kms);
  2627. mutex_unlock(&priv->phandle.phandle_lock);
  2628. }
  2629. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  2630. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2631. {
  2632. struct sde_kms *sde_kms = usr;
  2633. struct msm_kms *msm_kms;
  2634. msm_kms = &sde_kms->base;
  2635. if (!sde_kms)
  2636. return;
  2637. SDE_DEBUG("event_type:%d\n", event_type);
  2638. SDE_EVT32_VERBOSE(event_type);
  2639. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2640. sde_irq_update(msm_kms, true);
  2641. sde_kms->first_kickoff = true;
  2642. if (sde_kms->splash_data.num_splash_displays ||
  2643. sde_in_trusted_vm(sde_kms))
  2644. return;
  2645. sde_vbif_init_memtypes(sde_kms);
  2646. sde_kms_init_shared_hw(sde_kms);
  2647. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2648. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2649. sde_irq_update(msm_kms, false);
  2650. sde_kms->first_kickoff = false;
  2651. if (sde_in_trusted_vm(sde_kms))
  2652. return;
  2653. _sde_kms_active_override(sde_kms, true);
  2654. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  2655. sde_vbif_axi_halt_request(sde_kms);
  2656. }
  2657. }
  2658. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2659. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2660. {
  2661. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2662. int rc = -EINVAL;
  2663. SDE_DEBUG("\n");
  2664. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2665. if (rc > 0)
  2666. rc = 0;
  2667. SDE_EVT32(rc, genpd->device_count);
  2668. return rc;
  2669. }
  2670. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2671. {
  2672. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2673. SDE_DEBUG("\n");
  2674. pm_runtime_put_sync(sde_kms->dev->dev);
  2675. SDE_EVT32(genpd->device_count);
  2676. return 0;
  2677. }
  2678. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  2679. struct sde_splash_data *data)
  2680. {
  2681. int i = 0;
  2682. int ret = 0;
  2683. struct device_node *parent, *node, *node1;
  2684. struct resource r, r1;
  2685. const char *node_name = "splash_region";
  2686. struct sde_splash_mem *mem;
  2687. bool share_splash_mem = false;
  2688. int num_displays, num_regions;
  2689. struct sde_splash_display *splash_display;
  2690. if (!data)
  2691. return -EINVAL;
  2692. memset(data, 0, sizeof(*data));
  2693. parent = of_find_node_by_path("/reserved-memory");
  2694. if (!parent) {
  2695. SDE_ERROR("failed to find reserved-memory node\n");
  2696. return -EINVAL;
  2697. }
  2698. node = of_find_node_by_name(parent, node_name);
  2699. if (!node) {
  2700. SDE_DEBUG("failed to find node %s\n", node_name);
  2701. return -EINVAL;
  2702. }
  2703. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  2704. if (!node1)
  2705. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2706. /**
  2707. * Support sharing a single splash memory for all the built in displays
  2708. * and also independent splash region per displays. Incase of
  2709. * independent splash region for each connected display, dtsi node of
  2710. * cont_splash_region should be collection of all memory regions
  2711. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2712. */
  2713. num_displays = dsi_display_get_num_of_displays();
  2714. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2715. data->num_splash_displays = num_displays;
  2716. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2717. if (num_displays > num_regions) {
  2718. share_splash_mem = true;
  2719. pr_info(":%d displays share same splash buf\n", num_displays);
  2720. }
  2721. for (i = 0; i < num_displays; i++) {
  2722. splash_display = &data->splash_display[i];
  2723. if (!i || !share_splash_mem) {
  2724. if (of_address_to_resource(node, i, &r)) {
  2725. SDE_ERROR("invalid data for:%s\n", node_name);
  2726. return -EINVAL;
  2727. }
  2728. mem = &data->splash_mem[i];
  2729. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2730. SDE_DEBUG("failed to find ramdump memory\n");
  2731. mem->ramdump_base = 0;
  2732. mem->ramdump_size = 0;
  2733. } else {
  2734. mem->ramdump_base = (unsigned long)r1.start;
  2735. mem->ramdump_size = (r1.end - r1.start) + 1;
  2736. }
  2737. mem->splash_buf_base = (unsigned long)r.start;
  2738. mem->splash_buf_size = (r.end - r.start) + 1;
  2739. mem->ref_cnt = 0;
  2740. splash_display->splash = mem;
  2741. data->num_splash_regions++;
  2742. } else {
  2743. data->splash_display[i].splash = &data->splash_mem[0];
  2744. }
  2745. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2746. splash_display->splash->splash_buf_base,
  2747. splash_display->splash->splash_buf_size);
  2748. }
  2749. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  2750. return ret;
  2751. }
  2752. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2753. struct platform_device *platformdev)
  2754. {
  2755. int rc = -EINVAL;
  2756. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2757. if (IS_ERR(sde_kms->mmio)) {
  2758. rc = PTR_ERR(sde_kms->mmio);
  2759. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2760. sde_kms->mmio = NULL;
  2761. goto error;
  2762. }
  2763. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2764. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2765. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2766. sde_kms->mmio_len);
  2767. if (rc)
  2768. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2769. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2770. "vbif_phys");
  2771. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2772. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2773. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2774. sde_kms->vbif[VBIF_RT] = NULL;
  2775. goto error;
  2776. }
  2777. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2778. "vbif_phys");
  2779. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2780. sde_kms->vbif_len[VBIF_RT]);
  2781. if (rc)
  2782. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2783. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2784. "vbif_nrt_phys");
  2785. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2786. sde_kms->vbif[VBIF_NRT] = NULL;
  2787. SDE_DEBUG("VBIF NRT is not defined");
  2788. } else {
  2789. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2790. "vbif_nrt_phys");
  2791. rc = sde_dbg_reg_register_base("vbif_nrt",
  2792. sde_kms->vbif[VBIF_NRT],
  2793. sde_kms->vbif_len[VBIF_NRT]);
  2794. if (rc)
  2795. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2796. rc);
  2797. }
  2798. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2799. "regdma_phys");
  2800. if (IS_ERR(sde_kms->reg_dma)) {
  2801. sde_kms->reg_dma = NULL;
  2802. SDE_DEBUG("REG_DMA is not defined");
  2803. } else {
  2804. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2805. "regdma_phys");
  2806. rc = sde_dbg_reg_register_base("reg_dma",
  2807. sde_kms->reg_dma,
  2808. sde_kms->reg_dma_len);
  2809. if (rc)
  2810. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2811. rc);
  2812. }
  2813. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2814. "sid_phys");
  2815. if (IS_ERR(sde_kms->sid)) {
  2816. SDE_DEBUG("sid register is not defined: %d\n", rc);
  2817. sde_kms->sid = NULL;
  2818. } else {
  2819. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2820. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  2821. sde_kms->sid_len);
  2822. if (rc)
  2823. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2824. }
  2825. error:
  2826. return rc;
  2827. }
  2828. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2829. struct sde_kms *sde_kms)
  2830. {
  2831. int rc = 0;
  2832. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2833. sde_kms->genpd.name = dev->unique;
  2834. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2835. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2836. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2837. if (rc < 0) {
  2838. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2839. sde_kms->genpd.name, rc);
  2840. return rc;
  2841. }
  2842. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2843. &sde_kms->genpd);
  2844. if (rc < 0) {
  2845. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2846. sde_kms->genpd.name, rc);
  2847. pm_genpd_remove(&sde_kms->genpd);
  2848. return rc;
  2849. }
  2850. sde_kms->genpd_init = true;
  2851. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2852. }
  2853. return rc;
  2854. }
  2855. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2856. struct drm_device *dev,
  2857. struct msm_drm_private *priv)
  2858. {
  2859. struct sde_rm *rm = NULL;
  2860. int i, rc = -EINVAL;
  2861. sde_kms->catalog = sde_hw_catalog_init(dev);
  2862. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2863. rc = PTR_ERR(sde_kms->catalog);
  2864. if (!sde_kms->catalog)
  2865. rc = -EINVAL;
  2866. SDE_ERROR("catalog init failed: %d\n", rc);
  2867. sde_kms->catalog = NULL;
  2868. goto power_error;
  2869. }
  2870. sde_kms->core_rev = sde_kms->catalog->hwversion;
  2871. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2872. /* initialize power domain if defined */
  2873. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2874. if (rc) {
  2875. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2876. goto genpd_err;
  2877. }
  2878. rc = _sde_kms_mmu_init(sde_kms);
  2879. if (rc) {
  2880. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2881. goto power_error;
  2882. }
  2883. /* Initialize reg dma block which is a singleton */
  2884. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2885. sde_kms->dev);
  2886. if (rc) {
  2887. SDE_ERROR("failed: reg dma init failed\n");
  2888. goto power_error;
  2889. }
  2890. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2891. rm = &sde_kms->rm;
  2892. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2893. sde_kms->dev);
  2894. if (rc) {
  2895. SDE_ERROR("rm init failed: %d\n", rc);
  2896. goto power_error;
  2897. }
  2898. sde_kms->rm_init = true;
  2899. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2900. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2901. rc = PTR_ERR(sde_kms->hw_intr);
  2902. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2903. sde_kms->hw_intr = NULL;
  2904. goto hw_intr_init_err;
  2905. }
  2906. /*
  2907. * Attempt continuous splash handoff only if reserved
  2908. * splash memory is found & release resources on any error
  2909. * in finding display hw config in splash
  2910. */
  2911. if (sde_kms->splash_data.num_splash_regions) {
  2912. struct sde_splash_display *display;
  2913. int ret, display_count =
  2914. sde_kms->splash_data.num_splash_displays;
  2915. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2916. &sde_kms->splash_data, sde_kms->catalog);
  2917. for (i = 0; i < display_count; i++) {
  2918. display = &sde_kms->splash_data.splash_display[i];
  2919. /*
  2920. * free splash region on resource init failure and
  2921. * cont-splash disabled case
  2922. */
  2923. if (!display->cont_splash_enabled || ret)
  2924. _sde_kms_free_splash_display_data(
  2925. sde_kms, display);
  2926. }
  2927. }
  2928. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2929. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2930. rc = PTR_ERR(sde_kms->hw_mdp);
  2931. if (!sde_kms->hw_mdp)
  2932. rc = -EINVAL;
  2933. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2934. sde_kms->hw_mdp = NULL;
  2935. goto power_error;
  2936. }
  2937. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2938. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2939. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2940. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2941. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2942. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2943. if (!sde_kms->hw_vbif[vbif_idx])
  2944. rc = -EINVAL;
  2945. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2946. sde_kms->hw_vbif[vbif_idx] = NULL;
  2947. goto power_error;
  2948. }
  2949. }
  2950. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2951. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2952. sde_kms->mmio_len, sde_kms->catalog);
  2953. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2954. rc = PTR_ERR(sde_kms->hw_uidle);
  2955. if (!sde_kms->hw_uidle)
  2956. rc = -EINVAL;
  2957. /* uidle is optional, so do not make it a fatal error */
  2958. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2959. sde_kms->hw_uidle = NULL;
  2960. rc = 0;
  2961. }
  2962. } else {
  2963. sde_kms->hw_uidle = NULL;
  2964. }
  2965. if (sde_kms->sid) {
  2966. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2967. sde_kms->sid_len, sde_kms->catalog);
  2968. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  2969. rc = PTR_ERR(sde_kms->hw_sid);
  2970. SDE_ERROR("failed to init sid %ld\n", rc);
  2971. sde_kms->hw_sid = NULL;
  2972. goto power_error;
  2973. }
  2974. }
  2975. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2976. &priv->phandle, "core_clk");
  2977. if (rc) {
  2978. SDE_ERROR("failed to init perf %d\n", rc);
  2979. goto perf_err;
  2980. }
  2981. /*
  2982. * _sde_kms_drm_obj_init should create the DRM related objects
  2983. * i.e. CRTCs, planes, encoders, connectors and so forth
  2984. */
  2985. rc = _sde_kms_drm_obj_init(sde_kms);
  2986. if (rc) {
  2987. SDE_ERROR("modeset init failed: %d\n", rc);
  2988. goto drm_obj_init_err;
  2989. }
  2990. return 0;
  2991. genpd_err:
  2992. drm_obj_init_err:
  2993. sde_core_perf_destroy(&sde_kms->perf);
  2994. hw_intr_init_err:
  2995. perf_err:
  2996. power_error:
  2997. return rc;
  2998. }
  2999. static int sde_kms_hw_init(struct msm_kms *kms)
  3000. {
  3001. struct sde_kms *sde_kms;
  3002. struct drm_device *dev;
  3003. struct msm_drm_private *priv;
  3004. struct platform_device *platformdev;
  3005. int i, irq_num, rc = -EINVAL;
  3006. if (!kms) {
  3007. SDE_ERROR("invalid kms\n");
  3008. goto end;
  3009. }
  3010. sde_kms = to_sde_kms(kms);
  3011. dev = sde_kms->dev;
  3012. if (!dev || !dev->dev) {
  3013. SDE_ERROR("invalid device\n");
  3014. goto end;
  3015. }
  3016. platformdev = to_platform_device(dev->dev);
  3017. priv = dev->dev_private;
  3018. if (!priv) {
  3019. SDE_ERROR("invalid private data\n");
  3020. goto end;
  3021. }
  3022. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3023. if (rc)
  3024. goto error;
  3025. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3026. if (rc)
  3027. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3028. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3029. if (rc)
  3030. goto error;
  3031. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3032. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3033. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3034. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3035. mutex_init(&sde_kms->secure_transition_lock);
  3036. atomic_set(&sde_kms->detach_sec_cb, 0);
  3037. atomic_set(&sde_kms->detach_all_cb, 0);
  3038. /*
  3039. * Support format modifiers for compression etc.
  3040. */
  3041. dev->mode_config.allow_fb_modifiers = true;
  3042. /*
  3043. * Handle (re)initializations during power enable
  3044. */
  3045. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3046. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3047. SDE_POWER_EVENT_POST_ENABLE |
  3048. SDE_POWER_EVENT_PRE_DISABLE,
  3049. sde_kms_handle_power_event, sde_kms, "kms");
  3050. if (sde_kms->splash_data.num_splash_displays) {
  3051. SDE_DEBUG("Skipping MDP Resources disable\n");
  3052. } else {
  3053. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3054. sde_power_data_bus_set_quota(&priv->phandle, i,
  3055. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3056. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3057. pm_runtime_put_sync(sde_kms->dev->dev);
  3058. }
  3059. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3060. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3061. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3062. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3063. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3064. return 0;
  3065. error:
  3066. _sde_kms_hw_destroy(sde_kms, platformdev);
  3067. end:
  3068. return rc;
  3069. }
  3070. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3071. {
  3072. struct msm_drm_private *priv;
  3073. struct sde_kms *sde_kms;
  3074. if (!dev || !dev->dev_private) {
  3075. SDE_ERROR("drm device node invalid\n");
  3076. return ERR_PTR(-EINVAL);
  3077. }
  3078. priv = dev->dev_private;
  3079. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3080. if (!sde_kms) {
  3081. SDE_ERROR("failed to allocate sde kms\n");
  3082. return ERR_PTR(-ENOMEM);
  3083. }
  3084. msm_kms_init(&sde_kms->base, &kms_funcs);
  3085. sde_kms->dev = dev;
  3086. return &sde_kms->base;
  3087. }
  3088. static int _sde_kms_register_events(struct msm_kms *kms,
  3089. struct drm_mode_object *obj, u32 event, bool en)
  3090. {
  3091. int ret = 0;
  3092. struct drm_crtc *crtc = NULL;
  3093. struct drm_connector *conn = NULL;
  3094. struct sde_kms *sde_kms = NULL;
  3095. if (!kms || !obj) {
  3096. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3097. return -EINVAL;
  3098. }
  3099. sde_kms = to_sde_kms(kms);
  3100. switch (obj->type) {
  3101. case DRM_MODE_OBJECT_CRTC:
  3102. crtc = obj_to_crtc(obj);
  3103. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3104. break;
  3105. case DRM_MODE_OBJECT_CONNECTOR:
  3106. conn = obj_to_connector(obj);
  3107. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3108. en);
  3109. break;
  3110. }
  3111. return ret;
  3112. }
  3113. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3114. {
  3115. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3116. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3117. }