dp_be.c 67 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. #ifdef WLAN_SUPPORT_PPEDS
  33. #include "be/dp_ppeds.h"
  34. #include <ppe_vp_public.h>
  35. #include <ppe_drv_sc.h>
  36. #endif
  37. /* Generic AST entry aging timer value */
  38. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  39. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  40. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  41. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  42. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  43. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  44. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  45. #ifdef QCA_WIFI_KIWI_V2
  46. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  47. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  48. #else
  49. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  50. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  51. #endif
  52. };
  53. #else
  54. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  55. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  56. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  57. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  58. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  59. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  60. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  61. };
  62. #endif
  63. #ifdef WLAN_SUPPORT_PPEDS
  64. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  65. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  66. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  67. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  68. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  69. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  70. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  71. };
  72. static void dp_ppeds_rings_status(struct dp_soc *soc)
  73. {
  74. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  75. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  76. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  77. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  78. WBM2SW_RELEASE);
  79. }
  80. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  81. {
  82. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  83. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  84. be_soc->ppeds_tx_desc.num_allocated,
  85. be_soc->ppeds_tx_desc.num_free);
  86. }
  87. #endif
  88. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  89. {
  90. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  91. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  92. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  93. /* this is used only when dmac mode is enabled */
  94. soc->num_rx_refill_buf_rings = 1;
  95. soc->wlan_cfg_ctx->notify_frame_support =
  96. DP_MARK_NOTIFY_FRAME_SUPPORT;
  97. }
  98. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  99. {
  100. switch (context_type) {
  101. case DP_CONTEXT_TYPE_SOC:
  102. return sizeof(struct dp_soc_be);
  103. case DP_CONTEXT_TYPE_PDEV:
  104. return sizeof(struct dp_pdev_be);
  105. case DP_CONTEXT_TYPE_VDEV:
  106. return sizeof(struct dp_vdev_be);
  107. case DP_CONTEXT_TYPE_PEER:
  108. return sizeof(struct dp_peer_be);
  109. default:
  110. return 0;
  111. }
  112. }
  113. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  114. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  115. /**
  116. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  117. * per wbm2sw ring
  118. *
  119. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  120. *
  121. * Return: None
  122. */
  123. static inline
  124. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  125. {
  126. cc_cfg->wbm2sw6_cc_en = 1;
  127. cc_cfg->wbm2sw5_cc_en = 1;
  128. cc_cfg->wbm2sw4_cc_en = 1;
  129. cc_cfg->wbm2sw3_cc_en = 1;
  130. cc_cfg->wbm2sw2_cc_en = 1;
  131. /* disable wbm2sw1 hw cc as it's for FW */
  132. cc_cfg->wbm2sw1_cc_en = 0;
  133. cc_cfg->wbm2sw0_cc_en = 1;
  134. cc_cfg->wbm2fw_cc_en = 0;
  135. }
  136. #else
  137. static inline
  138. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  139. {
  140. cc_cfg->wbm2sw6_cc_en = 1;
  141. cc_cfg->wbm2sw5_cc_en = 1;
  142. cc_cfg->wbm2sw4_cc_en = 1;
  143. cc_cfg->wbm2sw3_cc_en = 1;
  144. cc_cfg->wbm2sw2_cc_en = 1;
  145. cc_cfg->wbm2sw1_cc_en = 1;
  146. cc_cfg->wbm2sw0_cc_en = 1;
  147. cc_cfg->wbm2fw_cc_en = 0;
  148. }
  149. #endif
  150. #if defined(WLAN_SUPPORT_RX_FISA)
  151. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  152. {
  153. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  154. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  155. /* get CMEM for cookie conversion */
  156. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  157. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  158. return QDF_STATUS_E_NOMEM;
  159. }
  160. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  161. soc->fst_cmem_base = soc->cmem_base +
  162. (soc->cmem_total_size - soc->cmem_avail_size);
  163. soc->cmem_avail_size -= soc->fst_cmem_size;
  164. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  165. soc->fst_cmem_base, soc->fst_cmem_size);
  166. return QDF_STATUS_SUCCESS;
  167. }
  168. #else /* !WLAN_SUPPORT_RX_FISA */
  169. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  170. {
  171. return QDF_STATUS_SUCCESS;
  172. }
  173. #endif
  174. /**
  175. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  176. * conversion register
  177. *
  178. * @soc: SOC handle
  179. * @is_4k_align: page address 4k aligned
  180. *
  181. * Return: None
  182. */
  183. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  184. bool is_4k_align)
  185. {
  186. struct hal_hw_cc_config cc_cfg = { 0 };
  187. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  188. if (soc->cdp_soc.ol_ops->get_con_mode &&
  189. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  190. return;
  191. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  192. dp_info("INI skip HW CC register setting");
  193. return;
  194. }
  195. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  196. cc_cfg.cc_global_en = true;
  197. cc_cfg.page_4k_align = is_4k_align;
  198. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  199. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  200. /* 36th bit should be 1 then HW know this is CMEM address */
  201. cc_cfg.lut_base_addr_39_32 = 0x10;
  202. cc_cfg.error_path_cookie_conv_en = true;
  203. cc_cfg.release_path_cookie_conv_en = true;
  204. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  205. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  206. }
  207. /**
  208. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  209. * @hal_soc_hdl: HAL SOC handle
  210. * @offset: CMEM address
  211. * @value: value to write
  212. *
  213. * Return: None.
  214. */
  215. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  216. uint32_t offset,
  217. uint32_t value)
  218. {
  219. hal_cmem_write(hal_soc_hdl, offset, value);
  220. }
  221. /**
  222. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  223. * HW cookie conversion
  224. *
  225. * @soc: SOC handle
  226. *
  227. * Return: 0 in case of success, else error value
  228. */
  229. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  230. {
  231. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  232. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  233. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  234. /* get CMEM for cookie conversion */
  235. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  236. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  237. return QDF_STATUS_E_RESOURCES;
  238. }
  239. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  240. DP_CC_MEM_OFFSET_IN_CMEM);
  241. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  242. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  243. be_soc->cc_cmem_base, soc->cmem_avail_size);
  244. return QDF_STATUS_SUCCESS;
  245. }
  246. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  247. uint8_t for_feature)
  248. {
  249. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  250. switch (for_feature) {
  251. case COOKIE_CONVERSION:
  252. status = dp_hw_cc_cmem_addr_init(soc);
  253. break;
  254. case FISA_FST:
  255. status = dp_fisa_fst_cmem_addr_init(soc);
  256. break;
  257. default:
  258. dp_err("Invalid CMEM request");
  259. }
  260. return status;
  261. }
  262. #else
  263. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  264. bool is_4k_align) {}
  265. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  266. uint32_t offset,
  267. uint32_t value)
  268. { }
  269. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  270. {
  271. return QDF_STATUS_SUCCESS;
  272. }
  273. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  274. uint8_t for_feature)
  275. {
  276. return QDF_STATUS_SUCCESS;
  277. }
  278. #endif
  279. QDF_STATUS
  280. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  281. struct dp_hw_cookie_conversion_t *cc_ctx,
  282. uint32_t num_descs,
  283. enum dp_desc_type desc_type,
  284. uint8_t desc_pool_id)
  285. {
  286. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  287. uint32_t num_spt_pages, i = 0;
  288. struct dp_spt_page_desc *spt_desc;
  289. struct qdf_mem_dma_page_t *dma_page;
  290. uint8_t chip_id;
  291. /* estimate how many SPT DDR pages needed */
  292. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  293. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  294. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  295. dp_info("num_spt_pages needed %d", num_spt_pages);
  296. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  297. &cc_ctx->page_pool, qdf_page_size,
  298. num_spt_pages, 0, false);
  299. if (!cc_ctx->page_pool.dma_pages) {
  300. dp_err("spt ddr pages allocation failed");
  301. return QDF_STATUS_E_RESOURCES;
  302. }
  303. cc_ctx->page_desc_base = qdf_mem_malloc(
  304. num_spt_pages * sizeof(struct dp_spt_page_desc));
  305. if (!cc_ctx->page_desc_base) {
  306. dp_err("spt page descs allocation failed");
  307. goto fail_0;
  308. }
  309. chip_id = dp_mlo_get_chip_id(soc);
  310. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  311. desc_type);
  312. /* initial page desc */
  313. spt_desc = cc_ctx->page_desc_base;
  314. dma_page = cc_ctx->page_pool.dma_pages;
  315. while (i < num_spt_pages) {
  316. /* check if page address 4K aligned */
  317. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  318. dp_err("non-4k aligned pages addr %pK",
  319. (void *)dma_page[i].page_p_addr);
  320. goto fail_1;
  321. }
  322. spt_desc[i].page_v_addr =
  323. dma_page[i].page_v_addr_start;
  324. spt_desc[i].page_p_addr =
  325. dma_page[i].page_p_addr;
  326. i++;
  327. }
  328. cc_ctx->total_page_num = num_spt_pages;
  329. qdf_spinlock_create(&cc_ctx->cc_lock);
  330. return QDF_STATUS_SUCCESS;
  331. fail_1:
  332. qdf_mem_free(cc_ctx->page_desc_base);
  333. fail_0:
  334. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  335. &cc_ctx->page_pool, 0, false);
  336. return QDF_STATUS_E_FAILURE;
  337. }
  338. QDF_STATUS
  339. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  340. struct dp_hw_cookie_conversion_t *cc_ctx)
  341. {
  342. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  343. qdf_mem_free(cc_ctx->page_desc_base);
  344. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  345. &cc_ctx->page_pool, 0, false);
  346. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  347. return QDF_STATUS_SUCCESS;
  348. }
  349. QDF_STATUS
  350. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  351. struct dp_hw_cookie_conversion_t *cc_ctx)
  352. {
  353. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  354. uint32_t i = 0;
  355. struct dp_spt_page_desc *spt_desc;
  356. uint32_t ppt_index;
  357. uint32_t ppt_id_start;
  358. if (!cc_ctx->total_page_num) {
  359. dp_err("total page num is 0");
  360. return QDF_STATUS_E_INVAL;
  361. }
  362. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  363. spt_desc = cc_ctx->page_desc_base;
  364. while (i < cc_ctx->total_page_num) {
  365. /* write page PA to CMEM */
  366. dp_hw_cc_cmem_write(soc->hal_soc,
  367. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  368. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  369. (spt_desc[i].page_p_addr >>
  370. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  371. ppt_index = ppt_id_start + i;
  372. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  373. qdf_assert_always(0);
  374. spt_desc[i].ppt_index = ppt_index;
  375. be_soc->page_desc_base[ppt_index].page_v_addr =
  376. spt_desc[i].page_v_addr;
  377. i++;
  378. }
  379. return QDF_STATUS_SUCCESS;
  380. }
  381. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  382. QDF_STATUS
  383. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  384. struct dp_hw_cookie_conversion_t *cc_ctx)
  385. {
  386. uint32_t ppt_index;
  387. struct dp_spt_page_desc *spt_desc;
  388. int i = 0;
  389. spt_desc = cc_ctx->page_desc_base;
  390. while (i < cc_ctx->total_page_num) {
  391. ppt_index = spt_desc[i].ppt_index;
  392. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  393. i++;
  394. }
  395. return QDF_STATUS_SUCCESS;
  396. }
  397. #else
  398. QDF_STATUS
  399. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  400. struct dp_hw_cookie_conversion_t *cc_ctx)
  401. {
  402. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  403. uint32_t ppt_index;
  404. struct dp_spt_page_desc *spt_desc;
  405. int i = 0;
  406. spt_desc = cc_ctx->page_desc_base;
  407. while (i < cc_ctx->total_page_num) {
  408. /* reset PA in CMEM to NULL */
  409. dp_hw_cc_cmem_write(soc->hal_soc,
  410. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  411. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  412. 0);
  413. ppt_index = spt_desc[i].ppt_index;
  414. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  415. i++;
  416. }
  417. return QDF_STATUS_SUCCESS;
  418. }
  419. #endif
  420. #ifdef WLAN_SUPPORT_PPEDS
  421. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  422. {
  423. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  424. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  425. /*
  426. * Check if PPE DS is enabled.
  427. */
  428. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  429. return QDF_STATUS_SUCCESS;
  430. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  431. return QDF_STATUS_SUCCESS;
  432. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  433. return QDF_STATUS_SUCCESS;
  434. }
  435. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  436. {
  437. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  438. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  439. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  440. return QDF_STATUS_E_FAILURE;
  441. dp_ppeds_detach_soc_be(be_soc);
  442. cdp_ops->ppeds_ops = NULL;
  443. return QDF_STATUS_SUCCESS;
  444. }
  445. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  446. struct dp_peer_be *be_peer,
  447. uint8_t vdev_id,
  448. uint16_t src_info)
  449. {
  450. uint16_t service_code;
  451. uint8_t priority_valid;
  452. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  453. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  454. QDF_STATUS status = QDF_STATUS_SUCCESS;
  455. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  456. struct dp_vdev_be *be_vdev;
  457. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  458. /*
  459. * Program service code bypass to avoid L2 new mac address
  460. * learning exception when fdb learning is disabled.
  461. */
  462. service_code = PPE_DRV_SC_SPF_BYPASS;
  463. priority_valid = be_peer->priority_valid;
  464. /*
  465. * if FST is enabled and MLO is disabled then
  466. * let flow rule take the decision of routing
  467. * the pkt to DS or host
  468. */
  469. if (wlan_cfg_is_rx_flow_tag_enabled(cfg) &&
  470. qdf_is_macaddr_zero((struct qdf_mac_addr *)
  471. be_vdev->vdev.mld_mac_addr.raw))
  472. use_ppe_ds = 0;
  473. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  474. status =
  475. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  476. (soc->ctrl_psoc,
  477. be_peer->peer.mac_addr.raw,
  478. service_code, priority_valid,
  479. src_info, vdev_id, use_ppe_ds,
  480. peer_routing_enabled);
  481. if (status != QDF_STATUS_SUCCESS) {
  482. dp_err("vdev_id: %d, PPE peer routing mac:"
  483. QDF_MAC_ADDR_FMT, vdev_id,
  484. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  485. return QDF_STATUS_E_FAILURE;
  486. }
  487. }
  488. return QDF_STATUS_SUCCESS;
  489. }
  490. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  491. struct dp_peer *peer,
  492. struct dp_vdev_be *be_vdev)
  493. {
  494. struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
  495. uint16_t src_info = ppe_vp_profile->vp_num;
  496. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  497. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  498. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  499. if (!be_peer) {
  500. dp_err("BE peer is null");
  501. return QDF_STATUS_E_NULL_VALUE;
  502. }
  503. if (IS_DP_LEGACY_PEER(peer)) {
  504. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  505. vdev_id, src_info);
  506. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  507. int i;
  508. struct dp_peer *link_peer = NULL;
  509. struct dp_mld_link_peers link_peers_info;
  510. /* get link peers with reference */
  511. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  512. DP_MOD_ID_DS);
  513. for (i = 0; i < link_peers_info.num_links; i++) {
  514. link_peer = link_peers_info.link_peers[i];
  515. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  516. if (!be_peer) {
  517. dp_err("BE peer is null");
  518. continue;
  519. }
  520. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  521. if (!be_vdev) {
  522. dp_err("BE vap is null for peer id %d ",
  523. link_peer->peer_id);
  524. continue;
  525. }
  526. vdev_id = be_vdev->vdev.vdev_id;
  527. qdf_status = dp_peer_ppeds_default_route_be(soc,
  528. be_peer,
  529. vdev_id,
  530. src_info);
  531. }
  532. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  533. } else {
  534. struct dp_peer *mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  535. if (!mld_peer)
  536. return qdf_status;
  537. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  538. if (!be_vdev) {
  539. dp_err("BE vap is null");
  540. return QDF_STATUS_E_NULL_VALUE;
  541. }
  542. ppe_vp_profile = &be_vdev->ppe_vp_profile;
  543. src_info = ppe_vp_profile->vp_num;
  544. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  545. vdev_id, src_info);
  546. }
  547. return qdf_status;
  548. }
  549. #else
  550. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  551. {
  552. return QDF_STATUS_SUCCESS;
  553. }
  554. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  555. {
  556. return QDF_STATUS_SUCCESS;
  557. }
  558. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  559. {
  560. return QDF_STATUS_SUCCESS;
  561. }
  562. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  563. {
  564. return QDF_STATUS_SUCCESS;
  565. }
  566. static inline
  567. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  568. struct dp_vdev_be *be_vdev)
  569. {
  570. return QDF_STATUS_SUCCESS;
  571. }
  572. #endif /* WLAN_SUPPORT_PPEDS */
  573. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  574. {
  575. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  576. int i = 0;
  577. dp_soc_ppeds_detach_be(soc);
  578. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  579. dp_hw_cookie_conversion_detach(be_soc,
  580. &be_soc->tx_cc_ctx[i]);
  581. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  582. dp_hw_cookie_conversion_detach(be_soc,
  583. &be_soc->rx_cc_ctx[i]);
  584. qdf_mem_free(be_soc->page_desc_base);
  585. be_soc->page_desc_base = NULL;
  586. return QDF_STATUS_SUCCESS;
  587. }
  588. #ifdef WLAN_MLO_MULTI_CHIP
  589. #ifdef WLAN_MCAST_MLO
  590. static inline void
  591. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  592. {
  593. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  594. be_vdev->mcast_primary = false;
  595. be_vdev->seq_num = 0;
  596. hal_tx_mcast_mlo_reinject_routing_set(
  597. soc->hal_soc,
  598. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  599. if (vdev->opmode == wlan_op_mode_ap) {
  600. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  601. vdev->vdev_id,
  602. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  603. }
  604. }
  605. static inline void
  606. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  607. {
  608. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  609. be_vdev->seq_num = 0;
  610. be_vdev->mcast_primary = false;
  611. vdev->mlo_vdev = false;
  612. }
  613. #else
  614. static inline void
  615. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  616. {
  617. }
  618. static inline void
  619. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  620. {
  621. }
  622. #endif
  623. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  624. {
  625. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  626. qdf_mem_set(be_vdev->partner_vdev_list,
  627. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  628. CDP_INVALID_VDEV_ID);
  629. }
  630. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  631. struct cdp_lro_hash_config *lro_hash)
  632. {
  633. dp_mlo_get_rx_hash_key(soc, lro_hash);
  634. }
  635. #else
  636. static inline void
  637. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  638. {
  639. }
  640. static inline void
  641. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  642. {
  643. }
  644. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  645. {
  646. }
  647. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  648. struct cdp_lro_hash_config *lro_hash)
  649. {
  650. dp_get_rx_hash_key_bytes(lro_hash);
  651. }
  652. #endif
  653. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  654. struct cdp_soc_attach_params *params)
  655. {
  656. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  657. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  658. uint32_t max_tx_rx_desc_num, num_spt_pages;
  659. uint32_t num_entries;
  660. int i = 0;
  661. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  662. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  663. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  664. /* estimate how many SPT DDR pages needed */
  665. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  666. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  667. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  668. be_soc->page_desc_base = qdf_mem_malloc(
  669. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  670. if (!be_soc->page_desc_base) {
  671. dp_err("spt page descs allocation failed");
  672. return QDF_STATUS_E_NOMEM;
  673. }
  674. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  675. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  676. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  677. goto fail;
  678. dp_soc_mlo_fill_params(soc, params);
  679. qdf_status = dp_soc_ppeds_attach_be(soc);
  680. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  681. goto fail;
  682. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  683. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  684. qdf_status =
  685. dp_hw_cookie_conversion_attach(be_soc,
  686. &be_soc->tx_cc_ctx[i],
  687. num_entries,
  688. DP_TX_DESC_TYPE, i);
  689. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  690. goto fail;
  691. }
  692. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  693. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  694. goto fail;
  695. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  696. num_entries =
  697. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  698. qdf_status =
  699. dp_hw_cookie_conversion_attach(be_soc,
  700. &be_soc->rx_cc_ctx[i],
  701. num_entries,
  702. DP_RX_DESC_BUF_TYPE, i);
  703. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  704. goto fail;
  705. }
  706. return qdf_status;
  707. fail:
  708. dp_soc_detach_be(soc);
  709. return qdf_status;
  710. }
  711. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  712. {
  713. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  714. int i = 0;
  715. dp_tx_deinit_bank_profiles(be_soc);
  716. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  717. dp_hw_cookie_conversion_deinit(be_soc,
  718. &be_soc->tx_cc_ctx[i]);
  719. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  720. dp_hw_cookie_conversion_deinit(be_soc,
  721. &be_soc->rx_cc_ctx[i]);
  722. dp_ppeds_deinit_soc_be(soc);
  723. return QDF_STATUS_SUCCESS;
  724. }
  725. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  726. {
  727. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  728. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  729. int i = 0;
  730. dp_ppeds_init_soc_be(soc);
  731. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  732. qdf_status =
  733. dp_hw_cookie_conversion_init(be_soc,
  734. &be_soc->tx_cc_ctx[i]);
  735. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  736. goto fail;
  737. }
  738. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  739. qdf_status =
  740. dp_hw_cookie_conversion_init(be_soc,
  741. &be_soc->rx_cc_ctx[i]);
  742. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  743. goto fail;
  744. }
  745. /* route vdev_id mismatch notification via FW completion */
  746. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  747. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  748. qdf_status = dp_tx_init_bank_profiles(be_soc);
  749. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  750. goto fail;
  751. /* write WBM/REO cookie conversion CFG register */
  752. dp_cc_reg_cfg_init(soc, true);
  753. return qdf_status;
  754. fail:
  755. dp_soc_deinit_be(soc);
  756. return qdf_status;
  757. }
  758. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  759. struct cdp_pdev_attach_params *params)
  760. {
  761. dp_pdev_mlo_fill_params(pdev, params);
  762. return QDF_STATUS_SUCCESS;
  763. }
  764. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  765. {
  766. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  767. return QDF_STATUS_SUCCESS;
  768. }
  769. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  770. {
  771. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  772. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  773. struct dp_pdev *pdev = vdev->pdev;
  774. if (vdev->opmode == wlan_op_mode_monitor)
  775. return QDF_STATUS_SUCCESS;
  776. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  777. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  778. vdev->bank_id = be_vdev->bank_id;
  779. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  780. QDF_BUG(0);
  781. return QDF_STATUS_E_FAULT;
  782. }
  783. if (vdev->opmode == wlan_op_mode_sta) {
  784. if (soc->cdp_soc.ol_ops->set_mec_timer)
  785. soc->cdp_soc.ol_ops->set_mec_timer(
  786. soc->ctrl_psoc,
  787. vdev->vdev_id,
  788. DP_AST_AGING_TIMER_DEFAULT_MS);
  789. if (pdev->isolation)
  790. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  791. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  792. else
  793. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  794. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  795. }
  796. dp_mlo_mcast_init(soc, vdev);
  797. dp_mlo_init_ptnr_list(vdev);
  798. return QDF_STATUS_SUCCESS;
  799. }
  800. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  801. {
  802. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  803. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  804. if (vdev->opmode == wlan_op_mode_monitor)
  805. return QDF_STATUS_SUCCESS;
  806. if (vdev->opmode == wlan_op_mode_ap)
  807. dp_mlo_mcast_deinit(soc, vdev);
  808. dp_tx_put_bank_profile(be_soc, be_vdev);
  809. dp_clr_mlo_ptnr_list(soc, vdev);
  810. return QDF_STATUS_SUCCESS;
  811. }
  812. #ifdef WLAN_SUPPORT_PPEDS
  813. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  814. {
  815. struct dp_vdev_be *be_vdev;
  816. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  817. be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
  818. if (!be_vdev) {
  819. qdf_err("BE vap is null");
  820. return QDF_STATUS_E_NULL_VALUE;
  821. }
  822. /*
  823. * Check if PPE DS routing is enabled on the associated vap.
  824. */
  825. if (be_vdev->ppe_vp_enabled == PPE_VP_USER_TYPE_DS)
  826. qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev);
  827. return qdf_status;
  828. }
  829. #else
  830. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  831. {
  832. return QDF_STATUS_SUCCESS;
  833. }
  834. #endif
  835. qdf_size_t dp_get_soc_context_size_be(void)
  836. {
  837. return sizeof(struct dp_soc_be);
  838. }
  839. #ifdef CONFIG_WORD_BASED_TLV
  840. /**
  841. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  842. * @soc: Common DP soc handle
  843. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  844. *
  845. * Return: none
  846. */
  847. static inline void
  848. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  849. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  850. {
  851. htt_tlv_filter->rx_msdu_end_wmask =
  852. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  853. htt_tlv_filter->rx_mpdu_start_wmask =
  854. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  855. }
  856. #else
  857. static inline void
  858. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  859. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  860. {
  861. }
  862. #endif
  863. #ifdef WLAN_SUPPORT_PPEDS
  864. static
  865. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  866. int ring_type, int ring_num)
  867. {
  868. if (srng->irq >= 0) {
  869. if (ring_type == WBM2SW_RELEASE &&
  870. ring_num == WBM2_SW_PPE_REL_RING_ID)
  871. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  872. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  873. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  874. dp_get_ppe_ds_ctxt(soc));
  875. }
  876. }
  877. static
  878. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  879. int vector, int ring_type, int ring_num)
  880. {
  881. int irq = -1, ret = 0;
  882. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  883. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  884. srng->irq = -1;
  885. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  886. if (ring_type == WBM2SW_RELEASE &&
  887. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  888. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  889. "pci%d_ppe_wbm_rel", pci_slot);
  890. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  891. dp_ppeds_handle_tx_comp,
  892. IRQF_SHARED | IRQF_NO_SUSPEND,
  893. be_soc->irq_name[2], (void *)soc);
  894. if (ret)
  895. goto fail;
  896. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  897. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  898. "pci%d_reo2ppe", pci_slot);
  899. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  900. dp_ppe_ds_reo2ppe_irq_handler,
  901. IRQF_SHARED | IRQF_NO_SUSPEND,
  902. be_soc->irq_name[0],
  903. dp_get_ppe_ds_ctxt(soc));
  904. if (ret)
  905. goto fail;
  906. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  907. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  908. "pci%d_ppe2tcl", pci_slot);
  909. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  910. dp_ppe_ds_ppe2tcl_irq_handler,
  911. IRQF_SHARED | IRQF_NO_SUSPEND,
  912. be_soc->irq_name[1],
  913. dp_get_ppe_ds_ctxt(soc));
  914. if (ret)
  915. goto fail;
  916. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  917. } else {
  918. return 0;
  919. }
  920. srng->irq = irq;
  921. dp_info("Registered irq %d for soc %pK ring type %d",
  922. irq, soc, ring_type);
  923. return 0;
  924. fail:
  925. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  926. ring_type, irq, vector);
  927. return ret;
  928. }
  929. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  930. {
  931. if (srng->irq >= 0)
  932. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  933. }
  934. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  935. {
  936. if (srng->irq >= 0)
  937. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  938. }
  939. #endif
  940. #ifdef NO_RX_PKT_HDR_TLV
  941. /**
  942. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  943. * @soc: Common DP soc handle
  944. *
  945. * Return: QDF_STATUS
  946. */
  947. static QDF_STATUS
  948. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  949. {
  950. int i;
  951. int mac_id;
  952. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  953. struct dp_srng *rx_mac_srng;
  954. QDF_STATUS status = QDF_STATUS_SUCCESS;
  955. /*
  956. * In Beryllium chipset msdu_start, mpdu_end
  957. * and rx_attn are part of msdu_end/mpdu_start
  958. */
  959. htt_tlv_filter.msdu_start = 0;
  960. htt_tlv_filter.mpdu_end = 0;
  961. htt_tlv_filter.attention = 0;
  962. htt_tlv_filter.mpdu_start = 1;
  963. htt_tlv_filter.msdu_end = 1;
  964. htt_tlv_filter.packet = 1;
  965. htt_tlv_filter.packet_header = 0;
  966. htt_tlv_filter.ppdu_start = 0;
  967. htt_tlv_filter.ppdu_end = 0;
  968. htt_tlv_filter.ppdu_end_user_stats = 0;
  969. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  970. htt_tlv_filter.ppdu_end_status_done = 0;
  971. htt_tlv_filter.enable_fp = 1;
  972. htt_tlv_filter.enable_md = 0;
  973. htt_tlv_filter.enable_md = 0;
  974. htt_tlv_filter.enable_mo = 0;
  975. htt_tlv_filter.fp_mgmt_filter = 0;
  976. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  977. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  978. FILTER_DATA_MCAST |
  979. FILTER_DATA_DATA);
  980. htt_tlv_filter.mo_mgmt_filter = 0;
  981. htt_tlv_filter.mo_ctrl_filter = 0;
  982. htt_tlv_filter.mo_data_filter = 0;
  983. htt_tlv_filter.md_data_filter = 0;
  984. htt_tlv_filter.offset_valid = true;
  985. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  986. htt_tlv_filter.rx_mpdu_end_offset = 0;
  987. htt_tlv_filter.rx_msdu_start_offset = 0;
  988. htt_tlv_filter.rx_attn_offset = 0;
  989. /*
  990. * For monitor mode, the packet hdr tlv is enabled later during
  991. * filter update
  992. */
  993. if (soc->cdp_soc.ol_ops->get_con_mode &&
  994. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  995. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  996. else
  997. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  998. /*Not subscribing rx_pkt_header*/
  999. htt_tlv_filter.rx_header_offset = 0;
  1000. htt_tlv_filter.rx_mpdu_start_offset =
  1001. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1002. htt_tlv_filter.rx_msdu_end_offset =
  1003. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1004. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1005. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1006. struct dp_pdev *pdev = soc->pdev_list[i];
  1007. if (!pdev)
  1008. continue;
  1009. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1010. int mac_for_pdev =
  1011. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1012. /*
  1013. * Obtain lmac id from pdev to access the LMAC ring
  1014. * in soc context
  1015. */
  1016. int lmac_id =
  1017. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1018. pdev->pdev_id);
  1019. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1020. if (!rx_mac_srng->hal_srng)
  1021. continue;
  1022. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1023. rx_mac_srng->hal_srng,
  1024. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1025. &htt_tlv_filter);
  1026. }
  1027. }
  1028. return status;
  1029. }
  1030. #else
  1031. /**
  1032. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1033. * @soc: Common DP soc handle
  1034. *
  1035. * Return: QDF_STATUS
  1036. */
  1037. static QDF_STATUS
  1038. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1039. {
  1040. int i;
  1041. int mac_id;
  1042. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1043. struct dp_srng *rx_mac_srng;
  1044. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1045. /*
  1046. * In Beryllium chipset msdu_start, mpdu_end
  1047. * and rx_attn are part of msdu_end/mpdu_start
  1048. */
  1049. htt_tlv_filter.msdu_start = 0;
  1050. htt_tlv_filter.mpdu_end = 0;
  1051. htt_tlv_filter.attention = 0;
  1052. htt_tlv_filter.mpdu_start = 1;
  1053. htt_tlv_filter.msdu_end = 1;
  1054. htt_tlv_filter.packet = 1;
  1055. htt_tlv_filter.packet_header = 1;
  1056. htt_tlv_filter.ppdu_start = 0;
  1057. htt_tlv_filter.ppdu_end = 0;
  1058. htt_tlv_filter.ppdu_end_user_stats = 0;
  1059. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1060. htt_tlv_filter.ppdu_end_status_done = 0;
  1061. htt_tlv_filter.enable_fp = 1;
  1062. htt_tlv_filter.enable_md = 0;
  1063. htt_tlv_filter.enable_md = 0;
  1064. htt_tlv_filter.enable_mo = 0;
  1065. htt_tlv_filter.fp_mgmt_filter = 0;
  1066. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1067. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1068. FILTER_DATA_MCAST |
  1069. FILTER_DATA_DATA);
  1070. htt_tlv_filter.mo_mgmt_filter = 0;
  1071. htt_tlv_filter.mo_ctrl_filter = 0;
  1072. htt_tlv_filter.mo_data_filter = 0;
  1073. htt_tlv_filter.md_data_filter = 0;
  1074. htt_tlv_filter.offset_valid = true;
  1075. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1076. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1077. htt_tlv_filter.rx_msdu_start_offset = 0;
  1078. htt_tlv_filter.rx_attn_offset = 0;
  1079. /*
  1080. * For monitor mode, the packet hdr tlv is enabled later during
  1081. * filter update
  1082. */
  1083. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1084. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1085. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1086. else
  1087. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1088. htt_tlv_filter.rx_header_offset =
  1089. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1090. htt_tlv_filter.rx_mpdu_start_offset =
  1091. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1092. htt_tlv_filter.rx_msdu_end_offset =
  1093. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1094. dp_info("TLV subscription\n"
  1095. "msdu_start %d, mpdu_end %d, attention %d"
  1096. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1097. "TLV offsets\n"
  1098. "msdu_start %d, mpdu_end %d, attention %d"
  1099. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1100. htt_tlv_filter.msdu_start,
  1101. htt_tlv_filter.mpdu_end,
  1102. htt_tlv_filter.attention,
  1103. htt_tlv_filter.mpdu_start,
  1104. htt_tlv_filter.msdu_end,
  1105. htt_tlv_filter.packet_header,
  1106. htt_tlv_filter.packet,
  1107. htt_tlv_filter.rx_msdu_start_offset,
  1108. htt_tlv_filter.rx_mpdu_end_offset,
  1109. htt_tlv_filter.rx_attn_offset,
  1110. htt_tlv_filter.rx_mpdu_start_offset,
  1111. htt_tlv_filter.rx_msdu_end_offset,
  1112. htt_tlv_filter.rx_header_offset,
  1113. htt_tlv_filter.rx_packet_offset);
  1114. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1115. struct dp_pdev *pdev = soc->pdev_list[i];
  1116. if (!pdev)
  1117. continue;
  1118. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1119. int mac_for_pdev =
  1120. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1121. /*
  1122. * Obtain lmac id from pdev to access the LMAC ring
  1123. * in soc context
  1124. */
  1125. int lmac_id =
  1126. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1127. pdev->pdev_id);
  1128. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1129. if (!rx_mac_srng->hal_srng)
  1130. continue;
  1131. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1132. rx_mac_srng->hal_srng,
  1133. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1134. &htt_tlv_filter);
  1135. }
  1136. }
  1137. return status;
  1138. }
  1139. #endif
  1140. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1141. /**
  1142. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1143. * near-full IRQs.
  1144. * @soc: Datapath SoC handle
  1145. * @int_ctx: Interrupt context
  1146. * @dp_budget: Budget of the work that can be done in the bottom half
  1147. *
  1148. * Return: work done in the handler
  1149. */
  1150. static uint32_t
  1151. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1152. uint32_t dp_budget)
  1153. {
  1154. int ring = 0;
  1155. int budget = dp_budget;
  1156. uint32_t work_done = 0;
  1157. uint32_t remaining_quota = dp_budget;
  1158. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1159. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1160. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1161. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1162. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1163. rx_near_full_grp_2_mask;
  1164. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1165. rx_near_full_mask,
  1166. tx_ring_near_full_mask);
  1167. if (rx_near_full_mask) {
  1168. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1169. if (!(rx_near_full_mask & (1 << ring)))
  1170. continue;
  1171. work_done = dp_rx_nf_process(int_ctx,
  1172. soc->reo_dest_ring[ring].hal_srng,
  1173. ring, remaining_quota);
  1174. if (work_done) {
  1175. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1176. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1177. rx_near_full_mask, ring,
  1178. work_done,
  1179. budget);
  1180. budget -= work_done;
  1181. if (budget <= 0)
  1182. goto budget_done;
  1183. remaining_quota = budget;
  1184. }
  1185. }
  1186. }
  1187. if (tx_ring_near_full_mask) {
  1188. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1189. if (!(tx_ring_near_full_mask & (1 << ring)))
  1190. continue;
  1191. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1192. soc->tx_comp_ring[ring].hal_srng,
  1193. ring, remaining_quota);
  1194. if (work_done) {
  1195. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1196. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1197. tx_ring_near_full_mask, ring,
  1198. work_done, budget);
  1199. budget -= work_done;
  1200. if (budget <= 0)
  1201. break;
  1202. remaining_quota = budget;
  1203. }
  1204. }
  1205. }
  1206. intr_stats->num_near_full_masks++;
  1207. budget_done:
  1208. return dp_budget - budget;
  1209. }
  1210. /**
  1211. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1212. * state and set the reap_limit appropriately
  1213. * as per the near full state
  1214. * @soc: Datapath soc handle
  1215. * @dp_srng: Datapath handle for SRNG
  1216. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1217. * the srng near-full state
  1218. *
  1219. * Return: 1, if the srng is in near-full state
  1220. * 0, if the srng is not in near-full state
  1221. */
  1222. static int
  1223. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1224. struct dp_srng *dp_srng,
  1225. int *max_reap_limit)
  1226. {
  1227. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1228. }
  1229. /**
  1230. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1231. * near full IRQ handling operations.
  1232. * @arch_ops: arch ops handle
  1233. *
  1234. * Return: none
  1235. */
  1236. static inline void
  1237. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1238. {
  1239. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1240. arch_ops->dp_srng_test_and_update_nf_params =
  1241. dp_srng_test_and_update_nf_params_be;
  1242. }
  1243. #else
  1244. static inline void
  1245. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1246. {
  1247. }
  1248. #endif
  1249. #ifdef WLAN_SUPPORT_PPEDS
  1250. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1251. {
  1252. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1253. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1254. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1255. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1256. return;
  1257. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1258. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1259. be_soc->ppe2tcl_ring.alloc_size,
  1260. soc->ctrl_psoc,
  1261. WLAN_MD_DP_SRNG_PPE2TCL,
  1262. "ppe2tcl_ring");
  1263. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1264. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1265. be_soc->reo2ppe_ring.alloc_size,
  1266. soc->ctrl_psoc,
  1267. WLAN_MD_DP_SRNG_REO2PPE,
  1268. "reo2ppe_ring");
  1269. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1270. WBM2_SW_PPE_REL_RING_ID);
  1271. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1272. be_soc->ppeds_wbm_release_ring.alloc_size,
  1273. soc->ctrl_psoc,
  1274. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1275. "ppeds_wbm_release_ring");
  1276. }
  1277. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1278. {
  1279. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1280. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1281. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1282. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1283. return;
  1284. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1285. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1286. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1287. }
  1288. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1289. {
  1290. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1291. uint32_t entries;
  1292. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1293. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1294. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1295. return QDF_STATUS_SUCCESS;
  1296. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1297. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1298. entries, 0)) {
  1299. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1300. goto fail;
  1301. }
  1302. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1303. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1304. entries, 0)) {
  1305. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1306. goto fail;
  1307. }
  1308. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1309. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1310. entries, 1)) {
  1311. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1312. soc);
  1313. goto fail;
  1314. }
  1315. return QDF_STATUS_SUCCESS;
  1316. fail:
  1317. dp_soc_ppeds_srng_free(soc);
  1318. return QDF_STATUS_E_NOMEM;
  1319. }
  1320. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1321. {
  1322. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1323. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1324. hal_soc_handle_t hal_soc = soc->hal_soc;
  1325. struct dp_ppe_ds_idxs idx = {0};
  1326. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1327. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1328. return QDF_STATUS_SUCCESS;
  1329. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1330. dp_err("%pK: ppeds registration failed", soc);
  1331. goto fail;
  1332. }
  1333. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1334. idx.reo2ppe_start_idx)) {
  1335. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1336. goto fail;
  1337. }
  1338. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1339. be_soc->reo2ppe_ring.alloc_size,
  1340. soc->ctrl_psoc,
  1341. WLAN_MD_DP_SRNG_REO2PPE,
  1342. "reo2ppe_ring");
  1343. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1344. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1345. idx.ppe2tcl_start_idx)) {
  1346. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1347. goto fail;
  1348. }
  1349. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1350. be_soc->ppe2tcl_ring.alloc_size,
  1351. soc->ctrl_psoc,
  1352. WLAN_MD_DP_SRNG_PPE2TCL,
  1353. "ppe2tcl_ring");
  1354. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1355. be_soc->ppe2tcl_ring.hal_srng,
  1356. WBM2_SW_PPE_REL_MAP_ID);
  1357. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1358. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1359. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1360. soc);
  1361. goto fail;
  1362. }
  1363. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1364. be_soc->ppeds_wbm_release_ring.alloc_size,
  1365. soc->ctrl_psoc,
  1366. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1367. "ppeds_wbm_release_ring");
  1368. return QDF_STATUS_SUCCESS;
  1369. fail:
  1370. dp_soc_ppeds_srng_deinit(soc);
  1371. return QDF_STATUS_E_NOMEM;
  1372. }
  1373. #else
  1374. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1375. {
  1376. }
  1377. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1378. {
  1379. }
  1380. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1381. {
  1382. return QDF_STATUS_SUCCESS;
  1383. }
  1384. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1385. {
  1386. return QDF_STATUS_SUCCESS;
  1387. }
  1388. #endif
  1389. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1390. {
  1391. uint32_t i;
  1392. dp_soc_ppeds_srng_deinit(soc);
  1393. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1394. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1395. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1396. RXDMA_BUF, 0);
  1397. }
  1398. }
  1399. }
  1400. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1401. {
  1402. uint32_t i;
  1403. dp_soc_ppeds_srng_free(soc);
  1404. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1405. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1406. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1407. }
  1408. }
  1409. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1410. {
  1411. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1412. uint32_t ring_size;
  1413. uint32_t i;
  1414. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1415. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1416. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1417. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1418. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1419. RXDMA_BUF, ring_size, 0)) {
  1420. dp_err("%pK: dp_srng_alloc failed refill ring",
  1421. soc);
  1422. goto fail;
  1423. }
  1424. }
  1425. }
  1426. if (dp_soc_ppeds_srng_alloc(soc)) {
  1427. dp_err("%pK: ppe rings alloc failed",
  1428. soc);
  1429. goto fail;
  1430. }
  1431. return QDF_STATUS_SUCCESS;
  1432. fail:
  1433. dp_soc_srng_free_be(soc);
  1434. return QDF_STATUS_E_NOMEM;
  1435. }
  1436. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1437. {
  1438. int i = 0;
  1439. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1440. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1441. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1442. RXDMA_BUF, 0, 0)) {
  1443. dp_err("%pK: dp_srng_init failed refill ring",
  1444. soc);
  1445. goto fail;
  1446. }
  1447. }
  1448. }
  1449. if (dp_soc_ppeds_srng_init(soc)) {
  1450. dp_err("%pK: ppe ds rings init failed",
  1451. soc);
  1452. goto fail;
  1453. }
  1454. return QDF_STATUS_SUCCESS;
  1455. fail:
  1456. dp_soc_srng_deinit_be(soc);
  1457. return QDF_STATUS_E_NOMEM;
  1458. }
  1459. #ifdef WLAN_FEATURE_11BE_MLO
  1460. static inline unsigned
  1461. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1462. union dp_align_mac_addr *mac_addr)
  1463. {
  1464. uint32_t index;
  1465. index =
  1466. mac_addr->align2.bytes_ab ^
  1467. mac_addr->align2.bytes_cd ^
  1468. mac_addr->align2.bytes_ef;
  1469. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1470. index &= mld_hash_obj->mld_peer_hash.mask;
  1471. return index;
  1472. }
  1473. QDF_STATUS
  1474. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1475. int hash_elems)
  1476. {
  1477. int i, log2;
  1478. if (!mld_hash_obj)
  1479. return QDF_STATUS_E_FAILURE;
  1480. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1481. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1482. log2 = dp_log2_ceil(hash_elems);
  1483. hash_elems = 1 << log2;
  1484. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1485. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1486. /* allocate an array of TAILQ peer object lists */
  1487. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1488. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1489. if (!mld_hash_obj->mld_peer_hash.bins)
  1490. return QDF_STATUS_E_NOMEM;
  1491. for (i = 0; i < hash_elems; i++)
  1492. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1493. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1494. return QDF_STATUS_SUCCESS;
  1495. }
  1496. void
  1497. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1498. {
  1499. if (!mld_hash_obj)
  1500. return;
  1501. if (mld_hash_obj->mld_peer_hash.bins) {
  1502. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1503. mld_hash_obj->mld_peer_hash.bins = NULL;
  1504. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1505. }
  1506. }
  1507. #ifdef WLAN_MLO_MULTI_CHIP
  1508. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1509. {
  1510. /* In case of MULTI chip MLO peer hash table when MLO global object
  1511. * is created, avoid from SOC attach path
  1512. */
  1513. return QDF_STATUS_SUCCESS;
  1514. }
  1515. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1516. {
  1517. }
  1518. #else
  1519. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1520. {
  1521. dp_mld_peer_hash_obj_t mld_hash_obj;
  1522. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1523. if (!mld_hash_obj)
  1524. return QDF_STATUS_E_FAILURE;
  1525. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1526. }
  1527. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1528. {
  1529. dp_mld_peer_hash_obj_t mld_hash_obj;
  1530. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1531. if (!mld_hash_obj)
  1532. return;
  1533. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1534. }
  1535. #endif
  1536. static struct dp_peer *
  1537. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1538. uint8_t *peer_mac_addr,
  1539. int mac_addr_is_aligned,
  1540. enum dp_mod_id mod_id,
  1541. uint8_t vdev_id)
  1542. {
  1543. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1544. uint32_t index;
  1545. struct dp_peer *peer;
  1546. struct dp_vdev *vdev;
  1547. dp_mld_peer_hash_obj_t mld_hash_obj;
  1548. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1549. if (!mld_hash_obj)
  1550. return NULL;
  1551. if (!mld_hash_obj->mld_peer_hash.bins)
  1552. return NULL;
  1553. if (mac_addr_is_aligned) {
  1554. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1555. } else {
  1556. qdf_mem_copy(
  1557. &local_mac_addr_aligned.raw[0],
  1558. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1559. mac_addr = &local_mac_addr_aligned;
  1560. }
  1561. if (vdev_id != DP_VDEV_ALL) {
  1562. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1563. if (!vdev) {
  1564. dp_err("vdev is null\n");
  1565. return NULL;
  1566. }
  1567. } else {
  1568. vdev = NULL;
  1569. }
  1570. /* search mld peer table if no link peer for given mac address */
  1571. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1572. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1573. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1574. hash_list_elem) {
  1575. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1576. if ((vdev_id == DP_VDEV_ALL) || (
  1577. dp_peer_find_mac_addr_cmp(
  1578. &peer->vdev->mld_mac_addr,
  1579. &vdev->mld_mac_addr) == 0)) {
  1580. /* take peer reference before returning */
  1581. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1582. QDF_STATUS_SUCCESS)
  1583. peer = NULL;
  1584. if (vdev)
  1585. dp_vdev_unref_delete(soc, vdev, mod_id);
  1586. qdf_spin_unlock_bh(
  1587. &mld_hash_obj->mld_peer_hash_lock);
  1588. return peer;
  1589. }
  1590. }
  1591. }
  1592. if (vdev)
  1593. dp_vdev_unref_delete(soc, vdev, mod_id);
  1594. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1595. return NULL; /* failure */
  1596. }
  1597. static void
  1598. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1599. {
  1600. uint32_t index;
  1601. struct dp_peer *tmppeer = NULL;
  1602. int found = 0;
  1603. dp_mld_peer_hash_obj_t mld_hash_obj;
  1604. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1605. if (!mld_hash_obj)
  1606. return;
  1607. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1608. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1609. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1610. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1611. hash_list_elem) {
  1612. if (tmppeer == peer) {
  1613. found = 1;
  1614. break;
  1615. }
  1616. }
  1617. QDF_ASSERT(found);
  1618. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1619. hash_list_elem);
  1620. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1621. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1622. }
  1623. static void
  1624. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1625. {
  1626. uint32_t index;
  1627. dp_mld_peer_hash_obj_t mld_hash_obj;
  1628. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1629. if (!mld_hash_obj)
  1630. return;
  1631. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1632. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1633. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1634. DP_MOD_ID_CONFIG))) {
  1635. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1636. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1637. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1638. return;
  1639. }
  1640. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1641. hash_list_elem);
  1642. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1643. }
  1644. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1645. {
  1646. uint32_t index;
  1647. struct dp_peer *peer;
  1648. dp_mld_peer_hash_obj_t mld_hash_obj;
  1649. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1650. if (!mld_hash_obj)
  1651. return;
  1652. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1653. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1654. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1655. hash_list_elem) {
  1656. dp_print_peer_ast_entries(soc, peer, NULL);
  1657. }
  1658. }
  1659. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1660. }
  1661. #endif
  1662. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1663. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1664. struct dp_vdev *vdev)
  1665. {
  1666. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1667. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1668. hal_soc_handle_t hal_soc = soc->hal_soc;
  1669. uint8_t vdev_id = vdev->vdev_id;
  1670. if (vdev->opmode == wlan_op_mode_sta) {
  1671. if (vdev->pdev->isolation)
  1672. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1673. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1674. else
  1675. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1676. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1677. } else if (vdev->opmode == wlan_op_mode_ap) {
  1678. hal_tx_mcast_mlo_reinject_routing_set(
  1679. hal_soc,
  1680. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1681. if (vdev->mlo_vdev) {
  1682. hal_tx_vdev_mcast_ctrl_set(
  1683. hal_soc,
  1684. vdev_id,
  1685. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1686. } else {
  1687. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1688. vdev_id,
  1689. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1690. }
  1691. }
  1692. }
  1693. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1694. {
  1695. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1696. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1697. union hal_tx_bank_config *bank_config;
  1698. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1699. return;
  1700. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1701. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1702. be_vdev->bank_id);
  1703. }
  1704. #endif
  1705. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1706. defined(WLAN_MCAST_MLO)
  1707. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  1708. struct dp_vdev *ptnr_vdev,
  1709. void *arg)
  1710. {
  1711. struct dp_vdev_be *be_ptnr_vdev =
  1712. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  1713. be_ptnr_vdev->mcast_primary = false;
  1714. }
  1715. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1716. struct dp_vdev *vdev,
  1717. cdp_config_param_type val)
  1718. {
  1719. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1720. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1721. be_vdev->vdev.pdev->soc);
  1722. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1723. vdev->mlo_vdev = true;
  1724. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1725. vdev->vdev_id,
  1726. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1727. if (be_vdev->mcast_primary) {
  1728. dp_mcast_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  1729. dp_mlo_mcast_reset_pri_mcast,
  1730. (void *)&be_vdev->mcast_primary,
  1731. DP_MOD_ID_TX_MCAST);
  1732. }
  1733. }
  1734. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1735. struct dp_vdev *vdev,
  1736. cdp_config_param_type val)
  1737. {
  1738. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1739. be_vdev->mcast_primary = false;
  1740. vdev->mlo_vdev = false;
  1741. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1742. vdev->vdev_id,
  1743. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1744. }
  1745. /**
  1746. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  1747. * params related to multicast
  1748. * @soc: DP soc handle
  1749. * @vdev: pointer to vdev structure
  1750. * @val: buffer address
  1751. *
  1752. * Return: QDF_STATUS
  1753. */
  1754. static
  1755. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1756. struct dp_vdev *vdev,
  1757. cdp_config_param_type *val)
  1758. {
  1759. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1760. if (be_vdev->mcast_primary)
  1761. val->cdp_vdev_param_mcast_vdev = true;
  1762. else
  1763. val->cdp_vdev_param_mcast_vdev = false;
  1764. return QDF_STATUS_SUCCESS;
  1765. }
  1766. #else
  1767. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1768. struct dp_vdev *vdev,
  1769. cdp_config_param_type val)
  1770. {
  1771. }
  1772. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1773. struct dp_vdev *vdev,
  1774. cdp_config_param_type val)
  1775. {
  1776. }
  1777. static
  1778. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1779. struct dp_vdev *vdev,
  1780. cdp_config_param_type *val)
  1781. {
  1782. return QDF_STATUS_SUCCESS;
  1783. }
  1784. #endif
  1785. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1786. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1787. uint8_t tx_ring_id,
  1788. uint8_t bm_id)
  1789. {
  1790. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1791. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1792. bm_id);
  1793. }
  1794. #else
  1795. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1796. uint8_t tx_ring_id,
  1797. uint8_t bm_id)
  1798. {
  1799. }
  1800. #endif
  1801. /**
  1802. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  1803. * @soc: DP soc handle
  1804. * @vdev: pointer to vdev structure
  1805. * @param: parameter type to get value
  1806. * @val: value
  1807. *
  1808. * Return: QDF_STATUS
  1809. */
  1810. static
  1811. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1812. struct dp_vdev *vdev,
  1813. enum cdp_vdev_param_type param,
  1814. cdp_config_param_type val)
  1815. {
  1816. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1817. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1818. switch (param) {
  1819. case CDP_TX_ENCAP_TYPE:
  1820. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1821. case CDP_UPDATE_TDLS_FLAGS:
  1822. dp_tx_update_bank_profile(be_soc, be_vdev);
  1823. break;
  1824. case CDP_ENABLE_CIPHER:
  1825. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1826. dp_tx_update_bank_profile(be_soc, be_vdev);
  1827. break;
  1828. case CDP_SET_MCAST_VDEV:
  1829. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  1830. break;
  1831. case CDP_RESET_MLO_MCAST_VDEV:
  1832. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  1833. break;
  1834. default:
  1835. dp_warn("invalid param %d", param);
  1836. break;
  1837. }
  1838. return QDF_STATUS_SUCCESS;
  1839. }
  1840. #ifdef WLAN_FEATURE_11BE_MLO
  1841. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1842. static inline void
  1843. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1844. {
  1845. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1846. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1847. /*
  1848. * Double the peers since we use ML indication bit
  1849. * alongwith peer_id to find peers.
  1850. */
  1851. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1852. }
  1853. #else
  1854. static inline void
  1855. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1856. {
  1857. soc->max_peer_id =
  1858. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1859. }
  1860. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1861. #else
  1862. static inline void
  1863. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1864. {
  1865. soc->max_peer_id = soc->max_peers;
  1866. }
  1867. #endif /* WLAN_FEATURE_11BE_MLO */
  1868. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1869. {
  1870. if (soc->host_ast_db_enable)
  1871. dp_peer_ast_hash_detach(soc);
  1872. }
  1873. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1874. {
  1875. QDF_STATUS status;
  1876. if (soc->host_ast_db_enable) {
  1877. status = dp_peer_ast_hash_attach(soc);
  1878. if (QDF_IS_STATUS_ERROR(status))
  1879. return status;
  1880. }
  1881. dp_soc_max_peer_id_set(soc);
  1882. return QDF_STATUS_SUCCESS;
  1883. }
  1884. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1885. uint8_t *dest_mac,
  1886. uint8_t vdev_id)
  1887. {
  1888. struct dp_peer *peer = NULL;
  1889. struct dp_peer *tgt_peer = NULL;
  1890. struct dp_ast_entry *ast_entry = NULL;
  1891. uint16_t peer_id;
  1892. qdf_spin_lock_bh(&soc->ast_lock);
  1893. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1894. if (!ast_entry) {
  1895. qdf_spin_unlock_bh(&soc->ast_lock);
  1896. dp_err("NULL ast entry");
  1897. return NULL;
  1898. }
  1899. peer_id = ast_entry->peer_id;
  1900. qdf_spin_unlock_bh(&soc->ast_lock);
  1901. if (peer_id == HTT_INVALID_PEER)
  1902. return NULL;
  1903. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1904. if (!peer) {
  1905. dp_err("NULL peer for peer_id:%d", peer_id);
  1906. return NULL;
  1907. }
  1908. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1909. /*
  1910. * Once tgt_peer is obtained,
  1911. * release the ref taken for original peer.
  1912. */
  1913. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1914. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1915. return tgt_peer;
  1916. }
  1917. #ifdef WLAN_FEATURE_11BE_MLO
  1918. #ifdef WLAN_MCAST_MLO
  1919. static inline void
  1920. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1921. {
  1922. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1923. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1924. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  1925. }
  1926. #else /* WLAN_MCAST_MLO */
  1927. static inline void
  1928. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1929. {
  1930. }
  1931. #endif /* WLAN_MCAST_MLO */
  1932. #ifdef WLAN_MLO_MULTI_CHIP
  1933. static inline void
  1934. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  1935. {
  1936. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  1937. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  1938. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  1939. }
  1940. #else
  1941. static inline void
  1942. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  1943. {
  1944. }
  1945. #endif
  1946. static inline void
  1947. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1948. {
  1949. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1950. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  1951. arch_ops->mlo_peer_find_hash_detach =
  1952. dp_mlo_peer_find_hash_detach_wrapper;
  1953. arch_ops->mlo_peer_find_hash_attach =
  1954. dp_mlo_peer_find_hash_attach_wrapper;
  1955. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1956. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1957. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1958. }
  1959. #else /* WLAN_FEATURE_11BE_MLO */
  1960. static inline void
  1961. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1962. {
  1963. }
  1964. #endif /* WLAN_FEATURE_11BE_MLO */
  1965. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  1966. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  1967. #define DP_LMAC_PEER_ID_MSB_MLO 3
  1968. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1969. struct cdp_peer_setup_info *setup_info,
  1970. enum cdp_host_reo_dest_ring *reo_dest,
  1971. bool *hash_based,
  1972. uint8_t *lmac_peer_id_msb)
  1973. {
  1974. struct dp_soc *soc = vdev->pdev->soc;
  1975. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1976. if (!be_soc->mlo_enabled)
  1977. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1978. hash_based);
  1979. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1980. *reo_dest = vdev->pdev->reo_dest;
  1981. /* Not a ML link peer use non-mlo */
  1982. if (!setup_info) {
  1983. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1984. return;
  1985. }
  1986. /* For STA ML VAP we do not have num links info at this point
  1987. * use MLO case always
  1988. */
  1989. if (vdev->opmode == wlan_op_mode_sta) {
  1990. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1991. return;
  1992. }
  1993. /* For AP ML VAP consider the peer as ML only it associates with
  1994. * multiple links
  1995. */
  1996. if (setup_info->num_links == 1) {
  1997. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1998. return;
  1999. }
  2000. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2001. }
  2002. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2003. uint32_t *remap0,
  2004. uint32_t *remap1,
  2005. uint32_t *remap2)
  2006. {
  2007. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2008. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2009. uint32_t reo_mlo_config =
  2010. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2011. if (!be_soc->mlo_enabled)
  2012. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2013. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2014. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2015. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2016. return true;
  2017. }
  2018. #else
  2019. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2020. struct cdp_peer_setup_info *setup_info,
  2021. enum cdp_host_reo_dest_ring *reo_dest,
  2022. bool *hash_based,
  2023. uint8_t *lmac_peer_id_msb)
  2024. {
  2025. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2026. }
  2027. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2028. uint32_t *remap0,
  2029. uint32_t *remap1,
  2030. uint32_t *remap2)
  2031. {
  2032. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2033. }
  2034. #endif
  2035. #ifdef IPA_OFFLOAD
  2036. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2037. {
  2038. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2039. return be_soc->ipa_bank_id;
  2040. }
  2041. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2042. {
  2043. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2044. }
  2045. #else /* !IPA_OFFLOAD */
  2046. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2047. {
  2048. }
  2049. #endif /* IPA_OFFLOAD */
  2050. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2051. {
  2052. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2053. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2054. arch_ops->dp_rx_process = dp_rx_process_be;
  2055. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2056. arch_ops->tx_comp_get_params_from_hal_desc =
  2057. dp_tx_comp_get_params_from_hal_desc_be;
  2058. arch_ops->dp_tx_process_htt_completion =
  2059. dp_tx_process_htt_completion_be;
  2060. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2061. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2062. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2063. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2064. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2065. dp_wbm_get_rx_desc_from_hal_desc_be;
  2066. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2067. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2068. #endif
  2069. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2070. #ifdef WIFI_MONITOR_SUPPORT
  2071. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2072. #endif
  2073. arch_ops->dp_rx_desc_cookie_2_va =
  2074. dp_rx_desc_cookie_2_va_be;
  2075. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  2076. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2077. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2078. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2079. arch_ops->txrx_soc_init = dp_soc_init_be;
  2080. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  2081. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2082. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2083. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2084. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2085. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2086. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2087. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2088. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2089. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2090. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2091. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2092. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2093. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2094. dp_rx_peer_metadata_peer_id_get_be;
  2095. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2096. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2097. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2098. dp_initialize_arch_ops_be_mlo(arch_ops);
  2099. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  2100. arch_ops->dp_peer_rx_reorder_queue_setup =
  2101. dp_peer_rx_reorder_queue_setup_be;
  2102. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2103. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  2104. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2105. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2106. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2107. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2108. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2109. #endif
  2110. #ifdef WLAN_SUPPORT_PPEDS
  2111. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2112. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2113. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2114. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2115. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2116. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2117. #endif
  2118. dp_init_near_full_arch_ops_be(arch_ops);
  2119. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2120. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2121. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2122. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2123. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2124. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2125. dp_initialize_arch_ops_be_ipa(arch_ops);
  2126. }