bengal.c 186 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd937x/wcd937x-mbhc.h"
  32. #include "codecs/wsa881x-analog.h"
  33. #include "codecs/wcd937x/wcd937x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "bengal-port-config.h"
  37. #define DRV_NAME "bengal-asoc-snd"
  38. #define __CHIPSET__ "BENGAL "
  39. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define WCD9XXX_MBHC_DEF_RLOADS 5
  54. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  55. #define CODEC_EXT_CLK_RATE 9600000
  56. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  57. #define DEV_NAME_STR_LEN 32
  58. #define WCD_MBHC_HS_V_MAX 1600
  59. #define TDM_CHANNEL_MAX 8
  60. #define DEV_NAME_STR_LEN 32
  61. /* time in us to ensure LPM doesn't go in C3/C4 */
  62. #define MSM_LL_QOS_VALUE 300
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WCN_CDC_SLIM_RX_CH_MAX 2
  65. #define WCN_CDC_SLIM_TX_CH_MAX 3
  66. enum {
  67. TDM_0 = 0,
  68. TDM_1,
  69. TDM_2,
  70. TDM_3,
  71. TDM_4,
  72. TDM_5,
  73. TDM_6,
  74. TDM_7,
  75. TDM_PORT_MAX,
  76. };
  77. enum {
  78. TDM_PRI = 0,
  79. TDM_SEC,
  80. TDM_TERT,
  81. TDM_QUAT,
  82. TDM_INTERFACE_MAX,
  83. };
  84. enum {
  85. PRIM_AUX_PCM = 0,
  86. SEC_AUX_PCM,
  87. TERT_AUX_PCM,
  88. QUAT_AUX_PCM,
  89. AUX_PCM_MAX,
  90. };
  91. enum {
  92. PRIM_MI2S = 0,
  93. SEC_MI2S,
  94. TERT_MI2S,
  95. QUAT_MI2S,
  96. MI2S_MAX,
  97. };
  98. enum {
  99. RX_CDC_DMA_RX_0 = 0,
  100. RX_CDC_DMA_RX_1,
  101. RX_CDC_DMA_RX_2,
  102. RX_CDC_DMA_RX_3,
  103. RX_CDC_DMA_RX_5,
  104. CDC_DMA_RX_MAX,
  105. };
  106. enum {
  107. TX_CDC_DMA_TX_0 = 0,
  108. TX_CDC_DMA_TX_3,
  109. TX_CDC_DMA_TX_4,
  110. VA_CDC_DMA_TX_0,
  111. VA_CDC_DMA_TX_1,
  112. VA_CDC_DMA_TX_2,
  113. CDC_DMA_TX_MAX,
  114. };
  115. enum {
  116. SLIM_RX_7 = 0,
  117. SLIM_RX_MAX,
  118. };
  119. enum {
  120. SLIM_TX_7 = 0,
  121. SLIM_TX_8,
  122. SLIM_TX_MAX,
  123. };
  124. enum {
  125. AFE_LOOPBACK_TX_IDX = 0,
  126. AFE_LOOPBACK_TX_IDX_MAX,
  127. };
  128. struct msm_asoc_mach_data {
  129. struct snd_info_entry *codec_root;
  130. int usbc_en2_gpio; /* used by gpio driver API */
  131. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  132. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  133. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  134. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  135. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  136. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  137. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  138. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  139. bool is_afe_config_done;
  140. struct device_node *fsa_handle;
  141. };
  142. struct tdm_port {
  143. u32 mode;
  144. u32 channel;
  145. };
  146. enum {
  147. EXT_DISP_RX_IDX_DP = 0,
  148. EXT_DISP_RX_IDX_DP1,
  149. EXT_DISP_RX_IDX_MAX,
  150. };
  151. struct msm_wsa881x_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct aux_codec_dev_info {
  156. struct device_node *of_node;
  157. u32 index;
  158. };
  159. struct dev_config {
  160. u32 sample_rate;
  161. u32 bit_format;
  162. u32 channels;
  163. };
  164. /* Default configuration of slimbus channels */
  165. static struct dev_config slim_rx_cfg[] = {
  166. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  167. };
  168. static struct dev_config slim_tx_cfg[] = {
  169. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  170. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  171. };
  172. static struct dev_config usb_rx_cfg = {
  173. .sample_rate = SAMPLING_RATE_48KHZ,
  174. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  175. .channels = 2,
  176. };
  177. static struct dev_config usb_tx_cfg = {
  178. .sample_rate = SAMPLING_RATE_48KHZ,
  179. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  180. .channels = 1,
  181. };
  182. static struct dev_config proxy_rx_cfg = {
  183. .sample_rate = SAMPLING_RATE_48KHZ,
  184. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  185. .channels = 2,
  186. };
  187. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  188. {
  189. AFE_API_VERSION_I2S_CONFIG,
  190. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  191. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  192. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  193. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  194. 0,
  195. },
  196. {
  197. AFE_API_VERSION_I2S_CONFIG,
  198. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  199. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  200. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  201. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  202. 0,
  203. },
  204. {
  205. AFE_API_VERSION_I2S_CONFIG,
  206. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  207. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  208. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  209. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  210. 0,
  211. },
  212. {
  213. AFE_API_VERSION_I2S_CONFIG,
  214. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  215. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  216. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  217. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  218. 0,
  219. },
  220. };
  221. struct mi2s_conf {
  222. struct mutex lock;
  223. u32 ref_cnt;
  224. u32 msm_is_mi2s_master;
  225. };
  226. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  227. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  228. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  229. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  230. };
  231. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  232. /* Default configuration of TDM channels */
  233. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  234. { /* PRI TDM */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  243. },
  244. { /* SEC TDM */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  253. },
  254. { /* TERT TDM */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  263. },
  264. { /* QUAT TDM */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  273. },
  274. };
  275. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  276. { /* PRI TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* SEC TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* TERT TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. },
  306. { /* QUAT TDM */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  315. },
  316. };
  317. /* Default configuration of AUX PCM channels */
  318. static struct dev_config aux_pcm_rx_cfg[] = {
  319. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. };
  324. static struct dev_config aux_pcm_tx_cfg[] = {
  325. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. };
  330. /* Default configuration of MI2S channels */
  331. static struct dev_config mi2s_rx_cfg[] = {
  332. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  335. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  336. };
  337. static struct dev_config mi2s_tx_cfg[] = {
  338. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  339. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  340. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  341. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  342. };
  343. /* Default configuration of Codec DMA Interface RX */
  344. static struct dev_config cdc_dma_rx_cfg[] = {
  345. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  346. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. };
  351. /* Default configuration of Codec DMA Interface TX */
  352. static struct dev_config cdc_dma_tx_cfg[] = {
  353. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  354. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  355. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  357. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  358. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  359. };
  360. static struct dev_config afe_loopback_tx_cfg[] = {
  361. [AFE_LOOPBACK_TX_IDX] = {
  362. SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. };
  364. static int msm_vi_feed_tx_ch = 2;
  365. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  366. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  367. "S32_LE"};
  368. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  369. "Six", "Seven", "Eight"};
  370. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  371. "KHZ_16", "KHZ_22P05",
  372. "KHZ_32", "KHZ_44P1", "KHZ_48",
  373. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  374. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  375. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  376. "Five", "Six", "Seven",
  377. "Eight"};
  378. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  379. "KHZ_48", "KHZ_176P4",
  380. "KHZ_352P8"};
  381. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  382. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  383. "Five", "Six", "Seven", "Eight"};
  384. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  385. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  386. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  387. "KHZ_48", "KHZ_96", "KHZ_192"};
  388. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  389. "Five", "Six", "Seven",
  390. "Eight"};
  391. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  392. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  393. "Five", "Six", "Seven",
  394. "Eight"};
  395. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  396. "KHZ_16", "KHZ_22P05",
  397. "KHZ_32", "KHZ_44P1", "KHZ_48",
  398. "KHZ_88P2", "KHZ_96",
  399. "KHZ_176P4", "KHZ_192",
  400. "KHZ_352P8", "KHZ_384"};
  401. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  402. "KHZ_44P1", "KHZ_48",
  403. "KHZ_88P2", "KHZ_96"};
  404. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  405. "KHZ_44P1", "KHZ_48",
  406. "KHZ_88P2", "KHZ_96"};
  407. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  408. "KHZ_44P1", "KHZ_48",
  409. "KHZ_88P2", "KHZ_96"};
  410. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  411. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  412. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  413. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  414. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  415. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  416. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  417. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  418. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  419. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  420. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  421. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  476. cdc_dma_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  478. cdc_dma_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  480. cdc_dma_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  482. cdc_dma_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  484. cdc_dma_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  486. cdc_dma_sample_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  488. cdc_dma_sample_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  490. cdc_dma_sample_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  492. cdc_dma_sample_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  494. cdc_dma_sample_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  496. cdc_dma_sample_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  501. static bool is_initial_boot;
  502. static bool codec_reg_done;
  503. static struct snd_soc_aux_dev *msm_aux_dev;
  504. static struct snd_soc_codec_conf *msm_codec_conf;
  505. static struct snd_soc_card snd_soc_card_bengal_msm;
  506. static int dmic_0_1_gpio_cnt;
  507. static int dmic_2_3_gpio_cnt;
  508. static void *def_wcd_mbhc_cal(void);
  509. /*
  510. * Need to report LINEIN
  511. * if R/L channel impedance is larger than 5K ohm
  512. */
  513. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  514. .read_fw_bin = false,
  515. .calibration = NULL,
  516. .detect_extn_cable = true,
  517. .mono_stero_detection = false,
  518. .swap_gnd_mic = NULL,
  519. .hs_ext_micbias = true,
  520. .key_code[0] = KEY_MEDIA,
  521. .key_code[1] = KEY_VOICECOMMAND,
  522. .key_code[2] = KEY_VOLUMEUP,
  523. .key_code[3] = KEY_VOLUMEDOWN,
  524. .key_code[4] = 0,
  525. .key_code[5] = 0,
  526. .key_code[6] = 0,
  527. .key_code[7] = 0,
  528. .linein_th = 5000,
  529. .moisture_en = false,
  530. .mbhc_micbias = MIC_BIAS_2,
  531. .anc_micbias = MIC_BIAS_2,
  532. .enable_anc_mic_detect = false,
  533. .moisture_duty_cycle_en = true,
  534. };
  535. static inline int param_is_mask(int p)
  536. {
  537. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  538. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  539. }
  540. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  541. int n)
  542. {
  543. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  544. }
  545. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  546. unsigned int bit)
  547. {
  548. if (bit >= SNDRV_MASK_MAX)
  549. return;
  550. if (param_is_mask(n)) {
  551. struct snd_mask *m = param_to_mask(p, n);
  552. m->bits[0] = 0;
  553. m->bits[1] = 0;
  554. m->bits[bit >> 5] |= (1 << (bit & 31));
  555. }
  556. }
  557. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  558. struct snd_ctl_elem_value *ucontrol)
  559. {
  560. int sample_rate_val = 0;
  561. switch (usb_rx_cfg.sample_rate) {
  562. case SAMPLING_RATE_384KHZ:
  563. sample_rate_val = 12;
  564. break;
  565. case SAMPLING_RATE_352P8KHZ:
  566. sample_rate_val = 11;
  567. break;
  568. case SAMPLING_RATE_192KHZ:
  569. sample_rate_val = 10;
  570. break;
  571. case SAMPLING_RATE_176P4KHZ:
  572. sample_rate_val = 9;
  573. break;
  574. case SAMPLING_RATE_96KHZ:
  575. sample_rate_val = 8;
  576. break;
  577. case SAMPLING_RATE_88P2KHZ:
  578. sample_rate_val = 7;
  579. break;
  580. case SAMPLING_RATE_48KHZ:
  581. sample_rate_val = 6;
  582. break;
  583. case SAMPLING_RATE_44P1KHZ:
  584. sample_rate_val = 5;
  585. break;
  586. case SAMPLING_RATE_32KHZ:
  587. sample_rate_val = 4;
  588. break;
  589. case SAMPLING_RATE_22P05KHZ:
  590. sample_rate_val = 3;
  591. break;
  592. case SAMPLING_RATE_16KHZ:
  593. sample_rate_val = 2;
  594. break;
  595. case SAMPLING_RATE_11P025KHZ:
  596. sample_rate_val = 1;
  597. break;
  598. case SAMPLING_RATE_8KHZ:
  599. default:
  600. sample_rate_val = 0;
  601. break;
  602. }
  603. ucontrol->value.integer.value[0] = sample_rate_val;
  604. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  605. usb_rx_cfg.sample_rate);
  606. return 0;
  607. }
  608. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  609. struct snd_ctl_elem_value *ucontrol)
  610. {
  611. switch (ucontrol->value.integer.value[0]) {
  612. case 12:
  613. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  614. break;
  615. case 11:
  616. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  617. break;
  618. case 10:
  619. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  620. break;
  621. case 9:
  622. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  623. break;
  624. case 8:
  625. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  626. break;
  627. case 7:
  628. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  629. break;
  630. case 6:
  631. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  632. break;
  633. case 5:
  634. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  635. break;
  636. case 4:
  637. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  638. break;
  639. case 3:
  640. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  641. break;
  642. case 2:
  643. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  644. break;
  645. case 1:
  646. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  647. break;
  648. case 0:
  649. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  650. break;
  651. default:
  652. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  653. break;
  654. }
  655. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  656. __func__, ucontrol->value.integer.value[0],
  657. usb_rx_cfg.sample_rate);
  658. return 0;
  659. }
  660. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  661. struct snd_ctl_elem_value *ucontrol)
  662. {
  663. int sample_rate_val = 0;
  664. switch (usb_tx_cfg.sample_rate) {
  665. case SAMPLING_RATE_384KHZ:
  666. sample_rate_val = 12;
  667. break;
  668. case SAMPLING_RATE_352P8KHZ:
  669. sample_rate_val = 11;
  670. break;
  671. case SAMPLING_RATE_192KHZ:
  672. sample_rate_val = 10;
  673. break;
  674. case SAMPLING_RATE_176P4KHZ:
  675. sample_rate_val = 9;
  676. break;
  677. case SAMPLING_RATE_96KHZ:
  678. sample_rate_val = 8;
  679. break;
  680. case SAMPLING_RATE_88P2KHZ:
  681. sample_rate_val = 7;
  682. break;
  683. case SAMPLING_RATE_48KHZ:
  684. sample_rate_val = 6;
  685. break;
  686. case SAMPLING_RATE_44P1KHZ:
  687. sample_rate_val = 5;
  688. break;
  689. case SAMPLING_RATE_32KHZ:
  690. sample_rate_val = 4;
  691. break;
  692. case SAMPLING_RATE_22P05KHZ:
  693. sample_rate_val = 3;
  694. break;
  695. case SAMPLING_RATE_16KHZ:
  696. sample_rate_val = 2;
  697. break;
  698. case SAMPLING_RATE_11P025KHZ:
  699. sample_rate_val = 1;
  700. break;
  701. case SAMPLING_RATE_8KHZ:
  702. sample_rate_val = 0;
  703. break;
  704. default:
  705. sample_rate_val = 6;
  706. break;
  707. }
  708. ucontrol->value.integer.value[0] = sample_rate_val;
  709. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  710. usb_tx_cfg.sample_rate);
  711. return 0;
  712. }
  713. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  714. struct snd_ctl_elem_value *ucontrol)
  715. {
  716. switch (ucontrol->value.integer.value[0]) {
  717. case 12:
  718. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  719. break;
  720. case 11:
  721. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  722. break;
  723. case 10:
  724. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  725. break;
  726. case 9:
  727. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  728. break;
  729. case 8:
  730. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  731. break;
  732. case 7:
  733. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  734. break;
  735. case 6:
  736. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  737. break;
  738. case 5:
  739. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  740. break;
  741. case 4:
  742. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  743. break;
  744. case 3:
  745. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  746. break;
  747. case 2:
  748. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  749. break;
  750. case 1:
  751. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  752. break;
  753. case 0:
  754. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  755. break;
  756. default:
  757. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  758. break;
  759. }
  760. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  761. __func__, ucontrol->value.integer.value[0],
  762. usb_tx_cfg.sample_rate);
  763. return 0;
  764. }
  765. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  766. struct snd_ctl_elem_value *ucontrol)
  767. {
  768. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  769. afe_loopback_tx_cfg[0].channels);
  770. ucontrol->value.enumerated.item[0] =
  771. afe_loopback_tx_cfg[0].channels - 1;
  772. return 0;
  773. }
  774. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  775. struct snd_ctl_elem_value *ucontrol)
  776. {
  777. afe_loopback_tx_cfg[0].channels =
  778. ucontrol->value.enumerated.item[0] + 1;
  779. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  780. afe_loopback_tx_cfg[0].channels);
  781. return 1;
  782. }
  783. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  784. struct snd_ctl_elem_value *ucontrol)
  785. {
  786. switch (usb_rx_cfg.bit_format) {
  787. case SNDRV_PCM_FORMAT_S32_LE:
  788. ucontrol->value.integer.value[0] = 3;
  789. break;
  790. case SNDRV_PCM_FORMAT_S24_3LE:
  791. ucontrol->value.integer.value[0] = 2;
  792. break;
  793. case SNDRV_PCM_FORMAT_S24_LE:
  794. ucontrol->value.integer.value[0] = 1;
  795. break;
  796. case SNDRV_PCM_FORMAT_S16_LE:
  797. default:
  798. ucontrol->value.integer.value[0] = 0;
  799. break;
  800. }
  801. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  802. __func__, usb_rx_cfg.bit_format,
  803. ucontrol->value.integer.value[0]);
  804. return 0;
  805. }
  806. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  807. struct snd_ctl_elem_value *ucontrol)
  808. {
  809. int rc = 0;
  810. switch (ucontrol->value.integer.value[0]) {
  811. case 3:
  812. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  813. break;
  814. case 2:
  815. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  816. break;
  817. case 1:
  818. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  819. break;
  820. case 0:
  821. default:
  822. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  823. break;
  824. }
  825. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  826. __func__, usb_rx_cfg.bit_format,
  827. ucontrol->value.integer.value[0]);
  828. return rc;
  829. }
  830. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  831. struct snd_ctl_elem_value *ucontrol)
  832. {
  833. switch (usb_tx_cfg.bit_format) {
  834. case SNDRV_PCM_FORMAT_S32_LE:
  835. ucontrol->value.integer.value[0] = 3;
  836. break;
  837. case SNDRV_PCM_FORMAT_S24_3LE:
  838. ucontrol->value.integer.value[0] = 2;
  839. break;
  840. case SNDRV_PCM_FORMAT_S24_LE:
  841. ucontrol->value.integer.value[0] = 1;
  842. break;
  843. case SNDRV_PCM_FORMAT_S16_LE:
  844. default:
  845. ucontrol->value.integer.value[0] = 0;
  846. break;
  847. }
  848. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  849. __func__, usb_tx_cfg.bit_format,
  850. ucontrol->value.integer.value[0]);
  851. return 0;
  852. }
  853. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. int rc = 0;
  857. switch (ucontrol->value.integer.value[0]) {
  858. case 3:
  859. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  860. break;
  861. case 2:
  862. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  863. break;
  864. case 1:
  865. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  866. break;
  867. case 0:
  868. default:
  869. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  870. break;
  871. }
  872. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  873. __func__, usb_tx_cfg.bit_format,
  874. ucontrol->value.integer.value[0]);
  875. return rc;
  876. }
  877. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  878. struct snd_ctl_elem_value *ucontrol)
  879. {
  880. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  881. usb_rx_cfg.channels);
  882. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  883. return 0;
  884. }
  885. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  886. struct snd_ctl_elem_value *ucontrol)
  887. {
  888. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  889. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  890. return 1;
  891. }
  892. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  893. struct snd_ctl_elem_value *ucontrol)
  894. {
  895. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  896. usb_tx_cfg.channels);
  897. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  898. return 0;
  899. }
  900. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  901. struct snd_ctl_elem_value *ucontrol)
  902. {
  903. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  904. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  905. return 1;
  906. }
  907. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  908. struct snd_ctl_elem_value *ucontrol)
  909. {
  910. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  911. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  912. ucontrol->value.integer.value[0]);
  913. return 0;
  914. }
  915. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  916. struct snd_ctl_elem_value *ucontrol)
  917. {
  918. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  919. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  920. return 1;
  921. }
  922. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  923. struct snd_ctl_elem_value *ucontrol)
  924. {
  925. pr_debug("%s: proxy_rx channels = %d\n",
  926. __func__, proxy_rx_cfg.channels);
  927. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  928. return 0;
  929. }
  930. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  931. struct snd_ctl_elem_value *ucontrol)
  932. {
  933. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  934. pr_debug("%s: proxy_rx channels = %d\n",
  935. __func__, proxy_rx_cfg.channels);
  936. return 1;
  937. }
  938. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  939. struct tdm_port *port)
  940. {
  941. if (port) {
  942. if (strnstr(kcontrol->id.name, "PRI",
  943. sizeof(kcontrol->id.name))) {
  944. port->mode = TDM_PRI;
  945. } else if (strnstr(kcontrol->id.name, "SEC",
  946. sizeof(kcontrol->id.name))) {
  947. port->mode = TDM_SEC;
  948. } else if (strnstr(kcontrol->id.name, "TERT",
  949. sizeof(kcontrol->id.name))) {
  950. port->mode = TDM_TERT;
  951. } else if (strnstr(kcontrol->id.name, "QUAT",
  952. sizeof(kcontrol->id.name))) {
  953. port->mode = TDM_QUAT;
  954. } else {
  955. pr_err("%s: unsupported mode in: %s\n",
  956. __func__, kcontrol->id.name);
  957. return -EINVAL;
  958. }
  959. if (strnstr(kcontrol->id.name, "RX_0",
  960. sizeof(kcontrol->id.name)) ||
  961. strnstr(kcontrol->id.name, "TX_0",
  962. sizeof(kcontrol->id.name))) {
  963. port->channel = TDM_0;
  964. } else if (strnstr(kcontrol->id.name, "RX_1",
  965. sizeof(kcontrol->id.name)) ||
  966. strnstr(kcontrol->id.name, "TX_1",
  967. sizeof(kcontrol->id.name))) {
  968. port->channel = TDM_1;
  969. } else if (strnstr(kcontrol->id.name, "RX_2",
  970. sizeof(kcontrol->id.name)) ||
  971. strnstr(kcontrol->id.name, "TX_2",
  972. sizeof(kcontrol->id.name))) {
  973. port->channel = TDM_2;
  974. } else if (strnstr(kcontrol->id.name, "RX_3",
  975. sizeof(kcontrol->id.name)) ||
  976. strnstr(kcontrol->id.name, "TX_3",
  977. sizeof(kcontrol->id.name))) {
  978. port->channel = TDM_3;
  979. } else if (strnstr(kcontrol->id.name, "RX_4",
  980. sizeof(kcontrol->id.name)) ||
  981. strnstr(kcontrol->id.name, "TX_4",
  982. sizeof(kcontrol->id.name))) {
  983. port->channel = TDM_4;
  984. } else if (strnstr(kcontrol->id.name, "RX_5",
  985. sizeof(kcontrol->id.name)) ||
  986. strnstr(kcontrol->id.name, "TX_5",
  987. sizeof(kcontrol->id.name))) {
  988. port->channel = TDM_5;
  989. } else if (strnstr(kcontrol->id.name, "RX_6",
  990. sizeof(kcontrol->id.name)) ||
  991. strnstr(kcontrol->id.name, "TX_6",
  992. sizeof(kcontrol->id.name))) {
  993. port->channel = TDM_6;
  994. } else if (strnstr(kcontrol->id.name, "RX_7",
  995. sizeof(kcontrol->id.name)) ||
  996. strnstr(kcontrol->id.name, "TX_7",
  997. sizeof(kcontrol->id.name))) {
  998. port->channel = TDM_7;
  999. } else {
  1000. pr_err("%s: unsupported channel in: %s\n",
  1001. __func__, kcontrol->id.name);
  1002. return -EINVAL;
  1003. }
  1004. } else {
  1005. return -EINVAL;
  1006. }
  1007. return 0;
  1008. }
  1009. static int tdm_get_sample_rate(int value)
  1010. {
  1011. int sample_rate = 0;
  1012. switch (value) {
  1013. case 0:
  1014. sample_rate = SAMPLING_RATE_8KHZ;
  1015. break;
  1016. case 1:
  1017. sample_rate = SAMPLING_RATE_16KHZ;
  1018. break;
  1019. case 2:
  1020. sample_rate = SAMPLING_RATE_32KHZ;
  1021. break;
  1022. case 3:
  1023. sample_rate = SAMPLING_RATE_48KHZ;
  1024. break;
  1025. case 4:
  1026. sample_rate = SAMPLING_RATE_176P4KHZ;
  1027. break;
  1028. case 5:
  1029. sample_rate = SAMPLING_RATE_352P8KHZ;
  1030. break;
  1031. default:
  1032. sample_rate = SAMPLING_RATE_48KHZ;
  1033. break;
  1034. }
  1035. return sample_rate;
  1036. }
  1037. static int tdm_get_sample_rate_val(int sample_rate)
  1038. {
  1039. int sample_rate_val = 0;
  1040. switch (sample_rate) {
  1041. case SAMPLING_RATE_8KHZ:
  1042. sample_rate_val = 0;
  1043. break;
  1044. case SAMPLING_RATE_16KHZ:
  1045. sample_rate_val = 1;
  1046. break;
  1047. case SAMPLING_RATE_32KHZ:
  1048. sample_rate_val = 2;
  1049. break;
  1050. case SAMPLING_RATE_48KHZ:
  1051. sample_rate_val = 3;
  1052. break;
  1053. case SAMPLING_RATE_176P4KHZ:
  1054. sample_rate_val = 4;
  1055. break;
  1056. case SAMPLING_RATE_352P8KHZ:
  1057. sample_rate_val = 5;
  1058. break;
  1059. default:
  1060. sample_rate_val = 3;
  1061. break;
  1062. }
  1063. return sample_rate_val;
  1064. }
  1065. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1066. struct snd_ctl_elem_value *ucontrol)
  1067. {
  1068. struct tdm_port port;
  1069. int ret = tdm_get_port_idx(kcontrol, &port);
  1070. if (ret) {
  1071. pr_err("%s: unsupported control: %s\n",
  1072. __func__, kcontrol->id.name);
  1073. } else {
  1074. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1075. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1076. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1077. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1078. ucontrol->value.enumerated.item[0]);
  1079. }
  1080. return ret;
  1081. }
  1082. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1083. struct snd_ctl_elem_value *ucontrol)
  1084. {
  1085. struct tdm_port port;
  1086. int ret = tdm_get_port_idx(kcontrol, &port);
  1087. if (ret) {
  1088. pr_err("%s: unsupported control: %s\n",
  1089. __func__, kcontrol->id.name);
  1090. } else {
  1091. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1092. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1093. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1094. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1095. ucontrol->value.enumerated.item[0]);
  1096. }
  1097. return ret;
  1098. }
  1099. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1100. struct snd_ctl_elem_value *ucontrol)
  1101. {
  1102. struct tdm_port port;
  1103. int ret = tdm_get_port_idx(kcontrol, &port);
  1104. if (ret) {
  1105. pr_err("%s: unsupported control: %s\n",
  1106. __func__, kcontrol->id.name);
  1107. } else {
  1108. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1109. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1110. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1111. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1112. ucontrol->value.enumerated.item[0]);
  1113. }
  1114. return ret;
  1115. }
  1116. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1117. struct snd_ctl_elem_value *ucontrol)
  1118. {
  1119. struct tdm_port port;
  1120. int ret = tdm_get_port_idx(kcontrol, &port);
  1121. if (ret) {
  1122. pr_err("%s: unsupported control: %s\n",
  1123. __func__, kcontrol->id.name);
  1124. } else {
  1125. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1126. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1127. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1128. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1129. ucontrol->value.enumerated.item[0]);
  1130. }
  1131. return ret;
  1132. }
  1133. static int tdm_get_format(int value)
  1134. {
  1135. int format = 0;
  1136. switch (value) {
  1137. case 0:
  1138. format = SNDRV_PCM_FORMAT_S16_LE;
  1139. break;
  1140. case 1:
  1141. format = SNDRV_PCM_FORMAT_S24_LE;
  1142. break;
  1143. case 2:
  1144. format = SNDRV_PCM_FORMAT_S32_LE;
  1145. break;
  1146. default:
  1147. format = SNDRV_PCM_FORMAT_S16_LE;
  1148. break;
  1149. }
  1150. return format;
  1151. }
  1152. static int tdm_get_format_val(int format)
  1153. {
  1154. int value = 0;
  1155. switch (format) {
  1156. case SNDRV_PCM_FORMAT_S16_LE:
  1157. value = 0;
  1158. break;
  1159. case SNDRV_PCM_FORMAT_S24_LE:
  1160. value = 1;
  1161. break;
  1162. case SNDRV_PCM_FORMAT_S32_LE:
  1163. value = 2;
  1164. break;
  1165. default:
  1166. value = 0;
  1167. break;
  1168. }
  1169. return value;
  1170. }
  1171. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1172. struct snd_ctl_elem_value *ucontrol)
  1173. {
  1174. struct tdm_port port;
  1175. int ret = tdm_get_port_idx(kcontrol, &port);
  1176. if (ret) {
  1177. pr_err("%s: unsupported control: %s\n",
  1178. __func__, kcontrol->id.name);
  1179. } else {
  1180. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1181. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1182. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1183. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1184. ucontrol->value.enumerated.item[0]);
  1185. }
  1186. return ret;
  1187. }
  1188. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1189. struct snd_ctl_elem_value *ucontrol)
  1190. {
  1191. struct tdm_port port;
  1192. int ret = tdm_get_port_idx(kcontrol, &port);
  1193. if (ret) {
  1194. pr_err("%s: unsupported control: %s\n",
  1195. __func__, kcontrol->id.name);
  1196. } else {
  1197. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1198. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1199. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1200. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1201. ucontrol->value.enumerated.item[0]);
  1202. }
  1203. return ret;
  1204. }
  1205. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1206. struct snd_ctl_elem_value *ucontrol)
  1207. {
  1208. struct tdm_port port;
  1209. int ret = tdm_get_port_idx(kcontrol, &port);
  1210. if (ret) {
  1211. pr_err("%s: unsupported control: %s\n",
  1212. __func__, kcontrol->id.name);
  1213. } else {
  1214. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1215. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1216. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1217. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1218. ucontrol->value.enumerated.item[0]);
  1219. }
  1220. return ret;
  1221. }
  1222. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1223. struct snd_ctl_elem_value *ucontrol)
  1224. {
  1225. struct tdm_port port;
  1226. int ret = tdm_get_port_idx(kcontrol, &port);
  1227. if (ret) {
  1228. pr_err("%s: unsupported control: %s\n",
  1229. __func__, kcontrol->id.name);
  1230. } else {
  1231. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1232. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1233. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1234. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1235. ucontrol->value.enumerated.item[0]);
  1236. }
  1237. return ret;
  1238. }
  1239. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1240. struct snd_ctl_elem_value *ucontrol)
  1241. {
  1242. struct tdm_port port;
  1243. int ret = tdm_get_port_idx(kcontrol, &port);
  1244. if (ret) {
  1245. pr_err("%s: unsupported control: %s\n",
  1246. __func__, kcontrol->id.name);
  1247. } else {
  1248. ucontrol->value.enumerated.item[0] =
  1249. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1250. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1251. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1252. ucontrol->value.enumerated.item[0]);
  1253. }
  1254. return ret;
  1255. }
  1256. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1257. struct snd_ctl_elem_value *ucontrol)
  1258. {
  1259. struct tdm_port port;
  1260. int ret = tdm_get_port_idx(kcontrol, &port);
  1261. if (ret) {
  1262. pr_err("%s: unsupported control: %s\n",
  1263. __func__, kcontrol->id.name);
  1264. } else {
  1265. tdm_rx_cfg[port.mode][port.channel].channels =
  1266. ucontrol->value.enumerated.item[0] + 1;
  1267. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1268. tdm_rx_cfg[port.mode][port.channel].channels,
  1269. ucontrol->value.enumerated.item[0] + 1);
  1270. }
  1271. return ret;
  1272. }
  1273. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1274. struct snd_ctl_elem_value *ucontrol)
  1275. {
  1276. struct tdm_port port;
  1277. int ret = tdm_get_port_idx(kcontrol, &port);
  1278. if (ret) {
  1279. pr_err("%s: unsupported control: %s\n",
  1280. __func__, kcontrol->id.name);
  1281. } else {
  1282. ucontrol->value.enumerated.item[0] =
  1283. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1284. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1285. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1286. ucontrol->value.enumerated.item[0]);
  1287. }
  1288. return ret;
  1289. }
  1290. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1291. struct snd_ctl_elem_value *ucontrol)
  1292. {
  1293. struct tdm_port port;
  1294. int ret = tdm_get_port_idx(kcontrol, &port);
  1295. if (ret) {
  1296. pr_err("%s: unsupported control: %s\n",
  1297. __func__, kcontrol->id.name);
  1298. } else {
  1299. tdm_tx_cfg[port.mode][port.channel].channels =
  1300. ucontrol->value.enumerated.item[0] + 1;
  1301. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1302. tdm_tx_cfg[port.mode][port.channel].channels,
  1303. ucontrol->value.enumerated.item[0] + 1);
  1304. }
  1305. return ret;
  1306. }
  1307. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1308. {
  1309. int idx = 0;
  1310. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1311. sizeof("PRIM_AUX_PCM"))) {
  1312. idx = PRIM_AUX_PCM;
  1313. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1314. sizeof("SEC_AUX_PCM"))) {
  1315. idx = SEC_AUX_PCM;
  1316. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1317. sizeof("TERT_AUX_PCM"))) {
  1318. idx = TERT_AUX_PCM;
  1319. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1320. sizeof("QUAT_AUX_PCM"))) {
  1321. idx = QUAT_AUX_PCM;
  1322. } else {
  1323. pr_err("%s: unsupported port: %s\n",
  1324. __func__, kcontrol->id.name);
  1325. idx = -EINVAL;
  1326. }
  1327. return idx;
  1328. }
  1329. static int aux_pcm_get_sample_rate(int value)
  1330. {
  1331. int sample_rate = 0;
  1332. switch (value) {
  1333. case 1:
  1334. sample_rate = SAMPLING_RATE_16KHZ;
  1335. break;
  1336. case 0:
  1337. default:
  1338. sample_rate = SAMPLING_RATE_8KHZ;
  1339. break;
  1340. }
  1341. return sample_rate;
  1342. }
  1343. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1344. {
  1345. int sample_rate_val = 0;
  1346. switch (sample_rate) {
  1347. case SAMPLING_RATE_16KHZ:
  1348. sample_rate_val = 1;
  1349. break;
  1350. case SAMPLING_RATE_8KHZ:
  1351. default:
  1352. sample_rate_val = 0;
  1353. break;
  1354. }
  1355. return sample_rate_val;
  1356. }
  1357. static int mi2s_auxpcm_get_format(int value)
  1358. {
  1359. int format = 0;
  1360. switch (value) {
  1361. case 0:
  1362. format = SNDRV_PCM_FORMAT_S16_LE;
  1363. break;
  1364. case 1:
  1365. format = SNDRV_PCM_FORMAT_S24_LE;
  1366. break;
  1367. case 2:
  1368. format = SNDRV_PCM_FORMAT_S24_3LE;
  1369. break;
  1370. case 3:
  1371. format = SNDRV_PCM_FORMAT_S32_LE;
  1372. break;
  1373. default:
  1374. format = SNDRV_PCM_FORMAT_S16_LE;
  1375. break;
  1376. }
  1377. return format;
  1378. }
  1379. static int mi2s_auxpcm_get_format_value(int format)
  1380. {
  1381. int value = 0;
  1382. switch (format) {
  1383. case SNDRV_PCM_FORMAT_S16_LE:
  1384. value = 0;
  1385. break;
  1386. case SNDRV_PCM_FORMAT_S24_LE:
  1387. value = 1;
  1388. break;
  1389. case SNDRV_PCM_FORMAT_S24_3LE:
  1390. value = 2;
  1391. break;
  1392. case SNDRV_PCM_FORMAT_S32_LE:
  1393. value = 3;
  1394. break;
  1395. default:
  1396. value = 0;
  1397. break;
  1398. }
  1399. return value;
  1400. }
  1401. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_value *ucontrol)
  1403. {
  1404. int idx = aux_pcm_get_port_idx(kcontrol);
  1405. if (idx < 0)
  1406. return idx;
  1407. ucontrol->value.enumerated.item[0] =
  1408. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1409. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1410. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1411. ucontrol->value.enumerated.item[0]);
  1412. return 0;
  1413. }
  1414. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1415. struct snd_ctl_elem_value *ucontrol)
  1416. {
  1417. int idx = aux_pcm_get_port_idx(kcontrol);
  1418. if (idx < 0)
  1419. return idx;
  1420. aux_pcm_rx_cfg[idx].sample_rate =
  1421. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1422. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1423. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1424. ucontrol->value.enumerated.item[0]);
  1425. return 0;
  1426. }
  1427. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1428. struct snd_ctl_elem_value *ucontrol)
  1429. {
  1430. int idx = aux_pcm_get_port_idx(kcontrol);
  1431. if (idx < 0)
  1432. return idx;
  1433. ucontrol->value.enumerated.item[0] =
  1434. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1435. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1436. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1437. ucontrol->value.enumerated.item[0]);
  1438. return 0;
  1439. }
  1440. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1441. struct snd_ctl_elem_value *ucontrol)
  1442. {
  1443. int idx = aux_pcm_get_port_idx(kcontrol);
  1444. if (idx < 0)
  1445. return idx;
  1446. aux_pcm_tx_cfg[idx].sample_rate =
  1447. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1448. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1449. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1450. ucontrol->value.enumerated.item[0]);
  1451. return 0;
  1452. }
  1453. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1454. struct snd_ctl_elem_value *ucontrol)
  1455. {
  1456. int idx = aux_pcm_get_port_idx(kcontrol);
  1457. if (idx < 0)
  1458. return idx;
  1459. ucontrol->value.enumerated.item[0] =
  1460. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1461. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1462. idx, aux_pcm_rx_cfg[idx].bit_format,
  1463. ucontrol->value.enumerated.item[0]);
  1464. return 0;
  1465. }
  1466. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1467. struct snd_ctl_elem_value *ucontrol)
  1468. {
  1469. int idx = aux_pcm_get_port_idx(kcontrol);
  1470. if (idx < 0)
  1471. return idx;
  1472. aux_pcm_rx_cfg[idx].bit_format =
  1473. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1474. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1475. idx, aux_pcm_rx_cfg[idx].bit_format,
  1476. ucontrol->value.enumerated.item[0]);
  1477. return 0;
  1478. }
  1479. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1480. struct snd_ctl_elem_value *ucontrol)
  1481. {
  1482. int idx = aux_pcm_get_port_idx(kcontrol);
  1483. if (idx < 0)
  1484. return idx;
  1485. ucontrol->value.enumerated.item[0] =
  1486. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1487. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1488. idx, aux_pcm_tx_cfg[idx].bit_format,
  1489. ucontrol->value.enumerated.item[0]);
  1490. return 0;
  1491. }
  1492. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_value *ucontrol)
  1494. {
  1495. int idx = aux_pcm_get_port_idx(kcontrol);
  1496. if (idx < 0)
  1497. return idx;
  1498. aux_pcm_tx_cfg[idx].bit_format =
  1499. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1500. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1501. idx, aux_pcm_tx_cfg[idx].bit_format,
  1502. ucontrol->value.enumerated.item[0]);
  1503. return 0;
  1504. }
  1505. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1506. {
  1507. int idx = 0;
  1508. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1509. sizeof("PRIM_MI2S_RX"))) {
  1510. idx = PRIM_MI2S;
  1511. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1512. sizeof("SEC_MI2S_RX"))) {
  1513. idx = SEC_MI2S;
  1514. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1515. sizeof("TERT_MI2S_RX"))) {
  1516. idx = TERT_MI2S;
  1517. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1518. sizeof("QUAT_MI2S_RX"))) {
  1519. idx = QUAT_MI2S;
  1520. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1521. sizeof("PRIM_MI2S_TX"))) {
  1522. idx = PRIM_MI2S;
  1523. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1524. sizeof("SEC_MI2S_TX"))) {
  1525. idx = SEC_MI2S;
  1526. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1527. sizeof("TERT_MI2S_TX"))) {
  1528. idx = TERT_MI2S;
  1529. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1530. sizeof("QUAT_MI2S_TX"))) {
  1531. idx = QUAT_MI2S;
  1532. } else {
  1533. pr_err("%s: unsupported channel: %s\n",
  1534. __func__, kcontrol->id.name);
  1535. idx = -EINVAL;
  1536. }
  1537. return idx;
  1538. }
  1539. static int mi2s_get_sample_rate(int value)
  1540. {
  1541. int sample_rate = 0;
  1542. switch (value) {
  1543. case 0:
  1544. sample_rate = SAMPLING_RATE_8KHZ;
  1545. break;
  1546. case 1:
  1547. sample_rate = SAMPLING_RATE_11P025KHZ;
  1548. break;
  1549. case 2:
  1550. sample_rate = SAMPLING_RATE_16KHZ;
  1551. break;
  1552. case 3:
  1553. sample_rate = SAMPLING_RATE_22P05KHZ;
  1554. break;
  1555. case 4:
  1556. sample_rate = SAMPLING_RATE_32KHZ;
  1557. break;
  1558. case 5:
  1559. sample_rate = SAMPLING_RATE_44P1KHZ;
  1560. break;
  1561. case 6:
  1562. sample_rate = SAMPLING_RATE_48KHZ;
  1563. break;
  1564. case 7:
  1565. sample_rate = SAMPLING_RATE_96KHZ;
  1566. break;
  1567. case 8:
  1568. sample_rate = SAMPLING_RATE_192KHZ;
  1569. break;
  1570. default:
  1571. sample_rate = SAMPLING_RATE_48KHZ;
  1572. break;
  1573. }
  1574. return sample_rate;
  1575. }
  1576. static int mi2s_get_sample_rate_val(int sample_rate)
  1577. {
  1578. int sample_rate_val = 0;
  1579. switch (sample_rate) {
  1580. case SAMPLING_RATE_8KHZ:
  1581. sample_rate_val = 0;
  1582. break;
  1583. case SAMPLING_RATE_11P025KHZ:
  1584. sample_rate_val = 1;
  1585. break;
  1586. case SAMPLING_RATE_16KHZ:
  1587. sample_rate_val = 2;
  1588. break;
  1589. case SAMPLING_RATE_22P05KHZ:
  1590. sample_rate_val = 3;
  1591. break;
  1592. case SAMPLING_RATE_32KHZ:
  1593. sample_rate_val = 4;
  1594. break;
  1595. case SAMPLING_RATE_44P1KHZ:
  1596. sample_rate_val = 5;
  1597. break;
  1598. case SAMPLING_RATE_48KHZ:
  1599. sample_rate_val = 6;
  1600. break;
  1601. case SAMPLING_RATE_96KHZ:
  1602. sample_rate_val = 7;
  1603. break;
  1604. case SAMPLING_RATE_192KHZ:
  1605. sample_rate_val = 8;
  1606. break;
  1607. default:
  1608. sample_rate_val = 6;
  1609. break;
  1610. }
  1611. return sample_rate_val;
  1612. }
  1613. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1614. struct snd_ctl_elem_value *ucontrol)
  1615. {
  1616. int idx = mi2s_get_port_idx(kcontrol);
  1617. if (idx < 0)
  1618. return idx;
  1619. ucontrol->value.enumerated.item[0] =
  1620. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1621. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1622. idx, mi2s_rx_cfg[idx].sample_rate,
  1623. ucontrol->value.enumerated.item[0]);
  1624. return 0;
  1625. }
  1626. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1627. struct snd_ctl_elem_value *ucontrol)
  1628. {
  1629. int idx = mi2s_get_port_idx(kcontrol);
  1630. if (idx < 0)
  1631. return idx;
  1632. mi2s_rx_cfg[idx].sample_rate =
  1633. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1634. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1635. idx, mi2s_rx_cfg[idx].sample_rate,
  1636. ucontrol->value.enumerated.item[0]);
  1637. return 0;
  1638. }
  1639. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1640. struct snd_ctl_elem_value *ucontrol)
  1641. {
  1642. int idx = mi2s_get_port_idx(kcontrol);
  1643. if (idx < 0)
  1644. return idx;
  1645. ucontrol->value.enumerated.item[0] =
  1646. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1647. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1648. idx, mi2s_tx_cfg[idx].sample_rate,
  1649. ucontrol->value.enumerated.item[0]);
  1650. return 0;
  1651. }
  1652. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1653. struct snd_ctl_elem_value *ucontrol)
  1654. {
  1655. int idx = mi2s_get_port_idx(kcontrol);
  1656. if (idx < 0)
  1657. return idx;
  1658. mi2s_tx_cfg[idx].sample_rate =
  1659. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1660. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1661. idx, mi2s_tx_cfg[idx].sample_rate,
  1662. ucontrol->value.enumerated.item[0]);
  1663. return 0;
  1664. }
  1665. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1666. struct snd_ctl_elem_value *ucontrol)
  1667. {
  1668. int idx = mi2s_get_port_idx(kcontrol);
  1669. if (idx < 0)
  1670. return idx;
  1671. ucontrol->value.enumerated.item[0] =
  1672. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1673. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1674. idx, mi2s_rx_cfg[idx].bit_format,
  1675. ucontrol->value.enumerated.item[0]);
  1676. return 0;
  1677. }
  1678. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1679. struct snd_ctl_elem_value *ucontrol)
  1680. {
  1681. int idx = mi2s_get_port_idx(kcontrol);
  1682. if (idx < 0)
  1683. return idx;
  1684. mi2s_rx_cfg[idx].bit_format =
  1685. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1686. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1687. idx, mi2s_rx_cfg[idx].bit_format,
  1688. ucontrol->value.enumerated.item[0]);
  1689. return 0;
  1690. }
  1691. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1692. struct snd_ctl_elem_value *ucontrol)
  1693. {
  1694. int idx = mi2s_get_port_idx(kcontrol);
  1695. if (idx < 0)
  1696. return idx;
  1697. ucontrol->value.enumerated.item[0] =
  1698. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1699. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1700. idx, mi2s_tx_cfg[idx].bit_format,
  1701. ucontrol->value.enumerated.item[0]);
  1702. return 0;
  1703. }
  1704. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1705. struct snd_ctl_elem_value *ucontrol)
  1706. {
  1707. int idx = mi2s_get_port_idx(kcontrol);
  1708. if (idx < 0)
  1709. return idx;
  1710. mi2s_tx_cfg[idx].bit_format =
  1711. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1712. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1713. idx, mi2s_tx_cfg[idx].bit_format,
  1714. ucontrol->value.enumerated.item[0]);
  1715. return 0;
  1716. }
  1717. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1718. struct snd_ctl_elem_value *ucontrol)
  1719. {
  1720. int idx = mi2s_get_port_idx(kcontrol);
  1721. if (idx < 0)
  1722. return idx;
  1723. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1724. idx, mi2s_rx_cfg[idx].channels);
  1725. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1726. return 0;
  1727. }
  1728. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1729. struct snd_ctl_elem_value *ucontrol)
  1730. {
  1731. int idx = mi2s_get_port_idx(kcontrol);
  1732. if (idx < 0)
  1733. return idx;
  1734. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1735. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1736. idx, mi2s_rx_cfg[idx].channels);
  1737. return 1;
  1738. }
  1739. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1740. struct snd_ctl_elem_value *ucontrol)
  1741. {
  1742. int idx = mi2s_get_port_idx(kcontrol);
  1743. if (idx < 0)
  1744. return idx;
  1745. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1746. idx, mi2s_tx_cfg[idx].channels);
  1747. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1748. return 0;
  1749. }
  1750. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1751. struct snd_ctl_elem_value *ucontrol)
  1752. {
  1753. int idx = mi2s_get_port_idx(kcontrol);
  1754. if (idx < 0)
  1755. return idx;
  1756. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1757. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1758. idx, mi2s_tx_cfg[idx].channels);
  1759. return 1;
  1760. }
  1761. static int msm_get_port_id(int be_id)
  1762. {
  1763. int afe_port_id = 0;
  1764. switch (be_id) {
  1765. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  1766. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  1767. break;
  1768. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  1769. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  1770. break;
  1771. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  1772. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  1773. break;
  1774. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  1775. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  1776. break;
  1777. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  1778. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  1779. break;
  1780. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  1781. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  1782. break;
  1783. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  1784. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  1785. break;
  1786. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  1787. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  1788. break;
  1789. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  1790. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  1791. break;
  1792. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  1793. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  1794. break;
  1795. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  1796. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  1797. break;
  1798. default:
  1799. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  1800. afe_port_id = -EINVAL;
  1801. }
  1802. return afe_port_id;
  1803. }
  1804. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  1805. {
  1806. u32 bit_per_sample = 0;
  1807. switch (bit_format) {
  1808. case SNDRV_PCM_FORMAT_S32_LE:
  1809. case SNDRV_PCM_FORMAT_S24_3LE:
  1810. case SNDRV_PCM_FORMAT_S24_LE:
  1811. bit_per_sample = 32;
  1812. break;
  1813. case SNDRV_PCM_FORMAT_S16_LE:
  1814. default:
  1815. bit_per_sample = 16;
  1816. break;
  1817. }
  1818. return bit_per_sample;
  1819. }
  1820. static void update_mi2s_clk_val(int dai_id, int stream)
  1821. {
  1822. u32 bit_per_sample = 0;
  1823. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1824. bit_per_sample =
  1825. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  1826. mi2s_clk[dai_id].clk_freq_in_hz =
  1827. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1828. } else {
  1829. bit_per_sample =
  1830. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  1831. mi2s_clk[dai_id].clk_freq_in_hz =
  1832. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1833. }
  1834. }
  1835. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  1836. {
  1837. int ret = 0;
  1838. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1839. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  1840. int port_id = 0;
  1841. int index = cpu_dai->id;
  1842. port_id = msm_get_port_id(rtd->dai_link->id);
  1843. if (port_id < 0) {
  1844. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  1845. ret = port_id;
  1846. goto err;
  1847. }
  1848. if (enable) {
  1849. update_mi2s_clk_val(index, substream->stream);
  1850. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  1851. mi2s_clk[index].clk_freq_in_hz);
  1852. }
  1853. mi2s_clk[index].enable = enable;
  1854. ret = afe_set_lpass_clock_v2(port_id,
  1855. &mi2s_clk[index]);
  1856. if (ret < 0) {
  1857. dev_err(rtd->card->dev,
  1858. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  1859. __func__, port_id, ret);
  1860. goto err;
  1861. }
  1862. err:
  1863. return ret;
  1864. }
  1865. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1866. {
  1867. int idx = 0;
  1868. if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  1869. sizeof("RX_CDC_DMA_RX_0")))
  1870. idx = RX_CDC_DMA_RX_0;
  1871. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  1872. sizeof("RX_CDC_DMA_RX_1")))
  1873. idx = RX_CDC_DMA_RX_1;
  1874. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  1875. sizeof("RX_CDC_DMA_RX_2")))
  1876. idx = RX_CDC_DMA_RX_2;
  1877. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  1878. sizeof("RX_CDC_DMA_RX_3")))
  1879. idx = RX_CDC_DMA_RX_3;
  1880. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  1881. sizeof("RX_CDC_DMA_RX_5")))
  1882. idx = RX_CDC_DMA_RX_5;
  1883. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  1884. sizeof("TX_CDC_DMA_TX_0")))
  1885. idx = TX_CDC_DMA_TX_0;
  1886. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  1887. sizeof("TX_CDC_DMA_TX_3")))
  1888. idx = TX_CDC_DMA_TX_3;
  1889. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  1890. sizeof("TX_CDC_DMA_TX_4")))
  1891. idx = TX_CDC_DMA_TX_4;
  1892. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1893. sizeof("VA_CDC_DMA_TX_0")))
  1894. idx = VA_CDC_DMA_TX_0;
  1895. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1896. sizeof("VA_CDC_DMA_TX_1")))
  1897. idx = VA_CDC_DMA_TX_1;
  1898. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  1899. sizeof("VA_CDC_DMA_TX_2")))
  1900. idx = VA_CDC_DMA_TX_2;
  1901. else {
  1902. pr_err("%s: unsupported channel: %s\n",
  1903. __func__, kcontrol->id.name);
  1904. return -EINVAL;
  1905. }
  1906. return idx;
  1907. }
  1908. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1909. struct snd_ctl_elem_value *ucontrol)
  1910. {
  1911. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1912. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1913. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1914. return ch_num;
  1915. }
  1916. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1917. cdc_dma_rx_cfg[ch_num].channels - 1);
  1918. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1919. return 0;
  1920. }
  1921. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1922. struct snd_ctl_elem_value *ucontrol)
  1923. {
  1924. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1925. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1926. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1927. return ch_num;
  1928. }
  1929. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1930. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1931. cdc_dma_rx_cfg[ch_num].channels);
  1932. return 1;
  1933. }
  1934. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1935. struct snd_ctl_elem_value *ucontrol)
  1936. {
  1937. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1938. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1939. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1940. return ch_num;
  1941. }
  1942. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1943. case SNDRV_PCM_FORMAT_S32_LE:
  1944. ucontrol->value.integer.value[0] = 3;
  1945. break;
  1946. case SNDRV_PCM_FORMAT_S24_3LE:
  1947. ucontrol->value.integer.value[0] = 2;
  1948. break;
  1949. case SNDRV_PCM_FORMAT_S24_LE:
  1950. ucontrol->value.integer.value[0] = 1;
  1951. break;
  1952. case SNDRV_PCM_FORMAT_S16_LE:
  1953. default:
  1954. ucontrol->value.integer.value[0] = 0;
  1955. break;
  1956. }
  1957. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1958. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1959. ucontrol->value.integer.value[0]);
  1960. return 0;
  1961. }
  1962. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1963. struct snd_ctl_elem_value *ucontrol)
  1964. {
  1965. int rc = 0;
  1966. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1967. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1968. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1969. return ch_num;
  1970. }
  1971. switch (ucontrol->value.integer.value[0]) {
  1972. case 3:
  1973. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1974. break;
  1975. case 2:
  1976. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1977. break;
  1978. case 1:
  1979. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1980. break;
  1981. case 0:
  1982. default:
  1983. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1984. break;
  1985. }
  1986. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1987. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1988. ucontrol->value.integer.value[0]);
  1989. return rc;
  1990. }
  1991. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1992. {
  1993. int sample_rate_val = 0;
  1994. switch (sample_rate) {
  1995. case SAMPLING_RATE_8KHZ:
  1996. sample_rate_val = 0;
  1997. break;
  1998. case SAMPLING_RATE_11P025KHZ:
  1999. sample_rate_val = 1;
  2000. break;
  2001. case SAMPLING_RATE_16KHZ:
  2002. sample_rate_val = 2;
  2003. break;
  2004. case SAMPLING_RATE_22P05KHZ:
  2005. sample_rate_val = 3;
  2006. break;
  2007. case SAMPLING_RATE_32KHZ:
  2008. sample_rate_val = 4;
  2009. break;
  2010. case SAMPLING_RATE_44P1KHZ:
  2011. sample_rate_val = 5;
  2012. break;
  2013. case SAMPLING_RATE_48KHZ:
  2014. sample_rate_val = 6;
  2015. break;
  2016. case SAMPLING_RATE_88P2KHZ:
  2017. sample_rate_val = 7;
  2018. break;
  2019. case SAMPLING_RATE_96KHZ:
  2020. sample_rate_val = 8;
  2021. break;
  2022. case SAMPLING_RATE_176P4KHZ:
  2023. sample_rate_val = 9;
  2024. break;
  2025. case SAMPLING_RATE_192KHZ:
  2026. sample_rate_val = 10;
  2027. break;
  2028. case SAMPLING_RATE_352P8KHZ:
  2029. sample_rate_val = 11;
  2030. break;
  2031. case SAMPLING_RATE_384KHZ:
  2032. sample_rate_val = 12;
  2033. break;
  2034. default:
  2035. sample_rate_val = 6;
  2036. break;
  2037. }
  2038. return sample_rate_val;
  2039. }
  2040. static int cdc_dma_get_sample_rate(int value)
  2041. {
  2042. int sample_rate = 0;
  2043. switch (value) {
  2044. case 0:
  2045. sample_rate = SAMPLING_RATE_8KHZ;
  2046. break;
  2047. case 1:
  2048. sample_rate = SAMPLING_RATE_11P025KHZ;
  2049. break;
  2050. case 2:
  2051. sample_rate = SAMPLING_RATE_16KHZ;
  2052. break;
  2053. case 3:
  2054. sample_rate = SAMPLING_RATE_22P05KHZ;
  2055. break;
  2056. case 4:
  2057. sample_rate = SAMPLING_RATE_32KHZ;
  2058. break;
  2059. case 5:
  2060. sample_rate = SAMPLING_RATE_44P1KHZ;
  2061. break;
  2062. case 6:
  2063. sample_rate = SAMPLING_RATE_48KHZ;
  2064. break;
  2065. case 7:
  2066. sample_rate = SAMPLING_RATE_88P2KHZ;
  2067. break;
  2068. case 8:
  2069. sample_rate = SAMPLING_RATE_96KHZ;
  2070. break;
  2071. case 9:
  2072. sample_rate = SAMPLING_RATE_176P4KHZ;
  2073. break;
  2074. case 10:
  2075. sample_rate = SAMPLING_RATE_192KHZ;
  2076. break;
  2077. case 11:
  2078. sample_rate = SAMPLING_RATE_352P8KHZ;
  2079. break;
  2080. case 12:
  2081. sample_rate = SAMPLING_RATE_384KHZ;
  2082. break;
  2083. default:
  2084. sample_rate = SAMPLING_RATE_48KHZ;
  2085. break;
  2086. }
  2087. return sample_rate;
  2088. }
  2089. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2090. struct snd_ctl_elem_value *ucontrol)
  2091. {
  2092. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2093. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2094. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2095. return ch_num;
  2096. }
  2097. ucontrol->value.enumerated.item[0] =
  2098. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2099. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2100. cdc_dma_rx_cfg[ch_num].sample_rate);
  2101. return 0;
  2102. }
  2103. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2104. struct snd_ctl_elem_value *ucontrol)
  2105. {
  2106. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2107. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2108. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2109. return ch_num;
  2110. }
  2111. cdc_dma_rx_cfg[ch_num].sample_rate =
  2112. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2113. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2114. __func__, ucontrol->value.enumerated.item[0],
  2115. cdc_dma_rx_cfg[ch_num].sample_rate);
  2116. return 0;
  2117. }
  2118. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2119. struct snd_ctl_elem_value *ucontrol)
  2120. {
  2121. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2122. if (ch_num < 0) {
  2123. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2124. return ch_num;
  2125. }
  2126. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2127. cdc_dma_tx_cfg[ch_num].channels);
  2128. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2129. return 0;
  2130. }
  2131. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2132. struct snd_ctl_elem_value *ucontrol)
  2133. {
  2134. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2135. if (ch_num < 0) {
  2136. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2137. return ch_num;
  2138. }
  2139. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2140. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2141. cdc_dma_tx_cfg[ch_num].channels);
  2142. return 1;
  2143. }
  2144. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2145. struct snd_ctl_elem_value *ucontrol)
  2146. {
  2147. int sample_rate_val;
  2148. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2149. if (ch_num < 0) {
  2150. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2151. return ch_num;
  2152. }
  2153. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2154. case SAMPLING_RATE_384KHZ:
  2155. sample_rate_val = 12;
  2156. break;
  2157. case SAMPLING_RATE_352P8KHZ:
  2158. sample_rate_val = 11;
  2159. break;
  2160. case SAMPLING_RATE_192KHZ:
  2161. sample_rate_val = 10;
  2162. break;
  2163. case SAMPLING_RATE_176P4KHZ:
  2164. sample_rate_val = 9;
  2165. break;
  2166. case SAMPLING_RATE_96KHZ:
  2167. sample_rate_val = 8;
  2168. break;
  2169. case SAMPLING_RATE_88P2KHZ:
  2170. sample_rate_val = 7;
  2171. break;
  2172. case SAMPLING_RATE_48KHZ:
  2173. sample_rate_val = 6;
  2174. break;
  2175. case SAMPLING_RATE_44P1KHZ:
  2176. sample_rate_val = 5;
  2177. break;
  2178. case SAMPLING_RATE_32KHZ:
  2179. sample_rate_val = 4;
  2180. break;
  2181. case SAMPLING_RATE_22P05KHZ:
  2182. sample_rate_val = 3;
  2183. break;
  2184. case SAMPLING_RATE_16KHZ:
  2185. sample_rate_val = 2;
  2186. break;
  2187. case SAMPLING_RATE_11P025KHZ:
  2188. sample_rate_val = 1;
  2189. break;
  2190. case SAMPLING_RATE_8KHZ:
  2191. sample_rate_val = 0;
  2192. break;
  2193. default:
  2194. sample_rate_val = 6;
  2195. break;
  2196. }
  2197. ucontrol->value.integer.value[0] = sample_rate_val;
  2198. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2199. cdc_dma_tx_cfg[ch_num].sample_rate);
  2200. return 0;
  2201. }
  2202. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2203. struct snd_ctl_elem_value *ucontrol)
  2204. {
  2205. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2206. if (ch_num < 0) {
  2207. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2208. return ch_num;
  2209. }
  2210. switch (ucontrol->value.integer.value[0]) {
  2211. case 12:
  2212. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2213. break;
  2214. case 11:
  2215. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2216. break;
  2217. case 10:
  2218. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2219. break;
  2220. case 9:
  2221. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2222. break;
  2223. case 8:
  2224. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2225. break;
  2226. case 7:
  2227. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2228. break;
  2229. case 6:
  2230. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2231. break;
  2232. case 5:
  2233. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2234. break;
  2235. case 4:
  2236. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2237. break;
  2238. case 3:
  2239. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2240. break;
  2241. case 2:
  2242. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2243. break;
  2244. case 1:
  2245. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2246. break;
  2247. case 0:
  2248. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2249. break;
  2250. default:
  2251. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2252. break;
  2253. }
  2254. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2255. __func__, ucontrol->value.integer.value[0],
  2256. cdc_dma_tx_cfg[ch_num].sample_rate);
  2257. return 0;
  2258. }
  2259. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2260. struct snd_ctl_elem_value *ucontrol)
  2261. {
  2262. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2263. if (ch_num < 0) {
  2264. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2265. return ch_num;
  2266. }
  2267. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2268. case SNDRV_PCM_FORMAT_S32_LE:
  2269. ucontrol->value.integer.value[0] = 3;
  2270. break;
  2271. case SNDRV_PCM_FORMAT_S24_3LE:
  2272. ucontrol->value.integer.value[0] = 2;
  2273. break;
  2274. case SNDRV_PCM_FORMAT_S24_LE:
  2275. ucontrol->value.integer.value[0] = 1;
  2276. break;
  2277. case SNDRV_PCM_FORMAT_S16_LE:
  2278. default:
  2279. ucontrol->value.integer.value[0] = 0;
  2280. break;
  2281. }
  2282. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2283. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2284. ucontrol->value.integer.value[0]);
  2285. return 0;
  2286. }
  2287. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2288. struct snd_ctl_elem_value *ucontrol)
  2289. {
  2290. int rc = 0;
  2291. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2292. if (ch_num < 0) {
  2293. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2294. return ch_num;
  2295. }
  2296. switch (ucontrol->value.integer.value[0]) {
  2297. case 3:
  2298. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2299. break;
  2300. case 2:
  2301. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2302. break;
  2303. case 1:
  2304. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2305. break;
  2306. case 0:
  2307. default:
  2308. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2309. break;
  2310. }
  2311. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2312. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2313. ucontrol->value.integer.value[0]);
  2314. return rc;
  2315. }
  2316. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2317. {
  2318. int idx = 0;
  2319. switch (be_id) {
  2320. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2321. idx = RX_CDC_DMA_RX_0;
  2322. break;
  2323. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2324. idx = RX_CDC_DMA_RX_1;
  2325. break;
  2326. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2327. idx = RX_CDC_DMA_RX_2;
  2328. break;
  2329. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2330. idx = RX_CDC_DMA_RX_3;
  2331. break;
  2332. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2333. idx = RX_CDC_DMA_RX_5;
  2334. break;
  2335. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2336. idx = TX_CDC_DMA_TX_0;
  2337. break;
  2338. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2339. idx = TX_CDC_DMA_TX_3;
  2340. break;
  2341. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2342. idx = TX_CDC_DMA_TX_4;
  2343. break;
  2344. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2345. idx = VA_CDC_DMA_TX_0;
  2346. break;
  2347. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2348. idx = VA_CDC_DMA_TX_1;
  2349. break;
  2350. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2351. idx = VA_CDC_DMA_TX_2;
  2352. break;
  2353. default:
  2354. idx = RX_CDC_DMA_RX_0;
  2355. break;
  2356. }
  2357. return idx;
  2358. }
  2359. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2360. struct snd_ctl_elem_value *ucontrol)
  2361. {
  2362. /*
  2363. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2364. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2365. * value.
  2366. */
  2367. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2368. case SAMPLING_RATE_96KHZ:
  2369. ucontrol->value.integer.value[0] = 5;
  2370. break;
  2371. case SAMPLING_RATE_88P2KHZ:
  2372. ucontrol->value.integer.value[0] = 4;
  2373. break;
  2374. case SAMPLING_RATE_48KHZ:
  2375. ucontrol->value.integer.value[0] = 3;
  2376. break;
  2377. case SAMPLING_RATE_44P1KHZ:
  2378. ucontrol->value.integer.value[0] = 2;
  2379. break;
  2380. case SAMPLING_RATE_16KHZ:
  2381. ucontrol->value.integer.value[0] = 1;
  2382. break;
  2383. case SAMPLING_RATE_8KHZ:
  2384. default:
  2385. ucontrol->value.integer.value[0] = 0;
  2386. break;
  2387. }
  2388. pr_debug("%s: sample rate = %d\n", __func__,
  2389. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2390. return 0;
  2391. }
  2392. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2393. struct snd_ctl_elem_value *ucontrol)
  2394. {
  2395. switch (ucontrol->value.integer.value[0]) {
  2396. case 1:
  2397. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2398. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2399. break;
  2400. case 2:
  2401. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2402. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2403. break;
  2404. case 3:
  2405. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2406. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2407. break;
  2408. case 4:
  2409. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2410. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2411. break;
  2412. case 5:
  2413. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2414. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2415. break;
  2416. case 0:
  2417. default:
  2418. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2419. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2420. break;
  2421. }
  2422. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2423. __func__,
  2424. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2425. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2426. ucontrol->value.enumerated.item[0]);
  2427. return 0;
  2428. }
  2429. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2430. struct snd_ctl_elem_value *ucontrol)
  2431. {
  2432. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2433. case SAMPLING_RATE_96KHZ:
  2434. ucontrol->value.integer.value[0] = 5;
  2435. break;
  2436. case SAMPLING_RATE_88P2KHZ:
  2437. ucontrol->value.integer.value[0] = 4;
  2438. break;
  2439. case SAMPLING_RATE_48KHZ:
  2440. ucontrol->value.integer.value[0] = 3;
  2441. break;
  2442. case SAMPLING_RATE_44P1KHZ:
  2443. ucontrol->value.integer.value[0] = 2;
  2444. break;
  2445. case SAMPLING_RATE_16KHZ:
  2446. ucontrol->value.integer.value[0] = 1;
  2447. break;
  2448. case SAMPLING_RATE_8KHZ:
  2449. default:
  2450. ucontrol->value.integer.value[0] = 0;
  2451. break;
  2452. }
  2453. pr_debug("%s: sample rate rx = %d\n", __func__,
  2454. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2455. return 0;
  2456. }
  2457. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2458. struct snd_ctl_elem_value *ucontrol)
  2459. {
  2460. switch (ucontrol->value.integer.value[0]) {
  2461. case 1:
  2462. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2463. break;
  2464. case 2:
  2465. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2466. break;
  2467. case 3:
  2468. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2469. break;
  2470. case 4:
  2471. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2472. break;
  2473. case 5:
  2474. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2475. break;
  2476. case 0:
  2477. default:
  2478. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2479. break;
  2480. }
  2481. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2482. __func__,
  2483. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2484. ucontrol->value.enumerated.item[0]);
  2485. return 0;
  2486. }
  2487. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2488. struct snd_ctl_elem_value *ucontrol)
  2489. {
  2490. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2491. case SAMPLING_RATE_96KHZ:
  2492. ucontrol->value.integer.value[0] = 5;
  2493. break;
  2494. case SAMPLING_RATE_88P2KHZ:
  2495. ucontrol->value.integer.value[0] = 4;
  2496. break;
  2497. case SAMPLING_RATE_48KHZ:
  2498. ucontrol->value.integer.value[0] = 3;
  2499. break;
  2500. case SAMPLING_RATE_44P1KHZ:
  2501. ucontrol->value.integer.value[0] = 2;
  2502. break;
  2503. case SAMPLING_RATE_16KHZ:
  2504. ucontrol->value.integer.value[0] = 1;
  2505. break;
  2506. case SAMPLING_RATE_8KHZ:
  2507. default:
  2508. ucontrol->value.integer.value[0] = 0;
  2509. break;
  2510. }
  2511. pr_debug("%s: sample rate tx = %d\n", __func__,
  2512. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2513. return 0;
  2514. }
  2515. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2516. struct snd_ctl_elem_value *ucontrol)
  2517. {
  2518. switch (ucontrol->value.integer.value[0]) {
  2519. case 1:
  2520. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2521. break;
  2522. case 2:
  2523. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2524. break;
  2525. case 3:
  2526. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2527. break;
  2528. case 4:
  2529. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2530. break;
  2531. case 5:
  2532. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2533. break;
  2534. case 0:
  2535. default:
  2536. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2537. break;
  2538. }
  2539. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2540. __func__,
  2541. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2542. ucontrol->value.enumerated.item[0]);
  2543. return 0;
  2544. }
  2545. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2546. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2547. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2548. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2549. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2550. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2551. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2552. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2553. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2554. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2555. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2556. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2557. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2558. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2559. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2560. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2561. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2562. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2563. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2564. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2565. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2566. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2567. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2568. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2569. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2570. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2571. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2572. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2573. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2574. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2575. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2576. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2577. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2578. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2579. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2580. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2581. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2582. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2583. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2584. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2585. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2586. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2587. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2588. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2589. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2590. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2591. rx_cdc_dma_rx_0_sample_rate,
  2592. cdc_dma_rx_sample_rate_get,
  2593. cdc_dma_rx_sample_rate_put),
  2594. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2595. rx_cdc_dma_rx_1_sample_rate,
  2596. cdc_dma_rx_sample_rate_get,
  2597. cdc_dma_rx_sample_rate_put),
  2598. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2599. rx_cdc_dma_rx_2_sample_rate,
  2600. cdc_dma_rx_sample_rate_get,
  2601. cdc_dma_rx_sample_rate_put),
  2602. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2603. rx_cdc_dma_rx_3_sample_rate,
  2604. cdc_dma_rx_sample_rate_get,
  2605. cdc_dma_rx_sample_rate_put),
  2606. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2607. rx_cdc_dma_rx_5_sample_rate,
  2608. cdc_dma_rx_sample_rate_get,
  2609. cdc_dma_rx_sample_rate_put),
  2610. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2611. tx_cdc_dma_tx_0_sample_rate,
  2612. cdc_dma_tx_sample_rate_get,
  2613. cdc_dma_tx_sample_rate_put),
  2614. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2615. tx_cdc_dma_tx_3_sample_rate,
  2616. cdc_dma_tx_sample_rate_get,
  2617. cdc_dma_tx_sample_rate_put),
  2618. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2619. tx_cdc_dma_tx_4_sample_rate,
  2620. cdc_dma_tx_sample_rate_get,
  2621. cdc_dma_tx_sample_rate_put),
  2622. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2623. va_cdc_dma_tx_0_sample_rate,
  2624. cdc_dma_tx_sample_rate_get,
  2625. cdc_dma_tx_sample_rate_put),
  2626. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2627. va_cdc_dma_tx_1_sample_rate,
  2628. cdc_dma_tx_sample_rate_get,
  2629. cdc_dma_tx_sample_rate_put),
  2630. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2631. va_cdc_dma_tx_2_sample_rate,
  2632. cdc_dma_tx_sample_rate_get,
  2633. cdc_dma_tx_sample_rate_put),
  2634. };
  2635. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  2636. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2637. usb_audio_rx_sample_rate_get,
  2638. usb_audio_rx_sample_rate_put),
  2639. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2640. usb_audio_tx_sample_rate_get,
  2641. usb_audio_tx_sample_rate_put),
  2642. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2643. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2644. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2645. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2646. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2647. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2648. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2649. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2650. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2651. proxy_rx_ch_get, proxy_rx_ch_put),
  2652. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2653. msm_bt_sample_rate_get,
  2654. msm_bt_sample_rate_put),
  2655. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  2656. msm_bt_sample_rate_rx_get,
  2657. msm_bt_sample_rate_rx_put),
  2658. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  2659. msm_bt_sample_rate_tx_get,
  2660. msm_bt_sample_rate_tx_put),
  2661. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  2662. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  2663. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2664. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2665. };
  2666. static const struct snd_kcontrol_new msm_tdm_snd_controls[] = {
  2667. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2668. tdm_rx_sample_rate_get,
  2669. tdm_rx_sample_rate_put),
  2670. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2671. tdm_rx_sample_rate_get,
  2672. tdm_rx_sample_rate_put),
  2673. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2674. tdm_rx_sample_rate_get,
  2675. tdm_rx_sample_rate_put),
  2676. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2677. tdm_rx_sample_rate_get,
  2678. tdm_rx_sample_rate_put),
  2679. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2680. tdm_tx_sample_rate_get,
  2681. tdm_tx_sample_rate_put),
  2682. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2683. tdm_tx_sample_rate_get,
  2684. tdm_tx_sample_rate_put),
  2685. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2686. tdm_tx_sample_rate_get,
  2687. tdm_tx_sample_rate_put),
  2688. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2689. tdm_tx_sample_rate_get,
  2690. tdm_tx_sample_rate_put),
  2691. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2692. tdm_rx_format_get,
  2693. tdm_rx_format_put),
  2694. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2695. tdm_rx_format_get,
  2696. tdm_rx_format_put),
  2697. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2698. tdm_rx_format_get,
  2699. tdm_rx_format_put),
  2700. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2701. tdm_rx_format_get,
  2702. tdm_rx_format_put),
  2703. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2704. tdm_tx_format_get,
  2705. tdm_tx_format_put),
  2706. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2707. tdm_tx_format_get,
  2708. tdm_tx_format_put),
  2709. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2710. tdm_tx_format_get,
  2711. tdm_tx_format_put),
  2712. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2713. tdm_tx_format_get,
  2714. tdm_tx_format_put),
  2715. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2716. tdm_rx_ch_get,
  2717. tdm_rx_ch_put),
  2718. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2719. tdm_rx_ch_get,
  2720. tdm_rx_ch_put),
  2721. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2722. tdm_rx_ch_get,
  2723. tdm_rx_ch_put),
  2724. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2725. tdm_rx_ch_get,
  2726. tdm_rx_ch_put),
  2727. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2728. tdm_tx_ch_get,
  2729. tdm_tx_ch_put),
  2730. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2731. tdm_tx_ch_get,
  2732. tdm_tx_ch_put),
  2733. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2734. tdm_tx_ch_get,
  2735. tdm_tx_ch_put),
  2736. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2737. tdm_tx_ch_get,
  2738. tdm_tx_ch_put),
  2739. };
  2740. static const struct snd_kcontrol_new msm_auxpcm_snd_controls[] = {
  2741. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2742. aux_pcm_rx_sample_rate_get,
  2743. aux_pcm_rx_sample_rate_put),
  2744. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2745. aux_pcm_rx_sample_rate_get,
  2746. aux_pcm_rx_sample_rate_put),
  2747. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2748. aux_pcm_rx_sample_rate_get,
  2749. aux_pcm_rx_sample_rate_put),
  2750. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2751. aux_pcm_rx_sample_rate_get,
  2752. aux_pcm_rx_sample_rate_put),
  2753. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2754. aux_pcm_tx_sample_rate_get,
  2755. aux_pcm_tx_sample_rate_put),
  2756. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2757. aux_pcm_tx_sample_rate_get,
  2758. aux_pcm_tx_sample_rate_put),
  2759. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2760. aux_pcm_tx_sample_rate_get,
  2761. aux_pcm_tx_sample_rate_put),
  2762. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2763. aux_pcm_tx_sample_rate_get,
  2764. aux_pcm_tx_sample_rate_put),
  2765. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2766. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2767. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2768. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2769. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2770. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2771. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2772. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2773. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2774. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2775. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2776. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2777. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2778. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2779. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2780. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2781. };
  2782. static const struct snd_kcontrol_new msm_mi2s_snd_controls[] = {
  2783. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2784. mi2s_rx_sample_rate_get,
  2785. mi2s_rx_sample_rate_put),
  2786. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2787. mi2s_rx_sample_rate_get,
  2788. mi2s_rx_sample_rate_put),
  2789. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2790. mi2s_rx_sample_rate_get,
  2791. mi2s_rx_sample_rate_put),
  2792. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2793. mi2s_rx_sample_rate_get,
  2794. mi2s_tx_sample_rate_put),
  2795. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2796. mi2s_tx_sample_rate_get,
  2797. mi2s_tx_sample_rate_put),
  2798. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2799. mi2s_tx_sample_rate_get,
  2800. mi2s_tx_sample_rate_put),
  2801. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2802. mi2s_tx_sample_rate_get,
  2803. mi2s_tx_sample_rate_put),
  2804. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2805. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2806. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2807. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2808. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2809. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2810. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2811. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2812. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2813. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2814. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2815. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2816. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2817. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2818. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2819. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2820. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2821. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2822. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2823. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2824. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2825. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2826. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2827. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2828. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2829. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2830. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2831. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2832. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2833. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2834. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2835. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2836. };
  2837. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2838. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2839. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2840. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2841. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2842. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2843. aux_pcm_rx_sample_rate_get,
  2844. aux_pcm_rx_sample_rate_put),
  2845. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2846. aux_pcm_tx_sample_rate_get,
  2847. aux_pcm_tx_sample_rate_put),
  2848. };
  2849. static int bengal_send_island_va_config(int32_t be_id)
  2850. {
  2851. int rc = 0;
  2852. int port_id = 0xFFFF;
  2853. port_id = msm_get_port_id(be_id);
  2854. if (port_id < 0) {
  2855. pr_err("%s: Invalid island interface, be_id: %d\n",
  2856. __func__, be_id);
  2857. rc = -EINVAL;
  2858. } else {
  2859. /*
  2860. * send island mode config
  2861. * This should be the first configuration
  2862. */
  2863. rc = afe_send_port_island_mode(port_id);
  2864. if (rc)
  2865. pr_err("%s: afe send island mode failed %d\n",
  2866. __func__, rc);
  2867. }
  2868. return rc;
  2869. }
  2870. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  2871. struct snd_pcm_hw_params *params)
  2872. {
  2873. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  2874. struct snd_interval *rate = hw_param_interval(params,
  2875. SNDRV_PCM_HW_PARAM_RATE);
  2876. struct snd_interval *channels = hw_param_interval(params,
  2877. SNDRV_PCM_HW_PARAM_CHANNELS);
  2878. int idx = 0;
  2879. pr_debug("%s: format = %d, rate = %d\n",
  2880. __func__, params_format(params), params_rate(params));
  2881. switch (dai_link->id) {
  2882. case MSM_BACKEND_DAI_USB_RX:
  2883. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2884. usb_rx_cfg.bit_format);
  2885. rate->min = rate->max = usb_rx_cfg.sample_rate;
  2886. channels->min = channels->max = usb_rx_cfg.channels;
  2887. break;
  2888. case MSM_BACKEND_DAI_USB_TX:
  2889. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2890. usb_tx_cfg.bit_format);
  2891. rate->min = rate->max = usb_tx_cfg.sample_rate;
  2892. channels->min = channels->max = usb_tx_cfg.channels;
  2893. break;
  2894. case MSM_BACKEND_DAI_AFE_PCM_RX:
  2895. channels->min = channels->max = proxy_rx_cfg.channels;
  2896. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2897. break;
  2898. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  2899. channels->min = channels->max =
  2900. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  2901. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2902. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  2903. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  2904. break;
  2905. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  2906. channels->min = channels->max =
  2907. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  2908. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2909. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  2910. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  2911. break;
  2912. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  2913. channels->min = channels->max =
  2914. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  2915. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2916. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  2917. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  2918. break;
  2919. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  2920. channels->min = channels->max =
  2921. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  2922. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2923. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  2924. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  2925. break;
  2926. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  2927. channels->min = channels->max =
  2928. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  2929. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2930. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  2931. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  2932. break;
  2933. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  2934. channels->min = channels->max =
  2935. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2936. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2937. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2938. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2939. break;
  2940. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2941. channels->min = channels->max =
  2942. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2943. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2944. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2945. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2946. break;
  2947. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2948. channels->min = channels->max =
  2949. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2950. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2951. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2952. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2953. break;
  2954. case MSM_BACKEND_DAI_AUXPCM_RX:
  2955. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2956. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  2957. rate->min = rate->max =
  2958. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2959. channels->min = channels->max =
  2960. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2961. break;
  2962. case MSM_BACKEND_DAI_AUXPCM_TX:
  2963. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2964. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  2965. rate->min = rate->max =
  2966. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2967. channels->min = channels->max =
  2968. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2969. break;
  2970. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2971. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2972. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  2973. rate->min = rate->max =
  2974. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2975. channels->min = channels->max =
  2976. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2977. break;
  2978. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2979. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2980. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  2981. rate->min = rate->max =
  2982. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2983. channels->min = channels->max =
  2984. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2985. break;
  2986. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2987. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2988. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  2989. rate->min = rate->max =
  2990. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2991. channels->min = channels->max =
  2992. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2993. break;
  2994. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2995. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2996. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  2997. rate->min = rate->max =
  2998. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  2999. channels->min = channels->max =
  3000. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3001. break;
  3002. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3003. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3004. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3005. rate->min = rate->max =
  3006. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3007. channels->min = channels->max =
  3008. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3009. break;
  3010. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3011. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3012. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3013. rate->min = rate->max =
  3014. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3015. channels->min = channels->max =
  3016. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3017. break;
  3018. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3019. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3020. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3021. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3022. channels->min = channels->max =
  3023. mi2s_rx_cfg[PRIM_MI2S].channels;
  3024. break;
  3025. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3026. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3027. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3028. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3029. channels->min = channels->max =
  3030. mi2s_tx_cfg[PRIM_MI2S].channels;
  3031. break;
  3032. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3033. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3034. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3035. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3036. channels->min = channels->max =
  3037. mi2s_rx_cfg[SEC_MI2S].channels;
  3038. break;
  3039. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3040. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3041. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3042. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3043. channels->min = channels->max =
  3044. mi2s_tx_cfg[SEC_MI2S].channels;
  3045. break;
  3046. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3047. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3048. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3049. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3050. channels->min = channels->max =
  3051. mi2s_rx_cfg[TERT_MI2S].channels;
  3052. break;
  3053. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3054. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3055. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3056. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3057. channels->min = channels->max =
  3058. mi2s_tx_cfg[TERT_MI2S].channels;
  3059. break;
  3060. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3061. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3062. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3063. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3064. channels->min = channels->max =
  3065. mi2s_rx_cfg[QUAT_MI2S].channels;
  3066. break;
  3067. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3068. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3069. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3070. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3071. channels->min = channels->max =
  3072. mi2s_tx_cfg[QUAT_MI2S].channels;
  3073. break;
  3074. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3075. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3076. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3077. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3078. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3079. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3080. cdc_dma_rx_cfg[idx].bit_format);
  3081. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3082. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3083. break;
  3084. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3085. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3086. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3087. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3088. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3089. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3090. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3091. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3092. cdc_dma_tx_cfg[idx].bit_format);
  3093. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3094. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3095. break;
  3096. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3097. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3098. slim_rx_cfg[SLIM_RX_7].bit_format);
  3099. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3100. channels->min = channels->max =
  3101. slim_rx_cfg[SLIM_RX_7].channels;
  3102. break;
  3103. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3104. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3105. slim_tx_cfg[SLIM_TX_7].bit_format);
  3106. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3107. channels->min = channels->max =
  3108. slim_tx_cfg[SLIM_TX_7].channels;
  3109. break;
  3110. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3111. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3112. channels->min = channels->max =
  3113. slim_tx_cfg[SLIM_TX_8].channels;
  3114. break;
  3115. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3116. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3117. afe_loopback_tx_cfg[idx].bit_format);
  3118. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3119. channels->min = channels->max =
  3120. afe_loopback_tx_cfg[idx].channels;
  3121. break;
  3122. default:
  3123. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3124. break;
  3125. }
  3126. return 0;
  3127. }
  3128. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component,
  3129. bool active)
  3130. {
  3131. struct snd_soc_card *card = component->card;
  3132. struct msm_asoc_mach_data *pdata =
  3133. snd_soc_card_get_drvdata(card);
  3134. if (!pdata->fsa_handle)
  3135. return false;
  3136. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3137. }
  3138. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3139. {
  3140. int value = 0;
  3141. bool ret = false;
  3142. struct snd_soc_card *card;
  3143. struct msm_asoc_mach_data *pdata;
  3144. if (!component) {
  3145. pr_err("%s component is NULL\n", __func__);
  3146. return false;
  3147. }
  3148. card = component->card;
  3149. pdata = snd_soc_card_get_drvdata(card);
  3150. if (!pdata)
  3151. return false;
  3152. if (wcd_mbhc_cfg.enable_usbc_analog)
  3153. return msm_usbc_swap_gnd_mic(component, active);
  3154. /* if usbc is not defined, swap using us_euro_gpio_p */
  3155. if (pdata->us_euro_gpio_p) {
  3156. value = msm_cdc_pinctrl_get_state(
  3157. pdata->us_euro_gpio_p);
  3158. if (value)
  3159. msm_cdc_pinctrl_select_sleep_state(
  3160. pdata->us_euro_gpio_p);
  3161. else
  3162. msm_cdc_pinctrl_select_active_state(
  3163. pdata->us_euro_gpio_p);
  3164. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3165. __func__, value, !value);
  3166. ret = true;
  3167. }
  3168. return ret;
  3169. }
  3170. static int bengal_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3171. struct snd_pcm_hw_params *params)
  3172. {
  3173. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3174. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3175. int ret = 0;
  3176. int slot_width = 32;
  3177. int channels, slots;
  3178. unsigned int slot_mask, rate, clk_freq;
  3179. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3180. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3181. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3182. switch (cpu_dai->id) {
  3183. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3184. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3185. break;
  3186. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3187. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3188. break;
  3189. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3190. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3191. break;
  3192. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3193. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3194. break;
  3195. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3196. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3197. break;
  3198. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3199. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3200. break;
  3201. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3202. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3203. break;
  3204. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3205. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3206. break;
  3207. default:
  3208. pr_err("%s: dai id 0x%x not supported\n",
  3209. __func__, cpu_dai->id);
  3210. return -EINVAL;
  3211. }
  3212. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3213. /*2 slot config - bits 0 and 1 set for the first two slots */
  3214. slot_mask = 0x0000FFFF >> (16 - slots);
  3215. channels = slots;
  3216. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3217. __func__, slot_width, slots);
  3218. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3219. slots, slot_width);
  3220. if (ret < 0) {
  3221. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3222. __func__, ret);
  3223. goto end;
  3224. }
  3225. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3226. 0, NULL, channels, slot_offset);
  3227. if (ret < 0) {
  3228. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3229. __func__, ret);
  3230. goto end;
  3231. }
  3232. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3233. /*2 slot config - bits 0 and 1 set for the first two slots */
  3234. slot_mask = 0x0000FFFF >> (16 - slots);
  3235. channels = slots;
  3236. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3237. __func__, slot_width, slots);
  3238. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3239. slots, slot_width);
  3240. if (ret < 0) {
  3241. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3242. __func__, ret);
  3243. goto end;
  3244. }
  3245. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3246. channels, slot_offset, 0, NULL);
  3247. if (ret < 0) {
  3248. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3249. __func__, ret);
  3250. goto end;
  3251. }
  3252. } else {
  3253. ret = -EINVAL;
  3254. pr_err("%s: invalid use case, err:%d\n",
  3255. __func__, ret);
  3256. goto end;
  3257. }
  3258. rate = params_rate(params);
  3259. clk_freq = rate * slot_width * slots;
  3260. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3261. if (ret < 0)
  3262. pr_err("%s: failed to set tdm clk, err:%d\n",
  3263. __func__, ret);
  3264. end:
  3265. return ret;
  3266. }
  3267. static int msm_get_tdm_mode(u32 port_id)
  3268. {
  3269. int tdm_mode;
  3270. switch (port_id) {
  3271. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3272. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3273. tdm_mode = TDM_PRI;
  3274. break;
  3275. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3276. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3277. tdm_mode = TDM_SEC;
  3278. break;
  3279. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3280. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3281. tdm_mode = TDM_TERT;
  3282. break;
  3283. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3284. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3285. tdm_mode = TDM_QUAT;
  3286. break;
  3287. default:
  3288. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3289. tdm_mode = -EINVAL;
  3290. }
  3291. return tdm_mode;
  3292. }
  3293. static int bengal_tdm_snd_startup(struct snd_pcm_substream *substream)
  3294. {
  3295. int ret = 0;
  3296. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3297. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3298. struct snd_soc_card *card = rtd->card;
  3299. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3300. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3301. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3302. ret = -EINVAL;
  3303. pr_err("%s: Invalid TDM interface %d\n",
  3304. __func__, ret);
  3305. return ret;
  3306. }
  3307. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3308. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3309. == 0) {
  3310. ret = msm_cdc_pinctrl_select_active_state(
  3311. pdata->mi2s_gpio_p[tdm_mode]);
  3312. if (ret) {
  3313. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3314. __func__, ret);
  3315. goto done;
  3316. }
  3317. }
  3318. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3319. }
  3320. done:
  3321. return ret;
  3322. }
  3323. static void bengal_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3324. {
  3325. int ret = 0;
  3326. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3327. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3328. struct snd_soc_card *card = rtd->card;
  3329. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3330. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3331. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3332. ret = -EINVAL;
  3333. pr_err("%s: Invalid TDM interface %d\n",
  3334. __func__, ret);
  3335. return;
  3336. }
  3337. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3338. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3339. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3340. == 0) {
  3341. ret = msm_cdc_pinctrl_select_sleep_state(
  3342. pdata->mi2s_gpio_p[tdm_mode]);
  3343. if (ret)
  3344. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3345. __func__, ret);
  3346. }
  3347. }
  3348. }
  3349. static int bengal_aux_snd_startup(struct snd_pcm_substream *substream)
  3350. {
  3351. int ret = 0;
  3352. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3353. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3354. struct snd_soc_card *card = rtd->card;
  3355. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3356. u32 aux_mode = cpu_dai->id - 1;
  3357. if (aux_mode >= AUX_PCM_MAX) {
  3358. ret = -EINVAL;
  3359. pr_err("%s: Invalid AUX interface %d\n",
  3360. __func__, ret);
  3361. return ret;
  3362. }
  3363. if (pdata->mi2s_gpio_p[aux_mode]) {
  3364. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3365. == 0) {
  3366. ret = msm_cdc_pinctrl_select_active_state(
  3367. pdata->mi2s_gpio_p[aux_mode]);
  3368. if (ret) {
  3369. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3370. __func__, ret);
  3371. goto done;
  3372. }
  3373. }
  3374. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3375. }
  3376. done:
  3377. return ret;
  3378. }
  3379. static void bengal_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3380. {
  3381. int ret = 0;
  3382. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3383. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3384. struct snd_soc_card *card = rtd->card;
  3385. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3386. u32 aux_mode = cpu_dai->id - 1;
  3387. if (aux_mode >= AUX_PCM_MAX) {
  3388. pr_err("%s: Invalid AUX interface %d\n",
  3389. __func__, ret);
  3390. return;
  3391. }
  3392. if (pdata->mi2s_gpio_p[aux_mode]) {
  3393. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3394. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3395. == 0) {
  3396. ret = msm_cdc_pinctrl_select_sleep_state(
  3397. pdata->mi2s_gpio_p[aux_mode]);
  3398. if (ret)
  3399. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  3400. __func__, ret);
  3401. }
  3402. }
  3403. }
  3404. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  3405. {
  3406. int ret = 0;
  3407. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3408. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3409. switch (dai_link->id) {
  3410. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3411. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3412. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3413. ret = bengal_send_island_va_config(dai_link->id);
  3414. if (ret)
  3415. pr_err("%s: send island va cfg failed, err: %d\n",
  3416. __func__, ret);
  3417. break;
  3418. }
  3419. return ret;
  3420. }
  3421. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3422. struct snd_pcm_hw_params *params)
  3423. {
  3424. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3425. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3426. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3427. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3428. int ret = 0;
  3429. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3430. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3431. u32 user_set_tx_ch = 0;
  3432. u32 user_set_rx_ch = 0;
  3433. u32 ch_id;
  3434. ret = snd_soc_dai_get_channel_map(codec_dai,
  3435. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3436. &rx_ch_cdc_dma);
  3437. if (ret < 0) {
  3438. pr_err("%s: failed to get codec chan map, err:%d\n",
  3439. __func__, ret);
  3440. goto err;
  3441. }
  3442. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3443. switch (dai_link->id) {
  3444. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3445. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3446. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3447. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3448. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3449. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3450. {
  3451. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3452. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3453. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3454. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3455. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3456. user_set_rx_ch, &rx_ch_cdc_dma);
  3457. if (ret < 0) {
  3458. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3459. __func__, ret);
  3460. goto err;
  3461. }
  3462. }
  3463. break;
  3464. }
  3465. } else {
  3466. switch (dai_link->id) {
  3467. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3468. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3469. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3470. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3471. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3472. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3473. {
  3474. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3475. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3476. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3477. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3478. }
  3479. break;
  3480. }
  3481. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3482. &tx_ch_cdc_dma, 0, 0);
  3483. if (ret < 0) {
  3484. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3485. __func__, ret);
  3486. goto err;
  3487. }
  3488. }
  3489. err:
  3490. return ret;
  3491. }
  3492. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3493. {
  3494. cpumask_t mask;
  3495. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  3496. pm_qos_remove_request(&substream->latency_pm_qos_req);
  3497. cpumask_clear(&mask);
  3498. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  3499. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  3500. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  3501. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  3502. pm_qos_add_request(&substream->latency_pm_qos_req,
  3503. PM_QOS_CPU_DMA_LATENCY,
  3504. MSM_LL_QOS_VALUE);
  3505. return 0;
  3506. }
  3507. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3508. {
  3509. int ret = 0;
  3510. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3511. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3512. int index = cpu_dai->id;
  3513. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3514. struct snd_soc_card *card = rtd->card;
  3515. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3516. dev_dbg(rtd->card->dev,
  3517. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3518. __func__, substream->name, substream->stream,
  3519. cpu_dai->name, cpu_dai->id);
  3520. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3521. ret = -EINVAL;
  3522. dev_err(rtd->card->dev,
  3523. "%s: CPU DAI id (%d) out of range\n",
  3524. __func__, cpu_dai->id);
  3525. goto err;
  3526. }
  3527. /*
  3528. * Mutex protection in case the same MI2S
  3529. * interface using for both TX and RX so
  3530. * that the same clock won't be enable twice.
  3531. */
  3532. mutex_lock(&mi2s_intf_conf[index].lock);
  3533. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3534. /* Check if msm needs to provide the clock to the interface */
  3535. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3536. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3537. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3538. }
  3539. ret = msm_mi2s_set_sclk(substream, true);
  3540. if (ret < 0) {
  3541. dev_err(rtd->card->dev,
  3542. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3543. __func__, ret);
  3544. goto clean_up;
  3545. }
  3546. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3547. if (ret < 0) {
  3548. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  3549. __func__, index, ret);
  3550. goto clk_off;
  3551. }
  3552. if (pdata->mi2s_gpio_p[index]) {
  3553. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  3554. == 0) {
  3555. ret = msm_cdc_pinctrl_select_active_state(
  3556. pdata->mi2s_gpio_p[index]);
  3557. if (ret) {
  3558. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  3559. __func__, ret);
  3560. goto clk_off;
  3561. }
  3562. }
  3563. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  3564. }
  3565. }
  3566. clk_off:
  3567. if (ret < 0)
  3568. msm_mi2s_set_sclk(substream, false);
  3569. clean_up:
  3570. if (ret < 0)
  3571. mi2s_intf_conf[index].ref_cnt--;
  3572. mutex_unlock(&mi2s_intf_conf[index].lock);
  3573. err:
  3574. return ret;
  3575. }
  3576. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  3577. {
  3578. int ret = 0;
  3579. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3580. int index = rtd->cpu_dai->id;
  3581. struct snd_soc_card *card = rtd->card;
  3582. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3583. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  3584. substream->name, substream->stream);
  3585. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3586. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  3587. return;
  3588. }
  3589. mutex_lock(&mi2s_intf_conf[index].lock);
  3590. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  3591. if (pdata->mi2s_gpio_p[index]) {
  3592. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  3593. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  3594. == 0) {
  3595. ret = msm_cdc_pinctrl_select_sleep_state(
  3596. pdata->mi2s_gpio_p[index]);
  3597. if (ret)
  3598. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  3599. __func__, ret);
  3600. }
  3601. }
  3602. ret = msm_mi2s_set_sclk(substream, false);
  3603. if (ret < 0)
  3604. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  3605. __func__, index, ret);
  3606. }
  3607. mutex_unlock(&mi2s_intf_conf[index].lock);
  3608. }
  3609. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3610. struct snd_pcm_hw_params *params)
  3611. {
  3612. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3613. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3614. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3615. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3616. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3617. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3618. int ret = 0;
  3619. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3620. codec_dai->name, codec_dai->id);
  3621. ret = snd_soc_dai_get_channel_map(codec_dai,
  3622. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3623. if (ret) {
  3624. dev_err(rtd->dev,
  3625. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3626. __func__, ret);
  3627. goto err;
  3628. }
  3629. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3630. __func__, tx_ch_cnt, dai_link->id);
  3631. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3632. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3633. if (ret)
  3634. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3635. __func__, ret);
  3636. err:
  3637. return ret;
  3638. }
  3639. static struct snd_soc_ops bengal_aux_be_ops = {
  3640. .startup = bengal_aux_snd_startup,
  3641. .shutdown = bengal_aux_snd_shutdown
  3642. };
  3643. static struct snd_soc_ops bengal_tdm_be_ops = {
  3644. .hw_params = bengal_tdm_snd_hw_params,
  3645. .startup = bengal_tdm_snd_startup,
  3646. .shutdown = bengal_tdm_snd_shutdown
  3647. };
  3648. static struct snd_soc_ops msm_mi2s_be_ops = {
  3649. .startup = msm_mi2s_snd_startup,
  3650. .shutdown = msm_mi2s_snd_shutdown,
  3651. };
  3652. static struct snd_soc_ops msm_fe_qos_ops = {
  3653. .prepare = msm_fe_qos_prepare,
  3654. };
  3655. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  3656. .startup = msm_snd_cdc_dma_startup,
  3657. .hw_params = msm_snd_cdc_dma_hw_params,
  3658. };
  3659. static struct snd_soc_ops msm_wcn_ops = {
  3660. .hw_params = msm_wcn_hw_params,
  3661. };
  3662. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3663. struct snd_kcontrol *kcontrol, int event)
  3664. {
  3665. struct msm_asoc_mach_data *pdata = NULL;
  3666. struct snd_soc_component *component =
  3667. snd_soc_dapm_to_component(w->dapm);
  3668. int ret = 0;
  3669. u32 dmic_idx;
  3670. int *dmic_gpio_cnt;
  3671. struct device_node *dmic_gpio;
  3672. char *wname;
  3673. wname = strpbrk(w->name, "0123");
  3674. if (!wname) {
  3675. dev_err(component->dev, "%s: widget not found\n", __func__);
  3676. return -EINVAL;
  3677. }
  3678. ret = kstrtouint(wname, 10, &dmic_idx);
  3679. if (ret < 0) {
  3680. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3681. __func__);
  3682. return -EINVAL;
  3683. }
  3684. pdata = snd_soc_card_get_drvdata(component->card);
  3685. switch (dmic_idx) {
  3686. case 0:
  3687. case 1:
  3688. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  3689. dmic_gpio = pdata->dmic01_gpio_p;
  3690. break;
  3691. case 2:
  3692. case 3:
  3693. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  3694. dmic_gpio = pdata->dmic23_gpio_p;
  3695. break;
  3696. default:
  3697. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3698. __func__);
  3699. return -EINVAL;
  3700. }
  3701. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3702. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3703. switch (event) {
  3704. case SND_SOC_DAPM_PRE_PMU:
  3705. (*dmic_gpio_cnt)++;
  3706. if (*dmic_gpio_cnt == 1) {
  3707. ret = msm_cdc_pinctrl_select_active_state(
  3708. dmic_gpio);
  3709. if (ret < 0) {
  3710. pr_err("%s: gpio set cannot be activated %sd",
  3711. __func__, "dmic_gpio");
  3712. return ret;
  3713. }
  3714. }
  3715. break;
  3716. case SND_SOC_DAPM_POST_PMD:
  3717. (*dmic_gpio_cnt)--;
  3718. if (*dmic_gpio_cnt == 0) {
  3719. ret = msm_cdc_pinctrl_select_sleep_state(
  3720. dmic_gpio);
  3721. if (ret < 0) {
  3722. pr_err("%s: gpio set cannot be de-activated %sd",
  3723. __func__, "dmic_gpio");
  3724. return ret;
  3725. }
  3726. }
  3727. break;
  3728. default:
  3729. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  3730. return -EINVAL;
  3731. }
  3732. return 0;
  3733. }
  3734. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  3735. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  3736. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  3737. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3738. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3739. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3740. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3741. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3742. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3743. };
  3744. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3745. {
  3746. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3747. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3748. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3749. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3750. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3751. }
  3752. #ifndef CONFIG_TDM_DISABLE
  3753. static void msm_add_tdm_snd_controls(struct snd_soc_component *component)
  3754. {
  3755. snd_soc_add_component_controls(component, msm_tdm_snd_controls,
  3756. ARRAY_SIZE(msm_tdm_snd_controls));
  3757. }
  3758. #else
  3759. static void msm_add_tdm_snd_controls(struct snd_soc_component *component)
  3760. {
  3761. return;
  3762. }
  3763. #endif
  3764. #ifndef CONFIG_MI2S_DISABLE
  3765. static void msm_add_mi2s_snd_controls(struct snd_soc_component *component)
  3766. {
  3767. snd_soc_add_component_controls(component, msm_mi2s_snd_controls,
  3768. ARRAY_SIZE(msm_mi2s_snd_controls));
  3769. }
  3770. #else
  3771. static void msm_add_mi2s_snd_controls(struct snd_soc_component *component)
  3772. {
  3773. return;
  3774. }
  3775. #endif
  3776. #ifndef CONFIG_AUXPCM_DISABLE
  3777. static void msm_add_auxpcm_snd_controls(struct snd_soc_component *component)
  3778. {
  3779. snd_soc_add_component_controls(component, msm_auxpcm_snd_controls,
  3780. ARRAY_SIZE(msm_auxpcm_snd_controls));
  3781. }
  3782. #else
  3783. static void msm_add_auxpcm_snd_controls(struct snd_soc_component *component)
  3784. {
  3785. return;
  3786. }
  3787. #endif
  3788. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3789. {
  3790. int ret = -EINVAL;
  3791. struct snd_soc_component *component;
  3792. struct snd_soc_dapm_context *dapm;
  3793. struct snd_card *card;
  3794. struct snd_info_entry *entry;
  3795. struct msm_asoc_mach_data *pdata =
  3796. snd_soc_card_get_drvdata(rtd->card);
  3797. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  3798. if (!component) {
  3799. pr_err("%s: could not find component for bolero_codec\n",
  3800. __func__);
  3801. return ret;
  3802. }
  3803. dapm = snd_soc_component_get_dapm(component);
  3804. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  3805. ARRAY_SIZE(msm_int_snd_controls));
  3806. if (ret < 0) {
  3807. pr_err("%s: add_component_controls failed: %d\n",
  3808. __func__, ret);
  3809. return ret;
  3810. }
  3811. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  3812. ARRAY_SIZE(msm_common_snd_controls));
  3813. if (ret < 0) {
  3814. pr_err("%s: add common snd controls failed: %d\n",
  3815. __func__, ret);
  3816. return ret;
  3817. }
  3818. msm_add_tdm_snd_controls(component);
  3819. msm_add_mi2s_snd_controls(component);
  3820. msm_add_auxpcm_snd_controls(component);
  3821. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  3822. ARRAY_SIZE(msm_int_dapm_widgets));
  3823. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3824. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3825. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3826. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3827. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  3828. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  3829. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3830. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3831. snd_soc_dapm_sync(dapm);
  3832. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  3833. sm_port_map);
  3834. card = rtd->card->snd_card;
  3835. if (!pdata->codec_root) {
  3836. entry = snd_info_create_subdir(card->module, "codecs",
  3837. card->proc_root);
  3838. if (!entry) {
  3839. pr_debug("%s: Cannot create codecs module entry\n",
  3840. __func__);
  3841. ret = 0;
  3842. goto err;
  3843. }
  3844. pdata->codec_root = entry;
  3845. }
  3846. bolero_info_create_codec_entry(pdata->codec_root, component);
  3847. bolero_register_wake_irq(component, false);
  3848. codec_reg_done = true;
  3849. return 0;
  3850. err:
  3851. return ret;
  3852. }
  3853. static void *def_wcd_mbhc_cal(void)
  3854. {
  3855. void *wcd_mbhc_cal;
  3856. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  3857. u16 *btn_high;
  3858. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  3859. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  3860. if (!wcd_mbhc_cal)
  3861. return NULL;
  3862. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  3863. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  3864. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  3865. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  3866. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  3867. btn_high[0] = 75;
  3868. btn_high[1] = 150;
  3869. btn_high[2] = 237;
  3870. btn_high[3] = 500;
  3871. btn_high[4] = 500;
  3872. btn_high[5] = 500;
  3873. btn_high[6] = 500;
  3874. btn_high[7] = 500;
  3875. return wcd_mbhc_cal;
  3876. }
  3877. /* Digital audio interface glue - connects codec <---> CPU */
  3878. static struct snd_soc_dai_link msm_common_dai_links[] = {
  3879. /* FrontEnd DAI Links */
  3880. {/* hw:x,0 */
  3881. .name = MSM_DAILINK_NAME(Media1),
  3882. .stream_name = "MultiMedia1",
  3883. .cpu_dai_name = "MultiMedia1",
  3884. .platform_name = "msm-pcm-dsp.0",
  3885. .dynamic = 1,
  3886. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3887. .dpcm_playback = 1,
  3888. .dpcm_capture = 1,
  3889. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3890. SND_SOC_DPCM_TRIGGER_POST},
  3891. .codec_dai_name = "snd-soc-dummy-dai",
  3892. .codec_name = "snd-soc-dummy",
  3893. .ignore_suspend = 1,
  3894. /* this dainlink has playback support */
  3895. .ignore_pmdown_time = 1,
  3896. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  3897. },
  3898. {/* hw:x,1 */
  3899. .name = MSM_DAILINK_NAME(Media2),
  3900. .stream_name = "MultiMedia2",
  3901. .cpu_dai_name = "MultiMedia2",
  3902. .platform_name = "msm-pcm-dsp.0",
  3903. .dynamic = 1,
  3904. .dpcm_playback = 1,
  3905. .dpcm_capture = 1,
  3906. .codec_dai_name = "snd-soc-dummy-dai",
  3907. .codec_name = "snd-soc-dummy",
  3908. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3909. SND_SOC_DPCM_TRIGGER_POST},
  3910. .ignore_suspend = 1,
  3911. /* this dainlink has playback support */
  3912. .ignore_pmdown_time = 1,
  3913. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  3914. },
  3915. {/* hw:x,2 */
  3916. .name = "VoiceMMode1",
  3917. .stream_name = "VoiceMMode1",
  3918. .cpu_dai_name = "VoiceMMode1",
  3919. .platform_name = "msm-pcm-voice",
  3920. .dynamic = 1,
  3921. .dpcm_playback = 1,
  3922. .dpcm_capture = 1,
  3923. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3924. SND_SOC_DPCM_TRIGGER_POST},
  3925. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3926. .ignore_suspend = 1,
  3927. .ignore_pmdown_time = 1,
  3928. .codec_dai_name = "snd-soc-dummy-dai",
  3929. .codec_name = "snd-soc-dummy",
  3930. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  3931. },
  3932. {/* hw:x,3 */
  3933. .name = "MSM VoIP",
  3934. .stream_name = "VoIP",
  3935. .cpu_dai_name = "VoIP",
  3936. .platform_name = "msm-voip-dsp",
  3937. .dynamic = 1,
  3938. .dpcm_playback = 1,
  3939. .dpcm_capture = 1,
  3940. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3941. SND_SOC_DPCM_TRIGGER_POST},
  3942. .codec_dai_name = "snd-soc-dummy-dai",
  3943. .codec_name = "snd-soc-dummy",
  3944. .ignore_suspend = 1,
  3945. /* this dainlink has playback support */
  3946. .ignore_pmdown_time = 1,
  3947. .id = MSM_FRONTEND_DAI_VOIP,
  3948. },
  3949. {/* hw:x,4 */
  3950. .name = MSM_DAILINK_NAME(ULL),
  3951. .stream_name = "MultiMedia3",
  3952. .cpu_dai_name = "MultiMedia3",
  3953. .platform_name = "msm-pcm-dsp.2",
  3954. .dynamic = 1,
  3955. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3956. .dpcm_playback = 1,
  3957. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3958. SND_SOC_DPCM_TRIGGER_POST},
  3959. .codec_dai_name = "snd-soc-dummy-dai",
  3960. .codec_name = "snd-soc-dummy",
  3961. .ignore_suspend = 1,
  3962. /* this dainlink has playback support */
  3963. .ignore_pmdown_time = 1,
  3964. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  3965. },
  3966. {/* hw:x,5 */
  3967. .name = "MSM AFE-PCM RX",
  3968. .stream_name = "AFE-PROXY RX",
  3969. .cpu_dai_name = "msm-dai-q6-dev.241",
  3970. .codec_name = "msm-stub-codec.1",
  3971. .codec_dai_name = "msm-stub-rx",
  3972. .platform_name = "msm-pcm-afe",
  3973. .dpcm_playback = 1,
  3974. .ignore_suspend = 1,
  3975. /* this dainlink has playback support */
  3976. .ignore_pmdown_time = 1,
  3977. },
  3978. {/* hw:x,6 */
  3979. .name = "MSM AFE-PCM TX",
  3980. .stream_name = "AFE-PROXY TX",
  3981. .cpu_dai_name = "msm-dai-q6-dev.240",
  3982. .codec_name = "msm-stub-codec.1",
  3983. .codec_dai_name = "msm-stub-tx",
  3984. .platform_name = "msm-pcm-afe",
  3985. .dpcm_capture = 1,
  3986. .ignore_suspend = 1,
  3987. },
  3988. {/* hw:x,7 */
  3989. .name = MSM_DAILINK_NAME(Compress1),
  3990. .stream_name = "Compress1",
  3991. .cpu_dai_name = "MultiMedia4",
  3992. .platform_name = "msm-compress-dsp",
  3993. .dynamic = 1,
  3994. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  3995. .dpcm_playback = 1,
  3996. .dpcm_capture = 1,
  3997. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3998. SND_SOC_DPCM_TRIGGER_POST},
  3999. .codec_dai_name = "snd-soc-dummy-dai",
  4000. .codec_name = "snd-soc-dummy",
  4001. .ignore_suspend = 1,
  4002. .ignore_pmdown_time = 1,
  4003. /* this dainlink has playback support */
  4004. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4005. },
  4006. /* Hostless PCM purpose */
  4007. {/* hw:x,8 */
  4008. .name = "AUXPCM Hostless",
  4009. .stream_name = "AUXPCM Hostless",
  4010. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4011. .platform_name = "msm-pcm-hostless",
  4012. .dynamic = 1,
  4013. .dpcm_playback = 1,
  4014. .dpcm_capture = 1,
  4015. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4016. SND_SOC_DPCM_TRIGGER_POST},
  4017. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4018. .ignore_suspend = 1,
  4019. /* this dainlink has playback support */
  4020. .ignore_pmdown_time = 1,
  4021. .codec_dai_name = "snd-soc-dummy-dai",
  4022. .codec_name = "snd-soc-dummy",
  4023. },
  4024. {/* hw:x,9 */
  4025. .name = MSM_DAILINK_NAME(LowLatency),
  4026. .stream_name = "MultiMedia5",
  4027. .cpu_dai_name = "MultiMedia5",
  4028. .platform_name = "msm-pcm-dsp.1",
  4029. .dynamic = 1,
  4030. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4031. .dpcm_playback = 1,
  4032. .dpcm_capture = 1,
  4033. .codec_dai_name = "snd-soc-dummy-dai",
  4034. .codec_name = "snd-soc-dummy",
  4035. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4036. SND_SOC_DPCM_TRIGGER_POST},
  4037. .ignore_suspend = 1,
  4038. /* this dainlink has playback support */
  4039. .ignore_pmdown_time = 1,
  4040. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4041. .ops = &msm_fe_qos_ops,
  4042. },
  4043. {/* hw:x,10 */
  4044. .name = "Listen 1 Audio Service",
  4045. .stream_name = "Listen 1 Audio Service",
  4046. .cpu_dai_name = "LSM1",
  4047. .platform_name = "msm-lsm-client",
  4048. .dynamic = 1,
  4049. .dpcm_capture = 1,
  4050. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4051. SND_SOC_DPCM_TRIGGER_POST },
  4052. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4053. .ignore_suspend = 1,
  4054. .codec_dai_name = "snd-soc-dummy-dai",
  4055. .codec_name = "snd-soc-dummy",
  4056. .id = MSM_FRONTEND_DAI_LSM1,
  4057. },
  4058. /* Multiple Tunnel instances */
  4059. {/* hw:x,11 */
  4060. .name = MSM_DAILINK_NAME(Compress2),
  4061. .stream_name = "Compress2",
  4062. .cpu_dai_name = "MultiMedia7",
  4063. .platform_name = "msm-compress-dsp",
  4064. .dynamic = 1,
  4065. .dpcm_playback = 1,
  4066. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4067. SND_SOC_DPCM_TRIGGER_POST},
  4068. .codec_dai_name = "snd-soc-dummy-dai",
  4069. .codec_name = "snd-soc-dummy",
  4070. .ignore_suspend = 1,
  4071. .ignore_pmdown_time = 1,
  4072. /* this dainlink has playback support */
  4073. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4074. },
  4075. {/* hw:x,12 */
  4076. .name = MSM_DAILINK_NAME(MultiMedia10),
  4077. .stream_name = "MultiMedia10",
  4078. .cpu_dai_name = "MultiMedia10",
  4079. .platform_name = "msm-pcm-dsp.1",
  4080. .dynamic = 1,
  4081. .dpcm_playback = 1,
  4082. .dpcm_capture = 1,
  4083. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4084. SND_SOC_DPCM_TRIGGER_POST},
  4085. .codec_dai_name = "snd-soc-dummy-dai",
  4086. .codec_name = "snd-soc-dummy",
  4087. .ignore_suspend = 1,
  4088. .ignore_pmdown_time = 1,
  4089. /* this dainlink has playback support */
  4090. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4091. },
  4092. {/* hw:x,13 */
  4093. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4094. .stream_name = "MM_NOIRQ",
  4095. .cpu_dai_name = "MultiMedia8",
  4096. .platform_name = "msm-pcm-dsp-noirq",
  4097. .dynamic = 1,
  4098. .dpcm_playback = 1,
  4099. .dpcm_capture = 1,
  4100. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4101. SND_SOC_DPCM_TRIGGER_POST},
  4102. .codec_dai_name = "snd-soc-dummy-dai",
  4103. .codec_name = "snd-soc-dummy",
  4104. .ignore_suspend = 1,
  4105. .ignore_pmdown_time = 1,
  4106. /* this dainlink has playback support */
  4107. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4108. .ops = &msm_fe_qos_ops,
  4109. },
  4110. /* HDMI Hostless */
  4111. {/* hw:x,14 */
  4112. .name = "HDMI_RX_HOSTLESS",
  4113. .stream_name = "HDMI_RX_HOSTLESS",
  4114. .cpu_dai_name = "HDMI_HOSTLESS",
  4115. .platform_name = "msm-pcm-hostless",
  4116. .dynamic = 1,
  4117. .dpcm_playback = 1,
  4118. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4119. SND_SOC_DPCM_TRIGGER_POST},
  4120. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4121. .ignore_suspend = 1,
  4122. .ignore_pmdown_time = 1,
  4123. .codec_dai_name = "snd-soc-dummy-dai",
  4124. .codec_name = "snd-soc-dummy",
  4125. },
  4126. {/* hw:x,15 */
  4127. .name = "VoiceMMode2",
  4128. .stream_name = "VoiceMMode2",
  4129. .cpu_dai_name = "VoiceMMode2",
  4130. .platform_name = "msm-pcm-voice",
  4131. .dynamic = 1,
  4132. .dpcm_playback = 1,
  4133. .dpcm_capture = 1,
  4134. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4135. SND_SOC_DPCM_TRIGGER_POST},
  4136. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4137. .ignore_suspend = 1,
  4138. .ignore_pmdown_time = 1,
  4139. .codec_dai_name = "snd-soc-dummy-dai",
  4140. .codec_name = "snd-soc-dummy",
  4141. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4142. },
  4143. /* LSM FE */
  4144. {/* hw:x,16 */
  4145. .name = "Listen 2 Audio Service",
  4146. .stream_name = "Listen 2 Audio Service",
  4147. .cpu_dai_name = "LSM2",
  4148. .platform_name = "msm-lsm-client",
  4149. .dynamic = 1,
  4150. .dpcm_capture = 1,
  4151. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4152. SND_SOC_DPCM_TRIGGER_POST },
  4153. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4154. .ignore_suspend = 1,
  4155. .codec_dai_name = "snd-soc-dummy-dai",
  4156. .codec_name = "snd-soc-dummy",
  4157. .id = MSM_FRONTEND_DAI_LSM2,
  4158. },
  4159. {/* hw:x,17 */
  4160. .name = "Listen 3 Audio Service",
  4161. .stream_name = "Listen 3 Audio Service",
  4162. .cpu_dai_name = "LSM3",
  4163. .platform_name = "msm-lsm-client",
  4164. .dynamic = 1,
  4165. .dpcm_capture = 1,
  4166. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4167. SND_SOC_DPCM_TRIGGER_POST },
  4168. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4169. .ignore_suspend = 1,
  4170. .codec_dai_name = "snd-soc-dummy-dai",
  4171. .codec_name = "snd-soc-dummy",
  4172. .id = MSM_FRONTEND_DAI_LSM3,
  4173. },
  4174. {/* hw:x,18 */
  4175. .name = "Listen 4 Audio Service",
  4176. .stream_name = "Listen 4 Audio Service",
  4177. .cpu_dai_name = "LSM4",
  4178. .platform_name = "msm-lsm-client",
  4179. .dynamic = 1,
  4180. .dpcm_capture = 1,
  4181. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4182. SND_SOC_DPCM_TRIGGER_POST },
  4183. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4184. .ignore_suspend = 1,
  4185. .codec_dai_name = "snd-soc-dummy-dai",
  4186. .codec_name = "snd-soc-dummy",
  4187. .id = MSM_FRONTEND_DAI_LSM4,
  4188. },
  4189. {/* hw:x,19 */
  4190. .name = "Listen 5 Audio Service",
  4191. .stream_name = "Listen 5 Audio Service",
  4192. .cpu_dai_name = "LSM5",
  4193. .platform_name = "msm-lsm-client",
  4194. .dynamic = 1,
  4195. .dpcm_capture = 1,
  4196. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4197. SND_SOC_DPCM_TRIGGER_POST },
  4198. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4199. .ignore_suspend = 1,
  4200. .codec_dai_name = "snd-soc-dummy-dai",
  4201. .codec_name = "snd-soc-dummy",
  4202. .id = MSM_FRONTEND_DAI_LSM5,
  4203. },
  4204. {/* hw:x,20 */
  4205. .name = "Listen 6 Audio Service",
  4206. .stream_name = "Listen 6 Audio Service",
  4207. .cpu_dai_name = "LSM6",
  4208. .platform_name = "msm-lsm-client",
  4209. .dynamic = 1,
  4210. .dpcm_capture = 1,
  4211. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4212. SND_SOC_DPCM_TRIGGER_POST },
  4213. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4214. .ignore_suspend = 1,
  4215. .codec_dai_name = "snd-soc-dummy-dai",
  4216. .codec_name = "snd-soc-dummy",
  4217. .id = MSM_FRONTEND_DAI_LSM6,
  4218. },
  4219. {/* hw:x,21 */
  4220. .name = "Listen 7 Audio Service",
  4221. .stream_name = "Listen 7 Audio Service",
  4222. .cpu_dai_name = "LSM7",
  4223. .platform_name = "msm-lsm-client",
  4224. .dynamic = 1,
  4225. .dpcm_capture = 1,
  4226. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4227. SND_SOC_DPCM_TRIGGER_POST },
  4228. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4229. .ignore_suspend = 1,
  4230. .codec_dai_name = "snd-soc-dummy-dai",
  4231. .codec_name = "snd-soc-dummy",
  4232. .id = MSM_FRONTEND_DAI_LSM7,
  4233. },
  4234. {/* hw:x,22 */
  4235. .name = "Listen 8 Audio Service",
  4236. .stream_name = "Listen 8 Audio Service",
  4237. .cpu_dai_name = "LSM8",
  4238. .platform_name = "msm-lsm-client",
  4239. .dynamic = 1,
  4240. .dpcm_capture = 1,
  4241. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4242. SND_SOC_DPCM_TRIGGER_POST },
  4243. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4244. .ignore_suspend = 1,
  4245. .codec_dai_name = "snd-soc-dummy-dai",
  4246. .codec_name = "snd-soc-dummy",
  4247. .id = MSM_FRONTEND_DAI_LSM8,
  4248. },
  4249. {/* hw:x,23 */
  4250. .name = MSM_DAILINK_NAME(Media9),
  4251. .stream_name = "MultiMedia9",
  4252. .cpu_dai_name = "MultiMedia9",
  4253. .platform_name = "msm-pcm-dsp.0",
  4254. .dynamic = 1,
  4255. .dpcm_playback = 1,
  4256. .dpcm_capture = 1,
  4257. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4258. SND_SOC_DPCM_TRIGGER_POST},
  4259. .codec_dai_name = "snd-soc-dummy-dai",
  4260. .codec_name = "snd-soc-dummy",
  4261. .ignore_suspend = 1,
  4262. /* this dainlink has playback support */
  4263. .ignore_pmdown_time = 1,
  4264. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4265. },
  4266. {/* hw:x,24 */
  4267. .name = MSM_DAILINK_NAME(Compress4),
  4268. .stream_name = "Compress4",
  4269. .cpu_dai_name = "MultiMedia11",
  4270. .platform_name = "msm-compress-dsp",
  4271. .dynamic = 1,
  4272. .dpcm_playback = 1,
  4273. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4274. SND_SOC_DPCM_TRIGGER_POST},
  4275. .codec_dai_name = "snd-soc-dummy-dai",
  4276. .codec_name = "snd-soc-dummy",
  4277. .ignore_suspend = 1,
  4278. .ignore_pmdown_time = 1,
  4279. /* this dainlink has playback support */
  4280. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4281. },
  4282. {/* hw:x,25 */
  4283. .name = MSM_DAILINK_NAME(Compress5),
  4284. .stream_name = "Compress5",
  4285. .cpu_dai_name = "MultiMedia12",
  4286. .platform_name = "msm-compress-dsp",
  4287. .dynamic = 1,
  4288. .dpcm_playback = 1,
  4289. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4290. SND_SOC_DPCM_TRIGGER_POST},
  4291. .codec_dai_name = "snd-soc-dummy-dai",
  4292. .codec_name = "snd-soc-dummy",
  4293. .ignore_suspend = 1,
  4294. .ignore_pmdown_time = 1,
  4295. /* this dainlink has playback support */
  4296. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4297. },
  4298. {/* hw:x,26 */
  4299. .name = MSM_DAILINK_NAME(Compress6),
  4300. .stream_name = "Compress6",
  4301. .cpu_dai_name = "MultiMedia13",
  4302. .platform_name = "msm-compress-dsp",
  4303. .dynamic = 1,
  4304. .dpcm_playback = 1,
  4305. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4306. SND_SOC_DPCM_TRIGGER_POST},
  4307. .codec_dai_name = "snd-soc-dummy-dai",
  4308. .codec_name = "snd-soc-dummy",
  4309. .ignore_suspend = 1,
  4310. .ignore_pmdown_time = 1,
  4311. /* this dainlink has playback support */
  4312. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4313. },
  4314. {/* hw:x,27 */
  4315. .name = MSM_DAILINK_NAME(Compress7),
  4316. .stream_name = "Compress7",
  4317. .cpu_dai_name = "MultiMedia14",
  4318. .platform_name = "msm-compress-dsp",
  4319. .dynamic = 1,
  4320. .dpcm_playback = 1,
  4321. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4322. SND_SOC_DPCM_TRIGGER_POST},
  4323. .codec_dai_name = "snd-soc-dummy-dai",
  4324. .codec_name = "snd-soc-dummy",
  4325. .ignore_suspend = 1,
  4326. .ignore_pmdown_time = 1,
  4327. /* this dainlink has playback support */
  4328. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4329. },
  4330. {/* hw:x,28 */
  4331. .name = MSM_DAILINK_NAME(Compress8),
  4332. .stream_name = "Compress8",
  4333. .cpu_dai_name = "MultiMedia15",
  4334. .platform_name = "msm-compress-dsp",
  4335. .dynamic = 1,
  4336. .dpcm_playback = 1,
  4337. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4338. SND_SOC_DPCM_TRIGGER_POST},
  4339. .codec_dai_name = "snd-soc-dummy-dai",
  4340. .codec_name = "snd-soc-dummy",
  4341. .ignore_suspend = 1,
  4342. .ignore_pmdown_time = 1,
  4343. /* this dainlink has playback support */
  4344. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4345. },
  4346. {/* hw:x,29 */
  4347. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4348. .stream_name = "MM_NOIRQ_2",
  4349. .cpu_dai_name = "MultiMedia16",
  4350. .platform_name = "msm-pcm-dsp-noirq",
  4351. .dynamic = 1,
  4352. .dpcm_playback = 1,
  4353. .dpcm_capture = 1,
  4354. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4355. SND_SOC_DPCM_TRIGGER_POST},
  4356. .codec_dai_name = "snd-soc-dummy-dai",
  4357. .codec_name = "snd-soc-dummy",
  4358. .ignore_suspend = 1,
  4359. .ignore_pmdown_time = 1,
  4360. /* this dainlink has playback support */
  4361. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4362. .ops = &msm_fe_qos_ops,
  4363. },
  4364. {/* hw:x,30 */
  4365. .name = "CDC_DMA Hostless",
  4366. .stream_name = "CDC_DMA Hostless",
  4367. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  4368. .platform_name = "msm-pcm-hostless",
  4369. .dynamic = 1,
  4370. .dpcm_playback = 1,
  4371. .dpcm_capture = 1,
  4372. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4373. SND_SOC_DPCM_TRIGGER_POST},
  4374. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4375. .ignore_suspend = 1,
  4376. /* this dailink has playback support */
  4377. .ignore_pmdown_time = 1,
  4378. .codec_dai_name = "snd-soc-dummy-dai",
  4379. .codec_name = "snd-soc-dummy",
  4380. },
  4381. {/* hw:x,31 */
  4382. .name = "TX3_CDC_DMA Hostless",
  4383. .stream_name = "TX3_CDC_DMA Hostless",
  4384. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  4385. .platform_name = "msm-pcm-hostless",
  4386. .dynamic = 1,
  4387. .dpcm_capture = 1,
  4388. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4389. SND_SOC_DPCM_TRIGGER_POST},
  4390. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4391. .ignore_suspend = 1,
  4392. .codec_dai_name = "snd-soc-dummy-dai",
  4393. .codec_name = "snd-soc-dummy",
  4394. },
  4395. {/* hw:x,32 */
  4396. .name = "Tertiary MI2S TX_Hostless",
  4397. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4398. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  4399. .platform_name = "msm-pcm-hostless",
  4400. .dynamic = 1,
  4401. .dpcm_capture = 1,
  4402. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4403. SND_SOC_DPCM_TRIGGER_POST},
  4404. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4405. .ignore_suspend = 1,
  4406. .ignore_pmdown_time = 1,
  4407. .codec_dai_name = "snd-soc-dummy-dai",
  4408. .codec_name = "snd-soc-dummy",
  4409. },
  4410. };
  4411. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4412. {/* hw:x,33 */
  4413. .name = MSM_DAILINK_NAME(ASM Loopback),
  4414. .stream_name = "MultiMedia6",
  4415. .cpu_dai_name = "MultiMedia6",
  4416. .platform_name = "msm-pcm-loopback",
  4417. .dynamic = 1,
  4418. .dpcm_playback = 1,
  4419. .dpcm_capture = 1,
  4420. .codec_dai_name = "snd-soc-dummy-dai",
  4421. .codec_name = "snd-soc-dummy",
  4422. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4423. SND_SOC_DPCM_TRIGGER_POST},
  4424. .ignore_suspend = 1,
  4425. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4426. .ignore_pmdown_time = 1,
  4427. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4428. },
  4429. {/* hw:x,34 */
  4430. .name = "USB Audio Hostless",
  4431. .stream_name = "USB Audio Hostless",
  4432. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  4433. .platform_name = "msm-pcm-hostless",
  4434. .dynamic = 1,
  4435. .dpcm_playback = 1,
  4436. .dpcm_capture = 1,
  4437. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4438. SND_SOC_DPCM_TRIGGER_POST},
  4439. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4440. .ignore_suspend = 1,
  4441. .ignore_pmdown_time = 1,
  4442. .codec_dai_name = "snd-soc-dummy-dai",
  4443. .codec_name = "snd-soc-dummy",
  4444. },
  4445. {/* hw:x,35 */
  4446. .name = "SLIMBUS_7 Hostless",
  4447. .stream_name = "SLIMBUS_7 Hostless",
  4448. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  4449. .platform_name = "msm-pcm-hostless",
  4450. .dynamic = 1,
  4451. .dpcm_capture = 1,
  4452. .dpcm_playback = 1,
  4453. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4454. SND_SOC_DPCM_TRIGGER_POST},
  4455. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4456. .ignore_suspend = 1,
  4457. .ignore_pmdown_time = 1,
  4458. .codec_dai_name = "snd-soc-dummy-dai",
  4459. .codec_name = "snd-soc-dummy",
  4460. },
  4461. {/* hw:x,36 */
  4462. .name = "Compress Capture",
  4463. .stream_name = "Compress9",
  4464. .cpu_dai_name = "MultiMedia17",
  4465. .platform_name = "msm-compress-dsp",
  4466. .dynamic = 1,
  4467. .dpcm_capture = 1,
  4468. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4469. SND_SOC_DPCM_TRIGGER_POST},
  4470. .codec_dai_name = "snd-soc-dummy-dai",
  4471. .codec_name = "snd-soc-dummy",
  4472. .ignore_suspend = 1,
  4473. .ignore_pmdown_time = 1,
  4474. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4475. },
  4476. {/* hw:x,37 */
  4477. .name = "SLIMBUS_8 Hostless",
  4478. .stream_name = "SLIMBUS_8 Hostless",
  4479. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  4480. .platform_name = "msm-pcm-hostless",
  4481. .dynamic = 1,
  4482. .dpcm_capture = 1,
  4483. .dpcm_playback = 1,
  4484. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4485. SND_SOC_DPCM_TRIGGER_POST},
  4486. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4487. .ignore_suspend = 1,
  4488. .ignore_pmdown_time = 1,
  4489. .codec_dai_name = "snd-soc-dummy-dai",
  4490. .codec_name = "snd-soc-dummy",
  4491. },
  4492. {/* hw:x,38 */
  4493. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  4494. .stream_name = "TX CDC DMA5 Capture",
  4495. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  4496. .platform_name = "msm-pcm-hostless",
  4497. .codec_name = "bolero_codec",
  4498. .codec_dai_name = "tx_macro_tx3",
  4499. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  4500. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4501. .ignore_suspend = 1,
  4502. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4503. .ops = &msm_cdc_dma_be_ops,
  4504. },
  4505. };
  4506. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4507. /* Backend AFE DAI Links */
  4508. {
  4509. .name = LPASS_BE_AFE_PCM_RX,
  4510. .stream_name = "AFE Playback",
  4511. .cpu_dai_name = "msm-dai-q6-dev.224",
  4512. .platform_name = "msm-pcm-routing",
  4513. .codec_name = "msm-stub-codec.1",
  4514. .codec_dai_name = "msm-stub-rx",
  4515. .no_pcm = 1,
  4516. .dpcm_playback = 1,
  4517. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4518. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4519. /* this dainlink has playback support */
  4520. .ignore_pmdown_time = 1,
  4521. .ignore_suspend = 1,
  4522. },
  4523. {
  4524. .name = LPASS_BE_AFE_PCM_TX,
  4525. .stream_name = "AFE Capture",
  4526. .cpu_dai_name = "msm-dai-q6-dev.225",
  4527. .platform_name = "msm-pcm-routing",
  4528. .codec_name = "msm-stub-codec.1",
  4529. .codec_dai_name = "msm-stub-tx",
  4530. .no_pcm = 1,
  4531. .dpcm_capture = 1,
  4532. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4533. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4534. .ignore_suspend = 1,
  4535. },
  4536. /* Incall Record Uplink BACK END DAI Link */
  4537. {
  4538. .name = LPASS_BE_INCALL_RECORD_TX,
  4539. .stream_name = "Voice Uplink Capture",
  4540. .cpu_dai_name = "msm-dai-q6-dev.32772",
  4541. .platform_name = "msm-pcm-routing",
  4542. .codec_name = "msm-stub-codec.1",
  4543. .codec_dai_name = "msm-stub-tx",
  4544. .no_pcm = 1,
  4545. .dpcm_capture = 1,
  4546. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4547. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4548. .ignore_suspend = 1,
  4549. },
  4550. /* Incall Record Downlink BACK END DAI Link */
  4551. {
  4552. .name = LPASS_BE_INCALL_RECORD_RX,
  4553. .stream_name = "Voice Downlink Capture",
  4554. .cpu_dai_name = "msm-dai-q6-dev.32771",
  4555. .platform_name = "msm-pcm-routing",
  4556. .codec_name = "msm-stub-codec.1",
  4557. .codec_dai_name = "msm-stub-tx",
  4558. .no_pcm = 1,
  4559. .dpcm_capture = 1,
  4560. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4561. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4562. .ignore_suspend = 1,
  4563. },
  4564. /* Incall Music BACK END DAI Link */
  4565. {
  4566. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4567. .stream_name = "Voice Farend Playback",
  4568. .cpu_dai_name = "msm-dai-q6-dev.32773",
  4569. .platform_name = "msm-pcm-routing",
  4570. .codec_name = "msm-stub-codec.1",
  4571. .codec_dai_name = "msm-stub-rx",
  4572. .no_pcm = 1,
  4573. .dpcm_playback = 1,
  4574. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4575. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4576. .ignore_suspend = 1,
  4577. .ignore_pmdown_time = 1,
  4578. },
  4579. /* Incall Music 2 BACK END DAI Link */
  4580. {
  4581. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4582. .stream_name = "Voice2 Farend Playback",
  4583. .cpu_dai_name = "msm-dai-q6-dev.32770",
  4584. .platform_name = "msm-pcm-routing",
  4585. .codec_name = "msm-stub-codec.1",
  4586. .codec_dai_name = "msm-stub-rx",
  4587. .no_pcm = 1,
  4588. .dpcm_playback = 1,
  4589. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4590. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4591. .ignore_suspend = 1,
  4592. .ignore_pmdown_time = 1,
  4593. },
  4594. {
  4595. .name = LPASS_BE_USB_AUDIO_RX,
  4596. .stream_name = "USB Audio Playback",
  4597. .cpu_dai_name = "msm-dai-q6-dev.28672",
  4598. .platform_name = "msm-pcm-routing",
  4599. .codec_name = "msm-stub-codec.1",
  4600. .codec_dai_name = "msm-stub-rx",
  4601. .dynamic_be = 1,
  4602. .no_pcm = 1,
  4603. .dpcm_playback = 1,
  4604. .id = MSM_BACKEND_DAI_USB_RX,
  4605. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4606. .ignore_pmdown_time = 1,
  4607. .ignore_suspend = 1,
  4608. },
  4609. {
  4610. .name = LPASS_BE_USB_AUDIO_TX,
  4611. .stream_name = "USB Audio Capture",
  4612. .cpu_dai_name = "msm-dai-q6-dev.28673",
  4613. .platform_name = "msm-pcm-routing",
  4614. .codec_name = "msm-stub-codec.1",
  4615. .codec_dai_name = "msm-stub-tx",
  4616. .no_pcm = 1,
  4617. .dpcm_capture = 1,
  4618. .id = MSM_BACKEND_DAI_USB_TX,
  4619. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4620. .ignore_suspend = 1,
  4621. },
  4622. };
  4623. static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
  4624. {
  4625. .name = LPASS_BE_PRI_TDM_RX_0,
  4626. .stream_name = "Primary TDM0 Playback",
  4627. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  4628. .platform_name = "msm-pcm-routing",
  4629. .codec_name = "msm-stub-codec.1",
  4630. .codec_dai_name = "msm-stub-rx",
  4631. .no_pcm = 1,
  4632. .dpcm_playback = 1,
  4633. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4634. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4635. .ops = &bengal_tdm_be_ops,
  4636. .ignore_suspend = 1,
  4637. .ignore_pmdown_time = 1,
  4638. },
  4639. {
  4640. .name = LPASS_BE_PRI_TDM_TX_0,
  4641. .stream_name = "Primary TDM0 Capture",
  4642. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  4643. .platform_name = "msm-pcm-routing",
  4644. .codec_name = "msm-stub-codec.1",
  4645. .codec_dai_name = "msm-stub-tx",
  4646. .no_pcm = 1,
  4647. .dpcm_capture = 1,
  4648. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4649. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4650. .ops = &bengal_tdm_be_ops,
  4651. .ignore_suspend = 1,
  4652. },
  4653. {
  4654. .name = LPASS_BE_SEC_TDM_RX_0,
  4655. .stream_name = "Secondary TDM0 Playback",
  4656. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  4657. .platform_name = "msm-pcm-routing",
  4658. .codec_name = "msm-stub-codec.1",
  4659. .codec_dai_name = "msm-stub-rx",
  4660. .no_pcm = 1,
  4661. .dpcm_playback = 1,
  4662. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4663. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4664. .ops = &bengal_tdm_be_ops,
  4665. .ignore_suspend = 1,
  4666. .ignore_pmdown_time = 1,
  4667. },
  4668. {
  4669. .name = LPASS_BE_SEC_TDM_TX_0,
  4670. .stream_name = "Secondary TDM0 Capture",
  4671. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  4672. .platform_name = "msm-pcm-routing",
  4673. .codec_name = "msm-stub-codec.1",
  4674. .codec_dai_name = "msm-stub-tx",
  4675. .no_pcm = 1,
  4676. .dpcm_capture = 1,
  4677. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4678. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4679. .ops = &bengal_tdm_be_ops,
  4680. .ignore_suspend = 1,
  4681. },
  4682. {
  4683. .name = LPASS_BE_TERT_TDM_RX_0,
  4684. .stream_name = "Tertiary TDM0 Playback",
  4685. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  4686. .platform_name = "msm-pcm-routing",
  4687. .codec_name = "msm-stub-codec.1",
  4688. .codec_dai_name = "msm-stub-rx",
  4689. .no_pcm = 1,
  4690. .dpcm_playback = 1,
  4691. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4692. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4693. .ops = &bengal_tdm_be_ops,
  4694. .ignore_suspend = 1,
  4695. .ignore_pmdown_time = 1,
  4696. },
  4697. {
  4698. .name = LPASS_BE_TERT_TDM_TX_0,
  4699. .stream_name = "Tertiary TDM0 Capture",
  4700. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  4701. .platform_name = "msm-pcm-routing",
  4702. .codec_name = "msm-stub-codec.1",
  4703. .codec_dai_name = "msm-stub-tx",
  4704. .no_pcm = 1,
  4705. .dpcm_capture = 1,
  4706. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4707. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4708. .ops = &bengal_tdm_be_ops,
  4709. .ignore_suspend = 1,
  4710. },
  4711. {
  4712. .name = LPASS_BE_QUAT_TDM_RX_0,
  4713. .stream_name = "Quaternary TDM0 Playback",
  4714. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  4715. .platform_name = "msm-pcm-routing",
  4716. .codec_name = "msm-stub-codec.1",
  4717. .codec_dai_name = "msm-stub-rx",
  4718. .no_pcm = 1,
  4719. .dpcm_playback = 1,
  4720. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  4721. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4722. .ops = &bengal_tdm_be_ops,
  4723. .ignore_suspend = 1,
  4724. .ignore_pmdown_time = 1,
  4725. },
  4726. {
  4727. .name = LPASS_BE_QUAT_TDM_TX_0,
  4728. .stream_name = "Quaternary TDM0 Capture",
  4729. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  4730. .platform_name = "msm-pcm-routing",
  4731. .codec_name = "msm-stub-codec.1",
  4732. .codec_dai_name = "msm-stub-tx",
  4733. .no_pcm = 1,
  4734. .dpcm_capture = 1,
  4735. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  4736. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4737. .ops = &bengal_tdm_be_ops,
  4738. .ignore_suspend = 1,
  4739. },
  4740. };
  4741. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  4742. {
  4743. .name = LPASS_BE_SLIMBUS_7_RX,
  4744. .stream_name = "Slimbus7 Playback",
  4745. .cpu_dai_name = "msm-dai-q6-dev.16398",
  4746. .platform_name = "msm-pcm-routing",
  4747. .codec_name = "btfmslim_slave",
  4748. /* BT codec driver determines capabilities based on
  4749. * dai name, bt codecdai name should always contains
  4750. * supported usecase information
  4751. */
  4752. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  4753. .no_pcm = 1,
  4754. .dpcm_playback = 1,
  4755. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  4756. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4757. .init = &msm_wcn_init,
  4758. .ops = &msm_wcn_ops,
  4759. /* dai link has playback support */
  4760. .ignore_pmdown_time = 1,
  4761. .ignore_suspend = 1,
  4762. },
  4763. {
  4764. .name = LPASS_BE_SLIMBUS_7_TX,
  4765. .stream_name = "Slimbus7 Capture",
  4766. .cpu_dai_name = "msm-dai-q6-dev.16399",
  4767. .platform_name = "msm-pcm-routing",
  4768. .codec_name = "btfmslim_slave",
  4769. .codec_dai_name = "btfm_bt_sco_slim_tx",
  4770. .no_pcm = 1,
  4771. .dpcm_capture = 1,
  4772. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  4773. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4774. .ops = &msm_wcn_ops,
  4775. .ignore_suspend = 1,
  4776. },
  4777. {
  4778. .name = LPASS_BE_SLIMBUS_8_TX,
  4779. .stream_name = "Slimbus8 Capture",
  4780. .cpu_dai_name = "msm-dai-q6-dev.16401",
  4781. .platform_name = "msm-pcm-routing",
  4782. .codec_name = "btfmslim_slave",
  4783. .codec_dai_name = "btfm_fm_slim_tx",
  4784. .no_pcm = 1,
  4785. .dpcm_capture = 1,
  4786. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  4787. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4788. .ops = &msm_wcn_ops,
  4789. .ignore_suspend = 1,
  4790. },
  4791. };
  4792. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  4793. {
  4794. .name = LPASS_BE_PRI_MI2S_RX,
  4795. .stream_name = "Primary MI2S Playback",
  4796. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4797. .platform_name = "msm-pcm-routing",
  4798. .codec_name = "msm-stub-codec.1",
  4799. .codec_dai_name = "msm-stub-rx",
  4800. .no_pcm = 1,
  4801. .dpcm_playback = 1,
  4802. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  4803. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4804. .ops = &msm_mi2s_be_ops,
  4805. .ignore_suspend = 1,
  4806. .ignore_pmdown_time = 1,
  4807. },
  4808. {
  4809. .name = LPASS_BE_PRI_MI2S_TX,
  4810. .stream_name = "Primary MI2S Capture",
  4811. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4812. .platform_name = "msm-pcm-routing",
  4813. .codec_name = "msm-stub-codec.1",
  4814. .codec_dai_name = "msm-stub-tx",
  4815. .no_pcm = 1,
  4816. .dpcm_capture = 1,
  4817. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  4818. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4819. .ops = &msm_mi2s_be_ops,
  4820. .ignore_suspend = 1,
  4821. },
  4822. {
  4823. .name = LPASS_BE_SEC_MI2S_RX,
  4824. .stream_name = "Secondary MI2S Playback",
  4825. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4826. .platform_name = "msm-pcm-routing",
  4827. .codec_name = "msm-stub-codec.1",
  4828. .codec_dai_name = "msm-stub-rx",
  4829. .no_pcm = 1,
  4830. .dpcm_playback = 1,
  4831. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  4832. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4833. .ops = &msm_mi2s_be_ops,
  4834. .ignore_suspend = 1,
  4835. .ignore_pmdown_time = 1,
  4836. },
  4837. {
  4838. .name = LPASS_BE_SEC_MI2S_TX,
  4839. .stream_name = "Secondary MI2S Capture",
  4840. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4841. .platform_name = "msm-pcm-routing",
  4842. .codec_name = "msm-stub-codec.1",
  4843. .codec_dai_name = "msm-stub-tx",
  4844. .no_pcm = 1,
  4845. .dpcm_capture = 1,
  4846. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  4847. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4848. .ops = &msm_mi2s_be_ops,
  4849. .ignore_suspend = 1,
  4850. },
  4851. {
  4852. .name = LPASS_BE_TERT_MI2S_RX,
  4853. .stream_name = "Tertiary MI2S Playback",
  4854. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4855. .platform_name = "msm-pcm-routing",
  4856. .codec_name = "msm-stub-codec.1",
  4857. .codec_dai_name = "msm-stub-rx",
  4858. .no_pcm = 1,
  4859. .dpcm_playback = 1,
  4860. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  4861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4862. .ops = &msm_mi2s_be_ops,
  4863. .ignore_suspend = 1,
  4864. .ignore_pmdown_time = 1,
  4865. },
  4866. {
  4867. .name = LPASS_BE_TERT_MI2S_TX,
  4868. .stream_name = "Tertiary MI2S Capture",
  4869. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4870. .platform_name = "msm-pcm-routing",
  4871. .codec_name = "msm-stub-codec.1",
  4872. .codec_dai_name = "msm-stub-tx",
  4873. .no_pcm = 1,
  4874. .dpcm_capture = 1,
  4875. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  4876. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4877. .ops = &msm_mi2s_be_ops,
  4878. .ignore_suspend = 1,
  4879. },
  4880. {
  4881. .name = LPASS_BE_QUAT_MI2S_RX,
  4882. .stream_name = "Quaternary MI2S Playback",
  4883. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  4884. .platform_name = "msm-pcm-routing",
  4885. .codec_name = "msm-stub-codec.1",
  4886. .codec_dai_name = "msm-stub-rx",
  4887. .no_pcm = 1,
  4888. .dpcm_playback = 1,
  4889. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  4890. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4891. .ops = &msm_mi2s_be_ops,
  4892. .ignore_suspend = 1,
  4893. .ignore_pmdown_time = 1,
  4894. },
  4895. {
  4896. .name = LPASS_BE_QUAT_MI2S_TX,
  4897. .stream_name = "Quaternary MI2S Capture",
  4898. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  4899. .platform_name = "msm-pcm-routing",
  4900. .codec_name = "msm-stub-codec.1",
  4901. .codec_dai_name = "msm-stub-tx",
  4902. .no_pcm = 1,
  4903. .dpcm_capture = 1,
  4904. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  4905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4906. .ops = &msm_mi2s_be_ops,
  4907. .ignore_suspend = 1,
  4908. },
  4909. };
  4910. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  4911. /* Primary AUX PCM Backend DAI Links */
  4912. {
  4913. .name = LPASS_BE_AUXPCM_RX,
  4914. .stream_name = "AUX PCM Playback",
  4915. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4916. .platform_name = "msm-pcm-routing",
  4917. .codec_name = "msm-stub-codec.1",
  4918. .codec_dai_name = "msm-stub-rx",
  4919. .no_pcm = 1,
  4920. .dpcm_playback = 1,
  4921. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  4922. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4923. .ops = &bengal_aux_be_ops,
  4924. .ignore_pmdown_time = 1,
  4925. .ignore_suspend = 1,
  4926. },
  4927. {
  4928. .name = LPASS_BE_AUXPCM_TX,
  4929. .stream_name = "AUX PCM Capture",
  4930. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4931. .platform_name = "msm-pcm-routing",
  4932. .codec_name = "msm-stub-codec.1",
  4933. .codec_dai_name = "msm-stub-tx",
  4934. .no_pcm = 1,
  4935. .dpcm_capture = 1,
  4936. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  4937. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4938. .ops = &bengal_aux_be_ops,
  4939. .ignore_suspend = 1,
  4940. },
  4941. /* Secondary AUX PCM Backend DAI Links */
  4942. {
  4943. .name = LPASS_BE_SEC_AUXPCM_RX,
  4944. .stream_name = "Sec AUX PCM Playback",
  4945. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4946. .platform_name = "msm-pcm-routing",
  4947. .codec_name = "msm-stub-codec.1",
  4948. .codec_dai_name = "msm-stub-rx",
  4949. .no_pcm = 1,
  4950. .dpcm_playback = 1,
  4951. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  4952. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4953. .ops = &bengal_aux_be_ops,
  4954. .ignore_pmdown_time = 1,
  4955. .ignore_suspend = 1,
  4956. },
  4957. {
  4958. .name = LPASS_BE_SEC_AUXPCM_TX,
  4959. .stream_name = "Sec AUX PCM Capture",
  4960. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4961. .platform_name = "msm-pcm-routing",
  4962. .codec_name = "msm-stub-codec.1",
  4963. .codec_dai_name = "msm-stub-tx",
  4964. .no_pcm = 1,
  4965. .dpcm_capture = 1,
  4966. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  4967. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4968. .ops = &bengal_aux_be_ops,
  4969. .ignore_suspend = 1,
  4970. },
  4971. /* Tertiary AUX PCM Backend DAI Links */
  4972. {
  4973. .name = LPASS_BE_TERT_AUXPCM_RX,
  4974. .stream_name = "Tert AUX PCM Playback",
  4975. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4976. .platform_name = "msm-pcm-routing",
  4977. .codec_name = "msm-stub-codec.1",
  4978. .codec_dai_name = "msm-stub-rx",
  4979. .no_pcm = 1,
  4980. .dpcm_playback = 1,
  4981. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  4982. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4983. .ops = &bengal_aux_be_ops,
  4984. .ignore_suspend = 1,
  4985. },
  4986. {
  4987. .name = LPASS_BE_TERT_AUXPCM_TX,
  4988. .stream_name = "Tert AUX PCM Capture",
  4989. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4990. .platform_name = "msm-pcm-routing",
  4991. .codec_name = "msm-stub-codec.1",
  4992. .codec_dai_name = "msm-stub-tx",
  4993. .no_pcm = 1,
  4994. .dpcm_capture = 1,
  4995. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  4996. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4997. .ops = &bengal_aux_be_ops,
  4998. .ignore_suspend = 1,
  4999. },
  5000. /* Quaternary AUX PCM Backend DAI Links */
  5001. {
  5002. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5003. .stream_name = "Quat AUX PCM Playback",
  5004. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5005. .platform_name = "msm-pcm-routing",
  5006. .codec_name = "msm-stub-codec.1",
  5007. .codec_dai_name = "msm-stub-rx",
  5008. .no_pcm = 1,
  5009. .dpcm_playback = 1,
  5010. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5011. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5012. .ops = &bengal_aux_be_ops,
  5013. .ignore_suspend = 1,
  5014. },
  5015. {
  5016. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5017. .stream_name = "Quat AUX PCM Capture",
  5018. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5019. .platform_name = "msm-pcm-routing",
  5020. .codec_name = "msm-stub-codec.1",
  5021. .codec_dai_name = "msm-stub-tx",
  5022. .no_pcm = 1,
  5023. .dpcm_capture = 1,
  5024. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5025. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5026. .ops = &bengal_aux_be_ops,
  5027. .ignore_suspend = 1,
  5028. },
  5029. };
  5030. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5031. /* RX CDC DMA Backend DAI Links */
  5032. {
  5033. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5034. .stream_name = "RX CDC DMA0 Playback",
  5035. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  5036. .platform_name = "msm-pcm-routing",
  5037. .codec_name = "bolero_codec",
  5038. .codec_dai_name = "rx_macro_rx1",
  5039. .dynamic_be = 1,
  5040. .no_pcm = 1,
  5041. .dpcm_playback = 1,
  5042. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5043. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5044. .ignore_pmdown_time = 1,
  5045. .ignore_suspend = 1,
  5046. .ops = &msm_cdc_dma_be_ops,
  5047. },
  5048. {
  5049. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5050. .stream_name = "RX CDC DMA1 Playback",
  5051. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  5052. .platform_name = "msm-pcm-routing",
  5053. .codec_name = "bolero_codec",
  5054. .codec_dai_name = "rx_macro_rx2",
  5055. .dynamic_be = 1,
  5056. .no_pcm = 1,
  5057. .dpcm_playback = 1,
  5058. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5059. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5060. .ignore_pmdown_time = 1,
  5061. .ignore_suspend = 1,
  5062. .ops = &msm_cdc_dma_be_ops,
  5063. },
  5064. {
  5065. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5066. .stream_name = "RX CDC DMA2 Playback",
  5067. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  5068. .platform_name = "msm-pcm-routing",
  5069. .codec_name = "bolero_codec",
  5070. .codec_dai_name = "rx_macro_rx3",
  5071. .dynamic_be = 1,
  5072. .no_pcm = 1,
  5073. .dpcm_playback = 1,
  5074. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5075. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5076. .ignore_pmdown_time = 1,
  5077. .ignore_suspend = 1,
  5078. .ops = &msm_cdc_dma_be_ops,
  5079. },
  5080. {
  5081. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5082. .stream_name = "RX CDC DMA3 Playback",
  5083. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  5084. .platform_name = "msm-pcm-routing",
  5085. .codec_name = "bolero_codec",
  5086. .codec_dai_name = "rx_macro_rx4",
  5087. .dynamic_be = 1,
  5088. .no_pcm = 1,
  5089. .dpcm_playback = 1,
  5090. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5091. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5092. .ignore_pmdown_time = 1,
  5093. .ignore_suspend = 1,
  5094. .ops = &msm_cdc_dma_be_ops,
  5095. },
  5096. /* TX CDC DMA Backend DAI Links */
  5097. {
  5098. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5099. .stream_name = "TX CDC DMA3 Capture",
  5100. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  5101. .platform_name = "msm-pcm-routing",
  5102. .codec_name = "bolero_codec",
  5103. .codec_dai_name = "tx_macro_tx1",
  5104. .no_pcm = 1,
  5105. .dpcm_capture = 1,
  5106. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5107. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5108. .ignore_suspend = 1,
  5109. .ops = &msm_cdc_dma_be_ops,
  5110. },
  5111. {
  5112. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5113. .stream_name = "TX CDC DMA4 Capture",
  5114. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  5115. .platform_name = "msm-pcm-routing",
  5116. .codec_name = "bolero_codec",
  5117. .codec_dai_name = "tx_macro_tx2",
  5118. .no_pcm = 1,
  5119. .dpcm_capture = 1,
  5120. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5121. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5122. .ignore_suspend = 1,
  5123. .ops = &msm_cdc_dma_be_ops,
  5124. },
  5125. };
  5126. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5127. {
  5128. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5129. .stream_name = "VA CDC DMA0 Capture",
  5130. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  5131. .platform_name = "msm-pcm-routing",
  5132. .codec_name = "bolero_codec",
  5133. .codec_dai_name = "va_macro_tx1",
  5134. .no_pcm = 1,
  5135. .dpcm_capture = 1,
  5136. .init = &msm_int_audrx_init,
  5137. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5138. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5139. .ignore_suspend = 1,
  5140. .ops = &msm_cdc_dma_be_ops,
  5141. },
  5142. {
  5143. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5144. .stream_name = "VA CDC DMA1 Capture",
  5145. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  5146. .platform_name = "msm-pcm-routing",
  5147. .codec_name = "bolero_codec",
  5148. .codec_dai_name = "va_macro_tx2",
  5149. .no_pcm = 1,
  5150. .dpcm_capture = 1,
  5151. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5152. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5153. .ignore_suspend = 1,
  5154. .ops = &msm_cdc_dma_be_ops,
  5155. },
  5156. {
  5157. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5158. .stream_name = "VA CDC DMA2 Capture",
  5159. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  5160. .platform_name = "msm-pcm-routing",
  5161. .codec_name = "bolero_codec",
  5162. .codec_dai_name = "va_macro_tx3",
  5163. .no_pcm = 1,
  5164. .dpcm_capture = 1,
  5165. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5166. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5167. .ignore_suspend = 1,
  5168. .ops = &msm_cdc_dma_be_ops,
  5169. },
  5170. };
  5171. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5172. {
  5173. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5174. .stream_name = "AFE Loopback Capture",
  5175. .cpu_dai_name = "msm-dai-q6-dev.24577",
  5176. .platform_name = "msm-pcm-routing",
  5177. .codec_name = "msm-stub-codec.1",
  5178. .codec_dai_name = "msm-stub-tx",
  5179. .no_pcm = 1,
  5180. .dpcm_capture = 1,
  5181. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5182. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5183. .ignore_pmdown_time = 1,
  5184. .ignore_suspend = 1,
  5185. },
  5186. };
  5187. static struct snd_soc_dai_link msm_bengal_dai_links[
  5188. ARRAY_SIZE(msm_common_dai_links) +
  5189. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5190. ARRAY_SIZE(msm_common_be_dai_links) +
  5191. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5192. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5193. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5194. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5195. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  5196. ARRAY_SIZE(msm_wcn_btfm_be_dai_links) +
  5197. ARRAY_SIZE(msm_tdm_be_dai_links)];
  5198. static int msm_populate_dai_link_component_of_node(
  5199. struct snd_soc_card *card)
  5200. {
  5201. int i, index, ret = 0;
  5202. struct device *cdev = card->dev;
  5203. struct snd_soc_dai_link *dai_link = card->dai_link;
  5204. struct device_node *np;
  5205. if (!cdev) {
  5206. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5207. return -ENODEV;
  5208. }
  5209. for (i = 0; i < card->num_links; i++) {
  5210. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  5211. continue;
  5212. /* populate platform_of_node for snd card dai links */
  5213. if (dai_link[i].platform_name &&
  5214. !dai_link[i].platform_of_node) {
  5215. index = of_property_match_string(cdev->of_node,
  5216. "asoc-platform-names",
  5217. dai_link[i].platform_name);
  5218. if (index < 0) {
  5219. dev_err(cdev,
  5220. "%s: No match found for platform name: %s\n",
  5221. __func__, dai_link[i].platform_name);
  5222. ret = index;
  5223. goto err;
  5224. }
  5225. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5226. index);
  5227. if (!np) {
  5228. dev_err(cdev,
  5229. "%s: retrieving phandle for platform %s, index %d failed\n",
  5230. __func__, dai_link[i].platform_name,
  5231. index);
  5232. ret = -ENODEV;
  5233. goto err;
  5234. }
  5235. dai_link[i].platform_of_node = np;
  5236. dai_link[i].platform_name = NULL;
  5237. }
  5238. /* populate cpu_of_node for snd card dai links */
  5239. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  5240. index = of_property_match_string(cdev->of_node,
  5241. "asoc-cpu-names",
  5242. dai_link[i].cpu_dai_name);
  5243. if (index >= 0) {
  5244. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5245. index);
  5246. if (!np) {
  5247. dev_err(cdev,
  5248. "%s: retrieving phandle for cpu dai %s failed\n",
  5249. __func__,
  5250. dai_link[i].cpu_dai_name);
  5251. ret = -ENODEV;
  5252. goto err;
  5253. }
  5254. dai_link[i].cpu_of_node = np;
  5255. dai_link[i].cpu_dai_name = NULL;
  5256. }
  5257. }
  5258. /* populate codec_of_node for snd card dai links */
  5259. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  5260. index = of_property_match_string(cdev->of_node,
  5261. "asoc-codec-names",
  5262. dai_link[i].codec_name);
  5263. if (index < 0)
  5264. continue;
  5265. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  5266. index);
  5267. if (!np) {
  5268. dev_err(cdev,
  5269. "%s: retrieving phandle for codec %s failed\n",
  5270. __func__, dai_link[i].codec_name);
  5271. ret = -ENODEV;
  5272. goto err;
  5273. }
  5274. dai_link[i].codec_of_node = np;
  5275. dai_link[i].codec_name = NULL;
  5276. }
  5277. }
  5278. err:
  5279. return ret;
  5280. }
  5281. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5282. {
  5283. int ret = -EINVAL;
  5284. struct snd_soc_component *component =
  5285. snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5286. if (!component) {
  5287. pr_err("* %s: No match for msm-stub-codec component\n",
  5288. __func__);
  5289. return ret;
  5290. }
  5291. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5292. ARRAY_SIZE(msm_snd_controls));
  5293. if (ret < 0) {
  5294. dev_err(component->dev,
  5295. "%s: add_codec_controls failed, err = %d\n",
  5296. __func__, ret);
  5297. return ret;
  5298. }
  5299. return ret;
  5300. }
  5301. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5302. struct snd_pcm_hw_params *params)
  5303. {
  5304. return 0;
  5305. }
  5306. static struct snd_soc_ops msm_stub_be_ops = {
  5307. .hw_params = msm_snd_stub_hw_params,
  5308. };
  5309. struct snd_soc_card snd_soc_card_stub_msm = {
  5310. .name = "bengal-stub-snd-card",
  5311. };
  5312. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5313. /* FrontEnd DAI Links */
  5314. {
  5315. .name = "MSMSTUB Media1",
  5316. .stream_name = "MultiMedia1",
  5317. .cpu_dai_name = "MultiMedia1",
  5318. .platform_name = "msm-pcm-dsp.0",
  5319. .dynamic = 1,
  5320. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5321. .dpcm_playback = 1,
  5322. .dpcm_capture = 1,
  5323. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5324. SND_SOC_DPCM_TRIGGER_POST},
  5325. .codec_dai_name = "snd-soc-dummy-dai",
  5326. .codec_name = "snd-soc-dummy",
  5327. .ignore_suspend = 1,
  5328. /* this dainlink has playback support */
  5329. .ignore_pmdown_time = 1,
  5330. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5331. },
  5332. };
  5333. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5334. /* Backend DAI Links */
  5335. {
  5336. .name = LPASS_BE_AUXPCM_RX,
  5337. .stream_name = "AUX PCM Playback",
  5338. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5339. .platform_name = "msm-pcm-routing",
  5340. .codec_name = "msm-stub-codec.1",
  5341. .codec_dai_name = "msm-stub-rx",
  5342. .no_pcm = 1,
  5343. .dpcm_playback = 1,
  5344. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5345. .init = &msm_audrx_stub_init,
  5346. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5347. .ignore_pmdown_time = 1,
  5348. .ignore_suspend = 1,
  5349. .ops = &msm_stub_be_ops,
  5350. },
  5351. {
  5352. .name = LPASS_BE_AUXPCM_TX,
  5353. .stream_name = "AUX PCM Capture",
  5354. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5355. .platform_name = "msm-pcm-routing",
  5356. .codec_name = "msm-stub-codec.1",
  5357. .codec_dai_name = "msm-stub-tx",
  5358. .no_pcm = 1,
  5359. .dpcm_capture = 1,
  5360. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5361. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5362. .ignore_suspend = 1,
  5363. .ops = &msm_stub_be_ops,
  5364. },
  5365. };
  5366. static struct snd_soc_dai_link msm_stub_dai_links[
  5367. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5368. ARRAY_SIZE(msm_stub_be_dai_links)];
  5369. static const struct of_device_id bengal_asoc_machine_of_match[] = {
  5370. { .compatible = "qcom,bengal-asoc-snd",
  5371. .data = "codec"},
  5372. { .compatible = "qcom,bengal-asoc-snd-stub",
  5373. .data = "stub_codec"},
  5374. {},
  5375. };
  5376. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5377. {
  5378. struct snd_soc_card *card = NULL;
  5379. struct snd_soc_dai_link *dailink = NULL;
  5380. int len_1 = 0;
  5381. int len_2 = 0;
  5382. int total_links = 0;
  5383. int rc = 0;
  5384. u32 mi2s_audio_intf = 0;
  5385. u32 auxpcm_audio_intf = 0;
  5386. u32 rxtx_bolero_codec = 0;
  5387. u32 va_bolero_codec = 0;
  5388. u32 val = 0;
  5389. u32 wcn_btfm_intf = 0;
  5390. const struct of_device_id *match;
  5391. match = of_match_node(bengal_asoc_machine_of_match, dev->of_node);
  5392. if (!match) {
  5393. dev_err(dev, "%s: No DT match found for sound card\n",
  5394. __func__);
  5395. return NULL;
  5396. }
  5397. if (!strcmp(match->data, "codec")) {
  5398. card = &snd_soc_card_bengal_msm;
  5399. memcpy(msm_bengal_dai_links + total_links,
  5400. msm_common_dai_links,
  5401. sizeof(msm_common_dai_links));
  5402. total_links += ARRAY_SIZE(msm_common_dai_links);
  5403. memcpy(msm_bengal_dai_links + total_links,
  5404. msm_common_misc_fe_dai_links,
  5405. sizeof(msm_common_misc_fe_dai_links));
  5406. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5407. memcpy(msm_bengal_dai_links + total_links,
  5408. msm_common_be_dai_links,
  5409. sizeof(msm_common_be_dai_links));
  5410. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5411. rc = of_property_read_u32(dev->of_node,
  5412. "qcom,rxtx-bolero-codec",
  5413. &rxtx_bolero_codec);
  5414. if (rc) {
  5415. dev_dbg(dev, "%s: No DT match RXTX Macro codec\n",
  5416. __func__);
  5417. } else {
  5418. if (rxtx_bolero_codec) {
  5419. memcpy(msm_bengal_dai_links + total_links,
  5420. msm_rx_tx_cdc_dma_be_dai_links,
  5421. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5422. total_links +=
  5423. ARRAY_SIZE(
  5424. msm_rx_tx_cdc_dma_be_dai_links);
  5425. }
  5426. }
  5427. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  5428. &va_bolero_codec);
  5429. if (rc) {
  5430. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  5431. __func__);
  5432. } else {
  5433. if (va_bolero_codec) {
  5434. memcpy(msm_bengal_dai_links + total_links,
  5435. msm_va_cdc_dma_be_dai_links,
  5436. sizeof(msm_va_cdc_dma_be_dai_links));
  5437. total_links +=
  5438. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5439. }
  5440. }
  5441. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5442. &mi2s_audio_intf);
  5443. if (rc) {
  5444. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5445. __func__);
  5446. } else {
  5447. if (mi2s_audio_intf) {
  5448. memcpy(msm_bengal_dai_links + total_links,
  5449. msm_mi2s_be_dai_links,
  5450. sizeof(msm_mi2s_be_dai_links));
  5451. total_links +=
  5452. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5453. }
  5454. }
  5455. rc = of_property_read_u32(dev->of_node,
  5456. "qcom,auxpcm-audio-intf",
  5457. &auxpcm_audio_intf);
  5458. if (rc) {
  5459. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5460. __func__);
  5461. } else {
  5462. if (auxpcm_audio_intf) {
  5463. memcpy(msm_bengal_dai_links + total_links,
  5464. msm_auxpcm_be_dai_links,
  5465. sizeof(msm_auxpcm_be_dai_links));
  5466. total_links +=
  5467. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5468. }
  5469. }
  5470. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5471. &val);
  5472. if (!rc && val) {
  5473. memcpy(msm_bengal_dai_links + total_links,
  5474. msm_afe_rxtx_lb_be_dai_link,
  5475. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5476. total_links +=
  5477. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5478. }
  5479. rc = of_property_read_u32(dev->of_node, "qcom,tdm-audio-intf",
  5480. &val);
  5481. if (!rc && val) {
  5482. memcpy(msm_bengal_dai_links + total_links,
  5483. msm_tdm_be_dai_links,
  5484. sizeof(msm_tdm_be_dai_links));
  5485. total_links +=
  5486. ARRAY_SIZE(msm_tdm_be_dai_links);
  5487. }
  5488. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  5489. &wcn_btfm_intf);
  5490. if (rc) {
  5491. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  5492. __func__);
  5493. } else {
  5494. if (wcn_btfm_intf) {
  5495. memcpy(msm_bengal_dai_links + total_links,
  5496. msm_wcn_btfm_be_dai_links,
  5497. sizeof(msm_wcn_btfm_be_dai_links));
  5498. total_links +=
  5499. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  5500. }
  5501. }
  5502. dailink = msm_bengal_dai_links;
  5503. } else if (!strcmp(match->data, "stub_codec")) {
  5504. card = &snd_soc_card_stub_msm;
  5505. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5506. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5507. memcpy(msm_stub_dai_links,
  5508. msm_stub_fe_dai_links,
  5509. sizeof(msm_stub_fe_dai_links));
  5510. memcpy(msm_stub_dai_links + len_1,
  5511. msm_stub_be_dai_links,
  5512. sizeof(msm_stub_be_dai_links));
  5513. dailink = msm_stub_dai_links;
  5514. total_links = len_2;
  5515. }
  5516. if (card) {
  5517. card->dai_link = dailink;
  5518. card->num_links = total_links;
  5519. }
  5520. return card;
  5521. }
  5522. static int msm_aux_codec_init(struct snd_soc_component *component)
  5523. {
  5524. struct snd_soc_dapm_context *dapm =
  5525. snd_soc_component_get_dapm(component);
  5526. int ret = 0;
  5527. void *mbhc_calibration;
  5528. struct snd_info_entry *entry;
  5529. struct snd_card *card = component->card->snd_card;
  5530. struct msm_asoc_mach_data *pdata;
  5531. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5532. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5533. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5534. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5535. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5536. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5537. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5538. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5539. snd_soc_dapm_sync(dapm);
  5540. pdata = snd_soc_card_get_drvdata(component->card);
  5541. if (!pdata->codec_root) {
  5542. entry = snd_info_create_subdir(card->module, "codecs",
  5543. card->proc_root);
  5544. if (!entry) {
  5545. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5546. __func__);
  5547. ret = 0;
  5548. goto mbhc_cfg_cal;
  5549. }
  5550. pdata->codec_root = entry;
  5551. }
  5552. wcd937x_info_create_codec_entry(pdata->codec_root, component);
  5553. mbhc_cfg_cal:
  5554. mbhc_calibration = def_wcd_mbhc_cal();
  5555. if (!mbhc_calibration)
  5556. return -ENOMEM;
  5557. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5558. ret = wcd937x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5559. if (ret) {
  5560. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5561. __func__, ret);
  5562. goto err_hs_detect;
  5563. }
  5564. return 0;
  5565. err_hs_detect:
  5566. kfree(mbhc_calibration);
  5567. return ret;
  5568. }
  5569. static int msm_init_aux_dev(struct platform_device *pdev,
  5570. struct snd_soc_card *card)
  5571. {
  5572. struct device_node *wsa_of_node;
  5573. struct device_node *aux_codec_of_node;
  5574. u32 wsa_max_devs;
  5575. u32 wsa_dev_cnt;
  5576. u32 codec_max_aux_devs = 0;
  5577. u32 codec_aux_dev_cnt = 0;
  5578. int i;
  5579. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  5580. struct aux_codec_dev_info *aux_cdc_dev_info;
  5581. const char *auxdev_name_prefix[1];
  5582. char *dev_name_str = NULL;
  5583. int found = 0;
  5584. int codecs_found = 0;
  5585. int ret = 0;
  5586. /* Get maximum WSA device count for this platform */
  5587. ret = of_property_read_u32(pdev->dev.of_node,
  5588. "qcom,wsa-max-devs", &wsa_max_devs);
  5589. if (ret) {
  5590. dev_info(&pdev->dev,
  5591. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  5592. __func__, pdev->dev.of_node->full_name, ret);
  5593. wsa_max_devs = 0;
  5594. goto codec_aux_dev;
  5595. }
  5596. if (wsa_max_devs == 0) {
  5597. dev_warn(&pdev->dev,
  5598. "%s: Max WSA devices is 0 for this target?\n",
  5599. __func__);
  5600. goto codec_aux_dev;
  5601. }
  5602. /* Get count of WSA device phandles for this platform */
  5603. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  5604. "qcom,wsa-devs", NULL);
  5605. if (wsa_dev_cnt == -ENOENT) {
  5606. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  5607. __func__);
  5608. goto err;
  5609. } else if (wsa_dev_cnt <= 0) {
  5610. dev_err(&pdev->dev,
  5611. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  5612. __func__, wsa_dev_cnt);
  5613. ret = -EINVAL;
  5614. goto err;
  5615. }
  5616. /*
  5617. * Expect total phandles count to be NOT less than maximum possible
  5618. * WSA count. However, if it is less, then assign same value to
  5619. * max count as well.
  5620. */
  5621. if (wsa_dev_cnt < wsa_max_devs) {
  5622. dev_dbg(&pdev->dev,
  5623. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  5624. __func__, wsa_max_devs, wsa_dev_cnt);
  5625. wsa_max_devs = wsa_dev_cnt;
  5626. }
  5627. /* Make sure prefix string passed for each WSA device */
  5628. ret = of_property_count_strings(pdev->dev.of_node,
  5629. "qcom,wsa-aux-dev-prefix");
  5630. if (ret != wsa_dev_cnt) {
  5631. dev_err(&pdev->dev,
  5632. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  5633. __func__, wsa_dev_cnt, ret);
  5634. ret = -EINVAL;
  5635. goto err;
  5636. }
  5637. /*
  5638. * Alloc mem to store phandle and index info of WSA device, if already
  5639. * registered with ALSA core
  5640. */
  5641. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  5642. sizeof(struct msm_wsa881x_dev_info),
  5643. GFP_KERNEL);
  5644. if (!wsa881x_dev_info) {
  5645. ret = -ENOMEM;
  5646. goto err;
  5647. }
  5648. /*
  5649. * search and check whether all WSA devices are already
  5650. * registered with ALSA core or not. If found a node, store
  5651. * the node and the index in a local array of struct for later
  5652. * use.
  5653. */
  5654. for (i = 0; i < wsa_dev_cnt; i++) {
  5655. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  5656. "qcom,wsa-devs", i);
  5657. if (unlikely(!wsa_of_node)) {
  5658. /* we should not be here */
  5659. dev_err(&pdev->dev,
  5660. "%s: wsa dev node is not present\n",
  5661. __func__);
  5662. ret = -EINVAL;
  5663. goto err;
  5664. }
  5665. if (soc_find_component(wsa_of_node, NULL)) {
  5666. /* WSA device registered with ALSA core */
  5667. wsa881x_dev_info[found].of_node = wsa_of_node;
  5668. wsa881x_dev_info[found].index = i;
  5669. found++;
  5670. if (found == wsa_max_devs)
  5671. break;
  5672. }
  5673. }
  5674. if (found < wsa_max_devs) {
  5675. dev_dbg(&pdev->dev,
  5676. "%s: failed to find %d components. Found only %d\n",
  5677. __func__, wsa_max_devs, found);
  5678. return -EPROBE_DEFER;
  5679. }
  5680. dev_info(&pdev->dev,
  5681. "%s: found %d wsa881x devices registered with ALSA core\n",
  5682. __func__, found);
  5683. codec_aux_dev:
  5684. /* Get maximum aux codec device count for this platform */
  5685. ret = of_property_read_u32(pdev->dev.of_node,
  5686. "qcom,codec-max-aux-devs",
  5687. &codec_max_aux_devs);
  5688. if (ret) {
  5689. dev_err(&pdev->dev,
  5690. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  5691. __func__, pdev->dev.of_node->full_name, ret);
  5692. codec_max_aux_devs = 0;
  5693. goto aux_dev_register;
  5694. }
  5695. if (codec_max_aux_devs == 0) {
  5696. dev_dbg(&pdev->dev,
  5697. "%s: Max aux codec devices is 0 for this target?\n",
  5698. __func__);
  5699. goto aux_dev_register;
  5700. }
  5701. /* Get count of aux codec device phandles for this platform */
  5702. codec_aux_dev_cnt = of_count_phandle_with_args(
  5703. pdev->dev.of_node,
  5704. "qcom,codec-aux-devs", NULL);
  5705. if (codec_aux_dev_cnt == -ENOENT) {
  5706. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  5707. __func__);
  5708. goto err;
  5709. } else if (codec_aux_dev_cnt <= 0) {
  5710. dev_err(&pdev->dev,
  5711. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  5712. __func__, codec_aux_dev_cnt);
  5713. ret = -EINVAL;
  5714. goto err;
  5715. }
  5716. /*
  5717. * Expect total phandles count to be NOT less than maximum possible
  5718. * AUX device count. However, if it is less, then assign same value to
  5719. * max count as well.
  5720. */
  5721. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  5722. dev_dbg(&pdev->dev,
  5723. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  5724. __func__, codec_max_aux_devs,
  5725. codec_aux_dev_cnt);
  5726. codec_max_aux_devs = codec_aux_dev_cnt;
  5727. }
  5728. /*
  5729. * Alloc mem to store phandle and index info of aux codec
  5730. * if already registered with ALSA core
  5731. */
  5732. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  5733. sizeof(struct aux_codec_dev_info),
  5734. GFP_KERNEL);
  5735. if (!aux_cdc_dev_info) {
  5736. ret = -ENOMEM;
  5737. goto err;
  5738. }
  5739. /*
  5740. * search and check whether all aux codecs are already
  5741. * registered with ALSA core or not. If found a node, store
  5742. * the node and the index in a local array of struct for later
  5743. * use.
  5744. */
  5745. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5746. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  5747. "qcom,codec-aux-devs", i);
  5748. if (unlikely(!aux_codec_of_node)) {
  5749. /* we should not be here */
  5750. dev_err(&pdev->dev,
  5751. "%s: aux codec dev node is not present\n",
  5752. __func__);
  5753. ret = -EINVAL;
  5754. goto err;
  5755. }
  5756. if (soc_find_component(aux_codec_of_node, NULL)) {
  5757. /* AUX codec registered with ALSA core */
  5758. aux_cdc_dev_info[codecs_found].of_node =
  5759. aux_codec_of_node;
  5760. aux_cdc_dev_info[codecs_found].index = i;
  5761. codecs_found++;
  5762. }
  5763. }
  5764. if (codecs_found < codec_aux_dev_cnt) {
  5765. dev_dbg(&pdev->dev,
  5766. "%s: failed to find %d components. Found only %d\n",
  5767. __func__, codec_aux_dev_cnt, codecs_found);
  5768. return -EPROBE_DEFER;
  5769. }
  5770. dev_info(&pdev->dev,
  5771. "%s: found %d AUX codecs registered with ALSA core\n",
  5772. __func__, codecs_found);
  5773. aux_dev_register:
  5774. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  5775. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  5776. /* Alloc array of AUX devs struct */
  5777. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  5778. sizeof(struct snd_soc_aux_dev),
  5779. GFP_KERNEL);
  5780. if (!msm_aux_dev) {
  5781. ret = -ENOMEM;
  5782. goto err;
  5783. }
  5784. /* Alloc array of codec conf struct */
  5785. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  5786. sizeof(struct snd_soc_codec_conf),
  5787. GFP_KERNEL);
  5788. if (!msm_codec_conf) {
  5789. ret = -ENOMEM;
  5790. goto err;
  5791. }
  5792. for (i = 0; i < wsa_max_devs; i++) {
  5793. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  5794. GFP_KERNEL);
  5795. if (!dev_name_str) {
  5796. ret = -ENOMEM;
  5797. goto err;
  5798. }
  5799. ret = of_property_read_string_index(pdev->dev.of_node,
  5800. "qcom,wsa-aux-dev-prefix",
  5801. wsa881x_dev_info[i].index,
  5802. auxdev_name_prefix);
  5803. if (ret) {
  5804. dev_err(&pdev->dev,
  5805. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  5806. __func__, ret);
  5807. ret = -EINVAL;
  5808. goto err;
  5809. }
  5810. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  5811. msm_aux_dev[i].name = dev_name_str;
  5812. msm_aux_dev[i].codec_name = NULL;
  5813. msm_aux_dev[i].codec_of_node =
  5814. wsa881x_dev_info[i].of_node;
  5815. msm_aux_dev[i].init = NULL;
  5816. msm_codec_conf[i].dev_name = NULL;
  5817. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  5818. msm_codec_conf[i].of_node =
  5819. wsa881x_dev_info[i].of_node;
  5820. }
  5821. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5822. msm_aux_dev[wsa_max_devs + i].name = NULL;
  5823. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  5824. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  5825. aux_cdc_dev_info[i].of_node;
  5826. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  5827. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  5828. msm_codec_conf[wsa_max_devs + i].name_prefix =
  5829. NULL;
  5830. msm_codec_conf[wsa_max_devs + i].of_node =
  5831. aux_cdc_dev_info[i].of_node;
  5832. }
  5833. card->codec_conf = msm_codec_conf;
  5834. card->aux_dev = msm_aux_dev;
  5835. err:
  5836. return ret;
  5837. }
  5838. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5839. {
  5840. int count = 0;
  5841. u32 mi2s_master_slave[MI2S_MAX];
  5842. int ret = 0;
  5843. for (count = 0; count < MI2S_MAX; count++) {
  5844. mutex_init(&mi2s_intf_conf[count].lock);
  5845. mi2s_intf_conf[count].ref_cnt = 0;
  5846. }
  5847. ret = of_property_read_u32_array(pdev->dev.of_node,
  5848. "qcom,msm-mi2s-master",
  5849. mi2s_master_slave, MI2S_MAX);
  5850. if (ret) {
  5851. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5852. __func__);
  5853. } else {
  5854. for (count = 0; count < MI2S_MAX; count++) {
  5855. mi2s_intf_conf[count].msm_is_mi2s_master =
  5856. mi2s_master_slave[count];
  5857. }
  5858. }
  5859. }
  5860. static void msm_i2s_auxpcm_deinit(void)
  5861. {
  5862. int count = 0;
  5863. for (count = 0; count < MI2S_MAX; count++) {
  5864. mutex_destroy(&mi2s_intf_conf[count].lock);
  5865. mi2s_intf_conf[count].ref_cnt = 0;
  5866. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5867. }
  5868. }
  5869. static int bengal_ssr_enable(struct device *dev, void *data)
  5870. {
  5871. struct platform_device *pdev = to_platform_device(dev);
  5872. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5873. int ret = 0;
  5874. if (!card) {
  5875. dev_err(dev, "%s: card is NULL\n", __func__);
  5876. ret = -EINVAL;
  5877. goto err;
  5878. }
  5879. if (!strcmp(card->name, "bengal-stub-snd-card")) {
  5880. /* TODO */
  5881. dev_dbg(dev, "%s: TODO\n", __func__);
  5882. }
  5883. snd_soc_card_change_online_state(card, 1);
  5884. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5885. err:
  5886. return ret;
  5887. }
  5888. static void bengal_ssr_disable(struct device *dev, void *data)
  5889. {
  5890. struct platform_device *pdev = to_platform_device(dev);
  5891. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5892. if (!card) {
  5893. dev_err(dev, "%s: card is NULL\n", __func__);
  5894. return;
  5895. }
  5896. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5897. snd_soc_card_change_online_state(card, 0);
  5898. if (!strcmp(card->name, "bengal-stub-snd-card")) {
  5899. /* TODO */
  5900. dev_dbg(dev, "%s: TODO\n", __func__);
  5901. }
  5902. }
  5903. static const struct snd_event_ops bengal_ssr_ops = {
  5904. .enable = bengal_ssr_enable,
  5905. .disable = bengal_ssr_disable,
  5906. };
  5907. static int msm_audio_ssr_compare(struct device *dev, void *data)
  5908. {
  5909. struct device_node *node = data;
  5910. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  5911. __func__, dev->of_node, node);
  5912. return (dev->of_node && dev->of_node == node);
  5913. }
  5914. static int msm_audio_ssr_register(struct device *dev)
  5915. {
  5916. struct device_node *np = dev->of_node;
  5917. struct snd_event_clients *ssr_clients = NULL;
  5918. struct device_node *node = NULL;
  5919. int ret = 0;
  5920. int i = 0;
  5921. for (i = 0; ; i++) {
  5922. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  5923. if (!node)
  5924. break;
  5925. snd_event_mstr_add_client(&ssr_clients,
  5926. msm_audio_ssr_compare, node);
  5927. }
  5928. ret = snd_event_master_register(dev, &bengal_ssr_ops,
  5929. ssr_clients, NULL);
  5930. if (!ret)
  5931. snd_event_notify(dev, SND_EVENT_UP);
  5932. return ret;
  5933. }
  5934. static int msm_asoc_machine_probe(struct platform_device *pdev)
  5935. {
  5936. struct snd_soc_card *card = NULL;
  5937. struct msm_asoc_mach_data *pdata = NULL;
  5938. const char *mbhc_audio_jack_type = NULL;
  5939. int ret = 0;
  5940. uint index = 0;
  5941. if (!pdev->dev.of_node) {
  5942. dev_err(&pdev->dev,
  5943. "%s: No platform supplied from device tree\n",
  5944. __func__);
  5945. return -EINVAL;
  5946. }
  5947. pdata = devm_kzalloc(&pdev->dev,
  5948. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  5949. if (!pdata)
  5950. return -ENOMEM;
  5951. card = populate_snd_card_dailinks(&pdev->dev);
  5952. if (!card) {
  5953. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  5954. ret = -EINVAL;
  5955. goto err;
  5956. }
  5957. card->dev = &pdev->dev;
  5958. platform_set_drvdata(pdev, card);
  5959. snd_soc_card_set_drvdata(card, pdata);
  5960. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  5961. if (ret) {
  5962. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  5963. __func__, ret);
  5964. goto err;
  5965. }
  5966. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  5967. if (ret) {
  5968. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  5969. __func__, ret);
  5970. goto err;
  5971. }
  5972. ret = msm_populate_dai_link_component_of_node(card);
  5973. if (ret) {
  5974. ret = -EPROBE_DEFER;
  5975. goto err;
  5976. }
  5977. ret = msm_init_aux_dev(pdev, card);
  5978. if (ret)
  5979. goto err;
  5980. ret = devm_snd_soc_register_card(&pdev->dev, card);
  5981. if (ret == -EPROBE_DEFER) {
  5982. if (codec_reg_done)
  5983. ret = -EINVAL;
  5984. goto err;
  5985. } else if (ret) {
  5986. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  5987. __func__, ret);
  5988. goto err;
  5989. }
  5990. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  5991. __func__, card->name);
  5992. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  5993. "qcom,hph-en1-gpio", 0);
  5994. if (!pdata->hph_en1_gpio_p) {
  5995. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  5996. __func__, "qcom,hph-en1-gpio",
  5997. pdev->dev.of_node->full_name);
  5998. }
  5999. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6000. "qcom,hph-en0-gpio", 0);
  6001. if (!pdata->hph_en0_gpio_p) {
  6002. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6003. __func__, "qcom,hph-en0-gpio",
  6004. pdev->dev.of_node->full_name);
  6005. }
  6006. ret = of_property_read_string(pdev->dev.of_node,
  6007. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6008. if (ret) {
  6009. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6010. __func__, "qcom,mbhc-audio-jack-type",
  6011. pdev->dev.of_node->full_name);
  6012. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6013. } else {
  6014. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6015. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6016. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6017. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6018. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6019. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6020. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6021. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6022. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6023. } else {
  6024. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6025. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6026. }
  6027. }
  6028. /*
  6029. * Parse US-Euro gpio info from DT. Report no error if us-euro
  6030. * entry is not found in DT file as some targets do not support
  6031. * US-Euro detection
  6032. */
  6033. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6034. "qcom,us-euro-gpios", 0);
  6035. if (!pdata->us_euro_gpio_p) {
  6036. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  6037. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  6038. } else {
  6039. dev_dbg(&pdev->dev, "%s detected\n",
  6040. "qcom,us-euro-gpios");
  6041. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  6042. }
  6043. if (wcd_mbhc_cfg.enable_usbc_analog)
  6044. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  6045. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  6046. "fsa4480-i2c-handle", 0);
  6047. if (!pdata->fsa_handle)
  6048. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  6049. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  6050. msm_i2s_auxpcm_init(pdev);
  6051. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6052. "qcom,cdc-dmic01-gpios",
  6053. 0);
  6054. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6055. "qcom,cdc-dmic23-gpios",
  6056. 0);
  6057. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6058. "qcom,pri-mi2s-gpios", 0);
  6059. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6060. "qcom,sec-mi2s-gpios", 0);
  6061. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6062. "qcom,tert-mi2s-gpios", 0);
  6063. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6064. "qcom,quat-mi2s-gpios", 0);
  6065. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  6066. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  6067. ret = msm_audio_ssr_register(&pdev->dev);
  6068. if (ret)
  6069. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  6070. __func__, ret);
  6071. is_initial_boot = true;
  6072. return 0;
  6073. err:
  6074. devm_kfree(&pdev->dev, pdata);
  6075. return ret;
  6076. }
  6077. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6078. {
  6079. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6080. snd_event_master_deregister(&pdev->dev);
  6081. snd_soc_unregister_card(card);
  6082. msm_i2s_auxpcm_deinit();
  6083. return 0;
  6084. }
  6085. static struct platform_driver bengal_asoc_machine_driver = {
  6086. .driver = {
  6087. .name = DRV_NAME,
  6088. .owner = THIS_MODULE,
  6089. .pm = &snd_soc_pm_ops,
  6090. .of_match_table = bengal_asoc_machine_of_match,
  6091. .suppress_bind_attrs = true,
  6092. },
  6093. .probe = msm_asoc_machine_probe,
  6094. .remove = msm_asoc_machine_remove,
  6095. };
  6096. module_platform_driver(bengal_asoc_machine_driver);
  6097. MODULE_DESCRIPTION("ALSA SoC msm");
  6098. MODULE_LICENSE("GPL v2");
  6099. MODULE_ALIAS("platform:" DRV_NAME);
  6100. MODULE_DEVICE_TABLE(of, bengal_asoc_machine_of_match);