91a8910061
git-subtree-dir: qcom/opensource/audio-kernel git-subtree-mainline:99ab089c55git-subtree-split:0ee387dfadChange-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/audio-kernel-ar tag: AUDIO.LA.9.0.r1-07400-lanai.0
285 wiersze
7.4 KiB
C
285 wiersze
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <soc/soundwire.h>
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#define ADDR_BYTES (2)
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#define ADDR_BYTES_4 (4)
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#define VAL_BYTES (1)
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#define PAD_BYTES (0)
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#define SCP1_ADDRESS_VAL_MASK (0x7f800000)
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#define SCP2_ADDRESS_VAL_MASK (0x007f8000)
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#define BIT_WIDTH_CHECK_MASK (0xffff0000)
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#define SCP1_ADDRESS_VAL_SHIFT (23)
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#define SCP2_ADDRESS_VAL_SHIFT (15)
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#define SCP1_ADDRESS (0X48)
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#define SCP2_ADDRESS (0X49)
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#define SDCA_READ_WRITE_BIT (0x8000)
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static DEFINE_MUTEX(swr_rw_lock);
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static int regmap_swr_reg_address_get(struct swr_device *swr,
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u16 *reg_addr, const void *reg, size_t reg_size)
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{
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u8 scp1_val = 0, scp2_val = 0;
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u32 temp = 0;
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int ret = 0;
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if (reg_size == ADDR_BYTES_4) {
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temp = (*(u32 *)reg) & SCP1_ADDRESS_VAL_MASK;
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scp1_val = temp >> SCP1_ADDRESS_VAL_SHIFT;
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temp = (*(u32 *)reg) & SCP2_ADDRESS_VAL_MASK;
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scp2_val = temp >> SCP2_ADDRESS_VAL_SHIFT;
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if (scp1_val || scp2_val) {
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if (scp1_val != swr->scp1_val) {
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ret = swr_write(swr, swr->dev_num, SCP1_ADDRESS, &scp1_val);
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if (ret < 0) {
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dev_err(&swr->dev, "%s: write reg scp1_address failed, err %d\n",
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__func__, ret);
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return ret;
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}
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swr->scp1_val = scp1_val;
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}
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if (scp2_val != swr->scp2_val) {
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ret = swr_write(swr, swr->dev_num, SCP2_ADDRESS, &scp2_val);
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if (ret < 0) {
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dev_err(&swr->dev, "%s: write reg scp2_address failed, err %d\n",
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__func__, ret);
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return ret;
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}
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swr->scp2_val = scp2_val;
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}
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*reg_addr = (*(u16 *)reg | SDCA_READ_WRITE_BIT);
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dev_dbg(&swr->dev, "%s: reg: 0x%x, scp1_val: 0x%x, scp2_val: 0x%x, reg_addr: 0x%x\n",
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__func__, *(u32 *)reg, scp1_val, scp2_val, *reg_addr);
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} else {
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*reg_addr = *(u16 *)reg;
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}
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} else {
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*reg_addr = *(u16 *)reg;
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}
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return ret;
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}
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static int regmap_swr_gather_write(void *context,
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const void *reg, size_t reg_size,
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const void *val, size_t val_len)
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{
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struct device *dev = context;
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struct swr_device *swr = to_swr_device(dev);
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struct regmap *map = dev_get_regmap(dev, NULL);
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int i, ret = 0;
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u16 reg_addr = 0;
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u8 *value;
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if (map == NULL) {
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dev_err_ratelimited(dev, "%s: regmap is NULL\n", __func__);
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return -EINVAL;
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}
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if (swr == NULL) {
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dev_err_ratelimited(dev, "%s: swr device is NULL\n", __func__);
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return -EINVAL;
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}
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if ((reg_size != ADDR_BYTES) && (reg_size != ADDR_BYTES_4)) {
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dev_err_ratelimited(dev, "%s: reg size %zd bytes not supported\n",
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__func__, reg_size);
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return -EINVAL;
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}
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mutex_lock(&swr_rw_lock);
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ret = regmap_swr_reg_address_get(swr, ®_addr, reg, reg_size);
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if (ret < 0) {
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mutex_unlock(&swr_rw_lock);
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return ret;
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}
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/* val_len = VAL_BYTES * val_count */
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for (i = 0; i < (val_len / VAL_BYTES); i++) {
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value = (u8 *)val + (VAL_BYTES * i);
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ret = swr_write(swr, swr->dev_num, (reg_addr + i), value);
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if (ret < 0) {
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dev_err_ratelimited(dev, "%s: write reg 0x%x failed, err %d\n",
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__func__, (reg_addr + i), ret);
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break;
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}
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dev_dbg(dev, "%s: dev_num: 0x%x, gather write reg: 0x%x, value: 0x%x\n",
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__func__, swr->dev_num, (reg_addr + i), *value);
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}
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mutex_unlock(&swr_rw_lock);
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return ret;
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}
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static int regmap_swr_raw_multi_reg_write(void *context, const void *data,
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size_t count)
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{
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struct device *dev = context;
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struct swr_device *swr = to_swr_device(dev);
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struct regmap *map = dev_get_regmap(dev, NULL);
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size_t num_regs;
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int i = 0;
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int ret = 0;
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u16 *reg;
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u8 *val;
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u8 *buf;
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if (swr == NULL) {
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dev_err_ratelimited(dev, "%s: swr device is NULL\n", __func__);
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return -EINVAL;
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}
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if (map == NULL) {
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dev_err_ratelimited(dev, "%s: regmap is NULL\n", __func__);
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return -EINVAL;
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}
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if (ADDR_BYTES + VAL_BYTES + PAD_BYTES == 0) {
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dev_err_ratelimited(dev, "%s: sum of addr, value and pad is 0\n", __func__);
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return -EINVAL;
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}
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num_regs = count / (ADDR_BYTES + VAL_BYTES + PAD_BYTES);
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reg = kcalloc(num_regs, sizeof(u16), GFP_KERNEL);
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if (!reg)
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return -ENOMEM;
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val = kcalloc(num_regs, sizeof(u8), GFP_KERNEL);
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if (!val) {
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ret = -ENOMEM;
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goto mem_fail;
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}
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buf = (u8 *)data;
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for (i = 0; i < num_regs; i++) {
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reg[i] = *(u16 *)buf;
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buf += (ADDR_BYTES + PAD_BYTES);
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val[i] = *buf;
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buf += VAL_BYTES;
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}
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ret = swr_bulk_write(swr, swr->dev_num, reg, val, num_regs);
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if (ret)
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dev_err_ratelimited(dev, "%s: multi reg write failed\n", __func__);
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kfree(val);
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mem_fail:
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kfree(reg);
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return ret;
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}
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static int regmap_swr_write(void *context, const void *data, size_t count)
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{
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struct device *dev = context;
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struct swr_device *swr = to_swr_device(dev);
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struct regmap *map = dev_get_regmap(dev, NULL);
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int addr_bytes = 0;
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if (map == NULL) {
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dev_err_ratelimited(dev, "%s: regmap is NULL\n", __func__);
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return -EINVAL;
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}
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if (swr == NULL) {
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dev_err_ratelimited(dev, "%s: swr is NULL\n", __func__);
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return -EINVAL;
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}
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addr_bytes = (swr->paging_support ? ADDR_BYTES_4 : ADDR_BYTES);
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WARN_ON(count < addr_bytes);
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if (count > (addr_bytes + VAL_BYTES + PAD_BYTES))
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return regmap_swr_raw_multi_reg_write(context, data, count);
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else
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return regmap_swr_gather_write(context, data, addr_bytes,
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(data + addr_bytes),
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(count - addr_bytes));
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}
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static int regmap_swr_read(void *context,
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const void *reg, size_t reg_size,
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void *val, size_t val_size)
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{
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struct device *dev = context;
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struct swr_device *swr = to_swr_device(dev);
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struct regmap *map = dev_get_regmap(dev, NULL);
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int ret = 0;
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u16 reg_addr = 0;
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if (map == NULL) {
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dev_err_ratelimited(dev, "%s: regmap is NULL\n", __func__);
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return -EINVAL;
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}
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if (swr == NULL) {
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dev_err_ratelimited(dev, "%s: swr is NULL\n", __func__);
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return -EINVAL;
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}
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if ((reg_size != ADDR_BYTES) && (reg_size != ADDR_BYTES_4)) {
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dev_err_ratelimited(dev, "%s: reg size %zd bytes not supported\n",
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__func__, reg_size);
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return -EINVAL;
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}
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mutex_lock(&swr_rw_lock);
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ret = regmap_swr_reg_address_get(swr, ®_addr, reg, reg_size);
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if (ret < 0) {
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dev_err_ratelimited(dev,
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"%s: regmap_swr_reg_address_get failed, reg: 0x%x\n",
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__func__, *(u32 *)reg);
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mutex_unlock(&swr_rw_lock);
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return ret;
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}
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ret = swr_read(swr, swr->dev_num, reg_addr, val, val_size);
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if (ret < 0)
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dev_err_ratelimited(dev, "%s: codec reg 0x%x read failed %d\n",
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__func__, reg_addr, ret);
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mutex_unlock(&swr_rw_lock);
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return ret;
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}
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static struct regmap_bus regmap_swr = {
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.write = regmap_swr_write,
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.gather_write = regmap_swr_gather_write,
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.read = regmap_swr_read,
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.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
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.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
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};
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struct regmap *__regmap_init_swr(struct swr_device *swr,
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const struct regmap_config *config,
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struct lock_class_key *lock_key,
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const char *lock_name)
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{
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return __regmap_init(&swr->dev, ®map_swr, &swr->dev, config,
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lock_key, lock_name);
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}
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EXPORT_SYMBOL(__regmap_init_swr);
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struct regmap *__devm_regmap_init_swr(struct swr_device *swr,
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const struct regmap_config *config,
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struct lock_class_key *lock_key,
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const char *lock_name)
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{
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return __devm_regmap_init(&swr->dev, ®map_swr, &swr->dev, config,
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lock_key, lock_name);
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}
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EXPORT_SYMBOL(__devm_regmap_init_swr);
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MODULE_LICENSE("GPL v2");
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