wcd938x.c 127 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. WCD_SUPPLIES_LPM_MODE,
  65. WCD_ADC1_MODE,
  66. WCD_ADC2_MODE,
  67. WCD_ADC3_MODE,
  68. WCD_ADC4_MODE,
  69. };
  70. enum {
  71. ADC_MODE_INVALID = 0,
  72. ADC_MODE_HIFI,
  73. ADC_MODE_LO_HIF,
  74. ADC_MODE_NORMAL,
  75. ADC_MODE_LP,
  76. ADC_MODE_ULP1,
  77. ADC_MODE_ULP2,
  78. };
  79. static u8 tx_mode_bit[] = {
  80. [ADC_MODE_INVALID] = 0x00,
  81. [ADC_MODE_HIFI] = 0x01,
  82. [ADC_MODE_LO_HIF] = 0x02,
  83. [ADC_MODE_NORMAL] = 0x04,
  84. [ADC_MODE_LP] = 0x08,
  85. [ADC_MODE_ULP1] = 0x10,
  86. [ADC_MODE_ULP2] = 0x20,
  87. };
  88. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  89. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  90. static int wcd938x_handle_post_irq(void *data);
  91. static int wcd938x_reset(struct device *dev);
  92. static int wcd938x_reset_low(struct device *dev);
  93. static int wcd938x_get_adc_mode(int val);
  94. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  95. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  115. };
  116. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  117. .name = "wcd938x",
  118. .irqs = wcd938x_irqs,
  119. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  120. .num_regs = 3,
  121. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  122. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  123. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  124. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  125. .use_ack = 1,
  126. .runtime_pm = false,
  127. .handle_post_irq = wcd938x_handle_post_irq,
  128. .irq_drv_data = NULL,
  129. };
  130. static int wcd938x_handle_post_irq(void *data)
  131. {
  132. struct wcd938x_priv *wcd938x = data;
  133. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  134. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  135. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  136. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  137. wcd938x->tx_swr_dev->slave_irq_pending =
  138. ((sts1 || sts2 || sts3) ? true : false);
  139. return IRQ_HANDLED;
  140. }
  141. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  142. {
  143. int ret = 0;
  144. int bank = 0;
  145. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  146. if (ret)
  147. return -EINVAL;
  148. return ((bank & 0x40) ? 1: 0);
  149. }
  150. static int wcd938x_get_clk_rate(int mode)
  151. {
  152. int rate;
  153. switch (mode) {
  154. case ADC_MODE_ULP2:
  155. rate = SWR_CLK_RATE_0P6MHZ;
  156. break;
  157. case ADC_MODE_ULP1:
  158. rate = SWR_CLK_RATE_1P2MHZ;
  159. break;
  160. case ADC_MODE_LP:
  161. rate = SWR_CLK_RATE_4P8MHZ;
  162. break;
  163. case ADC_MODE_NORMAL:
  164. case ADC_MODE_LO_HIF:
  165. case ADC_MODE_HIFI:
  166. case ADC_MODE_INVALID:
  167. default:
  168. rate = SWR_CLK_RATE_9P6MHZ;
  169. break;
  170. }
  171. return rate;
  172. }
  173. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  174. int rate, int bank)
  175. {
  176. u8 mask = (bank ? 0xF0 : 0x0F);
  177. u8 val = 0;
  178. switch (rate) {
  179. case SWR_CLK_RATE_0P6MHZ:
  180. val = (bank ? 0x60 : 0x06);
  181. break;
  182. case SWR_CLK_RATE_1P2MHZ:
  183. val = (bank ? 0x50 : 0x05);
  184. break;
  185. case SWR_CLK_RATE_2P4MHZ:
  186. val = (bank ? 0x30 : 0x03);
  187. break;
  188. case SWR_CLK_RATE_4P8MHZ:
  189. val = (bank ? 0x10 : 0x01);
  190. break;
  191. case SWR_CLK_RATE_9P6MHZ:
  192. default:
  193. val = 0x00;
  194. break;
  195. }
  196. snd_soc_component_update_bits(component,
  197. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  198. mask, val);
  199. return 0;
  200. }
  201. static int wcd938x_init_reg(struct snd_soc_component *component)
  202. {
  203. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  204. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  205. /* 1 msec delay as per HW requirement */
  206. usleep_range(1000, 1010);
  207. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  208. /* 1 msec delay as per HW requirement */
  209. usleep_range(1000, 1010);
  210. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  211. 0x10, 0x00);
  212. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  213. 0xF0, 0x80);
  214. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  215. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  216. /* 10 msec delay as per HW requirement */
  217. usleep_range(10000, 10010);
  218. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  219. snd_soc_component_update_bits(component,
  220. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  221. 0xF0, 0x00);
  222. snd_soc_component_update_bits(component,
  223. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  224. 0x1F, 0x15);
  225. snd_soc_component_update_bits(component,
  226. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  227. 0x1F, 0x15);
  228. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  229. 0xC0, 0x80);
  230. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  231. 0x02, 0x02);
  232. snd_soc_component_update_bits(component,
  233. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  234. 0xFF, 0x14);
  235. snd_soc_component_update_bits(component,
  236. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  237. 0x1F, 0x08);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  252. snd_soc_component_update_bits(component,
  253. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  254. snd_soc_component_update_bits(component,
  255. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  256. snd_soc_component_update_bits(component,
  257. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  258. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  259. ((snd_soc_component_read32(component,
  260. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  261. snd_soc_component_update_bits(component,
  262. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  263. return 0;
  264. }
  265. static int wcd938x_set_port_params(struct snd_soc_component *component,
  266. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  267. u8 *ch_mask, u32 *ch_rate,
  268. u8 *port_type, u8 path)
  269. {
  270. int i, j;
  271. u8 num_ports = 0;
  272. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  273. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  274. switch (path) {
  275. case CODEC_RX:
  276. map = &wcd938x->rx_port_mapping;
  277. num_ports = wcd938x->num_rx_ports;
  278. break;
  279. case CODEC_TX:
  280. map = &wcd938x->tx_port_mapping;
  281. num_ports = wcd938x->num_tx_ports;
  282. break;
  283. default:
  284. dev_err(component->dev, "%s Invalid path selected %u\n",
  285. __func__, path);
  286. return -EINVAL;
  287. }
  288. for (i = 0; i <= num_ports; i++) {
  289. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  290. if ((*map)[i][j].slave_port_type == slv_prt_type)
  291. goto found;
  292. }
  293. }
  294. found:
  295. if (i > num_ports || j == MAX_CH_PER_PORT) {
  296. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  297. __func__, slv_prt_type);
  298. return -EINVAL;
  299. }
  300. *port_id = i;
  301. *num_ch = (*map)[i][j].num_ch;
  302. *ch_mask = (*map)[i][j].ch_mask;
  303. *ch_rate = (*map)[i][j].ch_rate;
  304. *port_type = (*map)[i][j].master_port_type;
  305. return 0;
  306. }
  307. static int wcd938x_parse_port_mapping(struct device *dev,
  308. char *prop, u8 path)
  309. {
  310. u32 *dt_array, map_size, map_length;
  311. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  312. u32 slave_port_type, master_port_type;
  313. u32 i, ch_iter = 0;
  314. int ret = 0;
  315. u8 *num_ports = NULL;
  316. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  317. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  318. switch (path) {
  319. case CODEC_RX:
  320. map = &wcd938x->rx_port_mapping;
  321. num_ports = &wcd938x->num_rx_ports;
  322. break;
  323. case CODEC_TX:
  324. map = &wcd938x->tx_port_mapping;
  325. num_ports = &wcd938x->num_tx_ports;
  326. break;
  327. default:
  328. dev_err(dev, "%s Invalid path selected %u\n",
  329. __func__, path);
  330. return -EINVAL;
  331. }
  332. if (!of_find_property(dev->of_node, prop,
  333. &map_size)) {
  334. dev_err(dev, "missing port mapping prop %s\n", prop);
  335. ret = -EINVAL;
  336. goto err_port_map;
  337. }
  338. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  339. dt_array = kzalloc(map_size, GFP_KERNEL);
  340. if (!dt_array) {
  341. ret = -ENOMEM;
  342. goto err_alloc;
  343. }
  344. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  345. NUM_SWRS_DT_PARAMS * map_length);
  346. if (ret) {
  347. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  348. __func__, prop);
  349. goto err_pdata_fail;
  350. }
  351. for (i = 0; i < map_length; i++) {
  352. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  353. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  354. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  355. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  356. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  357. if (port_num != old_port_num)
  358. ch_iter = 0;
  359. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  360. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  361. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  362. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  363. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  364. old_port_num = port_num;
  365. }
  366. *num_ports = port_num;
  367. kfree(dt_array);
  368. return 0;
  369. err_pdata_fail:
  370. kfree(dt_array);
  371. err_alloc:
  372. err_port_map:
  373. return ret;
  374. }
  375. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  376. u8 slv_port_type, int clk_rate,
  377. u8 enable)
  378. {
  379. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  380. u8 port_id, num_ch, ch_mask;
  381. u8 ch_type = 0;
  382. u32 ch_rate;
  383. int slave_ch_idx;
  384. u8 num_port = 1;
  385. int ret = 0;
  386. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  387. &num_ch, &ch_mask, &ch_rate,
  388. &ch_type, CODEC_TX);
  389. if (ret)
  390. return ret;
  391. if (clk_rate)
  392. ch_rate = clk_rate;
  393. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  394. if (slave_ch_idx != -EINVAL)
  395. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  396. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  397. __func__, slave_ch_idx, ch_type);
  398. if (enable)
  399. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  400. num_port, &ch_mask, &ch_rate,
  401. &num_ch, &ch_type);
  402. else
  403. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  404. num_port, &ch_mask, &ch_type);
  405. return ret;
  406. }
  407. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  408. u8 slv_port_type, u8 enable)
  409. {
  410. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  411. u8 port_id, num_ch, ch_mask, port_type;
  412. u32 ch_rate;
  413. u8 num_port = 1;
  414. int ret = 0;
  415. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  416. &num_ch, &ch_mask, &ch_rate,
  417. &port_type, CODEC_RX);
  418. if (ret)
  419. return ret;
  420. if (enable)
  421. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  422. num_port, &ch_mask, &ch_rate,
  423. &num_ch, &port_type);
  424. else
  425. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  426. num_port, &ch_mask, &port_type);
  427. return ret;
  428. }
  429. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  430. {
  431. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  432. if (wcd938x->rx_clk_cnt == 0) {
  433. snd_soc_component_update_bits(component,
  434. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  441. snd_soc_component_update_bits(component,
  442. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  443. snd_soc_component_update_bits(component,
  444. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  445. snd_soc_component_update_bits(component,
  446. WCD938X_AUX_AUXPA, 0x10, 0x10);
  447. }
  448. wcd938x->rx_clk_cnt++;
  449. return 0;
  450. }
  451. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  452. {
  453. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  454. wcd938x->rx_clk_cnt--;
  455. if (wcd938x->rx_clk_cnt == 0) {
  456. snd_soc_component_update_bits(component,
  457. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  458. snd_soc_component_update_bits(component,
  459. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  460. snd_soc_component_update_bits(component,
  461. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  462. snd_soc_component_update_bits(component,
  463. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  464. snd_soc_component_update_bits(component,
  465. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  466. }
  467. return 0;
  468. }
  469. /*
  470. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  471. * @component: handle to snd_soc_component *
  472. *
  473. * return wcd938x_mbhc handle or error code in case of failure
  474. */
  475. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  476. {
  477. struct wcd938x_priv *wcd938x;
  478. if (!component) {
  479. pr_err("%s: Invalid params, NULL component\n", __func__);
  480. return NULL;
  481. }
  482. wcd938x = snd_soc_component_get_drvdata(component);
  483. if (!wcd938x) {
  484. pr_err("%s: wcd938x is NULL\n", __func__);
  485. return NULL;
  486. }
  487. return wcd938x->mbhc;
  488. }
  489. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  490. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  491. struct snd_kcontrol *kcontrol,
  492. int event)
  493. {
  494. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  495. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  496. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  497. w->name, event);
  498. switch (event) {
  499. case SND_SOC_DAPM_PRE_PMU:
  500. wcd938x_rx_clk_enable(component);
  501. snd_soc_component_update_bits(component,
  502. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  503. snd_soc_component_update_bits(component,
  504. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  505. snd_soc_component_update_bits(component,
  506. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  507. break;
  508. case SND_SOC_DAPM_POST_PMU:
  509. snd_soc_component_update_bits(component,
  510. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  511. if (wcd938x->comp1_enable) {
  512. snd_soc_component_update_bits(component,
  513. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  514. /* 5msec compander delay as per HW requirement */
  515. if (!wcd938x->comp2_enable ||
  516. (snd_soc_component_read32(component,
  517. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  518. usleep_range(5000, 5010);
  519. snd_soc_component_update_bits(component,
  520. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  521. } else {
  522. snd_soc_component_update_bits(component,
  523. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  524. 0x02, 0x00);
  525. snd_soc_component_update_bits(component,
  526. WCD938X_HPH_L_EN, 0x20, 0x20);
  527. }
  528. break;
  529. case SND_SOC_DAPM_POST_PMD:
  530. snd_soc_component_update_bits(component,
  531. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  532. 0x0F, 0x01);
  533. break;
  534. }
  535. return 0;
  536. }
  537. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  538. struct snd_kcontrol *kcontrol,
  539. int event)
  540. {
  541. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  542. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  543. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  544. w->name, event);
  545. switch (event) {
  546. case SND_SOC_DAPM_PRE_PMU:
  547. wcd938x_rx_clk_enable(component);
  548. snd_soc_component_update_bits(component,
  549. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  550. snd_soc_component_update_bits(component,
  551. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  552. snd_soc_component_update_bits(component,
  553. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  554. break;
  555. case SND_SOC_DAPM_POST_PMU:
  556. snd_soc_component_update_bits(component,
  557. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  558. if (wcd938x->comp2_enable) {
  559. snd_soc_component_update_bits(component,
  560. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  561. /* 5msec compander delay as per HW requirement */
  562. if (!wcd938x->comp1_enable ||
  563. (snd_soc_component_read32(component,
  564. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  565. usleep_range(5000, 5010);
  566. snd_soc_component_update_bits(component,
  567. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  568. } else {
  569. snd_soc_component_update_bits(component,
  570. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  571. 0x01, 0x00);
  572. snd_soc_component_update_bits(component,
  573. WCD938X_HPH_R_EN, 0x20, 0x20);
  574. }
  575. break;
  576. case SND_SOC_DAPM_POST_PMD:
  577. snd_soc_component_update_bits(component,
  578. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  579. 0x0F, 0x01);
  580. break;
  581. }
  582. return 0;
  583. }
  584. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  585. struct snd_kcontrol *kcontrol,
  586. int event)
  587. {
  588. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  589. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  590. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  591. w->name, event);
  592. switch (event) {
  593. case SND_SOC_DAPM_PRE_PMU:
  594. wcd938x_rx_clk_enable(component);
  595. wcd938x->ear_rx_path =
  596. snd_soc_component_read32(
  597. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  598. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  599. snd_soc_component_update_bits(component,
  600. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  601. snd_soc_component_update_bits(component,
  602. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  603. snd_soc_component_update_bits(component,
  604. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  605. snd_soc_component_update_bits(component,
  606. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  607. } else {
  608. snd_soc_component_update_bits(component,
  609. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  610. snd_soc_component_update_bits(component,
  611. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  612. if (wcd938x->comp1_enable)
  613. snd_soc_component_update_bits(component,
  614. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  615. 0x02, 0x02);
  616. }
  617. /* 5 msec delay as per HW requirement */
  618. usleep_range(5000, 5010);
  619. if (wcd938x->flyback_cur_det_disable == 0)
  620. snd_soc_component_update_bits(component,
  621. WCD938X_FLYBACK_EN,
  622. 0x04, 0x00);
  623. wcd938x->flyback_cur_det_disable++;
  624. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  625. WCD_CLSH_EVENT_PRE_DAC,
  626. WCD_CLSH_STATE_EAR,
  627. wcd938x->hph_mode);
  628. break;
  629. case SND_SOC_DAPM_POST_PMD:
  630. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  631. snd_soc_component_update_bits(component,
  632. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  633. snd_soc_component_update_bits(component,
  634. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  635. } else {
  636. snd_soc_component_update_bits(component,
  637. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  638. snd_soc_component_update_bits(component,
  639. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  640. if (wcd938x->comp1_enable)
  641. snd_soc_component_update_bits(component,
  642. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  643. 0x02, 0x00);
  644. }
  645. snd_soc_component_update_bits(component,
  646. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  647. snd_soc_component_update_bits(component,
  648. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  649. break;
  650. };
  651. return 0;
  652. }
  653. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  654. struct snd_kcontrol *kcontrol,
  655. int event)
  656. {
  657. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  658. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  659. int ret = 0;
  660. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  661. w->name, event);
  662. switch (event) {
  663. case SND_SOC_DAPM_PRE_PMU:
  664. wcd938x_rx_clk_enable(component);
  665. snd_soc_component_update_bits(component,
  666. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  667. snd_soc_component_update_bits(component,
  668. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  669. snd_soc_component_update_bits(component,
  670. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  671. if (wcd938x->flyback_cur_det_disable == 0)
  672. snd_soc_component_update_bits(component,
  673. WCD938X_FLYBACK_EN,
  674. 0x04, 0x00);
  675. wcd938x->flyback_cur_det_disable++;
  676. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  677. WCD_CLSH_EVENT_PRE_DAC,
  678. WCD_CLSH_STATE_AUX,
  679. wcd938x->hph_mode);
  680. break;
  681. case SND_SOC_DAPM_POST_PMD:
  682. snd_soc_component_update_bits(component,
  683. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  684. break;
  685. };
  686. return ret;
  687. }
  688. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  689. struct snd_kcontrol *kcontrol,
  690. int event)
  691. {
  692. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  693. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  694. int ret = 0;
  695. int hph_mode = wcd938x->hph_mode;
  696. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  697. w->name, event);
  698. switch (event) {
  699. case SND_SOC_DAPM_PRE_PMU:
  700. if (wcd938x->ldoh)
  701. snd_soc_component_update_bits(component,
  702. WCD938X_LDOH_MODE,
  703. 0x80, 0x80);
  704. if (wcd938x->update_wcd_event)
  705. wcd938x->update_wcd_event(wcd938x->handle,
  706. WCD_BOLERO_EVT_RX_MUTE,
  707. (WCD_RX2 << 0x10 | 0x1));
  708. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  709. wcd938x->rx_swr_dev->dev_num,
  710. true);
  711. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  712. WCD_CLSH_EVENT_PRE_DAC,
  713. WCD_CLSH_STATE_HPHR,
  714. hph_mode);
  715. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  716. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  717. hph_mode == CLS_H_ULP) {
  718. snd_soc_component_update_bits(component,
  719. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  720. }
  721. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  722. 0x10, 0x10);
  723. wcd_clsh_set_hph_mode(component, hph_mode);
  724. /* 100 usec delay as per HW requirement */
  725. usleep_range(100, 110);
  726. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  727. snd_soc_component_update_bits(component,
  728. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  729. break;
  730. case SND_SOC_DAPM_POST_PMU:
  731. /*
  732. * 7ms sleep is required if compander is enabled as per
  733. * HW requirement. If compander is disabled, then
  734. * 20ms delay is required.
  735. */
  736. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  737. if (!wcd938x->comp2_enable)
  738. usleep_range(20000, 20100);
  739. else
  740. usleep_range(7000, 7100);
  741. if (hph_mode == CLS_H_LP ||
  742. hph_mode == CLS_H_LOHIFI ||
  743. hph_mode == CLS_H_ULP)
  744. snd_soc_component_update_bits(component,
  745. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  746. 0x00);
  747. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  748. }
  749. snd_soc_component_update_bits(component,
  750. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  751. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  752. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  753. snd_soc_component_update_bits(component,
  754. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  755. if (wcd938x->update_wcd_event)
  756. wcd938x->update_wcd_event(wcd938x->handle,
  757. WCD_BOLERO_EVT_RX_MUTE,
  758. (WCD_RX2 << 0x10));
  759. wcd_enable_irq(&wcd938x->irq_info,
  760. WCD938X_IRQ_HPHR_PDM_WD_INT);
  761. break;
  762. case SND_SOC_DAPM_PRE_PMD:
  763. if (wcd938x->update_wcd_event)
  764. wcd938x->update_wcd_event(wcd938x->handle,
  765. WCD_BOLERO_EVT_RX_MUTE,
  766. (WCD_RX2 << 0x10 | 0x1));
  767. wcd_disable_irq(&wcd938x->irq_info,
  768. WCD938X_IRQ_HPHR_PDM_WD_INT);
  769. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  770. wcd938x->update_wcd_event(wcd938x->handle,
  771. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  772. (WCD_RX2 << 0x10));
  773. /*
  774. * 7ms sleep is required if compander is enabled as per
  775. * HW requirement. If compander is disabled, then
  776. * 20ms delay is required.
  777. */
  778. if (!wcd938x->comp2_enable)
  779. usleep_range(20000, 20100);
  780. else
  781. usleep_range(7000, 7100);
  782. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  783. 0x40, 0x00);
  784. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  785. WCD_EVENT_PRE_HPHR_PA_OFF,
  786. &wcd938x->mbhc->wcd_mbhc);
  787. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  788. break;
  789. case SND_SOC_DAPM_POST_PMD:
  790. /*
  791. * 7ms sleep is required if compander is enabled as per
  792. * HW requirement. If compander is disabled, then
  793. * 20ms delay is required.
  794. */
  795. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  796. if (!wcd938x->comp2_enable)
  797. usleep_range(20000, 20100);
  798. else
  799. usleep_range(7000, 7100);
  800. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  801. }
  802. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  803. WCD_EVENT_POST_HPHR_PA_OFF,
  804. &wcd938x->mbhc->wcd_mbhc);
  805. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  806. 0x10, 0x00);
  807. snd_soc_component_update_bits(component,
  808. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  809. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  810. WCD_CLSH_EVENT_POST_PA,
  811. WCD_CLSH_STATE_HPHR,
  812. hph_mode);
  813. if (wcd938x->ldoh)
  814. snd_soc_component_update_bits(component,
  815. WCD938X_LDOH_MODE,
  816. 0x80, 0x00);
  817. break;
  818. };
  819. return ret;
  820. }
  821. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  822. struct snd_kcontrol *kcontrol,
  823. int event)
  824. {
  825. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  826. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  827. int ret = 0;
  828. int hph_mode = wcd938x->hph_mode;
  829. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  830. w->name, event);
  831. switch (event) {
  832. case SND_SOC_DAPM_PRE_PMU:
  833. if (wcd938x->ldoh)
  834. snd_soc_component_update_bits(component,
  835. WCD938X_LDOH_MODE,
  836. 0x80, 0x80);
  837. if (wcd938x->update_wcd_event)
  838. wcd938x->update_wcd_event(wcd938x->handle,
  839. WCD_BOLERO_EVT_RX_MUTE,
  840. (WCD_RX1 << 0x10 | 0x01));
  841. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  842. wcd938x->rx_swr_dev->dev_num,
  843. true);
  844. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  845. WCD_CLSH_EVENT_PRE_DAC,
  846. WCD_CLSH_STATE_HPHL,
  847. hph_mode);
  848. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  849. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  850. hph_mode == CLS_H_ULP) {
  851. snd_soc_component_update_bits(component,
  852. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  853. }
  854. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  855. 0x20, 0x20);
  856. wcd_clsh_set_hph_mode(component, hph_mode);
  857. /* 100 usec delay as per HW requirement */
  858. usleep_range(100, 110);
  859. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  860. snd_soc_component_update_bits(component,
  861. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  862. break;
  863. case SND_SOC_DAPM_POST_PMU:
  864. /*
  865. * 7ms sleep is required if compander is enabled as per
  866. * HW requirement. If compander is disabled, then
  867. * 20ms delay is required.
  868. */
  869. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  870. if (!wcd938x->comp1_enable)
  871. usleep_range(20000, 20100);
  872. else
  873. usleep_range(7000, 7100);
  874. if (hph_mode == CLS_H_LP ||
  875. hph_mode == CLS_H_LOHIFI ||
  876. hph_mode == CLS_H_ULP)
  877. snd_soc_component_update_bits(component,
  878. WCD938X_HPH_REFBUFF_LP_CTL,
  879. 0x01, 0x00);
  880. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  881. }
  882. snd_soc_component_update_bits(component,
  883. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  884. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  885. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  886. snd_soc_component_update_bits(component,
  887. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  888. if (wcd938x->update_wcd_event)
  889. wcd938x->update_wcd_event(wcd938x->handle,
  890. WCD_BOLERO_EVT_RX_MUTE,
  891. (WCD_RX1 << 0x10));
  892. wcd_enable_irq(&wcd938x->irq_info,
  893. WCD938X_IRQ_HPHL_PDM_WD_INT);
  894. break;
  895. case SND_SOC_DAPM_PRE_PMD:
  896. if (wcd938x->update_wcd_event)
  897. wcd938x->update_wcd_event(wcd938x->handle,
  898. WCD_BOLERO_EVT_RX_MUTE,
  899. (WCD_RX1 << 0x10 | 0x1));
  900. wcd_disable_irq(&wcd938x->irq_info,
  901. WCD938X_IRQ_HPHL_PDM_WD_INT);
  902. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  903. wcd938x->update_wcd_event(wcd938x->handle,
  904. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  905. (WCD_RX1 << 0x10));
  906. /*
  907. * 7ms sleep is required if compander is enabled as per
  908. * HW requirement. If compander is disabled, then
  909. * 20ms delay is required.
  910. */
  911. if (!wcd938x->comp1_enable)
  912. usleep_range(20000, 20100);
  913. else
  914. usleep_range(7000, 7100);
  915. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  916. 0x80, 0x00);
  917. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  918. WCD_EVENT_PRE_HPHL_PA_OFF,
  919. &wcd938x->mbhc->wcd_mbhc);
  920. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  921. break;
  922. case SND_SOC_DAPM_POST_PMD:
  923. /*
  924. * 7ms sleep is required if compander is enabled as per
  925. * HW requirement. If compander is disabled, then
  926. * 20ms delay is required.
  927. */
  928. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  929. if (!wcd938x->comp1_enable)
  930. usleep_range(21000, 21100);
  931. else
  932. usleep_range(7000, 7100);
  933. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  934. }
  935. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  936. WCD_EVENT_POST_HPHL_PA_OFF,
  937. &wcd938x->mbhc->wcd_mbhc);
  938. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  939. 0x20, 0x00);
  940. snd_soc_component_update_bits(component,
  941. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  942. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  943. WCD_CLSH_EVENT_POST_PA,
  944. WCD_CLSH_STATE_HPHL,
  945. hph_mode);
  946. if (wcd938x->ldoh)
  947. snd_soc_component_update_bits(component,
  948. WCD938X_LDOH_MODE,
  949. 0x80, 0x00);
  950. break;
  951. };
  952. return ret;
  953. }
  954. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  955. struct snd_kcontrol *kcontrol,
  956. int event)
  957. {
  958. struct snd_soc_component *component =
  959. snd_soc_dapm_to_component(w->dapm);
  960. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  961. int hph_mode = wcd938x->hph_mode;
  962. int ret = 0;
  963. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  964. w->name, event);
  965. switch (event) {
  966. case SND_SOC_DAPM_PRE_PMU:
  967. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  968. wcd938x->rx_swr_dev->dev_num,
  969. true);
  970. snd_soc_component_update_bits(component,
  971. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  972. break;
  973. case SND_SOC_DAPM_POST_PMU:
  974. /* 1 msec delay as per HW requirement */
  975. usleep_range(1000, 1010);
  976. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  977. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  978. snd_soc_component_update_bits(component,
  979. WCD938X_ANA_RX_SUPPLIES,
  980. 0x02, 0x02);
  981. if (wcd938x->update_wcd_event)
  982. wcd938x->update_wcd_event(wcd938x->handle,
  983. WCD_BOLERO_EVT_RX_MUTE,
  984. (WCD_RX3 << 0x10));
  985. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  986. break;
  987. case SND_SOC_DAPM_PRE_PMD:
  988. wcd_disable_irq(&wcd938x->irq_info,
  989. WCD938X_IRQ_AUX_PDM_WD_INT);
  990. if (wcd938x->update_wcd_event)
  991. wcd938x->update_wcd_event(wcd938x->handle,
  992. WCD_BOLERO_EVT_RX_MUTE,
  993. (WCD_RX3 << 0x10 | 0x1));
  994. break;
  995. case SND_SOC_DAPM_POST_PMD:
  996. /* 1 msec delay as per HW requirement */
  997. usleep_range(1000, 1010);
  998. snd_soc_component_update_bits(component,
  999. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1000. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1001. WCD_CLSH_EVENT_POST_PA,
  1002. WCD_CLSH_STATE_AUX,
  1003. hph_mode);
  1004. wcd938x->flyback_cur_det_disable--;
  1005. if (wcd938x->flyback_cur_det_disable == 0)
  1006. snd_soc_component_update_bits(component,
  1007. WCD938X_FLYBACK_EN,
  1008. 0x04, 0x04);
  1009. break;
  1010. };
  1011. return ret;
  1012. }
  1013. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1014. struct snd_kcontrol *kcontrol,
  1015. int event)
  1016. {
  1017. struct snd_soc_component *component =
  1018. snd_soc_dapm_to_component(w->dapm);
  1019. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1020. int hph_mode = wcd938x->hph_mode;
  1021. int ret = 0;
  1022. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1023. w->name, event);
  1024. switch (event) {
  1025. case SND_SOC_DAPM_PRE_PMU:
  1026. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1027. wcd938x->rx_swr_dev->dev_num,
  1028. true);
  1029. /*
  1030. * Enable watchdog interrupt for HPHL or AUX
  1031. * depending on mux value
  1032. */
  1033. wcd938x->ear_rx_path =
  1034. snd_soc_component_read32(
  1035. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1036. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1037. snd_soc_component_update_bits(component,
  1038. WCD938X_DIGITAL_PDM_WD_CTL2,
  1039. 0x01, 0x01);
  1040. else
  1041. snd_soc_component_update_bits(component,
  1042. WCD938X_DIGITAL_PDM_WD_CTL0,
  1043. 0x07, 0x03);
  1044. if (!wcd938x->comp1_enable)
  1045. snd_soc_component_update_bits(component,
  1046. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1047. break;
  1048. case SND_SOC_DAPM_POST_PMU:
  1049. /* 6 msec delay as per HW requirement */
  1050. usleep_range(6000, 6010);
  1051. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1052. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1053. snd_soc_component_update_bits(component,
  1054. WCD938X_ANA_RX_SUPPLIES,
  1055. 0x02, 0x02);
  1056. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1057. if (wcd938x->update_wcd_event)
  1058. wcd938x->update_wcd_event(wcd938x->handle,
  1059. WCD_BOLERO_EVT_RX_MUTE,
  1060. (WCD_RX3 << 0x10));
  1061. wcd_enable_irq(&wcd938x->irq_info,
  1062. WCD938X_IRQ_AUX_PDM_WD_INT);
  1063. } else {
  1064. if (wcd938x->update_wcd_event)
  1065. wcd938x->update_wcd_event(wcd938x->handle,
  1066. WCD_BOLERO_EVT_RX_MUTE,
  1067. (WCD_RX1 << 0x10));
  1068. wcd_enable_irq(&wcd938x->irq_info,
  1069. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1070. }
  1071. break;
  1072. case SND_SOC_DAPM_PRE_PMD:
  1073. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1074. wcd_disable_irq(&wcd938x->irq_info,
  1075. WCD938X_IRQ_AUX_PDM_WD_INT);
  1076. if (wcd938x->update_wcd_event)
  1077. wcd938x->update_wcd_event(wcd938x->handle,
  1078. WCD_BOLERO_EVT_RX_MUTE,
  1079. (WCD_RX3 << 0x10 | 0x1));
  1080. } else {
  1081. wcd_disable_irq(&wcd938x->irq_info,
  1082. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1083. if (wcd938x->update_wcd_event)
  1084. wcd938x->update_wcd_event(wcd938x->handle,
  1085. WCD_BOLERO_EVT_RX_MUTE,
  1086. (WCD_RX1 << 0x10 | 0x1));
  1087. }
  1088. break;
  1089. case SND_SOC_DAPM_POST_PMD:
  1090. if (!wcd938x->comp1_enable)
  1091. snd_soc_component_update_bits(component,
  1092. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1093. /* 7 msec delay as per HW requirement */
  1094. usleep_range(7000, 7010);
  1095. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1096. snd_soc_component_update_bits(component,
  1097. WCD938X_DIGITAL_PDM_WD_CTL2,
  1098. 0x01, 0x00);
  1099. else
  1100. snd_soc_component_update_bits(component,
  1101. WCD938X_DIGITAL_PDM_WD_CTL0,
  1102. 0x07, 0x00);
  1103. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1104. WCD_CLSH_EVENT_POST_PA,
  1105. WCD_CLSH_STATE_EAR,
  1106. hph_mode);
  1107. wcd938x->flyback_cur_det_disable--;
  1108. if (wcd938x->flyback_cur_det_disable == 0)
  1109. snd_soc_component_update_bits(component,
  1110. WCD938X_FLYBACK_EN,
  1111. 0x04, 0x04);
  1112. break;
  1113. };
  1114. return ret;
  1115. }
  1116. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1117. struct snd_kcontrol *kcontrol,
  1118. int event)
  1119. {
  1120. struct snd_soc_component *component =
  1121. snd_soc_dapm_to_component(w->dapm);
  1122. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1123. int mode = wcd938x->hph_mode;
  1124. int ret = 0;
  1125. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1126. w->name, event);
  1127. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1128. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1129. wcd938x_rx_connect_port(component, CLSH,
  1130. SND_SOC_DAPM_EVENT_ON(event));
  1131. }
  1132. if (SND_SOC_DAPM_EVENT_OFF(event))
  1133. ret = swr_slvdev_datapath_control(
  1134. wcd938x->rx_swr_dev,
  1135. wcd938x->rx_swr_dev->dev_num,
  1136. false);
  1137. return ret;
  1138. }
  1139. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1140. struct snd_kcontrol *kcontrol,
  1141. int event)
  1142. {
  1143. struct snd_soc_component *component =
  1144. snd_soc_dapm_to_component(w->dapm);
  1145. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1146. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1147. w->name, event);
  1148. switch (event) {
  1149. case SND_SOC_DAPM_PRE_PMU:
  1150. wcd938x_rx_connect_port(component, HPH_L, true);
  1151. if (wcd938x->comp1_enable)
  1152. wcd938x_rx_connect_port(component, COMP_L, true);
  1153. break;
  1154. case SND_SOC_DAPM_POST_PMD:
  1155. wcd938x_rx_connect_port(component, HPH_L, false);
  1156. if (wcd938x->comp1_enable)
  1157. wcd938x_rx_connect_port(component, COMP_L, false);
  1158. wcd938x_rx_clk_disable(component);
  1159. snd_soc_component_update_bits(component,
  1160. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1161. 0x01, 0x00);
  1162. break;
  1163. };
  1164. return 0;
  1165. }
  1166. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1167. struct snd_kcontrol *kcontrol, int event)
  1168. {
  1169. struct snd_soc_component *component =
  1170. snd_soc_dapm_to_component(w->dapm);
  1171. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1172. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1173. w->name, event);
  1174. switch (event) {
  1175. case SND_SOC_DAPM_PRE_PMU:
  1176. wcd938x_rx_connect_port(component, HPH_R, true);
  1177. if (wcd938x->comp2_enable)
  1178. wcd938x_rx_connect_port(component, COMP_R, true);
  1179. break;
  1180. case SND_SOC_DAPM_POST_PMD:
  1181. wcd938x_rx_connect_port(component, HPH_R, false);
  1182. if (wcd938x->comp2_enable)
  1183. wcd938x_rx_connect_port(component, COMP_R, false);
  1184. wcd938x_rx_clk_disable(component);
  1185. snd_soc_component_update_bits(component,
  1186. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1187. 0x02, 0x00);
  1188. break;
  1189. };
  1190. return 0;
  1191. }
  1192. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1193. struct snd_kcontrol *kcontrol,
  1194. int event)
  1195. {
  1196. struct snd_soc_component *component =
  1197. snd_soc_dapm_to_component(w->dapm);
  1198. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1199. w->name, event);
  1200. switch (event) {
  1201. case SND_SOC_DAPM_PRE_PMU:
  1202. wcd938x_rx_connect_port(component, LO, true);
  1203. break;
  1204. case SND_SOC_DAPM_POST_PMD:
  1205. wcd938x_rx_connect_port(component, LO, false);
  1206. /* 6 msec delay as per HW requirement */
  1207. usleep_range(6000, 6010);
  1208. wcd938x_rx_clk_disable(component);
  1209. snd_soc_component_update_bits(component,
  1210. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1211. break;
  1212. }
  1213. return 0;
  1214. }
  1215. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1216. struct snd_kcontrol *kcontrol,
  1217. int event)
  1218. {
  1219. struct snd_soc_component *component =
  1220. snd_soc_dapm_to_component(w->dapm);
  1221. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1222. u16 dmic_clk_reg, dmic_clk_en_reg;
  1223. s32 *dmic_clk_cnt;
  1224. u8 dmic_ctl_shift = 0;
  1225. u8 dmic_clk_shift = 0;
  1226. u8 dmic_clk_mask = 0;
  1227. u16 dmic2_left_en = 0;
  1228. int ret = 0;
  1229. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1230. w->name, event);
  1231. switch (w->shift) {
  1232. case 0:
  1233. case 1:
  1234. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1235. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1236. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1237. dmic_clk_mask = 0x0F;
  1238. dmic_clk_shift = 0x00;
  1239. dmic_ctl_shift = 0x00;
  1240. break;
  1241. case 2:
  1242. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1243. case 3:
  1244. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1245. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1246. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1247. dmic_clk_mask = 0xF0;
  1248. dmic_clk_shift = 0x04;
  1249. dmic_ctl_shift = 0x01;
  1250. break;
  1251. case 4:
  1252. case 5:
  1253. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1254. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1255. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1256. dmic_clk_mask = 0x0F;
  1257. dmic_clk_shift = 0x00;
  1258. dmic_ctl_shift = 0x02;
  1259. break;
  1260. case 6:
  1261. case 7:
  1262. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1263. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1264. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1265. dmic_clk_mask = 0xF0;
  1266. dmic_clk_shift = 0x04;
  1267. dmic_ctl_shift = 0x03;
  1268. break;
  1269. default:
  1270. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1271. __func__);
  1272. return -EINVAL;
  1273. };
  1274. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1275. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1276. switch (event) {
  1277. case SND_SOC_DAPM_PRE_PMU:
  1278. snd_soc_component_update_bits(component,
  1279. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1280. (0x01 << dmic_ctl_shift), 0x00);
  1281. /* 250us sleep as per HW requirement */
  1282. usleep_range(250, 260);
  1283. if (dmic2_left_en)
  1284. snd_soc_component_update_bits(component,
  1285. dmic2_left_en, 0x80, 0x80);
  1286. /* Setting DMIC clock rate to 2.4MHz */
  1287. snd_soc_component_update_bits(component,
  1288. dmic_clk_reg, dmic_clk_mask,
  1289. (0x03 << dmic_clk_shift));
  1290. snd_soc_component_update_bits(component,
  1291. dmic_clk_en_reg, 0x08, 0x08);
  1292. /* enable clock scaling */
  1293. snd_soc_component_update_bits(component,
  1294. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1295. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1296. wcd938x->tx_swr_dev->dev_num,
  1297. true);
  1298. break;
  1299. case SND_SOC_DAPM_POST_PMD:
  1300. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1301. false);
  1302. snd_soc_component_update_bits(component,
  1303. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1304. (0x01 << dmic_ctl_shift),
  1305. (0x01 << dmic_ctl_shift));
  1306. if (dmic2_left_en)
  1307. snd_soc_component_update_bits(component,
  1308. dmic2_left_en, 0x80, 0x00);
  1309. snd_soc_component_update_bits(component,
  1310. dmic_clk_en_reg, 0x08, 0x00);
  1311. break;
  1312. };
  1313. return ret;
  1314. }
  1315. /*
  1316. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1317. * @micb_mv: micbias in mv
  1318. *
  1319. * return register value converted
  1320. */
  1321. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1322. {
  1323. /* min micbias voltage is 1V and maximum is 2.85V */
  1324. if (micb_mv < 1000 || micb_mv > 2850) {
  1325. pr_err("%s: unsupported micbias voltage\n", __func__);
  1326. return -EINVAL;
  1327. }
  1328. return (micb_mv - 1000) / 50;
  1329. }
  1330. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1331. /*
  1332. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1333. * @component: handle to snd_soc_component *
  1334. * @req_volt: micbias voltage to be set
  1335. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1336. *
  1337. * return 0 if adjustment is success or error code in case of failure
  1338. */
  1339. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1340. int req_volt, int micb_num)
  1341. {
  1342. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1343. int cur_vout_ctl, req_vout_ctl;
  1344. int micb_reg, micb_val, micb_en;
  1345. int ret = 0;
  1346. switch (micb_num) {
  1347. case MIC_BIAS_1:
  1348. micb_reg = WCD938X_ANA_MICB1;
  1349. break;
  1350. case MIC_BIAS_2:
  1351. micb_reg = WCD938X_ANA_MICB2;
  1352. break;
  1353. case MIC_BIAS_3:
  1354. micb_reg = WCD938X_ANA_MICB3;
  1355. break;
  1356. case MIC_BIAS_4:
  1357. micb_reg = WCD938X_ANA_MICB4;
  1358. break;
  1359. default:
  1360. return -EINVAL;
  1361. }
  1362. mutex_lock(&wcd938x->micb_lock);
  1363. /*
  1364. * If requested micbias voltage is same as current micbias
  1365. * voltage, then just return. Otherwise, adjust voltage as
  1366. * per requested value. If micbias is already enabled, then
  1367. * to avoid slow micbias ramp-up or down enable pull-up
  1368. * momentarily, change the micbias value and then re-enable
  1369. * micbias.
  1370. */
  1371. micb_val = snd_soc_component_read32(component, micb_reg);
  1372. micb_en = (micb_val & 0xC0) >> 6;
  1373. cur_vout_ctl = micb_val & 0x3F;
  1374. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1375. if (req_vout_ctl < 0) {
  1376. ret = -EINVAL;
  1377. goto exit;
  1378. }
  1379. if (cur_vout_ctl == req_vout_ctl) {
  1380. ret = 0;
  1381. goto exit;
  1382. }
  1383. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1384. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1385. req_volt, micb_en);
  1386. if (micb_en == 0x1)
  1387. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1388. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1389. if (micb_en == 0x1) {
  1390. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1391. /*
  1392. * Add 2ms delay as per HW requirement after enabling
  1393. * micbias
  1394. */
  1395. usleep_range(2000, 2100);
  1396. }
  1397. exit:
  1398. mutex_unlock(&wcd938x->micb_lock);
  1399. return ret;
  1400. }
  1401. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1402. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1403. struct snd_kcontrol *kcontrol,
  1404. int event)
  1405. {
  1406. struct snd_soc_component *component =
  1407. snd_soc_dapm_to_component(w->dapm);
  1408. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1409. int ret = 0;
  1410. int bank = 0;
  1411. u8 mode = 0;
  1412. int i = 0;
  1413. int rate = 0;
  1414. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1415. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1416. /* power mode is applicable only to analog mics */
  1417. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1418. /* Get channel rate */
  1419. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1420. }
  1421. switch (event) {
  1422. case SND_SOC_DAPM_PRE_PMU:
  1423. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1424. if (w->shift == ADC2 && !(snd_soc_component_read32(component,
  1425. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1426. if (!wcd938x->bcs_dis)
  1427. wcd938x_tx_connect_port(component, MBHC,
  1428. SWR_CLK_RATE_4P8MHZ, true);
  1429. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1430. }
  1431. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1432. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1433. wcd938x_tx_connect_port(component, w->shift, rate,
  1434. true);
  1435. } else {
  1436. wcd938x_tx_connect_port(component, w->shift,
  1437. SWR_CLK_RATE_2P4MHZ, true);
  1438. }
  1439. break;
  1440. case SND_SOC_DAPM_POST_PMD:
  1441. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1442. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1443. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1444. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1445. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1446. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1447. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1448. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1449. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1450. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1451. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1452. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1453. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1454. }
  1455. }
  1456. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1457. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1458. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1459. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1460. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1461. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1462. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1463. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1464. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1465. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1466. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1467. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1468. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1469. if (mode != 0) {
  1470. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1471. if (mode & (1 << i)) {
  1472. i++;
  1473. break;
  1474. }
  1475. }
  1476. }
  1477. rate = wcd938x_get_clk_rate(i);
  1478. if (wcd938x->adc_count) {
  1479. rate = (wcd938x->adc_count * rate);
  1480. if (rate > SWR_CLK_RATE_9P6MHZ)
  1481. rate = SWR_CLK_RATE_9P6MHZ;
  1482. }
  1483. wcd938x_set_swr_clk_rate(component, rate, bank);
  1484. }
  1485. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1486. wcd938x->tx_swr_dev->dev_num,
  1487. false);
  1488. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1489. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1490. break;
  1491. };
  1492. return ret;
  1493. }
  1494. static int wcd938x_get_adc_mode(int val)
  1495. {
  1496. int ret = 0;
  1497. switch (val) {
  1498. case ADC_MODE_INVALID:
  1499. ret = ADC_MODE_VAL_NORMAL;
  1500. break;
  1501. case ADC_MODE_HIFI:
  1502. ret = ADC_MODE_VAL_HIFI;
  1503. break;
  1504. case ADC_MODE_LO_HIF:
  1505. ret = ADC_MODE_VAL_LO_HIF;
  1506. break;
  1507. case ADC_MODE_NORMAL:
  1508. ret = ADC_MODE_VAL_NORMAL;
  1509. break;
  1510. case ADC_MODE_LP:
  1511. ret = ADC_MODE_VAL_LP;
  1512. break;
  1513. case ADC_MODE_ULP1:
  1514. ret = ADC_MODE_VAL_ULP1;
  1515. break;
  1516. case ADC_MODE_ULP2:
  1517. ret = ADC_MODE_VAL_ULP2;
  1518. break;
  1519. default:
  1520. ret = -EINVAL;
  1521. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1522. break;
  1523. }
  1524. return ret;
  1525. }
  1526. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1527. int channel, int mode)
  1528. {
  1529. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1530. int ret = 0;
  1531. switch (channel) {
  1532. case 0:
  1533. reg = WCD938X_ANA_TX_CH2;
  1534. mask = 0x40;
  1535. break;
  1536. case 1:
  1537. reg = WCD938X_ANA_TX_CH2;
  1538. mask = 0x20;
  1539. break;
  1540. case 2:
  1541. reg = WCD938X_ANA_TX_CH4;
  1542. mask = 0x40;
  1543. break;
  1544. case 3:
  1545. reg = WCD938X_ANA_TX_CH4;
  1546. mask = 0x20;
  1547. break;
  1548. default:
  1549. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1550. ret = -EINVAL;
  1551. break;
  1552. }
  1553. if (!mode)
  1554. val = 0x00;
  1555. else
  1556. val = mask;
  1557. if (!ret)
  1558. snd_soc_component_update_bits(component, reg, mask, val);
  1559. return ret;
  1560. }
  1561. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1562. struct snd_kcontrol *kcontrol,
  1563. int event){
  1564. struct snd_soc_component *component =
  1565. snd_soc_dapm_to_component(w->dapm);
  1566. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1567. int clk_rate = 0, ret = 0;
  1568. int mode = 0, i = 0, bank = 0;
  1569. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1570. w->name, event);
  1571. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1572. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1573. switch (event) {
  1574. case SND_SOC_DAPM_PRE_PMU:
  1575. wcd938x->adc_count++;
  1576. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1577. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1578. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1579. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1580. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1581. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1582. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1583. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1584. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1585. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1586. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1587. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1588. if (mode != 0) {
  1589. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1590. if (mode & (1 << i)) {
  1591. i++;
  1592. break;
  1593. }
  1594. }
  1595. }
  1596. clk_rate = wcd938x_get_clk_rate(i);
  1597. /* clk_rate depends on number of paths getting enabled */
  1598. clk_rate = (wcd938x->adc_count * clk_rate);
  1599. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1600. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1601. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1602. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1603. wcd938x->tx_swr_dev->dev_num,
  1604. true);
  1605. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1606. break;
  1607. case SND_SOC_DAPM_POST_PMD:
  1608. wcd938x->adc_count--;
  1609. if (wcd938x->adc_count < 0)
  1610. wcd938x->adc_count = 0;
  1611. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1612. if (w->shift + ADC1 == ADC2 &&
  1613. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1614. if (!wcd938x->bcs_dis)
  1615. wcd938x_tx_connect_port(component, MBHC, 0,
  1616. false);
  1617. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1618. }
  1619. break;
  1620. };
  1621. return ret;
  1622. }
  1623. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1624. bool bcs_disable)
  1625. {
  1626. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1627. if (wcd938x->update_wcd_event) {
  1628. if (bcs_disable)
  1629. wcd938x->update_wcd_event(wcd938x->handle,
  1630. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1631. else
  1632. wcd938x->update_wcd_event(wcd938x->handle,
  1633. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1634. }
  1635. }
  1636. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1637. struct snd_kcontrol *kcontrol, int event)
  1638. {
  1639. struct snd_soc_component *component =
  1640. snd_soc_dapm_to_component(w->dapm);
  1641. struct wcd938x_priv *wcd938x =
  1642. snd_soc_component_get_drvdata(component);
  1643. int ret = 0;
  1644. u8 mode = 0;
  1645. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1646. w->name, event);
  1647. switch (event) {
  1648. case SND_SOC_DAPM_PRE_PMU:
  1649. snd_soc_component_update_bits(component,
  1650. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1651. snd_soc_component_update_bits(component,
  1652. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1653. snd_soc_component_update_bits(component,
  1654. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1655. snd_soc_component_update_bits(component,
  1656. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1657. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1658. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1659. if (mode < 0) {
  1660. dev_info(component->dev,
  1661. "%s: invalid mode, setting to normal mode\n",
  1662. __func__);
  1663. mode = ADC_MODE_VAL_NORMAL;
  1664. }
  1665. switch (w->shift) {
  1666. case 0:
  1667. snd_soc_component_update_bits(component,
  1668. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1669. mode);
  1670. snd_soc_component_update_bits(component,
  1671. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1672. break;
  1673. case 1:
  1674. snd_soc_component_update_bits(component,
  1675. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1676. mode << 4);
  1677. snd_soc_component_update_bits(component,
  1678. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1679. break;
  1680. case 2:
  1681. snd_soc_component_update_bits(component,
  1682. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1683. mode);
  1684. snd_soc_component_update_bits(component,
  1685. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1686. break;
  1687. case 3:
  1688. snd_soc_component_update_bits(component,
  1689. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1690. mode << 4);
  1691. snd_soc_component_update_bits(component,
  1692. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1693. break;
  1694. default:
  1695. break;
  1696. }
  1697. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1698. break;
  1699. case SND_SOC_DAPM_POST_PMD:
  1700. switch (w->shift) {
  1701. case 0:
  1702. snd_soc_component_update_bits(component,
  1703. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1704. 0x00);
  1705. snd_soc_component_update_bits(component,
  1706. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1707. break;
  1708. case 1:
  1709. snd_soc_component_update_bits(component,
  1710. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1711. 0x00);
  1712. snd_soc_component_update_bits(component,
  1713. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1714. break;
  1715. case 2:
  1716. snd_soc_component_update_bits(component,
  1717. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1718. 0x00);
  1719. snd_soc_component_update_bits(component,
  1720. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1721. break;
  1722. case 3:
  1723. snd_soc_component_update_bits(component,
  1724. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1725. 0x00);
  1726. snd_soc_component_update_bits(component,
  1727. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1728. break;
  1729. default:
  1730. break;
  1731. }
  1732. if (wcd938x->adc_count == 0)
  1733. snd_soc_component_update_bits(component,
  1734. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1735. break;
  1736. };
  1737. return ret;
  1738. }
  1739. int wcd938x_micbias_control(struct snd_soc_component *component,
  1740. int micb_num, int req, bool is_dapm)
  1741. {
  1742. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1743. int micb_index = micb_num - 1;
  1744. u16 micb_reg;
  1745. int pre_off_event = 0, post_off_event = 0;
  1746. int post_on_event = 0, post_dapm_off = 0;
  1747. int post_dapm_on = 0;
  1748. int ret = 0;
  1749. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1750. dev_err(component->dev,
  1751. "%s: Invalid micbias index, micb_ind:%d\n",
  1752. __func__, micb_index);
  1753. return -EINVAL;
  1754. }
  1755. if (NULL == wcd938x) {
  1756. dev_err(component->dev,
  1757. "%s: wcd938x private data is NULL\n", __func__);
  1758. return -EINVAL;
  1759. }
  1760. switch (micb_num) {
  1761. case MIC_BIAS_1:
  1762. micb_reg = WCD938X_ANA_MICB1;
  1763. break;
  1764. case MIC_BIAS_2:
  1765. micb_reg = WCD938X_ANA_MICB2;
  1766. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1767. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1768. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1769. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1770. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1771. break;
  1772. case MIC_BIAS_3:
  1773. micb_reg = WCD938X_ANA_MICB3;
  1774. break;
  1775. case MIC_BIAS_4:
  1776. micb_reg = WCD938X_ANA_MICB4;
  1777. break;
  1778. default:
  1779. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1780. __func__, micb_num);
  1781. return -EINVAL;
  1782. };
  1783. mutex_lock(&wcd938x->micb_lock);
  1784. switch (req) {
  1785. case MICB_PULLUP_ENABLE:
  1786. if (!wcd938x->dev_up) {
  1787. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1788. __func__, req);
  1789. ret = -ENODEV;
  1790. goto done;
  1791. }
  1792. wcd938x->pullup_ref[micb_index]++;
  1793. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1794. (wcd938x->micb_ref[micb_index] == 0))
  1795. snd_soc_component_update_bits(component, micb_reg,
  1796. 0xC0, 0x80);
  1797. break;
  1798. case MICB_PULLUP_DISABLE:
  1799. if (wcd938x->pullup_ref[micb_index] > 0)
  1800. wcd938x->pullup_ref[micb_index]--;
  1801. if (!wcd938x->dev_up) {
  1802. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1803. __func__, req);
  1804. ret = -ENODEV;
  1805. goto done;
  1806. }
  1807. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1808. (wcd938x->micb_ref[micb_index] == 0))
  1809. snd_soc_component_update_bits(component, micb_reg,
  1810. 0xC0, 0x00);
  1811. break;
  1812. case MICB_ENABLE:
  1813. if (!wcd938x->dev_up) {
  1814. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1815. __func__, req);
  1816. ret = -ENODEV;
  1817. goto done;
  1818. }
  1819. wcd938x->micb_ref[micb_index]++;
  1820. if (wcd938x->micb_ref[micb_index] == 1) {
  1821. snd_soc_component_update_bits(component,
  1822. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1823. snd_soc_component_update_bits(component,
  1824. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1825. snd_soc_component_update_bits(component,
  1826. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1827. snd_soc_component_update_bits(component,
  1828. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1829. snd_soc_component_update_bits(component,
  1830. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1831. snd_soc_component_update_bits(component,
  1832. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1833. snd_soc_component_update_bits(component,
  1834. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1835. snd_soc_component_update_bits(component,
  1836. micb_reg, 0xC0, 0x40);
  1837. if (post_on_event)
  1838. blocking_notifier_call_chain(
  1839. &wcd938x->mbhc->notifier,
  1840. post_on_event,
  1841. &wcd938x->mbhc->wcd_mbhc);
  1842. }
  1843. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1844. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1845. post_dapm_on,
  1846. &wcd938x->mbhc->wcd_mbhc);
  1847. break;
  1848. case MICB_DISABLE:
  1849. if (wcd938x->micb_ref[micb_index] > 0)
  1850. wcd938x->micb_ref[micb_index]--;
  1851. if (!wcd938x->dev_up) {
  1852. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1853. __func__, req);
  1854. ret = -ENODEV;
  1855. goto done;
  1856. }
  1857. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1858. (wcd938x->pullup_ref[micb_index] > 0))
  1859. snd_soc_component_update_bits(component, micb_reg,
  1860. 0xC0, 0x80);
  1861. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1862. (wcd938x->pullup_ref[micb_index] == 0)) {
  1863. if (pre_off_event && wcd938x->mbhc)
  1864. blocking_notifier_call_chain(
  1865. &wcd938x->mbhc->notifier,
  1866. pre_off_event,
  1867. &wcd938x->mbhc->wcd_mbhc);
  1868. snd_soc_component_update_bits(component, micb_reg,
  1869. 0xC0, 0x00);
  1870. if (post_off_event && wcd938x->mbhc)
  1871. blocking_notifier_call_chain(
  1872. &wcd938x->mbhc->notifier,
  1873. post_off_event,
  1874. &wcd938x->mbhc->wcd_mbhc);
  1875. }
  1876. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1877. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1878. post_dapm_off,
  1879. &wcd938x->mbhc->wcd_mbhc);
  1880. break;
  1881. };
  1882. dev_dbg(component->dev,
  1883. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1884. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1885. wcd938x->pullup_ref[micb_index]);
  1886. done:
  1887. mutex_unlock(&wcd938x->micb_lock);
  1888. return ret;
  1889. }
  1890. EXPORT_SYMBOL(wcd938x_micbias_control);
  1891. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1892. {
  1893. int ret = 0;
  1894. uint8_t devnum = 0;
  1895. int num_retry = NUM_ATTEMPTS;
  1896. do {
  1897. /* retry after 1ms */
  1898. usleep_range(1000, 1010);
  1899. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1900. } while (ret && --num_retry);
  1901. if (ret)
  1902. dev_err(&swr_dev->dev,
  1903. "%s get devnum %d for dev addr %llx failed\n",
  1904. __func__, devnum, swr_dev->addr);
  1905. swr_dev->dev_num = devnum;
  1906. return 0;
  1907. }
  1908. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1909. struct wcd_mbhc_config *mbhc_cfg)
  1910. {
  1911. if (mbhc_cfg->enable_usbc_analog) {
  1912. if (!(snd_soc_component_read32(component, WCD938X_ANA_MBHC_MECH)
  1913. & 0x20))
  1914. return true;
  1915. }
  1916. return false;
  1917. }
  1918. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  1919. struct notifier_block *nblock,
  1920. bool enable)
  1921. {
  1922. struct wcd938x_priv *wcd938x_priv;
  1923. if(NULL == component) {
  1924. pr_err("%s: wcd938x component is NULL\n", __func__);
  1925. return -EINVAL;
  1926. }
  1927. wcd938x_priv = snd_soc_component_get_drvdata(component);
  1928. wcd938x_priv->notify_swr_dmic = enable;
  1929. if (enable)
  1930. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  1931. nblock);
  1932. else
  1933. return blocking_notifier_chain_unregister(
  1934. &wcd938x_priv->notifier, nblock);
  1935. }
  1936. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  1937. static int wcd938x_event_notify(struct notifier_block *block,
  1938. unsigned long val,
  1939. void *data)
  1940. {
  1941. u16 event = (val & 0xffff);
  1942. int ret = 0;
  1943. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1944. struct snd_soc_component *component = wcd938x->component;
  1945. struct wcd_mbhc *mbhc;
  1946. switch (event) {
  1947. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1948. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1949. snd_soc_component_update_bits(component,
  1950. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1951. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1952. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1953. }
  1954. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1955. snd_soc_component_update_bits(component,
  1956. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1957. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1958. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1959. }
  1960. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1961. snd_soc_component_update_bits(component,
  1962. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1963. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1964. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1965. }
  1966. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1967. snd_soc_component_update_bits(component,
  1968. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1969. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1970. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1971. }
  1972. break;
  1973. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1974. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1975. 0xC0, 0x00);
  1976. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1977. 0x80, 0x00);
  1978. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1979. 0x80, 0x00);
  1980. break;
  1981. case BOLERO_WCD_EVT_SSR_DOWN:
  1982. wcd938x->dev_up = false;
  1983. if(wcd938x->notify_swr_dmic)
  1984. blocking_notifier_call_chain(&wcd938x->notifier,
  1985. WCD938X_EVT_SSR_DOWN,
  1986. NULL);
  1987. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1988. wcd938x->mbhc->wcd_mbhc.plug_before_ssr =
  1989. wcd938x->mbhc->wcd_mbhc.current_plug;
  1990. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1991. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  1992. mbhc->mbhc_cfg);
  1993. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1994. wcd938x_reset_low(wcd938x->dev);
  1995. break;
  1996. case BOLERO_WCD_EVT_SSR_UP:
  1997. wcd938x_reset(wcd938x->dev);
  1998. /* allow reset to take effect */
  1999. usleep_range(10000, 10010);
  2000. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2001. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2002. wcd938x_init_reg(component);
  2003. regcache_mark_dirty(wcd938x->regmap);
  2004. regcache_sync(wcd938x->regmap);
  2005. /* Initialize MBHC module */
  2006. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2007. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2008. if (ret) {
  2009. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2010. __func__);
  2011. } else {
  2012. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2013. if (wcd938x->usbc_hs_status)
  2014. mdelay(500);
  2015. }
  2016. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2017. wcd938x->dev_up = true;
  2018. if(wcd938x->notify_swr_dmic)
  2019. blocking_notifier_call_chain(&wcd938x->notifier,
  2020. WCD938X_EVT_SSR_UP,
  2021. NULL);
  2022. break;
  2023. case BOLERO_WCD_EVT_CLK_NOTIFY:
  2024. snd_soc_component_update_bits(component,
  2025. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2026. ((val >> 0x10) << 0x01));
  2027. break;
  2028. default:
  2029. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2030. break;
  2031. }
  2032. return 0;
  2033. }
  2034. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2035. int event)
  2036. {
  2037. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2038. int micb_num;
  2039. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2040. __func__, w->name, event);
  2041. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2042. micb_num = MIC_BIAS_1;
  2043. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2044. micb_num = MIC_BIAS_2;
  2045. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2046. micb_num = MIC_BIAS_3;
  2047. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2048. micb_num = MIC_BIAS_4;
  2049. else
  2050. return -EINVAL;
  2051. switch (event) {
  2052. case SND_SOC_DAPM_PRE_PMU:
  2053. wcd938x_micbias_control(component, micb_num,
  2054. MICB_ENABLE, true);
  2055. break;
  2056. case SND_SOC_DAPM_POST_PMU:
  2057. /* 1 msec delay as per HW requirement */
  2058. usleep_range(1000, 1100);
  2059. break;
  2060. case SND_SOC_DAPM_POST_PMD:
  2061. wcd938x_micbias_control(component, micb_num,
  2062. MICB_DISABLE, true);
  2063. break;
  2064. };
  2065. return 0;
  2066. }
  2067. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2068. struct snd_kcontrol *kcontrol,
  2069. int event)
  2070. {
  2071. return __wcd938x_codec_enable_micbias(w, event);
  2072. }
  2073. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2074. int event)
  2075. {
  2076. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2077. int micb_num;
  2078. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2079. __func__, w->name, event);
  2080. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2081. micb_num = MIC_BIAS_1;
  2082. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2083. micb_num = MIC_BIAS_2;
  2084. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2085. micb_num = MIC_BIAS_3;
  2086. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2087. micb_num = MIC_BIAS_4;
  2088. else
  2089. return -EINVAL;
  2090. switch (event) {
  2091. case SND_SOC_DAPM_PRE_PMU:
  2092. wcd938x_micbias_control(component, micb_num,
  2093. MICB_PULLUP_ENABLE, true);
  2094. break;
  2095. case SND_SOC_DAPM_POST_PMU:
  2096. /* 1 msec delay as per HW requirement */
  2097. usleep_range(1000, 1100);
  2098. break;
  2099. case SND_SOC_DAPM_POST_PMD:
  2100. wcd938x_micbias_control(component, micb_num,
  2101. MICB_PULLUP_DISABLE, true);
  2102. break;
  2103. };
  2104. return 0;
  2105. }
  2106. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2107. struct snd_kcontrol *kcontrol,
  2108. int event)
  2109. {
  2110. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2111. }
  2112. static int wcd938x_wakeup(void *handle, bool enable)
  2113. {
  2114. struct wcd938x_priv *priv;
  2115. int ret = 0;
  2116. if (!handle) {
  2117. pr_err("%s: NULL handle\n", __func__);
  2118. return -EINVAL;
  2119. }
  2120. priv = (struct wcd938x_priv *)handle;
  2121. if (!priv->tx_swr_dev) {
  2122. pr_err("%s: tx swr dev is NULL\n", __func__);
  2123. return -EINVAL;
  2124. }
  2125. mutex_lock(&priv->wakeup_lock);
  2126. if (enable)
  2127. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2128. else
  2129. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2130. mutex_unlock(&priv->wakeup_lock);
  2131. return ret;
  2132. }
  2133. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2134. struct snd_kcontrol *kcontrol,
  2135. int event)
  2136. {
  2137. int ret = 0;
  2138. struct snd_soc_component *component =
  2139. snd_soc_dapm_to_component(w->dapm);
  2140. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2141. switch (event) {
  2142. case SND_SOC_DAPM_PRE_PMU:
  2143. wcd938x_wakeup(wcd938x, true);
  2144. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2145. wcd938x_wakeup(wcd938x, false);
  2146. break;
  2147. case SND_SOC_DAPM_POST_PMD:
  2148. wcd938x_wakeup(wcd938x, true);
  2149. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2150. wcd938x_wakeup(wcd938x, false);
  2151. break;
  2152. }
  2153. return ret;
  2154. }
  2155. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2156. int micb_num, int req)
  2157. {
  2158. int micb_index = micb_num - 1;
  2159. u16 micb_reg;
  2160. if (NULL == wcd938x) {
  2161. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2162. return -EINVAL;
  2163. }
  2164. switch (micb_num) {
  2165. case MIC_BIAS_1:
  2166. micb_reg = WCD938X_ANA_MICB1;
  2167. break;
  2168. case MIC_BIAS_2:
  2169. micb_reg = WCD938X_ANA_MICB2;
  2170. break;
  2171. case MIC_BIAS_3:
  2172. micb_reg = WCD938X_ANA_MICB3;
  2173. break;
  2174. case MIC_BIAS_4:
  2175. micb_reg = WCD938X_ANA_MICB4;
  2176. break;
  2177. default:
  2178. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2179. return -EINVAL;
  2180. };
  2181. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2182. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2183. wcd938x->pullup_ref[micb_index]);
  2184. mutex_lock(&wcd938x->micb_lock);
  2185. switch (req) {
  2186. case MICB_ENABLE:
  2187. wcd938x->micb_ref[micb_index]++;
  2188. if (wcd938x->micb_ref[micb_index] == 1) {
  2189. regmap_update_bits(wcd938x->regmap,
  2190. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2191. regmap_update_bits(wcd938x->regmap,
  2192. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2193. regmap_update_bits(wcd938x->regmap,
  2194. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2195. regmap_update_bits(wcd938x->regmap,
  2196. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2197. regmap_update_bits(wcd938x->regmap,
  2198. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2199. regmap_update_bits(wcd938x->regmap,
  2200. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2201. regmap_update_bits(wcd938x->regmap,
  2202. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2203. regmap_update_bits(wcd938x->regmap,
  2204. micb_reg, 0xC0, 0x40);
  2205. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2206. }
  2207. break;
  2208. case MICB_PULLUP_ENABLE:
  2209. wcd938x->pullup_ref[micb_index]++;
  2210. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2211. (wcd938x->micb_ref[micb_index] == 0))
  2212. regmap_update_bits(wcd938x->regmap, micb_reg,
  2213. 0xC0, 0x80);
  2214. break;
  2215. case MICB_PULLUP_DISABLE:
  2216. if (wcd938x->pullup_ref[micb_index] > 0)
  2217. wcd938x->pullup_ref[micb_index]--;
  2218. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2219. (wcd938x->micb_ref[micb_index] == 0))
  2220. regmap_update_bits(wcd938x->regmap, micb_reg,
  2221. 0xC0, 0x00);
  2222. break;
  2223. case MICB_DISABLE:
  2224. if (wcd938x->micb_ref[micb_index] > 0)
  2225. wcd938x->micb_ref[micb_index]--;
  2226. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2227. (wcd938x->pullup_ref[micb_index] > 0))
  2228. regmap_update_bits(wcd938x->regmap, micb_reg,
  2229. 0xC0, 0x80);
  2230. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2231. (wcd938x->pullup_ref[micb_index] == 0))
  2232. regmap_update_bits(wcd938x->regmap, micb_reg,
  2233. 0xC0, 0x00);
  2234. break;
  2235. };
  2236. mutex_unlock(&wcd938x->micb_lock);
  2237. return 0;
  2238. }
  2239. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2240. int event, int micb_num)
  2241. {
  2242. struct wcd938x_priv *wcd938x_priv = NULL;
  2243. int ret = 0;
  2244. int micb_index = micb_num - 1;
  2245. if(NULL == component) {
  2246. pr_err("%s: wcd938x component is NULL\n", __func__);
  2247. return -EINVAL;
  2248. }
  2249. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2250. pr_err("%s: invalid event: %d\n", __func__, event);
  2251. return -EINVAL;
  2252. }
  2253. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2254. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2255. return -EINVAL;
  2256. }
  2257. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2258. if (!wcd938x_priv->dev_up) {
  2259. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2260. (event == SND_SOC_DAPM_POST_PMD)) {
  2261. wcd938x_priv->pullup_ref[micb_index]--;
  2262. ret = -ENODEV;
  2263. goto done;
  2264. }
  2265. }
  2266. switch (event) {
  2267. case SND_SOC_DAPM_PRE_PMU:
  2268. wcd938x_wakeup(wcd938x_priv, true);
  2269. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2270. wcd938x_wakeup(wcd938x_priv, false);
  2271. break;
  2272. case SND_SOC_DAPM_POST_PMD:
  2273. wcd938x_wakeup(wcd938x_priv, true);
  2274. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2275. wcd938x_wakeup(wcd938x_priv, false);
  2276. break;
  2277. }
  2278. done:
  2279. return ret;
  2280. }
  2281. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2282. static inline int wcd938x_tx_path_get(const char *wname,
  2283. unsigned int *path_num)
  2284. {
  2285. int ret = 0;
  2286. char *widget_name = NULL;
  2287. char *w_name = NULL;
  2288. char *path_num_char = NULL;
  2289. char *path_name = NULL;
  2290. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2291. if (!widget_name)
  2292. return -EINVAL;
  2293. w_name = widget_name;
  2294. path_name = strsep(&widget_name, " ");
  2295. if (!path_name) {
  2296. pr_err("%s: Invalid widget name = %s\n",
  2297. __func__, widget_name);
  2298. ret = -EINVAL;
  2299. goto err;
  2300. }
  2301. path_num_char = strpbrk(path_name, "0123");
  2302. if (!path_num_char) {
  2303. pr_err("%s: tx path index not found\n",
  2304. __func__);
  2305. ret = -EINVAL;
  2306. goto err;
  2307. }
  2308. ret = kstrtouint(path_num_char, 10, path_num);
  2309. if (ret < 0)
  2310. pr_err("%s: Invalid tx path = %s\n",
  2311. __func__, w_name);
  2312. err:
  2313. kfree(w_name);
  2314. return ret;
  2315. }
  2316. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2317. struct snd_ctl_elem_value *ucontrol)
  2318. {
  2319. struct snd_soc_component *component =
  2320. snd_soc_kcontrol_component(kcontrol);
  2321. struct wcd938x_priv *wcd938x = NULL;
  2322. int ret = 0;
  2323. unsigned int path = 0;
  2324. if (!component)
  2325. return -EINVAL;
  2326. wcd938x = snd_soc_component_get_drvdata(component);
  2327. if (!wcd938x)
  2328. return -EINVAL;
  2329. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2330. if (ret < 0)
  2331. return ret;
  2332. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2333. return 0;
  2334. }
  2335. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2336. struct snd_ctl_elem_value *ucontrol)
  2337. {
  2338. struct snd_soc_component *component =
  2339. snd_soc_kcontrol_component(kcontrol);
  2340. struct wcd938x_priv *wcd938x = NULL;
  2341. u32 mode_val;
  2342. unsigned int path = 0;
  2343. int ret = 0;
  2344. if (!component)
  2345. return -EINVAL;
  2346. wcd938x = snd_soc_component_get_drvdata(component);
  2347. if (!wcd938x)
  2348. return -EINVAL;
  2349. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2350. if (ret)
  2351. return ret;
  2352. mode_val = ucontrol->value.enumerated.item[0];
  2353. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2354. wcd938x->tx_mode[path] = mode_val;
  2355. return 0;
  2356. }
  2357. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2358. struct snd_ctl_elem_value *ucontrol)
  2359. {
  2360. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2361. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2362. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2363. return 0;
  2364. }
  2365. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2366. struct snd_ctl_elem_value *ucontrol)
  2367. {
  2368. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2369. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2370. u32 mode_val;
  2371. mode_val = ucontrol->value.enumerated.item[0];
  2372. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2373. if (wcd938x->variant == WCD9380) {
  2374. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2375. dev_info(component->dev,
  2376. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2377. __func__);
  2378. mode_val = CLS_H_ULP;
  2379. }
  2380. }
  2381. if (mode_val == CLS_H_NORMAL) {
  2382. dev_info(component->dev,
  2383. "%s:Invalid HPH Mode, default to class_AB\n",
  2384. __func__);
  2385. mode_val = CLS_H_ULP;
  2386. }
  2387. wcd938x->hph_mode = mode_val;
  2388. return 0;
  2389. }
  2390. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2391. struct snd_ctl_elem_value *ucontrol)
  2392. {
  2393. u8 ear_pa_gain = 0;
  2394. struct snd_soc_component *component =
  2395. snd_soc_kcontrol_component(kcontrol);
  2396. ear_pa_gain = snd_soc_component_read32(component,
  2397. WCD938X_ANA_EAR_COMPANDER_CTL);
  2398. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2399. ucontrol->value.integer.value[0] = ear_pa_gain;
  2400. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2401. ear_pa_gain);
  2402. return 0;
  2403. }
  2404. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2405. struct snd_ctl_elem_value *ucontrol)
  2406. {
  2407. u8 ear_pa_gain = 0;
  2408. struct snd_soc_component *component =
  2409. snd_soc_kcontrol_component(kcontrol);
  2410. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2411. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2412. __func__, ucontrol->value.integer.value[0]);
  2413. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2414. if (!wcd938x->comp1_enable) {
  2415. snd_soc_component_update_bits(component,
  2416. WCD938X_ANA_EAR_COMPANDER_CTL,
  2417. 0x7C, ear_pa_gain);
  2418. }
  2419. return 0;
  2420. }
  2421. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2422. struct snd_ctl_elem_value *ucontrol)
  2423. {
  2424. struct snd_soc_component *component =
  2425. snd_soc_kcontrol_component(kcontrol);
  2426. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2427. bool hphr;
  2428. struct soc_multi_mixer_control *mc;
  2429. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2430. hphr = mc->shift;
  2431. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2432. wcd938x->comp1_enable;
  2433. return 0;
  2434. }
  2435. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2436. struct snd_ctl_elem_value *ucontrol)
  2437. {
  2438. struct snd_soc_component *component =
  2439. snd_soc_kcontrol_component(kcontrol);
  2440. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2441. int value = ucontrol->value.integer.value[0];
  2442. bool hphr;
  2443. struct soc_multi_mixer_control *mc;
  2444. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2445. hphr = mc->shift;
  2446. if (hphr)
  2447. wcd938x->comp2_enable = value;
  2448. else
  2449. wcd938x->comp1_enable = value;
  2450. return 0;
  2451. }
  2452. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2453. struct snd_kcontrol *kcontrol,
  2454. int event)
  2455. {
  2456. struct snd_soc_component *component =
  2457. snd_soc_dapm_to_component(w->dapm);
  2458. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2459. struct wcd938x_pdata *pdata = NULL;
  2460. int ret = 0;
  2461. pdata = dev_get_platdata(wcd938x->dev);
  2462. if (!pdata) {
  2463. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2464. return -EINVAL;
  2465. }
  2466. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2467. wcd938x->supplies,
  2468. pdata->regulator,
  2469. pdata->num_supplies,
  2470. "cdc-vdd-buck"))
  2471. return 0;
  2472. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2473. w->name, event);
  2474. switch (event) {
  2475. case SND_SOC_DAPM_PRE_PMU:
  2476. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2477. dev_dbg(component->dev,
  2478. "%s: buck already in enabled state\n",
  2479. __func__);
  2480. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2481. return 0;
  2482. }
  2483. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2484. wcd938x->supplies,
  2485. pdata->regulator,
  2486. pdata->num_supplies,
  2487. "cdc-vdd-buck");
  2488. if (ret == -EINVAL) {
  2489. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2490. __func__);
  2491. return ret;
  2492. }
  2493. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2494. /*
  2495. * 200us sleep is required after LDO is enabled as per
  2496. * HW requirement
  2497. */
  2498. usleep_range(200, 250);
  2499. break;
  2500. case SND_SOC_DAPM_POST_PMD:
  2501. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2502. break;
  2503. }
  2504. return 0;
  2505. }
  2506. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2507. struct snd_ctl_elem_value *ucontrol)
  2508. {
  2509. struct snd_soc_component *component =
  2510. snd_soc_kcontrol_component(kcontrol);
  2511. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2512. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2513. return 0;
  2514. }
  2515. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2516. struct snd_ctl_elem_value *ucontrol)
  2517. {
  2518. struct snd_soc_component *component =
  2519. snd_soc_kcontrol_component(kcontrol);
  2520. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2521. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2522. return 0;
  2523. }
  2524. const char * const tx_master_ch_text[] = {
  2525. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2526. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2527. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2528. "SWRM_PCM_IN",
  2529. };
  2530. const struct soc_enum tx_master_ch_enum =
  2531. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2532. tx_master_ch_text);
  2533. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2534. {
  2535. u8 ch_type = 0;
  2536. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2537. ch_type = ADC1;
  2538. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2539. ch_type = ADC2;
  2540. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2541. ch_type = ADC3;
  2542. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2543. ch_type = ADC4;
  2544. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2545. ch_type = DMIC0;
  2546. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2547. ch_type = DMIC1;
  2548. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2549. ch_type = MBHC;
  2550. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2551. ch_type = DMIC2;
  2552. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2553. ch_type = DMIC3;
  2554. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2555. ch_type = DMIC4;
  2556. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2557. ch_type = DMIC5;
  2558. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2559. ch_type = DMIC6;
  2560. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2561. ch_type = DMIC7;
  2562. else
  2563. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2564. if (ch_type)
  2565. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2566. else
  2567. *ch_idx = -EINVAL;
  2568. }
  2569. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2570. struct snd_ctl_elem_value *ucontrol)
  2571. {
  2572. struct snd_soc_component *component =
  2573. snd_soc_kcontrol_component(kcontrol);
  2574. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2575. int slave_ch_idx;
  2576. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2577. if (slave_ch_idx != -EINVAL)
  2578. ucontrol->value.integer.value[0] =
  2579. wcd938x_slave_get_master_ch_val(
  2580. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2581. return 0;
  2582. }
  2583. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2584. struct snd_ctl_elem_value *ucontrol)
  2585. {
  2586. struct snd_soc_component *component =
  2587. snd_soc_kcontrol_component(kcontrol);
  2588. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2589. int slave_ch_idx;
  2590. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2591. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2592. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2593. __func__, ucontrol->value.enumerated.item[0]);
  2594. if (slave_ch_idx != -EINVAL)
  2595. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2596. wcd938x_slave_get_master_ch(
  2597. ucontrol->value.enumerated.item[0]);
  2598. return 0;
  2599. }
  2600. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2601. struct snd_ctl_elem_value *ucontrol)
  2602. {
  2603. struct snd_soc_component *component =
  2604. snd_soc_kcontrol_component(kcontrol);
  2605. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2606. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2607. return 0;
  2608. }
  2609. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2610. struct snd_ctl_elem_value *ucontrol)
  2611. {
  2612. struct snd_soc_component *component =
  2613. snd_soc_kcontrol_component(kcontrol);
  2614. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2615. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2616. return 0;
  2617. }
  2618. static const char * const tx_mode_mux_text_wcd9380[] = {
  2619. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2620. };
  2621. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2622. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2623. tx_mode_mux_text_wcd9380);
  2624. static const char * const tx_mode_mux_text[] = {
  2625. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2626. "ADC_ULP1", "ADC_ULP2",
  2627. };
  2628. static const struct soc_enum tx_mode_mux_enum =
  2629. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2630. tx_mode_mux_text);
  2631. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2632. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2633. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2634. "CLS_AB_LOHIFI",
  2635. };
  2636. static const char * const wcd938x_ear_pa_gain_text[] = {
  2637. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2638. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2639. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2640. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2641. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2642. };
  2643. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2644. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2645. rx_hph_mode_mux_text_wcd9380);
  2646. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2647. wcd938x_ear_pa_gain_text);
  2648. static const char * const rx_hph_mode_mux_text[] = {
  2649. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2650. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2651. };
  2652. static const struct soc_enum rx_hph_mode_mux_enum =
  2653. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2654. rx_hph_mode_mux_text);
  2655. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2656. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2657. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2658. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2659. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2660. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2661. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2662. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2663. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2664. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2665. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2666. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2667. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2668. };
  2669. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2670. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2671. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2672. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2673. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2674. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2675. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2676. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2677. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2678. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2679. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2680. };
  2681. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2682. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2683. wcd938x_get_compander, wcd938x_set_compander),
  2684. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2685. wcd938x_get_compander, wcd938x_set_compander),
  2686. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2687. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2688. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2689. wcd938x_bcs_get, wcd938x_bcs_put),
  2690. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2691. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2692. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2693. analog_gain),
  2694. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2695. analog_gain),
  2696. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2697. analog_gain),
  2698. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2699. analog_gain),
  2700. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2701. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2702. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2703. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2704. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2705. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2706. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2707. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2708. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2709. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2710. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2711. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2712. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2713. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2714. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2715. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2716. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2717. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2718. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2719. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2720. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2721. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2722. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2723. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2724. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2725. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2726. };
  2727. static const struct snd_kcontrol_new adc1_switch[] = {
  2728. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2729. };
  2730. static const struct snd_kcontrol_new adc2_switch[] = {
  2731. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2732. };
  2733. static const struct snd_kcontrol_new adc3_switch[] = {
  2734. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2735. };
  2736. static const struct snd_kcontrol_new adc4_switch[] = {
  2737. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2738. };
  2739. static const struct snd_kcontrol_new dmic1_switch[] = {
  2740. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2741. };
  2742. static const struct snd_kcontrol_new dmic2_switch[] = {
  2743. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2744. };
  2745. static const struct snd_kcontrol_new dmic3_switch[] = {
  2746. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2747. };
  2748. static const struct snd_kcontrol_new dmic4_switch[] = {
  2749. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2750. };
  2751. static const struct snd_kcontrol_new dmic5_switch[] = {
  2752. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2753. };
  2754. static const struct snd_kcontrol_new dmic6_switch[] = {
  2755. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2756. };
  2757. static const struct snd_kcontrol_new dmic7_switch[] = {
  2758. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2759. };
  2760. static const struct snd_kcontrol_new dmic8_switch[] = {
  2761. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2762. };
  2763. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2764. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2765. };
  2766. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2767. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2768. };
  2769. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2770. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2771. };
  2772. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2773. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2774. };
  2775. static const char * const adc2_mux_text[] = {
  2776. "INP2", "INP3"
  2777. };
  2778. static const struct soc_enum adc2_enum =
  2779. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2780. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2781. static const struct snd_kcontrol_new tx_adc2_mux =
  2782. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2783. static const char * const adc3_mux_text[] = {
  2784. "INP4", "INP6"
  2785. };
  2786. static const struct soc_enum adc3_enum =
  2787. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2788. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2789. static const struct snd_kcontrol_new tx_adc3_mux =
  2790. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2791. static const char * const adc4_mux_text[] = {
  2792. "INP5", "INP7"
  2793. };
  2794. static const struct soc_enum adc4_enum =
  2795. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2796. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2797. static const struct snd_kcontrol_new tx_adc4_mux =
  2798. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2799. static const char * const rdac3_mux_text[] = {
  2800. "RX1", "RX3"
  2801. };
  2802. static const char * const hdr12_mux_text[] = {
  2803. "NO_HDR12", "HDR12"
  2804. };
  2805. static const struct soc_enum hdr12_enum =
  2806. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2807. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2808. static const struct snd_kcontrol_new tx_hdr12_mux =
  2809. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2810. static const char * const hdr34_mux_text[] = {
  2811. "NO_HDR34", "HDR34"
  2812. };
  2813. static const struct soc_enum hdr34_enum =
  2814. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2815. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2816. static const struct snd_kcontrol_new tx_hdr34_mux =
  2817. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2818. static const struct soc_enum rdac3_enum =
  2819. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2820. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2821. static const struct snd_kcontrol_new rx_rdac3_mux =
  2822. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2823. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2824. /*input widgets*/
  2825. SND_SOC_DAPM_INPUT("AMIC1"),
  2826. SND_SOC_DAPM_INPUT("AMIC2"),
  2827. SND_SOC_DAPM_INPUT("AMIC3"),
  2828. SND_SOC_DAPM_INPUT("AMIC4"),
  2829. SND_SOC_DAPM_INPUT("AMIC5"),
  2830. SND_SOC_DAPM_INPUT("AMIC6"),
  2831. SND_SOC_DAPM_INPUT("AMIC7"),
  2832. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2833. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2834. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2835. /*
  2836. * These dummy widgets are null connected to WCD938x dapm input and
  2837. * output widgets which are not actual path endpoints. This ensures
  2838. * dapm doesnt set these dapm input and output widgets as endpoints.
  2839. */
  2840. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2841. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2842. /*tx widgets*/
  2843. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2844. wcd938x_codec_enable_adc,
  2845. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2846. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2847. wcd938x_codec_enable_adc,
  2848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2849. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2850. wcd938x_codec_enable_adc,
  2851. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2852. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2853. wcd938x_codec_enable_adc,
  2854. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2855. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2856. wcd938x_codec_enable_dmic,
  2857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2858. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2859. wcd938x_codec_enable_dmic,
  2860. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2861. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2862. wcd938x_codec_enable_dmic,
  2863. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2864. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2865. wcd938x_codec_enable_dmic,
  2866. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2867. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2868. wcd938x_codec_enable_dmic,
  2869. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2870. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2871. wcd938x_codec_enable_dmic,
  2872. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2873. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2874. wcd938x_codec_enable_dmic,
  2875. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2876. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2877. wcd938x_codec_enable_dmic,
  2878. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2879. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2880. NULL, 0, wcd938x_enable_req,
  2881. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2882. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2883. NULL, 0, wcd938x_enable_req,
  2884. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2885. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2886. NULL, 0, wcd938x_enable_req,
  2887. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2888. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2889. NULL, 0, wcd938x_enable_req,
  2890. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2891. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2892. &tx_adc2_mux),
  2893. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2894. &tx_adc3_mux),
  2895. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2896. &tx_adc4_mux),
  2897. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2898. &tx_hdr12_mux),
  2899. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2900. &tx_hdr34_mux),
  2901. /*tx mixers*/
  2902. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  2903. adc1_switch, ARRAY_SIZE(adc1_switch),
  2904. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2905. SND_SOC_DAPM_POST_PMD),
  2906. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  2907. adc2_switch, ARRAY_SIZE(adc2_switch),
  2908. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2909. SND_SOC_DAPM_POST_PMD),
  2910. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  2911. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2912. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2913. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  2914. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2915. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2916. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2917. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2918. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2919. SND_SOC_DAPM_POST_PMD),
  2920. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2921. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2922. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2923. SND_SOC_DAPM_POST_PMD),
  2924. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2925. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2926. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2927. SND_SOC_DAPM_POST_PMD),
  2928. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2929. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2930. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2931. SND_SOC_DAPM_POST_PMD),
  2932. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2933. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2934. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2935. SND_SOC_DAPM_POST_PMD),
  2936. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  2937. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2938. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2939. SND_SOC_DAPM_POST_PMD),
  2940. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  2941. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2942. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2943. SND_SOC_DAPM_POST_PMD),
  2944. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  2945. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2946. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2947. SND_SOC_DAPM_POST_PMD),
  2948. /* micbias widgets*/
  2949. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2950. wcd938x_codec_enable_micbias,
  2951. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2952. SND_SOC_DAPM_POST_PMD),
  2953. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2954. wcd938x_codec_enable_micbias,
  2955. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2956. SND_SOC_DAPM_POST_PMD),
  2957. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2958. wcd938x_codec_enable_micbias,
  2959. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2960. SND_SOC_DAPM_POST_PMD),
  2961. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2962. wcd938x_codec_enable_micbias,
  2963. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2964. SND_SOC_DAPM_POST_PMD),
  2965. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2966. wcd938x_codec_force_enable_micbias,
  2967. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2968. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2969. wcd938x_codec_force_enable_micbias,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2971. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2972. wcd938x_codec_force_enable_micbias,
  2973. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2974. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2975. wcd938x_codec_force_enable_micbias,
  2976. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2977. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2978. wcd938x_codec_enable_vdd_buck,
  2979. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2980. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2981. wcd938x_enable_clsh,
  2982. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2983. /*rx widgets*/
  2984. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2985. wcd938x_codec_enable_ear_pa,
  2986. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2987. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2988. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2989. wcd938x_codec_enable_aux_pa,
  2990. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2991. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2992. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2993. wcd938x_codec_enable_hphl_pa,
  2994. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2995. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2996. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2997. wcd938x_codec_enable_hphr_pa,
  2998. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2999. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3000. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3001. wcd938x_codec_hphl_dac_event,
  3002. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3003. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3004. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3005. wcd938x_codec_hphr_dac_event,
  3006. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3007. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3008. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3009. wcd938x_codec_ear_dac_event,
  3010. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3011. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3012. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3013. wcd938x_codec_aux_dac_event,
  3014. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3015. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3016. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3017. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3018. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3019. SND_SOC_DAPM_POST_PMD),
  3020. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3021. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3022. SND_SOC_DAPM_POST_PMD),
  3023. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3024. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3025. SND_SOC_DAPM_POST_PMD),
  3026. /* rx mixer widgets*/
  3027. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3028. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3029. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3030. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3031. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3032. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3033. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3034. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3035. /*output widgets tx*/
  3036. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3037. /*output widgets rx*/
  3038. SND_SOC_DAPM_OUTPUT("EAR"),
  3039. SND_SOC_DAPM_OUTPUT("AUX"),
  3040. SND_SOC_DAPM_OUTPUT("HPHL"),
  3041. SND_SOC_DAPM_OUTPUT("HPHR"),
  3042. /* micbias pull up widgets*/
  3043. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3044. wcd938x_codec_enable_micbias_pullup,
  3045. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3046. SND_SOC_DAPM_POST_PMD),
  3047. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3048. wcd938x_codec_enable_micbias_pullup,
  3049. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3050. SND_SOC_DAPM_POST_PMD),
  3051. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3052. wcd938x_codec_enable_micbias_pullup,
  3053. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3054. SND_SOC_DAPM_POST_PMD),
  3055. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3056. wcd938x_codec_enable_micbias_pullup,
  3057. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3058. SND_SOC_DAPM_POST_PMD),
  3059. };
  3060. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3061. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3062. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3063. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3064. {"ADC1 REQ", NULL, "ADC1"},
  3065. {"ADC1", NULL, "AMIC1"},
  3066. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3067. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3068. {"ADC2 REQ", NULL, "ADC2"},
  3069. {"ADC2", NULL, "HDR12 MUX"},
  3070. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3071. {"HDR12 MUX", "HDR12", "AMIC1"},
  3072. {"ADC2 MUX", "INP3", "AMIC3"},
  3073. {"ADC2 MUX", "INP2", "AMIC2"},
  3074. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3075. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3076. {"ADC3 REQ", NULL, "ADC3"},
  3077. {"ADC3", NULL, "HDR34 MUX"},
  3078. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3079. {"HDR34 MUX", "HDR34", "AMIC5"},
  3080. {"ADC3 MUX", "INP4", "AMIC4"},
  3081. {"ADC3 MUX", "INP6", "AMIC6"},
  3082. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3083. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3084. {"ADC4 REQ", NULL, "ADC4"},
  3085. {"ADC4", NULL, "ADC4 MUX"},
  3086. {"ADC4 MUX", "INP5", "AMIC5"},
  3087. {"ADC4 MUX", "INP7", "AMIC7"},
  3088. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3089. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3090. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3091. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3092. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3093. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3094. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3095. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3096. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3097. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3098. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3099. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3100. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3101. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3102. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3103. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3104. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3105. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3106. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3107. {"RX1", NULL, "IN1_HPHL"},
  3108. {"RDAC1", NULL, "RX1"},
  3109. {"HPHL_RDAC", "Switch", "RDAC1"},
  3110. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3111. {"HPHL", NULL, "HPHL PGA"},
  3112. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3113. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3114. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3115. {"RX2", NULL, "IN2_HPHR"},
  3116. {"RDAC2", NULL, "RX2"},
  3117. {"HPHR_RDAC", "Switch", "RDAC2"},
  3118. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3119. {"HPHR", NULL, "HPHR PGA"},
  3120. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3121. {"IN3_AUX", NULL, "VDD_BUCK"},
  3122. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3123. {"RX3", NULL, "IN3_AUX"},
  3124. {"RDAC4", NULL, "RX3"},
  3125. {"AUX_RDAC", "Switch", "RDAC4"},
  3126. {"AUX PGA", NULL, "AUX_RDAC"},
  3127. {"AUX", NULL, "AUX PGA"},
  3128. {"RDAC3_MUX", "RX3", "RX3"},
  3129. {"RDAC3_MUX", "RX1", "RX1"},
  3130. {"RDAC3", NULL, "RDAC3_MUX"},
  3131. {"EAR_RDAC", "Switch", "RDAC3"},
  3132. {"EAR PGA", NULL, "EAR_RDAC"},
  3133. {"EAR", NULL, "EAR PGA"},
  3134. };
  3135. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3136. void *file_private_data,
  3137. struct file *file,
  3138. char __user *buf, size_t count,
  3139. loff_t pos)
  3140. {
  3141. struct wcd938x_priv *priv;
  3142. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3143. int len = 0;
  3144. priv = (struct wcd938x_priv *) entry->private_data;
  3145. if (!priv) {
  3146. pr_err("%s: wcd938x priv is null\n", __func__);
  3147. return -EINVAL;
  3148. }
  3149. switch (priv->version) {
  3150. case WCD938X_VERSION_1_0:
  3151. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3152. break;
  3153. default:
  3154. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3155. }
  3156. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3157. }
  3158. static struct snd_info_entry_ops wcd938x_info_ops = {
  3159. .read = wcd938x_version_read,
  3160. };
  3161. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3162. void *file_private_data,
  3163. struct file *file,
  3164. char __user *buf, size_t count,
  3165. loff_t pos)
  3166. {
  3167. struct wcd938x_priv *priv;
  3168. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3169. int len = 0;
  3170. priv = (struct wcd938x_priv *) entry->private_data;
  3171. if (!priv) {
  3172. pr_err("%s: wcd938x priv is null\n", __func__);
  3173. return -EINVAL;
  3174. }
  3175. switch (priv->variant) {
  3176. case WCD9380:
  3177. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3178. break;
  3179. case WCD9385:
  3180. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3181. break;
  3182. default:
  3183. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3184. }
  3185. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3186. }
  3187. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3188. .read = wcd938x_variant_read,
  3189. };
  3190. /*
  3191. * wcd938x_get_codec_variant
  3192. * @component: component instance
  3193. *
  3194. * Return: codec variant or -EINVAL in error.
  3195. */
  3196. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3197. {
  3198. struct wcd938x_priv *priv = NULL;
  3199. if (!component)
  3200. return -EINVAL;
  3201. priv = snd_soc_component_get_drvdata(component);
  3202. if (!priv) {
  3203. dev_err(component->dev,
  3204. "%s:wcd938x not probed\n", __func__);
  3205. return 0;
  3206. }
  3207. return priv->variant;
  3208. }
  3209. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3210. /*
  3211. * wcd938x_info_create_codec_entry - creates wcd938x module
  3212. * @codec_root: The parent directory
  3213. * @component: component instance
  3214. *
  3215. * Creates wcd938x module, variant and version entry under the given
  3216. * parent directory.
  3217. *
  3218. * Return: 0 on success or negative error code on failure.
  3219. */
  3220. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3221. struct snd_soc_component *component)
  3222. {
  3223. struct snd_info_entry *version_entry;
  3224. struct snd_info_entry *variant_entry;
  3225. struct wcd938x_priv *priv;
  3226. struct snd_soc_card *card;
  3227. if (!codec_root || !component)
  3228. return -EINVAL;
  3229. priv = snd_soc_component_get_drvdata(component);
  3230. if (priv->entry) {
  3231. dev_dbg(priv->dev,
  3232. "%s:wcd938x module already created\n", __func__);
  3233. return 0;
  3234. }
  3235. card = component->card;
  3236. priv->entry = snd_info_create_module_entry(codec_root->module,
  3237. "wcd938x", codec_root);
  3238. if (!priv->entry) {
  3239. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3240. __func__);
  3241. return -ENOMEM;
  3242. }
  3243. priv->entry->mode = S_IFDIR | 0555;
  3244. if (snd_info_register(priv->entry) < 0) {
  3245. snd_info_free_entry(priv->entry);
  3246. return -ENOMEM;
  3247. }
  3248. version_entry = snd_info_create_card_entry(card->snd_card,
  3249. "version",
  3250. priv->entry);
  3251. if (!version_entry) {
  3252. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3253. __func__);
  3254. snd_info_free_entry(priv->entry);
  3255. return -ENOMEM;
  3256. }
  3257. version_entry->private_data = priv;
  3258. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3259. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3260. version_entry->c.ops = &wcd938x_info_ops;
  3261. if (snd_info_register(version_entry) < 0) {
  3262. snd_info_free_entry(version_entry);
  3263. snd_info_free_entry(priv->entry);
  3264. return -ENOMEM;
  3265. }
  3266. priv->version_entry = version_entry;
  3267. variant_entry = snd_info_create_card_entry(card->snd_card,
  3268. "variant",
  3269. priv->entry);
  3270. if (!variant_entry) {
  3271. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3272. __func__);
  3273. snd_info_free_entry(version_entry);
  3274. snd_info_free_entry(priv->entry);
  3275. return -ENOMEM;
  3276. }
  3277. variant_entry->private_data = priv;
  3278. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3279. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3280. variant_entry->c.ops = &wcd938x_variant_ops;
  3281. if (snd_info_register(variant_entry) < 0) {
  3282. snd_info_free_entry(variant_entry);
  3283. snd_info_free_entry(version_entry);
  3284. snd_info_free_entry(priv->entry);
  3285. return -ENOMEM;
  3286. }
  3287. priv->variant_entry = variant_entry;
  3288. return 0;
  3289. }
  3290. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3291. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3292. struct wcd938x_pdata *pdata)
  3293. {
  3294. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3295. int rc = 0;
  3296. if (!pdata) {
  3297. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3298. return -ENODEV;
  3299. }
  3300. /* set micbias voltage */
  3301. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3302. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3303. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3304. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3305. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3306. vout_ctl_4 < 0) {
  3307. rc = -EINVAL;
  3308. goto done;
  3309. }
  3310. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3311. vout_ctl_1);
  3312. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3313. vout_ctl_2);
  3314. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3315. vout_ctl_3);
  3316. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3317. vout_ctl_4);
  3318. done:
  3319. return rc;
  3320. }
  3321. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3322. {
  3323. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3324. struct snd_soc_dapm_context *dapm =
  3325. snd_soc_component_get_dapm(component);
  3326. int variant;
  3327. int ret = -EINVAL;
  3328. dev_info(component->dev, "%s()\n", __func__);
  3329. wcd938x = snd_soc_component_get_drvdata(component);
  3330. if (!wcd938x)
  3331. return -EINVAL;
  3332. wcd938x->component = component;
  3333. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3334. variant = (snd_soc_component_read32(component,
  3335. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3336. wcd938x->variant = variant;
  3337. wcd938x->fw_data = devm_kzalloc(component->dev,
  3338. sizeof(*(wcd938x->fw_data)),
  3339. GFP_KERNEL);
  3340. if (!wcd938x->fw_data) {
  3341. dev_err(component->dev, "Failed to allocate fw_data\n");
  3342. ret = -ENOMEM;
  3343. goto err;
  3344. }
  3345. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3346. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3347. WCD9XXX_CODEC_HWDEP_NODE, component);
  3348. if (ret < 0) {
  3349. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3350. goto err_hwdep;
  3351. }
  3352. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3353. if (ret) {
  3354. pr_err("%s: mbhc initialization failed\n", __func__);
  3355. goto err_hwdep;
  3356. }
  3357. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3358. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3359. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3360. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3361. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3362. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3363. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3364. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3365. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3366. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3367. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3368. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3369. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3370. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3371. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3372. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3373. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3374. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3375. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3376. snd_soc_dapm_sync(dapm);
  3377. wcd_cls_h_init(&wcd938x->clsh_info);
  3378. wcd938x_init_reg(component);
  3379. if (wcd938x->variant == WCD9380) {
  3380. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3381. ARRAY_SIZE(wcd9380_snd_controls));
  3382. if (ret < 0) {
  3383. dev_err(component->dev,
  3384. "%s: Failed to add snd ctrls for variant: %d\n",
  3385. __func__, wcd938x->variant);
  3386. goto err_hwdep;
  3387. }
  3388. }
  3389. if (wcd938x->variant == WCD9385) {
  3390. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3391. ARRAY_SIZE(wcd9385_snd_controls));
  3392. if (ret < 0) {
  3393. dev_err(component->dev,
  3394. "%s: Failed to add snd ctrls for variant: %d\n",
  3395. __func__, wcd938x->variant);
  3396. goto err_hwdep;
  3397. }
  3398. }
  3399. wcd938x->version = WCD938X_VERSION_1_0;
  3400. /* Register event notifier */
  3401. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3402. if (wcd938x->register_notifier) {
  3403. ret = wcd938x->register_notifier(wcd938x->handle,
  3404. &wcd938x->nblock,
  3405. true);
  3406. if (ret) {
  3407. dev_err(component->dev,
  3408. "%s: Failed to register notifier %d\n",
  3409. __func__, ret);
  3410. return ret;
  3411. }
  3412. }
  3413. return ret;
  3414. err_hwdep:
  3415. wcd938x->fw_data = NULL;
  3416. err:
  3417. return ret;
  3418. }
  3419. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3420. {
  3421. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3422. if (!wcd938x) {
  3423. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3424. __func__);
  3425. return;
  3426. }
  3427. if (wcd938x->register_notifier)
  3428. wcd938x->register_notifier(wcd938x->handle,
  3429. &wcd938x->nblock,
  3430. false);
  3431. }
  3432. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3433. {
  3434. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3435. if (!wcd938x)
  3436. return 0;
  3437. wcd938x->dapm_bias_off = true;
  3438. return 0;
  3439. }
  3440. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3441. {
  3442. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3443. if (!wcd938x)
  3444. return 0;
  3445. wcd938x->dapm_bias_off = false;
  3446. return 0;
  3447. }
  3448. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3449. .name = WCD938X_DRV_NAME,
  3450. .probe = wcd938x_soc_codec_probe,
  3451. .remove = wcd938x_soc_codec_remove,
  3452. .controls = wcd938x_snd_controls,
  3453. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3454. .dapm_widgets = wcd938x_dapm_widgets,
  3455. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3456. .dapm_routes = wcd938x_audio_map,
  3457. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3458. .suspend = wcd938x_soc_codec_suspend,
  3459. .resume = wcd938x_soc_codec_resume,
  3460. };
  3461. static int wcd938x_reset(struct device *dev)
  3462. {
  3463. struct wcd938x_priv *wcd938x = NULL;
  3464. int rc = 0;
  3465. int value = 0;
  3466. if (!dev)
  3467. return -ENODEV;
  3468. wcd938x = dev_get_drvdata(dev);
  3469. if (!wcd938x)
  3470. return -EINVAL;
  3471. if (!wcd938x->rst_np) {
  3472. dev_err(dev, "%s: reset gpio device node not specified\n",
  3473. __func__);
  3474. return -EINVAL;
  3475. }
  3476. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3477. if (value > 0)
  3478. return 0;
  3479. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3480. if (rc) {
  3481. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3482. __func__);
  3483. return rc;
  3484. }
  3485. /* 20us sleep required after pulling the reset gpio to LOW */
  3486. usleep_range(20, 30);
  3487. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3488. if (rc) {
  3489. dev_err(dev, "%s: wcd active state request fail!\n",
  3490. __func__);
  3491. return rc;
  3492. }
  3493. /* 20us sleep required after pulling the reset gpio to HIGH */
  3494. usleep_range(20, 30);
  3495. return rc;
  3496. }
  3497. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3498. u32 *val)
  3499. {
  3500. int rc = 0;
  3501. rc = of_property_read_u32(dev->of_node, name, val);
  3502. if (rc)
  3503. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3504. __func__, name, dev->of_node->full_name);
  3505. return rc;
  3506. }
  3507. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3508. struct wcd938x_micbias_setting *mb)
  3509. {
  3510. u32 prop_val = 0;
  3511. int rc = 0;
  3512. /* MB1 */
  3513. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3514. NULL)) {
  3515. rc = wcd938x_read_of_property_u32(dev,
  3516. "qcom,cdc-micbias1-mv",
  3517. &prop_val);
  3518. if (!rc)
  3519. mb->micb1_mv = prop_val;
  3520. } else {
  3521. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3522. __func__);
  3523. }
  3524. /* MB2 */
  3525. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3526. NULL)) {
  3527. rc = wcd938x_read_of_property_u32(dev,
  3528. "qcom,cdc-micbias2-mv",
  3529. &prop_val);
  3530. if (!rc)
  3531. mb->micb2_mv = prop_val;
  3532. } else {
  3533. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3534. __func__);
  3535. }
  3536. /* MB3 */
  3537. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3538. NULL)) {
  3539. rc = wcd938x_read_of_property_u32(dev,
  3540. "qcom,cdc-micbias3-mv",
  3541. &prop_val);
  3542. if (!rc)
  3543. mb->micb3_mv = prop_val;
  3544. } else {
  3545. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3546. __func__);
  3547. }
  3548. /* MB4 */
  3549. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3550. NULL)) {
  3551. rc = wcd938x_read_of_property_u32(dev,
  3552. "qcom,cdc-micbias4-mv",
  3553. &prop_val);
  3554. if (!rc)
  3555. mb->micb4_mv = prop_val;
  3556. } else {
  3557. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3558. __func__);
  3559. }
  3560. }
  3561. static int wcd938x_reset_low(struct device *dev)
  3562. {
  3563. struct wcd938x_priv *wcd938x = NULL;
  3564. int rc = 0;
  3565. if (!dev)
  3566. return -ENODEV;
  3567. wcd938x = dev_get_drvdata(dev);
  3568. if (!wcd938x)
  3569. return -EINVAL;
  3570. if (!wcd938x->rst_np) {
  3571. dev_err(dev, "%s: reset gpio device node not specified\n",
  3572. __func__);
  3573. return -EINVAL;
  3574. }
  3575. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3576. if (rc) {
  3577. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3578. __func__);
  3579. return rc;
  3580. }
  3581. /* 20us sleep required after pulling the reset gpio to LOW */
  3582. usleep_range(20, 30);
  3583. return rc;
  3584. }
  3585. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3586. {
  3587. struct wcd938x_pdata *pdata = NULL;
  3588. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3589. GFP_KERNEL);
  3590. if (!pdata)
  3591. return NULL;
  3592. pdata->rst_np = of_parse_phandle(dev->of_node,
  3593. "qcom,wcd-rst-gpio-node", 0);
  3594. if (!pdata->rst_np) {
  3595. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3596. __func__, "qcom,wcd-rst-gpio-node",
  3597. dev->of_node->full_name);
  3598. return NULL;
  3599. }
  3600. /* Parse power supplies */
  3601. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3602. &pdata->num_supplies);
  3603. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3604. dev_err(dev, "%s: no power supplies defined for codec\n",
  3605. __func__);
  3606. return NULL;
  3607. }
  3608. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3609. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3610. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3611. return pdata;
  3612. }
  3613. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3614. {
  3615. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3616. __func__, irq);
  3617. return IRQ_HANDLED;
  3618. }
  3619. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3620. {
  3621. .name = "wcd938x_cdc",
  3622. .playback = {
  3623. .stream_name = "WCD938X_AIF Playback",
  3624. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3625. .formats = WCD938X_FORMATS,
  3626. .rate_max = 192000,
  3627. .rate_min = 8000,
  3628. .channels_min = 1,
  3629. .channels_max = 4,
  3630. },
  3631. .capture = {
  3632. .stream_name = "WCD938X_AIF Capture",
  3633. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3634. .formats = WCD938X_FORMATS,
  3635. .rate_max = 192000,
  3636. .rate_min = 8000,
  3637. .channels_min = 1,
  3638. .channels_max = 4,
  3639. },
  3640. },
  3641. };
  3642. static int wcd938x_bind(struct device *dev)
  3643. {
  3644. int ret = 0, i = 0;
  3645. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3646. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3647. /*
  3648. * Add 5msec delay to provide sufficient time for
  3649. * soundwire auto enumeration of slave devices as
  3650. * as per HW requirement.
  3651. */
  3652. usleep_range(5000, 5010);
  3653. ret = component_bind_all(dev, wcd938x);
  3654. if (ret) {
  3655. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3656. __func__, ret);
  3657. return ret;
  3658. }
  3659. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3660. if (!wcd938x->rx_swr_dev) {
  3661. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3662. __func__);
  3663. ret = -ENODEV;
  3664. goto err;
  3665. }
  3666. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3667. if (!wcd938x->tx_swr_dev) {
  3668. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3669. __func__);
  3670. ret = -ENODEV;
  3671. goto err;
  3672. }
  3673. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3674. &wcd938x_regmap_config);
  3675. if (!wcd938x->regmap) {
  3676. dev_err(dev, "%s: Regmap init failed\n",
  3677. __func__);
  3678. goto err;
  3679. }
  3680. /* Set all interupts as edge triggered */
  3681. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3682. regmap_write(wcd938x->regmap,
  3683. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3684. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3685. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3686. wcd938x->irq_info.codec_name = "WCD938X";
  3687. wcd938x->irq_info.regmap = wcd938x->regmap;
  3688. wcd938x->irq_info.dev = dev;
  3689. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3690. if (ret) {
  3691. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3692. __func__, ret);
  3693. goto err;
  3694. }
  3695. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3696. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3697. if (ret < 0) {
  3698. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3699. goto err_irq;
  3700. }
  3701. /* Request for watchdog interrupt */
  3702. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3703. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3704. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3705. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3706. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3707. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3708. /* Disable watchdog interrupt for HPH and AUX */
  3709. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3710. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3711. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3712. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3713. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3714. if (ret) {
  3715. dev_err(dev, "%s: Codec registration failed\n",
  3716. __func__);
  3717. goto err_irq;
  3718. }
  3719. wcd938x->dev_up = true;
  3720. return ret;
  3721. err_irq:
  3722. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3723. err:
  3724. component_unbind_all(dev, wcd938x);
  3725. return ret;
  3726. }
  3727. static void wcd938x_unbind(struct device *dev)
  3728. {
  3729. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3730. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3731. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3732. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3733. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3734. snd_soc_unregister_component(dev);
  3735. component_unbind_all(dev, wcd938x);
  3736. }
  3737. static const struct of_device_id wcd938x_dt_match[] = {
  3738. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3739. {}
  3740. };
  3741. static const struct component_master_ops wcd938x_comp_ops = {
  3742. .bind = wcd938x_bind,
  3743. .unbind = wcd938x_unbind,
  3744. };
  3745. static int wcd938x_compare_of(struct device *dev, void *data)
  3746. {
  3747. return dev->of_node == data;
  3748. }
  3749. static void wcd938x_release_of(struct device *dev, void *data)
  3750. {
  3751. of_node_put(data);
  3752. }
  3753. static int wcd938x_add_slave_components(struct device *dev,
  3754. struct component_match **matchptr)
  3755. {
  3756. struct device_node *np, *rx_node, *tx_node;
  3757. np = dev->of_node;
  3758. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3759. if (!rx_node) {
  3760. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3761. return -ENODEV;
  3762. }
  3763. of_node_get(rx_node);
  3764. component_match_add_release(dev, matchptr,
  3765. wcd938x_release_of,
  3766. wcd938x_compare_of,
  3767. rx_node);
  3768. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3769. if (!tx_node) {
  3770. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3771. return -ENODEV;
  3772. }
  3773. of_node_get(tx_node);
  3774. component_match_add_release(dev, matchptr,
  3775. wcd938x_release_of,
  3776. wcd938x_compare_of,
  3777. tx_node);
  3778. return 0;
  3779. }
  3780. static int wcd938x_probe(struct platform_device *pdev)
  3781. {
  3782. struct component_match *match = NULL;
  3783. struct wcd938x_priv *wcd938x = NULL;
  3784. struct wcd938x_pdata *pdata = NULL;
  3785. struct wcd_ctrl_platform_data *plat_data = NULL;
  3786. struct device *dev = &pdev->dev;
  3787. int ret;
  3788. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3789. GFP_KERNEL);
  3790. if (!wcd938x)
  3791. return -ENOMEM;
  3792. dev_set_drvdata(dev, wcd938x);
  3793. wcd938x->dev = dev;
  3794. pdata = wcd938x_populate_dt_data(dev);
  3795. if (!pdata) {
  3796. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3797. return -EINVAL;
  3798. }
  3799. dev->platform_data = pdata;
  3800. wcd938x->rst_np = pdata->rst_np;
  3801. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3802. pdata->regulator, pdata->num_supplies);
  3803. if (!wcd938x->supplies) {
  3804. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3805. __func__);
  3806. return ret;
  3807. }
  3808. plat_data = dev_get_platdata(dev->parent);
  3809. if (!plat_data) {
  3810. dev_err(dev, "%s: platform data from parent is NULL\n",
  3811. __func__);
  3812. return -EINVAL;
  3813. }
  3814. wcd938x->handle = (void *)plat_data->handle;
  3815. if (!wcd938x->handle) {
  3816. dev_err(dev, "%s: handle is NULL\n", __func__);
  3817. return -EINVAL;
  3818. }
  3819. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3820. if (!wcd938x->update_wcd_event) {
  3821. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3822. __func__);
  3823. return -EINVAL;
  3824. }
  3825. wcd938x->register_notifier = plat_data->register_notifier;
  3826. if (!wcd938x->register_notifier) {
  3827. dev_err(dev, "%s: register_notifier api is null!\n",
  3828. __func__);
  3829. return -EINVAL;
  3830. }
  3831. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3832. pdata->regulator,
  3833. pdata->num_supplies);
  3834. if (ret) {
  3835. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3836. __func__);
  3837. return ret;
  3838. }
  3839. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3840. CODEC_RX);
  3841. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3842. CODEC_TX);
  3843. if (ret) {
  3844. dev_err(dev, "Failed to read port mapping\n");
  3845. goto err;
  3846. }
  3847. mutex_init(&wcd938x->wakeup_lock);
  3848. mutex_init(&wcd938x->micb_lock);
  3849. ret = wcd938x_add_slave_components(dev, &match);
  3850. if (ret)
  3851. goto err_lock_init;
  3852. wcd938x_reset(dev);
  3853. wcd938x->wakeup = wcd938x_wakeup;
  3854. return component_master_add_with_match(dev,
  3855. &wcd938x_comp_ops, match);
  3856. err_lock_init:
  3857. mutex_destroy(&wcd938x->micb_lock);
  3858. mutex_destroy(&wcd938x->wakeup_lock);
  3859. err:
  3860. return ret;
  3861. }
  3862. static int wcd938x_remove(struct platform_device *pdev)
  3863. {
  3864. struct wcd938x_priv *wcd938x = NULL;
  3865. wcd938x = platform_get_drvdata(pdev);
  3866. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3867. mutex_destroy(&wcd938x->micb_lock);
  3868. mutex_destroy(&wcd938x->wakeup_lock);
  3869. dev_set_drvdata(&pdev->dev, NULL);
  3870. return 0;
  3871. }
  3872. #ifdef CONFIG_PM_SLEEP
  3873. static int wcd938x_suspend(struct device *dev)
  3874. {
  3875. struct wcd938x_priv *wcd938x = NULL;
  3876. int ret = 0;
  3877. struct wcd938x_pdata *pdata = NULL;
  3878. if (!dev)
  3879. return -ENODEV;
  3880. wcd938x = dev_get_drvdata(dev);
  3881. if (!wcd938x)
  3882. return -EINVAL;
  3883. pdata = dev_get_platdata(wcd938x->dev);
  3884. if (!pdata) {
  3885. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3886. return -EINVAL;
  3887. }
  3888. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  3889. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  3890. wcd938x->supplies,
  3891. pdata->regulator,
  3892. pdata->num_supplies,
  3893. "cdc-vdd-buck");
  3894. if (ret == -EINVAL) {
  3895. dev_err(dev, "%s: vdd buck is not disabled\n",
  3896. __func__);
  3897. return 0;
  3898. }
  3899. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  3900. }
  3901. if (wcd938x->dapm_bias_off) {
  3902. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3903. wcd938x->supplies,
  3904. pdata->regulator,
  3905. pdata->num_supplies,
  3906. true);
  3907. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3908. }
  3909. return 0;
  3910. }
  3911. static int wcd938x_resume(struct device *dev)
  3912. {
  3913. struct wcd938x_priv *wcd938x = NULL;
  3914. struct wcd938x_pdata *pdata = NULL;
  3915. if (!dev)
  3916. return -ENODEV;
  3917. wcd938x = dev_get_drvdata(dev);
  3918. if (!wcd938x)
  3919. return -EINVAL;
  3920. pdata = dev_get_platdata(wcd938x->dev);
  3921. if (!pdata) {
  3922. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3923. return -EINVAL;
  3924. }
  3925. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  3926. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3927. wcd938x->supplies,
  3928. pdata->regulator,
  3929. pdata->num_supplies,
  3930. false);
  3931. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3932. }
  3933. return 0;
  3934. }
  3935. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3936. .suspend_late = wcd938x_suspend,
  3937. .resume_early = wcd938x_resume,
  3938. };
  3939. #endif
  3940. static struct platform_driver wcd938x_codec_driver = {
  3941. .probe = wcd938x_probe,
  3942. .remove = wcd938x_remove,
  3943. .driver = {
  3944. .name = "wcd938x_codec",
  3945. .owner = THIS_MODULE,
  3946. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3947. #ifdef CONFIG_PM_SLEEP
  3948. .pm = &wcd938x_dev_pm_ops,
  3949. #endif
  3950. .suppress_bind_attrs = true,
  3951. },
  3952. };
  3953. module_platform_driver(wcd938x_codec_driver);
  3954. MODULE_DESCRIPTION("WCD938X Codec driver");
  3955. MODULE_LICENSE("GPL v2");