08105d291d
Hardware files required to support TxMon. Change-Id: I7af4347cf90d590a0ac5467bd142d3a49ef712cb CRs-Fixed: 2262693
341 lines
24 KiB
C
341 lines
24 KiB
C
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_FES_STATUS_PROT_H_
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#define _TX_FES_STATUS_PROT_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "phytx_abort_request_info.h"
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#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14
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#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7
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struct tx_fes_status_prot {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t success : 1,
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phytx_pkt_end_info_valid : 1,
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phytx_abort_request_info_valid : 1,
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reserved_0 : 20,
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pkt_type : 4,
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dot11ax_su_extended : 1,
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rate_mcs : 4;
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uint32_t frame_type : 2,
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frame_subtype : 4,
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rx_pwr_mgmt : 1,
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status : 1,
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duration_field : 16,
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reserved_1a : 2,
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agc_cbw : 3,
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service_cbw : 3;
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uint32_t start_of_frame_timestamp_15_0 : 16,
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start_of_frame_timestamp_31_16 : 16;
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uint32_t end_of_frame_timestamp_15_0 : 16,
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end_of_frame_timestamp_31_16 : 16;
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uint32_t tx_group_delay : 12,
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timing_status : 2,
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dpdtrain_done : 1,
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reserved_4 : 1,
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transmit_delay : 16;
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uint32_t tpc_dbg_info_cmn_15_0 : 16,
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tpc_dbg_info_cmn_31_16 : 16;
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uint32_t tpc_dbg_info_cmn_47_32 : 16,
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tpc_dbg_info_chn1_15_0 : 16;
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uint32_t tpc_dbg_info_chn1_31_16 : 16,
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tpc_dbg_info_chn1_47_32 : 16;
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uint32_t tpc_dbg_info_chn1_63_48 : 16,
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tpc_dbg_info_chn1_79_64 : 16;
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uint32_t tpc_dbg_info_chn2_15_0 : 16,
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tpc_dbg_info_chn2_31_16 : 16;
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uint32_t tpc_dbg_info_chn2_47_32 : 16,
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tpc_dbg_info_chn2_63_48 : 16;
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uint32_t tpc_dbg_info_chn2_79_64 : 16;
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struct phytx_abort_request_info phytx_abort_request_info_details;
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uint32_t phytx_tx_end_sw_info_15_0 : 16,
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phytx_tx_end_sw_info_31_16 : 16;
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uint32_t phytx_tx_end_sw_info_47_32 : 16,
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phytx_tx_end_sw_info_63_48 : 16;
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#else
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uint32_t rate_mcs : 4,
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dot11ax_su_extended : 1,
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pkt_type : 4,
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reserved_0 : 20,
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phytx_abort_request_info_valid : 1,
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phytx_pkt_end_info_valid : 1,
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success : 1;
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uint32_t service_cbw : 3,
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agc_cbw : 3,
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reserved_1a : 2,
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duration_field : 16,
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status : 1,
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rx_pwr_mgmt : 1,
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frame_subtype : 4,
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frame_type : 2;
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uint32_t start_of_frame_timestamp_31_16 : 16,
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start_of_frame_timestamp_15_0 : 16;
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uint32_t end_of_frame_timestamp_31_16 : 16,
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end_of_frame_timestamp_15_0 : 16;
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uint32_t transmit_delay : 16,
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reserved_4 : 1,
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dpdtrain_done : 1,
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timing_status : 2,
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tx_group_delay : 12;
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uint32_t tpc_dbg_info_cmn_31_16 : 16,
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tpc_dbg_info_cmn_15_0 : 16;
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uint32_t tpc_dbg_info_chn1_15_0 : 16,
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tpc_dbg_info_cmn_47_32 : 16;
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uint32_t tpc_dbg_info_chn1_47_32 : 16,
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tpc_dbg_info_chn1_31_16 : 16;
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uint32_t tpc_dbg_info_chn1_79_64 : 16,
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tpc_dbg_info_chn1_63_48 : 16;
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uint32_t tpc_dbg_info_chn2_31_16 : 16,
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tpc_dbg_info_chn2_15_0 : 16;
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uint32_t tpc_dbg_info_chn2_63_48 : 16,
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tpc_dbg_info_chn2_47_32 : 16;
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struct phytx_abort_request_info phytx_abort_request_info_details;
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uint16_t tpc_dbg_info_chn2_79_64 : 16;
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uint32_t phytx_tx_end_sw_info_31_16 : 16,
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phytx_tx_end_sw_info_15_0 : 16;
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uint32_t phytx_tx_end_sw_info_63_48 : 16,
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phytx_tx_end_sw_info_47_32 : 16;
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#endif
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};
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#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_SUCCESS_LSB 0
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#define TX_FES_STATUS_PROT_SUCCESS_MSB 0
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#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001
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#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1
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#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1
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#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004
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#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3
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#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22
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#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8
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#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23
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#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26
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#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000
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#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27
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#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27
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#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000
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#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28
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#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31
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#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000
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#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32
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#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33
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#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000
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#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34
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#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37
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#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000
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#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38
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#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38
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#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000
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#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_STATUS_LSB 39
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#define TX_FES_STATUS_PROT_STATUS_MSB 39
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#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000
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#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40
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#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55
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#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000
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#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56
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#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57
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#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000
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#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58
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#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60
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#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000
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#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61
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#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63
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#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31
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#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63
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#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000
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#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0
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#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11
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#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff
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#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12
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#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13
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#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000
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#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14
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#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14
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#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000
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#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15
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#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15
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#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000
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#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16
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#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31
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#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47
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#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63
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#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63
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#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000
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#endif
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