dp_tx.c 93 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /* invalid peer id for reinject*/
  51. #define DP_INVALID_PEER 0XFFFE
  52. /*mapping between hal encrypt type and cdp_sec_type*/
  53. #define MAX_CDP_SEC_TYPE 12
  54. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  55. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  56. HAL_TX_ENCRYPT_TYPE_WEP_128,
  57. HAL_TX_ENCRYPT_TYPE_WEP_104,
  58. HAL_TX_ENCRYPT_TYPE_WEP_40,
  59. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  61. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_WAPI,
  63. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  64. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  66. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  67. /**
  68. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  69. * @vdev: DP Virtual device handle
  70. * @nbuf: Buffer pointer
  71. * @queue: queue ids container for nbuf
  72. *
  73. * TX packet queue has 2 instances, software descriptors id and dma ring id
  74. * Based on tx feature and hardware configuration queue id combination could be
  75. * different.
  76. * For example -
  77. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  78. * With no XPS,lock based resource protection, Descriptor pool ids are different
  79. * for each vdev, dma ring id will be same as single pdev id
  80. *
  81. * Return: None
  82. */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  167. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  170. qdf_atomic_dec(&pdev->num_tx_exception);
  171. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  172. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  173. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  174. else
  175. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  177. "Tx Completion Release desc %d status %d outstanding %d",
  178. tx_desc->id, comp_status,
  179. qdf_atomic_read(&pdev->num_tx_outstanding));
  180. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  181. return;
  182. }
  183. /**
  184. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  185. * @vdev: DP vdev Handle
  186. * @nbuf: skb
  187. *
  188. * Prepares and fills HTT metadata in the frame pre-header for special frames
  189. * that should be transmitted using varying transmit parameters.
  190. * There are 2 VDEV modes that currently needs this special metadata -
  191. * 1) Mesh Mode
  192. * 2) DSRC Mode
  193. *
  194. * Return: HTT metadata size
  195. *
  196. */
  197. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  198. uint32_t *meta_data)
  199. {
  200. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  201. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  202. uint8_t htt_desc_size;
  203. /* Size rounded of multiple of 8 bytes */
  204. uint8_t htt_desc_size_aligned;
  205. uint8_t *hdr = NULL;
  206. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  207. /*
  208. * Metadata - HTT MSDU Extension header
  209. */
  210. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  211. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  212. if (vdev->mesh_vdev) {
  213. /* Fill and add HTT metaheader */
  214. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  215. if (hdr == NULL) {
  216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  217. "Error in filling HTT metadata\n");
  218. return 0;
  219. }
  220. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  221. } else if (vdev->opmode == wlan_op_mode_ocb) {
  222. /* Todo - Add support for DSRC */
  223. }
  224. return htt_desc_size_aligned;
  225. }
  226. /**
  227. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  228. * @tso_seg: TSO segment to process
  229. * @ext_desc: Pointer to MSDU extension descriptor
  230. *
  231. * Return: void
  232. */
  233. #if defined(FEATURE_TSO)
  234. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  235. void *ext_desc)
  236. {
  237. uint8_t num_frag;
  238. uint32_t tso_flags;
  239. /*
  240. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  241. * tcp_flag_mask
  242. *
  243. * Checksum enable flags are set in TCL descriptor and not in Extension
  244. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  245. */
  246. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  247. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  248. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  249. tso_seg->tso_flags.ip_len);
  250. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  251. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  252. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  253. uint32_t lo = 0;
  254. uint32_t hi = 0;
  255. qdf_dmaaddr_to_32s(
  256. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  257. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  258. tso_seg->tso_frags[num_frag].length);
  259. }
  260. return;
  261. }
  262. #else
  263. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  264. void *ext_desc)
  265. {
  266. return;
  267. }
  268. #endif
  269. #if defined(FEATURE_TSO)
  270. /**
  271. * dp_tx_free_tso_seg() - Loop through the tso segments
  272. * allocated and free them
  273. *
  274. * @soc: soc handle
  275. * @free_seg: list of tso segments
  276. * @msdu_info: msdu descriptor
  277. *
  278. * Return - void
  279. */
  280. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  281. struct qdf_tso_seg_elem_t *free_seg,
  282. struct dp_tx_msdu_info_s *msdu_info)
  283. {
  284. struct qdf_tso_seg_elem_t *next_seg;
  285. while (free_seg) {
  286. next_seg = free_seg->next;
  287. dp_tx_tso_desc_free(soc,
  288. msdu_info->tx_queue.desc_pool_id,
  289. free_seg);
  290. free_seg = next_seg;
  291. }
  292. }
  293. /**
  294. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  295. * allocated and free them
  296. *
  297. * @soc: soc handle
  298. * @free_seg: list of tso segments
  299. * @msdu_info: msdu descriptor
  300. * Return - void
  301. */
  302. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  303. struct qdf_tso_num_seg_elem_t *free_seg,
  304. struct dp_tx_msdu_info_s *msdu_info)
  305. {
  306. struct qdf_tso_num_seg_elem_t *next_seg;
  307. while (free_seg) {
  308. next_seg = free_seg->next;
  309. dp_tso_num_seg_free(soc,
  310. msdu_info->tx_queue.desc_pool_id,
  311. free_seg);
  312. free_seg = next_seg;
  313. }
  314. }
  315. /**
  316. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  317. * @vdev: virtual device handle
  318. * @msdu: network buffer
  319. * @msdu_info: meta data associated with the msdu
  320. *
  321. * Return: QDF_STATUS_SUCCESS success
  322. */
  323. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  324. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  325. {
  326. struct qdf_tso_seg_elem_t *tso_seg;
  327. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  328. struct dp_soc *soc = vdev->pdev->soc;
  329. struct qdf_tso_info_t *tso_info;
  330. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  331. tso_info = &msdu_info->u.tso_info;
  332. tso_info->curr_seg = NULL;
  333. tso_info->tso_seg_list = NULL;
  334. tso_info->num_segs = num_seg;
  335. msdu_info->frm_type = dp_tx_frm_tso;
  336. tso_info->tso_num_seg_list = NULL;
  337. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  338. while (num_seg) {
  339. tso_seg = dp_tx_tso_desc_alloc(
  340. soc, msdu_info->tx_queue.desc_pool_id);
  341. if (tso_seg) {
  342. tso_seg->next = tso_info->tso_seg_list;
  343. tso_info->tso_seg_list = tso_seg;
  344. num_seg--;
  345. } else {
  346. struct qdf_tso_seg_elem_t *free_seg =
  347. tso_info->tso_seg_list;
  348. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  349. return QDF_STATUS_E_NOMEM;
  350. }
  351. }
  352. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  353. tso_num_seg = dp_tso_num_seg_alloc(soc,
  354. msdu_info->tx_queue.desc_pool_id);
  355. if (tso_num_seg) {
  356. tso_num_seg->next = tso_info->tso_num_seg_list;
  357. tso_info->tso_num_seg_list = tso_num_seg;
  358. } else {
  359. /* Bug: free tso_num_seg and tso_seg */
  360. /* Free the already allocated num of segments */
  361. struct qdf_tso_seg_elem_t *free_seg =
  362. tso_info->tso_seg_list;
  363. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  364. __func__);
  365. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  366. return QDF_STATUS_E_NOMEM;
  367. }
  368. msdu_info->num_seg =
  369. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  370. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  371. msdu_info->num_seg);
  372. if (!(msdu_info->num_seg)) {
  373. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  374. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  375. msdu_info);
  376. return QDF_STATUS_E_INVAL;
  377. }
  378. tso_info->curr_seg = tso_info->tso_seg_list;
  379. return QDF_STATUS_SUCCESS;
  380. }
  381. #else
  382. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  383. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. return QDF_STATUS_E_NOMEM;
  386. }
  387. #endif
  388. /**
  389. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  390. * @vdev: DP Vdev handle
  391. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  392. * @desc_pool_id: Descriptor Pool ID
  393. *
  394. * Return:
  395. */
  396. static
  397. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  398. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  399. {
  400. uint8_t i;
  401. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  402. struct dp_tx_seg_info_s *seg_info;
  403. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  404. struct dp_soc *soc = vdev->pdev->soc;
  405. /* Allocate an extension descriptor */
  406. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  407. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  408. if (!msdu_ext_desc) {
  409. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  410. return NULL;
  411. }
  412. if (msdu_info->exception_fw &&
  413. qdf_unlikely(vdev->mesh_vdev)) {
  414. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  415. &msdu_info->meta_data[0],
  416. sizeof(struct htt_tx_msdu_desc_ext2_t));
  417. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  418. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  419. }
  420. switch (msdu_info->frm_type) {
  421. case dp_tx_frm_sg:
  422. case dp_tx_frm_me:
  423. case dp_tx_frm_raw:
  424. seg_info = msdu_info->u.sg_info.curr_seg;
  425. /* Update the buffer pointers in MSDU Extension Descriptor */
  426. for (i = 0; i < seg_info->frag_cnt; i++) {
  427. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  428. seg_info->frags[i].paddr_lo,
  429. seg_info->frags[i].paddr_hi,
  430. seg_info->frags[i].len);
  431. }
  432. break;
  433. case dp_tx_frm_tso:
  434. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  435. &cached_ext_desc[0]);
  436. break;
  437. default:
  438. break;
  439. }
  440. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  441. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  442. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  443. msdu_ext_desc->vaddr);
  444. return msdu_ext_desc;
  445. }
  446. /**
  447. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  448. * @vdev: DP vdev handle
  449. * @nbuf: skb
  450. * @desc_pool_id: Descriptor pool ID
  451. * @meta_data: Metadata to the fw
  452. * @tx_exc_metadata: Handle that holds exception path metadata
  453. * Allocate and prepare Tx descriptor with msdu information.
  454. *
  455. * Return: Pointer to Tx Descriptor on success,
  456. * NULL on failure
  457. */
  458. static
  459. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  460. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  461. struct dp_tx_msdu_info_s *msdu_info,
  462. struct cdp_tx_exception_metadata *tx_exc_metadata)
  463. {
  464. uint8_t align_pad;
  465. uint8_t is_exception = 0;
  466. uint8_t htt_hdr_size;
  467. struct ether_header *eh;
  468. struct dp_tx_desc_s *tx_desc;
  469. struct dp_pdev *pdev = vdev->pdev;
  470. struct dp_soc *soc = pdev->soc;
  471. /* Allocate software Tx descriptor */
  472. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  473. if (qdf_unlikely(!tx_desc)) {
  474. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  475. return NULL;
  476. }
  477. /* Flow control/Congestion Control counters */
  478. qdf_atomic_inc(&pdev->num_tx_outstanding);
  479. /* Initialize the SW tx descriptor */
  480. tx_desc->nbuf = nbuf;
  481. tx_desc->frm_type = dp_tx_frm_std;
  482. tx_desc->tx_encap_type = (tx_exc_metadata ?
  483. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  484. tx_desc->vdev = vdev;
  485. tx_desc->pdev = pdev;
  486. tx_desc->msdu_ext_desc = NULL;
  487. tx_desc->pkt_offset = 0;
  488. /*
  489. * For special modes (vdev_type == ocb or mesh), data frames should be
  490. * transmitted using varying transmit parameters (tx spec) which include
  491. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  492. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  493. * These frames are sent as exception packets to firmware.
  494. *
  495. * HW requirement is that metadata should always point to a
  496. * 8-byte aligned address. So we add alignment pad to start of buffer.
  497. * HTT Metadata should be ensured to be multiple of 8-bytes,
  498. * to get 8-byte aligned start address along with align_pad added
  499. *
  500. * |-----------------------------|
  501. * | |
  502. * |-----------------------------| <-----Buffer Pointer Address given
  503. * | | ^ in HW descriptor (aligned)
  504. * | HTT Metadata | |
  505. * | | |
  506. * | | | Packet Offset given in descriptor
  507. * | | |
  508. * |-----------------------------| |
  509. * | Alignment Pad | v
  510. * |-----------------------------| <----- Actual buffer start address
  511. * | SKB Data | (Unaligned)
  512. * | |
  513. * | |
  514. * | |
  515. * | |
  516. * | |
  517. * |-----------------------------|
  518. */
  519. if (qdf_unlikely((msdu_info->exception_fw)) ||
  520. (vdev->opmode == wlan_op_mode_ocb)) {
  521. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  522. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  524. "qdf_nbuf_push_head failed\n");
  525. goto failure;
  526. }
  527. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  528. msdu_info->meta_data);
  529. if (htt_hdr_size == 0)
  530. goto failure;
  531. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  532. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  533. is_exception = 1;
  534. }
  535. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  536. qdf_nbuf_map(soc->osdev, nbuf,
  537. QDF_DMA_TO_DEVICE))) {
  538. /* Handle failure */
  539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  540. "qdf_nbuf_map failed\n");
  541. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  542. goto failure;
  543. }
  544. if (qdf_unlikely(vdev->nawds_enabled)) {
  545. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  546. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  547. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  548. is_exception = 1;
  549. }
  550. }
  551. #if !TQM_BYPASS_WAR
  552. if (is_exception || tx_exc_metadata)
  553. #endif
  554. {
  555. /* Temporary WAR due to TQM VP issues */
  556. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  557. qdf_atomic_inc(&pdev->num_tx_exception);
  558. }
  559. return tx_desc;
  560. failure:
  561. dp_tx_desc_release(tx_desc, desc_pool_id);
  562. return NULL;
  563. }
  564. /**
  565. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  566. * @vdev: DP vdev handle
  567. * @nbuf: skb
  568. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  569. * @desc_pool_id : Descriptor Pool ID
  570. *
  571. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  572. * information. For frames wth fragments, allocate and prepare
  573. * an MSDU extension descriptor
  574. *
  575. * Return: Pointer to Tx Descriptor on success,
  576. * NULL on failure
  577. */
  578. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  579. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  580. uint8_t desc_pool_id)
  581. {
  582. struct dp_tx_desc_s *tx_desc;
  583. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  584. struct dp_pdev *pdev = vdev->pdev;
  585. struct dp_soc *soc = pdev->soc;
  586. /* Allocate software Tx descriptor */
  587. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  588. if (!tx_desc) {
  589. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  590. return NULL;
  591. }
  592. /* Flow control/Congestion Control counters */
  593. qdf_atomic_inc(&pdev->num_tx_outstanding);
  594. /* Initialize the SW tx descriptor */
  595. tx_desc->nbuf = nbuf;
  596. tx_desc->frm_type = msdu_info->frm_type;
  597. tx_desc->tx_encap_type = vdev->tx_encap_type;
  598. tx_desc->vdev = vdev;
  599. tx_desc->pdev = pdev;
  600. tx_desc->pkt_offset = 0;
  601. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  602. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  603. /* Handle scattered frames - TSO/SG/ME */
  604. /* Allocate and prepare an extension descriptor for scattered frames */
  605. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  606. if (!msdu_ext_desc) {
  607. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  608. "%s Tx Extension Descriptor Alloc Fail\n",
  609. __func__);
  610. goto failure;
  611. }
  612. #if TQM_BYPASS_WAR
  613. /* Temporary WAR due to TQM VP issues */
  614. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  615. qdf_atomic_inc(&pdev->num_tx_exception);
  616. #endif
  617. if (qdf_unlikely(msdu_info->exception_fw))
  618. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  619. tx_desc->msdu_ext_desc = msdu_ext_desc;
  620. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  621. return tx_desc;
  622. failure:
  623. dp_tx_desc_release(tx_desc, desc_pool_id);
  624. return NULL;
  625. }
  626. /**
  627. * dp_tx_prepare_raw() - Prepare RAW packet TX
  628. * @vdev: DP vdev handle
  629. * @nbuf: buffer pointer
  630. * @seg_info: Pointer to Segment info Descriptor to be prepared
  631. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  632. * descriptor
  633. *
  634. * Return:
  635. */
  636. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  637. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  638. {
  639. qdf_nbuf_t curr_nbuf = NULL;
  640. uint16_t total_len = 0;
  641. qdf_dma_addr_t paddr;
  642. int32_t i;
  643. int32_t mapped_buf_num = 0;
  644. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  645. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  646. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  647. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  648. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  649. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  650. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  651. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  652. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  653. QDF_DMA_TO_DEVICE)) {
  654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  655. "%s dma map error \n", __func__);
  656. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  657. mapped_buf_num = i;
  658. goto error;
  659. }
  660. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  661. seg_info->frags[i].paddr_lo = paddr;
  662. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  663. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  664. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  665. total_len += qdf_nbuf_len(curr_nbuf);
  666. }
  667. seg_info->frag_cnt = i;
  668. seg_info->total_len = total_len;
  669. seg_info->next = NULL;
  670. sg_info->curr_seg = seg_info;
  671. msdu_info->frm_type = dp_tx_frm_raw;
  672. msdu_info->num_seg = 1;
  673. return nbuf;
  674. error:
  675. i = 0;
  676. while (nbuf) {
  677. curr_nbuf = nbuf;
  678. if (i < mapped_buf_num) {
  679. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  680. i++;
  681. }
  682. nbuf = qdf_nbuf_next(nbuf);
  683. qdf_nbuf_free(curr_nbuf);
  684. }
  685. return NULL;
  686. }
  687. /**
  688. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  689. * @soc: DP Soc Handle
  690. * @vdev: DP vdev handle
  691. * @tx_desc: Tx Descriptor Handle
  692. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  693. * @fw_metadata: Metadata to send to Target Firmware along with frame
  694. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  695. * @tx_exc_metadata: Handle that holds exception path meta data
  696. *
  697. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  698. * from software Tx descriptor
  699. *
  700. * Return:
  701. */
  702. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  703. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  704. uint16_t fw_metadata, uint8_t ring_id,
  705. struct cdp_tx_exception_metadata
  706. *tx_exc_metadata)
  707. {
  708. uint8_t type;
  709. uint16_t length;
  710. void *hal_tx_desc, *hal_tx_desc_cached;
  711. qdf_dma_addr_t dma_addr;
  712. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  713. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  714. tx_exc_metadata->sec_type : vdev->sec_type);
  715. /* Return Buffer Manager ID */
  716. uint8_t bm_id = ring_id;
  717. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  718. hal_tx_desc_cached = (void *) cached_desc;
  719. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  720. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  721. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  722. type = HAL_TX_BUF_TYPE_EXT_DESC;
  723. dma_addr = tx_desc->msdu_ext_desc->paddr;
  724. } else {
  725. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  726. type = HAL_TX_BUF_TYPE_BUFFER;
  727. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  728. }
  729. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  730. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  731. dma_addr , bm_id, tx_desc->id, type);
  732. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  733. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  734. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  735. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  736. vdev->dscp_tid_map_id);
  737. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  738. sec_type_map[sec_type]);
  739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  740. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  741. __func__, length, type, (uint64_t)dma_addr,
  742. tx_desc->pkt_offset, tx_desc->id);
  743. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  744. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  745. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  746. vdev->hal_desc_addr_search_flags);
  747. /* verify checksum offload configuration*/
  748. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  749. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  750. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  751. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  752. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  753. }
  754. if (tid != HTT_TX_EXT_TID_INVALID)
  755. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  756. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  757. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  758. /* Sync cached descriptor with HW */
  759. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  760. if (!hal_tx_desc) {
  761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  762. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  763. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  764. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  765. return QDF_STATUS_E_RESOURCES;
  766. }
  767. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  768. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  769. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  770. /*
  771. * If one packet is enqueued in HW, PM usage count needs to be
  772. * incremented by one to prevent future runtime suspend. This
  773. * should be tied with the success of enqueuing. It will be
  774. * decremented after the packet has been sent.
  775. */
  776. hif_pm_runtime_get_noresume(soc->hif_handle);
  777. return QDF_STATUS_SUCCESS;
  778. }
  779. /**
  780. * dp_cce_classify() - Classify the frame based on CCE rules
  781. * @vdev: DP vdev handle
  782. * @nbuf: skb
  783. *
  784. * Classify frames based on CCE rules
  785. * Return: bool( true if classified,
  786. * else false)
  787. */
  788. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  789. {
  790. struct ether_header *eh = NULL;
  791. uint16_t ether_type;
  792. qdf_llc_t *llcHdr;
  793. qdf_nbuf_t nbuf_clone = NULL;
  794. qdf_dot3_qosframe_t *qos_wh = NULL;
  795. /* for mesh packets don't do any classification */
  796. if (qdf_unlikely(vdev->mesh_vdev))
  797. return false;
  798. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  799. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  800. ether_type = eh->ether_type;
  801. llcHdr = (qdf_llc_t *)(nbuf->data +
  802. sizeof(struct ether_header));
  803. } else {
  804. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  805. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  806. if (qdf_unlikely(
  807. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  808. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  809. ether_type = *(uint16_t *)(nbuf->data
  810. + QDF_IEEE80211_4ADDR_HDR_LEN
  811. + sizeof(qdf_llc_t)
  812. - sizeof(ether_type));
  813. llcHdr = (qdf_llc_t *)(nbuf->data +
  814. QDF_IEEE80211_4ADDR_HDR_LEN);
  815. } else {
  816. ether_type = *(uint16_t *)(nbuf->data
  817. + QDF_IEEE80211_3ADDR_HDR_LEN
  818. + sizeof(qdf_llc_t)
  819. - sizeof(ether_type));
  820. llcHdr = (qdf_llc_t *)(nbuf->data +
  821. QDF_IEEE80211_3ADDR_HDR_LEN);
  822. }
  823. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  824. && (ether_type ==
  825. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  826. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  827. return true;
  828. }
  829. }
  830. return false;
  831. }
  832. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  833. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  834. sizeof(*llcHdr));
  835. nbuf_clone = qdf_nbuf_clone(nbuf);
  836. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  837. if (ether_type == htons(ETHERTYPE_8021Q)) {
  838. qdf_nbuf_pull_head(nbuf_clone,
  839. sizeof(qdf_net_vlanhdr_t));
  840. }
  841. } else {
  842. if (ether_type == htons(ETHERTYPE_8021Q)) {
  843. nbuf_clone = qdf_nbuf_clone(nbuf);
  844. qdf_nbuf_pull_head(nbuf_clone,
  845. sizeof(qdf_net_vlanhdr_t));
  846. }
  847. }
  848. if (qdf_unlikely(nbuf_clone))
  849. nbuf = nbuf_clone;
  850. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  851. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  852. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  853. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  854. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  855. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  856. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  857. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  858. if (qdf_unlikely(nbuf_clone != NULL))
  859. qdf_nbuf_free(nbuf_clone);
  860. return true;
  861. }
  862. if (qdf_unlikely(nbuf_clone != NULL))
  863. qdf_nbuf_free(nbuf_clone);
  864. return false;
  865. }
  866. /**
  867. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  868. * @vdev: DP vdev handle
  869. * @nbuf: skb
  870. *
  871. * Extract the DSCP or PCP information from frame and map into TID value.
  872. * Software based TID classification is required when more than 2 DSCP-TID
  873. * mapping tables are needed.
  874. * Hardware supports 2 DSCP-TID mapping tables
  875. *
  876. * Return: void
  877. */
  878. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  879. struct dp_tx_msdu_info_s *msdu_info)
  880. {
  881. uint8_t tos = 0, dscp_tid_override = 0;
  882. uint8_t *hdr_ptr, *L3datap;
  883. uint8_t is_mcast = 0;
  884. struct ether_header *eh = NULL;
  885. qdf_ethervlan_header_t *evh = NULL;
  886. uint16_t ether_type;
  887. qdf_llc_t *llcHdr;
  888. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  889. /* for mesh packets don't do any classification */
  890. if (qdf_unlikely(vdev->mesh_vdev))
  891. return;
  892. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  893. eh = (struct ether_header *) nbuf->data;
  894. hdr_ptr = eh->ether_dhost;
  895. L3datap = hdr_ptr + sizeof(struct ether_header);
  896. } else {
  897. qdf_dot3_qosframe_t *qos_wh =
  898. (qdf_dot3_qosframe_t *) nbuf->data;
  899. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  900. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  901. return;
  902. }
  903. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  904. ether_type = eh->ether_type;
  905. /*
  906. * Check if packet is dot3 or eth2 type.
  907. */
  908. if (IS_LLC_PRESENT(ether_type)) {
  909. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  910. sizeof(*llcHdr));
  911. if (ether_type == htons(ETHERTYPE_8021Q)) {
  912. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  913. sizeof(*llcHdr);
  914. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  915. + sizeof(*llcHdr) +
  916. sizeof(qdf_net_vlanhdr_t));
  917. } else {
  918. L3datap = hdr_ptr + sizeof(struct ether_header) +
  919. sizeof(*llcHdr);
  920. }
  921. } else {
  922. if (ether_type == htons(ETHERTYPE_8021Q)) {
  923. evh = (qdf_ethervlan_header_t *) eh;
  924. ether_type = evh->ether_type;
  925. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  926. }
  927. }
  928. /*
  929. * Find priority from IP TOS DSCP field
  930. */
  931. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  932. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  933. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  934. /* Only for unicast frames */
  935. if (!is_mcast) {
  936. /* send it on VO queue */
  937. msdu_info->tid = DP_VO_TID;
  938. }
  939. } else {
  940. /*
  941. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  942. * from TOS byte.
  943. */
  944. tos = ip->ip_tos;
  945. dscp_tid_override = 1;
  946. }
  947. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  948. /* TODO
  949. * use flowlabel
  950. *igmpmld cases to be handled in phase 2
  951. */
  952. unsigned long ver_pri_flowlabel;
  953. unsigned long pri;
  954. ver_pri_flowlabel = *(unsigned long *) L3datap;
  955. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  956. DP_IPV6_PRIORITY_SHIFT;
  957. tos = pri;
  958. dscp_tid_override = 1;
  959. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  960. msdu_info->tid = DP_VO_TID;
  961. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  962. /* Only for unicast frames */
  963. if (!is_mcast) {
  964. /* send ucast arp on VO queue */
  965. msdu_info->tid = DP_VO_TID;
  966. }
  967. }
  968. /*
  969. * Assign all MCAST packets to BE
  970. */
  971. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  972. if (is_mcast) {
  973. tos = 0;
  974. dscp_tid_override = 1;
  975. }
  976. }
  977. if (dscp_tid_override == 1) {
  978. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  979. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  980. }
  981. return;
  982. }
  983. #ifdef CONVERGED_TDLS_ENABLE
  984. /**
  985. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  986. * @tx_desc: TX descriptor
  987. *
  988. * Return: None
  989. */
  990. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  991. {
  992. if (tx_desc->vdev) {
  993. if (tx_desc->vdev->is_tdls_frame)
  994. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  995. tx_desc->vdev->is_tdls_frame = false;
  996. }
  997. }
  998. /**
  999. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1000. * @tx_desc: TX descriptor
  1001. * @vdev: datapath vdev handle
  1002. *
  1003. * Return: None
  1004. */
  1005. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1006. struct dp_vdev *vdev)
  1007. {
  1008. struct hal_tx_completion_status ts = {0};
  1009. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1010. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1011. if (vdev->tx_non_std_data_callback.func) {
  1012. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1013. vdev->tx_non_std_data_callback.func(
  1014. vdev->tx_non_std_data_callback.ctxt,
  1015. nbuf, ts.status);
  1016. return;
  1017. }
  1018. }
  1019. #endif
  1020. /**
  1021. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1022. * @vdev: DP vdev handle
  1023. * @nbuf: skb
  1024. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1025. * @meta_data: Metadata to the fw
  1026. * @tx_q: Tx queue to be used for this Tx frame
  1027. * @peer_id: peer_id of the peer in case of NAWDS frames
  1028. * @tx_exc_metadata: Handle that holds exception path metadata
  1029. *
  1030. * Return: NULL on success,
  1031. * nbuf when it fails to send
  1032. */
  1033. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1034. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1035. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1036. {
  1037. struct dp_pdev *pdev = vdev->pdev;
  1038. struct dp_soc *soc = pdev->soc;
  1039. struct dp_tx_desc_s *tx_desc;
  1040. QDF_STATUS status;
  1041. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1042. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1043. uint16_t htt_tcl_metadata = 0;
  1044. uint8_t tid = msdu_info->tid;
  1045. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  1046. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1047. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1048. msdu_info, tx_exc_metadata);
  1049. if (!tx_desc) {
  1050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1051. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1052. __func__, vdev, tx_q->desc_pool_id);
  1053. return nbuf;
  1054. }
  1055. if (qdf_unlikely(soc->cce_disable)) {
  1056. if (dp_cce_classify(vdev, nbuf) == true) {
  1057. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1058. tid = DP_VO_TID;
  1059. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1060. }
  1061. }
  1062. dp_tx_update_tdls_flags(tx_desc);
  1063. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1064. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1065. "%s %d : HAL RING Access Failed -- %pK\n",
  1066. __func__, __LINE__, hal_srng);
  1067. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1068. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1069. goto fail_return;
  1070. }
  1071. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1072. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1073. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1074. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1075. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1076. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1077. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1078. peer_id);
  1079. } else
  1080. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1081. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1082. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1083. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1084. if (status != QDF_STATUS_SUCCESS) {
  1085. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1086. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1087. __func__, tx_desc, tx_q->ring_id);
  1088. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1089. goto fail_return;
  1090. }
  1091. nbuf = NULL;
  1092. fail_return:
  1093. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1094. hal_srng_access_end(soc->hal_soc, hal_srng);
  1095. hif_pm_runtime_put(soc->hif_handle);
  1096. } else {
  1097. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1098. }
  1099. return nbuf;
  1100. }
  1101. /**
  1102. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1103. * @vdev: DP vdev handle
  1104. * @nbuf: skb
  1105. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1106. *
  1107. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1108. *
  1109. * Return: NULL on success,
  1110. * nbuf when it fails to send
  1111. */
  1112. #if QDF_LOCK_STATS
  1113. static noinline
  1114. #else
  1115. static
  1116. #endif
  1117. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1118. struct dp_tx_msdu_info_s *msdu_info)
  1119. {
  1120. uint8_t i;
  1121. struct dp_pdev *pdev = vdev->pdev;
  1122. struct dp_soc *soc = pdev->soc;
  1123. struct dp_tx_desc_s *tx_desc;
  1124. bool is_cce_classified = false;
  1125. QDF_STATUS status;
  1126. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1127. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1128. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1129. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1130. "%s %d : HAL RING Access Failed -- %pK\n",
  1131. __func__, __LINE__, hal_srng);
  1132. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1133. return nbuf;
  1134. }
  1135. if (qdf_unlikely(soc->cce_disable)) {
  1136. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1137. if (is_cce_classified) {
  1138. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1139. msdu_info->tid = DP_VO_TID;
  1140. }
  1141. }
  1142. if (msdu_info->frm_type == dp_tx_frm_me)
  1143. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1144. i = 0;
  1145. /* Print statement to track i and num_seg */
  1146. /*
  1147. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1148. * descriptors using information in msdu_info
  1149. */
  1150. while (i < msdu_info->num_seg) {
  1151. /*
  1152. * Setup Tx descriptor for an MSDU, and MSDU extension
  1153. * descriptor
  1154. */
  1155. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1156. tx_q->desc_pool_id);
  1157. if (!tx_desc) {
  1158. if (msdu_info->frm_type == dp_tx_frm_me) {
  1159. dp_tx_me_free_buf(pdev,
  1160. (void *)(msdu_info->u.sg_info
  1161. .curr_seg->frags[0].vaddr));
  1162. }
  1163. goto done;
  1164. }
  1165. if (msdu_info->frm_type == dp_tx_frm_me) {
  1166. tx_desc->me_buffer =
  1167. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1168. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1169. }
  1170. if (is_cce_classified)
  1171. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1172. /*
  1173. * Enqueue the Tx MSDU descriptor to HW for transmit
  1174. */
  1175. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1176. vdev->htt_tcl_metadata, tx_q->ring_id, NULL);
  1177. if (status != QDF_STATUS_SUCCESS) {
  1178. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1179. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1180. __func__, tx_desc, tx_q->ring_id);
  1181. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1182. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1183. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1184. goto done;
  1185. }
  1186. /*
  1187. * TODO
  1188. * if tso_info structure can be modified to have curr_seg
  1189. * as first element, following 2 blocks of code (for TSO and SG)
  1190. * can be combined into 1
  1191. */
  1192. /*
  1193. * For frames with multiple segments (TSO, ME), jump to next
  1194. * segment.
  1195. */
  1196. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1197. if (msdu_info->u.tso_info.curr_seg->next) {
  1198. msdu_info->u.tso_info.curr_seg =
  1199. msdu_info->u.tso_info.curr_seg->next;
  1200. /*
  1201. * If this is a jumbo nbuf, then increment the number of
  1202. * nbuf users for each additional segment of the msdu.
  1203. * This will ensure that the skb is freed only after
  1204. * receiving tx completion for all segments of an nbuf
  1205. */
  1206. qdf_nbuf_inc_users(nbuf);
  1207. /* Check with MCL if this is needed */
  1208. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1209. }
  1210. }
  1211. /*
  1212. * For Multicast-Unicast converted packets,
  1213. * each converted frame (for a client) is represented as
  1214. * 1 segment
  1215. */
  1216. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1217. (msdu_info->frm_type == dp_tx_frm_me)) {
  1218. if (msdu_info->u.sg_info.curr_seg->next) {
  1219. msdu_info->u.sg_info.curr_seg =
  1220. msdu_info->u.sg_info.curr_seg->next;
  1221. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1222. }
  1223. }
  1224. i++;
  1225. }
  1226. nbuf = NULL;
  1227. done:
  1228. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1229. hal_srng_access_end(soc->hal_soc, hal_srng);
  1230. hif_pm_runtime_put(soc->hif_handle);
  1231. } else {
  1232. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1233. }
  1234. return nbuf;
  1235. }
  1236. /**
  1237. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1238. * for SG frames
  1239. * @vdev: DP vdev handle
  1240. * @nbuf: skb
  1241. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1242. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1243. *
  1244. * Return: NULL on success,
  1245. * nbuf when it fails to send
  1246. */
  1247. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1248. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1249. {
  1250. uint32_t cur_frag, nr_frags;
  1251. qdf_dma_addr_t paddr;
  1252. struct dp_tx_sg_info_s *sg_info;
  1253. sg_info = &msdu_info->u.sg_info;
  1254. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1255. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1256. QDF_DMA_TO_DEVICE)) {
  1257. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1258. "dma map error\n");
  1259. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1260. qdf_nbuf_free(nbuf);
  1261. return NULL;
  1262. }
  1263. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1264. seg_info->frags[0].paddr_lo = paddr;
  1265. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1266. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1267. seg_info->frags[0].vaddr = (void *) nbuf;
  1268. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1269. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1270. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1271. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1272. "frag dma map error\n");
  1273. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1274. qdf_nbuf_free(nbuf);
  1275. return NULL;
  1276. }
  1277. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1278. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1279. seg_info->frags[cur_frag + 1].paddr_hi =
  1280. ((uint64_t) paddr) >> 32;
  1281. seg_info->frags[cur_frag + 1].len =
  1282. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1283. }
  1284. seg_info->frag_cnt = (cur_frag + 1);
  1285. seg_info->total_len = qdf_nbuf_len(nbuf);
  1286. seg_info->next = NULL;
  1287. sg_info->curr_seg = seg_info;
  1288. msdu_info->frm_type = dp_tx_frm_sg;
  1289. msdu_info->num_seg = 1;
  1290. return nbuf;
  1291. }
  1292. #ifdef MESH_MODE_SUPPORT
  1293. /**
  1294. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1295. and prepare msdu_info for mesh frames.
  1296. * @vdev: DP vdev handle
  1297. * @nbuf: skb
  1298. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1299. *
  1300. * Return: NULL on failure,
  1301. * nbuf when extracted successfully
  1302. */
  1303. static
  1304. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1305. struct dp_tx_msdu_info_s *msdu_info)
  1306. {
  1307. struct meta_hdr_s *mhdr;
  1308. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1309. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1310. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1311. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1312. msdu_info->exception_fw = 0;
  1313. goto remove_meta_hdr;
  1314. }
  1315. msdu_info->exception_fw = 1;
  1316. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1317. meta_data->host_tx_desc_pool = 1;
  1318. meta_data->update_peer_cache = 1;
  1319. meta_data->learning_frame = 1;
  1320. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1321. meta_data->power = mhdr->power;
  1322. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1323. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1324. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1325. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1326. meta_data->dyn_bw = 1;
  1327. meta_data->valid_pwr = 1;
  1328. meta_data->valid_mcs_mask = 1;
  1329. meta_data->valid_nss_mask = 1;
  1330. meta_data->valid_preamble_type = 1;
  1331. meta_data->valid_retries = 1;
  1332. meta_data->valid_bw_info = 1;
  1333. }
  1334. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1335. meta_data->encrypt_type = 0;
  1336. meta_data->valid_encrypt_type = 1;
  1337. }
  1338. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1339. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1340. else
  1341. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1342. meta_data->valid_key_flags = 1;
  1343. meta_data->key_flags = (mhdr->keyix & 0x3);
  1344. remove_meta_hdr:
  1345. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1346. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1347. "qdf_nbuf_pull_head failed\n");
  1348. qdf_nbuf_free(nbuf);
  1349. return NULL;
  1350. }
  1351. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1352. "%s , Meta hdr %0x %0x %0x %0x %0x to_fw %d\n",
  1353. __func__, msdu_info->meta_data[0],
  1354. msdu_info->meta_data[1],
  1355. msdu_info->meta_data[2],
  1356. msdu_info->meta_data[3],
  1357. msdu_info->meta_data[4], msdu_info->exception_fw);
  1358. return nbuf;
  1359. }
  1360. #else
  1361. static
  1362. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1363. struct dp_tx_msdu_info_s *msdu_info)
  1364. {
  1365. return nbuf;
  1366. }
  1367. #endif
  1368. #ifdef DP_FEATURE_NAWDS_TX
  1369. /**
  1370. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1371. * @vdev: dp_vdev handle
  1372. * @nbuf: skb
  1373. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1374. * @tx_q: Tx queue to be used for this Tx frame
  1375. * @meta_data: Meta date for mesh
  1376. * @peer_id: peer_id of the peer in case of NAWDS frames
  1377. *
  1378. * return: NULL on success nbuf on failure
  1379. */
  1380. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1381. struct dp_tx_msdu_info_s *msdu_info)
  1382. {
  1383. struct dp_peer *peer = NULL;
  1384. struct dp_soc *soc = vdev->pdev->soc;
  1385. struct dp_ast_entry *ast_entry = NULL;
  1386. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1387. uint16_t peer_id = HTT_INVALID_PEER;
  1388. struct dp_peer *sa_peer = NULL;
  1389. qdf_nbuf_t nbuf_copy;
  1390. qdf_spin_lock_bh(&(soc->ast_lock));
  1391. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1392. if (ast_entry)
  1393. sa_peer = ast_entry->peer;
  1394. qdf_spin_unlock_bh(&(soc->ast_lock));
  1395. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1396. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1397. (peer->nawds_enabled)) {
  1398. if (sa_peer == peer) {
  1399. QDF_TRACE(QDF_MODULE_ID_DP,
  1400. QDF_TRACE_LEVEL_DEBUG,
  1401. " %s: broadcast multicast packet",
  1402. __func__);
  1403. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1404. continue;
  1405. }
  1406. nbuf_copy = qdf_nbuf_copy(nbuf);
  1407. if (!nbuf_copy) {
  1408. QDF_TRACE(QDF_MODULE_ID_DP,
  1409. QDF_TRACE_LEVEL_ERROR,
  1410. "nbuf copy failed");
  1411. }
  1412. peer_id = peer->peer_ids[0];
  1413. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1414. msdu_info, peer_id, NULL);
  1415. if (nbuf_copy != NULL) {
  1416. qdf_nbuf_free(nbuf_copy);
  1417. continue;
  1418. }
  1419. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1420. 1, qdf_nbuf_len(nbuf));
  1421. }
  1422. }
  1423. if (peer_id == HTT_INVALID_PEER)
  1424. return nbuf;
  1425. return NULL;
  1426. }
  1427. #endif
  1428. /**
  1429. * dp_check_exc_metadata() - Checks if parameters are valid
  1430. * @tx_exc - holds all exception path parameters
  1431. *
  1432. * Returns true when all the parameters are valid else false
  1433. *
  1434. */
  1435. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1436. {
  1437. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1438. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1439. tx_exc->sec_type > cdp_num_sec_types) {
  1440. return false;
  1441. }
  1442. return true;
  1443. }
  1444. /**
  1445. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1446. * @vap_dev: DP vdev handle
  1447. * @nbuf: skb
  1448. * @tx_exc_metadata: Handle that holds exception path meta data
  1449. *
  1450. * Entry point for Core Tx layer (DP_TX) invoked from
  1451. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1452. *
  1453. * Return: NULL on success,
  1454. * nbuf when it fails to send
  1455. */
  1456. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1457. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1458. {
  1459. struct ether_header *eh = NULL;
  1460. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1461. struct dp_tx_msdu_info_s msdu_info;
  1462. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1463. msdu_info.tid = tx_exc_metadata->tid;
  1464. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1465. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1466. "%s , skb %pM",
  1467. __func__, nbuf->data);
  1468. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1469. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1471. "Invalid parameters in exception path");
  1472. goto fail;
  1473. }
  1474. /* Basic sanity checks for unsupported packets */
  1475. /* MESH mode */
  1476. if (qdf_unlikely(vdev->mesh_vdev)) {
  1477. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1478. "Mesh mode is not supported in exception path");
  1479. goto fail;
  1480. }
  1481. /* TSO or SG */
  1482. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1483. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1485. "TSO and SG are not supported in exception path");
  1486. goto fail;
  1487. }
  1488. /* RAW */
  1489. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1490. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1491. "Raw frame is not supported in exception path");
  1492. goto fail;
  1493. }
  1494. /* Mcast enhancement*/
  1495. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1496. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1498. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1499. }
  1500. }
  1501. /*
  1502. * Get HW Queue to use for this frame.
  1503. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1504. * dedicated for data and 1 for command.
  1505. * "queue_id" maps to one hardware ring.
  1506. * With each ring, we also associate a unique Tx descriptor pool
  1507. * to minimize lock contention for these resources.
  1508. */
  1509. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1510. /* Reset the control block */
  1511. qdf_nbuf_reset_ctxt(nbuf);
  1512. /* Single linear frame */
  1513. /*
  1514. * If nbuf is a simple linear frame, use send_single function to
  1515. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1516. * SRNG. There is no need to setup a MSDU extension descriptor.
  1517. */
  1518. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1519. tx_exc_metadata->peer_id, tx_exc_metadata);
  1520. return nbuf;
  1521. fail:
  1522. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1523. "pkt send failed");
  1524. return nbuf;
  1525. }
  1526. /**
  1527. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1528. * @vap_dev: DP vdev handle
  1529. * @nbuf: skb
  1530. *
  1531. * Entry point for Core Tx layer (DP_TX) invoked from
  1532. * hard_start_xmit in OSIF/HDD
  1533. *
  1534. * Return: NULL on success,
  1535. * nbuf when it fails to send
  1536. */
  1537. #ifdef MESH_MODE_SUPPORT
  1538. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1539. {
  1540. struct meta_hdr_s *mhdr;
  1541. qdf_nbuf_t nbuf_mesh = NULL;
  1542. qdf_nbuf_t nbuf_clone = NULL;
  1543. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1544. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1545. if (nbuf_mesh == NULL) {
  1546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1547. "qdf_nbuf_unshare failed\n");
  1548. return nbuf;
  1549. }
  1550. nbuf = nbuf_mesh;
  1551. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1552. if (mhdr->flags & METAHDR_FLAG_INFO_UPDATED) {
  1553. nbuf_clone = qdf_nbuf_clone(nbuf);
  1554. if (nbuf_clone == NULL) {
  1555. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1556. "qdf_nbuf_clone failed\n");
  1557. return nbuf;
  1558. }
  1559. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1560. }
  1561. if (nbuf_clone) {
  1562. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1563. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1564. } else
  1565. qdf_nbuf_free(nbuf_clone);
  1566. }
  1567. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1568. return dp_tx_send(vap_dev, nbuf);
  1569. }
  1570. #else
  1571. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1572. {
  1573. return dp_tx_send(vap_dev, nbuf);
  1574. }
  1575. #endif
  1576. /**
  1577. * dp_tx_send() - Transmit a frame on a given VAP
  1578. * @vap_dev: DP vdev handle
  1579. * @nbuf: skb
  1580. *
  1581. * Entry point for Core Tx layer (DP_TX) invoked from
  1582. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1583. * cases
  1584. *
  1585. * Return: NULL on success,
  1586. * nbuf when it fails to send
  1587. */
  1588. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1589. {
  1590. struct ether_header *eh = NULL;
  1591. struct dp_tx_msdu_info_s msdu_info;
  1592. struct dp_tx_seg_info_s seg_info;
  1593. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1594. uint16_t peer_id = HTT_INVALID_PEER;
  1595. qdf_nbuf_t nbuf_mesh = NULL;
  1596. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1597. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1598. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1599. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1600. "%s , skb %pM",
  1601. __func__, nbuf->data);
  1602. /*
  1603. * Set Default Host TID value to invalid TID
  1604. * (TID override disabled)
  1605. */
  1606. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1607. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1608. if (qdf_unlikely(vdev->mesh_vdev)) {
  1609. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1610. &msdu_info);
  1611. if (nbuf_mesh == NULL) {
  1612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1613. "Extracting mesh metadata failed\n");
  1614. return nbuf;
  1615. }
  1616. nbuf = nbuf_mesh;
  1617. }
  1618. /*
  1619. * Get HW Queue to use for this frame.
  1620. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1621. * dedicated for data and 1 for command.
  1622. * "queue_id" maps to one hardware ring.
  1623. * With each ring, we also associate a unique Tx descriptor pool
  1624. * to minimize lock contention for these resources.
  1625. */
  1626. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1627. /*
  1628. * TCL H/W supports 2 DSCP-TID mapping tables.
  1629. * Table 1 - Default DSCP-TID mapping table
  1630. * Table 2 - 1 DSCP-TID override table
  1631. *
  1632. * If we need a different DSCP-TID mapping for this vap,
  1633. * call tid_classify to extract DSCP/ToS from frame and
  1634. * map to a TID and store in msdu_info. This is later used
  1635. * to fill in TCL Input descriptor (per-packet TID override).
  1636. */
  1637. if (vdev->dscp_tid_map_id > 1)
  1638. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1639. /* Reset the control block */
  1640. qdf_nbuf_reset_ctxt(nbuf);
  1641. /*
  1642. * Classify the frame and call corresponding
  1643. * "prepare" function which extracts the segment (TSO)
  1644. * and fragmentation information (for TSO , SG, ME, or Raw)
  1645. * into MSDU_INFO structure which is later used to fill
  1646. * SW and HW descriptors.
  1647. */
  1648. if (qdf_nbuf_is_tso(nbuf)) {
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1650. "%s TSO frame %pK\n", __func__, vdev);
  1651. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1652. qdf_nbuf_len(nbuf));
  1653. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1654. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1655. return nbuf;
  1656. }
  1657. goto send_multiple;
  1658. }
  1659. /* SG */
  1660. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1661. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1663. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1664. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1665. qdf_nbuf_len(nbuf));
  1666. goto send_multiple;
  1667. }
  1668. #ifdef ATH_SUPPORT_IQUE
  1669. /* Mcast to Ucast Conversion*/
  1670. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1671. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1672. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1673. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1674. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1675. DP_STATS_INC_PKT(vdev,
  1676. tx_i.mcast_en.mcast_pkt, 1,
  1677. qdf_nbuf_len(nbuf));
  1678. if (dp_tx_prepare_send_me(vdev, nbuf) !=
  1679. QDF_STATUS_SUCCESS) {
  1680. qdf_nbuf_free(nbuf);
  1681. return NULL;
  1682. }
  1683. }
  1684. }
  1685. #endif
  1686. /* RAW */
  1687. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1688. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1689. if (nbuf == NULL)
  1690. return NULL;
  1691. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1692. "%s Raw frame %pK\n", __func__, vdev);
  1693. goto send_multiple;
  1694. }
  1695. /* Single linear frame */
  1696. /*
  1697. * If nbuf is a simple linear frame, use send_single function to
  1698. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1699. * SRNG. There is no need to setup a MSDU extension descriptor.
  1700. */
  1701. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1702. return nbuf;
  1703. send_multiple:
  1704. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1705. return nbuf;
  1706. }
  1707. /**
  1708. * dp_tx_reinject_handler() - Tx Reinject Handler
  1709. * @tx_desc: software descriptor head pointer
  1710. * @status : Tx completion status from HTT descriptor
  1711. *
  1712. * This function reinjects frames back to Target.
  1713. * Todo - Host queue needs to be added
  1714. *
  1715. * Return: none
  1716. */
  1717. static
  1718. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1719. {
  1720. struct dp_vdev *vdev;
  1721. struct dp_peer *peer = NULL;
  1722. uint32_t peer_id = HTT_INVALID_PEER;
  1723. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1724. qdf_nbuf_t nbuf_copy = NULL;
  1725. struct dp_tx_msdu_info_s msdu_info;
  1726. struct dp_peer *sa_peer = NULL;
  1727. struct dp_ast_entry *ast_entry = NULL;
  1728. struct dp_soc *soc = NULL;
  1729. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1730. #ifdef WDS_VENDOR_EXTENSION
  1731. int is_mcast = 0, is_ucast = 0;
  1732. int num_peers_3addr = 0;
  1733. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1734. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1735. #endif
  1736. vdev = tx_desc->vdev;
  1737. soc = vdev->pdev->soc;
  1738. qdf_assert(vdev);
  1739. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1740. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1741. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1742. "%s Tx reinject path\n", __func__);
  1743. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1744. qdf_nbuf_len(tx_desc->nbuf));
  1745. qdf_spin_lock_bh(&(soc->ast_lock));
  1746. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1747. if (ast_entry)
  1748. sa_peer = ast_entry->peer;
  1749. qdf_spin_unlock_bh(&(soc->ast_lock));
  1750. #ifdef WDS_VENDOR_EXTENSION
  1751. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1752. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1753. } else {
  1754. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1755. }
  1756. is_ucast = !is_mcast;
  1757. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1758. if (peer->bss_peer)
  1759. continue;
  1760. /* Detect wds peers that use 3-addr framing for mcast.
  1761. * if there are any, the bss_peer is used to send the
  1762. * the mcast frame using 3-addr format. all wds enabled
  1763. * peers that use 4-addr framing for mcast frames will
  1764. * be duplicated and sent as 4-addr frames below.
  1765. */
  1766. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1767. num_peers_3addr = 1;
  1768. break;
  1769. }
  1770. }
  1771. #endif
  1772. if (qdf_unlikely(vdev->mesh_vdev)) {
  1773. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1774. } else {
  1775. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1776. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1777. #ifdef WDS_VENDOR_EXTENSION
  1778. /*
  1779. * . if 3-addr STA, then send on BSS Peer
  1780. * . if Peer WDS enabled and accept 4-addr mcast,
  1781. * send mcast on that peer only
  1782. * . if Peer WDS enabled and accept 4-addr ucast,
  1783. * send ucast on that peer only
  1784. */
  1785. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1786. (peer->wds_enabled &&
  1787. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1788. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1789. #else
  1790. ((peer->bss_peer &&
  1791. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1792. peer->nawds_enabled)) {
  1793. #endif
  1794. peer_id = DP_INVALID_PEER;
  1795. if (peer->nawds_enabled) {
  1796. peer_id = peer->peer_ids[0];
  1797. if (sa_peer == peer) {
  1798. QDF_TRACE(
  1799. QDF_MODULE_ID_DP,
  1800. QDF_TRACE_LEVEL_DEBUG,
  1801. " %s: multicast packet",
  1802. __func__);
  1803. DP_STATS_INC(peer,
  1804. tx.nawds_mcast_drop, 1);
  1805. continue;
  1806. }
  1807. }
  1808. nbuf_copy = qdf_nbuf_copy(nbuf);
  1809. if (!nbuf_copy) {
  1810. QDF_TRACE(QDF_MODULE_ID_DP,
  1811. QDF_TRACE_LEVEL_DEBUG,
  1812. FL("nbuf copy failed"));
  1813. break;
  1814. }
  1815. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1816. nbuf_copy,
  1817. &msdu_info,
  1818. peer_id,
  1819. NULL);
  1820. if (nbuf_copy) {
  1821. QDF_TRACE(QDF_MODULE_ID_DP,
  1822. QDF_TRACE_LEVEL_DEBUG,
  1823. FL("pkt send failed"));
  1824. qdf_nbuf_free(nbuf_copy);
  1825. } else {
  1826. if (peer_id != DP_INVALID_PEER)
  1827. DP_STATS_INC_PKT(peer,
  1828. tx.nawds_mcast,
  1829. 1, qdf_nbuf_len(nbuf));
  1830. }
  1831. }
  1832. }
  1833. }
  1834. if (vdev->nawds_enabled) {
  1835. peer_id = DP_INVALID_PEER;
  1836. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1837. 1, qdf_nbuf_len(nbuf));
  1838. nbuf = dp_tx_send_msdu_single(vdev,
  1839. nbuf,
  1840. &msdu_info,
  1841. peer_id, NULL);
  1842. if (nbuf) {
  1843. QDF_TRACE(QDF_MODULE_ID_DP,
  1844. QDF_TRACE_LEVEL_DEBUG,
  1845. FL("pkt send failed"));
  1846. qdf_nbuf_free(nbuf);
  1847. }
  1848. } else
  1849. qdf_nbuf_free(nbuf);
  1850. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1851. }
  1852. /**
  1853. * dp_tx_inspect_handler() - Tx Inspect Handler
  1854. * @tx_desc: software descriptor head pointer
  1855. * @status : Tx completion status from HTT descriptor
  1856. *
  1857. * Handles Tx frames sent back to Host for inspection
  1858. * (ProxyARP)
  1859. *
  1860. * Return: none
  1861. */
  1862. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1863. {
  1864. struct dp_soc *soc;
  1865. struct dp_pdev *pdev = tx_desc->pdev;
  1866. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1867. "%s Tx inspect path\n",
  1868. __func__);
  1869. qdf_assert(pdev);
  1870. soc = pdev->soc;
  1871. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1872. qdf_nbuf_len(tx_desc->nbuf));
  1873. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1874. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1875. }
  1876. #ifdef FEATURE_PERPKT_INFO
  1877. /**
  1878. * dp_get_completion_indication_for_stack() - send completion to stack
  1879. * @soc : dp_soc handle
  1880. * @pdev: dp_pdev handle
  1881. * @peer_id: peer_id of the peer for which completion came
  1882. * @ppdu_id: ppdu_id
  1883. * @first_msdu: first msdu
  1884. * @last_msdu: last msdu
  1885. * @netbuf: Buffer pointer for free
  1886. *
  1887. * This function is used for indication whether buffer needs to be
  1888. * send to stack for free or not
  1889. */
  1890. QDF_STATUS
  1891. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1892. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1893. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1894. {
  1895. struct tx_capture_hdr *ppdu_hdr;
  1896. struct dp_peer *peer = NULL;
  1897. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1898. return QDF_STATUS_E_NOSUPPORT;
  1899. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1900. dp_peer_find_by_id(soc, peer_id);
  1901. if (!peer) {
  1902. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1903. FL("Peer Invalid"));
  1904. return QDF_STATUS_E_INVAL;
  1905. }
  1906. if (pdev->mcopy_mode) {
  1907. if ((pdev->am_copy_id.tx_ppdu_id == ppdu_id) &&
  1908. (pdev->am_copy_id.tx_peer_id == peer_id)) {
  1909. return QDF_STATUS_E_INVAL;
  1910. }
  1911. pdev->am_copy_id.tx_ppdu_id = ppdu_id;
  1912. pdev->am_copy_id.tx_peer_id = peer_id;
  1913. }
  1914. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1915. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1916. FL("No headroom"));
  1917. return QDF_STATUS_E_NOMEM;
  1918. }
  1919. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1920. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1921. IEEE80211_ADDR_LEN);
  1922. ppdu_hdr->ppdu_id = ppdu_id;
  1923. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1924. IEEE80211_ADDR_LEN);
  1925. ppdu_hdr->peer_id = peer_id;
  1926. ppdu_hdr->first_msdu = first_msdu;
  1927. ppdu_hdr->last_msdu = last_msdu;
  1928. return QDF_STATUS_SUCCESS;
  1929. }
  1930. /**
  1931. * dp_send_completion_to_stack() - send completion to stack
  1932. * @soc : dp_soc handle
  1933. * @pdev: dp_pdev handle
  1934. * @peer_id: peer_id of the peer for which completion came
  1935. * @ppdu_id: ppdu_id
  1936. * @netbuf: Buffer pointer for free
  1937. *
  1938. * This function is used to send completion to stack
  1939. * to free buffer
  1940. */
  1941. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1942. uint16_t peer_id, uint32_t ppdu_id,
  1943. qdf_nbuf_t netbuf)
  1944. {
  1945. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1946. netbuf, peer_id,
  1947. WDI_NO_VAL, pdev->pdev_id);
  1948. }
  1949. #else
  1950. static QDF_STATUS
  1951. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1952. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1953. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1954. {
  1955. return QDF_STATUS_E_NOSUPPORT;
  1956. }
  1957. static void
  1958. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1959. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1960. {
  1961. }
  1962. #endif
  1963. /**
  1964. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1965. * @soc: Soc handle
  1966. * @desc: software Tx descriptor to be processed
  1967. *
  1968. * Return: none
  1969. */
  1970. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1971. struct dp_tx_desc_s *desc)
  1972. {
  1973. struct dp_vdev *vdev = desc->vdev;
  1974. qdf_nbuf_t nbuf = desc->nbuf;
  1975. /* If it is TDLS mgmt, don't unmap or free the frame */
  1976. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1977. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1978. /* 0 : MSDU buffer, 1 : MLE */
  1979. if (desc->msdu_ext_desc) {
  1980. /* TSO free */
  1981. if (hal_tx_ext_desc_get_tso_enable(
  1982. desc->msdu_ext_desc->vaddr)) {
  1983. /* If remaining number of segment is 0
  1984. * actual TSO may unmap and free */
  1985. if (qdf_nbuf_get_users(nbuf) == 1)
  1986. __qdf_nbuf_unmap_single(soc->osdev,
  1987. nbuf,
  1988. QDF_DMA_TO_DEVICE);
  1989. qdf_nbuf_free(nbuf);
  1990. return;
  1991. }
  1992. }
  1993. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1994. if (qdf_likely(!vdev->mesh_vdev))
  1995. qdf_nbuf_free(nbuf);
  1996. else {
  1997. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1998. qdf_nbuf_free(nbuf);
  1999. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2000. } else
  2001. vdev->osif_tx_free_ext((nbuf));
  2002. }
  2003. }
  2004. /**
  2005. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2006. * @vdev: pointer to dp dev handler
  2007. * @status : Tx completion status from HTT descriptor
  2008. *
  2009. * Handles MEC notify event sent from fw to Host
  2010. *
  2011. * Return: none
  2012. */
  2013. #ifdef FEATURE_WDS
  2014. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2015. {
  2016. struct dp_soc *soc;
  2017. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2018. struct dp_peer *peer;
  2019. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2020. soc = vdev->pdev->soc;
  2021. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2022. peer = TAILQ_FIRST(&vdev->peer_list);
  2023. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2024. if (!peer) {
  2025. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2026. FL("peer is NULL"));
  2027. return;
  2028. }
  2029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2030. "%s Tx MEC Handler\n",
  2031. __func__);
  2032. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2033. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2034. status[(DP_MAC_ADDR_LEN - 2) + i];
  2035. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2036. dp_peer_add_ast(soc,
  2037. peer,
  2038. mac_addr,
  2039. CDP_TXRX_AST_TYPE_MEC,
  2040. flags);
  2041. }
  2042. #else
  2043. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2044. {
  2045. }
  2046. #endif
  2047. /**
  2048. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2049. * @tx_desc: software descriptor head pointer
  2050. * @status : Tx completion status from HTT descriptor
  2051. *
  2052. * This function will process HTT Tx indication messages from Target
  2053. *
  2054. * Return: none
  2055. */
  2056. static
  2057. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2058. {
  2059. uint8_t tx_status;
  2060. struct dp_pdev *pdev;
  2061. struct dp_vdev *vdev;
  2062. struct dp_soc *soc;
  2063. uint32_t *htt_status_word = (uint32_t *) status;
  2064. qdf_assert(tx_desc->pdev);
  2065. pdev = tx_desc->pdev;
  2066. vdev = tx_desc->vdev;
  2067. soc = pdev->soc;
  2068. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2069. switch (tx_status) {
  2070. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2071. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2072. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2073. {
  2074. dp_tx_comp_free_buf(soc, tx_desc);
  2075. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2076. break;
  2077. }
  2078. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2079. {
  2080. dp_tx_reinject_handler(tx_desc, status);
  2081. break;
  2082. }
  2083. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2084. {
  2085. dp_tx_inspect_handler(tx_desc, status);
  2086. break;
  2087. }
  2088. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2089. {
  2090. dp_tx_mec_handler(vdev, status);
  2091. break;
  2092. }
  2093. default:
  2094. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2095. "%s Invalid HTT tx_status %d\n",
  2096. __func__, tx_status);
  2097. break;
  2098. }
  2099. }
  2100. #ifdef MESH_MODE_SUPPORT
  2101. /**
  2102. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2103. * in mesh meta header
  2104. * @tx_desc: software descriptor head pointer
  2105. * @ts: pointer to tx completion stats
  2106. * Return: none
  2107. */
  2108. static
  2109. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2110. struct hal_tx_completion_status *ts)
  2111. {
  2112. struct meta_hdr_s *mhdr;
  2113. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2114. if (!tx_desc->msdu_ext_desc) {
  2115. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2116. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2117. "netbuf %pK offset %d\n",
  2118. netbuf, tx_desc->pkt_offset);
  2119. return;
  2120. }
  2121. }
  2122. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2123. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2124. "netbuf %pK offset %d\n", netbuf,
  2125. sizeof(struct meta_hdr_s));
  2126. return;
  2127. }
  2128. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2129. mhdr->rssi = ts->ack_frame_rssi;
  2130. mhdr->channel = tx_desc->pdev->operating_channel;
  2131. }
  2132. #else
  2133. static
  2134. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2135. struct hal_tx_completion_status *ts)
  2136. {
  2137. }
  2138. #endif
  2139. /**
  2140. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2141. * @peer: Handle to DP peer
  2142. * @ts: pointer to HAL Tx completion stats
  2143. * @length: MSDU length
  2144. *
  2145. * Return: None
  2146. */
  2147. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2148. struct hal_tx_completion_status *ts, uint32_t length)
  2149. {
  2150. struct dp_pdev *pdev = peer->vdev->pdev;
  2151. struct dp_soc *soc = pdev->soc;
  2152. uint8_t mcs, pkt_type;
  2153. mcs = ts->mcs;
  2154. pkt_type = ts->pkt_type;
  2155. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2156. return;
  2157. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2158. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2159. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2160. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2161. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2162. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2163. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2164. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2165. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2166. return;
  2167. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2168. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2169. if (!(soc->process_tx_status))
  2170. return;
  2171. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2172. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2173. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2174. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2175. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2176. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2177. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2178. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2179. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2180. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2181. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2182. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2183. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2184. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2185. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2186. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2187. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2188. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2189. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2190. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2191. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2192. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2193. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2194. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2195. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2196. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2197. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2198. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2199. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2200. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2201. &peer->stats, ts->peer_id,
  2202. UPDATE_PEER_STATS);
  2203. }
  2204. }
  2205. /**
  2206. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2207. * @tx_desc: software descriptor head pointer
  2208. * @length: packet length
  2209. *
  2210. * Return: none
  2211. */
  2212. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2213. uint32_t length)
  2214. {
  2215. struct hal_tx_completion_status ts;
  2216. struct dp_soc *soc = NULL;
  2217. struct dp_vdev *vdev = tx_desc->vdev;
  2218. struct dp_peer *peer = NULL;
  2219. struct ether_header *eh =
  2220. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2221. bool isBroadcast;
  2222. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2224. "-------------------- \n"
  2225. "Tx Completion Stats: \n"
  2226. "-------------------- \n"
  2227. "ack_frame_rssi = %d \n"
  2228. "first_msdu = %d \n"
  2229. "last_msdu = %d \n"
  2230. "msdu_part_of_amsdu = %d \n"
  2231. "rate_stats valid = %d \n"
  2232. "bw = %d \n"
  2233. "pkt_type = %d \n"
  2234. "stbc = %d \n"
  2235. "ldpc = %d \n"
  2236. "sgi = %d \n"
  2237. "mcs = %d \n"
  2238. "ofdma = %d \n"
  2239. "tones_in_ru = %d \n"
  2240. "tsf = %d \n"
  2241. "ppdu_id = %d \n"
  2242. "transmit_cnt = %d \n"
  2243. "tid = %d \n"
  2244. "peer_id = %d \n",
  2245. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2246. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2247. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2248. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2249. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2250. ts.peer_id);
  2251. if (!vdev) {
  2252. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2253. "invalid vdev");
  2254. goto out;
  2255. }
  2256. soc = vdev->pdev->soc;
  2257. /* Update SoC level stats */
  2258. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2259. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2260. /* Update per-packet stats */
  2261. if (qdf_unlikely(vdev->mesh_vdev) &&
  2262. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2263. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2264. /* Update peer level stats */
  2265. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2266. if (!peer) {
  2267. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2268. "invalid peer");
  2269. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2270. goto out;
  2271. }
  2272. if (qdf_likely(vdev->tx_encap_type == htt_cmn_pkt_type_ethernet)) {
  2273. isBroadcast = (IEEE80211_IS_BROADCAST(eh->ether_dhost)) ? 1 : 0 ;
  2274. if (isBroadcast) {
  2275. DP_STATS_INC_PKT(peer, tx.bcast, 1,
  2276. qdf_nbuf_len(tx_desc->nbuf));
  2277. }
  2278. }
  2279. dp_tx_update_peer_stats(peer, &ts, length);
  2280. out:
  2281. return;
  2282. }
  2283. /**
  2284. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2285. * @soc: core txrx main context
  2286. * @comp_head: software descriptor head pointer
  2287. *
  2288. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2289. * and release the software descriptors after processing is complete
  2290. *
  2291. * Return: none
  2292. */
  2293. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2294. struct dp_tx_desc_s *comp_head)
  2295. {
  2296. struct dp_tx_desc_s *desc;
  2297. struct dp_tx_desc_s *next;
  2298. struct hal_tx_completion_status ts = {0};
  2299. uint32_t length;
  2300. struct dp_peer *peer;
  2301. DP_HIST_INIT();
  2302. desc = comp_head;
  2303. while (desc) {
  2304. hal_tx_comp_get_status(&desc->comp, &ts);
  2305. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2306. length = qdf_nbuf_len(desc->nbuf);
  2307. dp_tx_comp_process_tx_status(desc, length);
  2308. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2309. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2310. desc->pdev, ts.peer_id, ts.ppdu_id,
  2311. ts.first_msdu, ts.last_msdu,
  2312. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2313. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2314. QDF_DMA_TO_DEVICE);
  2315. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2316. ts.ppdu_id, desc->nbuf);
  2317. } else {
  2318. dp_tx_comp_free_buf(soc, desc);
  2319. }
  2320. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2321. next = desc->next;
  2322. dp_tx_desc_release(desc, desc->pool_id);
  2323. desc = next;
  2324. }
  2325. DP_TX_HIST_STATS_PER_PDEV();
  2326. }
  2327. /**
  2328. * dp_tx_comp_handler() - Tx completion handler
  2329. * @soc: core txrx main context
  2330. * @ring_id: completion ring id
  2331. * @quota: No. of packets/descriptors that can be serviced in one loop
  2332. *
  2333. * This function will collect hardware release ring element contents and
  2334. * handle descriptor contents. Based on contents, free packet or handle error
  2335. * conditions
  2336. *
  2337. * Return: none
  2338. */
  2339. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2340. {
  2341. void *tx_comp_hal_desc;
  2342. uint8_t buffer_src;
  2343. uint8_t pool_id;
  2344. uint32_t tx_desc_id;
  2345. struct dp_tx_desc_s *tx_desc = NULL;
  2346. struct dp_tx_desc_s *head_desc = NULL;
  2347. struct dp_tx_desc_s *tail_desc = NULL;
  2348. uint32_t num_processed;
  2349. uint32_t count;
  2350. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2351. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2352. "%s %d : HAL RING Access Failed -- %pK\n",
  2353. __func__, __LINE__, hal_srng);
  2354. return 0;
  2355. }
  2356. num_processed = 0;
  2357. count = 0;
  2358. /* Find head descriptor from completion ring */
  2359. while (qdf_likely(tx_comp_hal_desc =
  2360. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2361. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2362. /* If this buffer was not released by TQM or FW, then it is not
  2363. * Tx completion indication, assert */
  2364. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2365. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2366. QDF_TRACE(QDF_MODULE_ID_DP,
  2367. QDF_TRACE_LEVEL_FATAL,
  2368. "Tx comp release_src != TQM | FW");
  2369. qdf_assert_always(0);
  2370. }
  2371. /* Get descriptor id */
  2372. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2373. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2374. DP_TX_DESC_ID_POOL_OS;
  2375. /* Pool ID is out of limit. Error */
  2376. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2377. soc->wlan_cfg_ctx)) {
  2378. QDF_TRACE(QDF_MODULE_ID_DP,
  2379. QDF_TRACE_LEVEL_FATAL,
  2380. "Tx Comp pool id %d not valid",
  2381. pool_id);
  2382. qdf_assert_always(0);
  2383. }
  2384. /* Find Tx descriptor */
  2385. tx_desc = dp_tx_desc_find(soc, pool_id,
  2386. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2387. DP_TX_DESC_ID_PAGE_OS,
  2388. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2389. DP_TX_DESC_ID_OFFSET_OS);
  2390. /*
  2391. * If the release source is FW, process the HTT status
  2392. */
  2393. if (qdf_unlikely(buffer_src ==
  2394. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2395. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2396. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2397. htt_tx_status);
  2398. dp_tx_process_htt_completion(tx_desc,
  2399. htt_tx_status);
  2400. } else {
  2401. /* Pool id is not matching. Error */
  2402. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  2403. QDF_TRACE(QDF_MODULE_ID_DP,
  2404. QDF_TRACE_LEVEL_FATAL,
  2405. "Tx Comp pool id %d not matched %d",
  2406. pool_id, tx_desc->pool_id);
  2407. qdf_assert_always(0);
  2408. }
  2409. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2410. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2411. QDF_TRACE(QDF_MODULE_ID_DP,
  2412. QDF_TRACE_LEVEL_FATAL,
  2413. "Txdesc invalid, flgs = %x,id = %d",
  2414. tx_desc->flags, tx_desc_id);
  2415. qdf_assert_always(0);
  2416. }
  2417. /* First ring descriptor on the cycle */
  2418. if (!head_desc) {
  2419. head_desc = tx_desc;
  2420. tail_desc = tx_desc;
  2421. }
  2422. tail_desc->next = tx_desc;
  2423. tx_desc->next = NULL;
  2424. tail_desc = tx_desc;
  2425. /* Collect hw completion contents */
  2426. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2427. &tx_desc->comp, 1);
  2428. }
  2429. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2430. /* Decrement PM usage count if the packet has been sent.*/
  2431. hif_pm_runtime_put(soc->hif_handle);
  2432. /*
  2433. * Processed packet count is more than given quota
  2434. * stop to processing
  2435. */
  2436. if ((num_processed >= quota))
  2437. break;
  2438. count++;
  2439. }
  2440. hal_srng_access_end(soc->hal_soc, hal_srng);
  2441. /* Process the reaped descriptors */
  2442. if (head_desc)
  2443. dp_tx_comp_process_desc(soc, head_desc);
  2444. return num_processed;
  2445. }
  2446. #ifdef CONVERGED_TDLS_ENABLE
  2447. /**
  2448. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2449. *
  2450. * @data_vdev - which vdev should transmit the tx data frames
  2451. * @tx_spec - what non-standard handling to apply to the tx data frames
  2452. * @msdu_list - NULL-terminated list of tx MSDUs
  2453. *
  2454. * Return: NULL on success,
  2455. * nbuf when it fails to send
  2456. */
  2457. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2458. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2459. {
  2460. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2461. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2462. vdev->is_tdls_frame = true;
  2463. return dp_tx_send(vdev_handle, msdu_list);
  2464. }
  2465. #endif
  2466. /**
  2467. * dp_tx_vdev_attach() - attach vdev to dp tx
  2468. * @vdev: virtual device instance
  2469. *
  2470. * Return: QDF_STATUS_SUCCESS: success
  2471. * QDF_STATUS_E_RESOURCES: Error return
  2472. */
  2473. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2474. {
  2475. /*
  2476. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2477. */
  2478. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2479. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2480. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2481. vdev->vdev_id);
  2482. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2483. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2484. /*
  2485. * Set HTT Extension Valid bit to 0 by default
  2486. */
  2487. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2488. dp_tx_vdev_update_search_flags(vdev);
  2489. return QDF_STATUS_SUCCESS;
  2490. }
  2491. /**
  2492. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2493. * @vdev: virtual device instance
  2494. *
  2495. * Return: void
  2496. *
  2497. */
  2498. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2499. {
  2500. /*
  2501. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2502. * for TDLS link
  2503. *
  2504. * Enable AddrY (SA based search) only for non-WDS STA and
  2505. * ProxySTA VAP modes.
  2506. *
  2507. * In all other VAP modes, only DA based search should be
  2508. * enabled
  2509. */
  2510. if (vdev->opmode == wlan_op_mode_sta &&
  2511. vdev->tdls_link_connected)
  2512. vdev->hal_desc_addr_search_flags =
  2513. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2514. else if ((vdev->opmode == wlan_op_mode_sta &&
  2515. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2516. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2517. else
  2518. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2519. }
  2520. /**
  2521. * dp_tx_vdev_detach() - detach vdev from dp tx
  2522. * @vdev: virtual device instance
  2523. *
  2524. * Return: QDF_STATUS_SUCCESS: success
  2525. * QDF_STATUS_E_RESOURCES: Error return
  2526. */
  2527. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2528. {
  2529. return QDF_STATUS_SUCCESS;
  2530. }
  2531. /**
  2532. * dp_tx_pdev_attach() - attach pdev to dp tx
  2533. * @pdev: physical device instance
  2534. *
  2535. * Return: QDF_STATUS_SUCCESS: success
  2536. * QDF_STATUS_E_RESOURCES: Error return
  2537. */
  2538. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2539. {
  2540. struct dp_soc *soc = pdev->soc;
  2541. /* Initialize Flow control counters */
  2542. qdf_atomic_init(&pdev->num_tx_exception);
  2543. qdf_atomic_init(&pdev->num_tx_outstanding);
  2544. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2545. /* Initialize descriptors in TCL Ring */
  2546. hal_tx_init_data_ring(soc->hal_soc,
  2547. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2548. }
  2549. return QDF_STATUS_SUCCESS;
  2550. }
  2551. /* dp_tx_desc_flush() - release resources associated
  2552. * to tx_desc
  2553. * @pdev: physical device instance
  2554. *
  2555. * This function will free all outstanding Tx buffers,
  2556. * including ME buffer for which either free during
  2557. * completion didn't happened or completion is not
  2558. * received.
  2559. */
  2560. static void dp_tx_desc_flush(struct dp_pdev *pdev)
  2561. {
  2562. uint8_t i, num_pool;
  2563. uint32_t j;
  2564. uint32_t num_desc;
  2565. struct dp_soc *soc = pdev->soc;
  2566. struct dp_tx_desc_s *tx_desc = NULL;
  2567. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2568. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2569. for (i = 0; i < num_pool; i++) {
  2570. for (j = 0; j < num_desc; j++) {
  2571. tx_desc = dp_tx_desc_find(soc, i,
  2572. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2573. DP_TX_DESC_ID_PAGE_OS,
  2574. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2575. DP_TX_DESC_ID_OFFSET_OS);
  2576. if (tx_desc && (tx_desc->pdev == pdev) &&
  2577. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2578. dp_tx_comp_free_buf(soc, tx_desc);
  2579. dp_tx_desc_release(tx_desc, i);
  2580. }
  2581. }
  2582. }
  2583. }
  2584. /**
  2585. * dp_tx_pdev_detach() - detach pdev from dp tx
  2586. * @pdev: physical device instance
  2587. *
  2588. * Return: QDF_STATUS_SUCCESS: success
  2589. * QDF_STATUS_E_RESOURCES: Error return
  2590. */
  2591. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2592. {
  2593. dp_tx_desc_flush(pdev);
  2594. dp_tx_me_exit(pdev);
  2595. return QDF_STATUS_SUCCESS;
  2596. }
  2597. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2598. /* Pools will be allocated dynamically */
  2599. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2600. int num_desc)
  2601. {
  2602. uint8_t i;
  2603. for (i = 0; i < num_pool; i++) {
  2604. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2605. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2606. }
  2607. return 0;
  2608. }
  2609. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2610. {
  2611. uint8_t i;
  2612. for (i = 0; i < num_pool; i++)
  2613. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2614. }
  2615. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2616. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2617. int num_desc)
  2618. {
  2619. uint8_t i;
  2620. /* Allocate software Tx descriptor pools */
  2621. for (i = 0; i < num_pool; i++) {
  2622. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2623. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2624. "%s Tx Desc Pool alloc %d failed %pK\n",
  2625. __func__, i, soc);
  2626. return ENOMEM;
  2627. }
  2628. }
  2629. return 0;
  2630. }
  2631. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2632. {
  2633. uint8_t i;
  2634. for (i = 0; i < num_pool; i++) {
  2635. if (dp_tx_desc_pool_free(soc, i)) {
  2636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2637. "%s Tx Desc Pool Free failed\n", __func__);
  2638. }
  2639. }
  2640. }
  2641. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2642. /**
  2643. * dp_tx_soc_detach() - detach soc from dp tx
  2644. * @soc: core txrx main context
  2645. *
  2646. * This function will detach dp tx into main device context
  2647. * will free dp tx resource and initialize resources
  2648. *
  2649. * Return: QDF_STATUS_SUCCESS: success
  2650. * QDF_STATUS_E_RESOURCES: Error return
  2651. */
  2652. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2653. {
  2654. uint8_t num_pool;
  2655. uint16_t num_desc;
  2656. uint16_t num_ext_desc;
  2657. uint8_t i;
  2658. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2659. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2660. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2661. dp_tx_flow_control_deinit(soc);
  2662. dp_tx_delete_static_pools(soc, num_pool);
  2663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2664. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2665. __func__, num_pool, num_desc);
  2666. for (i = 0; i < num_pool; i++) {
  2667. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2669. "%s Tx Ext Desc Pool Free failed\n",
  2670. __func__);
  2671. return QDF_STATUS_E_RESOURCES;
  2672. }
  2673. }
  2674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2675. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2676. __func__, num_pool, num_ext_desc);
  2677. for (i = 0; i < num_pool; i++) {
  2678. dp_tx_tso_desc_pool_free(soc, i);
  2679. }
  2680. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2681. "%s TSO Desc Pool %d Free descs = %d\n",
  2682. __func__, num_pool, num_desc);
  2683. for (i = 0; i < num_pool; i++)
  2684. dp_tx_tso_num_seg_pool_free(soc, i);
  2685. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2686. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2687. __func__, num_pool, num_desc);
  2688. return QDF_STATUS_SUCCESS;
  2689. }
  2690. /**
  2691. * dp_tx_soc_attach() - attach soc to dp tx
  2692. * @soc: core txrx main context
  2693. *
  2694. * This function will attach dp tx into main device context
  2695. * will allocate dp tx resource and initialize resources
  2696. *
  2697. * Return: QDF_STATUS_SUCCESS: success
  2698. * QDF_STATUS_E_RESOURCES: Error return
  2699. */
  2700. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2701. {
  2702. uint8_t i;
  2703. uint8_t num_pool;
  2704. uint32_t num_desc;
  2705. uint32_t num_ext_desc;
  2706. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2707. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2708. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2709. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2710. goto fail;
  2711. dp_tx_flow_control_init(soc);
  2712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2713. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2714. __func__, num_pool, num_desc);
  2715. /* Allocate extension tx descriptor pools */
  2716. for (i = 0; i < num_pool; i++) {
  2717. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2719. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2720. i, soc);
  2721. goto fail;
  2722. }
  2723. }
  2724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2725. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2726. __func__, num_pool, num_ext_desc);
  2727. for (i = 0; i < num_pool; i++) {
  2728. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2729. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2730. "TSO Desc Pool alloc %d failed %pK\n",
  2731. i, soc);
  2732. goto fail;
  2733. }
  2734. }
  2735. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2736. "%s TSO Desc Alloc %d, descs = %d\n",
  2737. __func__, num_pool, num_desc);
  2738. for (i = 0; i < num_pool; i++) {
  2739. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2740. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2741. "TSO Num of seg Pool alloc %d failed %pK\n",
  2742. i, soc);
  2743. goto fail;
  2744. }
  2745. }
  2746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2747. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2748. __func__, num_pool, num_desc);
  2749. /* Initialize descriptors in TCL Rings */
  2750. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2751. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2752. hal_tx_init_data_ring(soc->hal_soc,
  2753. soc->tcl_data_ring[i].hal_srng);
  2754. }
  2755. }
  2756. /*
  2757. * todo - Add a runtime config option to enable this.
  2758. */
  2759. /*
  2760. * Due to multiple issues on NPR EMU, enable it selectively
  2761. * only for NPR EMU, should be removed, once NPR platforms
  2762. * are stable.
  2763. */
  2764. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2766. "%s HAL Tx init Success\n", __func__);
  2767. return QDF_STATUS_SUCCESS;
  2768. fail:
  2769. /* Detach will take care of freeing only allocated resources */
  2770. dp_tx_soc_detach(soc);
  2771. return QDF_STATUS_E_RESOURCES;
  2772. }
  2773. /*
  2774. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2775. * pdev: pointer to DP PDEV structure
  2776. * seg_info_head: Pointer to the head of list
  2777. *
  2778. * return: void
  2779. */
  2780. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2781. struct dp_tx_seg_info_s *seg_info_head)
  2782. {
  2783. struct dp_tx_me_buf_t *mc_uc_buf;
  2784. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2785. qdf_nbuf_t nbuf = NULL;
  2786. uint64_t phy_addr;
  2787. while (seg_info_head) {
  2788. nbuf = seg_info_head->nbuf;
  2789. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2790. seg_info_head->frags[0].vaddr;
  2791. phy_addr = seg_info_head->frags[0].paddr_hi;
  2792. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2793. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2794. phy_addr,
  2795. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2796. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2797. qdf_nbuf_free(nbuf);
  2798. seg_info_new = seg_info_head;
  2799. seg_info_head = seg_info_head->next;
  2800. qdf_mem_free(seg_info_new);
  2801. }
  2802. }
  2803. /**
  2804. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2805. * @vdev: DP VDEV handle
  2806. * @nbuf: Multicast nbuf
  2807. * @newmac: Table of the clients to which packets have to be sent
  2808. * @new_mac_cnt: No of clients
  2809. *
  2810. * return: no of converted packets
  2811. */
  2812. uint16_t
  2813. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2814. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2815. {
  2816. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2817. struct dp_pdev *pdev = vdev->pdev;
  2818. struct ether_header *eh;
  2819. uint8_t *data;
  2820. uint16_t len;
  2821. /* reference to frame dst addr */
  2822. uint8_t *dstmac;
  2823. /* copy of original frame src addr */
  2824. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2825. /* local index into newmac */
  2826. uint8_t new_mac_idx = 0;
  2827. struct dp_tx_me_buf_t *mc_uc_buf;
  2828. qdf_nbuf_t nbuf_clone;
  2829. struct dp_tx_msdu_info_s msdu_info;
  2830. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2831. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2832. struct dp_tx_seg_info_s *seg_info_new;
  2833. struct dp_tx_frag_info_s data_frag;
  2834. qdf_dma_addr_t paddr_data;
  2835. qdf_dma_addr_t paddr_mcbuf = 0;
  2836. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2837. QDF_STATUS status;
  2838. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2839. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2840. eh = (struct ether_header *) nbuf;
  2841. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2842. len = qdf_nbuf_len(nbuf);
  2843. data = qdf_nbuf_data(nbuf);
  2844. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2845. QDF_DMA_TO_DEVICE);
  2846. if (status) {
  2847. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2848. "Mapping failure Error:%d", status);
  2849. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2850. return 0;
  2851. }
  2852. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2853. /*preparing data fragment*/
  2854. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2855. data_frag.paddr_lo = (uint32_t)paddr_data;
  2856. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2857. data_frag.len = len - DP_MAC_ADDR_LEN;
  2858. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2859. dstmac = newmac[new_mac_idx];
  2860. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2861. "added mac addr (%pM)", dstmac);
  2862. /* Check for NULL Mac Address */
  2863. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2864. continue;
  2865. /* frame to self mac. skip */
  2866. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2867. continue;
  2868. /*
  2869. * TODO: optimize to avoid malloc in per-packet path
  2870. * For eg. seg_pool can be made part of vdev structure
  2871. */
  2872. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2873. if (!seg_info_new) {
  2874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2875. "alloc failed");
  2876. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2877. goto fail_seg_alloc;
  2878. }
  2879. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2880. if (mc_uc_buf == NULL)
  2881. goto fail_buf_alloc;
  2882. /*
  2883. * TODO: Check if we need to clone the nbuf
  2884. * Or can we just use the reference for all cases
  2885. */
  2886. if (new_mac_idx < (new_mac_cnt - 1)) {
  2887. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2888. if (nbuf_clone == NULL) {
  2889. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2890. goto fail_clone;
  2891. }
  2892. } else {
  2893. /*
  2894. * Update the ref
  2895. * to account for frame sent without cloning
  2896. */
  2897. qdf_nbuf_ref(nbuf);
  2898. nbuf_clone = nbuf;
  2899. }
  2900. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2901. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2902. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2903. &paddr_mcbuf);
  2904. if (status) {
  2905. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2906. "Mapping failure Error:%d", status);
  2907. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2908. goto fail_map;
  2909. }
  2910. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2911. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2912. seg_info_new->frags[0].paddr_hi =
  2913. ((uint64_t) paddr_mcbuf >> 32);
  2914. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2915. seg_info_new->frags[1] = data_frag;
  2916. seg_info_new->nbuf = nbuf_clone;
  2917. seg_info_new->frag_cnt = 2;
  2918. seg_info_new->total_len = len;
  2919. seg_info_new->next = NULL;
  2920. if (seg_info_head == NULL)
  2921. seg_info_head = seg_info_new;
  2922. else
  2923. seg_info_tail->next = seg_info_new;
  2924. seg_info_tail = seg_info_new;
  2925. }
  2926. if (!seg_info_head)
  2927. return 0;
  2928. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2929. msdu_info.num_seg = new_mac_cnt;
  2930. msdu_info.frm_type = dp_tx_frm_me;
  2931. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2932. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2933. while (seg_info_head->next) {
  2934. seg_info_new = seg_info_head;
  2935. seg_info_head = seg_info_head->next;
  2936. qdf_mem_free(seg_info_new);
  2937. }
  2938. qdf_mem_free(seg_info_head);
  2939. return new_mac_cnt;
  2940. fail_map:
  2941. qdf_nbuf_free(nbuf_clone);
  2942. fail_clone:
  2943. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2944. fail_buf_alloc:
  2945. qdf_mem_free(seg_info_new);
  2946. fail_seg_alloc:
  2947. dp_tx_me_mem_free(pdev, seg_info_head);
  2948. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2949. return 0;
  2950. }