dp_main.c 155 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  57. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  58. #define DP_MAX_MCS_STRING_LEN 30
  59. #define DP_CURR_FW_STATS_AVAIL 19
  60. #define DP_HTT_DBG_EXT_STATS_MAX 256
  61. #ifdef IPA_OFFLOAD
  62. /* Exclude IPA rings from the interrupt context */
  63. #define TX_RING_MASK_VAL 0xb
  64. #define RX_RING_MASK_VAL 0x7
  65. #else
  66. #define TX_RING_MASK_VAL 0xF
  67. #define RX_RING_MASK_VAL 0xF
  68. #endif
  69. bool rx_hash = 1;
  70. qdf_declare_param(rx_hash, bool);
  71. #define STR_MAXLEN 64
  72. /**
  73. * default_dscp_tid_map - Default DSCP-TID mapping
  74. *
  75. * DSCP TID AC
  76. * 000000 0 WME_AC_BE
  77. * 001000 1 WME_AC_BK
  78. * 010000 1 WME_AC_BK
  79. * 011000 0 WME_AC_BE
  80. * 100000 5 WME_AC_VI
  81. * 101000 5 WME_AC_VI
  82. * 110000 6 WME_AC_VO
  83. * 111000 6 WME_AC_VO
  84. */
  85. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  86. 0, 0, 0, 0, 0, 0, 0, 0,
  87. 1, 1, 1, 1, 1, 1, 1, 1,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 0, 0, 0, 0, 0, 0, 0, 0,
  90. 5, 5, 5, 5, 5, 5, 5, 5,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 6, 6, 6, 6, 6, 6, 6, 6,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. };
  95. /*
  96. * struct dp_rate_debug
  97. *
  98. * @mcs_type: print string for a given mcs
  99. * @valid: valid mcs rate?
  100. */
  101. struct dp_rate_debug {
  102. char mcs_type[DP_MAX_MCS_STRING_LEN];
  103. uint8_t valid;
  104. };
  105. #define MCS_VALID 1
  106. #define MCS_INVALID 0
  107. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  108. {
  109. {"CCK 11 Mbps Long ", MCS_VALID},
  110. {"CCK 5.5 Mbps Long ", MCS_VALID},
  111. {"CCK 2 Mbps Long ", MCS_VALID},
  112. {"CCK 1 Mbps Long ", MCS_VALID},
  113. {"CCK 11 Mbps Short ", MCS_VALID},
  114. {"CCK 5.5 Mbps Short", MCS_VALID},
  115. {"CCK 2 Mbps Short ", MCS_VALID},
  116. {"INVALID ", MCS_INVALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_VALID},
  122. },
  123. {
  124. {"OFDM 48 Mbps", MCS_VALID},
  125. {"OFDM 24 Mbps", MCS_VALID},
  126. {"OFDM 12 Mbps", MCS_VALID},
  127. {"OFDM 6 Mbps ", MCS_VALID},
  128. {"OFDM 54 Mbps", MCS_VALID},
  129. {"OFDM 36 Mbps", MCS_VALID},
  130. {"OFDM 18 Mbps", MCS_VALID},
  131. {"OFDM 9 Mbps ", MCS_VALID},
  132. {"INVALID ", MCS_INVALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_VALID},
  137. },
  138. {
  139. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  140. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  142. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  143. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  144. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  145. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  146. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  147. {"INVALID ", MCS_INVALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_VALID},
  152. },
  153. {
  154. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  155. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  157. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  158. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  159. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  160. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  161. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  162. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  163. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  164. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  165. {"VHT MCS 11 (1024-QAM 5/6)", MCS_VALID},
  166. {"INVALID ", MCS_VALID},
  167. },
  168. {
  169. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  170. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  172. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  173. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  174. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  175. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  176. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  177. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  178. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  179. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  180. {"HE MCS 11 (1024-QAM 5/6)", MCS_VALID},
  181. {"INVALID ", MCS_VALID},
  182. }
  183. };
  184. /**
  185. * @brief Cpu ring map types
  186. */
  187. enum dp_cpu_ring_map_types {
  188. DP_DEFAULT_MAP,
  189. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  190. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  191. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  192. DP_CPU_RING_MAP_MAX
  193. };
  194. /**
  195. * @brief Cpu to tx ring map
  196. */
  197. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  198. {0x0, 0x1, 0x2, 0x0},
  199. {0x1, 0x2, 0x1, 0x2},
  200. {0x0, 0x2, 0x0, 0x2},
  201. {0x2, 0x2, 0x2, 0x2}
  202. };
  203. /**
  204. * @brief Select the type of statistics
  205. */
  206. enum dp_stats_type {
  207. STATS_FW = 0,
  208. STATS_HOST = 1,
  209. STATS_TYPE_MAX = 2,
  210. };
  211. /**
  212. * @brief General Firmware statistics options
  213. *
  214. */
  215. enum dp_fw_stats {
  216. TXRX_FW_STATS_INVALID = -1,
  217. };
  218. /**
  219. * dp_stats_mapping_table - Firmware and Host statistics
  220. * currently supported
  221. */
  222. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  223. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  224. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  234. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  242. /* Last ENUM for HTT FW STATS */
  243. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  244. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  245. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  251. };
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  264. {
  265. int ext_group_num;
  266. int mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  275. enum hal_ring_type ring_type,
  276. int ring_num)
  277. {
  278. int *grp_mask;
  279. switch (ring_type) {
  280. case WBM2SW_RELEASE:
  281. /* dp_tx_comp_handler - soc->tx_comp_ring */
  282. if (ring_num < 3)
  283. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  284. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  285. else if (ring_num == 3) {
  286. /* sw treats this as a separate ring type */
  287. grp_mask = &soc->wlan_cfg_ctx->
  288. int_rx_wbm_rel_ring_mask[0];
  289. ring_num = 0;
  290. } else {
  291. qdf_assert(0);
  292. return -QDF_STATUS_E_NOENT;
  293. }
  294. break;
  295. case REO_EXCEPTION:
  296. /* dp_rx_err_process - &soc->reo_exception_ring */
  297. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  298. break;
  299. case REO_DST:
  300. /* dp_rx_process - soc->reo_dest_ring */
  301. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  302. break;
  303. case REO_STATUS:
  304. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  305. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  306. break;
  307. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  308. case RXDMA_MONITOR_STATUS:
  309. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  310. case RXDMA_MONITOR_DST:
  311. /* dp_mon_process */
  312. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  313. break;
  314. case RXDMA_DST:
  315. /* dp_rxdma_err_process */
  316. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  317. break;
  318. case RXDMA_MONITOR_BUF:
  319. case RXDMA_BUF:
  320. /* TODO: support low_thresh interrupt */
  321. return -QDF_STATUS_E_NOENT;
  322. break;
  323. case TCL_DATA:
  324. case TCL_CMD:
  325. case REO_CMD:
  326. case SW2WBM_RELEASE:
  327. case WBM_IDLE_LINK:
  328. /* normally empty SW_TO_HW rings */
  329. return -QDF_STATUS_E_NOENT;
  330. break;
  331. case TCL_STATUS:
  332. case REO_REINJECT:
  333. /* misc unused rings */
  334. return -QDF_STATUS_E_NOENT;
  335. break;
  336. case CE_SRC:
  337. case CE_DST:
  338. case CE_DST_STATUS:
  339. /* CE_rings - currently handled by hif */
  340. default:
  341. return -QDF_STATUS_E_NOENT;
  342. break;
  343. }
  344. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  345. }
  346. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  347. *ring_params, int ring_type, int ring_num)
  348. {
  349. int msi_group_number;
  350. int msi_data_count;
  351. int ret;
  352. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  353. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  354. &msi_data_count, &msi_data_start,
  355. &msi_irq_start);
  356. if (ret)
  357. return;
  358. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  359. ring_num);
  360. if (msi_group_number < 0) {
  361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  362. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  363. ring_type, ring_num);
  364. ring_params->msi_addr = 0;
  365. ring_params->msi_data = 0;
  366. return;
  367. }
  368. if (msi_group_number > msi_data_count) {
  369. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  370. FL("2 msi_groups will share an msi; msi_group_num %d"),
  371. msi_group_number);
  372. QDF_ASSERT(0);
  373. }
  374. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  375. ring_params->msi_addr = addr_low;
  376. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  377. ring_params->msi_data = (msi_group_number % msi_data_count)
  378. + msi_data_start;
  379. ring_params->flags |= HAL_SRNG_MSI_INTR;
  380. }
  381. /**
  382. * dp_print_ast_stats() - Dump AST table contents
  383. * @soc: Datapath soc handle
  384. *
  385. * return void
  386. */
  387. #ifdef FEATURE_WDS
  388. static void dp_print_ast_stats(struct dp_soc *soc)
  389. {
  390. uint8_t i;
  391. uint8_t num_entries = 0;
  392. struct dp_vdev *vdev;
  393. struct dp_pdev *pdev;
  394. struct dp_peer *peer;
  395. struct dp_ast_entry *ase, *tmp_ase;
  396. DP_PRINT_STATS("AST Stats:");
  397. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  398. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  399. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  400. DP_PRINT_STATS("AST Table:");
  401. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  402. pdev = soc->pdev_list[i];
  403. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  404. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  405. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  406. DP_PRINT_STATS("%6d mac_addr = %pM"
  407. " peer_mac_addr = %pM"
  408. " type = %d"
  409. " next_hop = %d"
  410. " is_active = %d"
  411. " is_bss = %d",
  412. ++num_entries,
  413. ase->mac_addr.raw,
  414. ase->peer->mac_addr.raw,
  415. ase->type,
  416. ase->next_hop,
  417. ase->is_active,
  418. ase->is_bss);
  419. }
  420. }
  421. }
  422. }
  423. }
  424. #else
  425. static void dp_print_ast_stats(struct dp_soc *soc)
  426. {
  427. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  428. return;
  429. }
  430. #endif
  431. /*
  432. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  433. */
  434. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  435. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  436. {
  437. void *hal_soc = soc->hal_soc;
  438. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  439. /* TODO: See if we should get align size from hal */
  440. uint32_t ring_base_align = 8;
  441. struct hal_srng_params ring_params;
  442. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  443. /* TODO: Currently hal layer takes care of endianness related settings.
  444. * See if these settings need to passed from DP layer
  445. */
  446. ring_params.flags = 0;
  447. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  448. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  449. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  450. srng->hal_srng = NULL;
  451. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  452. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  453. soc->osdev, soc->osdev->dev, srng->alloc_size,
  454. &(srng->base_paddr_unaligned));
  455. if (!srng->base_vaddr_unaligned) {
  456. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  457. FL("alloc failed - ring_type: %d, ring_num %d"),
  458. ring_type, ring_num);
  459. return QDF_STATUS_E_NOMEM;
  460. }
  461. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  462. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  463. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  464. ((unsigned long)(ring_params.ring_base_vaddr) -
  465. (unsigned long)srng->base_vaddr_unaligned);
  466. ring_params.num_entries = num_entries;
  467. if (soc->intr_mode == DP_INTR_MSI) {
  468. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  470. FL("Using MSI for ring_type: %d, ring_num %d"),
  471. ring_type, ring_num);
  472. } else {
  473. ring_params.msi_data = 0;
  474. ring_params.msi_addr = 0;
  475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  476. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  477. ring_type, ring_num);
  478. }
  479. /*
  480. * Setup interrupt timer and batch counter thresholds for
  481. * interrupt mitigation based on ring type
  482. */
  483. if (ring_type == REO_DST) {
  484. ring_params.intr_timer_thres_us =
  485. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  486. ring_params.intr_batch_cntr_thres_entries =
  487. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  488. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  489. ring_params.intr_timer_thres_us =
  490. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  491. ring_params.intr_batch_cntr_thres_entries =
  492. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  493. } else {
  494. ring_params.intr_timer_thres_us =
  495. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  496. ring_params.intr_batch_cntr_thres_entries =
  497. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  498. }
  499. /* Enable low threshold interrupts for rx buffer rings (regular and
  500. * monitor buffer rings.
  501. * TODO: See if this is required for any other ring
  502. */
  503. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  504. /* TODO: Setting low threshold to 1/8th of ring size
  505. * see if this needs to be configurable
  506. */
  507. ring_params.low_threshold = num_entries >> 3;
  508. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  509. ring_params.intr_timer_thres_us = 0x1000;
  510. }
  511. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  512. mac_id, &ring_params);
  513. return 0;
  514. }
  515. /**
  516. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  517. * Any buffers allocated and attached to ring entries are expected to be freed
  518. * before calling this function.
  519. */
  520. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  521. int ring_type, int ring_num)
  522. {
  523. if (!srng->hal_srng) {
  524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  525. FL("Ring type: %d, num:%d not setup"),
  526. ring_type, ring_num);
  527. return;
  528. }
  529. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  530. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  531. srng->alloc_size,
  532. srng->base_vaddr_unaligned,
  533. srng->base_paddr_unaligned, 0);
  534. srng->hal_srng = NULL;
  535. }
  536. /* TODO: Need this interface from HIF */
  537. void *hif_get_hal_handle(void *hif_handle);
  538. /*
  539. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  540. * @dp_ctx: DP SOC handle
  541. * @budget: Number of frames/descriptors that can be processed in one shot
  542. *
  543. * Return: remaining budget/quota for the soc device
  544. */
  545. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  546. {
  547. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  548. struct dp_soc *soc = int_ctx->soc;
  549. int ring = 0;
  550. uint32_t work_done = 0;
  551. int budget = dp_budget;
  552. uint8_t tx_mask = int_ctx->tx_ring_mask;
  553. uint8_t rx_mask = int_ctx->rx_ring_mask;
  554. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  555. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  556. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  557. uint32_t remaining_quota = dp_budget;
  558. /* Process Tx completion interrupts first to return back buffers */
  559. while (tx_mask) {
  560. if (tx_mask & 0x1) {
  561. work_done = dp_tx_comp_handler(soc,
  562. soc->tx_comp_ring[ring].hal_srng,
  563. remaining_quota);
  564. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  565. "tx mask 0x%x ring %d, budget %d, work_done %d",
  566. tx_mask, ring, budget, work_done);
  567. budget -= work_done;
  568. if (budget <= 0)
  569. goto budget_done;
  570. remaining_quota = budget;
  571. }
  572. tx_mask = tx_mask >> 1;
  573. ring++;
  574. }
  575. /* Process REO Exception ring interrupt */
  576. if (rx_err_mask) {
  577. work_done = dp_rx_err_process(soc,
  578. soc->reo_exception_ring.hal_srng,
  579. remaining_quota);
  580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  581. "REO Exception Ring: work_done %d budget %d",
  582. work_done, budget);
  583. budget -= work_done;
  584. if (budget <= 0) {
  585. goto budget_done;
  586. }
  587. remaining_quota = budget;
  588. }
  589. /* Process Rx WBM release ring interrupt */
  590. if (rx_wbm_rel_mask) {
  591. work_done = dp_rx_wbm_err_process(soc,
  592. soc->rx_rel_ring.hal_srng, remaining_quota);
  593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  594. "WBM Release Ring: work_done %d budget %d",
  595. work_done, budget);
  596. budget -= work_done;
  597. if (budget <= 0) {
  598. goto budget_done;
  599. }
  600. remaining_quota = budget;
  601. }
  602. /* Process Rx interrupts */
  603. if (rx_mask) {
  604. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  605. if (rx_mask & (1 << ring)) {
  606. work_done = dp_rx_process(int_ctx,
  607. soc->reo_dest_ring[ring].hal_srng,
  608. remaining_quota);
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  610. "rx mask 0x%x ring %d, work_done %d budget %d",
  611. rx_mask, ring, work_done, budget);
  612. budget -= work_done;
  613. if (budget <= 0)
  614. goto budget_done;
  615. remaining_quota = budget;
  616. }
  617. }
  618. }
  619. if (reo_status_mask)
  620. dp_reo_status_ring_handler(soc);
  621. /* Process LMAC interrupts */
  622. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  623. if (soc->pdev_list[ring] == NULL)
  624. continue;
  625. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  626. work_done = dp_mon_process(soc, ring, remaining_quota);
  627. budget -= work_done;
  628. remaining_quota = budget;
  629. }
  630. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  631. work_done = dp_rxdma_err_process(soc, ring,
  632. remaining_quota);
  633. budget -= work_done;
  634. }
  635. }
  636. qdf_lro_flush(int_ctx->lro_ctx);
  637. budget_done:
  638. return dp_budget - budget;
  639. }
  640. #ifdef DP_INTR_POLL_BASED
  641. /* dp_interrupt_timer()- timer poll for interrupts
  642. *
  643. * @arg: SoC Handle
  644. *
  645. * Return:
  646. *
  647. */
  648. static void dp_interrupt_timer(void *arg)
  649. {
  650. struct dp_soc *soc = (struct dp_soc *) arg;
  651. int i;
  652. if (qdf_atomic_read(&soc->cmn_init_done)) {
  653. for (i = 0;
  654. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  655. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  656. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  657. }
  658. }
  659. /*
  660. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  661. * @txrx_soc: DP SOC handle
  662. *
  663. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  664. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  665. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  666. *
  667. * Return: 0 for success. nonzero for failure.
  668. */
  669. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  670. {
  671. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  672. int i;
  673. soc->intr_mode = DP_INTR_POLL;
  674. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  675. soc->intr_ctx[i].dp_intr_id = i;
  676. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  677. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  678. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  679. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  680. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  681. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  682. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  683. soc->intr_ctx[i].soc = soc;
  684. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  685. }
  686. qdf_timer_init(soc->osdev, &soc->int_timer,
  687. dp_interrupt_timer, (void *)soc,
  688. QDF_TIMER_TYPE_WAKE_APPS);
  689. return QDF_STATUS_SUCCESS;
  690. }
  691. #if defined(CONFIG_MCL)
  692. extern int con_mode_monitor;
  693. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  694. /*
  695. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  696. * @txrx_soc: DP SOC handle
  697. *
  698. * Call the appropriate attach function based on the mode of operation.
  699. * This is a WAR for enabling monitor mode.
  700. *
  701. * Return: 0 for success. nonzero for failure.
  702. */
  703. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  704. {
  705. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  706. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  707. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  708. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  709. "%s: Poll mode", __func__);
  710. return dp_soc_interrupt_attach_poll(txrx_soc);
  711. } else {
  712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  713. "%s: Interrupt mode", __func__);
  714. return dp_soc_interrupt_attach(txrx_soc);
  715. }
  716. }
  717. #else
  718. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  719. {
  720. return dp_soc_interrupt_attach_poll(txrx_soc);
  721. }
  722. #endif
  723. #endif
  724. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  725. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  726. {
  727. int j;
  728. int num_irq = 0;
  729. int tx_mask =
  730. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  731. int rx_mask =
  732. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  733. int rx_mon_mask =
  734. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  735. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  736. soc->wlan_cfg_ctx, intr_ctx_num);
  737. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  738. soc->wlan_cfg_ctx, intr_ctx_num);
  739. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  740. soc->wlan_cfg_ctx, intr_ctx_num);
  741. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  742. soc->wlan_cfg_ctx, intr_ctx_num);
  743. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  744. if (tx_mask & (1 << j)) {
  745. irq_id_map[num_irq++] =
  746. (wbm2host_tx_completions_ring1 - j);
  747. }
  748. if (rx_mask & (1 << j)) {
  749. irq_id_map[num_irq++] =
  750. (reo2host_destination_ring1 - j);
  751. }
  752. if (rxdma2host_ring_mask & (1 << j)) {
  753. irq_id_map[num_irq++] =
  754. rxdma2host_destination_ring_mac1 -
  755. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  756. }
  757. if (rx_mon_mask & (1 << j)) {
  758. irq_id_map[num_irq++] =
  759. ppdu_end_interrupts_mac1 -
  760. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  761. }
  762. if (rx_wbm_rel_ring_mask & (1 << j))
  763. irq_id_map[num_irq++] = wbm2host_rx_release;
  764. if (rx_err_ring_mask & (1 << j))
  765. irq_id_map[num_irq++] = reo2host_exception;
  766. if (reo_status_ring_mask & (1 << j))
  767. irq_id_map[num_irq++] = reo2host_status;
  768. }
  769. *num_irq_r = num_irq;
  770. }
  771. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  772. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  773. int msi_vector_count, int msi_vector_start)
  774. {
  775. int tx_mask = wlan_cfg_get_tx_ring_mask(
  776. soc->wlan_cfg_ctx, intr_ctx_num);
  777. int rx_mask = wlan_cfg_get_rx_ring_mask(
  778. soc->wlan_cfg_ctx, intr_ctx_num);
  779. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  780. soc->wlan_cfg_ctx, intr_ctx_num);
  781. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  782. soc->wlan_cfg_ctx, intr_ctx_num);
  783. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  784. soc->wlan_cfg_ctx, intr_ctx_num);
  785. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  786. soc->wlan_cfg_ctx, intr_ctx_num);
  787. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  788. soc->wlan_cfg_ctx, intr_ctx_num);
  789. unsigned int vector =
  790. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  791. int num_irq = 0;
  792. soc->intr_mode = DP_INTR_MSI;
  793. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  794. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  795. irq_id_map[num_irq++] =
  796. pld_get_msi_irq(soc->osdev->dev, vector);
  797. *num_irq_r = num_irq;
  798. }
  799. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  800. int *irq_id_map, int *num_irq)
  801. {
  802. int msi_vector_count, ret;
  803. uint32_t msi_base_data, msi_vector_start;
  804. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  805. &msi_vector_count,
  806. &msi_base_data,
  807. &msi_vector_start);
  808. if (ret)
  809. return dp_soc_interrupt_map_calculate_integrated(soc,
  810. intr_ctx_num, irq_id_map, num_irq);
  811. else
  812. dp_soc_interrupt_map_calculate_msi(soc,
  813. intr_ctx_num, irq_id_map, num_irq,
  814. msi_vector_count, msi_vector_start);
  815. }
  816. /*
  817. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  818. * @txrx_soc: DP SOC handle
  819. *
  820. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  821. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  822. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  823. *
  824. * Return: 0 for success. nonzero for failure.
  825. */
  826. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  827. {
  828. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  829. int i = 0;
  830. int num_irq = 0;
  831. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  832. int ret = 0;
  833. /* Map of IRQ ids registered with one interrupt context */
  834. int irq_id_map[HIF_MAX_GRP_IRQ];
  835. int tx_mask =
  836. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  837. int rx_mask =
  838. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  839. int rx_mon_mask =
  840. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  841. int rx_err_ring_mask =
  842. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  843. int rx_wbm_rel_ring_mask =
  844. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  845. int reo_status_ring_mask =
  846. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  847. int rxdma2host_ring_mask =
  848. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  849. soc->intr_ctx[i].dp_intr_id = i;
  850. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  851. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  852. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  853. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  854. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  855. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  856. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  857. soc->intr_ctx[i].soc = soc;
  858. num_irq = 0;
  859. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  860. &num_irq);
  861. ret = hif_register_ext_group(soc->hif_handle,
  862. num_irq, irq_id_map, dp_service_srngs,
  863. &soc->intr_ctx[i], "dp_intr",
  864. HIF_EXEC_NAPI_TYPE, 2);
  865. if (ret) {
  866. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  867. FL("failed, ret = %d"), ret);
  868. return QDF_STATUS_E_FAILURE;
  869. }
  870. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  871. }
  872. hif_configure_ext_group_interrupts(soc->hif_handle);
  873. return QDF_STATUS_SUCCESS;
  874. }
  875. /*
  876. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  877. * @txrx_soc: DP SOC handle
  878. *
  879. * Return: void
  880. */
  881. static void dp_soc_interrupt_detach(void *txrx_soc)
  882. {
  883. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  884. int i;
  885. if (soc->intr_mode == DP_INTR_POLL) {
  886. qdf_timer_stop(&soc->int_timer);
  887. qdf_timer_free(&soc->int_timer);
  888. } else {
  889. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  890. }
  891. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  892. soc->intr_ctx[i].tx_ring_mask = 0;
  893. soc->intr_ctx[i].rx_ring_mask = 0;
  894. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  895. soc->intr_ctx[i].rx_err_ring_mask = 0;
  896. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  897. soc->intr_ctx[i].reo_status_ring_mask = 0;
  898. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  899. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  900. }
  901. }
  902. #define AVG_MAX_MPDUS_PER_TID 128
  903. #define AVG_TIDS_PER_CLIENT 2
  904. #define AVG_FLOWS_PER_TID 2
  905. #define AVG_MSDUS_PER_FLOW 128
  906. #define AVG_MSDUS_PER_MPDU 4
  907. /*
  908. * Allocate and setup link descriptor pool that will be used by HW for
  909. * various link and queue descriptors and managed by WBM
  910. */
  911. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  912. {
  913. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  914. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  915. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  916. uint32_t num_mpdus_per_link_desc =
  917. hal_num_mpdus_per_link_desc(soc->hal_soc);
  918. uint32_t num_msdus_per_link_desc =
  919. hal_num_msdus_per_link_desc(soc->hal_soc);
  920. uint32_t num_mpdu_links_per_queue_desc =
  921. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  922. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  923. uint32_t total_link_descs, total_mem_size;
  924. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  925. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  926. uint32_t num_link_desc_banks;
  927. uint32_t last_bank_size = 0;
  928. uint32_t entry_size, num_entries;
  929. int i;
  930. uint32_t desc_id = 0;
  931. /* Only Tx queue descriptors are allocated from common link descriptor
  932. * pool Rx queue descriptors are not included in this because (REO queue
  933. * extension descriptors) they are expected to be allocated contiguously
  934. * with REO queue descriptors
  935. */
  936. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  937. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  938. num_mpdu_queue_descs = num_mpdu_link_descs /
  939. num_mpdu_links_per_queue_desc;
  940. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  941. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  942. num_msdus_per_link_desc;
  943. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  944. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  945. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  946. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  947. /* Round up to power of 2 */
  948. total_link_descs = 1;
  949. while (total_link_descs < num_entries)
  950. total_link_descs <<= 1;
  951. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  952. FL("total_link_descs: %u, link_desc_size: %d"),
  953. total_link_descs, link_desc_size);
  954. total_mem_size = total_link_descs * link_desc_size;
  955. total_mem_size += link_desc_align;
  956. if (total_mem_size <= max_alloc_size) {
  957. num_link_desc_banks = 0;
  958. last_bank_size = total_mem_size;
  959. } else {
  960. num_link_desc_banks = (total_mem_size) /
  961. (max_alloc_size - link_desc_align);
  962. last_bank_size = total_mem_size %
  963. (max_alloc_size - link_desc_align);
  964. }
  965. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  966. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  967. total_mem_size, num_link_desc_banks);
  968. for (i = 0; i < num_link_desc_banks; i++) {
  969. soc->link_desc_banks[i].base_vaddr_unaligned =
  970. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  971. max_alloc_size,
  972. &(soc->link_desc_banks[i].base_paddr_unaligned));
  973. soc->link_desc_banks[i].size = max_alloc_size;
  974. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  975. soc->link_desc_banks[i].base_vaddr_unaligned) +
  976. ((unsigned long)(
  977. soc->link_desc_banks[i].base_vaddr_unaligned) %
  978. link_desc_align));
  979. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  980. soc->link_desc_banks[i].base_paddr_unaligned) +
  981. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  982. (unsigned long)(
  983. soc->link_desc_banks[i].base_vaddr_unaligned));
  984. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  986. FL("Link descriptor memory alloc failed"));
  987. goto fail;
  988. }
  989. }
  990. if (last_bank_size) {
  991. /* Allocate last bank in case total memory required is not exact
  992. * multiple of max_alloc_size
  993. */
  994. soc->link_desc_banks[i].base_vaddr_unaligned =
  995. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  996. last_bank_size,
  997. &(soc->link_desc_banks[i].base_paddr_unaligned));
  998. soc->link_desc_banks[i].size = last_bank_size;
  999. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1000. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1001. ((unsigned long)(
  1002. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1003. link_desc_align));
  1004. soc->link_desc_banks[i].base_paddr =
  1005. (unsigned long)(
  1006. soc->link_desc_banks[i].base_paddr_unaligned) +
  1007. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1008. (unsigned long)(
  1009. soc->link_desc_banks[i].base_vaddr_unaligned));
  1010. }
  1011. /* Allocate and setup link descriptor idle list for HW internal use */
  1012. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1013. total_mem_size = entry_size * total_link_descs;
  1014. if (total_mem_size <= max_alloc_size) {
  1015. void *desc;
  1016. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1017. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1018. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1019. FL("Link desc idle ring setup failed"));
  1020. goto fail;
  1021. }
  1022. hal_srng_access_start_unlocked(soc->hal_soc,
  1023. soc->wbm_idle_link_ring.hal_srng);
  1024. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1025. soc->link_desc_banks[i].base_paddr; i++) {
  1026. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1027. ((unsigned long)(
  1028. soc->link_desc_banks[i].base_vaddr) -
  1029. (unsigned long)(
  1030. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1031. / link_desc_size;
  1032. unsigned long paddr = (unsigned long)(
  1033. soc->link_desc_banks[i].base_paddr);
  1034. while (num_entries && (desc = hal_srng_src_get_next(
  1035. soc->hal_soc,
  1036. soc->wbm_idle_link_ring.hal_srng))) {
  1037. hal_set_link_desc_addr(desc,
  1038. LINK_DESC_COOKIE(desc_id, i), paddr);
  1039. num_entries--;
  1040. desc_id++;
  1041. paddr += link_desc_size;
  1042. }
  1043. }
  1044. hal_srng_access_end_unlocked(soc->hal_soc,
  1045. soc->wbm_idle_link_ring.hal_srng);
  1046. } else {
  1047. uint32_t num_scatter_bufs;
  1048. uint32_t num_entries_per_buf;
  1049. uint32_t rem_entries;
  1050. uint8_t *scatter_buf_ptr;
  1051. uint16_t scatter_buf_num;
  1052. soc->wbm_idle_scatter_buf_size =
  1053. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1054. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1055. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1056. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1057. soc->hal_soc, total_mem_size,
  1058. soc->wbm_idle_scatter_buf_size);
  1059. for (i = 0; i < num_scatter_bufs; i++) {
  1060. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1061. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1062. soc->wbm_idle_scatter_buf_size,
  1063. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1064. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1065. QDF_TRACE(QDF_MODULE_ID_DP,
  1066. QDF_TRACE_LEVEL_ERROR,
  1067. FL("Scatter list memory alloc failed"));
  1068. goto fail;
  1069. }
  1070. }
  1071. /* Populate idle list scatter buffers with link descriptor
  1072. * pointers
  1073. */
  1074. scatter_buf_num = 0;
  1075. scatter_buf_ptr = (uint8_t *)(
  1076. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1077. rem_entries = num_entries_per_buf;
  1078. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1079. soc->link_desc_banks[i].base_paddr; i++) {
  1080. uint32_t num_link_descs =
  1081. (soc->link_desc_banks[i].size -
  1082. ((unsigned long)(
  1083. soc->link_desc_banks[i].base_vaddr) -
  1084. (unsigned long)(
  1085. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1086. / link_desc_size;
  1087. unsigned long paddr = (unsigned long)(
  1088. soc->link_desc_banks[i].base_paddr);
  1089. while (num_link_descs) {
  1090. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1091. LINK_DESC_COOKIE(desc_id, i), paddr);
  1092. num_link_descs--;
  1093. desc_id++;
  1094. paddr += link_desc_size;
  1095. rem_entries--;
  1096. if (rem_entries) {
  1097. scatter_buf_ptr += entry_size;
  1098. } else {
  1099. rem_entries = num_entries_per_buf;
  1100. scatter_buf_num++;
  1101. if (scatter_buf_num >= num_scatter_bufs)
  1102. break;
  1103. scatter_buf_ptr = (uint8_t *)(
  1104. soc->wbm_idle_scatter_buf_base_vaddr[
  1105. scatter_buf_num]);
  1106. }
  1107. }
  1108. }
  1109. /* Setup link descriptor idle list in HW */
  1110. hal_setup_link_idle_list(soc->hal_soc,
  1111. soc->wbm_idle_scatter_buf_base_paddr,
  1112. soc->wbm_idle_scatter_buf_base_vaddr,
  1113. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1114. (uint32_t)(scatter_buf_ptr -
  1115. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1116. scatter_buf_num-1])), total_link_descs);
  1117. }
  1118. return 0;
  1119. fail:
  1120. if (soc->wbm_idle_link_ring.hal_srng) {
  1121. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1122. WBM_IDLE_LINK, 0);
  1123. }
  1124. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1125. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1126. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1127. soc->wbm_idle_scatter_buf_size,
  1128. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1129. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1130. }
  1131. }
  1132. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1133. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1134. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1135. soc->link_desc_banks[i].size,
  1136. soc->link_desc_banks[i].base_vaddr_unaligned,
  1137. soc->link_desc_banks[i].base_paddr_unaligned,
  1138. 0);
  1139. }
  1140. }
  1141. return QDF_STATUS_E_FAILURE;
  1142. }
  1143. /*
  1144. * Free link descriptor pool that was setup HW
  1145. */
  1146. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1147. {
  1148. int i;
  1149. if (soc->wbm_idle_link_ring.hal_srng) {
  1150. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1151. WBM_IDLE_LINK, 0);
  1152. }
  1153. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1154. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1155. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1156. soc->wbm_idle_scatter_buf_size,
  1157. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1158. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1159. }
  1160. }
  1161. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1162. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1163. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1164. soc->link_desc_banks[i].size,
  1165. soc->link_desc_banks[i].base_vaddr_unaligned,
  1166. soc->link_desc_banks[i].base_paddr_unaligned,
  1167. 0);
  1168. }
  1169. }
  1170. }
  1171. /* TODO: Following should be configurable */
  1172. #define WBM_RELEASE_RING_SIZE 64
  1173. #define TCL_CMD_RING_SIZE 32
  1174. #define TCL_STATUS_RING_SIZE 32
  1175. #if defined(QCA_WIFI_QCA6290)
  1176. #define REO_DST_RING_SIZE 1024
  1177. #else
  1178. #define REO_DST_RING_SIZE 2048
  1179. #endif
  1180. #define REO_REINJECT_RING_SIZE 32
  1181. #define RX_RELEASE_RING_SIZE 1024
  1182. #define REO_EXCEPTION_RING_SIZE 128
  1183. #define REO_CMD_RING_SIZE 32
  1184. #define REO_STATUS_RING_SIZE 32
  1185. #define RXDMA_BUF_RING_SIZE 1024
  1186. #define RXDMA_REFILL_RING_SIZE 2048
  1187. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1188. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1189. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1190. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1191. #define RXDMA_ERR_DST_RING_SIZE 1024
  1192. /*
  1193. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1194. * @soc: Datapath SOC handle
  1195. *
  1196. * This is a timer function used to age out stale WDS nodes from
  1197. * AST table
  1198. */
  1199. #ifdef FEATURE_WDS
  1200. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1201. {
  1202. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1203. struct dp_pdev *pdev;
  1204. struct dp_vdev *vdev;
  1205. struct dp_peer *peer;
  1206. struct dp_ast_entry *ase, *temp_ase;
  1207. int i;
  1208. qdf_spin_lock_bh(&soc->ast_lock);
  1209. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1210. pdev = soc->pdev_list[i];
  1211. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1212. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1213. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1214. /*
  1215. * Do not expire static ast entries
  1216. */
  1217. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1218. continue;
  1219. if (ase->is_active) {
  1220. ase->is_active = FALSE;
  1221. continue;
  1222. }
  1223. DP_STATS_INC(soc, ast.aged_out, 1);
  1224. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1225. pdev->osif_pdev,
  1226. ase->mac_addr.raw);
  1227. dp_peer_del_ast(soc, ase);
  1228. }
  1229. }
  1230. }
  1231. }
  1232. qdf_spin_unlock_bh(&soc->ast_lock);
  1233. if (qdf_atomic_read(&soc->cmn_init_done))
  1234. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1235. }
  1236. /*
  1237. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1238. * @soc: Datapath SOC handle
  1239. *
  1240. * Return: None
  1241. */
  1242. static void dp_soc_wds_attach(struct dp_soc *soc)
  1243. {
  1244. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1245. dp_wds_aging_timer_fn, (void *)soc,
  1246. QDF_TIMER_TYPE_WAKE_APPS);
  1247. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1248. }
  1249. /*
  1250. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1251. * @txrx_soc: DP SOC handle
  1252. *
  1253. * Return: None
  1254. */
  1255. static void dp_soc_wds_detach(struct dp_soc *soc)
  1256. {
  1257. qdf_timer_stop(&soc->wds_aging_timer);
  1258. qdf_timer_free(&soc->wds_aging_timer);
  1259. }
  1260. #else
  1261. static void dp_soc_wds_attach(struct dp_soc *soc)
  1262. {
  1263. }
  1264. static void dp_soc_wds_detach(struct dp_soc *soc)
  1265. {
  1266. }
  1267. #endif
  1268. /*
  1269. * dp_soc_reset_ring_map() - Reset cpu ring map
  1270. * @soc: Datapath soc handler
  1271. *
  1272. * This api resets the default cpu ring map
  1273. */
  1274. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1275. {
  1276. uint8_t i;
  1277. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1278. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1279. if (nss_config == 1) {
  1280. /*
  1281. * Setting Tx ring map for one nss offloaded radio
  1282. */
  1283. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1284. } else if (nss_config == 2) {
  1285. /*
  1286. * Setting Tx ring for two nss offloaded radios
  1287. */
  1288. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1289. } else {
  1290. /*
  1291. * Setting Tx ring map for all nss offloaded radios
  1292. */
  1293. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1294. }
  1295. }
  1296. }
  1297. /*
  1298. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1299. * @dp_soc - DP soc handle
  1300. * @ring_type - ring type
  1301. * @ring_num - ring_num
  1302. *
  1303. * return 0 or 1
  1304. */
  1305. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1306. {
  1307. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1308. uint8_t status = 0;
  1309. switch (ring_type) {
  1310. case WBM2SW_RELEASE:
  1311. case REO_DST:
  1312. status = ((nss_config) & (1 << ring_num));
  1313. break;
  1314. default:
  1315. break;
  1316. }
  1317. return status;
  1318. }
  1319. /*
  1320. * dp_soc_reset_intr_mask() - reset interrupt mask
  1321. * @dp_soc - DP Soc handle
  1322. *
  1323. * Return: Return void
  1324. */
  1325. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1326. {
  1327. uint8_t j;
  1328. int *grp_mask = NULL;
  1329. int group_number, mask, num_ring;
  1330. /* number of tx ring */
  1331. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1332. /*
  1333. * group mask for tx completion ring.
  1334. */
  1335. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1336. /* loop and reset the mask for only offloaded ring */
  1337. for (j = 0; j < num_ring; j++) {
  1338. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1339. continue;
  1340. }
  1341. /*
  1342. * Group number corresponding to tx offloaded ring.
  1343. */
  1344. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1345. if (group_number < 0) {
  1346. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1347. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1348. WBM2SW_RELEASE, j);
  1349. return;
  1350. }
  1351. /* reset the tx mask for offloaded ring */
  1352. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1353. mask &= (~(1 << j));
  1354. /*
  1355. * reset the interrupt mask for offloaded ring.
  1356. */
  1357. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1358. }
  1359. /* number of rx rings */
  1360. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1361. /*
  1362. * group mask for reo destination ring.
  1363. */
  1364. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1365. /* loop and reset the mask for only offloaded ring */
  1366. for (j = 0; j < num_ring; j++) {
  1367. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1368. continue;
  1369. }
  1370. /*
  1371. * Group number corresponding to rx offloaded ring.
  1372. */
  1373. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1374. if (group_number < 0) {
  1375. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1376. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1377. REO_DST, j);
  1378. return;
  1379. }
  1380. /* set the interrupt mask for offloaded ring */
  1381. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1382. mask &= (~(1 << j));
  1383. /*
  1384. * set the interrupt mask to zero for rx offloaded radio.
  1385. */
  1386. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1387. }
  1388. }
  1389. #ifdef IPA_OFFLOAD
  1390. /**
  1391. * dp_reo_remap_config() - configure reo remap register value based
  1392. * nss configuration.
  1393. * based on offload_radio value below remap configuration
  1394. * get applied.
  1395. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1396. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1397. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1398. * 3 - both Radios handled by NSS (remap not required)
  1399. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1400. *
  1401. * @remap1: output parameter indicates reo remap 1 register value
  1402. * @remap2: output parameter indicates reo remap 2 register value
  1403. * Return: bool type, true if remap is configured else false.
  1404. */
  1405. static bool dp_reo_remap_config(struct dp_soc *soc,
  1406. uint32_t *remap1,
  1407. uint32_t *remap2)
  1408. {
  1409. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1410. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1411. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1412. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1413. return true;
  1414. }
  1415. #else
  1416. static bool dp_reo_remap_config(struct dp_soc *soc,
  1417. uint32_t *remap1,
  1418. uint32_t *remap2)
  1419. {
  1420. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1421. switch (offload_radio) {
  1422. case 0:
  1423. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1424. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1425. (0x3 << 18) | (0x4 << 21)) << 8;
  1426. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1427. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1428. (0x3 << 18) | (0x4 << 21)) << 8;
  1429. break;
  1430. case 1:
  1431. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1432. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1433. (0x2 << 18) | (0x3 << 21)) << 8;
  1434. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1435. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1436. (0x4 << 18) | (0x2 << 21)) << 8;
  1437. break;
  1438. case 2:
  1439. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1440. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1441. (0x1 << 18) | (0x3 << 21)) << 8;
  1442. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1443. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1444. (0x4 << 18) | (0x1 << 21)) << 8;
  1445. break;
  1446. case 3:
  1447. /* return false if both radios are offloaded to NSS */
  1448. return false;
  1449. }
  1450. return true;
  1451. }
  1452. #endif
  1453. /*
  1454. * dp_soc_cmn_setup() - Common SoC level initializion
  1455. * @soc: Datapath SOC handle
  1456. *
  1457. * This is an internal function used to setup common SOC data structures,
  1458. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1459. */
  1460. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1461. {
  1462. int i;
  1463. struct hal_reo_params reo_params;
  1464. int tx_ring_size;
  1465. int tx_comp_ring_size;
  1466. if (qdf_atomic_read(&soc->cmn_init_done))
  1467. return 0;
  1468. if (dp_peer_find_attach(soc))
  1469. goto fail0;
  1470. if (dp_hw_link_desc_pool_setup(soc))
  1471. goto fail1;
  1472. /* Setup SRNG rings */
  1473. /* Common rings */
  1474. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1475. WBM_RELEASE_RING_SIZE)) {
  1476. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1477. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1478. goto fail1;
  1479. }
  1480. soc->num_tcl_data_rings = 0;
  1481. /* Tx data rings */
  1482. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1483. soc->num_tcl_data_rings =
  1484. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1485. tx_comp_ring_size =
  1486. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1487. tx_ring_size =
  1488. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1489. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1490. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1491. TCL_DATA, i, 0, tx_ring_size)) {
  1492. QDF_TRACE(QDF_MODULE_ID_DP,
  1493. QDF_TRACE_LEVEL_ERROR,
  1494. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1495. goto fail1;
  1496. }
  1497. /*
  1498. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1499. * count
  1500. */
  1501. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1502. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1503. QDF_TRACE(QDF_MODULE_ID_DP,
  1504. QDF_TRACE_LEVEL_ERROR,
  1505. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1506. goto fail1;
  1507. }
  1508. }
  1509. } else {
  1510. /* This will be incremented during per pdev ring setup */
  1511. soc->num_tcl_data_rings = 0;
  1512. }
  1513. if (dp_tx_soc_attach(soc)) {
  1514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1515. FL("dp_tx_soc_attach failed"));
  1516. goto fail1;
  1517. }
  1518. /* TCL command and status rings */
  1519. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1520. TCL_CMD_RING_SIZE)) {
  1521. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1522. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1523. goto fail1;
  1524. }
  1525. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1526. TCL_STATUS_RING_SIZE)) {
  1527. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1528. FL("dp_srng_setup failed for tcl_status_ring"));
  1529. goto fail1;
  1530. }
  1531. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1532. * descriptors
  1533. */
  1534. /* Rx data rings */
  1535. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1536. soc->num_reo_dest_rings =
  1537. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1538. QDF_TRACE(QDF_MODULE_ID_DP,
  1539. QDF_TRACE_LEVEL_ERROR,
  1540. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1541. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1542. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1543. i, 0, REO_DST_RING_SIZE)) {
  1544. QDF_TRACE(QDF_MODULE_ID_DP,
  1545. QDF_TRACE_LEVEL_ERROR,
  1546. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1547. goto fail1;
  1548. }
  1549. }
  1550. } else {
  1551. /* This will be incremented during per pdev ring setup */
  1552. soc->num_reo_dest_rings = 0;
  1553. }
  1554. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1555. /* REO reinjection ring */
  1556. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1557. REO_REINJECT_RING_SIZE)) {
  1558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1559. FL("dp_srng_setup failed for reo_reinject_ring"));
  1560. goto fail1;
  1561. }
  1562. /* Rx release ring */
  1563. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1564. RX_RELEASE_RING_SIZE)) {
  1565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1566. FL("dp_srng_setup failed for rx_rel_ring"));
  1567. goto fail1;
  1568. }
  1569. /* Rx exception ring */
  1570. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1571. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1572. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1573. FL("dp_srng_setup failed for reo_exception_ring"));
  1574. goto fail1;
  1575. }
  1576. /* REO command and status rings */
  1577. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1578. REO_CMD_RING_SIZE)) {
  1579. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1580. FL("dp_srng_setup failed for reo_cmd_ring"));
  1581. goto fail1;
  1582. }
  1583. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1584. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1585. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1586. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1587. REO_STATUS_RING_SIZE)) {
  1588. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1589. FL("dp_srng_setup failed for reo_status_ring"));
  1590. goto fail1;
  1591. }
  1592. qdf_spinlock_create(&soc->ast_lock);
  1593. dp_soc_wds_attach(soc);
  1594. /* Reset the cpu ring map if radio is NSS offloaded */
  1595. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1596. dp_soc_reset_cpu_ring_map(soc);
  1597. dp_soc_reset_intr_mask(soc);
  1598. }
  1599. /* Setup HW REO */
  1600. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1601. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1602. /*
  1603. * Reo ring remap is not required if both radios
  1604. * are offloaded to NSS
  1605. */
  1606. if (!dp_reo_remap_config(soc,
  1607. &reo_params.remap1,
  1608. &reo_params.remap2))
  1609. goto out;
  1610. reo_params.rx_hash_enabled = true;
  1611. }
  1612. out:
  1613. hal_reo_setup(soc->hal_soc, &reo_params);
  1614. qdf_atomic_set(&soc->cmn_init_done, 1);
  1615. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1616. return 0;
  1617. fail1:
  1618. /*
  1619. * Cleanup will be done as part of soc_detach, which will
  1620. * be called on pdev attach failure
  1621. */
  1622. fail0:
  1623. return QDF_STATUS_E_FAILURE;
  1624. }
  1625. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1626. static void dp_lro_hash_setup(struct dp_soc *soc)
  1627. {
  1628. struct cdp_lro_hash_config lro_hash;
  1629. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1630. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1631. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1632. FL("LRO disabled RX hash disabled"));
  1633. return;
  1634. }
  1635. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1636. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1637. lro_hash.lro_enable = 1;
  1638. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1639. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1640. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1641. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1642. }
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1644. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1645. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1646. LRO_IPV4_SEED_ARR_SZ));
  1647. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1648. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1649. LRO_IPV6_SEED_ARR_SZ));
  1650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  1651. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  1652. lro_hash.lro_enable, lro_hash.tcp_flag,
  1653. lro_hash.tcp_flag_mask);
  1654. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1655. QDF_TRACE_LEVEL_ERROR,
  1656. (void *)lro_hash.toeplitz_hash_ipv4,
  1657. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1658. LRO_IPV4_SEED_ARR_SZ));
  1659. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1660. QDF_TRACE_LEVEL_ERROR,
  1661. (void *)lro_hash.toeplitz_hash_ipv6,
  1662. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1663. LRO_IPV6_SEED_ARR_SZ));
  1664. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1665. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1666. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1667. (soc->osif_soc, &lro_hash);
  1668. }
  1669. /*
  1670. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1671. * @soc: data path SoC handle
  1672. * @pdev: Physical device handle
  1673. *
  1674. * Return: 0 - success, > 0 - failure
  1675. */
  1676. #ifdef QCA_HOST2FW_RXBUF_RING
  1677. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1678. struct dp_pdev *pdev)
  1679. {
  1680. int max_mac_rings =
  1681. wlan_cfg_get_num_mac_rings
  1682. (pdev->wlan_cfg_ctx);
  1683. int i;
  1684. for (i = 0; i < max_mac_rings; i++) {
  1685. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1686. "%s: pdev_id %d mac_id %d\n",
  1687. __func__, pdev->pdev_id, i);
  1688. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1689. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1690. QDF_TRACE(QDF_MODULE_ID_DP,
  1691. QDF_TRACE_LEVEL_ERROR,
  1692. FL("failed rx mac ring setup"));
  1693. return QDF_STATUS_E_FAILURE;
  1694. }
  1695. }
  1696. return QDF_STATUS_SUCCESS;
  1697. }
  1698. #else
  1699. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1700. struct dp_pdev *pdev)
  1701. {
  1702. return QDF_STATUS_SUCCESS;
  1703. }
  1704. #endif
  1705. /**
  1706. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1707. * @pdev - DP_PDEV handle
  1708. *
  1709. * Return: void
  1710. */
  1711. static inline void
  1712. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1713. {
  1714. uint8_t map_id;
  1715. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1716. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1717. sizeof(default_dscp_tid_map));
  1718. }
  1719. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1720. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1721. pdev->dscp_tid_map[map_id],
  1722. map_id);
  1723. }
  1724. }
  1725. /*
  1726. * dp_pdev_attach_wifi3() - attach txrx pdev
  1727. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1728. * @txrx_soc: Datapath SOC handle
  1729. * @htc_handle: HTC handle for host-target interface
  1730. * @qdf_osdev: QDF OS device
  1731. * @pdev_id: PDEV ID
  1732. *
  1733. * Return: DP PDEV handle on success, NULL on failure
  1734. */
  1735. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1736. struct cdp_cfg *ctrl_pdev,
  1737. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1738. {
  1739. int tx_ring_size;
  1740. int tx_comp_ring_size;
  1741. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1742. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1743. if (!pdev) {
  1744. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1745. FL("DP PDEV memory allocation failed"));
  1746. goto fail0;
  1747. }
  1748. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1749. if (!pdev->wlan_cfg_ctx) {
  1750. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1751. FL("pdev cfg_attach failed"));
  1752. qdf_mem_free(pdev);
  1753. goto fail0;
  1754. }
  1755. /*
  1756. * set nss pdev config based on soc config
  1757. */
  1758. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1759. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1760. pdev->soc = soc;
  1761. pdev->osif_pdev = ctrl_pdev;
  1762. pdev->pdev_id = pdev_id;
  1763. soc->pdev_list[pdev_id] = pdev;
  1764. soc->pdev_count++;
  1765. TAILQ_INIT(&pdev->vdev_list);
  1766. pdev->vdev_count = 0;
  1767. qdf_spinlock_create(&pdev->tx_mutex);
  1768. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1769. TAILQ_INIT(&pdev->neighbour_peers_list);
  1770. if (dp_soc_cmn_setup(soc)) {
  1771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1772. FL("dp_soc_cmn_setup failed"));
  1773. goto fail1;
  1774. }
  1775. /* Setup per PDEV TCL rings if configured */
  1776. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1777. tx_ring_size =
  1778. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1779. tx_comp_ring_size =
  1780. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1781. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1782. pdev_id, pdev_id, tx_ring_size)) {
  1783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1784. FL("dp_srng_setup failed for tcl_data_ring"));
  1785. goto fail1;
  1786. }
  1787. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1788. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1789. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1790. FL("dp_srng_setup failed for tx_comp_ring"));
  1791. goto fail1;
  1792. }
  1793. soc->num_tcl_data_rings++;
  1794. }
  1795. /* Tx specific init */
  1796. if (dp_tx_pdev_attach(pdev)) {
  1797. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1798. FL("dp_tx_pdev_attach failed"));
  1799. goto fail1;
  1800. }
  1801. /* Setup per PDEV REO rings if configured */
  1802. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1803. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1804. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1805. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1806. FL("dp_srng_setup failed for reo_dest_ringn"));
  1807. goto fail1;
  1808. }
  1809. soc->num_reo_dest_rings++;
  1810. }
  1811. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1812. RXDMA_REFILL_RING_SIZE)) {
  1813. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1814. FL("dp_srng_setup failed rx refill ring"));
  1815. goto fail1;
  1816. }
  1817. if (dp_rxdma_ring_setup(soc, pdev)) {
  1818. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1819. FL("RXDMA ring config failed"));
  1820. goto fail1;
  1821. }
  1822. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1823. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1824. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1825. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1826. goto fail1;
  1827. }
  1828. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1829. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1830. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1831. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1832. goto fail1;
  1833. }
  1834. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1835. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1836. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1838. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1839. goto fail1;
  1840. }
  1841. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1842. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1844. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1845. goto fail1;
  1846. }
  1847. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  1848. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1849. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1850. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1851. goto fail1;
  1852. }
  1853. /* Setup second Rx refill buffer ring */
  1854. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2,
  1855. pdev->pdev_id, RXDMA_REFILL_RING_SIZE)) {
  1856. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1857. FL("dp_srng_setup failed second rx refill ring"));
  1858. goto fail1;
  1859. }
  1860. if (dp_ipa_ring_resource_setup(soc, pdev))
  1861. goto fail1;
  1862. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  1863. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1864. FL("dp_ipa_uc_attach failed"));
  1865. goto fail1;
  1866. }
  1867. /* Rx specific init */
  1868. if (dp_rx_pdev_attach(pdev)) {
  1869. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1870. FL("dp_rx_pdev_attach failed"));
  1871. goto fail0;
  1872. }
  1873. DP_STATS_INIT(pdev);
  1874. #ifndef CONFIG_WIN
  1875. /* MCL */
  1876. dp_local_peer_id_pool_init(pdev);
  1877. #endif
  1878. dp_dscp_tid_map_setup(pdev);
  1879. /* Rx monitor mode specific init */
  1880. if (dp_rx_pdev_mon_attach(pdev)) {
  1881. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1882. "dp_rx_pdev_attach failed\n");
  1883. goto fail1;
  1884. }
  1885. if (dp_wdi_event_attach(pdev)) {
  1886. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1887. "dp_wdi_evet_attach failed\n");
  1888. goto fail1;
  1889. }
  1890. /* set the reo destination during initialization */
  1891. pdev->reo_dest = pdev->pdev_id + 1;
  1892. return (struct cdp_pdev *)pdev;
  1893. fail1:
  1894. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1895. fail0:
  1896. return NULL;
  1897. }
  1898. /*
  1899. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1900. * @soc: data path SoC handle
  1901. * @pdev: Physical device handle
  1902. *
  1903. * Return: void
  1904. */
  1905. #ifdef QCA_HOST2FW_RXBUF_RING
  1906. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1907. struct dp_pdev *pdev)
  1908. {
  1909. int max_mac_rings =
  1910. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1911. int i;
  1912. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1913. max_mac_rings : MAX_RX_MAC_RINGS;
  1914. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  1915. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  1916. RXDMA_BUF, 1);
  1917. }
  1918. #else
  1919. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1920. struct dp_pdev *pdev)
  1921. {
  1922. }
  1923. #endif
  1924. /*
  1925. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  1926. * @pdev: device object
  1927. *
  1928. * Return: void
  1929. */
  1930. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  1931. {
  1932. struct dp_neighbour_peer *peer = NULL;
  1933. struct dp_neighbour_peer *temp_peer = NULL;
  1934. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  1935. neighbour_peer_list_elem, temp_peer) {
  1936. /* delete this peer from the list */
  1937. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  1938. peer, neighbour_peer_list_elem);
  1939. qdf_mem_free(peer);
  1940. }
  1941. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  1942. }
  1943. /*
  1944. * dp_pdev_detach_wifi3() - detach txrx pdev
  1945. * @txrx_pdev: Datapath PDEV handle
  1946. * @force: Force detach
  1947. *
  1948. */
  1949. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  1950. {
  1951. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1952. struct dp_soc *soc = pdev->soc;
  1953. dp_wdi_event_detach(pdev);
  1954. dp_tx_pdev_detach(pdev);
  1955. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1956. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  1957. TCL_DATA, pdev->pdev_id);
  1958. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  1959. WBM2SW_RELEASE, pdev->pdev_id);
  1960. }
  1961. dp_rx_pdev_detach(pdev);
  1962. dp_rx_pdev_mon_detach(pdev);
  1963. dp_neighbour_peers_detach(pdev);
  1964. qdf_spinlock_destroy(&pdev->tx_mutex);
  1965. dp_ipa_uc_detach(soc, pdev);
  1966. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2);
  1967. /* Cleanup per PDEV REO rings if configured */
  1968. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1969. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  1970. REO_DST, pdev->pdev_id);
  1971. }
  1972. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  1973. dp_rxdma_ring_cleanup(soc, pdev);
  1974. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  1975. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  1976. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  1977. RXDMA_MONITOR_STATUS, 0);
  1978. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  1979. RXDMA_MONITOR_DESC, 0);
  1980. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  1981. soc->pdev_list[pdev->pdev_id] = NULL;
  1982. soc->pdev_count--;
  1983. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  1984. qdf_mem_free(pdev);
  1985. }
  1986. /*
  1987. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  1988. * @soc: DP SOC handle
  1989. */
  1990. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  1991. {
  1992. struct reo_desc_list_node *desc;
  1993. struct dp_rx_tid *rx_tid;
  1994. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  1995. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  1996. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  1997. rx_tid = &desc->rx_tid;
  1998. qdf_mem_unmap_nbytes_single(soc->osdev,
  1999. rx_tid->hw_qdesc_paddr,
  2000. QDF_DMA_BIDIRECTIONAL,
  2001. rx_tid->hw_qdesc_alloc_size);
  2002. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2003. qdf_mem_free(desc);
  2004. }
  2005. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2006. qdf_list_destroy(&soc->reo_desc_freelist);
  2007. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2008. }
  2009. /*
  2010. * dp_soc_detach_wifi3() - Detach txrx SOC
  2011. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2012. */
  2013. static void dp_soc_detach_wifi3(void *txrx_soc)
  2014. {
  2015. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2016. int i;
  2017. qdf_atomic_set(&soc->cmn_init_done, 0);
  2018. qdf_flush_work(&soc->htt_stats.work);
  2019. qdf_disable_work(&soc->htt_stats.work);
  2020. /* Free pending htt stats messages */
  2021. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2022. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2023. if (soc->pdev_list[i])
  2024. dp_pdev_detach_wifi3(
  2025. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2026. }
  2027. dp_peer_find_detach(soc);
  2028. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2029. * SW descriptors
  2030. */
  2031. /* Free the ring memories */
  2032. /* Common rings */
  2033. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2034. dp_tx_soc_detach(soc);
  2035. /* Tx data rings */
  2036. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2037. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2038. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2039. TCL_DATA, i);
  2040. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2041. WBM2SW_RELEASE, i);
  2042. }
  2043. }
  2044. /* TCL command and status rings */
  2045. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2046. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2047. /* Rx data rings */
  2048. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2049. soc->num_reo_dest_rings =
  2050. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2051. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2052. /* TODO: Get number of rings and ring sizes
  2053. * from wlan_cfg
  2054. */
  2055. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2056. REO_DST, i);
  2057. }
  2058. }
  2059. /* REO reinjection ring */
  2060. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2061. /* Rx release ring */
  2062. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2063. /* Rx exception ring */
  2064. /* TODO: Better to store ring_type and ring_num in
  2065. * dp_srng during setup
  2066. */
  2067. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2068. /* REO command and status rings */
  2069. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2070. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2071. dp_hw_link_desc_pool_cleanup(soc);
  2072. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2073. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2074. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2075. htt_soc_detach(soc->htt_handle);
  2076. dp_reo_cmdlist_destroy(soc);
  2077. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2078. dp_reo_desc_freelist_destroy(soc);
  2079. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2080. dp_soc_wds_detach(soc);
  2081. qdf_spinlock_destroy(&soc->ast_lock);
  2082. qdf_mem_free(soc);
  2083. }
  2084. /*
  2085. * dp_rxdma_ring_config() - configure the RX DMA rings
  2086. *
  2087. * This function is used to configure the MAC rings.
  2088. * On MCL host provides buffers in Host2FW ring
  2089. * FW refills (copies) buffers to the ring and updates
  2090. * ring_idx in register
  2091. *
  2092. * @soc: data path SoC handle
  2093. *
  2094. * Return: void
  2095. */
  2096. #ifdef QCA_HOST2FW_RXBUF_RING
  2097. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2098. {
  2099. int i;
  2100. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2101. struct dp_pdev *pdev = soc->pdev_list[i];
  2102. if (pdev) {
  2103. int mac_id = 0;
  2104. int j;
  2105. bool dbs_enable = 0;
  2106. int max_mac_rings =
  2107. wlan_cfg_get_num_mac_rings
  2108. (pdev->wlan_cfg_ctx);
  2109. htt_srng_setup(soc->htt_handle, 0,
  2110. pdev->rx_refill_buf_ring.hal_srng,
  2111. RXDMA_BUF);
  2112. if (pdev->rx_refill_buf_ring2.hal_srng)
  2113. htt_srng_setup(soc->htt_handle, 0,
  2114. pdev->rx_refill_buf_ring2.hal_srng,
  2115. RXDMA_BUF);
  2116. if (soc->cdp_soc.ol_ops->
  2117. is_hw_dbs_2x2_capable) {
  2118. dbs_enable = soc->cdp_soc.ol_ops->
  2119. is_hw_dbs_2x2_capable(soc->psoc);
  2120. }
  2121. if (dbs_enable) {
  2122. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2123. QDF_TRACE_LEVEL_ERROR,
  2124. FL("DBS enabled max_mac_rings %d\n"),
  2125. max_mac_rings);
  2126. } else {
  2127. max_mac_rings = 1;
  2128. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2129. QDF_TRACE_LEVEL_ERROR,
  2130. FL("DBS disabled, max_mac_rings %d\n"),
  2131. max_mac_rings);
  2132. }
  2133. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2134. FL("pdev_id %d max_mac_rings %d\n"),
  2135. pdev->pdev_id, max_mac_rings);
  2136. for (j = 0; j < max_mac_rings; j++) {
  2137. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2138. QDF_TRACE_LEVEL_ERROR,
  2139. FL("mac_id %d\n"), mac_id);
  2140. htt_srng_setup(soc->htt_handle, mac_id,
  2141. pdev->rx_mac_buf_ring[j]
  2142. .hal_srng,
  2143. RXDMA_BUF);
  2144. mac_id++;
  2145. }
  2146. /* Configure monitor mode rings */
  2147. htt_srng_setup(soc->htt_handle, i,
  2148. pdev->rxdma_mon_buf_ring.hal_srng,
  2149. RXDMA_MONITOR_BUF);
  2150. htt_srng_setup(soc->htt_handle, i,
  2151. pdev->rxdma_mon_dst_ring.hal_srng,
  2152. RXDMA_MONITOR_DST);
  2153. htt_srng_setup(soc->htt_handle, i,
  2154. pdev->rxdma_mon_status_ring.hal_srng,
  2155. RXDMA_MONITOR_STATUS);
  2156. htt_srng_setup(soc->htt_handle, i,
  2157. pdev->rxdma_mon_desc_ring.hal_srng,
  2158. RXDMA_MONITOR_DESC);
  2159. htt_srng_setup(soc->htt_handle, i,
  2160. pdev->rxdma_err_dst_ring.hal_srng,
  2161. RXDMA_DST);
  2162. }
  2163. }
  2164. }
  2165. #else
  2166. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2167. {
  2168. int i;
  2169. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2170. struct dp_pdev *pdev = soc->pdev_list[i];
  2171. if (pdev) {
  2172. htt_srng_setup(soc->htt_handle, i,
  2173. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2174. htt_srng_setup(soc->htt_handle, i,
  2175. pdev->rxdma_mon_buf_ring.hal_srng,
  2176. RXDMA_MONITOR_BUF);
  2177. htt_srng_setup(soc->htt_handle, i,
  2178. pdev->rxdma_mon_dst_ring.hal_srng,
  2179. RXDMA_MONITOR_DST);
  2180. htt_srng_setup(soc->htt_handle, i,
  2181. pdev->rxdma_mon_status_ring.hal_srng,
  2182. RXDMA_MONITOR_STATUS);
  2183. htt_srng_setup(soc->htt_handle, i,
  2184. pdev->rxdma_mon_desc_ring.hal_srng,
  2185. RXDMA_MONITOR_DESC);
  2186. htt_srng_setup(soc->htt_handle, i,
  2187. pdev->rxdma_err_dst_ring.hal_srng,
  2188. RXDMA_DST);
  2189. }
  2190. }
  2191. }
  2192. #endif
  2193. /*
  2194. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2195. * @txrx_soc: Datapath SOC handle
  2196. */
  2197. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2198. {
  2199. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2200. htt_soc_attach_target(soc->htt_handle);
  2201. dp_rxdma_ring_config(soc);
  2202. DP_STATS_INIT(soc);
  2203. /* initialize work queue for stats processing */
  2204. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2205. return 0;
  2206. }
  2207. /*
  2208. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2209. * @txrx_soc: Datapath SOC handle
  2210. */
  2211. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2212. {
  2213. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2214. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2215. }
  2216. /*
  2217. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2218. * @txrx_soc: Datapath SOC handle
  2219. * @nss_cfg: nss config
  2220. */
  2221. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2222. {
  2223. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2224. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2225. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2226. FL("nss-wifi<0> nss config is enabled"));
  2227. }
  2228. /*
  2229. * dp_vdev_attach_wifi3() - attach txrx vdev
  2230. * @txrx_pdev: Datapath PDEV handle
  2231. * @vdev_mac_addr: MAC address of the virtual interface
  2232. * @vdev_id: VDEV Id
  2233. * @wlan_op_mode: VDEV operating mode
  2234. *
  2235. * Return: DP VDEV handle on success, NULL on failure
  2236. */
  2237. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2238. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2239. {
  2240. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2241. struct dp_soc *soc = pdev->soc;
  2242. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2243. int tx_ring_size;
  2244. if (!vdev) {
  2245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2246. FL("DP VDEV memory allocation failed"));
  2247. goto fail0;
  2248. }
  2249. vdev->pdev = pdev;
  2250. vdev->vdev_id = vdev_id;
  2251. vdev->opmode = op_mode;
  2252. vdev->osdev = soc->osdev;
  2253. vdev->osif_rx = NULL;
  2254. vdev->osif_rsim_rx_decap = NULL;
  2255. vdev->osif_get_key = NULL;
  2256. vdev->osif_rx_mon = NULL;
  2257. vdev->osif_tx_free_ext = NULL;
  2258. vdev->osif_vdev = NULL;
  2259. vdev->delete.pending = 0;
  2260. vdev->safemode = 0;
  2261. vdev->drop_unenc = 1;
  2262. #ifdef notyet
  2263. vdev->filters_num = 0;
  2264. #endif
  2265. qdf_mem_copy(
  2266. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2267. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2268. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2269. vdev->dscp_tid_map_id = 0;
  2270. vdev->mcast_enhancement_en = 0;
  2271. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2272. /* TODO: Initialize default HTT meta data that will be used in
  2273. * TCL descriptors for packets transmitted from this VDEV
  2274. */
  2275. TAILQ_INIT(&vdev->peer_list);
  2276. /* add this vdev into the pdev's list */
  2277. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2278. pdev->vdev_count++;
  2279. dp_tx_vdev_attach(vdev);
  2280. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2281. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2282. goto fail1;
  2283. if ((soc->intr_mode == DP_INTR_POLL) &&
  2284. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2285. if (pdev->vdev_count == 1)
  2286. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2287. }
  2288. dp_lro_hash_setup(soc);
  2289. /* LRO */
  2290. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2291. wlan_op_mode_sta == vdev->opmode)
  2292. vdev->lro_enable = true;
  2293. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2294. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2295. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2296. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2297. DP_STATS_INIT(vdev);
  2298. return (struct cdp_vdev *)vdev;
  2299. fail1:
  2300. dp_tx_vdev_detach(vdev);
  2301. qdf_mem_free(vdev);
  2302. fail0:
  2303. return NULL;
  2304. }
  2305. /**
  2306. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2307. * @vdev: Datapath VDEV handle
  2308. * @osif_vdev: OSIF vdev handle
  2309. * @txrx_ops: Tx and Rx operations
  2310. *
  2311. * Return: DP VDEV handle on success, NULL on failure
  2312. */
  2313. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2314. void *osif_vdev,
  2315. struct ol_txrx_ops *txrx_ops)
  2316. {
  2317. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2318. vdev->osif_vdev = osif_vdev;
  2319. vdev->osif_rx = txrx_ops->rx.rx;
  2320. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2321. vdev->osif_get_key = txrx_ops->get_key;
  2322. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2323. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2324. #ifdef notyet
  2325. #if ATH_SUPPORT_WAPI
  2326. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2327. #endif
  2328. #endif
  2329. #ifdef UMAC_SUPPORT_PROXY_ARP
  2330. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2331. #endif
  2332. vdev->me_convert = txrx_ops->me_convert;
  2333. /* TODO: Enable the following once Tx code is integrated */
  2334. txrx_ops->tx.tx = dp_tx_send;
  2335. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2336. "DP Vdev Register success");
  2337. }
  2338. /*
  2339. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2340. * @txrx_vdev: Datapath VDEV handle
  2341. * @callback: Callback OL_IF on completion of detach
  2342. * @cb_context: Callback context
  2343. *
  2344. */
  2345. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2346. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2347. {
  2348. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2349. struct dp_pdev *pdev = vdev->pdev;
  2350. struct dp_soc *soc = pdev->soc;
  2351. /* preconditions */
  2352. qdf_assert(vdev);
  2353. /* remove the vdev from its parent pdev's list */
  2354. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2355. /*
  2356. * Use peer_ref_mutex while accessing peer_list, in case
  2357. * a peer is in the process of being removed from the list.
  2358. */
  2359. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2360. /* check that the vdev has no peers allocated */
  2361. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2362. /* debug print - will be removed later */
  2363. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2364. FL("not deleting vdev object %pK (%pM)"
  2365. "until deletion finishes for all its peers"),
  2366. vdev, vdev->mac_addr.raw);
  2367. /* indicate that the vdev needs to be deleted */
  2368. vdev->delete.pending = 1;
  2369. vdev->delete.callback = callback;
  2370. vdev->delete.context = cb_context;
  2371. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2372. return;
  2373. }
  2374. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2375. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2376. vdev->vdev_id);
  2377. dp_tx_vdev_detach(vdev);
  2378. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2379. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2380. qdf_mem_free(vdev);
  2381. if (callback)
  2382. callback(cb_context);
  2383. }
  2384. /*
  2385. * dp_peer_create_wifi3() - attach txrx peer
  2386. * @txrx_vdev: Datapath VDEV handle
  2387. * @peer_mac_addr: Peer MAC address
  2388. *
  2389. * Return: DP peeer handle on success, NULL on failure
  2390. */
  2391. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2392. uint8_t *peer_mac_addr)
  2393. {
  2394. struct dp_peer *peer;
  2395. int i;
  2396. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2397. struct dp_pdev *pdev;
  2398. struct dp_soc *soc;
  2399. /* preconditions */
  2400. qdf_assert(vdev);
  2401. qdf_assert(peer_mac_addr);
  2402. pdev = vdev->pdev;
  2403. soc = pdev->soc;
  2404. #ifdef notyet
  2405. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2406. soc->mempool_ol_ath_peer);
  2407. #else
  2408. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2409. #endif
  2410. if (!peer)
  2411. return NULL; /* failure */
  2412. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2413. TAILQ_INIT(&peer->ast_entry_list);
  2414. /* store provided params */
  2415. peer->vdev = vdev;
  2416. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2417. qdf_spinlock_create(&peer->peer_info_lock);
  2418. qdf_mem_copy(
  2419. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2420. /* TODO: See of rx_opt_proc is really required */
  2421. peer->rx_opt_proc = soc->rx_opt_proc;
  2422. /* initialize the peer_id */
  2423. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2424. peer->peer_ids[i] = HTT_INVALID_PEER;
  2425. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2426. qdf_atomic_init(&peer->ref_cnt);
  2427. /* keep one reference for attach */
  2428. qdf_atomic_inc(&peer->ref_cnt);
  2429. /* add this peer into the vdev's list */
  2430. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2431. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2432. /* TODO: See if hash based search is required */
  2433. dp_peer_find_hash_add(soc, peer);
  2434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2435. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2436. vdev, peer, peer->mac_addr.raw,
  2437. qdf_atomic_read(&peer->ref_cnt));
  2438. /*
  2439. * For every peer MAp message search and set if bss_peer
  2440. */
  2441. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2443. "vdev bss_peer!!!!");
  2444. peer->bss_peer = 1;
  2445. vdev->vap_bss_peer = peer;
  2446. }
  2447. #ifndef CONFIG_WIN
  2448. dp_local_peer_id_alloc(pdev, peer);
  2449. #endif
  2450. DP_STATS_INIT(peer);
  2451. return (void *)peer;
  2452. }
  2453. /*
  2454. * dp_peer_setup_wifi3() - initialize the peer
  2455. * @vdev_hdl: virtual device object
  2456. * @peer: Peer object
  2457. *
  2458. * Return: void
  2459. */
  2460. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2461. {
  2462. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2463. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2464. struct dp_pdev *pdev;
  2465. struct dp_soc *soc;
  2466. bool hash_based = 0;
  2467. enum cdp_host_reo_dest_ring reo_dest;
  2468. /* preconditions */
  2469. qdf_assert(vdev);
  2470. qdf_assert(peer);
  2471. pdev = vdev->pdev;
  2472. soc = pdev->soc;
  2473. dp_peer_rx_init(pdev, peer);
  2474. peer->last_assoc_rcvd = 0;
  2475. peer->last_disassoc_rcvd = 0;
  2476. peer->last_deauth_rcvd = 0;
  2477. /*
  2478. * hash based steering is disabled for Radios which are offloaded
  2479. * to NSS
  2480. */
  2481. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2482. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2483. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2484. FL("hash based steering for pdev: %d is %d\n"),
  2485. pdev->pdev_id, hash_based);
  2486. /*
  2487. * Below line of code will ensure the proper reo_dest ring is choosen
  2488. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2489. */
  2490. reo_dest = pdev->reo_dest;
  2491. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2492. /* TODO: Check the destination ring number to be passed to FW */
  2493. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2494. pdev->osif_pdev, peer->mac_addr.raw,
  2495. peer->vdev->vdev_id, hash_based, reo_dest);
  2496. }
  2497. return;
  2498. }
  2499. /*
  2500. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2501. * @vdev_handle: virtual device object
  2502. * @htt_pkt_type: type of pkt
  2503. *
  2504. * Return: void
  2505. */
  2506. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2507. enum htt_cmn_pkt_type val)
  2508. {
  2509. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2510. vdev->tx_encap_type = val;
  2511. }
  2512. /*
  2513. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2514. * @vdev_handle: virtual device object
  2515. * @htt_pkt_type: type of pkt
  2516. *
  2517. * Return: void
  2518. */
  2519. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2520. enum htt_cmn_pkt_type val)
  2521. {
  2522. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2523. vdev->rx_decap_type = val;
  2524. }
  2525. /*
  2526. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2527. * @pdev_handle: physical device object
  2528. * @val: reo destination ring index (1 - 4)
  2529. *
  2530. * Return: void
  2531. */
  2532. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2533. enum cdp_host_reo_dest_ring val)
  2534. {
  2535. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2536. if (pdev)
  2537. pdev->reo_dest = val;
  2538. }
  2539. /*
  2540. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2541. * @pdev_handle: physical device object
  2542. *
  2543. * Return: reo destination ring index
  2544. */
  2545. static enum cdp_host_reo_dest_ring
  2546. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2547. {
  2548. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2549. if (pdev)
  2550. return pdev->reo_dest;
  2551. else
  2552. return cdp_host_reo_dest_ring_unknown;
  2553. }
  2554. #ifdef QCA_SUPPORT_SON
  2555. static void dp_son_peer_authorize(struct dp_peer *peer)
  2556. {
  2557. struct dp_soc *soc;
  2558. soc = peer->vdev->pdev->soc;
  2559. peer->peer_bs_inact_flag = 0;
  2560. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2561. return;
  2562. }
  2563. #else
  2564. static void dp_son_peer_authorize(struct dp_peer *peer)
  2565. {
  2566. return;
  2567. }
  2568. #endif
  2569. /*
  2570. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2571. * @pdev_handle: device object
  2572. * @val: value to be set
  2573. *
  2574. * Return: void
  2575. */
  2576. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2577. uint32_t val)
  2578. {
  2579. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2580. /* Enable/Disable smart mesh filtering. This flag will be checked
  2581. * during rx processing to check if packets are from NAC clients.
  2582. */
  2583. pdev->filter_neighbour_peers = val;
  2584. return 0;
  2585. }
  2586. /*
  2587. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2588. * address for smart mesh filtering
  2589. * @pdev_handle: device object
  2590. * @cmd: Add/Del command
  2591. * @macaddr: nac client mac address
  2592. *
  2593. * Return: void
  2594. */
  2595. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2596. uint32_t cmd, uint8_t *macaddr)
  2597. {
  2598. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2599. struct dp_neighbour_peer *peer = NULL;
  2600. if (!macaddr)
  2601. goto fail0;
  2602. /* Store address of NAC (neighbour peer) which will be checked
  2603. * against TA of received packets.
  2604. */
  2605. if (cmd == DP_NAC_PARAM_ADD) {
  2606. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2607. sizeof(*peer));
  2608. if (!peer) {
  2609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2610. FL("DP neighbour peer node memory allocation failed"));
  2611. goto fail0;
  2612. }
  2613. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2614. macaddr, DP_MAC_ADDR_LEN);
  2615. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2616. /* add this neighbour peer into the list */
  2617. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2618. neighbour_peer_list_elem);
  2619. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2620. return 1;
  2621. } else if (cmd == DP_NAC_PARAM_DEL) {
  2622. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2623. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2624. neighbour_peer_list_elem) {
  2625. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2626. macaddr, DP_MAC_ADDR_LEN)) {
  2627. /* delete this peer from the list */
  2628. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2629. peer, neighbour_peer_list_elem);
  2630. qdf_mem_free(peer);
  2631. break;
  2632. }
  2633. }
  2634. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2635. return 1;
  2636. }
  2637. fail0:
  2638. return 0;
  2639. }
  2640. /*
  2641. * dp_get_sec_type() - Get the security type
  2642. * @peer: Datapath peer handle
  2643. * @sec_idx: Security id (mcast, ucast)
  2644. *
  2645. * return sec_type: Security type
  2646. */
  2647. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2648. {
  2649. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2650. return dpeer->security[sec_idx].sec_type;
  2651. }
  2652. /*
  2653. * dp_peer_authorize() - authorize txrx peer
  2654. * @peer_handle: Datapath peer handle
  2655. * @authorize
  2656. *
  2657. */
  2658. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2659. {
  2660. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2661. struct dp_soc *soc;
  2662. if (peer != NULL) {
  2663. soc = peer->vdev->pdev->soc;
  2664. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2665. dp_son_peer_authorize(peer);
  2666. peer->authorize = authorize ? 1 : 0;
  2667. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2668. }
  2669. }
  2670. /*
  2671. * dp_peer_unref_delete() - unref and delete peer
  2672. * @peer_handle: Datapath peer handle
  2673. *
  2674. */
  2675. void dp_peer_unref_delete(void *peer_handle)
  2676. {
  2677. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2678. struct dp_vdev *vdev = peer->vdev;
  2679. struct dp_pdev *pdev = vdev->pdev;
  2680. struct dp_soc *soc = pdev->soc;
  2681. struct dp_peer *tmppeer;
  2682. int found = 0;
  2683. uint16_t peer_id;
  2684. /*
  2685. * Hold the lock all the way from checking if the peer ref count
  2686. * is zero until the peer references are removed from the hash
  2687. * table and vdev list (if the peer ref count is zero).
  2688. * This protects against a new HL tx operation starting to use the
  2689. * peer object just after this function concludes it's done being used.
  2690. * Furthermore, the lock needs to be held while checking whether the
  2691. * vdev's list of peers is empty, to make sure that list is not modified
  2692. * concurrently with the empty check.
  2693. */
  2694. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2695. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2696. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2697. peer, qdf_atomic_read(&peer->ref_cnt));
  2698. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2699. peer_id = peer->peer_ids[0];
  2700. /*
  2701. * Make sure that the reference to the peer in
  2702. * peer object map is removed
  2703. */
  2704. if (peer_id != HTT_INVALID_PEER)
  2705. soc->peer_id_to_obj_map[peer_id] = NULL;
  2706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2707. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2708. /* remove the reference to the peer from the hash table */
  2709. dp_peer_find_hash_remove(soc, peer);
  2710. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2711. if (tmppeer == peer) {
  2712. found = 1;
  2713. break;
  2714. }
  2715. }
  2716. if (found) {
  2717. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2718. peer_list_elem);
  2719. } else {
  2720. /*Ignoring the remove operation as peer not found*/
  2721. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2722. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2723. peer, vdev, &peer->vdev->peer_list);
  2724. }
  2725. /* cleanup the peer data */
  2726. dp_peer_cleanup(vdev, peer);
  2727. /* check whether the parent vdev has no peers left */
  2728. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2729. /*
  2730. * Now that there are no references to the peer, we can
  2731. * release the peer reference lock.
  2732. */
  2733. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2734. /*
  2735. * Check if the parent vdev was waiting for its peers
  2736. * to be deleted, in order for it to be deleted too.
  2737. */
  2738. if (vdev->delete.pending) {
  2739. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2740. vdev->delete.callback;
  2741. void *vdev_delete_context =
  2742. vdev->delete.context;
  2743. QDF_TRACE(QDF_MODULE_ID_DP,
  2744. QDF_TRACE_LEVEL_INFO_HIGH,
  2745. FL("deleting vdev object %pK (%pM)"
  2746. " - its last peer is done"),
  2747. vdev, vdev->mac_addr.raw);
  2748. /* all peers are gone, go ahead and delete it */
  2749. qdf_mem_free(vdev);
  2750. if (vdev_delete_cb)
  2751. vdev_delete_cb(vdev_delete_context);
  2752. }
  2753. } else {
  2754. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2755. }
  2756. #ifdef notyet
  2757. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2758. #else
  2759. qdf_mem_free(peer);
  2760. #endif
  2761. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2762. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2763. vdev->vdev_id, peer->mac_addr.raw);
  2764. }
  2765. } else {
  2766. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2767. }
  2768. }
  2769. /*
  2770. * dp_peer_detach_wifi3() – Detach txrx peer
  2771. * @peer_handle: Datapath peer handle
  2772. *
  2773. */
  2774. static void dp_peer_delete_wifi3(void *peer_handle)
  2775. {
  2776. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2777. /* redirect the peer's rx delivery function to point to a
  2778. * discard func
  2779. */
  2780. peer->rx_opt_proc = dp_rx_discard;
  2781. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2782. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2783. #ifndef CONFIG_WIN
  2784. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2785. #endif
  2786. qdf_spinlock_destroy(&peer->peer_info_lock);
  2787. /*
  2788. * Remove the reference added during peer_attach.
  2789. * The peer will still be left allocated until the
  2790. * PEER_UNMAP message arrives to remove the other
  2791. * reference, added by the PEER_MAP message.
  2792. */
  2793. dp_peer_unref_delete(peer_handle);
  2794. }
  2795. /*
  2796. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2797. * @peer_handle: Datapath peer handle
  2798. *
  2799. */
  2800. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2801. {
  2802. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2803. return vdev->mac_addr.raw;
  2804. }
  2805. /*
  2806. * dp_vdev_set_wds() - Enable per packet stats
  2807. * @vdev_handle: DP VDEV handle
  2808. * @val: value
  2809. *
  2810. * Return: none
  2811. */
  2812. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2813. {
  2814. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2815. vdev->wds_enabled = val;
  2816. return 0;
  2817. }
  2818. /*
  2819. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2820. * @peer_handle: Datapath peer handle
  2821. *
  2822. */
  2823. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2824. uint8_t vdev_id)
  2825. {
  2826. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2827. struct dp_vdev *vdev = NULL;
  2828. if (qdf_unlikely(!pdev))
  2829. return NULL;
  2830. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2831. if (vdev->vdev_id == vdev_id)
  2832. break;
  2833. }
  2834. return (struct cdp_vdev *)vdev;
  2835. }
  2836. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2837. {
  2838. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2839. return vdev->opmode;
  2840. }
  2841. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2842. {
  2843. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2844. struct dp_pdev *pdev = vdev->pdev;
  2845. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2846. }
  2847. /**
  2848. * dp_reset_monitor_mode() - Disable monitor mode
  2849. * @pdev_handle: Datapath PDEV handle
  2850. *
  2851. * Return: 0 on success, not 0 on failure
  2852. */
  2853. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  2854. {
  2855. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2856. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2857. struct dp_soc *soc;
  2858. uint8_t pdev_id;
  2859. pdev_id = pdev->pdev_id;
  2860. soc = pdev->soc;
  2861. pdev->monitor_vdev = NULL;
  2862. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  2863. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2864. pdev->rxdma_mon_buf_ring.hal_srng,
  2865. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2866. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2867. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2868. RX_BUFFER_SIZE, &htt_tlv_filter);
  2869. return 0;
  2870. }
  2871. /**
  2872. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2873. * @vdev_handle: Datapath VDEV handle
  2874. * @smart_monitor: Flag to denote if its smart monitor mode
  2875. *
  2876. * Return: 0 on success, not 0 on failure
  2877. */
  2878. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2879. uint8_t smart_monitor)
  2880. {
  2881. /* Many monitor VAPs can exists in a system but only one can be up at
  2882. * anytime
  2883. */
  2884. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2885. struct dp_pdev *pdev;
  2886. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2887. struct dp_soc *soc;
  2888. uint8_t pdev_id;
  2889. qdf_assert(vdev);
  2890. pdev = vdev->pdev;
  2891. pdev_id = pdev->pdev_id;
  2892. soc = pdev->soc;
  2893. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2894. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  2895. pdev, pdev_id, soc, vdev);
  2896. /*Check if current pdev's monitor_vdev exists */
  2897. if (pdev->monitor_vdev) {
  2898. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2899. "vdev=%pK\n", vdev);
  2900. qdf_assert(vdev);
  2901. }
  2902. pdev->monitor_vdev = vdev;
  2903. /* If smart monitor mode, do not configure monitor ring */
  2904. if (smart_monitor)
  2905. return QDF_STATUS_SUCCESS;
  2906. htt_tlv_filter.mpdu_start = 1;
  2907. htt_tlv_filter.msdu_start = 1;
  2908. htt_tlv_filter.packet = 1;
  2909. htt_tlv_filter.msdu_end = 1;
  2910. htt_tlv_filter.mpdu_end = 1;
  2911. htt_tlv_filter.packet_header = 1;
  2912. htt_tlv_filter.attention = 1;
  2913. htt_tlv_filter.ppdu_start = 0;
  2914. htt_tlv_filter.ppdu_end = 0;
  2915. htt_tlv_filter.ppdu_end_user_stats = 0;
  2916. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  2917. htt_tlv_filter.ppdu_end_status_done = 0;
  2918. htt_tlv_filter.header_per_msdu = 1;
  2919. htt_tlv_filter.enable_fp = 1;
  2920. htt_tlv_filter.enable_md = 0;
  2921. htt_tlv_filter.enable_mo = 1;
  2922. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2923. pdev->rxdma_mon_buf_ring.hal_srng,
  2924. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2925. htt_tlv_filter.mpdu_start = 1;
  2926. htt_tlv_filter.msdu_start = 1;
  2927. htt_tlv_filter.packet = 0;
  2928. htt_tlv_filter.msdu_end = 1;
  2929. htt_tlv_filter.mpdu_end = 1;
  2930. htt_tlv_filter.packet_header = 1;
  2931. htt_tlv_filter.attention = 1;
  2932. htt_tlv_filter.ppdu_start = 1;
  2933. htt_tlv_filter.ppdu_end = 1;
  2934. htt_tlv_filter.ppdu_end_user_stats = 1;
  2935. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  2936. htt_tlv_filter.ppdu_end_status_done = 1;
  2937. htt_tlv_filter.header_per_msdu = 0;
  2938. htt_tlv_filter.enable_fp = 1;
  2939. htt_tlv_filter.enable_md = 0;
  2940. htt_tlv_filter.enable_mo = 1;
  2941. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2942. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2943. RX_BUFFER_SIZE, &htt_tlv_filter);
  2944. return QDF_STATUS_SUCCESS;
  2945. }
  2946. #ifdef MESH_MODE_SUPPORT
  2947. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  2948. {
  2949. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2950. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2951. FL("val %d"), val);
  2952. vdev->mesh_vdev = val;
  2953. }
  2954. /*
  2955. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  2956. * @vdev_hdl: virtual device object
  2957. * @val: value to be set
  2958. *
  2959. * Return: void
  2960. */
  2961. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  2962. {
  2963. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2964. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2965. FL("val %d"), val);
  2966. vdev->mesh_rx_filter = val;
  2967. }
  2968. #endif
  2969. /*
  2970. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  2971. * Current scope is bar recieved count
  2972. *
  2973. * @pdev_handle: DP_PDEV handle
  2974. *
  2975. * Return: void
  2976. */
  2977. #define STATS_PROC_TIMEOUT (HZ/10)
  2978. static void
  2979. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  2980. {
  2981. struct dp_vdev *vdev;
  2982. struct dp_peer *peer;
  2983. uint32_t waitcnt;
  2984. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2985. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2986. if (!peer) {
  2987. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2988. FL("DP Invalid Peer refernce"));
  2989. return;
  2990. }
  2991. waitcnt = 0;
  2992. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  2993. while (!(qdf_atomic_read(&(pdev->stats.cmd_complete)))
  2994. && waitcnt < 10) {
  2995. schedule_timeout_interruptible(
  2996. STATS_PROC_TIMEOUT);
  2997. waitcnt++;
  2998. }
  2999. qdf_atomic_set(&(pdev->stats.cmd_complete), 0);
  3000. }
  3001. }
  3002. }
  3003. /**
  3004. * dp_rx_bar_stats_cb(): BAR received stats callback
  3005. * @soc: SOC handle
  3006. * @cb_ctxt: Call back context
  3007. * @reo_status: Reo status
  3008. *
  3009. * return: void
  3010. */
  3011. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3012. union hal_reo_status *reo_status)
  3013. {
  3014. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3015. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3016. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3017. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  3018. queue_status->header.status);
  3019. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3020. return;
  3021. }
  3022. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3023. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3024. }
  3025. /**
  3026. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3027. * @vdev: DP VDEV handle
  3028. *
  3029. * return: void
  3030. */
  3031. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3032. {
  3033. struct dp_peer *peer = NULL;
  3034. struct dp_soc *soc = vdev->pdev->soc;
  3035. int i;
  3036. uint8_t pream_type;
  3037. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3038. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3039. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3040. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3041. for (i = 0; i < MAX_MCS; i++) {
  3042. DP_STATS_AGGR(vdev, peer,
  3043. tx.pkt_type[pream_type].mcs_count[i]);
  3044. DP_STATS_AGGR(vdev, peer,
  3045. rx.pkt_type[pream_type].mcs_count[i]);
  3046. }
  3047. }
  3048. for (i = 0; i < MAX_BW; i++) {
  3049. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3050. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3051. }
  3052. for (i = 0; i < SS_COUNT; i++)
  3053. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3054. for (i = 0; i < WME_AC_MAX; i++) {
  3055. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3056. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3057. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3058. }
  3059. for (i = 0; i < MAX_GI; i++) {
  3060. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3061. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3062. }
  3063. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3064. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3065. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3066. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3067. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3068. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3069. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3070. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3071. DP_STATS_AGGR(vdev, peer, tx.retries);
  3072. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3073. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3074. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3075. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3076. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3077. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3078. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3079. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3080. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3081. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3082. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3083. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3084. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3085. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3086. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3087. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3088. peer->stats.rx.multicast.num;
  3089. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3090. peer->stats.rx.multicast.bytes;
  3091. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3092. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3093. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3094. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3095. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3096. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3097. vdev->stats.tx.last_ack_rssi =
  3098. peer->stats.tx.last_ack_rssi;
  3099. }
  3100. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3101. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3102. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3103. }
  3104. /**
  3105. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3106. * @pdev: DP PDEV handle
  3107. *
  3108. * return: void
  3109. */
  3110. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3111. {
  3112. struct dp_vdev *vdev = NULL;
  3113. uint8_t i;
  3114. uint8_t pream_type;
  3115. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3116. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3117. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3118. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3119. dp_aggregate_vdev_stats(vdev);
  3120. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3121. for (i = 0; i < MAX_MCS; i++) {
  3122. DP_STATS_AGGR(pdev, vdev,
  3123. tx.pkt_type[pream_type].mcs_count[i]);
  3124. DP_STATS_AGGR(pdev, vdev,
  3125. rx.pkt_type[pream_type].mcs_count[i]);
  3126. }
  3127. }
  3128. for (i = 0; i < MAX_BW; i++) {
  3129. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3130. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3131. }
  3132. for (i = 0; i < SS_COUNT; i++)
  3133. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3134. for (i = 0; i < WME_AC_MAX; i++) {
  3135. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3136. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3137. DP_STATS_AGGR(pdev, vdev,
  3138. tx.excess_retries_ac[i]);
  3139. }
  3140. for (i = 0; i < MAX_GI; i++) {
  3141. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3142. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3143. }
  3144. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3145. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3146. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3147. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3148. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3149. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3150. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3151. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3152. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3153. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3154. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3155. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3156. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3157. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3158. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3159. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3160. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3161. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3162. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3163. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3164. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3165. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3166. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3167. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3168. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3169. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3170. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3171. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3172. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3173. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3174. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3175. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3176. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3177. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3178. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3179. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3180. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3181. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3182. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3183. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3184. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3185. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3186. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3187. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3188. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3189. DP_STATS_AGGR(pdev, vdev,
  3190. tx_i.mcast_en.dropped_map_error);
  3191. DP_STATS_AGGR(pdev, vdev,
  3192. tx_i.mcast_en.dropped_self_mac);
  3193. DP_STATS_AGGR(pdev, vdev,
  3194. tx_i.mcast_en.dropped_send_fail);
  3195. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3196. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3197. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3198. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3199. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3200. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3201. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3202. pdev->stats.tx_i.dropped.dma_error +
  3203. pdev->stats.tx_i.dropped.ring_full +
  3204. pdev->stats.tx_i.dropped.enqueue_fail +
  3205. pdev->stats.tx_i.dropped.desc_na +
  3206. pdev->stats.tx_i.dropped.res_full;
  3207. pdev->stats.tx.last_ack_rssi =
  3208. vdev->stats.tx.last_ack_rssi;
  3209. pdev->stats.tx_i.tso.num_seg =
  3210. vdev->stats.tx_i.tso.num_seg;
  3211. }
  3212. }
  3213. /**
  3214. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3215. * @pdev: DP_PDEV Handle
  3216. *
  3217. * Return:void
  3218. */
  3219. static inline void
  3220. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3221. {
  3222. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3223. DP_PRINT_STATS("Received From Stack:");
  3224. DP_PRINT_STATS(" Packets = %d",
  3225. pdev->stats.tx_i.rcvd.num);
  3226. DP_PRINT_STATS(" Bytes = %d",
  3227. pdev->stats.tx_i.rcvd.bytes);
  3228. DP_PRINT_STATS("Processed:");
  3229. DP_PRINT_STATS(" Packets = %d",
  3230. pdev->stats.tx_i.processed.num);
  3231. DP_PRINT_STATS(" Bytes = %d",
  3232. pdev->stats.tx_i.processed.bytes);
  3233. DP_PRINT_STATS("Completions:");
  3234. DP_PRINT_STATS(" Packets = %d",
  3235. pdev->stats.tx.comp_pkt.num);
  3236. DP_PRINT_STATS(" Bytes = %d",
  3237. pdev->stats.tx.comp_pkt.bytes);
  3238. DP_PRINT_STATS("Dropped:");
  3239. DP_PRINT_STATS(" Total = %d",
  3240. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3241. DP_PRINT_STATS(" Dma_map_error = %d",
  3242. pdev->stats.tx_i.dropped.dma_error);
  3243. DP_PRINT_STATS(" Ring Full = %d",
  3244. pdev->stats.tx_i.dropped.ring_full);
  3245. DP_PRINT_STATS(" Descriptor Not available = %d",
  3246. pdev->stats.tx_i.dropped.desc_na);
  3247. DP_PRINT_STATS(" HW enqueue failed= %d",
  3248. pdev->stats.tx_i.dropped.enqueue_fail);
  3249. DP_PRINT_STATS(" Resources Full = %d",
  3250. pdev->stats.tx_i.dropped.res_full);
  3251. DP_PRINT_STATS(" FW removed = %d",
  3252. pdev->stats.tx.dropped.fw_rem);
  3253. DP_PRINT_STATS(" FW removed transmitted = %d",
  3254. pdev->stats.tx.dropped.fw_rem_tx);
  3255. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3256. pdev->stats.tx.dropped.fw_rem_notx);
  3257. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3258. pdev->stats.tx.dropped.age_out);
  3259. DP_PRINT_STATS("Scatter Gather:");
  3260. DP_PRINT_STATS(" Packets = %d",
  3261. pdev->stats.tx_i.sg.sg_pkt.num);
  3262. DP_PRINT_STATS(" Bytes = %d",
  3263. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3264. DP_PRINT_STATS(" Dropped By Host = %d",
  3265. pdev->stats.tx_i.sg.dropped_host);
  3266. DP_PRINT_STATS(" Dropped By Target = %d",
  3267. pdev->stats.tx_i.sg.dropped_target);
  3268. DP_PRINT_STATS("TSO:");
  3269. DP_PRINT_STATS(" Number of Segments = %d",
  3270. pdev->stats.tx_i.tso.num_seg);
  3271. DP_PRINT_STATS(" Packets = %d",
  3272. pdev->stats.tx_i.tso.tso_pkt.num);
  3273. DP_PRINT_STATS(" Bytes = %d",
  3274. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3275. DP_PRINT_STATS(" Dropped By Host = %d",
  3276. pdev->stats.tx_i.tso.dropped_host);
  3277. DP_PRINT_STATS("Mcast Enhancement:");
  3278. DP_PRINT_STATS(" Packets = %d",
  3279. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3280. DP_PRINT_STATS(" Bytes = %d",
  3281. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3282. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3283. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3284. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3285. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3286. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3287. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3288. DP_PRINT_STATS(" Unicast sent = %d",
  3289. pdev->stats.tx_i.mcast_en.ucast);
  3290. DP_PRINT_STATS("Raw:");
  3291. DP_PRINT_STATS(" Packets = %d",
  3292. pdev->stats.tx_i.raw.raw_pkt.num);
  3293. DP_PRINT_STATS(" Bytes = %d",
  3294. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3295. DP_PRINT_STATS(" DMA map error = %d",
  3296. pdev->stats.tx_i.raw.dma_map_error);
  3297. DP_PRINT_STATS("Reinjected:");
  3298. DP_PRINT_STATS(" Packets = %d",
  3299. pdev->stats.tx_i.reinject_pkts.num);
  3300. DP_PRINT_STATS("Bytes = %d\n",
  3301. pdev->stats.tx_i.reinject_pkts.bytes);
  3302. DP_PRINT_STATS("Inspected:");
  3303. DP_PRINT_STATS(" Packets = %d",
  3304. pdev->stats.tx_i.inspect_pkts.num);
  3305. DP_PRINT_STATS(" Bytes = %d",
  3306. pdev->stats.tx_i.inspect_pkts.bytes);
  3307. }
  3308. /**
  3309. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3310. * @pdev: DP_PDEV Handle
  3311. *
  3312. * Return: void
  3313. */
  3314. static inline void
  3315. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3316. {
  3317. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3318. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3319. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3320. pdev->stats.rx.rcvd_reo[0].num,
  3321. pdev->stats.rx.rcvd_reo[1].num,
  3322. pdev->stats.rx.rcvd_reo[2].num,
  3323. pdev->stats.rx.rcvd_reo[3].num);
  3324. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3325. pdev->stats.rx.rcvd_reo[0].bytes,
  3326. pdev->stats.rx.rcvd_reo[1].bytes,
  3327. pdev->stats.rx.rcvd_reo[2].bytes,
  3328. pdev->stats.rx.rcvd_reo[3].bytes);
  3329. DP_PRINT_STATS("Replenished:");
  3330. DP_PRINT_STATS(" Packets = %d",
  3331. pdev->stats.replenish.pkts.num);
  3332. DP_PRINT_STATS(" Bytes = %d",
  3333. pdev->stats.replenish.pkts.bytes);
  3334. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3335. pdev->stats.buf_freelist);
  3336. DP_PRINT_STATS("Dropped:");
  3337. DP_PRINT_STATS(" msdu_not_done = %d",
  3338. pdev->stats.dropped.msdu_not_done);
  3339. DP_PRINT_STATS("Sent To Stack:");
  3340. DP_PRINT_STATS(" Packets = %d",
  3341. pdev->stats.rx.to_stack.num);
  3342. DP_PRINT_STATS(" Bytes = %d",
  3343. pdev->stats.rx.to_stack.bytes);
  3344. DP_PRINT_STATS("Multicast/Broadcast:");
  3345. DP_PRINT_STATS(" Packets = %d",
  3346. pdev->stats.rx.multicast.num);
  3347. DP_PRINT_STATS(" Bytes = %d",
  3348. pdev->stats.rx.multicast.bytes);
  3349. DP_PRINT_STATS("Errors:");
  3350. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3351. pdev->stats.replenish.rxdma_err);
  3352. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3353. pdev->stats.err.desc_alloc_fail);
  3354. /* Get bar_recv_cnt */
  3355. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  3356. DP_PRINT_STATS("BAR Received Count: = %d",
  3357. pdev->stats.rx.bar_recv_cnt);
  3358. }
  3359. /**
  3360. * dp_print_soc_tx_stats(): Print SOC level stats
  3361. * @soc DP_SOC Handle
  3362. *
  3363. * Return: void
  3364. */
  3365. static inline void
  3366. dp_print_soc_tx_stats(struct dp_soc *soc)
  3367. {
  3368. DP_PRINT_STATS("SOC Tx Stats:\n");
  3369. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3370. soc->stats.tx.desc_in_use);
  3371. DP_PRINT_STATS("Invalid peer:");
  3372. DP_PRINT_STATS(" Packets = %d",
  3373. soc->stats.tx.tx_invalid_peer.num);
  3374. DP_PRINT_STATS(" Bytes = %d",
  3375. soc->stats.tx.tx_invalid_peer.bytes);
  3376. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3377. soc->stats.tx.tcl_ring_full[0],
  3378. soc->stats.tx.tcl_ring_full[1],
  3379. soc->stats.tx.tcl_ring_full[2]);
  3380. }
  3381. /**
  3382. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3383. * @soc: DP_SOC Handle
  3384. *
  3385. * Return:void
  3386. */
  3387. static inline void
  3388. dp_print_soc_rx_stats(struct dp_soc *soc)
  3389. {
  3390. uint32_t i;
  3391. char reo_error[DP_REO_ERR_LENGTH];
  3392. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3393. uint8_t index = 0;
  3394. DP_PRINT_STATS("SOC Rx Stats:\n");
  3395. DP_PRINT_STATS("Errors:\n");
  3396. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3397. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3398. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3399. DP_PRINT_STATS("Invalid RBM = %d",
  3400. soc->stats.rx.err.invalid_rbm);
  3401. DP_PRINT_STATS("Invalid Vdev = %d",
  3402. soc->stats.rx.err.invalid_vdev);
  3403. DP_PRINT_STATS("Invalid Pdev = %d",
  3404. soc->stats.rx.err.invalid_pdev);
  3405. DP_PRINT_STATS("Invalid Peer = %d",
  3406. soc->stats.rx.err.rx_invalid_peer.num);
  3407. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3408. soc->stats.rx.err.hal_ring_access_fail);
  3409. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3410. index += qdf_snprint(&rxdma_error[index],
  3411. DP_RXDMA_ERR_LENGTH - index,
  3412. " %d", soc->stats.rx.err.rxdma_error[i]);
  3413. }
  3414. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3415. rxdma_error);
  3416. index = 0;
  3417. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3418. index += qdf_snprint(&reo_error[index],
  3419. DP_REO_ERR_LENGTH - index,
  3420. " %d", soc->stats.rx.err.reo_error[i]);
  3421. }
  3422. DP_PRINT_STATS("REO Error(0-14):%s",
  3423. reo_error);
  3424. }
  3425. /**
  3426. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3427. * @soc: DP_SOC handle
  3428. * @srng: DP_SRNG handle
  3429. * @ring_name: SRNG name
  3430. *
  3431. * Return: void
  3432. */
  3433. static inline void
  3434. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3435. char *ring_name)
  3436. {
  3437. uint32_t tailp;
  3438. uint32_t headp;
  3439. if (srng->hal_srng != NULL) {
  3440. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3441. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3442. ring_name, headp, tailp);
  3443. }
  3444. }
  3445. /**
  3446. * dp_print_ring_stats(): Print tail and head pointer
  3447. * @pdev: DP_PDEV handle
  3448. *
  3449. * Return:void
  3450. */
  3451. static inline void
  3452. dp_print_ring_stats(struct dp_pdev *pdev)
  3453. {
  3454. uint32_t i;
  3455. char ring_name[STR_MAXLEN + 1];
  3456. dp_print_ring_stat_from_hal(pdev->soc,
  3457. &pdev->soc->reo_exception_ring,
  3458. "Reo Exception Ring");
  3459. dp_print_ring_stat_from_hal(pdev->soc,
  3460. &pdev->soc->reo_reinject_ring,
  3461. "Reo Inject Ring");
  3462. dp_print_ring_stat_from_hal(pdev->soc,
  3463. &pdev->soc->reo_cmd_ring,
  3464. "Reo Command Ring");
  3465. dp_print_ring_stat_from_hal(pdev->soc,
  3466. &pdev->soc->reo_status_ring,
  3467. "Reo Status Ring");
  3468. dp_print_ring_stat_from_hal(pdev->soc,
  3469. &pdev->soc->rx_rel_ring,
  3470. "Rx Release ring");
  3471. dp_print_ring_stat_from_hal(pdev->soc,
  3472. &pdev->soc->tcl_cmd_ring,
  3473. "Tcl command Ring");
  3474. dp_print_ring_stat_from_hal(pdev->soc,
  3475. &pdev->soc->tcl_status_ring,
  3476. "Tcl Status Ring");
  3477. dp_print_ring_stat_from_hal(pdev->soc,
  3478. &pdev->soc->wbm_desc_rel_ring,
  3479. "Wbm Desc Rel Ring");
  3480. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3481. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3482. dp_print_ring_stat_from_hal(pdev->soc,
  3483. &pdev->soc->reo_dest_ring[i],
  3484. ring_name);
  3485. }
  3486. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3487. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3488. dp_print_ring_stat_from_hal(pdev->soc,
  3489. &pdev->soc->tcl_data_ring[i],
  3490. ring_name);
  3491. }
  3492. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3493. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3494. dp_print_ring_stat_from_hal(pdev->soc,
  3495. &pdev->soc->tx_comp_ring[i],
  3496. ring_name);
  3497. }
  3498. dp_print_ring_stat_from_hal(pdev->soc,
  3499. &pdev->rx_refill_buf_ring,
  3500. "Rx Refill Buf Ring");
  3501. dp_print_ring_stat_from_hal(pdev->soc,
  3502. &pdev->rx_refill_buf_ring2,
  3503. "Second Rx Refill Buf Ring");
  3504. dp_print_ring_stat_from_hal(pdev->soc,
  3505. &pdev->rxdma_mon_buf_ring,
  3506. "Rxdma Mon Buf Ring");
  3507. dp_print_ring_stat_from_hal(pdev->soc,
  3508. &pdev->rxdma_mon_dst_ring,
  3509. "Rxdma Mon Dst Ring");
  3510. dp_print_ring_stat_from_hal(pdev->soc,
  3511. &pdev->rxdma_mon_status_ring,
  3512. "Rxdma Mon Status Ring");
  3513. dp_print_ring_stat_from_hal(pdev->soc,
  3514. &pdev->rxdma_mon_desc_ring,
  3515. "Rxdma mon desc Ring");
  3516. dp_print_ring_stat_from_hal(pdev->soc,
  3517. &pdev->rxdma_err_dst_ring,
  3518. "Rxdma err dst ring");
  3519. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3520. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3521. dp_print_ring_stat_from_hal(pdev->soc,
  3522. &pdev->rx_mac_buf_ring[i],
  3523. ring_name);
  3524. }
  3525. }
  3526. /**
  3527. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3528. * @vdev: DP_VDEV handle
  3529. *
  3530. * Return:void
  3531. */
  3532. static inline void
  3533. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3534. {
  3535. struct dp_peer *peer = NULL;
  3536. DP_STATS_CLR(vdev->pdev);
  3537. DP_STATS_CLR(vdev->pdev->soc);
  3538. DP_STATS_CLR(vdev);
  3539. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3540. if (!peer)
  3541. return;
  3542. DP_STATS_CLR(peer);
  3543. }
  3544. }
  3545. /**
  3546. * dp_print_rx_rates(): Print Rx rate stats
  3547. * @vdev: DP_VDEV handle
  3548. *
  3549. * Return:void
  3550. */
  3551. static inline void
  3552. dp_print_rx_rates(struct dp_vdev *vdev)
  3553. {
  3554. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3555. uint8_t i, mcs, pkt_type;
  3556. uint8_t index = 0;
  3557. char nss[DP_NSS_LENGTH];
  3558. DP_PRINT_STATS("Rx Rate Info:\n");
  3559. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3560. index = 0;
  3561. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3562. if (!dp_rate_string[pkt_type][mcs].valid)
  3563. continue;
  3564. DP_PRINT_STATS(" %s = %d",
  3565. dp_rate_string[pkt_type][mcs].mcs_type,
  3566. pdev->stats.rx.pkt_type[pkt_type].
  3567. mcs_count[mcs]);
  3568. }
  3569. DP_PRINT_STATS("\n");
  3570. }
  3571. index = 0;
  3572. for (i = 0; i < SS_COUNT; i++) {
  3573. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3574. " %d", pdev->stats.rx.nss[i]);
  3575. }
  3576. DP_PRINT_STATS("NSS(0-7) = %s",
  3577. nss);
  3578. DP_PRINT_STATS("SGI ="
  3579. " 0.8us %d,"
  3580. " 0.4us %d,"
  3581. " 1.6us %d,"
  3582. " 3.2us %d,",
  3583. pdev->stats.rx.sgi_count[0],
  3584. pdev->stats.rx.sgi_count[1],
  3585. pdev->stats.rx.sgi_count[2],
  3586. pdev->stats.rx.sgi_count[3]);
  3587. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3588. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3589. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3590. DP_PRINT_STATS("Reception Type ="
  3591. " SU: %d,"
  3592. " MU_MIMO:%d,"
  3593. " MU_OFDMA:%d,"
  3594. " MU_OFDMA_MIMO:%d\n",
  3595. pdev->stats.rx.reception_type[0],
  3596. pdev->stats.rx.reception_type[1],
  3597. pdev->stats.rx.reception_type[2],
  3598. pdev->stats.rx.reception_type[3]);
  3599. DP_PRINT_STATS("Aggregation:\n");
  3600. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3601. pdev->stats.rx.ampdu_cnt);
  3602. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3603. pdev->stats.rx.non_ampdu_cnt);
  3604. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3605. pdev->stats.rx.amsdu_cnt);
  3606. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3607. pdev->stats.rx.non_amsdu_cnt);
  3608. }
  3609. /**
  3610. * dp_print_tx_rates(): Print tx rates
  3611. * @vdev: DP_VDEV handle
  3612. *
  3613. * Return:void
  3614. */
  3615. static inline void
  3616. dp_print_tx_rates(struct dp_vdev *vdev)
  3617. {
  3618. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3619. uint8_t mcs, pkt_type;
  3620. uint32_t index;
  3621. DP_PRINT_STATS("Tx Rate Info:\n");
  3622. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3623. index = 0;
  3624. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3625. if (!dp_rate_string[pkt_type][mcs].valid)
  3626. continue;
  3627. DP_PRINT_STATS(" %s = %d",
  3628. dp_rate_string[pkt_type][mcs].mcs_type,
  3629. pdev->stats.tx.pkt_type[pkt_type].
  3630. mcs_count[mcs]);
  3631. }
  3632. DP_PRINT_STATS("\n");
  3633. }
  3634. DP_PRINT_STATS("SGI ="
  3635. " 0.8us %d"
  3636. " 0.4us %d"
  3637. " 1.6us %d"
  3638. " 3.2us %d",
  3639. pdev->stats.tx.sgi_count[0],
  3640. pdev->stats.tx.sgi_count[1],
  3641. pdev->stats.tx.sgi_count[2],
  3642. pdev->stats.tx.sgi_count[3]);
  3643. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3644. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3645. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3646. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3647. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3648. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3649. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3650. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3651. DP_PRINT_STATS("Aggregation:\n");
  3652. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3653. pdev->stats.tx.amsdu_cnt);
  3654. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3655. pdev->stats.tx.non_amsdu_cnt);
  3656. }
  3657. /**
  3658. * dp_print_peer_stats():print peer stats
  3659. * @peer: DP_PEER handle
  3660. *
  3661. * return void
  3662. */
  3663. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3664. {
  3665. uint8_t i, mcs, pkt_type;
  3666. uint32_t index;
  3667. char nss[DP_NSS_LENGTH];
  3668. DP_PRINT_STATS("Node Tx Stats:\n");
  3669. DP_PRINT_STATS("Total Packet Completions = %d",
  3670. peer->stats.tx.comp_pkt.num);
  3671. DP_PRINT_STATS("Total Bytes Completions = %d",
  3672. peer->stats.tx.comp_pkt.bytes);
  3673. DP_PRINT_STATS("Success Packets = %d",
  3674. peer->stats.tx.tx_success.num);
  3675. DP_PRINT_STATS("Success Bytes = %d",
  3676. peer->stats.tx.tx_success.bytes);
  3677. DP_PRINT_STATS("Packets Failed = %d",
  3678. peer->stats.tx.tx_failed);
  3679. DP_PRINT_STATS("Packets In OFDMA = %d",
  3680. peer->stats.tx.ofdma);
  3681. DP_PRINT_STATS("Packets In STBC = %d",
  3682. peer->stats.tx.stbc);
  3683. DP_PRINT_STATS("Packets In LDPC = %d",
  3684. peer->stats.tx.ldpc);
  3685. DP_PRINT_STATS("Packet Retries = %d",
  3686. peer->stats.tx.retries);
  3687. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3688. peer->stats.tx.amsdu_cnt);
  3689. DP_PRINT_STATS("Last Packet RSSI = %d",
  3690. peer->stats.tx.last_ack_rssi);
  3691. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3692. peer->stats.tx.dropped.fw_rem);
  3693. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3694. peer->stats.tx.dropped.fw_rem_tx);
  3695. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3696. peer->stats.tx.dropped.fw_rem_notx);
  3697. DP_PRINT_STATS("Dropped : Age Out = %d",
  3698. peer->stats.tx.dropped.age_out);
  3699. DP_PRINT_STATS("Rate Info:");
  3700. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3701. index = 0;
  3702. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3703. if (!dp_rate_string[pkt_type][mcs].valid)
  3704. continue;
  3705. DP_PRINT_STATS(" %s = %d",
  3706. dp_rate_string[pkt_type][mcs].mcs_type,
  3707. peer->stats.tx.pkt_type[pkt_type].
  3708. mcs_count[mcs]);
  3709. }
  3710. DP_PRINT_STATS("\n");
  3711. }
  3712. DP_PRINT_STATS("SGI = "
  3713. " 0.8us %d"
  3714. " 0.4us %d"
  3715. " 1.6us %d"
  3716. " 3.2us %d",
  3717. peer->stats.tx.sgi_count[0],
  3718. peer->stats.tx.sgi_count[1],
  3719. peer->stats.tx.sgi_count[2],
  3720. peer->stats.tx.sgi_count[3]);
  3721. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3722. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3723. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3724. DP_PRINT_STATS("Aggregation:");
  3725. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3726. peer->stats.tx.amsdu_cnt);
  3727. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3728. peer->stats.tx.non_amsdu_cnt);
  3729. DP_PRINT_STATS("Node Rx Stats:");
  3730. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3731. peer->stats.rx.to_stack.num);
  3732. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3733. peer->stats.rx.to_stack.bytes);
  3734. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3735. DP_PRINT_STATS("Packets Received = %d",
  3736. peer->stats.rx.rcvd_reo[i].num);
  3737. DP_PRINT_STATS("Bytes Received = %d",
  3738. peer->stats.rx.rcvd_reo[i].bytes);
  3739. }
  3740. DP_PRINT_STATS("Multicast Packets Received = %d",
  3741. peer->stats.rx.multicast.num);
  3742. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3743. peer->stats.rx.multicast.bytes);
  3744. DP_PRINT_STATS("WDS Packets Received = %d",
  3745. peer->stats.rx.wds.num);
  3746. DP_PRINT_STATS("WDS Bytes Received = %d",
  3747. peer->stats.rx.wds.bytes);
  3748. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3749. peer->stats.rx.intra_bss.pkts.num);
  3750. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3751. peer->stats.rx.intra_bss.pkts.bytes);
  3752. DP_PRINT_STATS("Raw Packets Received = %d",
  3753. peer->stats.rx.raw.num);
  3754. DP_PRINT_STATS("Raw Bytes Received = %d",
  3755. peer->stats.rx.raw.bytes);
  3756. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3757. peer->stats.rx.err.mic_err);
  3758. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3759. peer->stats.rx.err.decrypt_err);
  3760. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3761. peer->stats.rx.non_ampdu_cnt);
  3762. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3763. peer->stats.rx.ampdu_cnt);
  3764. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3765. peer->stats.rx.non_amsdu_cnt);
  3766. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3767. peer->stats.rx.amsdu_cnt);
  3768. DP_PRINT_STATS("SGI ="
  3769. " 0.8us %d"
  3770. " 0.4us %d"
  3771. " 1.6us %d"
  3772. " 3.2us %d",
  3773. peer->stats.rx.sgi_count[0],
  3774. peer->stats.rx.sgi_count[1],
  3775. peer->stats.rx.sgi_count[2],
  3776. peer->stats.rx.sgi_count[3]);
  3777. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3778. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3779. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3780. DP_PRINT_STATS("Reception Type ="
  3781. " SU %d,"
  3782. " MU_MIMO %d,"
  3783. " MU_OFDMA %d,"
  3784. " MU_OFDMA_MIMO %d",
  3785. peer->stats.rx.reception_type[0],
  3786. peer->stats.rx.reception_type[1],
  3787. peer->stats.rx.reception_type[2],
  3788. peer->stats.rx.reception_type[3]);
  3789. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3790. index = 0;
  3791. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3792. if (!dp_rate_string[pkt_type][mcs].valid)
  3793. continue;
  3794. DP_PRINT_STATS(" %s = %d",
  3795. dp_rate_string[pkt_type][mcs].mcs_type,
  3796. peer->stats.rx.pkt_type[pkt_type].
  3797. mcs_count[mcs]);
  3798. }
  3799. DP_PRINT_STATS("\n");
  3800. }
  3801. index = 0;
  3802. for (i = 0; i < SS_COUNT; i++) {
  3803. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3804. " %d", peer->stats.rx.nss[i]);
  3805. }
  3806. DP_PRINT_STATS("NSS(0-7) = %s",
  3807. nss);
  3808. DP_PRINT_STATS("Aggregation:");
  3809. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3810. peer->stats.rx.ampdu_cnt);
  3811. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3812. peer->stats.rx.non_ampdu_cnt);
  3813. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3814. peer->stats.rx.amsdu_cnt);
  3815. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3816. peer->stats.rx.non_amsdu_cnt);
  3817. }
  3818. /**
  3819. * dp_print_host_stats()- Function to print the stats aggregated at host
  3820. * @vdev_handle: DP_VDEV handle
  3821. * @type: host stats type
  3822. *
  3823. * Available Stat types
  3824. * TXRX_CLEAR_STATS : Clear the stats
  3825. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3826. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3827. * TXRX_TX_HOST_STATS: Print Tx Stats
  3828. * TXRX_RX_HOST_STATS: Print Rx Stats
  3829. * TXRX_AST_STATS: Print AST Stats
  3830. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  3831. *
  3832. * Return: 0 on success, print error message in case of failure
  3833. */
  3834. static int
  3835. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3836. {
  3837. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3838. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3839. dp_aggregate_pdev_stats(pdev);
  3840. switch (type) {
  3841. case TXRX_CLEAR_STATS:
  3842. dp_txrx_host_stats_clr(vdev);
  3843. break;
  3844. case TXRX_RX_RATE_STATS:
  3845. dp_print_rx_rates(vdev);
  3846. break;
  3847. case TXRX_TX_RATE_STATS:
  3848. dp_print_tx_rates(vdev);
  3849. break;
  3850. case TXRX_TX_HOST_STATS:
  3851. dp_print_pdev_tx_stats(pdev);
  3852. dp_print_soc_tx_stats(pdev->soc);
  3853. break;
  3854. case TXRX_RX_HOST_STATS:
  3855. dp_print_pdev_rx_stats(pdev);
  3856. dp_print_soc_rx_stats(pdev->soc);
  3857. break;
  3858. case TXRX_AST_STATS:
  3859. dp_print_ast_stats(pdev->soc);
  3860. break;
  3861. case TXRX_SRNG_PTR_STATS:
  3862. dp_print_ring_stats(pdev);
  3863. break;
  3864. default:
  3865. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3866. break;
  3867. }
  3868. return 0;
  3869. }
  3870. /*
  3871. * dp_get_host_peer_stats()- function to print peer stats
  3872. * @pdev_handle: DP_PDEV handle
  3873. * @mac_addr: mac address of the peer
  3874. *
  3875. * Return: void
  3876. */
  3877. static void
  3878. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3879. {
  3880. struct dp_peer *peer;
  3881. uint8_t local_id;
  3882. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3883. &local_id);
  3884. if (!peer) {
  3885. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3886. "%s: Invalid peer\n", __func__);
  3887. return;
  3888. }
  3889. dp_print_peer_stats(peer);
  3890. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  3891. return;
  3892. }
  3893. /*
  3894. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  3895. * @pdev: DP_PDEV handle
  3896. *
  3897. * Return: void
  3898. */
  3899. static void
  3900. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  3901. {
  3902. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  3903. htt_tlv_filter.mpdu_start = 0;
  3904. htt_tlv_filter.msdu_start = 0;
  3905. htt_tlv_filter.packet = 0;
  3906. htt_tlv_filter.msdu_end = 0;
  3907. htt_tlv_filter.mpdu_end = 0;
  3908. htt_tlv_filter.packet_header = 1;
  3909. htt_tlv_filter.attention = 1;
  3910. htt_tlv_filter.ppdu_start = 1;
  3911. htt_tlv_filter.ppdu_end = 1;
  3912. htt_tlv_filter.ppdu_end_user_stats = 1;
  3913. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3914. htt_tlv_filter.ppdu_end_status_done = 1;
  3915. htt_tlv_filter.enable_fp = 1;
  3916. htt_tlv_filter.enable_md = 0;
  3917. htt_tlv_filter.enable_mo = 0;
  3918. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  3919. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3920. RX_BUFFER_SIZE, &htt_tlv_filter);
  3921. }
  3922. /*
  3923. * dp_config_tx_capture()- API to enable/disable tx capture
  3924. * @pdev_handle: DP_PDEV handle
  3925. * @val: user provided value
  3926. *
  3927. * Return: void
  3928. */
  3929. static void
  3930. dp_config_tx_capture(struct cdp_pdev *pdev_handle, int val)
  3931. {
  3932. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3933. if (val) {
  3934. pdev->tx_sniffer_enable = 1;
  3935. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  3936. } else {
  3937. pdev->tx_sniffer_enable = 0;
  3938. if (!pdev->enhanced_stats_en)
  3939. dp_h2t_cfg_stats_msg_send(pdev, 0);
  3940. }
  3941. }
  3942. /*
  3943. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3944. * @pdev_handle: DP_PDEV handle
  3945. *
  3946. * Return: void
  3947. */
  3948. static void
  3949. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3950. {
  3951. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3952. pdev->enhanced_stats_en = 1;
  3953. dp_ppdu_ring_cfg(pdev);
  3954. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  3955. }
  3956. /*
  3957. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3958. * @pdev_handle: DP_PDEV handle
  3959. *
  3960. * Return: void
  3961. */
  3962. static void
  3963. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3964. {
  3965. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3966. pdev->enhanced_stats_en = 0;
  3967. if (!pdev->tx_sniffer_enable)
  3968. dp_h2t_cfg_stats_msg_send(pdev, 0);
  3969. }
  3970. /*
  3971. * dp_get_fw_peer_stats()- function to print peer stats
  3972. * @pdev_handle: DP_PDEV handle
  3973. * @mac_addr: mac address of the peer
  3974. * @cap: Type of htt stats requested
  3975. *
  3976. * Currently Supporting only MAC ID based requests Only
  3977. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3978. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3979. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3980. *
  3981. * Return: void
  3982. */
  3983. static void
  3984. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3985. uint32_t cap)
  3986. {
  3987. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3988. uint32_t config_param0 = 0;
  3989. uint32_t config_param1 = 0;
  3990. uint32_t config_param2 = 0;
  3991. uint32_t config_param3 = 0;
  3992. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3993. config_param0 |= (1 << (cap + 1));
  3994. config_param1 = 0x8f;
  3995. config_param2 |= (mac_addr[0] & 0x000000ff);
  3996. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3997. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3998. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3999. config_param3 |= (mac_addr[4] & 0x000000ff);
  4000. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4001. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4002. config_param0, config_param1, config_param2,
  4003. config_param3);
  4004. }
  4005. /*
  4006. * dp_set_pdev_param: function to set parameters in pdev
  4007. * @pdev_handle: DP pdev handle
  4008. * @param: parameter type to be set
  4009. * @val: value of parameter to be set
  4010. *
  4011. * return: void
  4012. */
  4013. static void dp_set_pdev_param(struct cdp_pdev *pdev_handle,
  4014. enum cdp_pdev_param_type param, uint8_t val)
  4015. {
  4016. switch (param) {
  4017. case CDP_CONFIG_TX_CAPTURE:
  4018. dp_config_tx_capture(pdev_handle, val);
  4019. break;
  4020. default:
  4021. break;
  4022. }
  4023. }
  4024. /*
  4025. * dp_set_vdev_param: function to set parameters in vdev
  4026. * @param: parameter type to be set
  4027. * @val: value of parameter to be set
  4028. *
  4029. * return: void
  4030. */
  4031. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4032. enum cdp_vdev_param_type param, uint32_t val)
  4033. {
  4034. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4035. switch (param) {
  4036. case CDP_ENABLE_WDS:
  4037. vdev->wds_enabled = val;
  4038. break;
  4039. case CDP_ENABLE_NAWDS:
  4040. vdev->nawds_enabled = val;
  4041. break;
  4042. case CDP_ENABLE_MCAST_EN:
  4043. vdev->mcast_enhancement_en = val;
  4044. break;
  4045. case CDP_ENABLE_PROXYSTA:
  4046. vdev->proxysta_vdev = val;
  4047. break;
  4048. case CDP_UPDATE_TDLS_FLAGS:
  4049. vdev->tdls_link_connected = val;
  4050. break;
  4051. case CDP_CFG_WDS_AGING_TIMER:
  4052. if (val == 0)
  4053. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4054. else if (val != vdev->wds_aging_timer_val)
  4055. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4056. vdev->wds_aging_timer_val = val;
  4057. break;
  4058. case CDP_ENABLE_AP_BRIDGE:
  4059. if (wlan_op_mode_sta != vdev->opmode)
  4060. vdev->ap_bridge_enabled = val;
  4061. else
  4062. vdev->ap_bridge_enabled = false;
  4063. break;
  4064. default:
  4065. break;
  4066. }
  4067. dp_tx_vdev_update_search_flags(vdev);
  4068. }
  4069. /**
  4070. * dp_peer_set_nawds: set nawds bit in peer
  4071. * @peer_handle: pointer to peer
  4072. * @value: enable/disable nawds
  4073. *
  4074. * return: void
  4075. */
  4076. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4077. {
  4078. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4079. peer->nawds_enabled = value;
  4080. }
  4081. /*
  4082. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4083. * @vdev_handle: DP_VDEV handle
  4084. * @map_id:ID of map that needs to be updated
  4085. *
  4086. * Return: void
  4087. */
  4088. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4089. uint8_t map_id)
  4090. {
  4091. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4092. vdev->dscp_tid_map_id = map_id;
  4093. return;
  4094. }
  4095. /**
  4096. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4097. * @pdev: DP_PDEV handle
  4098. * @map_id: ID of map that needs to be updated
  4099. * @tos: index value in map
  4100. * @tid: tid value passed by the user
  4101. *
  4102. * Return: void
  4103. */
  4104. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4105. uint8_t map_id, uint8_t tos, uint8_t tid)
  4106. {
  4107. uint8_t dscp;
  4108. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4109. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4110. pdev->dscp_tid_map[map_id][dscp] = tid;
  4111. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4112. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4113. map_id, dscp);
  4114. return;
  4115. }
  4116. /**
  4117. * dp_fw_stats_process(): Process TxRX FW stats request
  4118. * @vdev_handle: DP VDEV handle
  4119. * @val: value passed by user
  4120. *
  4121. * return: int
  4122. */
  4123. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4124. {
  4125. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4126. struct dp_pdev *pdev = NULL;
  4127. if (!vdev) {
  4128. DP_TRACE(NONE, "VDEV not found");
  4129. return 1;
  4130. }
  4131. pdev = vdev->pdev;
  4132. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4133. }
  4134. /*
  4135. * dp_txrx_stats() - function to map to firmware and host stats
  4136. * @vdev: virtual handle
  4137. * @stats: type of statistics requested
  4138. *
  4139. * Return: integer
  4140. */
  4141. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4142. {
  4143. int host_stats;
  4144. int fw_stats;
  4145. if (stats >= CDP_TXRX_MAX_STATS)
  4146. return 0;
  4147. /*
  4148. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4149. * has to be updated if new FW HTT stats added
  4150. */
  4151. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4152. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4153. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4154. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4156. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4157. stats, fw_stats, host_stats);
  4158. if (fw_stats != TXRX_FW_STATS_INVALID)
  4159. return dp_fw_stats_process(vdev, fw_stats);
  4160. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4161. (host_stats <= TXRX_HOST_STATS_MAX))
  4162. return dp_print_host_stats(vdev, host_stats);
  4163. else
  4164. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4165. "Wrong Input for TxRx Stats");
  4166. return 0;
  4167. }
  4168. /*
  4169. * dp_print_napi_stats(): NAPI stats
  4170. * @soc - soc handle
  4171. */
  4172. static void dp_print_napi_stats(struct dp_soc *soc)
  4173. {
  4174. hif_print_napi_stats(soc->hif_handle);
  4175. }
  4176. /*
  4177. * dp_print_per_ring_stats(): Packet count per ring
  4178. * @soc - soc handle
  4179. */
  4180. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4181. {
  4182. uint8_t core, ring;
  4183. uint64_t total_packets;
  4184. DP_TRACE(FATAL, "Reo packets per ring:");
  4185. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4186. total_packets = 0;
  4187. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4188. for (core = 0; core < NR_CPUS; core++) {
  4189. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4190. core, soc->stats.rx.ring_packets[core][ring]);
  4191. total_packets += soc->stats.rx.ring_packets[core][ring];
  4192. }
  4193. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4194. ring, total_packets);
  4195. }
  4196. }
  4197. /*
  4198. * dp_txrx_path_stats() - Function to display dump stats
  4199. * @soc - soc handle
  4200. *
  4201. * return: none
  4202. */
  4203. static void dp_txrx_path_stats(struct dp_soc *soc)
  4204. {
  4205. uint8_t error_code;
  4206. uint8_t loop_pdev;
  4207. struct dp_pdev *pdev;
  4208. uint8_t i;
  4209. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4210. pdev = soc->pdev_list[loop_pdev];
  4211. dp_aggregate_pdev_stats(pdev);
  4212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4213. "Tx path Statistics:");
  4214. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4215. pdev->stats.tx_i.rcvd.num,
  4216. pdev->stats.tx_i.rcvd.bytes);
  4217. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4218. pdev->stats.tx_i.processed.num,
  4219. pdev->stats.tx_i.processed.bytes);
  4220. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4221. pdev->stats.tx.tx_success.num,
  4222. pdev->stats.tx.tx_success.bytes);
  4223. DP_TRACE(FATAL, "Dropped in host:");
  4224. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4225. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4226. DP_TRACE(FATAL, "Descriptor not available: %u",
  4227. pdev->stats.tx_i.dropped.desc_na);
  4228. DP_TRACE(FATAL, "Ring full: %u",
  4229. pdev->stats.tx_i.dropped.ring_full);
  4230. DP_TRACE(FATAL, "Enqueue fail: %u",
  4231. pdev->stats.tx_i.dropped.enqueue_fail);
  4232. DP_TRACE(FATAL, "DMA Error: %u",
  4233. pdev->stats.tx_i.dropped.dma_error);
  4234. DP_TRACE(FATAL, "Dropped in hardware:");
  4235. DP_TRACE(FATAL, "total packets dropped: %u",
  4236. pdev->stats.tx.tx_failed);
  4237. DP_TRACE(FATAL, "mpdu age out: %u",
  4238. pdev->stats.tx.dropped.age_out);
  4239. DP_TRACE(FATAL, "firmware removed: %u",
  4240. pdev->stats.tx.dropped.fw_rem);
  4241. DP_TRACE(FATAL, "firmware removed tx: %u",
  4242. pdev->stats.tx.dropped.fw_rem_tx);
  4243. DP_TRACE(FATAL, "firmware removed notx %u",
  4244. pdev->stats.tx.dropped.fw_rem_notx);
  4245. DP_TRACE(FATAL, "peer_invalid: %u",
  4246. pdev->soc->stats.tx.tx_invalid_peer.num);
  4247. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4248. DP_TRACE(FATAL, "Single Packet: %u",
  4249. pdev->stats.tx_comp_histogram.pkts_1);
  4250. DP_TRACE(FATAL, "2-20 Packets: %u",
  4251. pdev->stats.tx_comp_histogram.pkts_2_20);
  4252. DP_TRACE(FATAL, "21-40 Packets: %u",
  4253. pdev->stats.tx_comp_histogram.pkts_21_40);
  4254. DP_TRACE(FATAL, "41-60 Packets: %u",
  4255. pdev->stats.tx_comp_histogram.pkts_41_60);
  4256. DP_TRACE(FATAL, "61-80 Packets: %u",
  4257. pdev->stats.tx_comp_histogram.pkts_61_80);
  4258. DP_TRACE(FATAL, "81-100 Packets: %u",
  4259. pdev->stats.tx_comp_histogram.pkts_81_100);
  4260. DP_TRACE(FATAL, "101-200 Packets: %u",
  4261. pdev->stats.tx_comp_histogram.pkts_101_200);
  4262. DP_TRACE(FATAL, " 201+ Packets: %u",
  4263. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4264. DP_TRACE(FATAL, "Rx path statistics");
  4265. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4266. pdev->stats.rx.to_stack.num,
  4267. pdev->stats.rx.to_stack.bytes);
  4268. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4269. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4270. i, pdev->stats.rx.rcvd_reo[i].num,
  4271. pdev->stats.rx.rcvd_reo[i].bytes);
  4272. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4273. pdev->stats.rx.intra_bss.pkts.num,
  4274. pdev->stats.rx.intra_bss.pkts.bytes);
  4275. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4276. pdev->stats.rx.intra_bss.fail.num,
  4277. pdev->stats.rx.intra_bss.fail.bytes);
  4278. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4279. pdev->stats.rx.raw.num,
  4280. pdev->stats.rx.raw.bytes);
  4281. DP_TRACE(FATAL, "dropped: error %u msdus",
  4282. pdev->stats.rx.err.mic_err);
  4283. DP_TRACE(FATAL, "peer invalid %u",
  4284. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4285. DP_TRACE(FATAL, "Reo Statistics");
  4286. DP_TRACE(FATAL, "rbm error: %u msdus",
  4287. pdev->soc->stats.rx.err.invalid_rbm);
  4288. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4289. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4290. DP_TRACE(FATAL, "Reo errors");
  4291. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4292. error_code++) {
  4293. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4294. error_code,
  4295. pdev->soc->stats.rx.err.reo_error[error_code]);
  4296. }
  4297. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4298. error_code++) {
  4299. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4300. error_code,
  4301. pdev->soc->stats.rx.err
  4302. .rxdma_error[error_code]);
  4303. }
  4304. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4305. DP_TRACE(FATAL, "Single Packet: %u",
  4306. pdev->stats.rx_ind_histogram.pkts_1);
  4307. DP_TRACE(FATAL, "2-20 Packets: %u",
  4308. pdev->stats.rx_ind_histogram.pkts_2_20);
  4309. DP_TRACE(FATAL, "21-40 Packets: %u",
  4310. pdev->stats.rx_ind_histogram.pkts_21_40);
  4311. DP_TRACE(FATAL, "41-60 Packets: %u",
  4312. pdev->stats.rx_ind_histogram.pkts_41_60);
  4313. DP_TRACE(FATAL, "61-80 Packets: %u",
  4314. pdev->stats.rx_ind_histogram.pkts_61_80);
  4315. DP_TRACE(FATAL, "81-100 Packets: %u",
  4316. pdev->stats.rx_ind_histogram.pkts_81_100);
  4317. DP_TRACE(FATAL, "101-200 Packets: %u",
  4318. pdev->stats.rx_ind_histogram.pkts_101_200);
  4319. DP_TRACE(FATAL, " 201+ Packets: %u",
  4320. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4321. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  4322. __func__,
  4323. pdev->soc->wlan_cfg_ctx->tso_enabled,
  4324. pdev->soc->wlan_cfg_ctx->lro_enabled,
  4325. pdev->soc->wlan_cfg_ctx->rx_hash,
  4326. pdev->soc->wlan_cfg_ctx->napi_enabled);
  4327. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4328. DP_TRACE_STATS(ERROR, "%s: Tx flow stop queue: %u tx flow start queue offset: %u",
  4329. __func__,
  4330. pdev->soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold,
  4331. pdev->soc->wlan_cfg_ctx->tx_flow_start_queue_offset);
  4332. #endif
  4333. }
  4334. }
  4335. /*
  4336. * dp_txrx_dump_stats() - Dump statistics
  4337. * @value - Statistics option
  4338. */
  4339. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4340. {
  4341. struct dp_soc *soc =
  4342. (struct dp_soc *)psoc;
  4343. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4344. if (!soc) {
  4345. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4346. "%s: soc is NULL", __func__);
  4347. return QDF_STATUS_E_INVAL;
  4348. }
  4349. switch (value) {
  4350. case CDP_TXRX_PATH_STATS:
  4351. dp_txrx_path_stats(soc);
  4352. break;
  4353. case CDP_RX_RING_STATS:
  4354. dp_print_per_ring_stats(soc);
  4355. break;
  4356. case CDP_TXRX_TSO_STATS:
  4357. /* TODO: NOT IMPLEMENTED */
  4358. break;
  4359. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4360. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4361. break;
  4362. case CDP_DP_NAPI_STATS:
  4363. dp_print_napi_stats(soc);
  4364. break;
  4365. case CDP_TXRX_DESC_STATS:
  4366. /* TODO: NOT IMPLEMENTED */
  4367. break;
  4368. default:
  4369. status = QDF_STATUS_E_INVAL;
  4370. break;
  4371. }
  4372. return status;
  4373. }
  4374. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4375. /**
  4376. * dp_update_flow_control_parameters() - API to store datapath
  4377. * config parameters
  4378. * @soc: soc handle
  4379. * @cfg: ini parameter handle
  4380. *
  4381. * Return: void
  4382. */
  4383. static inline
  4384. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4385. struct cdp_config_params *params)
  4386. {
  4387. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  4388. params->tx_flow_stop_queue_threshold;
  4389. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  4390. params->tx_flow_start_queue_offset;
  4391. }
  4392. #else
  4393. static inline
  4394. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4395. struct cdp_config_params *params)
  4396. {
  4397. }
  4398. #endif
  4399. /**
  4400. * dp_update_config_parameters() - API to store datapath
  4401. * config parameters
  4402. * @soc: soc handle
  4403. * @cfg: ini parameter handle
  4404. *
  4405. * Return: status
  4406. */
  4407. static
  4408. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  4409. struct cdp_config_params *params)
  4410. {
  4411. struct dp_soc *soc = (struct dp_soc *)psoc;
  4412. if (!(soc)) {
  4413. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4414. "%s: Invalid handle", __func__);
  4415. return QDF_STATUS_E_INVAL;
  4416. }
  4417. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  4418. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  4419. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  4420. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  4421. params->tcp_udp_checksumoffload;
  4422. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  4423. dp_update_flow_control_parameters(soc, params);
  4424. return QDF_STATUS_SUCCESS;
  4425. }
  4426. static struct cdp_wds_ops dp_ops_wds = {
  4427. .vdev_set_wds = dp_vdev_set_wds,
  4428. };
  4429. /*
  4430. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4431. * @soc - datapath soc handle
  4432. * @peer - datapath peer handle
  4433. *
  4434. * Delete the AST entries belonging to a peer
  4435. */
  4436. #ifdef FEATURE_WDS
  4437. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4438. struct dp_peer *peer)
  4439. {
  4440. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4441. qdf_spin_lock_bh(&soc->ast_lock);
  4442. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4443. if (ast_entry->next_hop) {
  4444. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4445. peer->vdev->pdev->osif_pdev,
  4446. ast_entry->mac_addr.raw);
  4447. }
  4448. dp_peer_del_ast(soc, ast_entry);
  4449. }
  4450. qdf_spin_unlock_bh(&soc->ast_lock);
  4451. }
  4452. #else
  4453. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4454. struct dp_peer *peer)
  4455. {
  4456. }
  4457. #endif
  4458. /*
  4459. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4460. * @vdev_handle - datapath vdev handle
  4461. * @callback - callback function
  4462. * @ctxt: callback context
  4463. *
  4464. */
  4465. static void
  4466. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4467. ol_txrx_data_tx_cb callback, void *ctxt)
  4468. {
  4469. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4470. vdev->tx_non_std_data_callback.func = callback;
  4471. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4472. }
  4473. #ifdef CONFIG_WIN
  4474. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4475. {
  4476. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4477. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4478. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4479. dp_peer_delete_ast_entries(soc, peer);
  4480. }
  4481. #endif
  4482. static struct cdp_cmn_ops dp_ops_cmn = {
  4483. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4484. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4485. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4486. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4487. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4488. .txrx_peer_create = dp_peer_create_wifi3,
  4489. .txrx_peer_setup = dp_peer_setup_wifi3,
  4490. #ifdef CONFIG_WIN
  4491. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4492. #else
  4493. .txrx_peer_teardown = NULL,
  4494. #endif
  4495. .txrx_peer_delete = dp_peer_delete_wifi3,
  4496. .txrx_vdev_register = dp_vdev_register_wifi3,
  4497. .txrx_soc_detach = dp_soc_detach_wifi3,
  4498. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4499. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4500. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4501. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4502. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4503. .delba_process = dp_delba_process_wifi3,
  4504. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4505. .flush_cache_rx_queue = NULL,
  4506. /* TODO: get API's for dscp-tid need to be added*/
  4507. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4508. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4509. .txrx_stats = dp_txrx_stats,
  4510. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4511. .display_stats = dp_txrx_dump_stats,
  4512. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4513. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4514. #ifdef DP_INTR_POLL_BASED
  4515. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4516. #else
  4517. .txrx_intr_attach = dp_soc_interrupt_attach,
  4518. #endif
  4519. .txrx_intr_detach = dp_soc_interrupt_detach,
  4520. .set_pn_check = dp_set_pn_check_wifi3,
  4521. .update_config_parameters = dp_update_config_parameters,
  4522. /* TODO: Add other functions */
  4523. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4524. };
  4525. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4526. .txrx_peer_authorize = dp_peer_authorize,
  4527. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4528. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4529. #ifdef MESH_MODE_SUPPORT
  4530. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4531. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4532. #endif
  4533. .txrx_set_vdev_param = dp_set_vdev_param,
  4534. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4535. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4536. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4537. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4538. .txrx_update_filter_neighbour_peers =
  4539. dp_update_filter_neighbour_peers,
  4540. .txrx_get_sec_type = dp_get_sec_type,
  4541. /* TODO: Add other functions */
  4542. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4543. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4544. .txrx_set_pdev_param = dp_set_pdev_param,
  4545. };
  4546. static struct cdp_me_ops dp_ops_me = {
  4547. #ifdef ATH_SUPPORT_IQUE
  4548. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4549. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4550. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4551. #endif
  4552. };
  4553. static struct cdp_mon_ops dp_ops_mon = {
  4554. .txrx_monitor_set_filter_ucast_data = NULL,
  4555. .txrx_monitor_set_filter_mcast_data = NULL,
  4556. .txrx_monitor_set_filter_non_data = NULL,
  4557. .txrx_monitor_get_filter_ucast_data = NULL,
  4558. .txrx_monitor_get_filter_mcast_data = NULL,
  4559. .txrx_monitor_get_filter_non_data = NULL,
  4560. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4561. };
  4562. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4563. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4564. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4565. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4566. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4567. /* TODO */
  4568. };
  4569. static struct cdp_raw_ops dp_ops_raw = {
  4570. /* TODO */
  4571. };
  4572. #ifdef CONFIG_WIN
  4573. static struct cdp_pflow_ops dp_ops_pflow = {
  4574. /* TODO */
  4575. };
  4576. #endif /* CONFIG_WIN */
  4577. #ifdef FEATURE_RUNTIME_PM
  4578. /**
  4579. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4580. * @opaque_pdev: DP pdev context
  4581. *
  4582. * DP is ready to runtime suspend if there are no pending TX packets.
  4583. *
  4584. * Return: QDF_STATUS
  4585. */
  4586. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4587. {
  4588. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4589. struct dp_soc *soc = pdev->soc;
  4590. /* Call DP TX flow control API to check if there is any
  4591. pending packets */
  4592. if (soc->intr_mode == DP_INTR_POLL)
  4593. qdf_timer_stop(&soc->int_timer);
  4594. return QDF_STATUS_SUCCESS;
  4595. }
  4596. /**
  4597. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4598. * @opaque_pdev: DP pdev context
  4599. *
  4600. * Resume DP for runtime PM.
  4601. *
  4602. * Return: QDF_STATUS
  4603. */
  4604. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4605. {
  4606. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4607. struct dp_soc *soc = pdev->soc;
  4608. void *hal_srng;
  4609. int i;
  4610. if (soc->intr_mode == DP_INTR_POLL)
  4611. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4612. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4613. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4614. if (hal_srng) {
  4615. /* We actually only need to acquire the lock */
  4616. hal_srng_access_start(soc->hal_soc, hal_srng);
  4617. /* Update SRC ring head pointer for HW to send
  4618. all pending packets */
  4619. hal_srng_access_end(soc->hal_soc, hal_srng);
  4620. }
  4621. }
  4622. return QDF_STATUS_SUCCESS;
  4623. }
  4624. #endif /* FEATURE_RUNTIME_PM */
  4625. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4626. {
  4627. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4628. struct dp_soc *soc = pdev->soc;
  4629. if (soc->intr_mode == DP_INTR_POLL)
  4630. qdf_timer_stop(&soc->int_timer);
  4631. return QDF_STATUS_SUCCESS;
  4632. }
  4633. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4634. {
  4635. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4636. struct dp_soc *soc = pdev->soc;
  4637. if (soc->intr_mode == DP_INTR_POLL)
  4638. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4639. return QDF_STATUS_SUCCESS;
  4640. }
  4641. #ifndef CONFIG_WIN
  4642. static struct cdp_misc_ops dp_ops_misc = {
  4643. .tx_non_std = dp_tx_non_std,
  4644. .get_opmode = dp_get_opmode,
  4645. #ifdef FEATURE_RUNTIME_PM
  4646. .runtime_suspend = dp_runtime_suspend,
  4647. .runtime_resume = dp_runtime_resume,
  4648. #endif /* FEATURE_RUNTIME_PM */
  4649. };
  4650. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4651. /* WIFI 3.0 DP implement as required. */
  4652. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4653. .register_pause_cb = dp_txrx_register_pause_cb,
  4654. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4655. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4656. };
  4657. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4658. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4659. };
  4660. #ifdef IPA_OFFLOAD
  4661. static struct cdp_ipa_ops dp_ops_ipa = {
  4662. .ipa_get_resource = dp_ipa_get_resource,
  4663. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4664. .ipa_op_response = dp_ipa_op_response,
  4665. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4666. .ipa_get_stat = dp_ipa_get_stat,
  4667. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4668. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4669. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4670. .ipa_setup = dp_ipa_setup,
  4671. .ipa_cleanup = dp_ipa_cleanup,
  4672. .ipa_setup_iface = dp_ipa_setup_iface,
  4673. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4674. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4675. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4676. .ipa_set_perf_level = dp_ipa_set_perf_level
  4677. };
  4678. #endif
  4679. static struct cdp_bus_ops dp_ops_bus = {
  4680. .bus_suspend = dp_bus_suspend,
  4681. .bus_resume = dp_bus_resume
  4682. };
  4683. static struct cdp_ocb_ops dp_ops_ocb = {
  4684. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4685. };
  4686. static struct cdp_throttle_ops dp_ops_throttle = {
  4687. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4688. };
  4689. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4690. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4691. };
  4692. static struct cdp_cfg_ops dp_ops_cfg = {
  4693. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4694. };
  4695. static struct cdp_peer_ops dp_ops_peer = {
  4696. .register_peer = dp_register_peer,
  4697. .clear_peer = dp_clear_peer,
  4698. .find_peer_by_addr = dp_find_peer_by_addr,
  4699. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4700. .local_peer_id = dp_local_peer_id,
  4701. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4702. .peer_state_update = dp_peer_state_update,
  4703. .get_vdevid = dp_get_vdevid,
  4704. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4705. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4706. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4707. .get_peer_state = dp_get_peer_state,
  4708. .last_assoc_received = dp_get_last_assoc_received,
  4709. .last_disassoc_received = dp_get_last_disassoc_received,
  4710. .last_deauth_received = dp_get_last_deauth_received,
  4711. };
  4712. #endif
  4713. static struct cdp_ops dp_txrx_ops = {
  4714. .cmn_drv_ops = &dp_ops_cmn,
  4715. .ctrl_ops = &dp_ops_ctrl,
  4716. .me_ops = &dp_ops_me,
  4717. .mon_ops = &dp_ops_mon,
  4718. .host_stats_ops = &dp_ops_host_stats,
  4719. .wds_ops = &dp_ops_wds,
  4720. .raw_ops = &dp_ops_raw,
  4721. #ifdef CONFIG_WIN
  4722. .pflow_ops = &dp_ops_pflow,
  4723. #endif /* CONFIG_WIN */
  4724. #ifndef CONFIG_WIN
  4725. .misc_ops = &dp_ops_misc,
  4726. .cfg_ops = &dp_ops_cfg,
  4727. .flowctl_ops = &dp_ops_flowctl,
  4728. .l_flowctl_ops = &dp_ops_l_flowctl,
  4729. #ifdef IPA_OFFLOAD
  4730. .ipa_ops = &dp_ops_ipa,
  4731. #endif
  4732. .bus_ops = &dp_ops_bus,
  4733. .ocb_ops = &dp_ops_ocb,
  4734. .peer_ops = &dp_ops_peer,
  4735. .throttle_ops = &dp_ops_throttle,
  4736. .mob_stats_ops = &dp_ops_mob_stats,
  4737. #endif
  4738. };
  4739. /*
  4740. * dp_soc_set_txrx_ring_map()
  4741. * @dp_soc: DP handler for soc
  4742. *
  4743. * Return: Void
  4744. */
  4745. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4746. {
  4747. uint32_t i;
  4748. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4749. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4750. }
  4751. }
  4752. /*
  4753. * dp_soc_attach_wifi3() - Attach txrx SOC
  4754. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4755. * @htc_handle: Opaque HTC handle
  4756. * @hif_handle: Opaque HIF handle
  4757. * @qdf_osdev: QDF device
  4758. *
  4759. * Return: DP SOC handle on success, NULL on failure
  4760. */
  4761. /*
  4762. * Local prototype added to temporarily address warning caused by
  4763. * -Wmissing-prototypes. A more correct solution, namely to expose
  4764. * a prototype in an appropriate header file, will come later.
  4765. */
  4766. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4767. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4768. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4769. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4770. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4771. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4772. {
  4773. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4774. if (!soc) {
  4775. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4776. FL("DP SOC memory allocation failed"));
  4777. goto fail0;
  4778. }
  4779. soc->cdp_soc.ops = &dp_txrx_ops;
  4780. soc->cdp_soc.ol_ops = ol_ops;
  4781. soc->osif_soc = osif_soc;
  4782. soc->osdev = qdf_osdev;
  4783. soc->hif_handle = hif_handle;
  4784. soc->psoc = psoc;
  4785. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4786. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4787. soc->hal_soc, qdf_osdev);
  4788. if (!soc->htt_handle) {
  4789. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4790. FL("HTT attach failed"));
  4791. goto fail1;
  4792. }
  4793. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4794. if (!soc->wlan_cfg_ctx) {
  4795. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4796. FL("wlan_cfg_soc_attach failed"));
  4797. goto fail2;
  4798. }
  4799. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4800. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4801. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4802. CDP_CFG_MAX_PEER_ID);
  4803. if (ret != -EINVAL) {
  4804. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4805. }
  4806. }
  4807. qdf_spinlock_create(&soc->peer_ref_mutex);
  4808. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4809. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4810. /* fill the tx/rx cpu ring map*/
  4811. dp_soc_set_txrx_ring_map(soc);
  4812. qdf_spinlock_create(&soc->htt_stats.lock);
  4813. /* initialize work queue for stats processing */
  4814. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4815. return (void *)soc;
  4816. fail2:
  4817. htt_soc_detach(soc->htt_handle);
  4818. fail1:
  4819. qdf_mem_free(soc);
  4820. fail0:
  4821. return NULL;
  4822. }
  4823. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4824. /*
  4825. * dp_set_pktlog_wifi3() - attach txrx vdev
  4826. * @pdev: Datapath PDEV handle
  4827. * @event: which event's notifications are being subscribed to
  4828. * @enable: WDI event subscribe or not. (True or False)
  4829. *
  4830. * Return: Success, NULL on failure
  4831. */
  4832. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4833. bool enable)
  4834. {
  4835. struct dp_soc *soc = pdev->soc;
  4836. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4837. if (enable) {
  4838. switch (event) {
  4839. case WDI_EVENT_RX_DESC:
  4840. if (pdev->monitor_vdev) {
  4841. /* Nothing needs to be done if monitor mode is
  4842. * enabled
  4843. */
  4844. return 0;
  4845. }
  4846. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4847. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4848. htt_tlv_filter.mpdu_start = 1;
  4849. htt_tlv_filter.msdu_start = 1;
  4850. htt_tlv_filter.msdu_end = 1;
  4851. htt_tlv_filter.mpdu_end = 1;
  4852. htt_tlv_filter.packet_header = 1;
  4853. htt_tlv_filter.attention = 1;
  4854. htt_tlv_filter.ppdu_start = 1;
  4855. htt_tlv_filter.ppdu_end = 1;
  4856. htt_tlv_filter.ppdu_end_user_stats = 1;
  4857. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4858. htt_tlv_filter.ppdu_end_status_done = 1;
  4859. htt_tlv_filter.enable_fp = 1;
  4860. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4861. pdev->pdev_id,
  4862. pdev->rxdma_mon_status_ring.hal_srng,
  4863. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4864. &htt_tlv_filter);
  4865. }
  4866. break;
  4867. case WDI_EVENT_LITE_RX:
  4868. if (pdev->monitor_vdev) {
  4869. /* Nothing needs to be done if monitor mode is
  4870. * enabled
  4871. */
  4872. return 0;
  4873. }
  4874. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4875. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4876. htt_tlv_filter.ppdu_start = 1;
  4877. htt_tlv_filter.ppdu_end = 1;
  4878. htt_tlv_filter.ppdu_end_user_stats = 1;
  4879. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4880. htt_tlv_filter.ppdu_end_status_done = 1;
  4881. htt_tlv_filter.enable_fp = 1;
  4882. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4883. pdev->pdev_id,
  4884. pdev->rxdma_mon_status_ring.hal_srng,
  4885. RXDMA_MONITOR_STATUS,
  4886. RX_BUFFER_SIZE_PKTLOG_LITE,
  4887. &htt_tlv_filter);
  4888. }
  4889. break;
  4890. case WDI_EVENT_LITE_T2H:
  4891. if (pdev->monitor_vdev) {
  4892. /* Nothing needs to be done if monitor mode is
  4893. * enabled
  4894. */
  4895. return 0;
  4896. }
  4897. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4898. * passing value 0xffff. Once these macros will define in htt
  4899. * header file will use proper macros
  4900. */
  4901. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4902. break;
  4903. default:
  4904. /* Nothing needs to be done for other pktlog types */
  4905. break;
  4906. }
  4907. } else {
  4908. switch (event) {
  4909. case WDI_EVENT_RX_DESC:
  4910. case WDI_EVENT_LITE_RX:
  4911. if (pdev->monitor_vdev) {
  4912. /* Nothing needs to be done if monitor mode is
  4913. * enabled
  4914. */
  4915. return 0;
  4916. }
  4917. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4918. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4919. /* htt_tlv_filter is initialized to 0 */
  4920. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4921. pdev->pdev_id,
  4922. pdev->rxdma_mon_status_ring.hal_srng,
  4923. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4924. &htt_tlv_filter);
  4925. }
  4926. break;
  4927. case WDI_EVENT_LITE_T2H:
  4928. if (pdev->monitor_vdev) {
  4929. /* Nothing needs to be done if monitor mode is
  4930. * enabled
  4931. */
  4932. return 0;
  4933. }
  4934. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4935. * passing value 0. Once these macros will define in htt
  4936. * header file will use proper macros
  4937. */
  4938. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4939. break;
  4940. default:
  4941. /* Nothing needs to be done for other pktlog types */
  4942. break;
  4943. }
  4944. }
  4945. return 0;
  4946. }
  4947. #endif