sde_kms.c 91 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <drm/drm_atomic_uapi.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "dp_mst_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_reg_dma.h"
  45. #include "sde_connector.h"
  46. #include <linux/qcom_scm.h>
  47. #include "soc/qcom/secure_buffer.h"
  48. #include <linux/qtee_shmbridge.h>
  49. #define CREATE_TRACE_POINTS
  50. #include "sde_trace.h"
  51. /* defines for secure channel call */
  52. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  53. #define MDP_DEVICE_ID 0x1A
  54. EXPORT_TRACEPOINT_SYMBOL(sde_drm_tracing_mark_write);
  55. static const char * const iommu_ports[] = {
  56. "mdp_0",
  57. };
  58. /**
  59. * Controls size of event log buffer. Specified as a power of 2.
  60. */
  61. #define SDE_EVTLOG_SIZE 1024
  62. /*
  63. * To enable overall DRM driver logging
  64. * # echo 0x2 > /sys/module/drm/parameters/debug
  65. *
  66. * To enable DRM driver h/w logging
  67. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  68. *
  69. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  70. */
  71. #define SDE_DEBUGFS_DIR "msm_sde"
  72. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  73. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  74. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  75. /**
  76. * sdecustom - enable certain driver customizations for sde clients
  77. * Enabling this modifies the standard DRM behavior slightly and assumes
  78. * that the clients have specific knowledge about the modifications that
  79. * are involved, so don't enable this unless you know what you're doing.
  80. *
  81. * Parts of the driver that are affected by this setting may be located by
  82. * searching for invocations of the 'sde_is_custom_client()' function.
  83. *
  84. * This is disabled by default.
  85. */
  86. static bool sdecustom = true;
  87. module_param(sdecustom, bool, 0400);
  88. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  89. static int sde_kms_hw_init(struct msm_kms *kms);
  90. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  91. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  92. static int _sde_kms_register_events(struct msm_kms *kms,
  93. struct drm_mode_object *obj, u32 event, bool en);
  94. bool sde_is_custom_client(void)
  95. {
  96. return sdecustom;
  97. }
  98. #ifdef CONFIG_DEBUG_FS
  99. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  100. {
  101. struct msm_drm_private *priv;
  102. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  103. return NULL;
  104. priv = sde_kms->dev->dev_private;
  105. return priv->debug_root;
  106. }
  107. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  108. {
  109. void *p;
  110. int rc;
  111. void *debugfs_root;
  112. p = sde_hw_util_get_log_mask_ptr();
  113. if (!sde_kms || !p)
  114. return -EINVAL;
  115. debugfs_root = sde_debugfs_get_root(sde_kms);
  116. if (!debugfs_root)
  117. return -EINVAL;
  118. /* allow debugfs_root to be NULL */
  119. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  120. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  121. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  122. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  123. if (rc) {
  124. SDE_ERROR("failed to init perf %d\n", rc);
  125. return rc;
  126. }
  127. if (sde_kms->catalog->qdss_count)
  128. debugfs_create_u32("qdss", 0600, debugfs_root,
  129. (u32 *)&sde_kms->qdss_enabled);
  130. return 0;
  131. }
  132. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  133. {
  134. /* don't need to NULL check debugfs_root */
  135. if (sde_kms) {
  136. sde_debugfs_vbif_destroy(sde_kms);
  137. sde_debugfs_core_irq_destroy(sde_kms);
  138. }
  139. }
  140. #else
  141. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  142. {
  143. return 0;
  144. }
  145. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  146. {
  147. }
  148. #endif
  149. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  150. {
  151. int ret = 0;
  152. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  153. ret = sde_crtc_vblank(crtc, true);
  154. SDE_ATRACE_END("sde_kms_enable_vblank");
  155. return ret;
  156. }
  157. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  158. {
  159. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  160. sde_crtc_vblank(crtc, false);
  161. SDE_ATRACE_END("sde_kms_disable_vblank");
  162. }
  163. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  164. struct drm_crtc *crtc)
  165. {
  166. struct drm_encoder *encoder;
  167. struct drm_device *dev;
  168. int ret;
  169. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  170. SDE_ERROR("invalid params\n");
  171. return;
  172. }
  173. if (!crtc->state->enable) {
  174. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  175. return;
  176. }
  177. if (!crtc->state->active) {
  178. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  179. return;
  180. }
  181. dev = crtc->dev;
  182. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  183. if (encoder->crtc != crtc)
  184. continue;
  185. /*
  186. * Video Mode - Wait for VSYNC
  187. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  188. * complete
  189. */
  190. SDE_EVT32_VERBOSE(DRMID(crtc));
  191. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  192. if (ret && ret != -EWOULDBLOCK) {
  193. SDE_ERROR(
  194. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  195. crtc->base.id, encoder->base.id, ret);
  196. break;
  197. }
  198. }
  199. }
  200. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  201. struct drm_crtc *crtc, bool enable)
  202. {
  203. struct drm_device *dev;
  204. struct msm_drm_private *priv;
  205. struct sde_mdss_cfg *sde_cfg;
  206. struct drm_plane *plane;
  207. int i, ret;
  208. dev = sde_kms->dev;
  209. priv = dev->dev_private;
  210. sde_cfg = sde_kms->catalog;
  211. ret = sde_vbif_halt_xin_mask(sde_kms,
  212. sde_cfg->sui_block_xin_mask, enable);
  213. if (ret) {
  214. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  215. return ret;
  216. }
  217. if (enable) {
  218. for (i = 0; i < priv->num_planes; i++) {
  219. plane = priv->planes[i];
  220. sde_plane_secure_ctrl_xin_client(plane, crtc);
  221. }
  222. }
  223. return 0;
  224. }
  225. /**
  226. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  227. * @sde_kms: Pointer to sde_kms struct
  228. * @vimd: switch the stage 2 translation to this VMID
  229. */
  230. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  231. {
  232. struct device dummy = {};
  233. dma_addr_t dma_handle;
  234. uint32_t num_sids;
  235. uint32_t *sec_sid;
  236. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  237. int ret = 0, i;
  238. struct qtee_shm shm;
  239. bool qtee_en = qtee_shmbridge_is_enabled();
  240. phys_addr_t mem_addr;
  241. u64 mem_size;
  242. num_sids = sde_cfg->sec_sid_mask_count;
  243. if (!num_sids) {
  244. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  245. return -EINVAL;
  246. }
  247. if (qtee_en) {
  248. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  249. &shm);
  250. if (ret)
  251. return -ENOMEM;
  252. sec_sid = (uint32_t *) shm.vaddr;
  253. mem_addr = shm.paddr;
  254. mem_size = shm.size;
  255. } else {
  256. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  257. if (!sec_sid)
  258. return -ENOMEM;
  259. mem_addr = virt_to_phys(sec_sid);
  260. mem_size = sizeof(uint32_t) * num_sids;
  261. }
  262. for (i = 0; i < num_sids; i++) {
  263. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  264. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  265. }
  266. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  267. if (ret) {
  268. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  269. goto map_error;
  270. }
  271. set_dma_ops(&dummy, NULL);
  272. dma_handle = dma_map_single(&dummy, sec_sid,
  273. num_sids *sizeof(uint32_t), DMA_TO_DEVICE);
  274. if (dma_mapping_error(&dummy, dma_handle)) {
  275. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  276. vmid);
  277. goto map_error;
  278. }
  279. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  280. vmid, num_sids, qtee_en);
  281. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  282. mem_size, vmid);
  283. if (ret)
  284. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  285. vmid, ret);
  286. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  287. vmid, qtee_en, num_sids, ret);
  288. dma_unmap_single(&dummy, dma_handle,
  289. num_sids *sizeof(uint32_t), DMA_TO_DEVICE);
  290. map_error:
  291. if (qtee_en)
  292. qtee_shmbridge_free_shm(&shm);
  293. else
  294. kfree(sec_sid);
  295. return ret;
  296. }
  297. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  298. {
  299. u32 ret;
  300. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  301. return 0;
  302. /* detach_all_contexts */
  303. ret = sde_kms_mmu_detach(sde_kms, false);
  304. if (ret) {
  305. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  306. goto mmu_error;
  307. }
  308. ret = _sde_kms_scm_call(sde_kms, vmid);
  309. if (ret) {
  310. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  311. goto scm_error;
  312. }
  313. return 0;
  314. scm_error:
  315. sde_kms_mmu_attach(sde_kms, false);
  316. mmu_error:
  317. atomic_dec(&sde_kms->detach_all_cb);
  318. return ret;
  319. }
  320. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  321. u32 old_vmid)
  322. {
  323. u32 ret;
  324. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  325. return 0;
  326. ret = _sde_kms_scm_call(sde_kms, vmid);
  327. if (ret) {
  328. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  329. goto scm_error;
  330. }
  331. /* attach_all_contexts */
  332. ret = sde_kms_mmu_attach(sde_kms, false);
  333. if (ret) {
  334. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  335. goto mmu_error;
  336. }
  337. return 0;
  338. mmu_error:
  339. _sde_kms_scm_call(sde_kms, old_vmid);
  340. scm_error:
  341. atomic_inc(&sde_kms->detach_all_cb);
  342. return ret;
  343. }
  344. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  345. {
  346. u32 ret;
  347. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  348. return 0;
  349. /* detach secure_context */
  350. ret = sde_kms_mmu_detach(sde_kms, true);
  351. if (ret) {
  352. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  353. goto mmu_error;
  354. }
  355. ret = _sde_kms_scm_call(sde_kms, vmid);
  356. if (ret) {
  357. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  358. goto scm_error;
  359. }
  360. return 0;
  361. scm_error:
  362. sde_kms_mmu_attach(sde_kms, true);
  363. mmu_error:
  364. atomic_dec(&sde_kms->detach_sec_cb);
  365. return ret;
  366. }
  367. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  368. u32 old_vmid)
  369. {
  370. u32 ret;
  371. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  372. return 0;
  373. ret = _sde_kms_scm_call(sde_kms, vmid);
  374. if (ret) {
  375. goto scm_error;
  376. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  377. }
  378. ret = sde_kms_mmu_attach(sde_kms, true);
  379. if (ret) {
  380. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  381. goto mmu_error;
  382. }
  383. return 0;
  384. mmu_error:
  385. _sde_kms_scm_call(sde_kms, old_vmid);
  386. scm_error:
  387. atomic_inc(&sde_kms->detach_sec_cb);
  388. return ret;
  389. }
  390. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  391. struct drm_crtc *crtc, bool enable)
  392. {
  393. int ret;
  394. if (enable) {
  395. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  396. if (ret < 0) {
  397. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  398. return ret;
  399. }
  400. sde_crtc_misr_setup(crtc, true, 1);
  401. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  402. if (ret) {
  403. sde_crtc_misr_setup(crtc, false, 0);
  404. pm_runtime_put_sync(sde_kms->dev->dev);
  405. return ret;
  406. }
  407. } else {
  408. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  409. sde_crtc_misr_setup(crtc, false, 0);
  410. pm_runtime_put_sync(sde_kms->dev->dev);
  411. }
  412. return 0;
  413. }
  414. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  415. bool post_commit)
  416. {
  417. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  418. int old_smmu_state = smmu_state->state;
  419. int ret = 0;
  420. u32 vmid;
  421. if (!sde_kms || !crtc) {
  422. SDE_ERROR("invalid argument(s)\n");
  423. return -EINVAL;
  424. }
  425. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  426. post_commit, smmu_state->sui_misr_state,
  427. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  428. if ((!smmu_state->transition_type) ||
  429. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  430. /* Bail out */
  431. return 0;
  432. /* enable sui misr if requested, before the transition */
  433. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  434. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  435. if (ret) {
  436. smmu_state->sui_misr_state = NONE;
  437. goto end;
  438. }
  439. }
  440. mutex_lock(&sde_kms->secure_transition_lock);
  441. switch (smmu_state->state) {
  442. case DETACH_ALL_REQ:
  443. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  444. if (!ret)
  445. smmu_state->state = DETACHED;
  446. break;
  447. case ATTACH_ALL_REQ:
  448. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  449. VMID_CP_SEC_DISPLAY);
  450. if (!ret) {
  451. smmu_state->state = ATTACHED;
  452. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  453. }
  454. break;
  455. case DETACH_SEC_REQ:
  456. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  457. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  458. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  459. if (!ret)
  460. smmu_state->state = DETACHED_SEC;
  461. break;
  462. case ATTACH_SEC_REQ:
  463. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  464. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  465. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  466. if (!ret) {
  467. smmu_state->state = ATTACHED;
  468. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  469. }
  470. break;
  471. default:
  472. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  473. DRMID(crtc), smmu_state->state,
  474. smmu_state->transition_type);
  475. ret = -EINVAL;
  476. break;
  477. }
  478. mutex_unlock(&sde_kms->secure_transition_lock);
  479. /* disable sui misr if requested, after the transition */
  480. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  481. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  482. if (ret)
  483. goto end;
  484. }
  485. end:
  486. smmu_state->transition_error = false;
  487. if (ret) {
  488. smmu_state->transition_error = true;
  489. SDE_ERROR(
  490. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  491. DRMID(crtc), old_smmu_state, smmu_state->state,
  492. smmu_state->secure_level, ret);
  493. smmu_state->state = smmu_state->prev_state;
  494. smmu_state->secure_level = smmu_state->prev_secure_level;
  495. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  496. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  497. }
  498. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  499. DRMID(crtc), old_smmu_state, smmu_state->state,
  500. smmu_state->secure_level, ret);
  501. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  502. smmu_state->transition_type,
  503. smmu_state->transition_error,
  504. smmu_state->secure_level, smmu_state->prev_secure_level,
  505. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  506. smmu_state->sui_misr_state = NONE;
  507. smmu_state->transition_type = NONE;
  508. return ret;
  509. }
  510. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  511. struct drm_atomic_state *state)
  512. {
  513. struct drm_crtc *crtc;
  514. struct drm_crtc_state *old_crtc_state;
  515. struct drm_plane_state *old_plane_state, *new_plane_state;
  516. struct drm_plane *plane;
  517. struct drm_plane_state *plane_state;
  518. struct sde_kms *sde_kms = to_sde_kms(kms);
  519. struct drm_device *dev = sde_kms->dev;
  520. int i, ops = 0, ret = 0;
  521. bool old_valid_fb = false;
  522. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  523. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  524. if (!crtc->state || !crtc->state->active)
  525. continue;
  526. /*
  527. * It is safe to assume only one active crtc,
  528. * and compatible translation modes on the
  529. * planes staged on this crtc.
  530. * otherwise validation would have failed.
  531. * For this CRTC,
  532. */
  533. /*
  534. * 1. Check if old state on the CRTC has planes
  535. * staged with valid fbs
  536. */
  537. for_each_old_plane_in_state(state, plane, plane_state, i) {
  538. if (!plane_state->crtc)
  539. continue;
  540. if (plane_state->fb) {
  541. old_valid_fb = true;
  542. break;
  543. }
  544. }
  545. /*
  546. * 2.Get the operations needed to be performed before
  547. * secure transition can be initiated.
  548. */
  549. ops = sde_crtc_get_secure_transition_ops(crtc,
  550. old_crtc_state, old_valid_fb);
  551. if (ops < 0) {
  552. SDE_ERROR("invalid secure operations %x\n", ops);
  553. return ops;
  554. }
  555. if (!ops) {
  556. smmu_state->transition_error = false;
  557. goto no_ops;
  558. }
  559. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  560. crtc->base.id, ops, crtc->state);
  561. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  562. /* 3. Perform operations needed for secure transition */
  563. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  564. SDE_DEBUG("wait_for_transfer_done\n");
  565. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  566. }
  567. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  568. SDE_DEBUG("cleanup planes\n");
  569. drm_atomic_helper_cleanup_planes(dev, state);
  570. for_each_oldnew_plane_in_state(state, plane,
  571. old_plane_state, new_plane_state, i)
  572. sde_plane_destroy_fb(old_plane_state);
  573. }
  574. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  575. SDE_DEBUG("secure ctrl\n");
  576. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  577. }
  578. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  579. SDE_DEBUG("prepare planes %d",
  580. crtc->state->plane_mask);
  581. drm_atomic_crtc_for_each_plane(plane,
  582. crtc) {
  583. const struct drm_plane_helper_funcs *funcs;
  584. plane_state = plane->state;
  585. funcs = plane->helper_private;
  586. SDE_DEBUG("psde:%d FB[%u]\n",
  587. plane->base.id,
  588. plane->fb->base.id);
  589. if (!funcs)
  590. continue;
  591. if (funcs->prepare_fb(plane, plane_state)) {
  592. ret = funcs->prepare_fb(plane,
  593. plane_state);
  594. if (ret)
  595. return ret;
  596. }
  597. }
  598. }
  599. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  600. SDE_DEBUG("secure operations completed\n");
  601. }
  602. no_ops:
  603. return 0;
  604. }
  605. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  606. unsigned int splash_buffer_size,
  607. unsigned int ramdump_base,
  608. unsigned int ramdump_buffer_size)
  609. {
  610. unsigned long pfn_start, pfn_end, pfn_idx;
  611. int ret = 0;
  612. if (!mem_addr || !splash_buffer_size) {
  613. SDE_ERROR("invalid params\n");
  614. return -EINVAL;
  615. }
  616. /* leave ramdump memory only if base address matches */
  617. if (ramdump_base == mem_addr &&
  618. ramdump_buffer_size <= splash_buffer_size) {
  619. mem_addr += ramdump_buffer_size;
  620. splash_buffer_size -= ramdump_buffer_size;
  621. }
  622. pfn_start = mem_addr >> PAGE_SHIFT;
  623. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  624. if (ret) {
  625. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  626. return ret;
  627. }
  628. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  629. free_reserved_page(pfn_to_page(pfn_idx));
  630. return ret;
  631. }
  632. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  633. struct sde_splash_mem *splash)
  634. {
  635. struct msm_mmu *mmu = NULL;
  636. int ret = 0;
  637. if (!sde_kms->aspace[0]) {
  638. SDE_ERROR("aspace not found for sde kms node\n");
  639. return -EINVAL;
  640. }
  641. mmu = sde_kms->aspace[0]->mmu;
  642. if (!mmu) {
  643. SDE_ERROR("mmu not found for aspace\n");
  644. return -EINVAL;
  645. }
  646. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  647. SDE_ERROR("invalid input params for map\n");
  648. return -EINVAL;
  649. }
  650. if (!splash->ref_cnt) {
  651. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  652. splash->splash_buf_base,
  653. splash->splash_buf_size,
  654. IOMMU_READ | IOMMU_NOEXEC);
  655. if (ret)
  656. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  657. }
  658. splash->ref_cnt++;
  659. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  660. splash->splash_buf_base,
  661. splash->splash_buf_size,
  662. splash->ref_cnt);
  663. return ret;
  664. }
  665. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  666. {
  667. int i = 0;
  668. int ret = 0;
  669. if (!sde_kms)
  670. return -EINVAL;
  671. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  672. ret = _sde_kms_splash_mem_get(sde_kms,
  673. sde_kms->splash_data.splash_display[i].splash);
  674. if (ret)
  675. return ret;
  676. }
  677. return ret;
  678. }
  679. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  680. struct sde_splash_mem *splash)
  681. {
  682. struct msm_mmu *mmu = NULL;
  683. int rc = 0;
  684. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  685. SDE_ERROR("invalid params\n");
  686. return -EINVAL;
  687. }
  688. mmu = sde_kms->aspace[0]->mmu;
  689. if (!splash || !splash->ref_cnt ||
  690. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  691. return -EINVAL;
  692. splash->ref_cnt--;
  693. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  694. splash->splash_buf_base, splash->ref_cnt);
  695. if (!splash->ref_cnt) {
  696. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  697. splash->splash_buf_size);
  698. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  699. splash->splash_buf_size, splash->ramdump_base,
  700. splash->ramdump_size);
  701. splash->splash_buf_base = 0;
  702. splash->splash_buf_size = 0;
  703. }
  704. return rc;
  705. }
  706. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  707. {
  708. int i = 0;
  709. int ret = 0;
  710. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  711. return -EINVAL;
  712. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  713. ret = _sde_kms_splash_mem_put(sde_kms,
  714. sde_kms->splash_data.splash_display[i].splash);
  715. if (ret)
  716. return ret;
  717. }
  718. return ret;
  719. }
  720. static void sde_kms_prepare_commit(struct msm_kms *kms,
  721. struct drm_atomic_state *state)
  722. {
  723. struct sde_kms *sde_kms;
  724. struct msm_drm_private *priv;
  725. struct drm_device *dev;
  726. struct drm_encoder *encoder;
  727. struct drm_crtc *crtc;
  728. struct drm_crtc_state *crtc_state;
  729. int i, rc;
  730. if (!kms)
  731. return;
  732. sde_kms = to_sde_kms(kms);
  733. dev = sde_kms->dev;
  734. if (!dev || !dev->dev_private)
  735. return;
  736. priv = dev->dev_private;
  737. SDE_ATRACE_BEGIN("prepare_commit");
  738. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  739. if (rc < 0) {
  740. SDE_ERROR("failed to enable power resources %d\n", rc);
  741. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  742. goto end;
  743. }
  744. if (sde_kms->first_kickoff) {
  745. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  746. sde_kms->first_kickoff = false;
  747. }
  748. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  749. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  750. head) {
  751. if (encoder->crtc != crtc)
  752. continue;
  753. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  754. SDE_ERROR("crtc:%d, initiating hw reset\n",
  755. DRMID(crtc));
  756. sde_encoder_needs_hw_reset(encoder);
  757. sde_crtc_set_needs_hw_reset(crtc);
  758. }
  759. }
  760. }
  761. /*
  762. * NOTE: for secure use cases we want to apply the new HW
  763. * configuration only after completing preparation for secure
  764. * transitions prepare below if any transtions is required.
  765. */
  766. sde_kms_prepare_secure_transition(kms, state);
  767. end:
  768. SDE_ATRACE_END("prepare_commit");
  769. }
  770. static void sde_kms_commit(struct msm_kms *kms,
  771. struct drm_atomic_state *old_state)
  772. {
  773. struct sde_kms *sde_kms;
  774. struct drm_crtc *crtc;
  775. struct drm_crtc_state *old_crtc_state;
  776. int i;
  777. if (!kms || !old_state)
  778. return;
  779. sde_kms = to_sde_kms(kms);
  780. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  781. SDE_ERROR("power resource is not enabled\n");
  782. return;
  783. }
  784. SDE_ATRACE_BEGIN("sde_kms_commit");
  785. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  786. if (crtc->state->active) {
  787. SDE_EVT32(DRMID(crtc));
  788. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  789. }
  790. }
  791. SDE_ATRACE_END("sde_kms_commit");
  792. }
  793. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  794. struct sde_splash_display *splash_display)
  795. {
  796. if (!sde_kms || !splash_display ||
  797. !sde_kms->splash_data.num_splash_displays)
  798. return;
  799. if (sde_kms->splash_data.num_splash_regions)
  800. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  801. sde_kms->splash_data.num_splash_displays--;
  802. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  803. sde_kms->splash_data.num_splash_displays);
  804. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  805. }
  806. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  807. struct drm_crtc *crtc)
  808. {
  809. struct msm_drm_private *priv;
  810. struct sde_splash_display *splash_display;
  811. int i;
  812. if (!sde_kms || !crtc)
  813. return;
  814. priv = sde_kms->dev->dev_private;
  815. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  816. return;
  817. SDE_EVT32(DRMID(crtc), crtc->state->active,
  818. sde_kms->splash_data.num_splash_displays);
  819. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  820. splash_display = &sde_kms->splash_data.splash_display[i];
  821. if (splash_display->encoder &&
  822. crtc == splash_display->encoder->crtc)
  823. break;
  824. }
  825. if (i >= MAX_DSI_DISPLAYS)
  826. return;
  827. if (splash_display->cont_splash_enabled) {
  828. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  829. splash_display, false);
  830. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  831. }
  832. /* remove the votes if all displays are done with splash */
  833. if (!sde_kms->splash_data.num_splash_displays) {
  834. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  835. sde_power_data_bus_set_quota(&priv->phandle, i,
  836. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  837. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  838. pm_runtime_put_sync(sde_kms->dev->dev);
  839. }
  840. }
  841. static void sde_kms_complete_commit(struct msm_kms *kms,
  842. struct drm_atomic_state *old_state)
  843. {
  844. struct sde_kms *sde_kms;
  845. struct msm_drm_private *priv;
  846. struct drm_crtc *crtc;
  847. struct drm_crtc_state *old_crtc_state;
  848. struct drm_connector *connector;
  849. struct drm_connector_state *old_conn_state;
  850. struct msm_display_conn_params params;
  851. int i, rc = 0;
  852. if (!kms || !old_state)
  853. return;
  854. sde_kms = to_sde_kms(kms);
  855. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  856. return;
  857. priv = sde_kms->dev->dev_private;
  858. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  859. SDE_ERROR("power resource is not enabled\n");
  860. return;
  861. }
  862. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  863. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  864. sde_crtc_complete_commit(crtc, old_crtc_state);
  865. /* complete secure transitions if any */
  866. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  867. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  868. }
  869. for_each_old_connector_in_state(old_state, connector,
  870. old_conn_state, i) {
  871. struct sde_connector *c_conn;
  872. c_conn = to_sde_connector(connector);
  873. if (!c_conn->ops.post_kickoff)
  874. continue;
  875. memset(&params, 0, sizeof(params));
  876. sde_connector_complete_qsync_commit(connector, &params);
  877. rc = c_conn->ops.post_kickoff(connector, &params);
  878. if (rc) {
  879. pr_err("Connector Post kickoff failed rc=%d\n",
  880. rc);
  881. }
  882. }
  883. pm_runtime_put_sync(sde_kms->dev->dev);
  884. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  885. _sde_kms_release_splash_resource(sde_kms, crtc);
  886. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  887. SDE_ATRACE_END("sde_kms_complete_commit");
  888. }
  889. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  890. struct drm_crtc *crtc)
  891. {
  892. struct drm_encoder *encoder;
  893. struct drm_device *dev;
  894. int ret;
  895. if (!kms || !crtc || !crtc->state) {
  896. SDE_ERROR("invalid params\n");
  897. return;
  898. }
  899. dev = crtc->dev;
  900. if (!crtc->state->enable) {
  901. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  902. return;
  903. }
  904. if (!crtc->state->active) {
  905. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  906. return;
  907. }
  908. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  909. SDE_ERROR("power resource is not enabled\n");
  910. return;
  911. }
  912. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  913. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  914. if (encoder->crtc != crtc)
  915. continue;
  916. /*
  917. * Wait for post-flush if necessary to delay before
  918. * plane_cleanup. For example, wait for vsync in case of video
  919. * mode panels. This may be a no-op for command mode panels.
  920. */
  921. SDE_EVT32_VERBOSE(DRMID(crtc));
  922. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  923. if (ret && ret != -EWOULDBLOCK) {
  924. SDE_ERROR("wait for commit done returned %d\n", ret);
  925. sde_crtc_request_frame_reset(crtc);
  926. break;
  927. }
  928. sde_crtc_complete_flip(crtc, NULL);
  929. }
  930. sde_crtc_static_cache_read_kickoff(crtc);
  931. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  932. }
  933. static void sde_kms_prepare_fence(struct msm_kms *kms,
  934. struct drm_atomic_state *old_state)
  935. {
  936. struct drm_crtc *crtc;
  937. struct drm_crtc_state *old_crtc_state;
  938. int i, rc;
  939. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  940. SDE_ERROR("invalid argument(s)\n");
  941. return;
  942. }
  943. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  944. retry:
  945. /* attempt to acquire ww mutex for connection */
  946. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  947. old_state->acquire_ctx);
  948. if (rc == -EDEADLK) {
  949. drm_modeset_backoff(old_state->acquire_ctx);
  950. goto retry;
  951. }
  952. /* old_state actually contains updated crtc pointers */
  953. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  954. if (crtc->state->active || crtc->state->active_changed)
  955. sde_crtc_prepare_commit(crtc, old_crtc_state);
  956. }
  957. SDE_ATRACE_END("sde_kms_prepare_fence");
  958. }
  959. /**
  960. * _sde_kms_get_displays - query for underlying display handles and cache them
  961. * @sde_kms: Pointer to sde kms structure
  962. * Returns: Zero on success
  963. */
  964. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  965. {
  966. int rc = -ENOMEM;
  967. if (!sde_kms) {
  968. SDE_ERROR("invalid sde kms\n");
  969. return -EINVAL;
  970. }
  971. /* dsi */
  972. sde_kms->dsi_displays = NULL;
  973. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  974. if (sde_kms->dsi_display_count) {
  975. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  976. sizeof(void *),
  977. GFP_KERNEL);
  978. if (!sde_kms->dsi_displays) {
  979. SDE_ERROR("failed to allocate dsi displays\n");
  980. goto exit_deinit_dsi;
  981. }
  982. sde_kms->dsi_display_count =
  983. dsi_display_get_active_displays(sde_kms->dsi_displays,
  984. sde_kms->dsi_display_count);
  985. }
  986. /* wb */
  987. sde_kms->wb_displays = NULL;
  988. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  989. if (sde_kms->wb_display_count) {
  990. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  991. sizeof(void *),
  992. GFP_KERNEL);
  993. if (!sde_kms->wb_displays) {
  994. SDE_ERROR("failed to allocate wb displays\n");
  995. goto exit_deinit_wb;
  996. }
  997. sde_kms->wb_display_count =
  998. wb_display_get_displays(sde_kms->wb_displays,
  999. sde_kms->wb_display_count);
  1000. }
  1001. /* dp */
  1002. sde_kms->dp_displays = NULL;
  1003. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1004. if (sde_kms->dp_display_count) {
  1005. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1006. sizeof(void *), GFP_KERNEL);
  1007. if (!sde_kms->dp_displays) {
  1008. SDE_ERROR("failed to allocate dp displays\n");
  1009. goto exit_deinit_dp;
  1010. }
  1011. sde_kms->dp_display_count =
  1012. dp_display_get_displays(sde_kms->dp_displays,
  1013. sde_kms->dp_display_count);
  1014. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1015. }
  1016. return 0;
  1017. exit_deinit_dp:
  1018. kfree(sde_kms->dp_displays);
  1019. sde_kms->dp_stream_count = 0;
  1020. sde_kms->dp_display_count = 0;
  1021. sde_kms->dp_displays = NULL;
  1022. exit_deinit_wb:
  1023. kfree(sde_kms->wb_displays);
  1024. sde_kms->wb_display_count = 0;
  1025. sde_kms->wb_displays = NULL;
  1026. exit_deinit_dsi:
  1027. kfree(sde_kms->dsi_displays);
  1028. sde_kms->dsi_display_count = 0;
  1029. sde_kms->dsi_displays = NULL;
  1030. return rc;
  1031. }
  1032. /**
  1033. * _sde_kms_release_displays - release cache of underlying display handles
  1034. * @sde_kms: Pointer to sde kms structure
  1035. */
  1036. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1037. {
  1038. if (!sde_kms) {
  1039. SDE_ERROR("invalid sde kms\n");
  1040. return;
  1041. }
  1042. kfree(sde_kms->wb_displays);
  1043. sde_kms->wb_displays = NULL;
  1044. sde_kms->wb_display_count = 0;
  1045. kfree(sde_kms->dsi_displays);
  1046. sde_kms->dsi_displays = NULL;
  1047. sde_kms->dsi_display_count = 0;
  1048. }
  1049. /**
  1050. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1051. * for underlying displays
  1052. * @dev: Pointer to drm device structure
  1053. * @priv: Pointer to private drm device data
  1054. * @sde_kms: Pointer to sde kms structure
  1055. * Returns: Zero on success
  1056. */
  1057. static int _sde_kms_setup_displays(struct drm_device *dev,
  1058. struct msm_drm_private *priv,
  1059. struct sde_kms *sde_kms)
  1060. {
  1061. static const struct sde_connector_ops dsi_ops = {
  1062. .set_info_blob = dsi_conn_set_info_blob,
  1063. .detect = dsi_conn_detect,
  1064. .get_modes = dsi_connector_get_modes,
  1065. .pre_destroy = dsi_connector_put_modes,
  1066. .mode_valid = dsi_conn_mode_valid,
  1067. .get_info = dsi_display_get_info,
  1068. .set_backlight = dsi_display_set_backlight,
  1069. .soft_reset = dsi_display_soft_reset,
  1070. .pre_kickoff = dsi_conn_pre_kickoff,
  1071. .clk_ctrl = dsi_display_clk_ctrl,
  1072. .set_power = dsi_display_set_power,
  1073. .get_mode_info = dsi_conn_get_mode_info,
  1074. .get_dst_format = dsi_display_get_dst_format,
  1075. .post_kickoff = dsi_conn_post_kickoff,
  1076. .check_status = dsi_display_check_status,
  1077. .enable_event = dsi_conn_enable_event,
  1078. .cmd_transfer = dsi_display_cmd_transfer,
  1079. .cont_splash_config = dsi_display_cont_splash_config,
  1080. .get_panel_vfp = dsi_display_get_panel_vfp,
  1081. .get_default_lms = dsi_display_get_default_lms,
  1082. };
  1083. static const struct sde_connector_ops wb_ops = {
  1084. .post_init = sde_wb_connector_post_init,
  1085. .set_info_blob = sde_wb_connector_set_info_blob,
  1086. .detect = sde_wb_connector_detect,
  1087. .get_modes = sde_wb_connector_get_modes,
  1088. .set_property = sde_wb_connector_set_property,
  1089. .get_info = sde_wb_get_info,
  1090. .soft_reset = NULL,
  1091. .get_mode_info = sde_wb_get_mode_info,
  1092. .get_dst_format = NULL,
  1093. .check_status = NULL,
  1094. .cmd_transfer = NULL,
  1095. .cont_splash_config = NULL,
  1096. .get_panel_vfp = NULL,
  1097. };
  1098. static const struct sde_connector_ops dp_ops = {
  1099. .post_init = dp_connector_post_init,
  1100. .detect = dp_connector_detect,
  1101. .get_modes = dp_connector_get_modes,
  1102. .atomic_check = dp_connector_atomic_check,
  1103. .mode_valid = dp_connector_mode_valid,
  1104. .get_info = dp_connector_get_info,
  1105. .get_mode_info = dp_connector_get_mode_info,
  1106. .post_open = dp_connector_post_open,
  1107. .check_status = NULL,
  1108. .set_colorspace = dp_connector_set_colorspace,
  1109. .config_hdr = dp_connector_config_hdr,
  1110. .cmd_transfer = NULL,
  1111. .cont_splash_config = NULL,
  1112. .get_panel_vfp = NULL,
  1113. .update_pps = dp_connector_update_pps,
  1114. };
  1115. struct msm_display_info info;
  1116. struct drm_encoder *encoder;
  1117. void *display, *connector;
  1118. int i, max_encoders;
  1119. int rc = 0;
  1120. if (!dev || !priv || !sde_kms) {
  1121. SDE_ERROR("invalid argument(s)\n");
  1122. return -EINVAL;
  1123. }
  1124. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1125. sde_kms->dp_display_count +
  1126. sde_kms->dp_stream_count;
  1127. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1128. max_encoders = ARRAY_SIZE(priv->encoders);
  1129. SDE_ERROR("capping number of displays to %d", max_encoders);
  1130. }
  1131. /* wb */
  1132. for (i = 0; i < sde_kms->wb_display_count &&
  1133. priv->num_encoders < max_encoders; ++i) {
  1134. display = sde_kms->wb_displays[i];
  1135. encoder = NULL;
  1136. memset(&info, 0x0, sizeof(info));
  1137. rc = sde_wb_get_info(NULL, &info, display);
  1138. if (rc) {
  1139. SDE_ERROR("wb get_info %d failed\n", i);
  1140. continue;
  1141. }
  1142. encoder = sde_encoder_init(dev, &info);
  1143. if (IS_ERR_OR_NULL(encoder)) {
  1144. SDE_ERROR("encoder init failed for wb %d\n", i);
  1145. continue;
  1146. }
  1147. rc = sde_wb_drm_init(display, encoder);
  1148. if (rc) {
  1149. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1150. sde_encoder_destroy(encoder);
  1151. continue;
  1152. }
  1153. connector = sde_connector_init(dev,
  1154. encoder,
  1155. 0,
  1156. display,
  1157. &wb_ops,
  1158. DRM_CONNECTOR_POLL_HPD,
  1159. DRM_MODE_CONNECTOR_VIRTUAL);
  1160. if (connector) {
  1161. priv->encoders[priv->num_encoders++] = encoder;
  1162. priv->connectors[priv->num_connectors++] = connector;
  1163. } else {
  1164. SDE_ERROR("wb %d connector init failed\n", i);
  1165. sde_wb_drm_deinit(display);
  1166. sde_encoder_destroy(encoder);
  1167. }
  1168. }
  1169. /* dsi */
  1170. for (i = 0; i < sde_kms->dsi_display_count &&
  1171. priv->num_encoders < max_encoders; ++i) {
  1172. display = sde_kms->dsi_displays[i];
  1173. encoder = NULL;
  1174. memset(&info, 0x0, sizeof(info));
  1175. rc = dsi_display_get_info(NULL, &info, display);
  1176. if (rc) {
  1177. SDE_ERROR("dsi get_info %d failed\n", i);
  1178. continue;
  1179. }
  1180. encoder = sde_encoder_init(dev, &info);
  1181. if (IS_ERR_OR_NULL(encoder)) {
  1182. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1183. continue;
  1184. }
  1185. rc = dsi_display_drm_bridge_init(display, encoder);
  1186. if (rc) {
  1187. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1188. sde_encoder_destroy(encoder);
  1189. continue;
  1190. }
  1191. connector = sde_connector_init(dev,
  1192. encoder,
  1193. dsi_display_get_drm_panel(display),
  1194. display,
  1195. &dsi_ops,
  1196. DRM_CONNECTOR_POLL_HPD,
  1197. DRM_MODE_CONNECTOR_DSI);
  1198. if (connector) {
  1199. priv->encoders[priv->num_encoders++] = encoder;
  1200. priv->connectors[priv->num_connectors++] = connector;
  1201. } else {
  1202. SDE_ERROR("dsi %d connector init failed\n", i);
  1203. dsi_display_drm_bridge_deinit(display);
  1204. sde_encoder_destroy(encoder);
  1205. continue;
  1206. }
  1207. rc = dsi_display_drm_ext_bridge_init(display,
  1208. encoder, connector);
  1209. if (rc) {
  1210. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1211. dsi_display_drm_bridge_deinit(display);
  1212. sde_connector_destroy(connector);
  1213. sde_encoder_destroy(encoder);
  1214. }
  1215. }
  1216. /* dp */
  1217. for (i = 0; i < sde_kms->dp_display_count &&
  1218. priv->num_encoders < max_encoders; ++i) {
  1219. int idx;
  1220. display = sde_kms->dp_displays[i];
  1221. encoder = NULL;
  1222. memset(&info, 0x0, sizeof(info));
  1223. rc = dp_connector_get_info(NULL, &info, display);
  1224. if (rc) {
  1225. SDE_ERROR("dp get_info %d failed\n", i);
  1226. continue;
  1227. }
  1228. encoder = sde_encoder_init(dev, &info);
  1229. if (IS_ERR_OR_NULL(encoder)) {
  1230. SDE_ERROR("dp encoder init failed %d\n", i);
  1231. continue;
  1232. }
  1233. rc = dp_drm_bridge_init(display, encoder);
  1234. if (rc) {
  1235. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1236. sde_encoder_destroy(encoder);
  1237. continue;
  1238. }
  1239. connector = sde_connector_init(dev,
  1240. encoder,
  1241. NULL,
  1242. display,
  1243. &dp_ops,
  1244. DRM_CONNECTOR_POLL_HPD,
  1245. DRM_MODE_CONNECTOR_DisplayPort);
  1246. if (connector) {
  1247. priv->encoders[priv->num_encoders++] = encoder;
  1248. priv->connectors[priv->num_connectors++] = connector;
  1249. } else {
  1250. SDE_ERROR("dp %d connector init failed\n", i);
  1251. dp_drm_bridge_deinit(display);
  1252. sde_encoder_destroy(encoder);
  1253. }
  1254. /* update display cap to MST_MODE for DP MST encoders */
  1255. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1256. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1257. priv->num_encoders < max_encoders; idx++) {
  1258. info.h_tile_instance[0] = idx;
  1259. encoder = sde_encoder_init(dev, &info);
  1260. if (IS_ERR_OR_NULL(encoder)) {
  1261. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1262. continue;
  1263. }
  1264. rc = dp_mst_drm_bridge_init(display, encoder);
  1265. if (rc) {
  1266. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1267. i, rc);
  1268. sde_encoder_destroy(encoder);
  1269. continue;
  1270. }
  1271. priv->encoders[priv->num_encoders++] = encoder;
  1272. }
  1273. }
  1274. return 0;
  1275. }
  1276. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1277. {
  1278. struct msm_drm_private *priv;
  1279. int i;
  1280. if (!sde_kms) {
  1281. SDE_ERROR("invalid sde_kms\n");
  1282. return;
  1283. } else if (!sde_kms->dev) {
  1284. SDE_ERROR("invalid dev\n");
  1285. return;
  1286. } else if (!sde_kms->dev->dev_private) {
  1287. SDE_ERROR("invalid dev_private\n");
  1288. return;
  1289. }
  1290. priv = sde_kms->dev->dev_private;
  1291. for (i = 0; i < priv->num_crtcs; i++)
  1292. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1293. priv->num_crtcs = 0;
  1294. for (i = 0; i < priv->num_planes; i++)
  1295. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1296. priv->num_planes = 0;
  1297. for (i = 0; i < priv->num_connectors; i++)
  1298. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1299. priv->num_connectors = 0;
  1300. for (i = 0; i < priv->num_encoders; i++)
  1301. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1302. priv->num_encoders = 0;
  1303. _sde_kms_release_displays(sde_kms);
  1304. }
  1305. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1306. {
  1307. struct drm_device *dev;
  1308. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1309. struct drm_crtc *crtc;
  1310. struct msm_drm_private *priv;
  1311. struct sde_mdss_cfg *catalog;
  1312. int primary_planes_idx = 0, i, ret;
  1313. int max_crtc_count;
  1314. u32 sspp_id[MAX_PLANES];
  1315. u32 master_plane_id[MAX_PLANES];
  1316. u32 num_virt_planes = 0;
  1317. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1318. SDE_ERROR("invalid sde_kms\n");
  1319. return -EINVAL;
  1320. }
  1321. dev = sde_kms->dev;
  1322. priv = dev->dev_private;
  1323. catalog = sde_kms->catalog;
  1324. ret = sde_core_irq_domain_add(sde_kms);
  1325. if (ret)
  1326. goto fail_irq;
  1327. /*
  1328. * Query for underlying display drivers, and create connectors,
  1329. * bridges and encoders for them.
  1330. */
  1331. if (!_sde_kms_get_displays(sde_kms))
  1332. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1333. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1334. /* Create the planes */
  1335. for (i = 0; i < catalog->sspp_count; i++) {
  1336. bool primary = true;
  1337. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1338. || primary_planes_idx >= max_crtc_count)
  1339. primary = false;
  1340. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1341. (1UL << max_crtc_count) - 1, 0);
  1342. if (IS_ERR(plane)) {
  1343. SDE_ERROR("sde_plane_init failed\n");
  1344. ret = PTR_ERR(plane);
  1345. goto fail;
  1346. }
  1347. priv->planes[priv->num_planes++] = plane;
  1348. if (primary)
  1349. primary_planes[primary_planes_idx++] = plane;
  1350. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1351. sde_is_custom_client()) {
  1352. int priority =
  1353. catalog->sspp[i].sblk->smart_dma_priority;
  1354. sspp_id[priority - 1] = catalog->sspp[i].id;
  1355. master_plane_id[priority - 1] = plane->base.id;
  1356. num_virt_planes++;
  1357. }
  1358. }
  1359. /* Initialize smart DMA virtual planes */
  1360. for (i = 0; i < num_virt_planes; i++) {
  1361. plane = sde_plane_init(dev, sspp_id[i], false,
  1362. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1363. if (IS_ERR(plane)) {
  1364. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1365. ret = PTR_ERR(plane);
  1366. goto fail;
  1367. }
  1368. priv->planes[priv->num_planes++] = plane;
  1369. }
  1370. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1371. /* Create one CRTC per encoder */
  1372. for (i = 0; i < max_crtc_count; i++) {
  1373. crtc = sde_crtc_init(dev, primary_planes[i]);
  1374. if (IS_ERR(crtc)) {
  1375. ret = PTR_ERR(crtc);
  1376. goto fail;
  1377. }
  1378. priv->crtcs[priv->num_crtcs++] = crtc;
  1379. }
  1380. if (sde_is_custom_client()) {
  1381. /* All CRTCs are compatible with all planes */
  1382. for (i = 0; i < priv->num_planes; i++)
  1383. priv->planes[i]->possible_crtcs =
  1384. (1 << priv->num_crtcs) - 1;
  1385. }
  1386. /* All CRTCs are compatible with all encoders */
  1387. for (i = 0; i < priv->num_encoders; i++)
  1388. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1389. return 0;
  1390. fail:
  1391. _sde_kms_drm_obj_destroy(sde_kms);
  1392. fail_irq:
  1393. sde_core_irq_domain_fini(sde_kms);
  1394. return ret;
  1395. }
  1396. /**
  1397. * sde_kms_timeline_status - provides current timeline status
  1398. * This API should be called without mode config lock.
  1399. * @dev: Pointer to drm device
  1400. */
  1401. void sde_kms_timeline_status(struct drm_device *dev)
  1402. {
  1403. struct drm_crtc *crtc;
  1404. struct drm_connector *conn;
  1405. struct drm_connector_list_iter conn_iter;
  1406. if (!dev) {
  1407. SDE_ERROR("invalid drm device node\n");
  1408. return;
  1409. }
  1410. drm_for_each_crtc(crtc, dev)
  1411. sde_crtc_timeline_status(crtc);
  1412. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1413. /*
  1414. *Probably locked from last close dumping status anyway
  1415. */
  1416. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1417. drm_connector_list_iter_begin(dev, &conn_iter);
  1418. drm_for_each_connector_iter(conn, &conn_iter)
  1419. sde_conn_timeline_status(conn);
  1420. drm_connector_list_iter_end(&conn_iter);
  1421. return;
  1422. }
  1423. mutex_lock(&dev->mode_config.mutex);
  1424. drm_connector_list_iter_begin(dev, &conn_iter);
  1425. drm_for_each_connector_iter(conn, &conn_iter)
  1426. sde_conn_timeline_status(conn);
  1427. drm_connector_list_iter_end(&conn_iter);
  1428. mutex_unlock(&dev->mode_config.mutex);
  1429. }
  1430. static int sde_kms_postinit(struct msm_kms *kms)
  1431. {
  1432. struct sde_kms *sde_kms = to_sde_kms(kms);
  1433. struct drm_device *dev;
  1434. struct drm_crtc *crtc;
  1435. int rc;
  1436. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1437. SDE_ERROR("invalid sde_kms\n");
  1438. return -EINVAL;
  1439. }
  1440. dev = sde_kms->dev;
  1441. rc = _sde_debugfs_init(sde_kms);
  1442. if (rc)
  1443. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1444. drm_for_each_crtc(crtc, dev)
  1445. sde_crtc_post_init(dev, crtc);
  1446. return rc;
  1447. }
  1448. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1449. struct drm_encoder *encoder)
  1450. {
  1451. return rate;
  1452. }
  1453. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1454. struct platform_device *pdev)
  1455. {
  1456. struct drm_device *dev;
  1457. struct msm_drm_private *priv;
  1458. int i;
  1459. if (!sde_kms || !pdev)
  1460. return;
  1461. dev = sde_kms->dev;
  1462. if (!dev)
  1463. return;
  1464. priv = dev->dev_private;
  1465. if (!priv)
  1466. return;
  1467. if (sde_kms->genpd_init) {
  1468. sde_kms->genpd_init = false;
  1469. pm_genpd_remove(&sde_kms->genpd);
  1470. of_genpd_del_provider(pdev->dev.of_node);
  1471. }
  1472. if (sde_kms->hw_intr)
  1473. sde_hw_intr_destroy(sde_kms->hw_intr);
  1474. sde_kms->hw_intr = NULL;
  1475. if (sde_kms->power_event)
  1476. sde_power_handle_unregister_event(
  1477. &priv->phandle, sde_kms->power_event);
  1478. _sde_kms_release_displays(sde_kms);
  1479. _sde_kms_unmap_all_splash_regions(sde_kms);
  1480. /* safe to call these more than once during shutdown */
  1481. _sde_debugfs_destroy(sde_kms);
  1482. _sde_kms_mmu_destroy(sde_kms);
  1483. if (sde_kms->catalog) {
  1484. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1485. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1486. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1487. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1488. }
  1489. }
  1490. if (sde_kms->rm_init)
  1491. sde_rm_destroy(&sde_kms->rm);
  1492. sde_kms->rm_init = false;
  1493. if (sde_kms->catalog)
  1494. sde_hw_catalog_deinit(sde_kms->catalog);
  1495. sde_kms->catalog = NULL;
  1496. if (sde_kms->sid)
  1497. msm_iounmap(pdev, sde_kms->sid);
  1498. sde_kms->sid = NULL;
  1499. if (sde_kms->reg_dma)
  1500. msm_iounmap(pdev, sde_kms->reg_dma);
  1501. sde_kms->reg_dma = NULL;
  1502. if (sde_kms->vbif[VBIF_NRT])
  1503. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1504. sde_kms->vbif[VBIF_NRT] = NULL;
  1505. if (sde_kms->vbif[VBIF_RT])
  1506. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1507. sde_kms->vbif[VBIF_RT] = NULL;
  1508. if (sde_kms->mmio)
  1509. msm_iounmap(pdev, sde_kms->mmio);
  1510. sde_kms->mmio = NULL;
  1511. sde_reg_dma_deinit();
  1512. }
  1513. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1514. {
  1515. int i;
  1516. if (!sde_kms)
  1517. return -EINVAL;
  1518. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1519. struct msm_mmu *mmu;
  1520. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1521. if (!aspace)
  1522. continue;
  1523. mmu = sde_kms->aspace[i]->mmu;
  1524. if (secure_only &&
  1525. !aspace->mmu->funcs->is_domain_secure(mmu))
  1526. continue;
  1527. /* cleanup aspace before detaching */
  1528. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1529. SDE_DEBUG("Detaching domain:%d\n", i);
  1530. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1531. ARRAY_SIZE(iommu_ports));
  1532. aspace->domain_attached = false;
  1533. }
  1534. return 0;
  1535. }
  1536. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1537. {
  1538. int i;
  1539. if (!sde_kms)
  1540. return -EINVAL;
  1541. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1542. struct msm_mmu *mmu;
  1543. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1544. if (!aspace)
  1545. continue;
  1546. mmu = sde_kms->aspace[i]->mmu;
  1547. if (secure_only &&
  1548. !aspace->mmu->funcs->is_domain_secure(mmu))
  1549. continue;
  1550. SDE_DEBUG("Attaching domain:%d\n", i);
  1551. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1552. ARRAY_SIZE(iommu_ports));
  1553. aspace->domain_attached = true;
  1554. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1555. }
  1556. return 0;
  1557. }
  1558. static void sde_kms_destroy(struct msm_kms *kms)
  1559. {
  1560. struct sde_kms *sde_kms;
  1561. struct drm_device *dev;
  1562. if (!kms) {
  1563. SDE_ERROR("invalid kms\n");
  1564. return;
  1565. }
  1566. sde_kms = to_sde_kms(kms);
  1567. dev = sde_kms->dev;
  1568. if (!dev || !dev->dev) {
  1569. SDE_ERROR("invalid device\n");
  1570. return;
  1571. }
  1572. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1573. kfree(sde_kms);
  1574. }
  1575. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1576. struct drm_atomic_state *state)
  1577. {
  1578. struct drm_device *dev = sde_kms->dev;
  1579. struct drm_plane *plane;
  1580. struct drm_plane_state *plane_state;
  1581. struct drm_crtc *crtc;
  1582. struct drm_crtc_state *crtc_state;
  1583. struct drm_connector *conn;
  1584. struct drm_connector_state *conn_state;
  1585. struct drm_connector_list_iter conn_iter;
  1586. int ret = 0;
  1587. drm_for_each_plane(plane, dev) {
  1588. plane_state = drm_atomic_get_plane_state(state, plane);
  1589. if (IS_ERR(plane_state)) {
  1590. ret = PTR_ERR(plane_state);
  1591. SDE_ERROR("error %d getting plane %d state\n",
  1592. ret, DRMID(plane));
  1593. return ret;
  1594. }
  1595. ret = sde_plane_helper_reset_custom_properties(plane,
  1596. plane_state);
  1597. if (ret) {
  1598. SDE_ERROR("error %d resetting plane props %d\n",
  1599. ret, DRMID(plane));
  1600. return ret;
  1601. }
  1602. }
  1603. drm_for_each_crtc(crtc, dev) {
  1604. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1605. if (IS_ERR(crtc_state)) {
  1606. ret = PTR_ERR(crtc_state);
  1607. SDE_ERROR("error %d getting crtc %d state\n",
  1608. ret, DRMID(crtc));
  1609. return ret;
  1610. }
  1611. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1612. if (ret) {
  1613. SDE_ERROR("error %d resetting crtc props %d\n",
  1614. ret, DRMID(crtc));
  1615. return ret;
  1616. }
  1617. }
  1618. drm_connector_list_iter_begin(dev, &conn_iter);
  1619. drm_for_each_connector_iter(conn, &conn_iter) {
  1620. conn_state = drm_atomic_get_connector_state(state, conn);
  1621. if (IS_ERR(conn_state)) {
  1622. ret = PTR_ERR(conn_state);
  1623. SDE_ERROR("error %d getting connector %d state\n",
  1624. ret, DRMID(conn));
  1625. return ret;
  1626. }
  1627. ret = sde_connector_helper_reset_custom_properties(conn,
  1628. conn_state);
  1629. if (ret) {
  1630. SDE_ERROR("error %d resetting connector props %d\n",
  1631. ret, DRMID(conn));
  1632. return ret;
  1633. }
  1634. }
  1635. drm_connector_list_iter_end(&conn_iter);
  1636. return ret;
  1637. }
  1638. static void sde_kms_lastclose(struct msm_kms *kms)
  1639. {
  1640. struct sde_kms *sde_kms;
  1641. struct drm_device *dev;
  1642. struct drm_atomic_state *state;
  1643. struct drm_modeset_acquire_ctx ctx;
  1644. int ret;
  1645. if (!kms) {
  1646. SDE_ERROR("invalid argument\n");
  1647. return;
  1648. }
  1649. sde_kms = to_sde_kms(kms);
  1650. dev = sde_kms->dev;
  1651. drm_modeset_acquire_init(&ctx, 0);
  1652. state = drm_atomic_state_alloc(dev);
  1653. if (!state) {
  1654. ret = -ENOMEM;
  1655. goto out_ctx;
  1656. }
  1657. state->acquire_ctx = &ctx;
  1658. retry:
  1659. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1660. if (ret)
  1661. goto out_state;
  1662. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1663. if (ret)
  1664. goto out_state;
  1665. ret = drm_atomic_commit(state);
  1666. out_state:
  1667. if (ret == -EDEADLK)
  1668. goto backoff;
  1669. drm_atomic_state_put(state);
  1670. out_ctx:
  1671. drm_modeset_drop_locks(&ctx);
  1672. drm_modeset_acquire_fini(&ctx);
  1673. if (ret)
  1674. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1675. return;
  1676. backoff:
  1677. drm_atomic_state_clear(state);
  1678. drm_modeset_backoff(&ctx);
  1679. goto retry;
  1680. }
  1681. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1682. struct drm_atomic_state *state)
  1683. {
  1684. struct sde_kms *sde_kms;
  1685. struct drm_device *dev;
  1686. struct drm_crtc *crtc;
  1687. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1688. struct drm_crtc_state *crtc_state;
  1689. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1690. bool sec_session = false, global_sec_session = false;
  1691. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1692. int i;
  1693. if (!kms || !state) {
  1694. return -EINVAL;
  1695. SDE_ERROR("invalid arguments\n");
  1696. }
  1697. sde_kms = to_sde_kms(kms);
  1698. dev = sde_kms->dev;
  1699. /* iterate state object for active secure/non-secure crtc */
  1700. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1701. if (!crtc_state->active)
  1702. continue;
  1703. active_crtc_cnt++;
  1704. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1705. &fb_sec, &fb_sec_dir);
  1706. if (fb_sec_dir)
  1707. sec_session = true;
  1708. cur_crtc = crtc;
  1709. }
  1710. /* iterate global list for active and secure/non-secure crtc */
  1711. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1712. if (!crtc->state->active)
  1713. continue;
  1714. global_active_crtc_cnt++;
  1715. /* update only when crtc is not the same as current crtc */
  1716. if (crtc != cur_crtc) {
  1717. fb_ns = fb_sec = fb_sec_dir = 0;
  1718. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1719. &fb_sec, &fb_sec_dir);
  1720. if (fb_sec_dir)
  1721. global_sec_session = true;
  1722. global_crtc = crtc;
  1723. }
  1724. }
  1725. if (!global_sec_session && !sec_session)
  1726. return 0;
  1727. /*
  1728. * - fail crtc commit, if secure-camera/secure-ui session is
  1729. * in-progress in any other display
  1730. * - fail secure-camera/secure-ui crtc commit, if any other display
  1731. * session is in-progress
  1732. */
  1733. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1734. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1735. SDE_ERROR(
  1736. "crtc%d secure check failed global_active:%d active:%d\n",
  1737. cur_crtc ? cur_crtc->base.id : -1,
  1738. global_active_crtc_cnt, active_crtc_cnt);
  1739. return -EPERM;
  1740. /*
  1741. * As only one crtc is allowed during secure session, the crtc
  1742. * in this commit should match with the global crtc
  1743. */
  1744. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1745. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1746. cur_crtc->base.id, sec_session,
  1747. global_crtc->base.id, global_sec_session);
  1748. return -EPERM;
  1749. }
  1750. return 0;
  1751. }
  1752. static int sde_kms_atomic_check(struct msm_kms *kms,
  1753. struct drm_atomic_state *state)
  1754. {
  1755. struct sde_kms *sde_kms;
  1756. struct drm_device *dev;
  1757. int ret;
  1758. if (!kms || !state)
  1759. return -EINVAL;
  1760. sde_kms = to_sde_kms(kms);
  1761. dev = sde_kms->dev;
  1762. SDE_ATRACE_BEGIN("atomic_check");
  1763. if (sde_kms_is_suspend_blocked(dev)) {
  1764. SDE_DEBUG("suspended, skip atomic_check\n");
  1765. ret = -EBUSY;
  1766. goto end;
  1767. }
  1768. ret = drm_atomic_helper_check(dev, state);
  1769. if (ret)
  1770. goto end;
  1771. /*
  1772. * Check if any secure transition(moving CRTC between secure and
  1773. * non-secure state and vice-versa) is allowed or not. when moving
  1774. * to secure state, planes with fb_mode set to dir_translated only can
  1775. * be staged on the CRTC, and only one CRTC can be active during
  1776. * Secure state
  1777. */
  1778. ret = sde_kms_check_secure_transition(kms, state);
  1779. end:
  1780. SDE_ATRACE_END("atomic_check");
  1781. return ret;
  1782. }
  1783. static struct msm_gem_address_space*
  1784. _sde_kms_get_address_space(struct msm_kms *kms,
  1785. unsigned int domain)
  1786. {
  1787. struct sde_kms *sde_kms;
  1788. if (!kms) {
  1789. SDE_ERROR("invalid kms\n");
  1790. return NULL;
  1791. }
  1792. sde_kms = to_sde_kms(kms);
  1793. if (!sde_kms) {
  1794. SDE_ERROR("invalid sde_kms\n");
  1795. return NULL;
  1796. }
  1797. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1798. return NULL;
  1799. return (sde_kms->aspace[domain] &&
  1800. sde_kms->aspace[domain]->domain_attached) ?
  1801. sde_kms->aspace[domain] : NULL;
  1802. }
  1803. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1804. unsigned int domain)
  1805. {
  1806. struct sde_kms *sde_kms;
  1807. struct device *dev;
  1808. struct msm_gem_address_space *aspace;
  1809. if (!kms) {
  1810. SDE_ERROR("invalid kms\n");
  1811. return NULL;
  1812. }
  1813. sde_kms = to_sde_kms(kms);
  1814. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1815. SDE_ERROR("invalid params\n");
  1816. return NULL;
  1817. }
  1818. /* return default device, when IOMMU is not present */
  1819. if (!iommu_present(&platform_bus_type)) {
  1820. dev = sde_kms->dev->dev;
  1821. } else {
  1822. aspace = _sde_kms_get_address_space(kms, domain);
  1823. dev = (aspace && aspace->domain_attached) ?
  1824. msm_gem_get_aspace_device(aspace) : NULL;
  1825. }
  1826. return dev;
  1827. }
  1828. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1829. {
  1830. struct drm_device *dev = NULL;
  1831. struct sde_kms *sde_kms = NULL;
  1832. struct drm_connector *connector = NULL;
  1833. struct drm_connector_list_iter conn_iter;
  1834. struct sde_connector *sde_conn = NULL;
  1835. if (!kms) {
  1836. SDE_ERROR("invalid kms\n");
  1837. return;
  1838. }
  1839. sde_kms = to_sde_kms(kms);
  1840. dev = sde_kms->dev;
  1841. if (!dev) {
  1842. SDE_ERROR("invalid device\n");
  1843. return;
  1844. }
  1845. if (!dev->mode_config.poll_enabled)
  1846. return;
  1847. mutex_lock(&dev->mode_config.mutex);
  1848. drm_connector_list_iter_begin(dev, &conn_iter);
  1849. drm_for_each_connector_iter(connector, &conn_iter) {
  1850. /* Only handle HPD capable connectors. */
  1851. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1852. continue;
  1853. sde_conn = to_sde_connector(connector);
  1854. if (sde_conn->ops.post_open)
  1855. sde_conn->ops.post_open(&sde_conn->base,
  1856. sde_conn->display);
  1857. }
  1858. drm_connector_list_iter_end(&conn_iter);
  1859. mutex_unlock(&dev->mode_config.mutex);
  1860. }
  1861. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1862. struct sde_splash_display *splash_display,
  1863. struct drm_crtc *crtc)
  1864. {
  1865. struct msm_drm_private *priv;
  1866. struct drm_plane *plane;
  1867. struct sde_splash_mem *splash;
  1868. enum sde_sspp plane_id;
  1869. bool is_virtual;
  1870. int i, j;
  1871. if (!sde_kms || !splash_display || !crtc) {
  1872. SDE_ERROR("invalid input args\n");
  1873. return -EINVAL;
  1874. }
  1875. priv = sde_kms->dev->dev_private;
  1876. for (i = 0; i < priv->num_planes; i++) {
  1877. plane = priv->planes[i];
  1878. plane_id = sde_plane_pipe(plane);
  1879. is_virtual = is_sde_plane_virtual(plane);
  1880. splash = splash_display->splash;
  1881. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1882. if ((plane_id != splash_display->pipes[j].sspp) ||
  1883. (splash_display->pipes[j].is_virtual
  1884. != is_virtual))
  1885. continue;
  1886. if (splash && sde_plane_validate_src_addr(plane,
  1887. splash->splash_buf_base,
  1888. splash->splash_buf_size)) {
  1889. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1890. plane_id, crtc->base.id);
  1891. }
  1892. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1893. crtc->base.id, plane_id, is_virtual);
  1894. }
  1895. }
  1896. return 0;
  1897. }
  1898. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1899. {
  1900. void *display;
  1901. struct dsi_display *dsi_display;
  1902. struct msm_display_info info;
  1903. struct drm_encoder *encoder = NULL;
  1904. struct drm_crtc *crtc = NULL;
  1905. int i, rc = 0;
  1906. struct drm_display_mode *drm_mode = NULL;
  1907. struct drm_device *dev;
  1908. struct msm_drm_private *priv;
  1909. struct sde_kms *sde_kms;
  1910. struct drm_connector_list_iter conn_iter;
  1911. struct drm_connector *connector = NULL;
  1912. struct sde_connector *sde_conn = NULL;
  1913. struct sde_splash_display *splash_display;
  1914. if (!kms) {
  1915. SDE_ERROR("invalid kms\n");
  1916. return -EINVAL;
  1917. }
  1918. sde_kms = to_sde_kms(kms);
  1919. dev = sde_kms->dev;
  1920. if (!dev) {
  1921. SDE_ERROR("invalid device\n");
  1922. return -EINVAL;
  1923. }
  1924. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  1925. && (!sde_kms->splash_data.num_splash_regions)) ||
  1926. !sde_kms->splash_data.num_splash_displays) {
  1927. DRM_INFO("cont_splash feature not enabled\n");
  1928. return rc;
  1929. }
  1930. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1931. sde_kms->splash_data.num_splash_displays,
  1932. sde_kms->dsi_display_count);
  1933. /* dsi */
  1934. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1935. display = sde_kms->dsi_displays[i];
  1936. dsi_display = (struct dsi_display *)display;
  1937. splash_display = &sde_kms->splash_data.splash_display[i];
  1938. if (!splash_display->cont_splash_enabled) {
  1939. SDE_DEBUG("display->name = %s splash not enabled\n",
  1940. dsi_display->name);
  1941. continue;
  1942. }
  1943. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1944. if (dsi_display->bridge->base.encoder) {
  1945. encoder = dsi_display->bridge->base.encoder;
  1946. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1947. }
  1948. memset(&info, 0x0, sizeof(info));
  1949. rc = dsi_display_get_info(NULL, &info, display);
  1950. if (rc) {
  1951. SDE_ERROR("dsi get_info %d failed\n", i);
  1952. encoder = NULL;
  1953. continue;
  1954. }
  1955. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  1956. ((info.is_connected) ? "true" : "false"),
  1957. info.display_type);
  1958. if (!encoder) {
  1959. SDE_ERROR("encoder not initialized\n");
  1960. return -EINVAL;
  1961. }
  1962. priv = sde_kms->dev->dev_private;
  1963. encoder->crtc = priv->crtcs[i];
  1964. crtc = encoder->crtc;
  1965. splash_display->encoder = encoder;
  1966. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1967. i, crtc->base.id, encoder->base.id);
  1968. mutex_lock(&dev->mode_config.mutex);
  1969. drm_connector_list_iter_begin(dev, &conn_iter);
  1970. drm_for_each_connector_iter(connector, &conn_iter) {
  1971. /**
  1972. * SDE_KMS doesn't attach more than one encoder to
  1973. * a DSI connector. So it is safe to check only with
  1974. * the first encoder entry. Revisit this logic if we
  1975. * ever have to support continuous splash for
  1976. * external displays in MST configuration.
  1977. */
  1978. if (connector->encoder_ids[0] == encoder->base.id)
  1979. break;
  1980. }
  1981. drm_connector_list_iter_end(&conn_iter);
  1982. if (!connector) {
  1983. SDE_ERROR("connector not initialized\n");
  1984. mutex_unlock(&dev->mode_config.mutex);
  1985. return -EINVAL;
  1986. }
  1987. if (connector->funcs->fill_modes) {
  1988. connector->funcs->fill_modes(connector,
  1989. dev->mode_config.max_width,
  1990. dev->mode_config.max_height);
  1991. } else {
  1992. SDE_ERROR("fill_modes api not defined\n");
  1993. mutex_unlock(&dev->mode_config.mutex);
  1994. return -EINVAL;
  1995. }
  1996. mutex_unlock(&dev->mode_config.mutex);
  1997. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  1998. /* currently consider modes[0] as the preferred mode */
  1999. drm_mode = list_first_entry(&connector->modes,
  2000. struct drm_display_mode, head);
  2001. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2002. drm_mode->name, drm_mode->type,
  2003. drm_mode->flags);
  2004. /* Update CRTC drm structure */
  2005. crtc->state->active = true;
  2006. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2007. if (rc) {
  2008. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2009. return rc;
  2010. }
  2011. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2012. drm_mode_copy(&crtc->mode, drm_mode);
  2013. /* Update encoder structure */
  2014. sde_encoder_update_caps_for_cont_splash(encoder,
  2015. splash_display, true);
  2016. sde_crtc_update_cont_splash_settings(crtc);
  2017. sde_conn = to_sde_connector(connector);
  2018. if (sde_conn && sde_conn->ops.cont_splash_config)
  2019. sde_conn->ops.cont_splash_config(sde_conn->display);
  2020. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2021. splash_display, crtc);
  2022. if (rc) {
  2023. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2024. return rc;
  2025. }
  2026. }
  2027. return rc;
  2028. }
  2029. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2030. {
  2031. struct sde_kms *sde_kms;
  2032. if (!kms) {
  2033. SDE_ERROR("invalid kms\n");
  2034. return false;
  2035. }
  2036. sde_kms = to_sde_kms(kms);
  2037. return sde_kms->splash_data.num_splash_displays;
  2038. }
  2039. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2040. const struct drm_display_mode *mode,
  2041. const struct msm_resource_caps_info *res, u32 *num_lm)
  2042. {
  2043. struct sde_kms *sde_kms;
  2044. s64 mode_clock_hz = 0;
  2045. s64 max_mdp_clock_hz = 0;
  2046. s64 max_lm_width = 0;
  2047. s64 hdisplay_fp = 0;
  2048. s64 htotal_fp = 0;
  2049. s64 vtotal_fp = 0;
  2050. s64 vrefresh_fp = 0;
  2051. s64 mdp_fudge_factor = 0;
  2052. s64 num_lm_fp = 0;
  2053. s64 lm_clk_fp = 0;
  2054. s64 lm_width_fp = 0;
  2055. int rc = 0;
  2056. if (!num_lm) {
  2057. SDE_ERROR("invalid num_lm pointer\n");
  2058. return -EINVAL;
  2059. }
  2060. /* default to 1 layer mixer */
  2061. *num_lm = 1;
  2062. if (!kms || !mode || !res) {
  2063. SDE_ERROR("invalid input args\n");
  2064. return -EINVAL;
  2065. }
  2066. sde_kms = to_sde_kms(kms);
  2067. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2068. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2069. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2070. htotal_fp = drm_int2fixp(mode->htotal);
  2071. vtotal_fp = drm_int2fixp(mode->vtotal);
  2072. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2073. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2074. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2075. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2076. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2077. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2078. if (mode_clock_hz > max_mdp_clock_hz ||
  2079. hdisplay_fp > max_lm_width) {
  2080. *num_lm = 0;
  2081. do {
  2082. *num_lm += 2;
  2083. num_lm_fp = drm_int2fixp(*num_lm);
  2084. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2085. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2086. if (*num_lm > 4) {
  2087. rc = -EINVAL;
  2088. goto error;
  2089. }
  2090. } while (lm_clk_fp > max_mdp_clock_hz ||
  2091. lm_width_fp > max_lm_width);
  2092. mode_clock_hz = lm_clk_fp;
  2093. }
  2094. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2095. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2096. *num_lm, drm_fixp2int(mode_clock_hz),
  2097. sde_kms->perf.max_core_clk_rate);
  2098. return 0;
  2099. error:
  2100. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2101. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2102. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2103. *num_lm, drm_fixp2int(mode_clock_hz),
  2104. sde_kms->perf.max_core_clk_rate);
  2105. return rc;
  2106. }
  2107. static void _sde_kms_null_commit(struct drm_device *dev,
  2108. struct drm_encoder *enc)
  2109. {
  2110. struct drm_modeset_acquire_ctx ctx;
  2111. struct drm_connector *conn = NULL;
  2112. struct drm_connector *tmp_conn = NULL;
  2113. struct drm_connector_list_iter conn_iter;
  2114. struct drm_atomic_state *state = NULL;
  2115. struct drm_crtc_state *crtc_state = NULL;
  2116. struct drm_connector_state *conn_state = NULL;
  2117. int retry_cnt = 0;
  2118. int ret = 0;
  2119. drm_modeset_acquire_init(&ctx, 0);
  2120. retry:
  2121. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2122. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2123. drm_modeset_backoff(&ctx);
  2124. retry_cnt++;
  2125. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2126. goto retry;
  2127. } else if (WARN_ON(ret)) {
  2128. goto end;
  2129. }
  2130. state = drm_atomic_state_alloc(dev);
  2131. if (!state) {
  2132. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2133. goto end;
  2134. }
  2135. state->acquire_ctx = &ctx;
  2136. drm_connector_list_iter_begin(dev, &conn_iter);
  2137. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2138. if (enc == tmp_conn->state->best_encoder) {
  2139. conn = tmp_conn;
  2140. break;
  2141. }
  2142. }
  2143. drm_connector_list_iter_end(&conn_iter);
  2144. if (!conn) {
  2145. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2146. goto end;
  2147. }
  2148. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2149. conn_state = drm_atomic_get_connector_state(state, conn);
  2150. if (IS_ERR(conn_state)) {
  2151. SDE_ERROR("error %d getting connector %d state\n",
  2152. ret, DRMID(conn));
  2153. goto end;
  2154. }
  2155. crtc_state->active = true;
  2156. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2157. if (ret)
  2158. SDE_ERROR("error %d setting the crtc\n", ret);
  2159. ret = drm_atomic_commit(state);
  2160. if (ret)
  2161. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2162. end:
  2163. if (state)
  2164. drm_atomic_state_put(state);
  2165. drm_modeset_drop_locks(&ctx);
  2166. drm_modeset_acquire_fini(&ctx);
  2167. }
  2168. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2169. struct device *dev)
  2170. {
  2171. int i, ret, crtc_id = 0;
  2172. struct drm_device *ddev = dev_get_drvdata(dev);
  2173. struct drm_connector *conn;
  2174. struct drm_connector_list_iter conn_iter;
  2175. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2176. drm_connector_list_iter_begin(ddev, &conn_iter);
  2177. drm_for_each_connector_iter(conn, &conn_iter) {
  2178. uint64_t lp;
  2179. lp = sde_connector_get_lp(conn);
  2180. if (lp != SDE_MODE_DPMS_LP2)
  2181. continue;
  2182. if (sde_encoder_in_clone_mode(conn->encoder))
  2183. continue;
  2184. ret = sde_encoder_wait_for_event(conn->encoder,
  2185. MSM_ENC_TX_COMPLETE);
  2186. if (ret && ret != -EWOULDBLOCK) {
  2187. SDE_ERROR(
  2188. "[conn: %d] wait for commit done returned %d\n",
  2189. conn->base.id, ret);
  2190. } else if (!ret) {
  2191. crtc_id = drm_crtc_index(conn->state->crtc);
  2192. if (priv->event_thread[crtc_id].thread)
  2193. kthread_flush_worker(
  2194. &priv->event_thread[crtc_id].worker);
  2195. sde_encoder_idle_request(conn->encoder);
  2196. }
  2197. }
  2198. drm_connector_list_iter_end(&conn_iter);
  2199. for (i = 0; i < priv->num_crtcs; i++) {
  2200. if (priv->disp_thread[i].thread)
  2201. kthread_flush_worker(
  2202. &priv->disp_thread[i].worker);
  2203. if (priv->event_thread[i].thread)
  2204. kthread_flush_worker(
  2205. &priv->event_thread[i].worker);
  2206. }
  2207. kthread_flush_worker(&priv->pp_event_worker);
  2208. }
  2209. static int sde_kms_pm_suspend(struct device *dev)
  2210. {
  2211. struct drm_device *ddev;
  2212. struct drm_modeset_acquire_ctx ctx;
  2213. struct drm_connector *conn;
  2214. struct drm_encoder *enc;
  2215. struct drm_connector_list_iter conn_iter;
  2216. struct drm_atomic_state *state = NULL;
  2217. struct sde_kms *sde_kms;
  2218. int ret = 0, num_crtcs = 0;
  2219. if (!dev)
  2220. return -EINVAL;
  2221. ddev = dev_get_drvdata(dev);
  2222. if (!ddev || !ddev_to_msm_kms(ddev))
  2223. return -EINVAL;
  2224. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2225. SDE_EVT32(0);
  2226. /* disable hot-plug polling */
  2227. drm_kms_helper_poll_disable(ddev);
  2228. /* if a display stuck in CS trigger a null commit to complete handoff */
  2229. drm_for_each_encoder(enc, ddev) {
  2230. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2231. _sde_kms_null_commit(ddev, enc);
  2232. }
  2233. /* acquire modeset lock(s) */
  2234. drm_modeset_acquire_init(&ctx, 0);
  2235. retry:
  2236. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2237. if (ret)
  2238. goto unlock;
  2239. /* save current state for resume */
  2240. if (sde_kms->suspend_state)
  2241. drm_atomic_state_put(sde_kms->suspend_state);
  2242. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2243. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2244. ret = PTR_ERR(sde_kms->suspend_state);
  2245. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2246. sde_kms->suspend_state = NULL;
  2247. goto unlock;
  2248. }
  2249. /* create atomic state to disable all CRTCs */
  2250. state = drm_atomic_state_alloc(ddev);
  2251. if (!state) {
  2252. ret = -ENOMEM;
  2253. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2254. goto unlock;
  2255. }
  2256. state->acquire_ctx = &ctx;
  2257. drm_connector_list_iter_begin(ddev, &conn_iter);
  2258. drm_for_each_connector_iter(conn, &conn_iter) {
  2259. struct drm_crtc_state *crtc_state;
  2260. uint64_t lp;
  2261. if (!conn->state || !conn->state->crtc ||
  2262. conn->dpms != DRM_MODE_DPMS_ON ||
  2263. sde_encoder_in_clone_mode(conn->encoder))
  2264. continue;
  2265. lp = sde_connector_get_lp(conn);
  2266. if (lp == SDE_MODE_DPMS_LP1) {
  2267. /* transition LP1->LP2 on pm suspend */
  2268. ret = sde_connector_set_property_for_commit(conn, state,
  2269. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2270. if (ret) {
  2271. DRM_ERROR("failed to set lp2 for conn %d\n",
  2272. conn->base.id);
  2273. drm_connector_list_iter_end(&conn_iter);
  2274. goto unlock;
  2275. }
  2276. }
  2277. if (lp != SDE_MODE_DPMS_LP2) {
  2278. /* force CRTC to be inactive */
  2279. crtc_state = drm_atomic_get_crtc_state(state,
  2280. conn->state->crtc);
  2281. if (IS_ERR_OR_NULL(crtc_state)) {
  2282. DRM_ERROR("failed to get crtc %d state\n",
  2283. conn->state->crtc->base.id);
  2284. drm_connector_list_iter_end(&conn_iter);
  2285. goto unlock;
  2286. }
  2287. if (lp != SDE_MODE_DPMS_LP1)
  2288. crtc_state->active = false;
  2289. ++num_crtcs;
  2290. }
  2291. }
  2292. drm_connector_list_iter_end(&conn_iter);
  2293. /* check for nothing to do */
  2294. if (num_crtcs == 0) {
  2295. DRM_DEBUG("all crtcs are already in the off state\n");
  2296. sde_kms->suspend_block = true;
  2297. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2298. goto unlock;
  2299. }
  2300. /* commit the "disable all" state */
  2301. ret = drm_atomic_commit(state);
  2302. if (ret < 0) {
  2303. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2304. goto unlock;
  2305. }
  2306. sde_kms->suspend_block = true;
  2307. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2308. unlock:
  2309. if (state) {
  2310. drm_atomic_state_put(state);
  2311. state = NULL;
  2312. }
  2313. if (ret == -EDEADLK) {
  2314. drm_modeset_backoff(&ctx);
  2315. goto retry;
  2316. }
  2317. drm_modeset_drop_locks(&ctx);
  2318. drm_modeset_acquire_fini(&ctx);
  2319. /*
  2320. * pm runtime driver avoids multiple runtime_suspend API call by
  2321. * checking runtime_status. However, this call helps when there is a
  2322. * race condition between pm_suspend call and doze_suspend/power_off
  2323. * commit. It removes the extra vote from suspend and adds it back
  2324. * later to allow power collapse during pm_suspend call
  2325. */
  2326. pm_runtime_put_sync(dev);
  2327. pm_runtime_get_noresume(dev);
  2328. return ret;
  2329. }
  2330. static int sde_kms_pm_resume(struct device *dev)
  2331. {
  2332. struct drm_device *ddev;
  2333. struct sde_kms *sde_kms;
  2334. struct drm_modeset_acquire_ctx ctx;
  2335. int ret, i;
  2336. if (!dev)
  2337. return -EINVAL;
  2338. ddev = dev_get_drvdata(dev);
  2339. if (!ddev || !ddev_to_msm_kms(ddev))
  2340. return -EINVAL;
  2341. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2342. SDE_EVT32(sde_kms->suspend_state != NULL);
  2343. drm_mode_config_reset(ddev);
  2344. drm_modeset_acquire_init(&ctx, 0);
  2345. retry:
  2346. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2347. if (ret == -EDEADLK) {
  2348. drm_modeset_backoff(&ctx);
  2349. goto retry;
  2350. } else if (WARN_ON(ret)) {
  2351. goto end;
  2352. }
  2353. sde_kms->suspend_block = false;
  2354. if (sde_kms->suspend_state) {
  2355. sde_kms->suspend_state->acquire_ctx = &ctx;
  2356. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2357. ret = drm_atomic_helper_commit_duplicated_state(
  2358. sde_kms->suspend_state, &ctx);
  2359. if (ret != -EDEADLK)
  2360. break;
  2361. drm_modeset_backoff(&ctx);
  2362. }
  2363. if (ret < 0)
  2364. DRM_ERROR("failed to restore state, %d\n", ret);
  2365. drm_atomic_state_put(sde_kms->suspend_state);
  2366. sde_kms->suspend_state = NULL;
  2367. }
  2368. end:
  2369. drm_modeset_drop_locks(&ctx);
  2370. drm_modeset_acquire_fini(&ctx);
  2371. /* enable hot-plug polling */
  2372. drm_kms_helper_poll_enable(ddev);
  2373. return 0;
  2374. }
  2375. static const struct msm_kms_funcs kms_funcs = {
  2376. .hw_init = sde_kms_hw_init,
  2377. .postinit = sde_kms_postinit,
  2378. .irq_preinstall = sde_irq_preinstall,
  2379. .irq_postinstall = sde_irq_postinstall,
  2380. .irq_uninstall = sde_irq_uninstall,
  2381. .irq = sde_irq,
  2382. .lastclose = sde_kms_lastclose,
  2383. .prepare_fence = sde_kms_prepare_fence,
  2384. .prepare_commit = sde_kms_prepare_commit,
  2385. .commit = sde_kms_commit,
  2386. .complete_commit = sde_kms_complete_commit,
  2387. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2388. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2389. .enable_vblank = sde_kms_enable_vblank,
  2390. .disable_vblank = sde_kms_disable_vblank,
  2391. .check_modified_format = sde_format_check_modified_format,
  2392. .atomic_check = sde_kms_atomic_check,
  2393. .get_format = sde_get_msm_format,
  2394. .round_pixclk = sde_kms_round_pixclk,
  2395. .pm_suspend = sde_kms_pm_suspend,
  2396. .pm_resume = sde_kms_pm_resume,
  2397. .destroy = sde_kms_destroy,
  2398. .cont_splash_config = sde_kms_cont_splash_config,
  2399. .register_events = _sde_kms_register_events,
  2400. .get_address_space = _sde_kms_get_address_space,
  2401. .get_address_space_device = _sde_kms_get_address_space_device,
  2402. .postopen = _sde_kms_post_open,
  2403. .check_for_splash = sde_kms_check_for_splash,
  2404. .get_mixer_count = sde_kms_get_mixer_count,
  2405. };
  2406. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2407. {
  2408. int i;
  2409. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2410. if (!sde_kms->aspace[i])
  2411. continue;
  2412. msm_gem_address_space_put(sde_kms->aspace[i]);
  2413. sde_kms->aspace[i] = NULL;
  2414. }
  2415. return 0;
  2416. }
  2417. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2418. {
  2419. struct msm_mmu *mmu;
  2420. int i, ret;
  2421. int early_map = 0;
  2422. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2423. return -EINVAL;
  2424. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2425. struct msm_gem_address_space *aspace;
  2426. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2427. if (IS_ERR(mmu)) {
  2428. ret = PTR_ERR(mmu);
  2429. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2430. i, ret);
  2431. continue;
  2432. }
  2433. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2434. mmu, "sde");
  2435. if (IS_ERR(aspace)) {
  2436. ret = PTR_ERR(aspace);
  2437. goto fail;
  2438. }
  2439. sde_kms->aspace[i] = aspace;
  2440. aspace->domain_attached = true;
  2441. /* Mapping splash memory block */
  2442. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2443. sde_kms->splash_data.num_splash_regions) {
  2444. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2445. if (ret) {
  2446. SDE_ERROR("failed to map ret:%d\n", ret);
  2447. goto fail;
  2448. }
  2449. }
  2450. /*
  2451. * disable early-map which would have been enabled during
  2452. * bootup by smmu through the device-tree hint for cont-spash
  2453. */
  2454. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2455. &early_map);
  2456. if (ret) {
  2457. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2458. ret, early_map);
  2459. goto early_map_fail;
  2460. }
  2461. }
  2462. sde_kms->base.aspace = sde_kms->aspace[0];
  2463. return 0;
  2464. early_map_fail:
  2465. _sde_kms_unmap_all_splash_regions(sde_kms);
  2466. fail:
  2467. mmu->funcs->destroy(mmu);
  2468. _sde_kms_mmu_destroy(sde_kms);
  2469. return ret;
  2470. }
  2471. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2472. {
  2473. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2474. return;
  2475. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2476. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2477. sde_kms->catalog);
  2478. if (sde_kms->sid)
  2479. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  2480. }
  2481. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2482. {
  2483. struct sde_vbif_set_qos_params qos_params;
  2484. struct sde_mdss_cfg *catalog;
  2485. if (!sde_kms->catalog)
  2486. return;
  2487. catalog = sde_kms->catalog;
  2488. memset(&qos_params, 0, sizeof(qos_params));
  2489. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2490. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2491. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2492. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2493. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2494. }
  2495. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2496. {
  2497. struct sde_hw_uidle *uidle;
  2498. if (!sde_kms) {
  2499. SDE_ERROR("invalid kms\n");
  2500. return -EINVAL;
  2501. }
  2502. uidle = sde_kms->hw_uidle;
  2503. if (uidle && uidle->ops.active_override_enable)
  2504. uidle->ops.active_override_enable(uidle, enable);
  2505. return 0;
  2506. }
  2507. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2508. {
  2509. struct device *cpu_dev;
  2510. int cpu = 0;
  2511. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  2512. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2513. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2514. return;
  2515. }
  2516. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2517. cpu_dev = get_cpu_device(cpu);
  2518. if (!cpu_dev) {
  2519. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2520. cpu);
  2521. continue;
  2522. }
  2523. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2524. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2525. cpu_irq_latency);
  2526. else
  2527. dev_pm_qos_add_request(cpu_dev,
  2528. &sde_kms->pm_qos_irq_req[cpu],
  2529. DEV_PM_QOS_RESUME_LATENCY,
  2530. cpu_irq_latency);
  2531. }
  2532. }
  2533. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2534. {
  2535. struct device *cpu_dev;
  2536. int cpu = 0;
  2537. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2538. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2539. return;
  2540. }
  2541. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2542. cpu_dev = get_cpu_device(cpu);
  2543. if (!cpu_dev) {
  2544. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2545. cpu);
  2546. continue;
  2547. }
  2548. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2549. dev_pm_qos_remove_request(
  2550. &sde_kms->pm_qos_irq_req[cpu]);
  2551. }
  2552. }
  2553. void sde_kms_irq_enable_notify(struct sde_kms *sde_kms, bool enable)
  2554. {
  2555. if (enable)
  2556. _sde_kms_update_pm_qos_irq_request(sde_kms);
  2557. else
  2558. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  2559. }
  2560. static void sde_kms_irq_affinity_notify(
  2561. struct irq_affinity_notify *affinity_notify,
  2562. const cpumask_t *mask)
  2563. {
  2564. struct msm_drm_private *priv;
  2565. struct sde_kms *sde_kms = container_of(affinity_notify,
  2566. struct sde_kms, affinity_notify);
  2567. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2568. return;
  2569. priv = sde_kms->dev->dev_private;
  2570. mutex_lock(&priv->phandle.phandle_lock);
  2571. // save irq cpu mask
  2572. sde_kms->irq_cpu_mask = *mask;
  2573. // request vote with updated irq cpu mask
  2574. if (sde_kms->irq_enabled)
  2575. _sde_kms_update_pm_qos_irq_request(sde_kms);
  2576. mutex_unlock(&priv->phandle.phandle_lock);
  2577. }
  2578. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  2579. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2580. {
  2581. struct sde_kms *sde_kms = usr;
  2582. struct msm_kms *msm_kms;
  2583. msm_kms = &sde_kms->base;
  2584. if (!sde_kms)
  2585. return;
  2586. SDE_DEBUG("event_type:%d\n", event_type);
  2587. SDE_EVT32_VERBOSE(event_type);
  2588. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2589. sde_irq_update(msm_kms, true);
  2590. if (sde_kms->splash_data.num_splash_displays)
  2591. return;
  2592. sde_vbif_init_memtypes(sde_kms);
  2593. sde_kms_init_shared_hw(sde_kms);
  2594. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2595. sde_kms->first_kickoff = true;
  2596. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2597. sde_irq_update(msm_kms, false);
  2598. sde_kms->first_kickoff = false;
  2599. _sde_kms_active_override(sde_kms, true);
  2600. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  2601. sde_vbif_axi_halt_request(sde_kms);
  2602. }
  2603. }
  2604. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2605. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2606. {
  2607. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2608. int rc = -EINVAL;
  2609. SDE_DEBUG("\n");
  2610. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2611. if (rc > 0)
  2612. rc = 0;
  2613. SDE_EVT32(rc, genpd->device_count);
  2614. return rc;
  2615. }
  2616. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2617. {
  2618. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2619. SDE_DEBUG("\n");
  2620. pm_runtime_put_sync(sde_kms->dev->dev);
  2621. SDE_EVT32(genpd->device_count);
  2622. return 0;
  2623. }
  2624. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  2625. struct sde_splash_data *data)
  2626. {
  2627. int i = 0;
  2628. int ret = 0;
  2629. struct device_node *parent, *node, *node1;
  2630. struct resource r, r1;
  2631. const char *node_name = "splash_region";
  2632. struct sde_splash_mem *mem;
  2633. bool share_splash_mem = false;
  2634. int num_displays, num_regions;
  2635. struct sde_splash_display *splash_display;
  2636. if (!data)
  2637. return -EINVAL;
  2638. memset(data, 0, sizeof(*data));
  2639. parent = of_find_node_by_path("/reserved-memory");
  2640. if (!parent) {
  2641. SDE_ERROR("failed to find reserved-memory node\n");
  2642. return -EINVAL;
  2643. }
  2644. node = of_find_node_by_name(parent, node_name);
  2645. if (!node) {
  2646. SDE_DEBUG("failed to find node %s\n", node_name);
  2647. return -EINVAL;
  2648. }
  2649. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  2650. if (!node1)
  2651. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2652. /**
  2653. * Support sharing a single splash memory for all the built in displays
  2654. * and also independent splash region per displays. Incase of
  2655. * independent splash region for each connected display, dtsi node of
  2656. * cont_splash_region should be collection of all memory regions
  2657. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2658. */
  2659. num_displays = dsi_display_get_num_of_displays();
  2660. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2661. data->num_splash_displays = num_displays;
  2662. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2663. if (num_displays > num_regions) {
  2664. share_splash_mem = true;
  2665. pr_info(":%d displays share same splash buf\n", num_displays);
  2666. }
  2667. for (i = 0; i < num_displays; i++) {
  2668. splash_display = &data->splash_display[i];
  2669. if (!i || !share_splash_mem) {
  2670. if (of_address_to_resource(node, i, &r)) {
  2671. SDE_ERROR("invalid data for:%s\n", node_name);
  2672. return -EINVAL;
  2673. }
  2674. mem = &data->splash_mem[i];
  2675. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2676. SDE_DEBUG("failed to find ramdump memory\n");
  2677. mem->ramdump_base = 0;
  2678. mem->ramdump_size = 0;
  2679. } else {
  2680. mem->ramdump_base = (unsigned long)r1.start;
  2681. mem->ramdump_size = (r1.end - r1.start) + 1;
  2682. }
  2683. mem->splash_buf_base = (unsigned long)r.start;
  2684. mem->splash_buf_size = (r.end - r.start) + 1;
  2685. mem->ref_cnt = 0;
  2686. splash_display->splash = mem;
  2687. data->num_splash_regions++;
  2688. } else {
  2689. data->splash_display[i].splash = &data->splash_mem[0];
  2690. }
  2691. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2692. splash_display->splash->splash_buf_base,
  2693. splash_display->splash->splash_buf_size);
  2694. }
  2695. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  2696. return ret;
  2697. }
  2698. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2699. struct platform_device *platformdev)
  2700. {
  2701. int rc = -EINVAL;
  2702. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2703. if (IS_ERR(sde_kms->mmio)) {
  2704. rc = PTR_ERR(sde_kms->mmio);
  2705. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2706. sde_kms->mmio = NULL;
  2707. goto error;
  2708. }
  2709. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2710. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2711. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2712. sde_kms->mmio_len);
  2713. if (rc)
  2714. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2715. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2716. "vbif_phys");
  2717. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2718. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2719. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2720. sde_kms->vbif[VBIF_RT] = NULL;
  2721. goto error;
  2722. }
  2723. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2724. "vbif_phys");
  2725. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2726. sde_kms->vbif_len[VBIF_RT]);
  2727. if (rc)
  2728. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2729. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2730. "vbif_nrt_phys");
  2731. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2732. sde_kms->vbif[VBIF_NRT] = NULL;
  2733. SDE_DEBUG("VBIF NRT is not defined");
  2734. } else {
  2735. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2736. "vbif_nrt_phys");
  2737. rc = sde_dbg_reg_register_base("vbif_nrt",
  2738. sde_kms->vbif[VBIF_NRT],
  2739. sde_kms->vbif_len[VBIF_NRT]);
  2740. if (rc)
  2741. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2742. rc);
  2743. }
  2744. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2745. "regdma_phys");
  2746. if (IS_ERR(sde_kms->reg_dma)) {
  2747. sde_kms->reg_dma = NULL;
  2748. SDE_DEBUG("REG_DMA is not defined");
  2749. } else {
  2750. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2751. "regdma_phys");
  2752. rc = sde_dbg_reg_register_base("reg_dma",
  2753. sde_kms->reg_dma,
  2754. sde_kms->reg_dma_len);
  2755. if (rc)
  2756. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2757. rc);
  2758. }
  2759. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2760. "sid_phys");
  2761. if (IS_ERR(sde_kms->sid)) {
  2762. SDE_DEBUG("sid register is not defined: %d\n", rc);
  2763. sde_kms->sid = NULL;
  2764. } else {
  2765. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2766. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  2767. sde_kms->sid_len);
  2768. if (rc)
  2769. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2770. }
  2771. error:
  2772. return rc;
  2773. }
  2774. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2775. struct sde_kms *sde_kms)
  2776. {
  2777. int rc = 0;
  2778. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2779. sde_kms->genpd.name = dev->unique;
  2780. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2781. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2782. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2783. if (rc < 0) {
  2784. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2785. sde_kms->genpd.name, rc);
  2786. return rc;
  2787. }
  2788. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2789. &sde_kms->genpd);
  2790. if (rc < 0) {
  2791. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2792. sde_kms->genpd.name, rc);
  2793. pm_genpd_remove(&sde_kms->genpd);
  2794. return rc;
  2795. }
  2796. sde_kms->genpd_init = true;
  2797. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2798. }
  2799. return rc;
  2800. }
  2801. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2802. struct drm_device *dev,
  2803. struct msm_drm_private *priv)
  2804. {
  2805. struct sde_rm *rm = NULL;
  2806. int i, rc = -EINVAL;
  2807. sde_kms->catalog = sde_hw_catalog_init(dev);
  2808. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2809. rc = PTR_ERR(sde_kms->catalog);
  2810. if (!sde_kms->catalog)
  2811. rc = -EINVAL;
  2812. SDE_ERROR("catalog init failed: %d\n", rc);
  2813. sde_kms->catalog = NULL;
  2814. goto power_error;
  2815. }
  2816. sde_kms->core_rev = sde_kms->catalog->hwversion;
  2817. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2818. /* initialize power domain if defined */
  2819. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2820. if (rc) {
  2821. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2822. goto genpd_err;
  2823. }
  2824. rc = _sde_kms_mmu_init(sde_kms);
  2825. if (rc) {
  2826. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2827. goto power_error;
  2828. }
  2829. /* Initialize reg dma block which is a singleton */
  2830. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2831. sde_kms->dev);
  2832. if (rc) {
  2833. SDE_ERROR("failed: reg dma init failed\n");
  2834. goto power_error;
  2835. }
  2836. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2837. rm = &sde_kms->rm;
  2838. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2839. sde_kms->dev);
  2840. if (rc) {
  2841. SDE_ERROR("rm init failed: %d\n", rc);
  2842. goto power_error;
  2843. }
  2844. sde_kms->rm_init = true;
  2845. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2846. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2847. rc = PTR_ERR(sde_kms->hw_intr);
  2848. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2849. sde_kms->hw_intr = NULL;
  2850. goto hw_intr_init_err;
  2851. }
  2852. /*
  2853. * Attempt continuous splash handoff only if reserved
  2854. * splash memory is found & release resources on any error
  2855. * in finding display hw config in splash
  2856. */
  2857. if (sde_kms->splash_data.num_splash_regions) {
  2858. struct sde_splash_display *display;
  2859. int ret, display_count =
  2860. sde_kms->splash_data.num_splash_displays;
  2861. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2862. &sde_kms->splash_data, sde_kms->catalog);
  2863. for (i = 0; i < display_count; i++) {
  2864. display = &sde_kms->splash_data.splash_display[i];
  2865. /*
  2866. * free splash region on resource init failure and
  2867. * cont-splash disabled case
  2868. */
  2869. if (!display->cont_splash_enabled || ret)
  2870. _sde_kms_free_splash_display_data(
  2871. sde_kms, display);
  2872. }
  2873. }
  2874. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2875. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2876. rc = PTR_ERR(sde_kms->hw_mdp);
  2877. if (!sde_kms->hw_mdp)
  2878. rc = -EINVAL;
  2879. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2880. sde_kms->hw_mdp = NULL;
  2881. goto power_error;
  2882. }
  2883. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2884. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2885. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2886. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2887. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2888. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2889. if (!sde_kms->hw_vbif[vbif_idx])
  2890. rc = -EINVAL;
  2891. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2892. sde_kms->hw_vbif[vbif_idx] = NULL;
  2893. goto power_error;
  2894. }
  2895. }
  2896. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2897. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2898. sde_kms->mmio_len, sde_kms->catalog);
  2899. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2900. rc = PTR_ERR(sde_kms->hw_uidle);
  2901. if (!sde_kms->hw_uidle)
  2902. rc = -EINVAL;
  2903. /* uidle is optional, so do not make it a fatal error */
  2904. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2905. sde_kms->hw_uidle = NULL;
  2906. rc = 0;
  2907. }
  2908. } else {
  2909. sde_kms->hw_uidle = NULL;
  2910. }
  2911. if (sde_kms->sid) {
  2912. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2913. sde_kms->sid_len, sde_kms->catalog);
  2914. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  2915. rc = PTR_ERR(sde_kms->hw_sid);
  2916. SDE_ERROR("failed to init sid %ld\n", rc);
  2917. sde_kms->hw_sid = NULL;
  2918. goto power_error;
  2919. }
  2920. }
  2921. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2922. &priv->phandle, "core_clk");
  2923. if (rc) {
  2924. SDE_ERROR("failed to init perf %d\n", rc);
  2925. goto perf_err;
  2926. }
  2927. /*
  2928. * _sde_kms_drm_obj_init should create the DRM related objects
  2929. * i.e. CRTCs, planes, encoders, connectors and so forth
  2930. */
  2931. rc = _sde_kms_drm_obj_init(sde_kms);
  2932. if (rc) {
  2933. SDE_ERROR("modeset init failed: %d\n", rc);
  2934. goto drm_obj_init_err;
  2935. }
  2936. return 0;
  2937. genpd_err:
  2938. drm_obj_init_err:
  2939. sde_core_perf_destroy(&sde_kms->perf);
  2940. hw_intr_init_err:
  2941. perf_err:
  2942. power_error:
  2943. return rc;
  2944. }
  2945. static int sde_kms_hw_init(struct msm_kms *kms)
  2946. {
  2947. struct sde_kms *sde_kms;
  2948. struct drm_device *dev;
  2949. struct msm_drm_private *priv;
  2950. struct platform_device *platformdev;
  2951. int i, irq_num, rc = -EINVAL;
  2952. if (!kms) {
  2953. SDE_ERROR("invalid kms\n");
  2954. goto end;
  2955. }
  2956. sde_kms = to_sde_kms(kms);
  2957. dev = sde_kms->dev;
  2958. if (!dev || !dev->dev) {
  2959. SDE_ERROR("invalid device\n");
  2960. goto end;
  2961. }
  2962. platformdev = to_platform_device(dev->dev);
  2963. priv = dev->dev_private;
  2964. if (!priv) {
  2965. SDE_ERROR("invalid private data\n");
  2966. goto end;
  2967. }
  2968. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2969. if (rc)
  2970. goto error;
  2971. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  2972. if (rc)
  2973. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2974. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2975. if (rc)
  2976. goto error;
  2977. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2978. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2979. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2980. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2981. mutex_init(&sde_kms->secure_transition_lock);
  2982. mutex_init(&sde_kms->vblank_ctl_global_lock);
  2983. atomic_set(&sde_kms->detach_sec_cb, 0);
  2984. atomic_set(&sde_kms->detach_all_cb, 0);
  2985. /*
  2986. * Support format modifiers for compression etc.
  2987. */
  2988. dev->mode_config.allow_fb_modifiers = true;
  2989. /*
  2990. * Handle (re)initializations during power enable
  2991. */
  2992. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2993. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2994. SDE_POWER_EVENT_POST_ENABLE |
  2995. SDE_POWER_EVENT_PRE_DISABLE,
  2996. sde_kms_handle_power_event, sde_kms, "kms");
  2997. if (sde_kms->splash_data.num_splash_displays) {
  2998. SDE_DEBUG("Skipping MDP Resources disable\n");
  2999. } else {
  3000. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3001. sde_power_data_bus_set_quota(&priv->phandle, i,
  3002. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3003. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3004. pm_runtime_put_sync(sde_kms->dev->dev);
  3005. }
  3006. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3007. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3008. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3009. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3010. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3011. return 0;
  3012. error:
  3013. _sde_kms_hw_destroy(sde_kms, platformdev);
  3014. end:
  3015. return rc;
  3016. }
  3017. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3018. {
  3019. struct msm_drm_private *priv;
  3020. struct sde_kms *sde_kms;
  3021. if (!dev || !dev->dev_private) {
  3022. SDE_ERROR("drm device node invalid\n");
  3023. return ERR_PTR(-EINVAL);
  3024. }
  3025. priv = dev->dev_private;
  3026. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3027. if (!sde_kms) {
  3028. SDE_ERROR("failed to allocate sde kms\n");
  3029. return ERR_PTR(-ENOMEM);
  3030. }
  3031. msm_kms_init(&sde_kms->base, &kms_funcs);
  3032. sde_kms->dev = dev;
  3033. return &sde_kms->base;
  3034. }
  3035. static int _sde_kms_register_events(struct msm_kms *kms,
  3036. struct drm_mode_object *obj, u32 event, bool en)
  3037. {
  3038. int ret = 0;
  3039. struct drm_crtc *crtc = NULL;
  3040. struct drm_connector *conn = NULL;
  3041. struct sde_kms *sde_kms = NULL;
  3042. if (!kms || !obj) {
  3043. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3044. return -EINVAL;
  3045. }
  3046. sde_kms = to_sde_kms(kms);
  3047. switch (obj->type) {
  3048. case DRM_MODE_OBJECT_CRTC:
  3049. crtc = obj_to_crtc(obj);
  3050. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3051. break;
  3052. case DRM_MODE_OBJECT_CONNECTOR:
  3053. conn = obj_to_connector(obj);
  3054. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3055. en);
  3056. break;
  3057. }
  3058. return ret;
  3059. }
  3060. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3061. {
  3062. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3063. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3064. }