qcs405.c 240 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "codecs/msm-cdc-pinctrl.h"
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. SEN_AUX_PCM,
  104. AUX_PCM_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_RX_0 = 0,
  108. WSA_CDC_DMA_RX_1,
  109. CDC_DMA_RX_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_TX_0 = 0,
  113. WSA_CDC_DMA_TX_1,
  114. WSA_CDC_DMA_TX_2,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. PRIM_SPDIF_RX = 0,
  121. SEC_SPDIF_RX,
  122. SPDIF_RX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_TX = 0,
  126. SEC_SPDIF_TX,
  127. SPDIF_TX_MAX,
  128. };
  129. struct mi2s_conf {
  130. struct mutex lock;
  131. u32 ref_cnt;
  132. u32 msm_is_mi2s_master;
  133. };
  134. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  135. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  136. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  161. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  162. int dmic_01_gpio_cnt;
  163. int dmic_23_gpio_cnt;
  164. int dmic_45_gpio_cnt;
  165. int dmic_67_gpio_cnt;
  166. struct regulator *tdm_micb_supply;
  167. u32 tdm_micb_voltage;
  168. u32 tdm_micb_current;
  169. bool codec_is_csra;
  170. };
  171. struct msm_asoc_wcd93xx_codec {
  172. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  173. enum afe_config_type config_type);
  174. };
  175. static const char *const pin_states[] = {"sleep", "i2s-active",
  176. "tdm-active"};
  177. enum {
  178. TDM_0 = 0,
  179. TDM_1,
  180. TDM_2,
  181. TDM_3,
  182. TDM_4,
  183. TDM_5,
  184. TDM_6,
  185. TDM_7,
  186. TDM_PORT_MAX,
  187. };
  188. enum {
  189. TDM_PRI = 0,
  190. TDM_SEC,
  191. TDM_TERT,
  192. TDM_QUAT,
  193. TDM_QUIN,
  194. TDM_INTERFACE_MAX,
  195. };
  196. struct tdm_port {
  197. u32 mode;
  198. u32 channel;
  199. };
  200. /* TDM default config */
  201. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  202. { /* PRI TDM */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  211. },
  212. { /* SEC TDM */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  221. },
  222. { /* TERT TDM */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  231. },
  232. { /* QUAT TDM */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  241. },
  242. { /* QUIN TDM */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  251. }
  252. };
  253. /* TDM default config */
  254. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  255. { /* PRI TDM */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  264. },
  265. { /* SEC TDM */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  274. },
  275. { /* TERT TDM */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  284. },
  285. { /* QUAT TDM */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  294. },
  295. { /* QUIN TDM */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  304. }
  305. };
  306. /* Default configuration of slimbus channels */
  307. static struct dev_config slim_rx_cfg[] = {
  308. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. };
  317. static struct dev_config slim_tx_cfg[] = {
  318. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  327. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. };
  329. /* Default configuration of Codec DMA Interface Tx */
  330. static struct dev_config cdc_dma_rx_cfg[] = {
  331. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. };
  334. /* Default configuration of Codec DMA Interface Rx */
  335. static struct dev_config cdc_dma_tx_cfg[] = {
  336. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  337. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  340. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. };
  342. static struct dev_config usb_rx_cfg = {
  343. .sample_rate = SAMPLING_RATE_48KHZ,
  344. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  345. .channels = 2,
  346. };
  347. static struct dev_config usb_tx_cfg = {
  348. .sample_rate = SAMPLING_RATE_48KHZ,
  349. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  350. .channels = 1,
  351. };
  352. static struct dev_config proxy_rx_cfg = {
  353. .sample_rate = SAMPLING_RATE_48KHZ,
  354. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  355. .channels = 2,
  356. };
  357. /* Default configuration of MI2S channels */
  358. static struct dev_config mi2s_rx_cfg[] = {
  359. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  360. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. };
  366. /* Default configuration of SPDIF channels */
  367. static struct dev_config spdif_rx_cfg[] = {
  368. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. };
  371. static struct dev_config spdif_tx_cfg[] = {
  372. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. };
  375. static struct dev_config mi2s_tx_cfg[] = {
  376. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. };
  383. static struct dev_config aux_pcm_rx_cfg[] = {
  384. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. };
  391. static struct dev_config aux_pcm_tx_cfg[] = {
  392. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. };
  399. static int msm_vi_feed_tx_ch = 2;
  400. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  401. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  402. "Five", "Six", "Seven",
  403. "Eight"};
  404. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  405. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  406. "S32_LE"};
  407. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  408. "KHZ_32", "KHZ_44P1", "KHZ_48",
  409. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  410. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  411. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  412. "KHZ_44P1", "KHZ_48",
  413. "KHZ_88P2", "KHZ_96"};
  414. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  415. "Five", "Six", "Seven",
  416. "Eight"};
  417. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  418. "Six", "Seven", "Eight"};
  419. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  420. "KHZ_16", "KHZ_22P05",
  421. "KHZ_32", "KHZ_44P1", "KHZ_48",
  422. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  423. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  424. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  425. "Five", "Six", "Seven", "Eight"};
  426. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  427. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  428. "KHZ_48", "KHZ_176P4",
  429. "KHZ_352P8"};
  430. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  431. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  432. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  433. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  434. static const char *const mi2s_ch_text[] = {
  435. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  436. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  437. "Fourteen", "Fifteen", "Sixteen"
  438. };
  439. static const char *const qos_text[] = {"Disable", "Enable"};
  440. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  441. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  442. "Five", "Six", "Seven",
  443. "Eight"};
  444. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  445. "KHZ_16", "KHZ_22P05",
  446. "KHZ_32", "KHZ_44P1", "KHZ_48",
  447. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  448. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  449. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  450. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  451. "KHZ_192"};
  452. static const char *spdif_ch_text[] = {"One", "Two"};
  453. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  454. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  539. cdc_dma_sample_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  541. cdc_dma_sample_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  543. cdc_dma_sample_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  545. cdc_dma_sample_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  547. cdc_dma_sample_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  549. cdc_dma_sample_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  551. cdc_dma_sample_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  558. static struct platform_device *spdev;
  559. static bool is_initial_boot;
  560. static bool codec_reg_done;
  561. static struct snd_soc_aux_dev *msm_aux_dev;
  562. static struct snd_soc_codec_conf *msm_codec_conf;
  563. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  564. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  565. int enable, bool dapm);
  566. static int msm_wsa881x_init(struct snd_soc_component *component);
  567. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  568. struct snd_ctl_elem_value *ucontrol);
  569. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  570. {"MIC BIAS1", NULL, "MCLK TX"},
  571. {"MIC BIAS2", NULL, "MCLK TX"},
  572. {"MIC BIAS3", NULL, "MCLK TX"},
  573. {"MIC BIAS4", NULL, "MCLK TX"},
  574. };
  575. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  576. {
  577. AFE_API_VERSION_I2S_CONFIG,
  578. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  579. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  580. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  581. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  582. 0,
  583. },
  584. {
  585. AFE_API_VERSION_I2S_CONFIG,
  586. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  587. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  588. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  589. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  590. 0,
  591. },
  592. {
  593. AFE_API_VERSION_I2S_CONFIG,
  594. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  595. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  596. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  597. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  598. 0,
  599. },
  600. {
  601. AFE_API_VERSION_I2S_CONFIG,
  602. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  603. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  604. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  605. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  606. 0,
  607. },
  608. {
  609. AFE_API_VERSION_I2S_CONFIG,
  610. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  611. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  612. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  613. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  614. 0,
  615. },
  616. {
  617. AFE_API_VERSION_I2S_CONFIG,
  618. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  619. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  620. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  621. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  622. 0,
  623. }
  624. };
  625. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  626. static int slim_get_sample_rate_val(int sample_rate)
  627. {
  628. int sample_rate_val = 0;
  629. switch (sample_rate) {
  630. case SAMPLING_RATE_8KHZ:
  631. sample_rate_val = 0;
  632. break;
  633. case SAMPLING_RATE_16KHZ:
  634. sample_rate_val = 1;
  635. break;
  636. case SAMPLING_RATE_32KHZ:
  637. sample_rate_val = 2;
  638. break;
  639. case SAMPLING_RATE_44P1KHZ:
  640. sample_rate_val = 3;
  641. break;
  642. case SAMPLING_RATE_48KHZ:
  643. sample_rate_val = 4;
  644. break;
  645. case SAMPLING_RATE_88P2KHZ:
  646. sample_rate_val = 5;
  647. break;
  648. case SAMPLING_RATE_96KHZ:
  649. sample_rate_val = 6;
  650. break;
  651. case SAMPLING_RATE_176P4KHZ:
  652. sample_rate_val = 7;
  653. break;
  654. case SAMPLING_RATE_192KHZ:
  655. sample_rate_val = 8;
  656. break;
  657. case SAMPLING_RATE_352P8KHZ:
  658. sample_rate_val = 9;
  659. break;
  660. case SAMPLING_RATE_384KHZ:
  661. sample_rate_val = 10;
  662. break;
  663. default:
  664. sample_rate_val = 4;
  665. break;
  666. }
  667. return sample_rate_val;
  668. }
  669. static int slim_get_sample_rate(int value)
  670. {
  671. int sample_rate = 0;
  672. switch (value) {
  673. case 0:
  674. sample_rate = SAMPLING_RATE_8KHZ;
  675. break;
  676. case 1:
  677. sample_rate = SAMPLING_RATE_16KHZ;
  678. break;
  679. case 2:
  680. sample_rate = SAMPLING_RATE_32KHZ;
  681. break;
  682. case 3:
  683. sample_rate = SAMPLING_RATE_44P1KHZ;
  684. break;
  685. case 4:
  686. sample_rate = SAMPLING_RATE_48KHZ;
  687. break;
  688. case 5:
  689. sample_rate = SAMPLING_RATE_88P2KHZ;
  690. break;
  691. case 6:
  692. sample_rate = SAMPLING_RATE_96KHZ;
  693. break;
  694. case 7:
  695. sample_rate = SAMPLING_RATE_176P4KHZ;
  696. break;
  697. case 8:
  698. sample_rate = SAMPLING_RATE_192KHZ;
  699. break;
  700. case 9:
  701. sample_rate = SAMPLING_RATE_352P8KHZ;
  702. break;
  703. case 10:
  704. sample_rate = SAMPLING_RATE_384KHZ;
  705. break;
  706. default:
  707. sample_rate = SAMPLING_RATE_48KHZ;
  708. break;
  709. }
  710. return sample_rate;
  711. }
  712. static int slim_get_bit_format_val(int bit_format)
  713. {
  714. int val = 0;
  715. switch (bit_format) {
  716. case SNDRV_PCM_FORMAT_S32_LE:
  717. val = 3;
  718. break;
  719. case SNDRV_PCM_FORMAT_S24_3LE:
  720. val = 2;
  721. break;
  722. case SNDRV_PCM_FORMAT_S24_LE:
  723. val = 1;
  724. break;
  725. case SNDRV_PCM_FORMAT_S16_LE:
  726. default:
  727. val = 0;
  728. break;
  729. }
  730. return val;
  731. }
  732. static int slim_get_bit_format(int val)
  733. {
  734. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  735. switch (val) {
  736. case 0:
  737. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  738. break;
  739. case 1:
  740. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  741. break;
  742. case 2:
  743. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  744. break;
  745. case 3:
  746. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  747. break;
  748. default:
  749. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  750. break;
  751. }
  752. return bit_fmt;
  753. }
  754. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  755. {
  756. int port_id = 0;
  757. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  758. port_id = SLIM_RX_0;
  759. } else if (strnstr(kcontrol->id.name,
  760. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  761. port_id = SLIM_RX_2;
  762. } else if (strnstr(kcontrol->id.name,
  763. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  764. port_id = SLIM_RX_5;
  765. } else if (strnstr(kcontrol->id.name,
  766. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  767. port_id = SLIM_RX_6;
  768. } else if (strnstr(kcontrol->id.name,
  769. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  770. port_id = SLIM_TX_0;
  771. } else if (strnstr(kcontrol->id.name,
  772. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  773. port_id = SLIM_TX_1;
  774. } else {
  775. pr_err("%s: unsupported channel: %s",
  776. __func__, kcontrol->id.name);
  777. return -EINVAL;
  778. }
  779. return port_id;
  780. }
  781. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  782. struct snd_ctl_elem_value *ucontrol)
  783. {
  784. int ch_num = slim_get_port_idx(kcontrol);
  785. if (ch_num < 0)
  786. return ch_num;
  787. ucontrol->value.enumerated.item[0] =
  788. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  789. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  790. ch_num, slim_rx_cfg[ch_num].sample_rate,
  791. ucontrol->value.enumerated.item[0]);
  792. return 0;
  793. }
  794. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  795. struct snd_ctl_elem_value *ucontrol)
  796. {
  797. int ch_num = slim_get_port_idx(kcontrol);
  798. if (ch_num < 0)
  799. return ch_num;
  800. slim_rx_cfg[ch_num].sample_rate =
  801. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  802. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  803. ch_num, slim_rx_cfg[ch_num].sample_rate,
  804. ucontrol->value.enumerated.item[0]);
  805. return 0;
  806. }
  807. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  808. struct snd_ctl_elem_value *ucontrol)
  809. {
  810. int ch_num = slim_get_port_idx(kcontrol);
  811. if (ch_num < 0)
  812. return ch_num;
  813. ucontrol->value.enumerated.item[0] =
  814. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  815. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  816. ch_num, slim_tx_cfg[ch_num].sample_rate,
  817. ucontrol->value.enumerated.item[0]);
  818. return 0;
  819. }
  820. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  821. struct snd_ctl_elem_value *ucontrol)
  822. {
  823. int sample_rate = 0;
  824. int ch_num = slim_get_port_idx(kcontrol);
  825. if (ch_num < 0)
  826. return ch_num;
  827. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  828. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  829. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  830. __func__, sample_rate);
  831. return -EINVAL;
  832. }
  833. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  834. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  835. ch_num, slim_tx_cfg[ch_num].sample_rate,
  836. ucontrol->value.enumerated.item[0]);
  837. return 0;
  838. }
  839. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  840. struct snd_ctl_elem_value *ucontrol)
  841. {
  842. int ch_num = slim_get_port_idx(kcontrol);
  843. if (ch_num < 0)
  844. return ch_num;
  845. ucontrol->value.enumerated.item[0] =
  846. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  847. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  848. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  849. ucontrol->value.enumerated.item[0]);
  850. return 0;
  851. }
  852. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. int ch_num = slim_get_port_idx(kcontrol);
  856. if (ch_num < 0)
  857. return ch_num;
  858. slim_rx_cfg[ch_num].bit_format =
  859. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  860. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  861. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  862. ucontrol->value.enumerated.item[0]);
  863. return 0;
  864. }
  865. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. int ch_num = slim_get_port_idx(kcontrol);
  869. if (ch_num < 0)
  870. return ch_num;
  871. ucontrol->value.enumerated.item[0] =
  872. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  873. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  874. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  875. ucontrol->value.enumerated.item[0]);
  876. return 0;
  877. }
  878. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. int ch_num = slim_get_port_idx(kcontrol);
  882. if (ch_num < 0)
  883. return ch_num;
  884. slim_tx_cfg[ch_num].bit_format =
  885. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  886. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  887. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  888. ucontrol->value.enumerated.item[0]);
  889. return 0;
  890. }
  891. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_value *ucontrol)
  893. {
  894. int ch_num = slim_get_port_idx(kcontrol);
  895. if (ch_num < 0)
  896. return ch_num;
  897. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  898. ch_num, slim_rx_cfg[ch_num].channels);
  899. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  900. return 0;
  901. }
  902. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. int ch_num = slim_get_port_idx(kcontrol);
  906. if (ch_num < 0)
  907. return ch_num;
  908. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  909. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  910. ch_num, slim_rx_cfg[ch_num].channels);
  911. return 1;
  912. }
  913. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  914. struct snd_ctl_elem_value *ucontrol)
  915. {
  916. int ch_num = slim_get_port_idx(kcontrol);
  917. if (ch_num < 0)
  918. return ch_num;
  919. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  920. ch_num, slim_tx_cfg[ch_num].channels);
  921. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  922. return 0;
  923. }
  924. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. int ch_num = slim_get_port_idx(kcontrol);
  928. if (ch_num < 0)
  929. return ch_num;
  930. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  931. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  932. ch_num, slim_tx_cfg[ch_num].channels);
  933. return 1;
  934. }
  935. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  939. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  940. ucontrol->value.integer.value[0]);
  941. return 0;
  942. }
  943. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  944. struct snd_ctl_elem_value *ucontrol)
  945. {
  946. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  947. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  948. return 1;
  949. }
  950. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  951. struct snd_ctl_elem_value *ucontrol)
  952. {
  953. /*
  954. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  955. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  956. * value.
  957. */
  958. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  959. case SAMPLING_RATE_96KHZ:
  960. ucontrol->value.integer.value[0] = 5;
  961. break;
  962. case SAMPLING_RATE_88P2KHZ:
  963. ucontrol->value.integer.value[0] = 4;
  964. break;
  965. case SAMPLING_RATE_48KHZ:
  966. ucontrol->value.integer.value[0] = 3;
  967. break;
  968. case SAMPLING_RATE_44P1KHZ:
  969. ucontrol->value.integer.value[0] = 2;
  970. break;
  971. case SAMPLING_RATE_16KHZ:
  972. ucontrol->value.integer.value[0] = 1;
  973. break;
  974. case SAMPLING_RATE_8KHZ:
  975. default:
  976. ucontrol->value.integer.value[0] = 0;
  977. break;
  978. }
  979. pr_debug("%s: sample rate = %d", __func__,
  980. slim_rx_cfg[SLIM_RX_7].sample_rate);
  981. return 0;
  982. }
  983. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  984. struct snd_ctl_elem_value *ucontrol)
  985. {
  986. switch (ucontrol->value.integer.value[0]) {
  987. case 1:
  988. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  989. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  990. break;
  991. case 2:
  992. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  993. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  994. break;
  995. case 3:
  996. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  997. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  998. break;
  999. case 4:
  1000. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1001. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1002. break;
  1003. case 5:
  1004. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1005. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1006. break;
  1007. case 0:
  1008. default:
  1009. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1010. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1011. break;
  1012. }
  1013. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1014. __func__,
  1015. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1016. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1017. ucontrol->value.enumerated.item[0]);
  1018. return 0;
  1019. }
  1020. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1021. struct snd_ctl_elem_value *ucontrol)
  1022. {
  1023. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1024. case SAMPLING_RATE_96KHZ:
  1025. ucontrol->value.integer.value[0] = 5;
  1026. break;
  1027. case SAMPLING_RATE_88P2KHZ:
  1028. ucontrol->value.integer.value[0] = 4;
  1029. break;
  1030. case SAMPLING_RATE_48KHZ:
  1031. ucontrol->value.integer.value[0] = 3;
  1032. break;
  1033. case SAMPLING_RATE_44P1KHZ:
  1034. ucontrol->value.integer.value[0] = 2;
  1035. break;
  1036. case SAMPLING_RATE_16KHZ:
  1037. ucontrol->value.integer.value[0] = 1;
  1038. break;
  1039. case SAMPLING_RATE_8KHZ:
  1040. default:
  1041. ucontrol->value.integer.value[0] = 0;
  1042. break;
  1043. }
  1044. pr_debug("%s: sample rate = %d", __func__,
  1045. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1046. return 0;
  1047. }
  1048. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1049. struct snd_ctl_elem_value *ucontrol)
  1050. {
  1051. switch (ucontrol->value.integer.value[0]) {
  1052. case 1:
  1053. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1054. break;
  1055. case 2:
  1056. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1057. break;
  1058. case 3:
  1059. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1060. break;
  1061. case 4:
  1062. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1063. break;
  1064. case 5:
  1065. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1066. break;
  1067. case 0:
  1068. default:
  1069. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1070. break;
  1071. }
  1072. pr_debug("%s: sample rate = %d, value = %d\n",
  1073. __func__,
  1074. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1075. ucontrol->value.enumerated.item[0]);
  1076. return 0;
  1077. }
  1078. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1079. {
  1080. int idx = 0;
  1081. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1082. sizeof("WSA_CDC_DMA_RX_0")))
  1083. idx = WSA_CDC_DMA_RX_0;
  1084. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1085. sizeof("WSA_CDC_DMA_RX_0")))
  1086. idx = WSA_CDC_DMA_RX_1;
  1087. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1088. sizeof("WSA_CDC_DMA_TX_0")))
  1089. idx = WSA_CDC_DMA_TX_0;
  1090. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1091. sizeof("WSA_CDC_DMA_TX_1")))
  1092. idx = WSA_CDC_DMA_TX_1;
  1093. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1094. sizeof("WSA_CDC_DMA_TX_2")))
  1095. idx = WSA_CDC_DMA_TX_2;
  1096. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1097. sizeof("VA_CDC_DMA_TX_0")))
  1098. idx = VA_CDC_DMA_TX_0;
  1099. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1100. sizeof("VA_CDC_DMA_TX_1")))
  1101. idx = VA_CDC_DMA_TX_1;
  1102. else {
  1103. pr_err("%s: unsupported port: %s\n",
  1104. __func__, kcontrol->id.name);
  1105. return -EINVAL;
  1106. }
  1107. return idx;
  1108. }
  1109. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1110. struct snd_ctl_elem_value *ucontrol)
  1111. {
  1112. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1113. if (ch_num < 0)
  1114. return ch_num;
  1115. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1116. cdc_dma_rx_cfg[ch_num].channels - 1);
  1117. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1118. return 0;
  1119. }
  1120. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1121. struct snd_ctl_elem_value *ucontrol)
  1122. {
  1123. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1124. if (ch_num < 0)
  1125. return ch_num;
  1126. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1127. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1128. cdc_dma_rx_cfg[ch_num].channels);
  1129. return 1;
  1130. }
  1131. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1132. struct snd_ctl_elem_value *ucontrol)
  1133. {
  1134. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1135. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1136. case SNDRV_PCM_FORMAT_S32_LE:
  1137. ucontrol->value.integer.value[0] = 3;
  1138. break;
  1139. case SNDRV_PCM_FORMAT_S24_3LE:
  1140. ucontrol->value.integer.value[0] = 2;
  1141. break;
  1142. case SNDRV_PCM_FORMAT_S24_LE:
  1143. ucontrol->value.integer.value[0] = 1;
  1144. break;
  1145. case SNDRV_PCM_FORMAT_S16_LE:
  1146. default:
  1147. ucontrol->value.integer.value[0] = 0;
  1148. break;
  1149. }
  1150. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1151. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1152. ucontrol->value.integer.value[0]);
  1153. return 0;
  1154. }
  1155. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1156. struct snd_ctl_elem_value *ucontrol)
  1157. {
  1158. int rc = 0;
  1159. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1160. switch (ucontrol->value.integer.value[0]) {
  1161. case 3:
  1162. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1163. break;
  1164. case 2:
  1165. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1166. break;
  1167. case 1:
  1168. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1169. break;
  1170. case 0:
  1171. default:
  1172. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1173. break;
  1174. }
  1175. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1176. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1177. ucontrol->value.integer.value[0]);
  1178. return rc;
  1179. }
  1180. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1181. {
  1182. int sample_rate_val = 0;
  1183. switch (sample_rate) {
  1184. case SAMPLING_RATE_8KHZ:
  1185. sample_rate_val = 0;
  1186. break;
  1187. case SAMPLING_RATE_11P025KHZ:
  1188. sample_rate_val = 1;
  1189. break;
  1190. case SAMPLING_RATE_16KHZ:
  1191. sample_rate_val = 2;
  1192. break;
  1193. case SAMPLING_RATE_22P05KHZ:
  1194. sample_rate_val = 3;
  1195. break;
  1196. case SAMPLING_RATE_32KHZ:
  1197. sample_rate_val = 4;
  1198. break;
  1199. case SAMPLING_RATE_44P1KHZ:
  1200. sample_rate_val = 5;
  1201. break;
  1202. case SAMPLING_RATE_48KHZ:
  1203. sample_rate_val = 6;
  1204. break;
  1205. case SAMPLING_RATE_88P2KHZ:
  1206. sample_rate_val = 7;
  1207. break;
  1208. case SAMPLING_RATE_96KHZ:
  1209. sample_rate_val = 8;
  1210. break;
  1211. case SAMPLING_RATE_176P4KHZ:
  1212. sample_rate_val = 9;
  1213. break;
  1214. case SAMPLING_RATE_192KHZ:
  1215. sample_rate_val = 10;
  1216. break;
  1217. case SAMPLING_RATE_352P8KHZ:
  1218. sample_rate_val = 11;
  1219. break;
  1220. case SAMPLING_RATE_384KHZ:
  1221. sample_rate_val = 12;
  1222. break;
  1223. default:
  1224. sample_rate_val = 6;
  1225. break;
  1226. }
  1227. return sample_rate_val;
  1228. }
  1229. static int cdc_dma_get_sample_rate(int value)
  1230. {
  1231. int sample_rate = 0;
  1232. switch (value) {
  1233. case 0:
  1234. sample_rate = SAMPLING_RATE_8KHZ;
  1235. break;
  1236. case 1:
  1237. sample_rate = SAMPLING_RATE_11P025KHZ;
  1238. break;
  1239. case 2:
  1240. sample_rate = SAMPLING_RATE_16KHZ;
  1241. break;
  1242. case 3:
  1243. sample_rate = SAMPLING_RATE_22P05KHZ;
  1244. break;
  1245. case 4:
  1246. sample_rate = SAMPLING_RATE_32KHZ;
  1247. break;
  1248. case 5:
  1249. sample_rate = SAMPLING_RATE_44P1KHZ;
  1250. break;
  1251. case 6:
  1252. sample_rate = SAMPLING_RATE_48KHZ;
  1253. break;
  1254. case 7:
  1255. sample_rate = SAMPLING_RATE_88P2KHZ;
  1256. break;
  1257. case 8:
  1258. sample_rate = SAMPLING_RATE_96KHZ;
  1259. break;
  1260. case 9:
  1261. sample_rate = SAMPLING_RATE_176P4KHZ;
  1262. break;
  1263. case 10:
  1264. sample_rate = SAMPLING_RATE_192KHZ;
  1265. break;
  1266. case 11:
  1267. sample_rate = SAMPLING_RATE_352P8KHZ;
  1268. break;
  1269. case 12:
  1270. sample_rate = SAMPLING_RATE_384KHZ;
  1271. break;
  1272. default:
  1273. sample_rate = SAMPLING_RATE_48KHZ;
  1274. break;
  1275. }
  1276. return sample_rate;
  1277. }
  1278. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1279. struct snd_ctl_elem_value *ucontrol)
  1280. {
  1281. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1282. if (ch_num < 0)
  1283. return ch_num;
  1284. ucontrol->value.enumerated.item[0] =
  1285. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1286. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1287. cdc_dma_rx_cfg[ch_num].sample_rate);
  1288. return 0;
  1289. }
  1290. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1291. struct snd_ctl_elem_value *ucontrol)
  1292. {
  1293. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1294. if (ch_num < 0)
  1295. return ch_num;
  1296. cdc_dma_rx_cfg[ch_num].sample_rate =
  1297. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1298. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1299. __func__, ucontrol->value.enumerated.item[0],
  1300. cdc_dma_rx_cfg[ch_num].sample_rate);
  1301. return 0;
  1302. }
  1303. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1304. struct snd_ctl_elem_value *ucontrol)
  1305. {
  1306. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1307. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1308. cdc_dma_tx_cfg[ch_num].channels);
  1309. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1310. return 0;
  1311. }
  1312. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1313. struct snd_ctl_elem_value *ucontrol)
  1314. {
  1315. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1316. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1317. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1318. cdc_dma_tx_cfg[ch_num].channels);
  1319. return 1;
  1320. }
  1321. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. int sample_rate_val;
  1325. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1326. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1327. case SAMPLING_RATE_384KHZ:
  1328. sample_rate_val = 12;
  1329. break;
  1330. case SAMPLING_RATE_352P8KHZ:
  1331. sample_rate_val = 11;
  1332. break;
  1333. case SAMPLING_RATE_192KHZ:
  1334. sample_rate_val = 10;
  1335. break;
  1336. case SAMPLING_RATE_176P4KHZ:
  1337. sample_rate_val = 9;
  1338. break;
  1339. case SAMPLING_RATE_96KHZ:
  1340. sample_rate_val = 8;
  1341. break;
  1342. case SAMPLING_RATE_88P2KHZ:
  1343. sample_rate_val = 7;
  1344. break;
  1345. case SAMPLING_RATE_48KHZ:
  1346. sample_rate_val = 6;
  1347. break;
  1348. case SAMPLING_RATE_44P1KHZ:
  1349. sample_rate_val = 5;
  1350. break;
  1351. case SAMPLING_RATE_32KHZ:
  1352. sample_rate_val = 4;
  1353. break;
  1354. case SAMPLING_RATE_22P05KHZ:
  1355. sample_rate_val = 3;
  1356. break;
  1357. case SAMPLING_RATE_16KHZ:
  1358. sample_rate_val = 2;
  1359. break;
  1360. case SAMPLING_RATE_11P025KHZ:
  1361. sample_rate_val = 1;
  1362. break;
  1363. case SAMPLING_RATE_8KHZ:
  1364. sample_rate_val = 0;
  1365. break;
  1366. default:
  1367. sample_rate_val = 6;
  1368. break;
  1369. }
  1370. ucontrol->value.integer.value[0] = sample_rate_val;
  1371. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1372. cdc_dma_tx_cfg[ch_num].sample_rate);
  1373. return 0;
  1374. }
  1375. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1376. struct snd_ctl_elem_value *ucontrol)
  1377. {
  1378. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1379. switch (ucontrol->value.integer.value[0]) {
  1380. case 12:
  1381. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1382. break;
  1383. case 11:
  1384. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1385. break;
  1386. case 10:
  1387. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1388. break;
  1389. case 9:
  1390. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1391. break;
  1392. case 8:
  1393. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1394. break;
  1395. case 7:
  1396. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1397. break;
  1398. case 6:
  1399. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1400. break;
  1401. case 5:
  1402. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1403. break;
  1404. case 4:
  1405. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1406. break;
  1407. case 3:
  1408. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1409. break;
  1410. case 2:
  1411. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1412. break;
  1413. case 1:
  1414. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1415. break;
  1416. case 0:
  1417. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1418. break;
  1419. default:
  1420. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1421. break;
  1422. }
  1423. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1424. __func__, ucontrol->value.integer.value[0],
  1425. cdc_dma_tx_cfg[ch_num].sample_rate);
  1426. return 0;
  1427. }
  1428. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1429. struct snd_ctl_elem_value *ucontrol)
  1430. {
  1431. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1432. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1433. case SNDRV_PCM_FORMAT_S32_LE:
  1434. ucontrol->value.integer.value[0] = 3;
  1435. break;
  1436. case SNDRV_PCM_FORMAT_S24_3LE:
  1437. ucontrol->value.integer.value[0] = 2;
  1438. break;
  1439. case SNDRV_PCM_FORMAT_S24_LE:
  1440. ucontrol->value.integer.value[0] = 1;
  1441. break;
  1442. case SNDRV_PCM_FORMAT_S16_LE:
  1443. default:
  1444. ucontrol->value.integer.value[0] = 0;
  1445. break;
  1446. }
  1447. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1448. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1449. ucontrol->value.integer.value[0]);
  1450. return 0;
  1451. }
  1452. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1453. struct snd_ctl_elem_value *ucontrol)
  1454. {
  1455. int rc = 0;
  1456. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1457. switch (ucontrol->value.integer.value[0]) {
  1458. case 3:
  1459. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1460. break;
  1461. case 2:
  1462. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1463. break;
  1464. case 1:
  1465. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1466. break;
  1467. case 0:
  1468. default:
  1469. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1470. break;
  1471. }
  1472. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1473. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1474. ucontrol->value.integer.value[0]);
  1475. return rc;
  1476. }
  1477. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1481. usb_rx_cfg.channels);
  1482. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1483. return 0;
  1484. }
  1485. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1486. struct snd_ctl_elem_value *ucontrol)
  1487. {
  1488. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1489. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1490. return 1;
  1491. }
  1492. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_value *ucontrol)
  1494. {
  1495. int sample_rate_val;
  1496. switch (usb_rx_cfg.sample_rate) {
  1497. case SAMPLING_RATE_384KHZ:
  1498. sample_rate_val = 12;
  1499. break;
  1500. case SAMPLING_RATE_352P8KHZ:
  1501. sample_rate_val = 11;
  1502. break;
  1503. case SAMPLING_RATE_192KHZ:
  1504. sample_rate_val = 10;
  1505. break;
  1506. case SAMPLING_RATE_176P4KHZ:
  1507. sample_rate_val = 9;
  1508. break;
  1509. case SAMPLING_RATE_96KHZ:
  1510. sample_rate_val = 8;
  1511. break;
  1512. case SAMPLING_RATE_88P2KHZ:
  1513. sample_rate_val = 7;
  1514. break;
  1515. case SAMPLING_RATE_48KHZ:
  1516. sample_rate_val = 6;
  1517. break;
  1518. case SAMPLING_RATE_44P1KHZ:
  1519. sample_rate_val = 5;
  1520. break;
  1521. case SAMPLING_RATE_32KHZ:
  1522. sample_rate_val = 4;
  1523. break;
  1524. case SAMPLING_RATE_22P05KHZ:
  1525. sample_rate_val = 3;
  1526. break;
  1527. case SAMPLING_RATE_16KHZ:
  1528. sample_rate_val = 2;
  1529. break;
  1530. case SAMPLING_RATE_11P025KHZ:
  1531. sample_rate_val = 1;
  1532. break;
  1533. case SAMPLING_RATE_8KHZ:
  1534. default:
  1535. sample_rate_val = 0;
  1536. break;
  1537. }
  1538. ucontrol->value.integer.value[0] = sample_rate_val;
  1539. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1540. usb_rx_cfg.sample_rate);
  1541. return 0;
  1542. }
  1543. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. switch (ucontrol->value.integer.value[0]) {
  1547. case 12:
  1548. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1549. break;
  1550. case 11:
  1551. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1552. break;
  1553. case 10:
  1554. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1555. break;
  1556. case 9:
  1557. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1558. break;
  1559. case 8:
  1560. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1561. break;
  1562. case 7:
  1563. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1564. break;
  1565. case 6:
  1566. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1567. break;
  1568. case 5:
  1569. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1570. break;
  1571. case 4:
  1572. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1573. break;
  1574. case 3:
  1575. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1576. break;
  1577. case 2:
  1578. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1579. break;
  1580. case 1:
  1581. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1582. break;
  1583. case 0:
  1584. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1585. break;
  1586. default:
  1587. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1588. break;
  1589. }
  1590. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1591. __func__, ucontrol->value.integer.value[0],
  1592. usb_rx_cfg.sample_rate);
  1593. return 0;
  1594. }
  1595. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_value *ucontrol)
  1597. {
  1598. switch (usb_rx_cfg.bit_format) {
  1599. case SNDRV_PCM_FORMAT_S32_LE:
  1600. ucontrol->value.integer.value[0] = 3;
  1601. break;
  1602. case SNDRV_PCM_FORMAT_S24_3LE:
  1603. ucontrol->value.integer.value[0] = 2;
  1604. break;
  1605. case SNDRV_PCM_FORMAT_S24_LE:
  1606. ucontrol->value.integer.value[0] = 1;
  1607. break;
  1608. case SNDRV_PCM_FORMAT_S16_LE:
  1609. default:
  1610. ucontrol->value.integer.value[0] = 0;
  1611. break;
  1612. }
  1613. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1614. __func__, usb_rx_cfg.bit_format,
  1615. ucontrol->value.integer.value[0]);
  1616. return 0;
  1617. }
  1618. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1619. struct snd_ctl_elem_value *ucontrol)
  1620. {
  1621. int rc = 0;
  1622. switch (ucontrol->value.integer.value[0]) {
  1623. case 3:
  1624. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1625. break;
  1626. case 2:
  1627. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1628. break;
  1629. case 1:
  1630. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1631. break;
  1632. case 0:
  1633. default:
  1634. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1635. break;
  1636. }
  1637. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1638. __func__, usb_rx_cfg.bit_format,
  1639. ucontrol->value.integer.value[0]);
  1640. return rc;
  1641. }
  1642. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1643. struct snd_ctl_elem_value *ucontrol)
  1644. {
  1645. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1646. usb_tx_cfg.channels);
  1647. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1648. return 0;
  1649. }
  1650. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1651. struct snd_ctl_elem_value *ucontrol)
  1652. {
  1653. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1654. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1655. return 1;
  1656. }
  1657. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1658. struct snd_ctl_elem_value *ucontrol)
  1659. {
  1660. int sample_rate_val;
  1661. switch (usb_tx_cfg.sample_rate) {
  1662. case SAMPLING_RATE_384KHZ:
  1663. sample_rate_val = 12;
  1664. break;
  1665. case SAMPLING_RATE_352P8KHZ:
  1666. sample_rate_val = 11;
  1667. break;
  1668. case SAMPLING_RATE_192KHZ:
  1669. sample_rate_val = 10;
  1670. break;
  1671. case SAMPLING_RATE_176P4KHZ:
  1672. sample_rate_val = 9;
  1673. break;
  1674. case SAMPLING_RATE_96KHZ:
  1675. sample_rate_val = 8;
  1676. break;
  1677. case SAMPLING_RATE_88P2KHZ:
  1678. sample_rate_val = 7;
  1679. break;
  1680. case SAMPLING_RATE_48KHZ:
  1681. sample_rate_val = 6;
  1682. break;
  1683. case SAMPLING_RATE_44P1KHZ:
  1684. sample_rate_val = 5;
  1685. break;
  1686. case SAMPLING_RATE_32KHZ:
  1687. sample_rate_val = 4;
  1688. break;
  1689. case SAMPLING_RATE_22P05KHZ:
  1690. sample_rate_val = 3;
  1691. break;
  1692. case SAMPLING_RATE_16KHZ:
  1693. sample_rate_val = 2;
  1694. break;
  1695. case SAMPLING_RATE_11P025KHZ:
  1696. sample_rate_val = 1;
  1697. break;
  1698. case SAMPLING_RATE_8KHZ:
  1699. sample_rate_val = 0;
  1700. break;
  1701. default:
  1702. sample_rate_val = 6;
  1703. break;
  1704. }
  1705. ucontrol->value.integer.value[0] = sample_rate_val;
  1706. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1707. usb_tx_cfg.sample_rate);
  1708. return 0;
  1709. }
  1710. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1711. struct snd_ctl_elem_value *ucontrol)
  1712. {
  1713. switch (ucontrol->value.integer.value[0]) {
  1714. case 12:
  1715. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1716. break;
  1717. case 11:
  1718. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1719. break;
  1720. case 10:
  1721. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1722. break;
  1723. case 9:
  1724. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1725. break;
  1726. case 8:
  1727. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1728. break;
  1729. case 7:
  1730. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1731. break;
  1732. case 6:
  1733. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1734. break;
  1735. case 5:
  1736. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1737. break;
  1738. case 4:
  1739. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1740. break;
  1741. case 3:
  1742. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1743. break;
  1744. case 2:
  1745. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1746. break;
  1747. case 1:
  1748. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1749. break;
  1750. case 0:
  1751. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1752. break;
  1753. default:
  1754. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1755. break;
  1756. }
  1757. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1758. __func__, ucontrol->value.integer.value[0],
  1759. usb_tx_cfg.sample_rate);
  1760. return 0;
  1761. }
  1762. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1763. struct snd_ctl_elem_value *ucontrol)
  1764. {
  1765. switch (usb_tx_cfg.bit_format) {
  1766. case SNDRV_PCM_FORMAT_S32_LE:
  1767. ucontrol->value.integer.value[0] = 3;
  1768. break;
  1769. case SNDRV_PCM_FORMAT_S24_3LE:
  1770. ucontrol->value.integer.value[0] = 2;
  1771. break;
  1772. case SNDRV_PCM_FORMAT_S24_LE:
  1773. ucontrol->value.integer.value[0] = 1;
  1774. break;
  1775. case SNDRV_PCM_FORMAT_S16_LE:
  1776. default:
  1777. ucontrol->value.integer.value[0] = 0;
  1778. break;
  1779. }
  1780. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1781. __func__, usb_tx_cfg.bit_format,
  1782. ucontrol->value.integer.value[0]);
  1783. return 0;
  1784. }
  1785. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1786. struct snd_ctl_elem_value *ucontrol)
  1787. {
  1788. int rc = 0;
  1789. switch (ucontrol->value.integer.value[0]) {
  1790. case 3:
  1791. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1792. break;
  1793. case 2:
  1794. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1795. break;
  1796. case 1:
  1797. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1798. break;
  1799. case 0:
  1800. default:
  1801. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1802. break;
  1803. }
  1804. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1805. __func__, usb_tx_cfg.bit_format,
  1806. ucontrol->value.integer.value[0]);
  1807. return rc;
  1808. }
  1809. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1810. struct snd_ctl_elem_value *ucontrol)
  1811. {
  1812. pr_debug("%s: proxy_rx channels = %d\n",
  1813. __func__, proxy_rx_cfg.channels);
  1814. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1815. return 0;
  1816. }
  1817. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1818. struct snd_ctl_elem_value *ucontrol)
  1819. {
  1820. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1821. pr_debug("%s: proxy_rx channels = %d\n",
  1822. __func__, proxy_rx_cfg.channels);
  1823. return 1;
  1824. }
  1825. static int tdm_get_sample_rate(int value)
  1826. {
  1827. int sample_rate = 0;
  1828. switch (value) {
  1829. case 0:
  1830. sample_rate = SAMPLING_RATE_8KHZ;
  1831. break;
  1832. case 1:
  1833. sample_rate = SAMPLING_RATE_16KHZ;
  1834. break;
  1835. case 2:
  1836. sample_rate = SAMPLING_RATE_32KHZ;
  1837. break;
  1838. case 3:
  1839. sample_rate = SAMPLING_RATE_48KHZ;
  1840. break;
  1841. case 4:
  1842. sample_rate = SAMPLING_RATE_176P4KHZ;
  1843. break;
  1844. case 5:
  1845. sample_rate = SAMPLING_RATE_352P8KHZ;
  1846. break;
  1847. default:
  1848. sample_rate = SAMPLING_RATE_48KHZ;
  1849. break;
  1850. }
  1851. return sample_rate;
  1852. }
  1853. static int aux_pcm_get_sample_rate(int value)
  1854. {
  1855. int sample_rate;
  1856. switch (value) {
  1857. case 1:
  1858. sample_rate = SAMPLING_RATE_16KHZ;
  1859. break;
  1860. case 0:
  1861. default:
  1862. sample_rate = SAMPLING_RATE_8KHZ;
  1863. break;
  1864. }
  1865. return sample_rate;
  1866. }
  1867. static int tdm_get_sample_rate_val(int sample_rate)
  1868. {
  1869. int sample_rate_val = 0;
  1870. switch (sample_rate) {
  1871. case SAMPLING_RATE_8KHZ:
  1872. sample_rate_val = 0;
  1873. break;
  1874. case SAMPLING_RATE_16KHZ:
  1875. sample_rate_val = 1;
  1876. break;
  1877. case SAMPLING_RATE_32KHZ:
  1878. sample_rate_val = 2;
  1879. break;
  1880. case SAMPLING_RATE_48KHZ:
  1881. sample_rate_val = 3;
  1882. break;
  1883. case SAMPLING_RATE_176P4KHZ:
  1884. sample_rate_val = 4;
  1885. break;
  1886. case SAMPLING_RATE_352P8KHZ:
  1887. sample_rate_val = 5;
  1888. break;
  1889. default:
  1890. sample_rate_val = 3;
  1891. break;
  1892. }
  1893. return sample_rate_val;
  1894. }
  1895. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1896. {
  1897. int sample_rate_val;
  1898. switch (sample_rate) {
  1899. case SAMPLING_RATE_16KHZ:
  1900. sample_rate_val = 1;
  1901. break;
  1902. case SAMPLING_RATE_8KHZ:
  1903. default:
  1904. sample_rate_val = 0;
  1905. break;
  1906. }
  1907. return sample_rate_val;
  1908. }
  1909. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1910. struct tdm_port *port)
  1911. {
  1912. if (port) {
  1913. if (strnstr(kcontrol->id.name, "PRI",
  1914. sizeof(kcontrol->id.name))) {
  1915. port->mode = TDM_PRI;
  1916. } else if (strnstr(kcontrol->id.name, "SEC",
  1917. sizeof(kcontrol->id.name))) {
  1918. port->mode = TDM_SEC;
  1919. } else if (strnstr(kcontrol->id.name, "TERT",
  1920. sizeof(kcontrol->id.name))) {
  1921. port->mode = TDM_TERT;
  1922. } else if (strnstr(kcontrol->id.name, "QUAT",
  1923. sizeof(kcontrol->id.name))) {
  1924. port->mode = TDM_QUAT;
  1925. } else if (strnstr(kcontrol->id.name, "QUIN",
  1926. sizeof(kcontrol->id.name))) {
  1927. port->mode = TDM_QUIN;
  1928. } else {
  1929. pr_err("%s: unsupported mode in: %s",
  1930. __func__, kcontrol->id.name);
  1931. return -EINVAL;
  1932. }
  1933. if (strnstr(kcontrol->id.name, "RX_0",
  1934. sizeof(kcontrol->id.name)) ||
  1935. strnstr(kcontrol->id.name, "TX_0",
  1936. sizeof(kcontrol->id.name))) {
  1937. port->channel = TDM_0;
  1938. } else if (strnstr(kcontrol->id.name, "RX_1",
  1939. sizeof(kcontrol->id.name)) ||
  1940. strnstr(kcontrol->id.name, "TX_1",
  1941. sizeof(kcontrol->id.name))) {
  1942. port->channel = TDM_1;
  1943. } else if (strnstr(kcontrol->id.name, "RX_2",
  1944. sizeof(kcontrol->id.name)) ||
  1945. strnstr(kcontrol->id.name, "TX_2",
  1946. sizeof(kcontrol->id.name))) {
  1947. port->channel = TDM_2;
  1948. } else if (strnstr(kcontrol->id.name, "RX_3",
  1949. sizeof(kcontrol->id.name)) ||
  1950. strnstr(kcontrol->id.name, "TX_3",
  1951. sizeof(kcontrol->id.name))) {
  1952. port->channel = TDM_3;
  1953. } else if (strnstr(kcontrol->id.name, "RX_4",
  1954. sizeof(kcontrol->id.name)) ||
  1955. strnstr(kcontrol->id.name, "TX_4",
  1956. sizeof(kcontrol->id.name))) {
  1957. port->channel = TDM_4;
  1958. } else if (strnstr(kcontrol->id.name, "RX_5",
  1959. sizeof(kcontrol->id.name)) ||
  1960. strnstr(kcontrol->id.name, "TX_5",
  1961. sizeof(kcontrol->id.name))) {
  1962. port->channel = TDM_5;
  1963. } else if (strnstr(kcontrol->id.name, "RX_6",
  1964. sizeof(kcontrol->id.name)) ||
  1965. strnstr(kcontrol->id.name, "TX_6",
  1966. sizeof(kcontrol->id.name))) {
  1967. port->channel = TDM_6;
  1968. } else if (strnstr(kcontrol->id.name, "RX_7",
  1969. sizeof(kcontrol->id.name)) ||
  1970. strnstr(kcontrol->id.name, "TX_7",
  1971. sizeof(kcontrol->id.name))) {
  1972. port->channel = TDM_7;
  1973. } else {
  1974. pr_err("%s: unsupported channel in: %s",
  1975. __func__, kcontrol->id.name);
  1976. return -EINVAL;
  1977. }
  1978. } else
  1979. return -EINVAL;
  1980. return 0;
  1981. }
  1982. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1983. struct snd_ctl_elem_value *ucontrol)
  1984. {
  1985. struct tdm_port port;
  1986. int ret = tdm_get_port_idx(kcontrol, &port);
  1987. if (ret) {
  1988. pr_err("%s: unsupported control: %s",
  1989. __func__, kcontrol->id.name);
  1990. } else {
  1991. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1992. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1993. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1994. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1995. ucontrol->value.enumerated.item[0]);
  1996. }
  1997. return ret;
  1998. }
  1999. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2000. struct snd_ctl_elem_value *ucontrol)
  2001. {
  2002. struct tdm_port port;
  2003. int ret = tdm_get_port_idx(kcontrol, &port);
  2004. if (ret) {
  2005. pr_err("%s: unsupported control: %s",
  2006. __func__, kcontrol->id.name);
  2007. } else {
  2008. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2009. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2010. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2011. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2012. ucontrol->value.enumerated.item[0]);
  2013. }
  2014. return ret;
  2015. }
  2016. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2017. struct snd_ctl_elem_value *ucontrol)
  2018. {
  2019. struct tdm_port port;
  2020. int ret = tdm_get_port_idx(kcontrol, &port);
  2021. if (ret) {
  2022. pr_err("%s: unsupported control: %s",
  2023. __func__, kcontrol->id.name);
  2024. } else {
  2025. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2026. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2027. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2028. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2029. ucontrol->value.enumerated.item[0]);
  2030. }
  2031. return ret;
  2032. }
  2033. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2034. struct snd_ctl_elem_value *ucontrol)
  2035. {
  2036. struct tdm_port port;
  2037. int ret = tdm_get_port_idx(kcontrol, &port);
  2038. if (ret) {
  2039. pr_err("%s: unsupported control: %s",
  2040. __func__, kcontrol->id.name);
  2041. } else {
  2042. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2043. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2044. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2045. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2046. ucontrol->value.enumerated.item[0]);
  2047. }
  2048. return ret;
  2049. }
  2050. static int tdm_get_format(int value)
  2051. {
  2052. int format = 0;
  2053. switch (value) {
  2054. case 0:
  2055. format = SNDRV_PCM_FORMAT_S16_LE;
  2056. break;
  2057. case 1:
  2058. format = SNDRV_PCM_FORMAT_S24_LE;
  2059. break;
  2060. case 2:
  2061. format = SNDRV_PCM_FORMAT_S32_LE;
  2062. break;
  2063. default:
  2064. format = SNDRV_PCM_FORMAT_S16_LE;
  2065. break;
  2066. }
  2067. return format;
  2068. }
  2069. static int tdm_get_format_val(int format)
  2070. {
  2071. int value = 0;
  2072. switch (format) {
  2073. case SNDRV_PCM_FORMAT_S16_LE:
  2074. value = 0;
  2075. break;
  2076. case SNDRV_PCM_FORMAT_S24_LE:
  2077. value = 1;
  2078. break;
  2079. case SNDRV_PCM_FORMAT_S32_LE:
  2080. value = 2;
  2081. break;
  2082. default:
  2083. value = 0;
  2084. break;
  2085. }
  2086. return value;
  2087. }
  2088. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2089. struct snd_ctl_elem_value *ucontrol)
  2090. {
  2091. struct tdm_port port;
  2092. int ret = tdm_get_port_idx(kcontrol, &port);
  2093. if (ret) {
  2094. pr_err("%s: unsupported control: %s",
  2095. __func__, kcontrol->id.name);
  2096. } else {
  2097. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2098. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2099. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2100. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2101. ucontrol->value.enumerated.item[0]);
  2102. }
  2103. return ret;
  2104. }
  2105. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2106. struct snd_ctl_elem_value *ucontrol)
  2107. {
  2108. struct tdm_port port;
  2109. int ret = tdm_get_port_idx(kcontrol, &port);
  2110. if (ret) {
  2111. pr_err("%s: unsupported control: %s",
  2112. __func__, kcontrol->id.name);
  2113. } else {
  2114. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2115. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2116. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2117. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2118. ucontrol->value.enumerated.item[0]);
  2119. }
  2120. return ret;
  2121. }
  2122. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2123. struct snd_ctl_elem_value *ucontrol)
  2124. {
  2125. struct tdm_port port;
  2126. int ret = tdm_get_port_idx(kcontrol, &port);
  2127. if (ret) {
  2128. pr_err("%s: unsupported control: %s",
  2129. __func__, kcontrol->id.name);
  2130. } else {
  2131. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2132. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2133. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2134. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2135. ucontrol->value.enumerated.item[0]);
  2136. }
  2137. return ret;
  2138. }
  2139. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2140. struct snd_ctl_elem_value *ucontrol)
  2141. {
  2142. struct tdm_port port;
  2143. int ret = tdm_get_port_idx(kcontrol, &port);
  2144. if (ret) {
  2145. pr_err("%s: unsupported control: %s",
  2146. __func__, kcontrol->id.name);
  2147. } else {
  2148. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2149. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2150. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2151. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2152. ucontrol->value.enumerated.item[0]);
  2153. }
  2154. return ret;
  2155. }
  2156. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2157. struct snd_ctl_elem_value *ucontrol)
  2158. {
  2159. struct tdm_port port;
  2160. int ret = tdm_get_port_idx(kcontrol, &port);
  2161. if (ret) {
  2162. pr_err("%s: unsupported control: %s",
  2163. __func__, kcontrol->id.name);
  2164. } else {
  2165. ucontrol->value.enumerated.item[0] =
  2166. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2167. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2168. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2169. ucontrol->value.enumerated.item[0]);
  2170. }
  2171. return ret;
  2172. }
  2173. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2174. struct snd_ctl_elem_value *ucontrol)
  2175. {
  2176. struct tdm_port port;
  2177. int ret = tdm_get_port_idx(kcontrol, &port);
  2178. if (ret) {
  2179. pr_err("%s: unsupported control: %s",
  2180. __func__, kcontrol->id.name);
  2181. } else {
  2182. tdm_rx_cfg[port.mode][port.channel].channels =
  2183. ucontrol->value.enumerated.item[0] + 1;
  2184. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2185. tdm_rx_cfg[port.mode][port.channel].channels,
  2186. ucontrol->value.enumerated.item[0] + 1);
  2187. }
  2188. return ret;
  2189. }
  2190. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2191. struct snd_ctl_elem_value *ucontrol)
  2192. {
  2193. struct tdm_port port;
  2194. int ret = tdm_get_port_idx(kcontrol, &port);
  2195. if (ret) {
  2196. pr_err("%s: unsupported control: %s",
  2197. __func__, kcontrol->id.name);
  2198. } else {
  2199. ucontrol->value.enumerated.item[0] =
  2200. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2201. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2202. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2203. ucontrol->value.enumerated.item[0]);
  2204. }
  2205. return ret;
  2206. }
  2207. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2208. struct snd_ctl_elem_value *ucontrol)
  2209. {
  2210. struct tdm_port port;
  2211. int ret = tdm_get_port_idx(kcontrol, &port);
  2212. if (ret) {
  2213. pr_err("%s: unsupported control: %s",
  2214. __func__, kcontrol->id.name);
  2215. } else {
  2216. tdm_tx_cfg[port.mode][port.channel].channels =
  2217. ucontrol->value.enumerated.item[0] + 1;
  2218. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2219. tdm_tx_cfg[port.mode][port.channel].channels,
  2220. ucontrol->value.enumerated.item[0] + 1);
  2221. }
  2222. return ret;
  2223. }
  2224. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2225. {
  2226. int idx;
  2227. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2228. sizeof("PRIM_AUX_PCM")))
  2229. idx = PRIM_AUX_PCM;
  2230. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2231. sizeof("SEC_AUX_PCM")))
  2232. idx = SEC_AUX_PCM;
  2233. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2234. sizeof("TERT_AUX_PCM")))
  2235. idx = TERT_AUX_PCM;
  2236. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2237. sizeof("QUAT_AUX_PCM")))
  2238. idx = QUAT_AUX_PCM;
  2239. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2240. sizeof("QUIN_AUX_PCM")))
  2241. idx = QUIN_AUX_PCM;
  2242. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2243. sizeof("SENN_AUX_PCM")))
  2244. idx = SEN_AUX_PCM;
  2245. else {
  2246. pr_err("%s: unsupported port: %s",
  2247. __func__, kcontrol->id.name);
  2248. idx = -EINVAL;
  2249. }
  2250. return idx;
  2251. }
  2252. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2253. struct snd_ctl_elem_value *ucontrol)
  2254. {
  2255. int idx = aux_pcm_get_port_idx(kcontrol);
  2256. if (idx < 0)
  2257. return idx;
  2258. aux_pcm_rx_cfg[idx].sample_rate =
  2259. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2260. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2261. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2262. ucontrol->value.enumerated.item[0]);
  2263. return 0;
  2264. }
  2265. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2266. struct snd_ctl_elem_value *ucontrol)
  2267. {
  2268. int idx = aux_pcm_get_port_idx(kcontrol);
  2269. if (idx < 0)
  2270. return idx;
  2271. ucontrol->value.enumerated.item[0] =
  2272. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2273. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2274. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2275. ucontrol->value.enumerated.item[0]);
  2276. return 0;
  2277. }
  2278. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2279. struct snd_ctl_elem_value *ucontrol)
  2280. {
  2281. int idx = aux_pcm_get_port_idx(kcontrol);
  2282. if (idx < 0)
  2283. return idx;
  2284. aux_pcm_tx_cfg[idx].sample_rate =
  2285. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2286. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2287. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2288. ucontrol->value.enumerated.item[0]);
  2289. return 0;
  2290. }
  2291. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2292. struct snd_ctl_elem_value *ucontrol)
  2293. {
  2294. int idx = aux_pcm_get_port_idx(kcontrol);
  2295. if (idx < 0)
  2296. return idx;
  2297. ucontrol->value.enumerated.item[0] =
  2298. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2299. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2300. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2301. ucontrol->value.enumerated.item[0]);
  2302. return 0;
  2303. }
  2304. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2305. {
  2306. int idx;
  2307. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2308. sizeof("PRIM_MI2S_RX")))
  2309. idx = PRIM_MI2S;
  2310. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2311. sizeof("SEC_MI2S_RX")))
  2312. idx = SEC_MI2S;
  2313. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2314. sizeof("TERT_MI2S_RX")))
  2315. idx = TERT_MI2S;
  2316. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2317. sizeof("QUAT_MI2S_RX")))
  2318. idx = QUAT_MI2S;
  2319. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2320. sizeof("QUIN_MI2S_RX")))
  2321. idx = QUIN_MI2S;
  2322. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2323. sizeof("SEN_MI2S_RX")))
  2324. idx = SEN_MI2S;
  2325. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2326. sizeof("PRIM_MI2S_TX")))
  2327. idx = PRIM_MI2S;
  2328. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2329. sizeof("SEC_MI2S_TX")))
  2330. idx = SEC_MI2S;
  2331. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2332. sizeof("TERT_MI2S_TX")))
  2333. idx = TERT_MI2S;
  2334. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2335. sizeof("QUAT_MI2S_TX")))
  2336. idx = QUAT_MI2S;
  2337. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2338. sizeof("QUIN_MI2S_TX")))
  2339. idx = QUIN_MI2S;
  2340. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2341. sizeof("SEN_MI2S_TX")))
  2342. idx = SEN_MI2S;
  2343. else {
  2344. pr_err("%s: unsupported channel: %s",
  2345. __func__, kcontrol->id.name);
  2346. idx = -EINVAL;
  2347. }
  2348. return idx;
  2349. }
  2350. static int mi2s_get_sample_rate_val(int sample_rate)
  2351. {
  2352. int sample_rate_val;
  2353. switch (sample_rate) {
  2354. case SAMPLING_RATE_8KHZ:
  2355. sample_rate_val = 0;
  2356. break;
  2357. case SAMPLING_RATE_11P025KHZ:
  2358. sample_rate_val = 1;
  2359. break;
  2360. case SAMPLING_RATE_16KHZ:
  2361. sample_rate_val = 2;
  2362. break;
  2363. case SAMPLING_RATE_22P05KHZ:
  2364. sample_rate_val = 3;
  2365. break;
  2366. case SAMPLING_RATE_32KHZ:
  2367. sample_rate_val = 4;
  2368. break;
  2369. case SAMPLING_RATE_44P1KHZ:
  2370. sample_rate_val = 5;
  2371. break;
  2372. case SAMPLING_RATE_48KHZ:
  2373. sample_rate_val = 6;
  2374. break;
  2375. case SAMPLING_RATE_96KHZ:
  2376. sample_rate_val = 7;
  2377. break;
  2378. case SAMPLING_RATE_192KHZ:
  2379. sample_rate_val = 8;
  2380. break;
  2381. case SAMPLING_RATE_384KHZ:
  2382. sample_rate_val = 9;
  2383. break;
  2384. default:
  2385. sample_rate_val = 6;
  2386. break;
  2387. }
  2388. return sample_rate_val;
  2389. }
  2390. static int mi2s_get_sample_rate(int value)
  2391. {
  2392. int sample_rate;
  2393. switch (value) {
  2394. case 0:
  2395. sample_rate = SAMPLING_RATE_8KHZ;
  2396. break;
  2397. case 1:
  2398. sample_rate = SAMPLING_RATE_11P025KHZ;
  2399. break;
  2400. case 2:
  2401. sample_rate = SAMPLING_RATE_16KHZ;
  2402. break;
  2403. case 3:
  2404. sample_rate = SAMPLING_RATE_22P05KHZ;
  2405. break;
  2406. case 4:
  2407. sample_rate = SAMPLING_RATE_32KHZ;
  2408. break;
  2409. case 5:
  2410. sample_rate = SAMPLING_RATE_44P1KHZ;
  2411. break;
  2412. case 6:
  2413. sample_rate = SAMPLING_RATE_48KHZ;
  2414. break;
  2415. case 7:
  2416. sample_rate = SAMPLING_RATE_96KHZ;
  2417. break;
  2418. case 8:
  2419. sample_rate = SAMPLING_RATE_192KHZ;
  2420. break;
  2421. case 9:
  2422. sample_rate = SAMPLING_RATE_384KHZ;
  2423. break;
  2424. default:
  2425. sample_rate = SAMPLING_RATE_48KHZ;
  2426. break;
  2427. }
  2428. return sample_rate;
  2429. }
  2430. static int mi2s_auxpcm_get_format(int value)
  2431. {
  2432. int format;
  2433. switch (value) {
  2434. case 0:
  2435. format = SNDRV_PCM_FORMAT_S16_LE;
  2436. break;
  2437. case 1:
  2438. format = SNDRV_PCM_FORMAT_S24_LE;
  2439. break;
  2440. case 2:
  2441. format = SNDRV_PCM_FORMAT_S24_3LE;
  2442. break;
  2443. case 3:
  2444. format = SNDRV_PCM_FORMAT_S32_LE;
  2445. break;
  2446. default:
  2447. format = SNDRV_PCM_FORMAT_S16_LE;
  2448. break;
  2449. }
  2450. return format;
  2451. }
  2452. static int mi2s_auxpcm_get_format_value(int format)
  2453. {
  2454. int value;
  2455. switch (format) {
  2456. case SNDRV_PCM_FORMAT_S16_LE:
  2457. value = 0;
  2458. break;
  2459. case SNDRV_PCM_FORMAT_S24_LE:
  2460. value = 1;
  2461. break;
  2462. case SNDRV_PCM_FORMAT_S24_3LE:
  2463. value = 2;
  2464. break;
  2465. case SNDRV_PCM_FORMAT_S32_LE:
  2466. value = 3;
  2467. break;
  2468. default:
  2469. value = 0;
  2470. break;
  2471. }
  2472. return value;
  2473. }
  2474. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2475. struct snd_ctl_elem_value *ucontrol)
  2476. {
  2477. int idx = mi2s_get_port_idx(kcontrol);
  2478. if (idx < 0)
  2479. return idx;
  2480. mi2s_rx_cfg[idx].sample_rate =
  2481. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2482. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2483. idx, mi2s_rx_cfg[idx].sample_rate,
  2484. ucontrol->value.enumerated.item[0]);
  2485. return 0;
  2486. }
  2487. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2488. struct snd_ctl_elem_value *ucontrol)
  2489. {
  2490. int idx = mi2s_get_port_idx(kcontrol);
  2491. if (idx < 0)
  2492. return idx;
  2493. ucontrol->value.enumerated.item[0] =
  2494. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2495. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2496. idx, mi2s_rx_cfg[idx].sample_rate,
  2497. ucontrol->value.enumerated.item[0]);
  2498. return 0;
  2499. }
  2500. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2501. struct snd_ctl_elem_value *ucontrol)
  2502. {
  2503. int idx = mi2s_get_port_idx(kcontrol);
  2504. if (idx < 0)
  2505. return idx;
  2506. mi2s_tx_cfg[idx].sample_rate =
  2507. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2508. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2509. idx, mi2s_tx_cfg[idx].sample_rate,
  2510. ucontrol->value.enumerated.item[0]);
  2511. return 0;
  2512. }
  2513. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2514. struct snd_ctl_elem_value *ucontrol)
  2515. {
  2516. int idx = mi2s_get_port_idx(kcontrol);
  2517. if (idx < 0)
  2518. return idx;
  2519. ucontrol->value.enumerated.item[0] =
  2520. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2521. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2522. idx, mi2s_tx_cfg[idx].sample_rate,
  2523. ucontrol->value.enumerated.item[0]);
  2524. return 0;
  2525. }
  2526. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2527. struct snd_ctl_elem_value *ucontrol)
  2528. {
  2529. int idx = mi2s_get_port_idx(kcontrol);
  2530. if (idx < 0)
  2531. return idx;
  2532. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2533. idx, mi2s_rx_cfg[idx].channels);
  2534. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2535. return 0;
  2536. }
  2537. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2538. struct snd_ctl_elem_value *ucontrol)
  2539. {
  2540. int idx = mi2s_get_port_idx(kcontrol);
  2541. if (idx < 0)
  2542. return idx;
  2543. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2544. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2545. idx, mi2s_rx_cfg[idx].channels);
  2546. return 1;
  2547. }
  2548. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2549. struct snd_ctl_elem_value *ucontrol)
  2550. {
  2551. int idx = mi2s_get_port_idx(kcontrol);
  2552. if (idx < 0)
  2553. return idx;
  2554. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2555. idx, mi2s_tx_cfg[idx].channels);
  2556. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2557. return 0;
  2558. }
  2559. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2560. struct snd_ctl_elem_value *ucontrol)
  2561. {
  2562. int idx = mi2s_get_port_idx(kcontrol);
  2563. if (idx < 0)
  2564. return idx;
  2565. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2566. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2567. idx, mi2s_tx_cfg[idx].channels);
  2568. return 1;
  2569. }
  2570. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2571. struct snd_ctl_elem_value *ucontrol)
  2572. {
  2573. int idx = mi2s_get_port_idx(kcontrol);
  2574. if (idx < 0)
  2575. return idx;
  2576. ucontrol->value.enumerated.item[0] =
  2577. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2578. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2579. idx, mi2s_rx_cfg[idx].bit_format,
  2580. ucontrol->value.enumerated.item[0]);
  2581. return 0;
  2582. }
  2583. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2584. struct snd_ctl_elem_value *ucontrol)
  2585. {
  2586. struct msm_asoc_mach_data *pdata = NULL;
  2587. struct snd_soc_component *component = NULL;
  2588. struct snd_soc_card *card = NULL;
  2589. int idx = mi2s_get_port_idx(kcontrol);
  2590. component = snd_soc_kcontrol_component(kcontrol);
  2591. card = kcontrol->private_data;
  2592. pdata = snd_soc_card_get_drvdata(card);
  2593. if (idx < 0)
  2594. return idx;
  2595. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2596. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2597. {
  2598. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2599. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2600. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2601. ucontrol->value.enumerated.item[0]);
  2602. } else {
  2603. mi2s_rx_cfg[idx].bit_format =
  2604. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2605. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2606. idx, mi2s_rx_cfg[idx].bit_format,
  2607. ucontrol->value.enumerated.item[0]);
  2608. }
  2609. return 0;
  2610. }
  2611. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2612. struct snd_ctl_elem_value *ucontrol)
  2613. {
  2614. int idx = mi2s_get_port_idx(kcontrol);
  2615. if (idx < 0)
  2616. return idx;
  2617. ucontrol->value.enumerated.item[0] =
  2618. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2619. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2620. idx, mi2s_tx_cfg[idx].bit_format,
  2621. ucontrol->value.enumerated.item[0]);
  2622. return 0;
  2623. }
  2624. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2625. struct snd_ctl_elem_value *ucontrol)
  2626. {
  2627. int idx = mi2s_get_port_idx(kcontrol);
  2628. if (idx < 0)
  2629. return idx;
  2630. mi2s_tx_cfg[idx].bit_format =
  2631. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2632. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2633. idx, mi2s_tx_cfg[idx].bit_format,
  2634. ucontrol->value.enumerated.item[0]);
  2635. return 0;
  2636. }
  2637. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2638. struct snd_ctl_elem_value *ucontrol)
  2639. {
  2640. int idx = aux_pcm_get_port_idx(kcontrol);
  2641. if (idx < 0)
  2642. return idx;
  2643. ucontrol->value.enumerated.item[0] =
  2644. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2645. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2646. idx, aux_pcm_rx_cfg[idx].bit_format,
  2647. ucontrol->value.enumerated.item[0]);
  2648. return 0;
  2649. }
  2650. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2651. struct snd_ctl_elem_value *ucontrol)
  2652. {
  2653. int idx = aux_pcm_get_port_idx(kcontrol);
  2654. if (idx < 0)
  2655. return idx;
  2656. aux_pcm_rx_cfg[idx].bit_format =
  2657. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2658. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2659. idx, aux_pcm_rx_cfg[idx].bit_format,
  2660. ucontrol->value.enumerated.item[0]);
  2661. return 0;
  2662. }
  2663. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2664. struct snd_ctl_elem_value *ucontrol)
  2665. {
  2666. int idx = aux_pcm_get_port_idx(kcontrol);
  2667. if (idx < 0)
  2668. return idx;
  2669. ucontrol->value.enumerated.item[0] =
  2670. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2671. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2672. idx, aux_pcm_tx_cfg[idx].bit_format,
  2673. ucontrol->value.enumerated.item[0]);
  2674. return 0;
  2675. }
  2676. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2677. struct snd_ctl_elem_value *ucontrol)
  2678. {
  2679. int idx = aux_pcm_get_port_idx(kcontrol);
  2680. if (idx < 0)
  2681. return idx;
  2682. aux_pcm_tx_cfg[idx].bit_format =
  2683. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2684. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2685. idx, aux_pcm_tx_cfg[idx].bit_format,
  2686. ucontrol->value.enumerated.item[0]);
  2687. return 0;
  2688. }
  2689. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2690. {
  2691. int idx;
  2692. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2693. sizeof("PRIM_SPDIF_RX")))
  2694. idx = PRIM_SPDIF_RX;
  2695. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2696. sizeof("SEC_SPDIF_RX")))
  2697. idx = SEC_SPDIF_RX;
  2698. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2699. sizeof("PRIM_SPDIF_TX")))
  2700. idx = PRIM_SPDIF_TX;
  2701. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2702. sizeof("SEC_SPDIF_TX")))
  2703. idx = SEC_SPDIF_TX;
  2704. else {
  2705. pr_err("%s: unsupported channel: %s",
  2706. __func__, kcontrol->id.name);
  2707. idx = -EINVAL;
  2708. }
  2709. return idx;
  2710. }
  2711. static int spdif_get_sample_rate_val(int sample_rate)
  2712. {
  2713. int sample_rate_val;
  2714. switch (sample_rate) {
  2715. case SAMPLING_RATE_32KHZ:
  2716. sample_rate_val = 0;
  2717. break;
  2718. case SAMPLING_RATE_44P1KHZ:
  2719. sample_rate_val = 1;
  2720. break;
  2721. case SAMPLING_RATE_48KHZ:
  2722. sample_rate_val = 2;
  2723. break;
  2724. case SAMPLING_RATE_88P2KHZ:
  2725. sample_rate_val = 3;
  2726. break;
  2727. case SAMPLING_RATE_96KHZ:
  2728. sample_rate_val = 4;
  2729. break;
  2730. case SAMPLING_RATE_176P4KHZ:
  2731. sample_rate_val = 5;
  2732. break;
  2733. case SAMPLING_RATE_192KHZ:
  2734. sample_rate_val = 6;
  2735. break;
  2736. default:
  2737. sample_rate_val = 2;
  2738. break;
  2739. }
  2740. return sample_rate_val;
  2741. }
  2742. static int spdif_get_sample_rate(int value)
  2743. {
  2744. int sample_rate;
  2745. switch (value) {
  2746. case 0:
  2747. sample_rate = SAMPLING_RATE_32KHZ;
  2748. break;
  2749. case 1:
  2750. sample_rate = SAMPLING_RATE_44P1KHZ;
  2751. break;
  2752. case 2:
  2753. sample_rate = SAMPLING_RATE_48KHZ;
  2754. break;
  2755. case 3:
  2756. sample_rate = SAMPLING_RATE_88P2KHZ;
  2757. break;
  2758. case 4:
  2759. sample_rate = SAMPLING_RATE_96KHZ;
  2760. break;
  2761. case 5:
  2762. sample_rate = SAMPLING_RATE_176P4KHZ;
  2763. break;
  2764. case 6:
  2765. sample_rate = SAMPLING_RATE_192KHZ;
  2766. break;
  2767. default:
  2768. sample_rate = SAMPLING_RATE_48KHZ;
  2769. break;
  2770. }
  2771. return sample_rate;
  2772. }
  2773. static int spdif_get_format(int value)
  2774. {
  2775. int format;
  2776. switch (value) {
  2777. case 0:
  2778. format = SNDRV_PCM_FORMAT_S16_LE;
  2779. break;
  2780. case 1:
  2781. format = SNDRV_PCM_FORMAT_S24_LE;
  2782. break;
  2783. default:
  2784. format = SNDRV_PCM_FORMAT_S16_LE;
  2785. break;
  2786. }
  2787. return format;
  2788. }
  2789. static int spdif_get_format_value(int format)
  2790. {
  2791. int value;
  2792. switch (format) {
  2793. case SNDRV_PCM_FORMAT_S16_LE:
  2794. value = 0;
  2795. break;
  2796. case SNDRV_PCM_FORMAT_S24_LE:
  2797. value = 1;
  2798. break;
  2799. default:
  2800. value = 0;
  2801. break;
  2802. }
  2803. return value;
  2804. }
  2805. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2806. struct snd_ctl_elem_value *ucontrol)
  2807. {
  2808. int idx = spdif_get_port_idx(kcontrol);
  2809. if (idx < 0)
  2810. return idx;
  2811. spdif_rx_cfg[idx].sample_rate =
  2812. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2813. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2814. idx, spdif_rx_cfg[idx].sample_rate,
  2815. ucontrol->value.enumerated.item[0]);
  2816. return 0;
  2817. }
  2818. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2819. struct snd_ctl_elem_value *ucontrol)
  2820. {
  2821. int idx = spdif_get_port_idx(kcontrol);
  2822. if (idx < 0)
  2823. return idx;
  2824. ucontrol->value.enumerated.item[0] =
  2825. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2826. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2827. idx, spdif_rx_cfg[idx].sample_rate,
  2828. ucontrol->value.enumerated.item[0]);
  2829. return 0;
  2830. }
  2831. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2832. struct snd_ctl_elem_value *ucontrol)
  2833. {
  2834. int idx = spdif_get_port_idx(kcontrol);
  2835. if (idx < 0)
  2836. return idx;
  2837. spdif_tx_cfg[idx].sample_rate =
  2838. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2839. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2840. idx, spdif_tx_cfg[idx].sample_rate,
  2841. ucontrol->value.enumerated.item[0]);
  2842. return 0;
  2843. }
  2844. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2845. struct snd_ctl_elem_value *ucontrol)
  2846. {
  2847. int idx = spdif_get_port_idx(kcontrol);
  2848. if (idx < 0)
  2849. return idx;
  2850. ucontrol->value.enumerated.item[0] =
  2851. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2852. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2853. idx, spdif_tx_cfg[idx].sample_rate,
  2854. ucontrol->value.enumerated.item[0]);
  2855. return 0;
  2856. }
  2857. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2858. struct snd_ctl_elem_value *ucontrol)
  2859. {
  2860. int idx = spdif_get_port_idx(kcontrol);
  2861. if (idx < 0)
  2862. return idx;
  2863. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2864. idx, spdif_rx_cfg[idx].channels);
  2865. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2866. return 0;
  2867. }
  2868. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2869. struct snd_ctl_elem_value *ucontrol)
  2870. {
  2871. int idx = spdif_get_port_idx(kcontrol);
  2872. if (idx < 0)
  2873. return idx;
  2874. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2875. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2876. idx, spdif_rx_cfg[idx].channels);
  2877. return 1;
  2878. }
  2879. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2880. struct snd_ctl_elem_value *ucontrol)
  2881. {
  2882. int idx = spdif_get_port_idx(kcontrol);
  2883. if (idx < 0)
  2884. return idx;
  2885. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2886. idx, spdif_tx_cfg[idx].channels);
  2887. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2888. return 0;
  2889. }
  2890. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2891. struct snd_ctl_elem_value *ucontrol)
  2892. {
  2893. int idx = spdif_get_port_idx(kcontrol);
  2894. if (idx < 0)
  2895. return idx;
  2896. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2897. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2898. idx, spdif_tx_cfg[idx].channels);
  2899. return 1;
  2900. }
  2901. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2902. struct snd_ctl_elem_value *ucontrol)
  2903. {
  2904. int idx = spdif_get_port_idx(kcontrol);
  2905. if (idx < 0)
  2906. return idx;
  2907. ucontrol->value.enumerated.item[0] =
  2908. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2909. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2910. idx, spdif_rx_cfg[idx].bit_format,
  2911. ucontrol->value.enumerated.item[0]);
  2912. return 0;
  2913. }
  2914. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2915. struct snd_ctl_elem_value *ucontrol)
  2916. {
  2917. int idx = spdif_get_port_idx(kcontrol);
  2918. if (idx < 0)
  2919. return idx;
  2920. spdif_rx_cfg[idx].bit_format =
  2921. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2922. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2923. idx, spdif_rx_cfg[idx].bit_format,
  2924. ucontrol->value.enumerated.item[0]);
  2925. return 0;
  2926. }
  2927. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2928. struct snd_ctl_elem_value *ucontrol)
  2929. {
  2930. int idx = spdif_get_port_idx(kcontrol);
  2931. if (idx < 0)
  2932. return idx;
  2933. ucontrol->value.enumerated.item[0] =
  2934. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2935. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2936. idx, spdif_tx_cfg[idx].bit_format,
  2937. ucontrol->value.enumerated.item[0]);
  2938. return 0;
  2939. }
  2940. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2941. struct snd_ctl_elem_value *ucontrol)
  2942. {
  2943. int idx = spdif_get_port_idx(kcontrol);
  2944. if (idx < 0)
  2945. return idx;
  2946. spdif_tx_cfg[idx].bit_format =
  2947. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2948. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2949. idx, spdif_tx_cfg[idx].bit_format,
  2950. ucontrol->value.enumerated.item[0]);
  2951. return 0;
  2952. }
  2953. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2954. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2955. slim_rx_ch_get, slim_rx_ch_put),
  2956. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2957. slim_rx_ch_get, slim_rx_ch_put),
  2958. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2959. slim_tx_ch_get, slim_tx_ch_put),
  2960. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2961. slim_tx_ch_get, slim_tx_ch_put),
  2962. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2963. slim_rx_ch_get, slim_rx_ch_put),
  2964. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2965. slim_rx_ch_get, slim_rx_ch_put),
  2966. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2967. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2968. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2969. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2970. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2971. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2972. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2973. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2974. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2975. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2976. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2977. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2979. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2980. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2981. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2982. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2983. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2984. };
  2985. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2986. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2987. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2988. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2989. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2990. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2991. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2992. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2993. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2994. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2995. va_cdc_dma_tx_0_sample_rate,
  2996. cdc_dma_tx_sample_rate_get,
  2997. cdc_dma_tx_sample_rate_put),
  2998. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2999. va_cdc_dma_tx_1_sample_rate,
  3000. cdc_dma_tx_sample_rate_get,
  3001. cdc_dma_tx_sample_rate_put),
  3002. };
  3003. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3004. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3005. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3006. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3007. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3008. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3009. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3010. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3011. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3012. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3013. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3014. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3015. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3016. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3017. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3018. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3019. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3020. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3021. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3022. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3023. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3024. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3025. wsa_cdc_dma_rx_0_sample_rate,
  3026. cdc_dma_rx_sample_rate_get,
  3027. cdc_dma_rx_sample_rate_put),
  3028. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3029. wsa_cdc_dma_rx_1_sample_rate,
  3030. cdc_dma_rx_sample_rate_get,
  3031. cdc_dma_rx_sample_rate_put),
  3032. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3033. wsa_cdc_dma_tx_0_sample_rate,
  3034. cdc_dma_tx_sample_rate_get,
  3035. cdc_dma_tx_sample_rate_put),
  3036. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3037. wsa_cdc_dma_tx_1_sample_rate,
  3038. cdc_dma_tx_sample_rate_get,
  3039. cdc_dma_tx_sample_rate_put),
  3040. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3041. wsa_cdc_dma_tx_2_sample_rate,
  3042. cdc_dma_tx_sample_rate_get,
  3043. cdc_dma_tx_sample_rate_put),
  3044. };
  3045. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3046. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3047. msm_bt_sample_rate_sink_get,
  3048. msm_bt_sample_rate_sink_put),
  3049. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3050. msm_bt_sample_rate_get,
  3051. msm_bt_sample_rate_put),
  3052. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3053. msm_bt_sample_rate_get,
  3054. msm_bt_sample_rate_put),
  3055. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3056. proxy_rx_ch_get, proxy_rx_ch_put),
  3057. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3058. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3059. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3060. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3061. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3062. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3063. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3064. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3065. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3066. usb_audio_rx_sample_rate_get,
  3067. usb_audio_rx_sample_rate_put),
  3068. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3069. usb_audio_tx_sample_rate_get,
  3070. usb_audio_tx_sample_rate_put),
  3071. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3072. tdm_rx_sample_rate_get,
  3073. tdm_rx_sample_rate_put),
  3074. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3075. tdm_tx_sample_rate_get,
  3076. tdm_tx_sample_rate_put),
  3077. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3078. tdm_rx_format_get,
  3079. tdm_rx_format_put),
  3080. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3081. tdm_tx_format_get,
  3082. tdm_tx_format_put),
  3083. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3084. tdm_rx_ch_get,
  3085. tdm_rx_ch_put),
  3086. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3087. tdm_tx_ch_get,
  3088. tdm_tx_ch_put),
  3089. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3090. tdm_rx_sample_rate_get,
  3091. tdm_rx_sample_rate_put),
  3092. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3093. tdm_tx_sample_rate_get,
  3094. tdm_tx_sample_rate_put),
  3095. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3096. tdm_rx_format_get,
  3097. tdm_rx_format_put),
  3098. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3099. tdm_tx_format_get,
  3100. tdm_tx_format_put),
  3101. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3102. tdm_rx_ch_get,
  3103. tdm_rx_ch_put),
  3104. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3105. tdm_tx_ch_get,
  3106. tdm_tx_ch_put),
  3107. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3108. tdm_rx_sample_rate_get,
  3109. tdm_rx_sample_rate_put),
  3110. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3111. tdm_tx_sample_rate_get,
  3112. tdm_tx_sample_rate_put),
  3113. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3114. tdm_rx_format_get,
  3115. tdm_rx_format_put),
  3116. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3117. tdm_tx_format_get,
  3118. tdm_tx_format_put),
  3119. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3120. tdm_rx_ch_get,
  3121. tdm_rx_ch_put),
  3122. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3123. tdm_tx_ch_get,
  3124. tdm_tx_ch_put),
  3125. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3126. tdm_rx_sample_rate_get,
  3127. tdm_rx_sample_rate_put),
  3128. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3129. tdm_tx_sample_rate_get,
  3130. tdm_tx_sample_rate_put),
  3131. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3132. tdm_rx_format_get,
  3133. tdm_rx_format_put),
  3134. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3135. tdm_tx_format_get,
  3136. tdm_tx_format_put),
  3137. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3138. tdm_rx_ch_get,
  3139. tdm_rx_ch_put),
  3140. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3141. tdm_tx_ch_get,
  3142. tdm_tx_ch_put),
  3143. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3144. tdm_rx_sample_rate_get,
  3145. tdm_rx_sample_rate_put),
  3146. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3147. tdm_tx_sample_rate_get,
  3148. tdm_tx_sample_rate_put),
  3149. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3150. tdm_rx_format_get,
  3151. tdm_rx_format_put),
  3152. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3153. tdm_tx_format_get,
  3154. tdm_tx_format_put),
  3155. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3156. tdm_rx_ch_get,
  3157. tdm_rx_ch_put),
  3158. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3159. tdm_tx_ch_get,
  3160. tdm_tx_ch_put),
  3161. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3162. aux_pcm_rx_sample_rate_get,
  3163. aux_pcm_rx_sample_rate_put),
  3164. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3165. aux_pcm_rx_sample_rate_get,
  3166. aux_pcm_rx_sample_rate_put),
  3167. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3168. aux_pcm_rx_sample_rate_get,
  3169. aux_pcm_rx_sample_rate_put),
  3170. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3171. aux_pcm_rx_sample_rate_get,
  3172. aux_pcm_rx_sample_rate_put),
  3173. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3174. aux_pcm_rx_sample_rate_get,
  3175. aux_pcm_rx_sample_rate_put),
  3176. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3177. aux_pcm_tx_sample_rate_get,
  3178. aux_pcm_tx_sample_rate_put),
  3179. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3180. aux_pcm_tx_sample_rate_get,
  3181. aux_pcm_tx_sample_rate_put),
  3182. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3183. aux_pcm_tx_sample_rate_get,
  3184. aux_pcm_tx_sample_rate_put),
  3185. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3186. aux_pcm_tx_sample_rate_get,
  3187. aux_pcm_tx_sample_rate_put),
  3188. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3189. aux_pcm_tx_sample_rate_get,
  3190. aux_pcm_tx_sample_rate_put),
  3191. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3192. aux_pcm_tx_sample_rate_get,
  3193. aux_pcm_tx_sample_rate_put),
  3194. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3195. mi2s_rx_sample_rate_get,
  3196. mi2s_rx_sample_rate_put),
  3197. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3198. mi2s_rx_sample_rate_get,
  3199. mi2s_rx_sample_rate_put),
  3200. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3201. mi2s_rx_sample_rate_get,
  3202. mi2s_rx_sample_rate_put),
  3203. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3204. mi2s_rx_sample_rate_get,
  3205. mi2s_rx_sample_rate_put),
  3206. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3207. mi2s_rx_sample_rate_get,
  3208. mi2s_rx_sample_rate_put),
  3209. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3210. mi2s_rx_sample_rate_get,
  3211. mi2s_rx_sample_rate_put),
  3212. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3213. mi2s_tx_sample_rate_get,
  3214. mi2s_tx_sample_rate_put),
  3215. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3216. mi2s_tx_sample_rate_get,
  3217. mi2s_tx_sample_rate_put),
  3218. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3219. mi2s_tx_sample_rate_get,
  3220. mi2s_tx_sample_rate_put),
  3221. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3222. mi2s_tx_sample_rate_get,
  3223. mi2s_tx_sample_rate_put),
  3224. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3225. mi2s_tx_sample_rate_get,
  3226. mi2s_tx_sample_rate_put),
  3227. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3228. mi2s_tx_sample_rate_get,
  3229. mi2s_tx_sample_rate_put),
  3230. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3231. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3232. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3233. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3234. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3235. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3236. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3237. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3238. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3239. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3240. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3241. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3242. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3243. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3244. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3245. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3246. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3247. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3248. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3249. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3250. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3251. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3252. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3253. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3254. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3255. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3256. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3257. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3258. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3259. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3260. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3261. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3262. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3263. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3264. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3265. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3266. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3267. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3268. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3269. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3270. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3271. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3272. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3273. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3274. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3275. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3276. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3277. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3278. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3279. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3280. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3281. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3282. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3283. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3284. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3285. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3286. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3287. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3288. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3289. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3290. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3291. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3292. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3293. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3294. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3295. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3296. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3297. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3298. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3299. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3300. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3301. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3302. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3303. msm_snd_vad_cfg_put),
  3304. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3305. msm_spdif_rx_sample_rate_get,
  3306. msm_spdif_rx_sample_rate_put),
  3307. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3308. msm_spdif_tx_sample_rate_get,
  3309. msm_spdif_tx_sample_rate_put),
  3310. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3311. msm_spdif_rx_sample_rate_get,
  3312. msm_spdif_rx_sample_rate_put),
  3313. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3314. msm_spdif_tx_sample_rate_get,
  3315. msm_spdif_tx_sample_rate_put),
  3316. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3317. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3318. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3319. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3320. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3321. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3322. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3323. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3324. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3325. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3326. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3327. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3328. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3329. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3330. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3331. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3332. };
  3333. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3334. int enable, bool dapm)
  3335. {
  3336. int ret = 0;
  3337. if (!strcmp(component.name, "tasha_codec")) {
  3338. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3339. } else {
  3340. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3341. __func__);
  3342. ret = -EINVAL;
  3343. }
  3344. return ret;
  3345. }
  3346. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  3347. int enable, bool dapm)
  3348. {
  3349. int ret = 0;
  3350. if (!strcmp(component.name, "tasha_codec")) {
  3351. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  3352. } else {
  3353. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  3354. __func__);
  3355. ret = -EINVAL;
  3356. }
  3357. return ret;
  3358. }
  3359. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3360. struct snd_kcontrol *kcontrol, int event)
  3361. {
  3362. struct snd_soc_component *component =
  3363. snd_soc_dapm_to_component(w->dapm);
  3364. pr_debug("%s: event = %d\n", __func__, event);
  3365. switch (event) {
  3366. case SND_SOC_DAPM_PRE_PMU:
  3367. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  3368. case SND_SOC_DAPM_POST_PMD:
  3369. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  3370. }
  3371. return 0;
  3372. }
  3373. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3374. struct snd_kcontrol *kcontrol, int event)
  3375. {
  3376. struct snd_soc_component *component =
  3377. snd_soc_dapm_to_component(w->dapm);
  3378. pr_debug("%s: event = %d\n", __func__, event);
  3379. switch (event) {
  3380. case SND_SOC_DAPM_PRE_PMU:
  3381. return msm_snd_enable_codec_ext_clk(component, 1, true);
  3382. case SND_SOC_DAPM_POST_PMD:
  3383. return msm_snd_enable_codec_ext_clk(component, 0, true);
  3384. }
  3385. return 0;
  3386. }
  3387. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3388. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3389. msm_mclk_event,
  3390. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3391. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3392. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3393. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3394. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3395. };
  3396. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3397. struct snd_kcontrol *kcontrol, int event)
  3398. {
  3399. struct msm_asoc_mach_data *pdata = NULL;
  3400. struct snd_soc_component *component =
  3401. snd_soc_dapm_to_component(w->dapm);
  3402. int ret = 0;
  3403. uint32_t dmic_idx;
  3404. int *dmic_gpio_cnt;
  3405. struct device_node *dmic_gpio;
  3406. char *wname;
  3407. wname = strpbrk(w->name, "01234567");
  3408. if (!wname) {
  3409. dev_err(component->dev, "%s: widget not found\n", __func__);
  3410. return -EINVAL;
  3411. }
  3412. ret = kstrtouint(wname, 10, &dmic_idx);
  3413. if (ret < 0) {
  3414. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3415. __func__);
  3416. return -EINVAL;
  3417. }
  3418. pdata = snd_soc_card_get_drvdata(component->card);
  3419. switch (dmic_idx) {
  3420. case 0:
  3421. case 1:
  3422. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3423. dmic_gpio = pdata->dmic_01_gpio_p;
  3424. break;
  3425. case 2:
  3426. case 3:
  3427. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3428. dmic_gpio = pdata->dmic_23_gpio_p;
  3429. break;
  3430. case 4:
  3431. case 5:
  3432. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3433. dmic_gpio = pdata->dmic_45_gpio_p;
  3434. break;
  3435. case 6:
  3436. case 7:
  3437. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3438. dmic_gpio = pdata->dmic_67_gpio_p;
  3439. break;
  3440. default:
  3441. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3442. __func__);
  3443. return -EINVAL;
  3444. }
  3445. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3446. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3447. switch (event) {
  3448. case SND_SOC_DAPM_PRE_PMU:
  3449. (*dmic_gpio_cnt)++;
  3450. if (*dmic_gpio_cnt == 1) {
  3451. ret = msm_cdc_pinctrl_select_active_state(
  3452. dmic_gpio);
  3453. if (ret < 0) {
  3454. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  3455. __func__, "dmic_gpio");
  3456. return ret;
  3457. }
  3458. }
  3459. break;
  3460. case SND_SOC_DAPM_POST_PMD:
  3461. (*dmic_gpio_cnt)--;
  3462. if (*dmic_gpio_cnt == 0) {
  3463. ret = msm_cdc_pinctrl_select_sleep_state(
  3464. dmic_gpio);
  3465. if (ret < 0) {
  3466. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  3467. __func__, "dmic_gpio");
  3468. return ret;
  3469. }
  3470. }
  3471. break;
  3472. default:
  3473. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  3474. __func__, event);
  3475. return -EINVAL;
  3476. }
  3477. return 0;
  3478. }
  3479. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3480. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3481. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3482. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3483. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3484. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3485. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3486. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3487. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3488. };
  3489. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3490. };
  3491. static inline int param_is_mask(int p)
  3492. {
  3493. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3494. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3495. }
  3496. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3497. int n)
  3498. {
  3499. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3500. }
  3501. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3502. unsigned int bit)
  3503. {
  3504. if (bit >= SNDRV_MASK_MAX)
  3505. return;
  3506. if (param_is_mask(n)) {
  3507. struct snd_mask *m = param_to_mask(p, n);
  3508. m->bits[0] = 0;
  3509. m->bits[1] = 0;
  3510. m->bits[bit >> 5] |= (1 << (bit & 31));
  3511. }
  3512. }
  3513. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3514. {
  3515. int ch_id = 0;
  3516. switch (be_id) {
  3517. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3518. ch_id = SLIM_RX_0;
  3519. break;
  3520. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3521. ch_id = SLIM_RX_1;
  3522. break;
  3523. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3524. ch_id = SLIM_RX_2;
  3525. break;
  3526. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3527. ch_id = SLIM_RX_3;
  3528. break;
  3529. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3530. ch_id = SLIM_RX_4;
  3531. break;
  3532. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3533. ch_id = SLIM_RX_6;
  3534. break;
  3535. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3536. ch_id = SLIM_TX_0;
  3537. break;
  3538. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3539. ch_id = SLIM_TX_3;
  3540. break;
  3541. default:
  3542. ch_id = SLIM_RX_0;
  3543. break;
  3544. }
  3545. return ch_id;
  3546. }
  3547. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3548. {
  3549. *port_id = 0xFFFF;
  3550. switch (be_id) {
  3551. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3552. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3553. break;
  3554. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3555. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3556. break;
  3557. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3558. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3559. break;
  3560. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3561. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3562. break;
  3563. default:
  3564. return -EINVAL;
  3565. }
  3566. return 0;
  3567. }
  3568. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3569. {
  3570. int idx = 0;
  3571. switch (be_id) {
  3572. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3573. idx = WSA_CDC_DMA_RX_0;
  3574. break;
  3575. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3576. idx = WSA_CDC_DMA_TX_0;
  3577. break;
  3578. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3579. idx = WSA_CDC_DMA_RX_1;
  3580. break;
  3581. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3582. idx = WSA_CDC_DMA_TX_1;
  3583. break;
  3584. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3585. idx = WSA_CDC_DMA_TX_2;
  3586. break;
  3587. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3588. idx = VA_CDC_DMA_TX_0;
  3589. break;
  3590. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3591. idx = VA_CDC_DMA_TX_1;
  3592. break;
  3593. default:
  3594. idx = VA_CDC_DMA_TX_0;
  3595. break;
  3596. }
  3597. return idx;
  3598. }
  3599. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3600. struct snd_pcm_hw_params *params)
  3601. {
  3602. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3603. struct snd_interval *rate = hw_param_interval(params,
  3604. SNDRV_PCM_HW_PARAM_RATE);
  3605. struct snd_interval *channels = hw_param_interval(params,
  3606. SNDRV_PCM_HW_PARAM_CHANNELS);
  3607. int rc = 0;
  3608. int idx;
  3609. void *config = NULL;
  3610. struct snd_soc_component *component = NULL;
  3611. pr_debug("%s: format = %d, rate = %d\n",
  3612. __func__, params_format(params), params_rate(params));
  3613. switch (dai_link->id) {
  3614. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3615. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3616. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3617. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3618. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3619. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3620. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3621. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3622. slim_rx_cfg[idx].bit_format);
  3623. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3624. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3625. break;
  3626. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3627. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3628. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3629. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3630. slim_tx_cfg[idx].bit_format);
  3631. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3632. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3633. break;
  3634. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3635. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3636. slim_tx_cfg[1].bit_format);
  3637. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3638. channels->min = channels->max = slim_tx_cfg[1].channels;
  3639. break;
  3640. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3641. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3642. SNDRV_PCM_FORMAT_S32_LE);
  3643. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3644. channels->min = channels->max = msm_vi_feed_tx_ch;
  3645. break;
  3646. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3647. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3648. slim_rx_cfg[5].bit_format);
  3649. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3650. channels->min = channels->max = slim_rx_cfg[5].channels;
  3651. break;
  3652. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3653. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  3654. if (!component) {
  3655. pr_err("%s: component is NULL\n", __func__);
  3656. return -EINVAL;
  3657. }
  3658. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3659. channels->min = channels->max = 1;
  3660. config = msm_codec_fn.get_afe_config_fn(component,
  3661. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3662. if (config) {
  3663. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3664. config, SLIMBUS_5_TX);
  3665. if (rc)
  3666. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3667. __func__, rc);
  3668. }
  3669. break;
  3670. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3671. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3672. slim_rx_cfg[SLIM_RX_7].bit_format);
  3673. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3674. channels->min = channels->max =
  3675. slim_rx_cfg[SLIM_RX_7].channels;
  3676. break;
  3677. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3678. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3679. channels->min = channels->max =
  3680. slim_tx_cfg[SLIM_TX_7].channels;
  3681. break;
  3682. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3683. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3684. channels->min = channels->max =
  3685. slim_tx_cfg[SLIM_TX_8].channels;
  3686. break;
  3687. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3689. slim_tx_cfg[SLIM_TX_9].bit_format);
  3690. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3691. channels->min = channels->max =
  3692. slim_tx_cfg[SLIM_TX_9].channels;
  3693. break;
  3694. case MSM_BACKEND_DAI_USB_RX:
  3695. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3696. usb_rx_cfg.bit_format);
  3697. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3698. channels->min = channels->max = usb_rx_cfg.channels;
  3699. break;
  3700. case MSM_BACKEND_DAI_USB_TX:
  3701. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3702. usb_tx_cfg.bit_format);
  3703. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3704. channels->min = channels->max = usb_tx_cfg.channels;
  3705. break;
  3706. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3707. channels->min = channels->max = proxy_rx_cfg.channels;
  3708. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3709. break;
  3710. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3711. channels->min = channels->max =
  3712. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3713. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3714. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3715. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3716. break;
  3717. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3718. channels->min = channels->max =
  3719. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3720. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3721. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3722. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3723. break;
  3724. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3725. channels->min = channels->max =
  3726. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3727. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3728. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3729. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3730. break;
  3731. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3732. channels->min = channels->max =
  3733. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3734. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3735. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3736. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3737. break;
  3738. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3739. channels->min = channels->max =
  3740. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3741. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3742. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3743. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3744. break;
  3745. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3746. channels->min = channels->max =
  3747. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3748. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3749. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3750. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3751. break;
  3752. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3753. channels->min = channels->max =
  3754. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3755. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3756. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3757. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3758. break;
  3759. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3760. channels->min = channels->max =
  3761. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3762. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3763. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3764. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3765. break;
  3766. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3767. channels->min = channels->max =
  3768. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3769. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3770. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3771. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3772. break;
  3773. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3774. channels->min = channels->max =
  3775. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3776. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3777. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3778. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3779. break;
  3780. case MSM_BACKEND_DAI_AUXPCM_RX:
  3781. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3782. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3783. rate->min = rate->max =
  3784. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3785. channels->min = channels->max =
  3786. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3787. break;
  3788. case MSM_BACKEND_DAI_AUXPCM_TX:
  3789. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3790. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3791. rate->min = rate->max =
  3792. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3793. channels->min = channels->max =
  3794. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3795. break;
  3796. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3797. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3798. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3799. rate->min = rate->max =
  3800. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3801. channels->min = channels->max =
  3802. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3803. break;
  3804. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3805. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3806. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3807. rate->min = rate->max =
  3808. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3809. channels->min = channels->max =
  3810. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3811. break;
  3812. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3813. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3814. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3815. rate->min = rate->max =
  3816. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3817. channels->min = channels->max =
  3818. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3819. break;
  3820. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3821. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3822. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3823. rate->min = rate->max =
  3824. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3825. channels->min = channels->max =
  3826. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3827. break;
  3828. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3829. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3830. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3831. rate->min = rate->max =
  3832. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3833. channels->min = channels->max =
  3834. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3835. break;
  3836. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3837. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3838. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3839. rate->min = rate->max =
  3840. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3841. channels->min = channels->max =
  3842. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3843. break;
  3844. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3845. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3846. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3847. rate->min = rate->max =
  3848. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3849. channels->min = channels->max =
  3850. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3851. break;
  3852. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3853. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3854. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3855. rate->min = rate->max =
  3856. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3857. channels->min = channels->max =
  3858. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3859. break;
  3860. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3861. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3862. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3863. rate->min = rate->max =
  3864. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3865. channels->min = channels->max =
  3866. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3867. break;
  3868. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3869. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3870. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3871. rate->min = rate->max =
  3872. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3873. channels->min = channels->max =
  3874. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3875. break;
  3876. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3877. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3878. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3879. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3880. channels->min = channels->max =
  3881. mi2s_rx_cfg[PRIM_MI2S].channels;
  3882. break;
  3883. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3884. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3885. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3886. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3887. channels->min = channels->max =
  3888. mi2s_tx_cfg[PRIM_MI2S].channels;
  3889. break;
  3890. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3891. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3892. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3893. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3894. channels->min = channels->max =
  3895. mi2s_rx_cfg[SEC_MI2S].channels;
  3896. break;
  3897. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3898. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3899. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3900. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3901. channels->min = channels->max =
  3902. mi2s_tx_cfg[SEC_MI2S].channels;
  3903. break;
  3904. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3905. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3906. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3907. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3908. channels->min = channels->max =
  3909. mi2s_rx_cfg[TERT_MI2S].channels;
  3910. break;
  3911. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3912. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3913. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3914. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3915. channels->min = channels->max =
  3916. mi2s_tx_cfg[TERT_MI2S].channels;
  3917. break;
  3918. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3919. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3920. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3921. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3922. channels->min = channels->max =
  3923. mi2s_rx_cfg[QUAT_MI2S].channels;
  3924. break;
  3925. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3926. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3927. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3928. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3929. channels->min = channels->max =
  3930. mi2s_tx_cfg[QUAT_MI2S].channels;
  3931. break;
  3932. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3933. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3934. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3935. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3936. channels->min = channels->max =
  3937. mi2s_rx_cfg[QUIN_MI2S].channels;
  3938. break;
  3939. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3940. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3941. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3942. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3943. channels->min = channels->max =
  3944. mi2s_tx_cfg[QUIN_MI2S].channels;
  3945. break;
  3946. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3947. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3948. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3949. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3950. channels->min = channels->max =
  3951. mi2s_rx_cfg[SEN_MI2S].channels;
  3952. break;
  3953. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3954. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3955. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3956. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3957. channels->min = channels->max =
  3958. mi2s_tx_cfg[SEN_MI2S].channels;
  3959. break;
  3960. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3961. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3962. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3963. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3964. cdc_dma_rx_cfg[idx].bit_format);
  3965. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3966. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3967. break;
  3968. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3969. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3970. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3971. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3972. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3973. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3974. cdc_dma_tx_cfg[idx].bit_format);
  3975. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3976. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3977. break;
  3978. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3979. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3980. SNDRV_PCM_FORMAT_S32_LE);
  3981. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3982. channels->min = channels->max = msm_vi_feed_tx_ch;
  3983. break;
  3984. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3985. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3986. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3987. rate->min = rate->max =
  3988. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3989. channels->min = channels->max =
  3990. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3991. break;
  3992. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3993. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3994. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3995. rate->min = rate->max =
  3996. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3997. channels->min = channels->max =
  3998. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3999. break;
  4000. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4001. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4002. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4003. rate->min = rate->max =
  4004. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4005. channels->min = channels->max =
  4006. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4007. break;
  4008. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4009. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4010. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4011. rate->min = rate->max =
  4012. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4013. channels->min = channels->max =
  4014. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4015. break;
  4016. default:
  4017. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4018. break;
  4019. }
  4020. return rc;
  4021. }
  4022. static int msm_afe_set_config(struct snd_soc_component *component)
  4023. {
  4024. int ret = 0;
  4025. void *config_data = NULL;
  4026. if (!msm_codec_fn.get_afe_config_fn) {
  4027. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4028. __func__);
  4029. return -EINVAL;
  4030. }
  4031. config_data = msm_codec_fn.get_afe_config_fn(component,
  4032. AFE_CDC_REGISTERS_CONFIG);
  4033. if (config_data) {
  4034. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4035. if (ret) {
  4036. dev_err(component->dev,
  4037. "%s: Failed to set codec registers config %d\n",
  4038. __func__, ret);
  4039. return ret;
  4040. }
  4041. }
  4042. config_data = msm_codec_fn.get_afe_config_fn(component,
  4043. AFE_CDC_REGISTER_PAGE_CONFIG);
  4044. if (config_data) {
  4045. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4046. 0);
  4047. if (ret)
  4048. dev_err(component->dev,
  4049. "%s: Failed to set cdc register page config\n",
  4050. __func__);
  4051. }
  4052. config_data = msm_codec_fn.get_afe_config_fn(component,
  4053. AFE_SLIMBUS_SLAVE_CONFIG);
  4054. if (config_data) {
  4055. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4056. if (ret) {
  4057. dev_err(component->dev,
  4058. "%s: Failed to set slimbus slave config %d\n",
  4059. __func__, ret);
  4060. return ret;
  4061. }
  4062. }
  4063. return 0;
  4064. }
  4065. static void msm_afe_clear_config(void)
  4066. {
  4067. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4068. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4069. }
  4070. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4071. struct snd_card *card)
  4072. {
  4073. int ret = 0;
  4074. unsigned long timeout;
  4075. int adsp_ready = 0;
  4076. bool snd_card_online = 0;
  4077. timeout = jiffies +
  4078. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4079. do {
  4080. if (!snd_card_online) {
  4081. snd_card_online = snd_card_is_online_state(card);
  4082. pr_debug("%s: Sound card is %s\n", __func__,
  4083. snd_card_online ? "Online" : "Offline");
  4084. }
  4085. if (!adsp_ready) {
  4086. adsp_ready = q6core_is_adsp_ready();
  4087. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4088. adsp_ready ? "ready" : "not ready");
  4089. }
  4090. if (snd_card_online && adsp_ready)
  4091. break;
  4092. /*
  4093. * Sound card/ADSP will be coming up after subsystem restart and
  4094. * it might not be fully up when the control reaches
  4095. * here. So, wait for 50msec before checking ADSP state
  4096. */
  4097. msleep(50);
  4098. } while (time_after(timeout, jiffies));
  4099. if (!snd_card_online || !adsp_ready) {
  4100. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4101. __func__,
  4102. snd_card_online ? "Online" : "Offline",
  4103. adsp_ready ? "ready" : "not ready");
  4104. ret = -ETIMEDOUT;
  4105. goto err;
  4106. }
  4107. ret = msm_afe_set_config(component);
  4108. if (ret)
  4109. pr_err("%s: Failed to set AFE config. err %d\n",
  4110. __func__, ret);
  4111. return 0;
  4112. err:
  4113. return ret;
  4114. }
  4115. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4116. unsigned long opcode, void *ptr)
  4117. {
  4118. int ret;
  4119. struct snd_soc_card *card = NULL;
  4120. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4121. struct snd_soc_pcm_runtime *rtd;
  4122. struct snd_soc_dai *codec_dai;
  4123. struct snd_soc_component *component;
  4124. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4125. switch (opcode) {
  4126. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4127. /*
  4128. * Use flag to ignore initial boot notifications
  4129. * On initial boot msm_adsp_power_up_config is
  4130. * called on init. There is no need to clear
  4131. * and set the config again on initial boot.
  4132. */
  4133. if (is_initial_boot)
  4134. break;
  4135. msm_afe_clear_config();
  4136. break;
  4137. case AUDIO_NOTIFIER_SERVICE_UP:
  4138. if (is_initial_boot) {
  4139. is_initial_boot = false;
  4140. break;
  4141. }
  4142. if (!spdev)
  4143. return -EINVAL;
  4144. card = platform_get_drvdata(spdev);
  4145. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4146. if (!rtd) {
  4147. dev_err(card->dev,
  4148. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4149. __func__, be_dl_name);
  4150. ret = -EINVAL;
  4151. goto err;
  4152. }
  4153. codec_dai = rtd->codec_dai;
  4154. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4155. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4156. ret = msm_adsp_power_up_config(component, card->snd_card);
  4157. if (ret < 0) {
  4158. dev_err(card->dev,
  4159. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4160. __func__, ret);
  4161. goto err;
  4162. }
  4163. break;
  4164. default:
  4165. break;
  4166. }
  4167. err:
  4168. return NOTIFY_OK;
  4169. }
  4170. static struct notifier_block service_nb = {
  4171. .notifier_call = qcs405_notifier_service_cb,
  4172. .priority = -INT_MAX,
  4173. };
  4174. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4175. {
  4176. int ret = 0;
  4177. void *config_data;
  4178. struct snd_soc_component *component;
  4179. struct snd_soc_dapm_context *dapm;
  4180. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4181. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4182. struct snd_card *card;
  4183. struct msm_asoc_mach_data *pdata =
  4184. snd_soc_card_get_drvdata(rtd->card);
  4185. /*
  4186. * Codec SLIMBUS configuration
  4187. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4188. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4189. * TX14, TX15, TX16
  4190. */
  4191. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4192. 151, 152, 153, 154, 155, 156};
  4193. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4194. 134, 135, 136, 137, 138, 139,
  4195. 140, 141, 142, 143};
  4196. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4197. rtd->pmdown_time = 0;
  4198. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4199. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4200. dapm = snd_soc_component_get_dapm(component);
  4201. }
  4202. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4203. ARRAY_SIZE(msm_snd_sb_controls));
  4204. if (ret < 0) {
  4205. pr_err("%s: add_codec_controls failed, err %d\n",
  4206. __func__, ret);
  4207. return ret;
  4208. }
  4209. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4210. ARRAY_SIZE(msm_dapm_widgets));
  4211. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4212. ARRAY_SIZE(wcd_audio_paths));
  4213. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4214. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4215. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4216. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4217. snd_soc_dapm_sync(dapm);
  4218. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4219. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4220. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4221. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4222. if (ret) {
  4223. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4224. __func__, ret);
  4225. goto err;
  4226. }
  4227. config_data = msm_codec_fn.get_afe_config_fn(component,
  4228. AFE_AANC_VERSION);
  4229. if (config_data) {
  4230. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4231. if (ret) {
  4232. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4233. __func__, ret);
  4234. goto err;
  4235. }
  4236. }
  4237. card = rtd->card->snd_card;
  4238. if (!pdata->codec_root)
  4239. pdata->codec_root = snd_info_create_subdir(card->module,
  4240. "codecs", card->proc_root);
  4241. if (!pdata->codec_root) {
  4242. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4243. __func__);
  4244. ret = 0;
  4245. goto err;
  4246. }
  4247. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4248. codec_reg_done = true;
  4249. return 0;
  4250. err:
  4251. return ret;
  4252. }
  4253. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4254. {
  4255. int ret = 0;
  4256. struct snd_soc_component *component;
  4257. struct snd_soc_dapm_context *dapm;
  4258. struct snd_card *card;
  4259. struct msm_asoc_mach_data *pdata =
  4260. snd_soc_card_get_drvdata(rtd->card);
  4261. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4262. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4263. if (!component) {
  4264. pr_err("%s: component is NULL\n", __func__);
  4265. return -EINVAL;
  4266. }
  4267. dapm = snd_soc_component_get_dapm(component);
  4268. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4269. ARRAY_SIZE(msm_snd_va_controls));
  4270. if (ret < 0) {
  4271. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4272. __func__, ret);
  4273. return ret;
  4274. }
  4275. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4276. ARRAY_SIZE(msm_va_dapm_widgets));
  4277. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4278. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4279. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4280. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4281. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4282. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4283. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4284. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4285. snd_soc_dapm_sync(dapm);
  4286. card = rtd->card->snd_card;
  4287. if (!pdata->codec_root)
  4288. pdata->codec_root = snd_info_create_subdir(card->module,
  4289. "codecs", card->proc_root);
  4290. if (!pdata->codec_root) {
  4291. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4292. __func__);
  4293. ret = 0;
  4294. goto done;
  4295. }
  4296. bolero_info_create_codec_entry(pdata->codec_root, component);
  4297. done:
  4298. return ret;
  4299. }
  4300. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4301. {
  4302. int ret = 0;
  4303. struct snd_soc_component *component = NULL;
  4304. struct snd_soc_dapm_context *dapm = NULL;
  4305. struct snd_soc_component *aux_comp = NULL;
  4306. struct snd_card *card = NULL;
  4307. struct msm_asoc_mach_data *pdata =
  4308. snd_soc_card_get_drvdata(rtd->card);
  4309. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4310. if (!component) {
  4311. pr_err("%s: component is NULL\n", __func__);
  4312. return -EINVAL;
  4313. }
  4314. dapm = snd_soc_component_get_dapm(component);
  4315. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  4316. ARRAY_SIZE(msm_snd_wsa_controls));
  4317. if (ret < 0) {
  4318. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4319. __func__, ret);
  4320. return ret;
  4321. }
  4322. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4323. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4324. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4325. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4326. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4327. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4328. snd_soc_dapm_sync(dapm);
  4329. /*
  4330. * Send speaker configuration only for WSA8810.
  4331. * Default configuration is for WSA8815.
  4332. */
  4333. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4334. __func__, rtd->card->num_aux_devs);
  4335. if (rtd->card->num_aux_devs &&
  4336. !list_empty(&rtd->card->component_dev_list)) {
  4337. aux_comp = list_first_entry(
  4338. &rtd->card->component_dev_list,
  4339. struct snd_soc_component,
  4340. card_aux_list);
  4341. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4342. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4343. wsa_macro_set_spkr_mode(component,
  4344. WSA_MACRO_SPKR_MODE_1);
  4345. wsa_macro_set_spkr_gain_offset(component,
  4346. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4347. }
  4348. }
  4349. card = rtd->card->snd_card;
  4350. if (!pdata->codec_root)
  4351. pdata->codec_root = snd_info_create_subdir(card->module,
  4352. "codecs", card->proc_root);
  4353. if (!pdata->codec_root) {
  4354. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  4355. __func__);
  4356. ret = 0;
  4357. goto done;
  4358. }
  4359. bolero_info_create_codec_entry(pdata->codec_root, component);
  4360. done:
  4361. return ret;
  4362. }
  4363. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4364. {
  4365. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4366. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4367. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4368. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4369. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4370. }
  4371. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4372. struct snd_pcm_hw_params *params)
  4373. {
  4374. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4375. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4376. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4377. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4378. int ret = 0;
  4379. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4380. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4381. u32 user_set_tx_ch = 0;
  4382. u32 rx_ch_count;
  4383. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4384. ret = snd_soc_dai_get_channel_map(codec_dai,
  4385. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4386. if (ret < 0) {
  4387. pr_err("%s: failed to get codec chan map, err:%d\n",
  4388. __func__, ret);
  4389. goto err;
  4390. }
  4391. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4392. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4393. slim_rx_cfg[5].channels);
  4394. rx_ch_count = slim_rx_cfg[5].channels;
  4395. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4396. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4397. slim_rx_cfg[2].channels);
  4398. rx_ch_count = slim_rx_cfg[2].channels;
  4399. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4400. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4401. slim_rx_cfg[6].channels);
  4402. rx_ch_count = slim_rx_cfg[6].channels;
  4403. } else {
  4404. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4405. slim_rx_cfg[0].channels);
  4406. rx_ch_count = slim_rx_cfg[0].channels;
  4407. }
  4408. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4409. rx_ch_count, rx_ch);
  4410. if (ret < 0) {
  4411. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4412. __func__, ret);
  4413. goto err;
  4414. }
  4415. } else {
  4416. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4417. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4418. ret = snd_soc_dai_get_channel_map(codec_dai,
  4419. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4420. if (ret < 0) {
  4421. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4422. __func__, ret);
  4423. goto err;
  4424. }
  4425. /* For <codec>_tx1 case */
  4426. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4427. user_set_tx_ch = slim_tx_cfg[0].channels;
  4428. /* For <codec>_tx3 case */
  4429. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4430. user_set_tx_ch = slim_tx_cfg[1].channels;
  4431. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4432. user_set_tx_ch = msm_vi_feed_tx_ch;
  4433. else
  4434. user_set_tx_ch = tx_ch_cnt;
  4435. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4436. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4437. tx_ch_cnt, dai_link->id);
  4438. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4439. user_set_tx_ch, tx_ch, 0, 0);
  4440. if (ret < 0)
  4441. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4442. __func__, ret);
  4443. }
  4444. err:
  4445. return ret;
  4446. }
  4447. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4448. struct snd_pcm_hw_params *params)
  4449. {
  4450. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4451. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4452. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4453. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4454. int ret = 0;
  4455. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4456. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4457. u32 user_set_tx_ch = 0;
  4458. u32 user_set_rx_ch = 0;
  4459. u32 ch_id;
  4460. ret = snd_soc_dai_get_channel_map(codec_dai,
  4461. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4462. &rx_ch_cdc_dma);
  4463. if (ret < 0) {
  4464. pr_err("%s: failed to get codec chan map, err:%d\n",
  4465. __func__, ret);
  4466. goto err;
  4467. }
  4468. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4469. switch (dai_link->id) {
  4470. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4471. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4472. {
  4473. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4474. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4475. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4476. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4477. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4478. user_set_rx_ch, &rx_ch_cdc_dma);
  4479. if (ret < 0) {
  4480. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4481. __func__, ret);
  4482. goto err;
  4483. }
  4484. }
  4485. break;
  4486. }
  4487. } else {
  4488. switch (dai_link->id) {
  4489. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4490. {
  4491. user_set_tx_ch = msm_vi_feed_tx_ch;
  4492. }
  4493. break;
  4494. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4495. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4496. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4497. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4498. {
  4499. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4500. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4501. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4502. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4503. }
  4504. break;
  4505. }
  4506. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4507. &tx_ch_cdc_dma, 0, 0);
  4508. if (ret < 0) {
  4509. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4510. __func__, ret);
  4511. goto err;
  4512. }
  4513. }
  4514. err:
  4515. return ret;
  4516. }
  4517. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4518. struct snd_pcm_hw_params *params)
  4519. {
  4520. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4521. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4522. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4523. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4524. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4525. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4526. int ret;
  4527. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4528. codec_dai->name, codec_dai->id);
  4529. ret = snd_soc_dai_get_channel_map(codec_dai,
  4530. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4531. if (ret) {
  4532. dev_err(rtd->dev,
  4533. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4534. __func__, ret);
  4535. goto err;
  4536. }
  4537. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4538. __func__, tx_ch_cnt, dai_link->id);
  4539. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4540. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4541. if (ret)
  4542. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4543. __func__, ret);
  4544. err:
  4545. return ret;
  4546. }
  4547. static int msm_get_port_id(int be_id)
  4548. {
  4549. int afe_port_id;
  4550. switch (be_id) {
  4551. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4552. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4553. break;
  4554. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4555. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4556. break;
  4557. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4558. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4559. break;
  4560. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4561. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4562. break;
  4563. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4564. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4565. break;
  4566. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4567. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4568. break;
  4569. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4570. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4571. break;
  4572. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4573. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4574. break;
  4575. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4576. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4577. break;
  4578. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4579. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4580. break;
  4581. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4582. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4583. break;
  4584. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4585. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4586. break;
  4587. default:
  4588. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4589. afe_port_id = -EINVAL;
  4590. }
  4591. return afe_port_id;
  4592. }
  4593. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4594. {
  4595. u32 bit_per_sample;
  4596. switch (bit_format) {
  4597. case SNDRV_PCM_FORMAT_S32_LE:
  4598. case SNDRV_PCM_FORMAT_S24_3LE:
  4599. case SNDRV_PCM_FORMAT_S24_LE:
  4600. bit_per_sample = 32;
  4601. break;
  4602. case SNDRV_PCM_FORMAT_S16_LE:
  4603. default:
  4604. bit_per_sample = 16;
  4605. break;
  4606. }
  4607. return bit_per_sample;
  4608. }
  4609. static void update_mi2s_clk_val(int dai_id, int stream)
  4610. {
  4611. u32 bit_per_sample;
  4612. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4613. bit_per_sample =
  4614. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4615. mi2s_clk[dai_id].clk_freq_in_hz =
  4616. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4617. } else {
  4618. bit_per_sample =
  4619. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4620. mi2s_clk[dai_id].clk_freq_in_hz =
  4621. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4622. }
  4623. }
  4624. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4625. {
  4626. int ret = 0;
  4627. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4628. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4629. int port_id = 0;
  4630. int index = cpu_dai->id;
  4631. port_id = msm_get_port_id(rtd->dai_link->id);
  4632. if (port_id < 0) {
  4633. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4634. ret = port_id;
  4635. goto err;
  4636. }
  4637. if (enable) {
  4638. update_mi2s_clk_val(index, substream->stream);
  4639. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4640. mi2s_clk[index].clk_freq_in_hz);
  4641. }
  4642. mi2s_clk[index].enable = enable;
  4643. ret = afe_set_lpass_clock_v2(port_id,
  4644. &mi2s_clk[index]);
  4645. if (ret < 0) {
  4646. dev_err(rtd->card->dev,
  4647. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4648. __func__, port_id, ret);
  4649. goto err;
  4650. }
  4651. err:
  4652. return ret;
  4653. }
  4654. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4655. struct snd_pcm_hw_params *params)
  4656. {
  4657. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4658. struct snd_interval *rate = hw_param_interval(params,
  4659. SNDRV_PCM_HW_PARAM_RATE);
  4660. struct snd_interval *channels = hw_param_interval(params,
  4661. SNDRV_PCM_HW_PARAM_CHANNELS);
  4662. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4663. channels->min = channels->max =
  4664. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4665. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4666. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4667. rate->min = rate->max =
  4668. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4669. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4670. channels->min = channels->max =
  4671. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4672. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4673. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4674. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4675. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4676. channels->min = channels->max =
  4677. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4678. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4679. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4680. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4681. } else {
  4682. pr_err("%s: dai id 0x%x not supported\n",
  4683. __func__, cpu_dai->id);
  4684. return -EINVAL;
  4685. }
  4686. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4687. __func__, cpu_dai->id, channels->max, rate->max,
  4688. params_format(params));
  4689. return 0;
  4690. }
  4691. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4692. struct snd_pcm_hw_params *params)
  4693. {
  4694. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4695. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4696. int ret = 0;
  4697. int slot_width = 32;
  4698. int channels, slots = 8;
  4699. unsigned int slot_mask, rate, clk_freq;
  4700. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4701. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4702. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4703. switch (cpu_dai->id) {
  4704. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4705. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4706. break;
  4707. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4708. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4709. break;
  4710. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4711. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4712. break;
  4713. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4714. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4715. break;
  4716. case AFE_PORT_ID_QUINARY_TDM_RX:
  4717. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4718. break;
  4719. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4720. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4721. break;
  4722. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4723. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4724. break;
  4725. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4726. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4727. break;
  4728. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4729. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4730. break;
  4731. case AFE_PORT_ID_QUINARY_TDM_TX:
  4732. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4733. break;
  4734. default:
  4735. pr_err("%s: dai id 0x%x not supported\n",
  4736. __func__, cpu_dai->id);
  4737. return -EINVAL;
  4738. }
  4739. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4740. /*2 slot config - bits 0 and 1 set for the first two slots */
  4741. slot_mask = 0x0000FFFF >> (16-channels);
  4742. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4743. __func__, slot_width, slots);
  4744. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4745. slots, slot_width);
  4746. if (ret < 0) {
  4747. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4748. __func__, ret);
  4749. goto end;
  4750. }
  4751. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4752. 0, NULL, channels, slot_offset);
  4753. if (ret < 0) {
  4754. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4755. __func__, ret);
  4756. goto end;
  4757. }
  4758. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4759. /*2 slot config - bits 0 and 1 set for the first two slots */
  4760. slot_mask = 0x0000FFFF >> (16-channels);
  4761. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4762. __func__, slot_width, slots);
  4763. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4764. slots, slot_width);
  4765. if (ret < 0) {
  4766. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4767. __func__, ret);
  4768. goto end;
  4769. }
  4770. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4771. channels, slot_offset, 0, NULL);
  4772. if (ret < 0) {
  4773. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4774. __func__, ret);
  4775. goto end;
  4776. }
  4777. } else {
  4778. ret = -EINVAL;
  4779. pr_err("%s: invalid use case, err:%d\n",
  4780. __func__, ret);
  4781. goto end;
  4782. }
  4783. rate = params_rate(params);
  4784. clk_freq = rate * slot_width * slots;
  4785. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4786. if (ret < 0)
  4787. pr_err("%s: failed to set tdm clk, err:%d\n",
  4788. __func__, ret);
  4789. end:
  4790. return ret;
  4791. }
  4792. static int msm_get_tdm_mode(u32 port_id)
  4793. {
  4794. u32 tdm_mode;
  4795. switch (port_id) {
  4796. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4797. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4798. tdm_mode = TDM_PRI;
  4799. break;
  4800. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4801. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4802. tdm_mode = TDM_SEC;
  4803. break;
  4804. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4805. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4806. tdm_mode = TDM_TERT;
  4807. break;
  4808. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4809. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4810. tdm_mode = TDM_QUAT;
  4811. break;
  4812. case AFE_PORT_ID_QUINARY_TDM_RX:
  4813. case AFE_PORT_ID_QUINARY_TDM_TX:
  4814. tdm_mode = TDM_QUIN;
  4815. break;
  4816. default:
  4817. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4818. tdm_mode = -EINVAL;
  4819. }
  4820. return tdm_mode;
  4821. }
  4822. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4823. {
  4824. int ret = 0;
  4825. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4826. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4827. struct snd_soc_card *card = rtd->card;
  4828. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4829. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4830. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4831. ret = -EINVAL;
  4832. pr_err("%s: Invalid TDM interface %d\n",
  4833. __func__, ret);
  4834. return ret;
  4835. }
  4836. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4837. ret = msm_cdc_pinctrl_select_active_state(
  4838. pdata->mi2s_gpio_p[tdm_mode]);
  4839. if (ret)
  4840. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4841. __func__, ret);
  4842. }
  4843. /* Enable Mic bias for TDM Mics */
  4844. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4845. if (pdata->tdm_micb_supply) {
  4846. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4847. pdata->tdm_micb_voltage,
  4848. pdata->tdm_micb_voltage);
  4849. if (ret) {
  4850. pr_err("%s: Setting voltage failed, err = %d\n",
  4851. __func__, ret);
  4852. return ret;
  4853. }
  4854. ret = regulator_set_load(pdata->tdm_micb_supply,
  4855. pdata->tdm_micb_current);
  4856. if (ret) {
  4857. pr_err("%s: Setting current failed, err = %d\n",
  4858. __func__, ret);
  4859. return ret;
  4860. }
  4861. ret = regulator_enable(pdata->tdm_micb_supply);
  4862. if (ret) {
  4863. pr_err("%s: regulator enable failed, err = %d\n",
  4864. __func__, ret);
  4865. return ret;
  4866. }
  4867. }
  4868. }
  4869. return ret;
  4870. }
  4871. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4872. {
  4873. int ret = 0;
  4874. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4875. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4876. struct snd_soc_card *card = rtd->card;
  4877. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4878. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4879. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4880. if (pdata->tdm_micb_supply) {
  4881. ret = regulator_disable(pdata->tdm_micb_supply);
  4882. if (ret)
  4883. pr_err("%s: regulator disable failed, err = %d\n",
  4884. __func__, ret);
  4885. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4886. pdata->tdm_micb_voltage);
  4887. regulator_set_load(pdata->tdm_micb_supply, 0);
  4888. }
  4889. }
  4890. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4891. ret = msm_cdc_pinctrl_select_sleep_state(
  4892. pdata->mi2s_gpio_p[tdm_mode]);
  4893. if (ret)
  4894. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4895. __func__, ret);
  4896. }
  4897. }
  4898. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4899. .hw_params = qcs405_tdm_snd_hw_params,
  4900. .startup = qcs405_tdm_snd_startup,
  4901. .shutdown = qcs405_tdm_snd_shutdown
  4902. };
  4903. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4904. {
  4905. cpumask_t mask;
  4906. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4907. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4908. cpumask_clear(&mask);
  4909. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4910. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4911. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4912. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4913. pm_qos_add_request(&substream->latency_pm_qos_req,
  4914. PM_QOS_CPU_DMA_LATENCY,
  4915. MSM_LL_QOS_VALUE);
  4916. return 0;
  4917. }
  4918. static struct snd_soc_ops msm_fe_qos_ops = {
  4919. .prepare = msm_fe_qos_prepare,
  4920. };
  4921. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4922. {
  4923. int ret = 0;
  4924. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4925. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4926. int index = cpu_dai->id;
  4927. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4928. struct snd_soc_card *card = rtd->card;
  4929. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4930. dev_dbg(rtd->card->dev,
  4931. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4932. __func__, substream->name, substream->stream,
  4933. cpu_dai->name, cpu_dai->id);
  4934. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4935. ret = -EINVAL;
  4936. dev_err(rtd->card->dev,
  4937. "%s: CPU DAI id (%d) out of range\n",
  4938. __func__, cpu_dai->id);
  4939. goto err;
  4940. }
  4941. /*
  4942. * Mutex protection in case the same MI2S
  4943. * interface using for both TX and RX so
  4944. * that the same clock won't be enable twice.
  4945. */
  4946. mutex_lock(&mi2s_intf_conf[index].lock);
  4947. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4948. /* Check if msm needs to provide the clock to the interface */
  4949. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4950. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4951. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4952. }
  4953. ret = msm_mi2s_set_sclk(substream, true);
  4954. if (ret < 0) {
  4955. dev_err(rtd->card->dev,
  4956. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4957. __func__, ret);
  4958. goto clean_up;
  4959. }
  4960. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4961. if (ret < 0) {
  4962. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4963. __func__, index, ret);
  4964. goto clk_off;
  4965. }
  4966. if (pdata->mi2s_gpio_p[index])
  4967. msm_cdc_pinctrl_select_active_state(
  4968. pdata->mi2s_gpio_p[index]);
  4969. }
  4970. clk_off:
  4971. if (ret < 0)
  4972. msm_mi2s_set_sclk(substream, false);
  4973. clean_up:
  4974. if (ret < 0)
  4975. mi2s_intf_conf[index].ref_cnt--;
  4976. mutex_unlock(&mi2s_intf_conf[index].lock);
  4977. err:
  4978. return ret;
  4979. }
  4980. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4981. {
  4982. int ret;
  4983. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4984. int index = rtd->cpu_dai->id;
  4985. struct snd_soc_card *card = rtd->card;
  4986. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4987. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4988. substream->name, substream->stream);
  4989. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4990. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4991. return;
  4992. }
  4993. mutex_lock(&mi2s_intf_conf[index].lock);
  4994. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4995. if (pdata->mi2s_gpio_p[index])
  4996. msm_cdc_pinctrl_select_sleep_state(
  4997. pdata->mi2s_gpio_p[index]);
  4998. ret = msm_mi2s_set_sclk(substream, false);
  4999. if (ret < 0)
  5000. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5001. __func__, index, ret);
  5002. }
  5003. mutex_unlock(&mi2s_intf_conf[index].lock);
  5004. }
  5005. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5006. {
  5007. int ret = 0;
  5008. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5009. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5010. int port_id = cpu_dai->id;
  5011. struct afe_clk_set clk_cfg;
  5012. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5013. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5014. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5015. clk_cfg.enable = enable;
  5016. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5017. switch (port_id) {
  5018. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5019. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5020. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5021. clk_cfg.clk_freq_in_hz =
  5022. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5023. break;
  5024. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5025. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5026. clk_cfg.clk_freq_in_hz =
  5027. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5028. break;
  5029. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5030. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5031. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5032. break;
  5033. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5034. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5035. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5036. break;
  5037. }
  5038. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5039. if (ret < 0) {
  5040. dev_err(rtd->card->dev,
  5041. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5042. __func__, port_id, ret);
  5043. goto err;
  5044. }
  5045. /* Set NPL clock for RX in addition */
  5046. switch (port_id) {
  5047. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5048. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5049. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5050. if (ret < 0) {
  5051. dev_err(rtd->card->dev,
  5052. "%s: afe NPL failed port 0x%x, err:%d\n",
  5053. __func__, port_id, ret);
  5054. goto err;
  5055. }
  5056. break;
  5057. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5058. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5059. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5060. if (ret < 0) {
  5061. dev_err(rtd->card->dev,
  5062. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5063. __func__, port_id, ret);
  5064. goto err;
  5065. }
  5066. break;
  5067. }
  5068. if (enable) {
  5069. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5070. clk_cfg.clk_freq_in_hz);
  5071. }
  5072. err:
  5073. return ret;
  5074. }
  5075. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5076. {
  5077. int ret = 0;
  5078. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5079. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5080. int port_id = cpu_dai->id;
  5081. dev_dbg(rtd->card->dev,
  5082. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5083. __func__, substream->name, substream->stream,
  5084. cpu_dai->name, cpu_dai->id);
  5085. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5086. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5087. ret = -EINVAL;
  5088. dev_err(rtd->card->dev,
  5089. "%s: CPU DAI id (%d) out of range\n",
  5090. __func__, cpu_dai->id);
  5091. goto err;
  5092. }
  5093. ret = msm_spdif_set_clk(substream, true);
  5094. if (ret < 0) {
  5095. dev_err(rtd->card->dev,
  5096. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5097. __func__, port_id, ret);
  5098. }
  5099. err:
  5100. return ret;
  5101. }
  5102. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5103. {
  5104. int ret;
  5105. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5106. int port_id = rtd->cpu_dai->id;
  5107. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5108. substream->name, substream->stream);
  5109. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5110. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5111. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5112. return;
  5113. }
  5114. ret = msm_spdif_set_clk(substream, false);
  5115. if (ret < 0)
  5116. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5117. __func__, port_id, ret);
  5118. }
  5119. static struct snd_soc_ops msm_mi2s_be_ops = {
  5120. .startup = msm_mi2s_snd_startup,
  5121. .shutdown = msm_mi2s_snd_shutdown,
  5122. };
  5123. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5124. .hw_params = msm_snd_cdc_dma_hw_params,
  5125. };
  5126. static struct snd_soc_ops msm_be_ops = {
  5127. .hw_params = msm_snd_hw_params,
  5128. };
  5129. static struct snd_soc_ops msm_wcn_ops = {
  5130. .hw_params = msm_wcn_hw_params,
  5131. };
  5132. static struct snd_soc_ops msm_spdif_be_ops = {
  5133. .startup = msm_spdif_snd_startup,
  5134. .shutdown = msm_spdif_snd_shutdown,
  5135. };
  5136. /* Digital audio interface glue - connects codec <---> CPU */
  5137. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5138. /* FrontEnd DAI Links */
  5139. {
  5140. .name = MSM_DAILINK_NAME(Media1),
  5141. .stream_name = "MultiMedia1",
  5142. .cpu_dai_name = "MultiMedia1",
  5143. .platform_name = "msm-pcm-dsp.0",
  5144. .dynamic = 1,
  5145. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5146. .dpcm_playback = 1,
  5147. .dpcm_capture = 1,
  5148. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5149. SND_SOC_DPCM_TRIGGER_POST},
  5150. .codec_dai_name = "snd-soc-dummy-dai",
  5151. .codec_name = "snd-soc-dummy",
  5152. .ignore_suspend = 1,
  5153. /* this dainlink has playback support */
  5154. .ignore_pmdown_time = 1,
  5155. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5156. },
  5157. {
  5158. .name = MSM_DAILINK_NAME(Media2),
  5159. .stream_name = "MultiMedia2",
  5160. .cpu_dai_name = "MultiMedia2",
  5161. .platform_name = "msm-pcm-dsp.0",
  5162. .dynamic = 1,
  5163. .dpcm_playback = 1,
  5164. .dpcm_capture = 1,
  5165. .codec_dai_name = "snd-soc-dummy-dai",
  5166. .codec_name = "snd-soc-dummy",
  5167. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5168. SND_SOC_DPCM_TRIGGER_POST},
  5169. .ignore_suspend = 1,
  5170. /* this dainlink has playback support */
  5171. .ignore_pmdown_time = 1,
  5172. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5173. },
  5174. {
  5175. .name = "VoiceMMode1",
  5176. .stream_name = "VoiceMMode1",
  5177. .cpu_dai_name = "VoiceMMode1",
  5178. .platform_name = "msm-pcm-voice",
  5179. .dynamic = 1,
  5180. .dpcm_playback = 1,
  5181. .dpcm_capture = 1,
  5182. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5183. SND_SOC_DPCM_TRIGGER_POST},
  5184. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5185. .ignore_suspend = 1,
  5186. .ignore_pmdown_time = 1,
  5187. .codec_dai_name = "snd-soc-dummy-dai",
  5188. .codec_name = "snd-soc-dummy",
  5189. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5190. },
  5191. {
  5192. .name = "MSM VoIP",
  5193. .stream_name = "VoIP",
  5194. .cpu_dai_name = "VoIP",
  5195. .platform_name = "msm-voip-dsp",
  5196. .dynamic = 1,
  5197. .dpcm_playback = 1,
  5198. .dpcm_capture = 1,
  5199. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5200. SND_SOC_DPCM_TRIGGER_POST},
  5201. .codec_dai_name = "snd-soc-dummy-dai",
  5202. .codec_name = "snd-soc-dummy",
  5203. .ignore_suspend = 1,
  5204. /* this dainlink has playback support */
  5205. .ignore_pmdown_time = 1,
  5206. .id = MSM_FRONTEND_DAI_VOIP,
  5207. },
  5208. {
  5209. .name = MSM_DAILINK_NAME(ULL),
  5210. .stream_name = "MultiMedia3",
  5211. .cpu_dai_name = "MultiMedia3",
  5212. .platform_name = "msm-pcm-dsp.2",
  5213. .dynamic = 1,
  5214. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5215. .dpcm_playback = 1,
  5216. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5217. SND_SOC_DPCM_TRIGGER_POST},
  5218. .codec_dai_name = "snd-soc-dummy-dai",
  5219. .codec_name = "snd-soc-dummy",
  5220. .ignore_suspend = 1,
  5221. /* this dainlink has playback support */
  5222. .ignore_pmdown_time = 1,
  5223. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5224. },
  5225. /* Hostless PCM purpose */
  5226. {
  5227. .name = "SLIMBUS_0 Hostless",
  5228. .stream_name = "SLIMBUS_0 Hostless",
  5229. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5230. .platform_name = "msm-pcm-hostless",
  5231. .dynamic = 1,
  5232. .dpcm_playback = 1,
  5233. .dpcm_capture = 1,
  5234. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5235. SND_SOC_DPCM_TRIGGER_POST},
  5236. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5237. .ignore_suspend = 1,
  5238. /* this dailink has playback support */
  5239. .ignore_pmdown_time = 1,
  5240. .codec_dai_name = "snd-soc-dummy-dai",
  5241. .codec_name = "snd-soc-dummy",
  5242. },
  5243. {
  5244. .name = "MSM AFE-PCM RX",
  5245. .stream_name = "AFE-PROXY RX",
  5246. .cpu_dai_name = "msm-dai-q6-dev.241",
  5247. .codec_name = "msm-stub-codec.1",
  5248. .codec_dai_name = "msm-stub-rx",
  5249. .platform_name = "msm-pcm-afe",
  5250. .dpcm_playback = 1,
  5251. .ignore_suspend = 1,
  5252. /* this dainlink has playback support */
  5253. .ignore_pmdown_time = 1,
  5254. },
  5255. {
  5256. .name = "MSM AFE-PCM TX",
  5257. .stream_name = "AFE-PROXY TX",
  5258. .cpu_dai_name = "msm-dai-q6-dev.240",
  5259. .codec_name = "msm-stub-codec.1",
  5260. .codec_dai_name = "msm-stub-tx",
  5261. .platform_name = "msm-pcm-afe",
  5262. .dpcm_capture = 1,
  5263. .ignore_suspend = 1,
  5264. },
  5265. {
  5266. .name = MSM_DAILINK_NAME(Compress1),
  5267. .stream_name = "Compress1",
  5268. .cpu_dai_name = "MultiMedia4",
  5269. .platform_name = "msm-compress-dsp",
  5270. .dynamic = 1,
  5271. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5272. .dpcm_playback = 1,
  5273. .dpcm_capture = 1,
  5274. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5275. SND_SOC_DPCM_TRIGGER_POST},
  5276. .codec_dai_name = "snd-soc-dummy-dai",
  5277. .codec_name = "snd-soc-dummy",
  5278. .ignore_suspend = 1,
  5279. .ignore_pmdown_time = 1,
  5280. /* this dainlink has playback support */
  5281. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5282. },
  5283. {
  5284. .name = "AUXPCM Hostless",
  5285. .stream_name = "AUXPCM Hostless",
  5286. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5287. .platform_name = "msm-pcm-hostless",
  5288. .dynamic = 1,
  5289. .dpcm_playback = 1,
  5290. .dpcm_capture = 1,
  5291. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5292. SND_SOC_DPCM_TRIGGER_POST},
  5293. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5294. .ignore_suspend = 1,
  5295. /* this dainlink has playback support */
  5296. .ignore_pmdown_time = 1,
  5297. .codec_dai_name = "snd-soc-dummy-dai",
  5298. .codec_name = "snd-soc-dummy",
  5299. },
  5300. {
  5301. .name = "SLIMBUS_1 Hostless",
  5302. .stream_name = "SLIMBUS_1 Hostless",
  5303. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5304. .platform_name = "msm-pcm-hostless",
  5305. .dynamic = 1,
  5306. .dpcm_playback = 1,
  5307. .dpcm_capture = 1,
  5308. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5309. SND_SOC_DPCM_TRIGGER_POST},
  5310. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5311. .ignore_suspend = 1,
  5312. /* this dailink has playback support */
  5313. .ignore_pmdown_time = 1,
  5314. .codec_dai_name = "snd-soc-dummy-dai",
  5315. .codec_name = "snd-soc-dummy",
  5316. },
  5317. {
  5318. .name = "SLIMBUS_3 Hostless",
  5319. .stream_name = "SLIMBUS_3 Hostless",
  5320. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5321. .platform_name = "msm-pcm-hostless",
  5322. .dynamic = 1,
  5323. .dpcm_playback = 1,
  5324. .dpcm_capture = 1,
  5325. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5326. SND_SOC_DPCM_TRIGGER_POST},
  5327. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5328. .ignore_suspend = 1,
  5329. /* this dailink has playback support */
  5330. .ignore_pmdown_time = 1,
  5331. .codec_dai_name = "snd-soc-dummy-dai",
  5332. .codec_name = "snd-soc-dummy",
  5333. },
  5334. {
  5335. .name = "SLIMBUS_4 Hostless",
  5336. .stream_name = "SLIMBUS_4 Hostless",
  5337. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5338. .platform_name = "msm-pcm-hostless",
  5339. .dynamic = 1,
  5340. .dpcm_playback = 1,
  5341. .dpcm_capture = 1,
  5342. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5343. SND_SOC_DPCM_TRIGGER_POST},
  5344. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5345. .ignore_suspend = 1,
  5346. /* this dailink has playback support */
  5347. .ignore_pmdown_time = 1,
  5348. .codec_dai_name = "snd-soc-dummy-dai",
  5349. .codec_name = "snd-soc-dummy",
  5350. },
  5351. {
  5352. .name = MSM_DAILINK_NAME(LowLatency),
  5353. .stream_name = "MultiMedia5",
  5354. .cpu_dai_name = "MultiMedia5",
  5355. .platform_name = "msm-pcm-dsp.1",
  5356. .dynamic = 1,
  5357. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5358. .dpcm_playback = 1,
  5359. .dpcm_capture = 1,
  5360. .codec_dai_name = "snd-soc-dummy-dai",
  5361. .codec_name = "snd-soc-dummy",
  5362. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5363. SND_SOC_DPCM_TRIGGER_POST},
  5364. .ignore_suspend = 1,
  5365. /* this dainlink has playback support */
  5366. .ignore_pmdown_time = 1,
  5367. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5368. .ops = &msm_fe_qos_ops,
  5369. },
  5370. {
  5371. .name = "Listen 1 Audio Service",
  5372. .stream_name = "Listen 1 Audio Service",
  5373. .cpu_dai_name = "LSM1",
  5374. .platform_name = "msm-lsm-client",
  5375. .dynamic = 1,
  5376. .dpcm_capture = 1,
  5377. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5378. SND_SOC_DPCM_TRIGGER_POST },
  5379. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5380. .ignore_suspend = 1,
  5381. .codec_dai_name = "snd-soc-dummy-dai",
  5382. .codec_name = "snd-soc-dummy",
  5383. .id = MSM_FRONTEND_DAI_LSM1,
  5384. },
  5385. /* Multiple Tunnel instances */
  5386. {
  5387. .name = MSM_DAILINK_NAME(Compress2),
  5388. .stream_name = "Compress2",
  5389. .cpu_dai_name = "MultiMedia7",
  5390. .platform_name = "msm-compress-dsp",
  5391. .dynamic = 1,
  5392. .dpcm_playback = 1,
  5393. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5394. SND_SOC_DPCM_TRIGGER_POST},
  5395. .codec_dai_name = "snd-soc-dummy-dai",
  5396. .codec_name = "snd-soc-dummy",
  5397. .ignore_suspend = 1,
  5398. .ignore_pmdown_time = 1,
  5399. /* this dainlink has playback support */
  5400. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5401. },
  5402. {
  5403. .name = MSM_DAILINK_NAME(MultiMedia10),
  5404. .stream_name = "MultiMedia10",
  5405. .cpu_dai_name = "MultiMedia10",
  5406. .platform_name = "msm-pcm-dsp.1",
  5407. .dynamic = 1,
  5408. .dpcm_playback = 1,
  5409. .dpcm_capture = 1,
  5410. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5411. SND_SOC_DPCM_TRIGGER_POST},
  5412. .codec_dai_name = "snd-soc-dummy-dai",
  5413. .codec_name = "snd-soc-dummy",
  5414. .ignore_suspend = 1,
  5415. .ignore_pmdown_time = 1,
  5416. /* this dainlink has playback support */
  5417. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5418. },
  5419. {
  5420. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5421. .stream_name = "MM_NOIRQ",
  5422. .cpu_dai_name = "MultiMedia8",
  5423. .platform_name = "msm-pcm-dsp-noirq",
  5424. .dynamic = 1,
  5425. .dpcm_playback = 1,
  5426. .dpcm_capture = 1,
  5427. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5428. SND_SOC_DPCM_TRIGGER_POST},
  5429. .codec_dai_name = "snd-soc-dummy-dai",
  5430. .codec_name = "snd-soc-dummy",
  5431. .ignore_suspend = 1,
  5432. .ignore_pmdown_time = 1,
  5433. /* this dainlink has playback support */
  5434. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5435. .ops = &msm_fe_qos_ops,
  5436. },
  5437. /* HDMI Hostless */
  5438. {
  5439. .name = "HDMI_RX_HOSTLESS",
  5440. .stream_name = "HDMI_RX_HOSTLESS",
  5441. .cpu_dai_name = "HDMI_HOSTLESS",
  5442. .platform_name = "msm-pcm-hostless",
  5443. .dynamic = 1,
  5444. .dpcm_playback = 1,
  5445. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5446. SND_SOC_DPCM_TRIGGER_POST},
  5447. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5448. .ignore_suspend = 1,
  5449. .ignore_pmdown_time = 1,
  5450. .codec_dai_name = "snd-soc-dummy-dai",
  5451. .codec_name = "snd-soc-dummy",
  5452. },
  5453. {
  5454. .name = "VoiceMMode2",
  5455. .stream_name = "VoiceMMode2",
  5456. .cpu_dai_name = "VoiceMMode2",
  5457. .platform_name = "msm-pcm-voice",
  5458. .dynamic = 1,
  5459. .dpcm_playback = 1,
  5460. .dpcm_capture = 1,
  5461. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5462. SND_SOC_DPCM_TRIGGER_POST},
  5463. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5464. .ignore_suspend = 1,
  5465. .ignore_pmdown_time = 1,
  5466. .codec_dai_name = "snd-soc-dummy-dai",
  5467. .codec_name = "snd-soc-dummy",
  5468. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5469. },
  5470. /* LSM FE */
  5471. {
  5472. .name = "Listen 2 Audio Service",
  5473. .stream_name = "Listen 2 Audio Service",
  5474. .cpu_dai_name = "LSM2",
  5475. .platform_name = "msm-lsm-client",
  5476. .dynamic = 1,
  5477. .dpcm_capture = 1,
  5478. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5479. SND_SOC_DPCM_TRIGGER_POST },
  5480. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5481. .ignore_suspend = 1,
  5482. .codec_dai_name = "snd-soc-dummy-dai",
  5483. .codec_name = "snd-soc-dummy",
  5484. .id = MSM_FRONTEND_DAI_LSM2,
  5485. },
  5486. {
  5487. .name = "Listen 3 Audio Service",
  5488. .stream_name = "Listen 3 Audio Service",
  5489. .cpu_dai_name = "LSM3",
  5490. .platform_name = "msm-lsm-client",
  5491. .dynamic = 1,
  5492. .dpcm_capture = 1,
  5493. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5494. SND_SOC_DPCM_TRIGGER_POST },
  5495. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5496. .ignore_suspend = 1,
  5497. .codec_dai_name = "snd-soc-dummy-dai",
  5498. .codec_name = "snd-soc-dummy",
  5499. .id = MSM_FRONTEND_DAI_LSM3,
  5500. },
  5501. {
  5502. .name = "Listen 4 Audio Service",
  5503. .stream_name = "Listen 4 Audio Service",
  5504. .cpu_dai_name = "LSM4",
  5505. .platform_name = "msm-lsm-client",
  5506. .dynamic = 1,
  5507. .dpcm_capture = 1,
  5508. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5509. SND_SOC_DPCM_TRIGGER_POST },
  5510. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5511. .ignore_suspend = 1,
  5512. .codec_dai_name = "snd-soc-dummy-dai",
  5513. .codec_name = "snd-soc-dummy",
  5514. .id = MSM_FRONTEND_DAI_LSM4,
  5515. },
  5516. {
  5517. .name = "Listen 5 Audio Service",
  5518. .stream_name = "Listen 5 Audio Service",
  5519. .cpu_dai_name = "LSM5",
  5520. .platform_name = "msm-lsm-client",
  5521. .dynamic = 1,
  5522. .dpcm_capture = 1,
  5523. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5524. SND_SOC_DPCM_TRIGGER_POST },
  5525. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5526. .ignore_suspend = 1,
  5527. .codec_dai_name = "snd-soc-dummy-dai",
  5528. .codec_name = "snd-soc-dummy",
  5529. .id = MSM_FRONTEND_DAI_LSM5,
  5530. },
  5531. {
  5532. .name = "Listen 6 Audio Service",
  5533. .stream_name = "Listen 6 Audio Service",
  5534. .cpu_dai_name = "LSM6",
  5535. .platform_name = "msm-lsm-client",
  5536. .dynamic = 1,
  5537. .dpcm_capture = 1,
  5538. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5539. SND_SOC_DPCM_TRIGGER_POST },
  5540. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5541. .ignore_suspend = 1,
  5542. .codec_dai_name = "snd-soc-dummy-dai",
  5543. .codec_name = "snd-soc-dummy",
  5544. .id = MSM_FRONTEND_DAI_LSM6,
  5545. },
  5546. {
  5547. .name = "Listen 7 Audio Service",
  5548. .stream_name = "Listen 7 Audio Service",
  5549. .cpu_dai_name = "LSM7",
  5550. .platform_name = "msm-lsm-client",
  5551. .dynamic = 1,
  5552. .dpcm_capture = 1,
  5553. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5554. SND_SOC_DPCM_TRIGGER_POST },
  5555. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5556. .ignore_suspend = 1,
  5557. .codec_dai_name = "snd-soc-dummy-dai",
  5558. .codec_name = "snd-soc-dummy",
  5559. .id = MSM_FRONTEND_DAI_LSM7,
  5560. },
  5561. {
  5562. .name = "Listen 8 Audio Service",
  5563. .stream_name = "Listen 8 Audio Service",
  5564. .cpu_dai_name = "LSM8",
  5565. .platform_name = "msm-lsm-client",
  5566. .dynamic = 1,
  5567. .dpcm_capture = 1,
  5568. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5569. SND_SOC_DPCM_TRIGGER_POST },
  5570. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5571. .ignore_suspend = 1,
  5572. .codec_dai_name = "snd-soc-dummy-dai",
  5573. .codec_name = "snd-soc-dummy",
  5574. .id = MSM_FRONTEND_DAI_LSM8,
  5575. },
  5576. {
  5577. .name = MSM_DAILINK_NAME(Media9),
  5578. .stream_name = "MultiMedia9",
  5579. .cpu_dai_name = "MultiMedia9",
  5580. .platform_name = "msm-pcm-dsp.0",
  5581. .dynamic = 1,
  5582. .dpcm_playback = 1,
  5583. .dpcm_capture = 1,
  5584. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5585. SND_SOC_DPCM_TRIGGER_POST},
  5586. .codec_dai_name = "snd-soc-dummy-dai",
  5587. .codec_name = "snd-soc-dummy",
  5588. .ignore_suspend = 1,
  5589. /* this dainlink has playback support */
  5590. .ignore_pmdown_time = 1,
  5591. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5592. },
  5593. {
  5594. .name = MSM_DAILINK_NAME(Compress4),
  5595. .stream_name = "Compress4",
  5596. .cpu_dai_name = "MultiMedia11",
  5597. .platform_name = "msm-compress-dsp",
  5598. .dynamic = 1,
  5599. .dpcm_playback = 1,
  5600. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5601. SND_SOC_DPCM_TRIGGER_POST},
  5602. .codec_dai_name = "snd-soc-dummy-dai",
  5603. .codec_name = "snd-soc-dummy",
  5604. .ignore_suspend = 1,
  5605. .ignore_pmdown_time = 1,
  5606. /* this dainlink has playback support */
  5607. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5608. },
  5609. {
  5610. .name = MSM_DAILINK_NAME(Compress5),
  5611. .stream_name = "Compress5",
  5612. .cpu_dai_name = "MultiMedia12",
  5613. .platform_name = "msm-compress-dsp",
  5614. .dynamic = 1,
  5615. .dpcm_playback = 1,
  5616. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5617. SND_SOC_DPCM_TRIGGER_POST},
  5618. .codec_dai_name = "snd-soc-dummy-dai",
  5619. .codec_name = "snd-soc-dummy",
  5620. .ignore_suspend = 1,
  5621. .ignore_pmdown_time = 1,
  5622. /* this dainlink has playback support */
  5623. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5624. },
  5625. {
  5626. .name = MSM_DAILINK_NAME(Compress6),
  5627. .stream_name = "Compress6",
  5628. .cpu_dai_name = "MultiMedia13",
  5629. .platform_name = "msm-compress-dsp",
  5630. .dynamic = 1,
  5631. .dpcm_playback = 1,
  5632. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5633. SND_SOC_DPCM_TRIGGER_POST},
  5634. .codec_dai_name = "snd-soc-dummy-dai",
  5635. .codec_name = "snd-soc-dummy",
  5636. .ignore_suspend = 1,
  5637. .ignore_pmdown_time = 1,
  5638. /* this dainlink has playback support */
  5639. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5640. },
  5641. {
  5642. .name = MSM_DAILINK_NAME(Compress7),
  5643. .stream_name = "Compress7",
  5644. .cpu_dai_name = "MultiMedia14",
  5645. .platform_name = "msm-compress-dsp",
  5646. .dynamic = 1,
  5647. .dpcm_playback = 1,
  5648. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5649. SND_SOC_DPCM_TRIGGER_POST},
  5650. .codec_dai_name = "snd-soc-dummy-dai",
  5651. .codec_name = "snd-soc-dummy",
  5652. .ignore_suspend = 1,
  5653. .ignore_pmdown_time = 1,
  5654. /* this dainlink has playback support */
  5655. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5656. },
  5657. {
  5658. .name = MSM_DAILINK_NAME(Compress8),
  5659. .stream_name = "Compress8",
  5660. .cpu_dai_name = "MultiMedia15",
  5661. .platform_name = "msm-compress-dsp",
  5662. .dynamic = 1,
  5663. .dpcm_playback = 1,
  5664. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5665. SND_SOC_DPCM_TRIGGER_POST},
  5666. .codec_dai_name = "snd-soc-dummy-dai",
  5667. .codec_name = "snd-soc-dummy",
  5668. .ignore_suspend = 1,
  5669. .ignore_pmdown_time = 1,
  5670. /* this dainlink has playback support */
  5671. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5672. },
  5673. {
  5674. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5675. .stream_name = "MM_NOIRQ_2",
  5676. .cpu_dai_name = "MultiMedia16",
  5677. .platform_name = "msm-pcm-dsp-noirq",
  5678. .dynamic = 1,
  5679. .dpcm_playback = 1,
  5680. .dpcm_capture = 1,
  5681. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5682. SND_SOC_DPCM_TRIGGER_POST},
  5683. .codec_dai_name = "snd-soc-dummy-dai",
  5684. .codec_name = "snd-soc-dummy",
  5685. .ignore_suspend = 1,
  5686. .ignore_pmdown_time = 1,
  5687. /* this dainlink has playback support */
  5688. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5689. },
  5690. {
  5691. .name = "SLIMBUS_8 Hostless",
  5692. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5693. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5694. .platform_name = "msm-pcm-hostless",
  5695. .dynamic = 1,
  5696. .dpcm_capture = 1,
  5697. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5698. SND_SOC_DPCM_TRIGGER_POST},
  5699. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5700. .ignore_suspend = 1,
  5701. .codec_dai_name = "snd-soc-dummy-dai",
  5702. .codec_name = "snd-soc-dummy",
  5703. },
  5704. /* Hostless PCM purpose */
  5705. {
  5706. .name = "CDC_DMA Hostless",
  5707. .stream_name = "CDC_DMA Hostless",
  5708. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5709. .platform_name = "msm-pcm-hostless",
  5710. .dynamic = 1,
  5711. .dpcm_playback = 1,
  5712. .dpcm_capture = 1,
  5713. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5714. SND_SOC_DPCM_TRIGGER_POST},
  5715. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5716. .ignore_suspend = 1,
  5717. /* this dailink has playback support */
  5718. .ignore_pmdown_time = 1,
  5719. .codec_dai_name = "snd-soc-dummy-dai",
  5720. .codec_name = "snd-soc-dummy",
  5721. },
  5722. };
  5723. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5724. {
  5725. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5726. .stream_name = "WSA CDC DMA0 Capture",
  5727. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5728. .platform_name = "msm-pcm-hostless",
  5729. .codec_name = "bolero_codec",
  5730. .codec_dai_name = "wsa_macro_vifeedback",
  5731. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5732. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5733. .ignore_suspend = 1,
  5734. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5735. .ops = &msm_cdc_dma_be_ops,
  5736. },
  5737. };
  5738. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5739. {
  5740. .name = MSM_DAILINK_NAME(ASM Loopback),
  5741. .stream_name = "MultiMedia6",
  5742. .cpu_dai_name = "MultiMedia6",
  5743. .platform_name = "msm-pcm-loopback",
  5744. .dynamic = 1,
  5745. .dpcm_playback = 1,
  5746. .dpcm_capture = 1,
  5747. .codec_dai_name = "snd-soc-dummy-dai",
  5748. .codec_name = "snd-soc-dummy",
  5749. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5750. SND_SOC_DPCM_TRIGGER_POST},
  5751. .ignore_suspend = 1,
  5752. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5753. .ignore_pmdown_time = 1,
  5754. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5755. },
  5756. {
  5757. .name = "USB Audio Hostless",
  5758. .stream_name = "USB Audio Hostless",
  5759. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5760. .platform_name = "msm-pcm-hostless",
  5761. .dynamic = 1,
  5762. .dpcm_playback = 1,
  5763. .dpcm_capture = 1,
  5764. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5765. SND_SOC_DPCM_TRIGGER_POST},
  5766. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5767. .ignore_suspend = 1,
  5768. .ignore_pmdown_time = 1,
  5769. .codec_dai_name = "snd-soc-dummy-dai",
  5770. .codec_name = "snd-soc-dummy",
  5771. },
  5772. {
  5773. .name = "SLIMBUS_7 Hostless",
  5774. .stream_name = "SLIMBUS_7 Hostless",
  5775. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5776. .platform_name = "msm-pcm-hostless",
  5777. .dynamic = 1,
  5778. .dpcm_capture = 1,
  5779. .dpcm_playback = 1,
  5780. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5781. SND_SOC_DPCM_TRIGGER_POST},
  5782. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5783. .ignore_suspend = 1,
  5784. .ignore_pmdown_time = 1,
  5785. .codec_dai_name = "snd-soc-dummy-dai",
  5786. .codec_name = "snd-soc-dummy",
  5787. },
  5788. {
  5789. .name = MSM_DAILINK_NAME(Compr Capture),
  5790. .stream_name = "Compr Capture",
  5791. .cpu_dai_name = "MultiMedia18",
  5792. .platform_name = "msm-compress-dsp",
  5793. .dynamic = 1,
  5794. .dpcm_capture = 1,
  5795. .codec_dai_name = "snd-soc-dummy-dai",
  5796. .codec_name = "snd-soc-dummy",
  5797. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5798. SND_SOC_DPCM_TRIGGER_POST},
  5799. .ignore_pmdown_time = 1,
  5800. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5801. },
  5802. {
  5803. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  5804. .stream_name = "Transcode Loopback Playback",
  5805. .cpu_dai_name = "MultiMedia26",
  5806. .platform_name = "msm-transcode-loopback",
  5807. .dynamic = 1,
  5808. .dpcm_playback = 1,
  5809. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5810. SND_SOC_DPCM_TRIGGER_POST},
  5811. .codec_dai_name = "snd-soc-dummy-dai",
  5812. .codec_name = "snd-soc-dummy",
  5813. .ignore_suspend = 1,
  5814. .ignore_pmdown_time = 1,
  5815. /* this dailink has playback support */
  5816. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  5817. },
  5818. {
  5819. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  5820. .stream_name = "Transcode Loopback Capture",
  5821. .cpu_dai_name = "MultiMedia27",
  5822. .platform_name = "msm-transcode-loopback",
  5823. .dynamic = 1,
  5824. .dpcm_capture = 1,
  5825. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5826. SND_SOC_DPCM_TRIGGER_POST},
  5827. .codec_dai_name = "snd-soc-dummy-dai",
  5828. .codec_name = "snd-soc-dummy",
  5829. .ignore_suspend = 1,
  5830. .ignore_pmdown_time = 1,
  5831. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  5832. },
  5833. };
  5834. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5835. /* Backend AFE DAI Links */
  5836. {
  5837. .name = LPASS_BE_AFE_PCM_RX,
  5838. .stream_name = "AFE Playback",
  5839. .cpu_dai_name = "msm-dai-q6-dev.224",
  5840. .platform_name = "msm-pcm-routing",
  5841. .codec_name = "msm-stub-codec.1",
  5842. .codec_dai_name = "msm-stub-rx",
  5843. .no_pcm = 1,
  5844. .dpcm_playback = 1,
  5845. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5846. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5847. /* this dainlink has playback support */
  5848. .ignore_pmdown_time = 1,
  5849. .ignore_suspend = 1,
  5850. },
  5851. {
  5852. .name = LPASS_BE_AFE_PCM_TX,
  5853. .stream_name = "AFE Capture",
  5854. .cpu_dai_name = "msm-dai-q6-dev.225",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-tx",
  5858. .no_pcm = 1,
  5859. .dpcm_capture = 1,
  5860. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ignore_suspend = 1,
  5863. },
  5864. /* Incall Record Uplink BACK END DAI Link */
  5865. {
  5866. .name = LPASS_BE_INCALL_RECORD_TX,
  5867. .stream_name = "Voice Uplink Capture",
  5868. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5869. .platform_name = "msm-pcm-routing",
  5870. .codec_name = "msm-stub-codec.1",
  5871. .codec_dai_name = "msm-stub-tx",
  5872. .no_pcm = 1,
  5873. .dpcm_capture = 1,
  5874. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5875. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5876. .ignore_suspend = 1,
  5877. },
  5878. /* Incall Record Downlink BACK END DAI Link */
  5879. {
  5880. .name = LPASS_BE_INCALL_RECORD_RX,
  5881. .stream_name = "Voice Downlink Capture",
  5882. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5883. .platform_name = "msm-pcm-routing",
  5884. .codec_name = "msm-stub-codec.1",
  5885. .codec_dai_name = "msm-stub-tx",
  5886. .no_pcm = 1,
  5887. .dpcm_capture = 1,
  5888. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5889. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5890. .ignore_suspend = 1,
  5891. },
  5892. /* Incall Music BACK END DAI Link */
  5893. {
  5894. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5895. .stream_name = "Voice Farend Playback",
  5896. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5897. .platform_name = "msm-pcm-routing",
  5898. .codec_name = "msm-stub-codec.1",
  5899. .codec_dai_name = "msm-stub-rx",
  5900. .no_pcm = 1,
  5901. .dpcm_playback = 1,
  5902. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5903. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5904. .ignore_suspend = 1,
  5905. .ignore_pmdown_time = 1,
  5906. },
  5907. /* Incall Music 2 BACK END DAI Link */
  5908. {
  5909. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5910. .stream_name = "Voice2 Farend Playback",
  5911. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5912. .platform_name = "msm-pcm-routing",
  5913. .codec_name = "msm-stub-codec.1",
  5914. .codec_dai_name = "msm-stub-rx",
  5915. .no_pcm = 1,
  5916. .dpcm_playback = 1,
  5917. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5918. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5919. .ignore_suspend = 1,
  5920. .ignore_pmdown_time = 1,
  5921. },
  5922. {
  5923. .name = LPASS_BE_USB_AUDIO_RX,
  5924. .stream_name = "USB Audio Playback",
  5925. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5926. .platform_name = "msm-pcm-routing",
  5927. .codec_name = "msm-stub-codec.1",
  5928. .codec_dai_name = "msm-stub-rx",
  5929. .no_pcm = 1,
  5930. .dpcm_playback = 1,
  5931. .id = MSM_BACKEND_DAI_USB_RX,
  5932. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5933. .ignore_pmdown_time = 1,
  5934. .ignore_suspend = 1,
  5935. },
  5936. {
  5937. .name = LPASS_BE_USB_AUDIO_TX,
  5938. .stream_name = "USB Audio Capture",
  5939. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5940. .platform_name = "msm-pcm-routing",
  5941. .codec_name = "msm-stub-codec.1",
  5942. .codec_dai_name = "msm-stub-tx",
  5943. .no_pcm = 1,
  5944. .dpcm_capture = 1,
  5945. .id = MSM_BACKEND_DAI_USB_TX,
  5946. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5947. .ignore_suspend = 1,
  5948. },
  5949. {
  5950. .name = LPASS_BE_PRI_TDM_RX_0,
  5951. .stream_name = "Primary TDM0 Playback",
  5952. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5953. .platform_name = "msm-pcm-routing",
  5954. .codec_name = "msm-stub-codec.1",
  5955. .codec_dai_name = "msm-stub-rx",
  5956. .no_pcm = 1,
  5957. .dpcm_playback = 1,
  5958. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5959. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5960. .ops = &qcs405_tdm_be_ops,
  5961. .ignore_suspend = 1,
  5962. .ignore_pmdown_time = 1,
  5963. },
  5964. {
  5965. .name = LPASS_BE_PRI_TDM_TX_0,
  5966. .stream_name = "Primary TDM0 Capture",
  5967. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5968. .platform_name = "msm-pcm-routing",
  5969. .codec_name = "msm-stub-codec.1",
  5970. .codec_dai_name = "msm-stub-tx",
  5971. .no_pcm = 1,
  5972. .dpcm_capture = 1,
  5973. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5974. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5975. .ops = &qcs405_tdm_be_ops,
  5976. .ignore_suspend = 1,
  5977. },
  5978. {
  5979. .name = LPASS_BE_SEC_TDM_RX_0,
  5980. .stream_name = "Secondary TDM0 Playback",
  5981. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5982. .platform_name = "msm-pcm-routing",
  5983. .codec_name = "msm-stub-codec.1",
  5984. .codec_dai_name = "msm-stub-rx",
  5985. .no_pcm = 1,
  5986. .dpcm_playback = 1,
  5987. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5988. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5989. .ops = &qcs405_tdm_be_ops,
  5990. .ignore_suspend = 1,
  5991. .ignore_pmdown_time = 1,
  5992. },
  5993. {
  5994. .name = LPASS_BE_SEC_TDM_TX_0,
  5995. .stream_name = "Secondary TDM0 Capture",
  5996. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5997. .platform_name = "msm-pcm-routing",
  5998. .codec_name = "msm-stub-codec.1",
  5999. .codec_dai_name = "msm-stub-tx",
  6000. .no_pcm = 1,
  6001. .dpcm_capture = 1,
  6002. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  6003. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6004. .ops = &qcs405_tdm_be_ops,
  6005. .ignore_suspend = 1,
  6006. },
  6007. {
  6008. .name = LPASS_BE_TERT_TDM_RX_0,
  6009. .stream_name = "Tertiary TDM0 Playback",
  6010. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  6011. .platform_name = "msm-pcm-routing",
  6012. .codec_name = "msm-stub-codec.1",
  6013. .codec_dai_name = "msm-stub-rx",
  6014. .no_pcm = 1,
  6015. .dpcm_playback = 1,
  6016. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  6017. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6018. .ops = &qcs405_tdm_be_ops,
  6019. .ignore_suspend = 1,
  6020. .ignore_pmdown_time = 1,
  6021. },
  6022. {
  6023. .name = LPASS_BE_TERT_TDM_TX_0,
  6024. .stream_name = "Tertiary TDM0 Capture",
  6025. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6026. .platform_name = "msm-pcm-routing",
  6027. .codec_name = "msm-stub-codec.1",
  6028. .codec_dai_name = "msm-stub-tx",
  6029. .no_pcm = 1,
  6030. .dpcm_capture = 1,
  6031. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6032. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6033. .ops = &qcs405_tdm_be_ops,
  6034. .ignore_suspend = 1,
  6035. },
  6036. {
  6037. .name = LPASS_BE_QUAT_TDM_RX_0,
  6038. .stream_name = "Quaternary TDM0 Playback",
  6039. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6040. .platform_name = "msm-pcm-routing",
  6041. .codec_name = "msm-stub-codec.1",
  6042. .codec_dai_name = "msm-stub-rx",
  6043. .no_pcm = 1,
  6044. .dpcm_playback = 1,
  6045. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6046. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6047. .ops = &qcs405_tdm_be_ops,
  6048. .ignore_suspend = 1,
  6049. .ignore_pmdown_time = 1,
  6050. },
  6051. {
  6052. .name = LPASS_BE_QUAT_TDM_TX_0,
  6053. .stream_name = "Quaternary TDM0 Capture",
  6054. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6055. .platform_name = "msm-pcm-routing",
  6056. .codec_name = "msm-stub-codec.1",
  6057. .codec_dai_name = "msm-stub-tx",
  6058. .no_pcm = 1,
  6059. .dpcm_capture = 1,
  6060. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6061. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6062. .ops = &qcs405_tdm_be_ops,
  6063. .ignore_suspend = 1,
  6064. },
  6065. {
  6066. .name = LPASS_BE_QUIN_TDM_RX_0,
  6067. .stream_name = "Quinary TDM0 Playback",
  6068. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6069. .platform_name = "msm-pcm-routing",
  6070. .codec_name = "msm-stub-codec.1",
  6071. .codec_dai_name = "msm-stub-rx",
  6072. .no_pcm = 1,
  6073. .dpcm_playback = 1,
  6074. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6075. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6076. .ops = &qcs405_tdm_be_ops,
  6077. .ignore_suspend = 1,
  6078. .ignore_pmdown_time = 1,
  6079. },
  6080. {
  6081. .name = LPASS_BE_QUIN_TDM_TX_0,
  6082. .stream_name = "Quinary TDM0 Capture",
  6083. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6084. .platform_name = "msm-pcm-routing",
  6085. .codec_name = "msm-stub-codec.1",
  6086. .codec_dai_name = "msm-stub-tx",
  6087. .no_pcm = 1,
  6088. .dpcm_capture = 1,
  6089. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6090. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6091. .ops = &qcs405_tdm_be_ops,
  6092. .ignore_suspend = 1,
  6093. },
  6094. };
  6095. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6096. {
  6097. .name = LPASS_BE_SLIMBUS_0_RX,
  6098. .stream_name = "Slimbus Playback",
  6099. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6100. .platform_name = "msm-pcm-routing",
  6101. .codec_name = "tasha_codec",
  6102. .codec_dai_name = "tasha_mix_rx1",
  6103. .no_pcm = 1,
  6104. .dpcm_playback = 1,
  6105. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6106. .init = &msm_audrx_init,
  6107. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6108. /* this dainlink has playback support */
  6109. .ignore_pmdown_time = 1,
  6110. .ignore_suspend = 1,
  6111. .ops = &msm_be_ops,
  6112. },
  6113. {
  6114. .name = LPASS_BE_SLIMBUS_0_TX,
  6115. .stream_name = "Slimbus Capture",
  6116. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6117. .platform_name = "msm-pcm-routing",
  6118. .codec_name = "tasha_codec",
  6119. .codec_dai_name = "tasha_tx1",
  6120. .no_pcm = 1,
  6121. .dpcm_capture = 1,
  6122. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6123. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6124. .ignore_suspend = 1,
  6125. .ops = &msm_be_ops,
  6126. },
  6127. {
  6128. .name = LPASS_BE_SLIMBUS_1_RX,
  6129. .stream_name = "Slimbus1 Playback",
  6130. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6131. .platform_name = "msm-pcm-routing",
  6132. .codec_name = "tasha_codec",
  6133. .codec_dai_name = "tasha_mix_rx1",
  6134. .no_pcm = 1,
  6135. .dpcm_playback = 1,
  6136. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6137. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6138. .ops = &msm_be_ops,
  6139. /* dai link has playback support */
  6140. .ignore_pmdown_time = 1,
  6141. .ignore_suspend = 1,
  6142. },
  6143. {
  6144. .name = LPASS_BE_SLIMBUS_1_TX,
  6145. .stream_name = "Slimbus1 Capture",
  6146. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6147. .platform_name = "msm-pcm-routing",
  6148. .codec_name = "tasha_codec",
  6149. .codec_dai_name = "tasha_tx3",
  6150. .no_pcm = 1,
  6151. .dpcm_capture = 1,
  6152. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6153. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6154. .ops = &msm_be_ops,
  6155. .ignore_suspend = 1,
  6156. },
  6157. {
  6158. .name = LPASS_BE_SLIMBUS_2_RX,
  6159. .stream_name = "Slimbus2 Playback",
  6160. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6161. .platform_name = "msm-pcm-routing",
  6162. .codec_name = "tasha_codec",
  6163. .codec_dai_name = "tasha_rx2",
  6164. .no_pcm = 1,
  6165. .dpcm_playback = 1,
  6166. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6167. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6168. .ops = &msm_be_ops,
  6169. .ignore_pmdown_time = 1,
  6170. .ignore_suspend = 1,
  6171. },
  6172. {
  6173. .name = LPASS_BE_SLIMBUS_3_RX,
  6174. .stream_name = "Slimbus3 Playback",
  6175. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6176. .platform_name = "msm-pcm-routing",
  6177. .codec_name = "tasha_codec",
  6178. .codec_dai_name = "tasha_mix_rx1",
  6179. .no_pcm = 1,
  6180. .dpcm_playback = 1,
  6181. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6182. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6183. .ops = &msm_be_ops,
  6184. /* dai link has playback support */
  6185. .ignore_pmdown_time = 1,
  6186. .ignore_suspend = 1,
  6187. },
  6188. {
  6189. .name = LPASS_BE_SLIMBUS_3_TX,
  6190. .stream_name = "Slimbus3 Capture",
  6191. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6192. .platform_name = "msm-pcm-routing",
  6193. .codec_name = "tasha_codec",
  6194. .codec_dai_name = "tasha_tx1",
  6195. .no_pcm = 1,
  6196. .dpcm_capture = 1,
  6197. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6198. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6199. .ops = &msm_be_ops,
  6200. .ignore_suspend = 1,
  6201. },
  6202. {
  6203. .name = LPASS_BE_SLIMBUS_4_RX,
  6204. .stream_name = "Slimbus4 Playback",
  6205. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6206. .platform_name = "msm-pcm-routing",
  6207. .codec_name = "tasha_codec",
  6208. .codec_dai_name = "tasha_mix_rx1",
  6209. .no_pcm = 1,
  6210. .dpcm_playback = 1,
  6211. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6212. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6213. .ops = &msm_be_ops,
  6214. /* dai link has playback support */
  6215. .ignore_pmdown_time = 1,
  6216. .ignore_suspend = 1,
  6217. },
  6218. {
  6219. .name = LPASS_BE_SLIMBUS_5_RX,
  6220. .stream_name = "Slimbus5 Playback",
  6221. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6222. .platform_name = "msm-pcm-routing",
  6223. .codec_name = "tasha_codec",
  6224. .codec_dai_name = "tasha_rx3",
  6225. .no_pcm = 1,
  6226. .dpcm_playback = 1,
  6227. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6228. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6229. .ops = &msm_be_ops,
  6230. /* dai link has playback support */
  6231. .ignore_pmdown_time = 1,
  6232. .ignore_suspend = 1,
  6233. },
  6234. {
  6235. .name = LPASS_BE_SLIMBUS_6_RX,
  6236. .stream_name = "Slimbus6 Playback",
  6237. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6238. .platform_name = "msm-pcm-routing",
  6239. .codec_name = "tasha_codec",
  6240. .codec_dai_name = "tasha_rx4",
  6241. .no_pcm = 1,
  6242. .dpcm_playback = 1,
  6243. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6244. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6245. .ops = &msm_be_ops,
  6246. /* dai link has playback support */
  6247. .ignore_pmdown_time = 1,
  6248. .ignore_suspend = 1,
  6249. },
  6250. /* Slimbus VI Recording */
  6251. {
  6252. .name = LPASS_BE_SLIMBUS_TX_VI,
  6253. .stream_name = "Slimbus4 Capture",
  6254. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6255. .platform_name = "msm-pcm-routing",
  6256. .codec_name = "tasha_codec",
  6257. .codec_dai_name = "tasha_vifeedback",
  6258. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6259. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6260. .ops = &msm_be_ops,
  6261. .ignore_suspend = 1,
  6262. .no_pcm = 1,
  6263. .dpcm_capture = 1,
  6264. .ignore_pmdown_time = 1,
  6265. },
  6266. };
  6267. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6268. {
  6269. .name = LPASS_BE_SLIMBUS_7_RX,
  6270. .stream_name = "Slimbus7 Playback",
  6271. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6272. .platform_name = "msm-pcm-routing",
  6273. .codec_name = "btfmslim_slave",
  6274. /* BT codec driver determines capabilities based on
  6275. * dai name, bt codecdai name should always contains
  6276. * supported usecase information
  6277. */
  6278. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6279. .no_pcm = 1,
  6280. .dpcm_playback = 1,
  6281. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6282. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6283. .ops = &msm_wcn_ops,
  6284. /* dai link has playback support */
  6285. .ignore_pmdown_time = 1,
  6286. .ignore_suspend = 1,
  6287. },
  6288. {
  6289. .name = LPASS_BE_SLIMBUS_7_TX,
  6290. .stream_name = "Slimbus7 Capture",
  6291. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6292. .platform_name = "msm-pcm-routing",
  6293. .codec_name = "btfmslim_slave",
  6294. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6295. .no_pcm = 1,
  6296. .dpcm_capture = 1,
  6297. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6298. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6299. .ops = &msm_wcn_ops,
  6300. .ignore_suspend = 1,
  6301. },
  6302. {
  6303. .name = LPASS_BE_SLIMBUS_8_TX,
  6304. .stream_name = "Slimbus8 Capture",
  6305. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6306. .platform_name = "msm-pcm-routing",
  6307. .codec_name = "btfmslim_slave",
  6308. .codec_dai_name = "btfm_fm_slim_tx",
  6309. .no_pcm = 1,
  6310. .dpcm_capture = 1,
  6311. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6312. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6313. .init = &msm_wcn_init,
  6314. .ops = &msm_wcn_ops,
  6315. .ignore_suspend = 1,
  6316. },
  6317. {
  6318. .name = LPASS_BE_SLIMBUS_9_TX,
  6319. .stream_name = "Slimbus9 Capture",
  6320. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6321. .platform_name = "msm-pcm-routing",
  6322. .codec_name = "btfmslim_slave",
  6323. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6324. .no_pcm = 1,
  6325. .dpcm_capture = 1,
  6326. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6327. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6328. .ops = &msm_wcn_ops,
  6329. .ignore_suspend = 1,
  6330. },
  6331. };
  6332. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6333. {
  6334. .name = LPASS_BE_PRI_MI2S_RX,
  6335. .stream_name = "Primary MI2S Playback",
  6336. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6337. .platform_name = "msm-pcm-routing",
  6338. .codec_name = "msm-stub-codec.1",
  6339. .codec_dai_name = "msm-stub-rx",
  6340. .no_pcm = 1,
  6341. .dpcm_playback = 1,
  6342. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6343. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6344. .ops = &msm_mi2s_be_ops,
  6345. .ignore_suspend = 1,
  6346. .ignore_pmdown_time = 1,
  6347. },
  6348. {
  6349. .name = LPASS_BE_PRI_MI2S_TX,
  6350. .stream_name = "Primary MI2S Capture",
  6351. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6352. .platform_name = "msm-pcm-routing",
  6353. .codec_name = "msm-stub-codec.1",
  6354. .codec_dai_name = "msm-stub-tx",
  6355. .no_pcm = 1,
  6356. .dpcm_capture = 1,
  6357. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6358. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6359. .ops = &msm_mi2s_be_ops,
  6360. .ignore_suspend = 1,
  6361. },
  6362. {
  6363. .name = LPASS_BE_SEC_MI2S_RX,
  6364. .stream_name = "Secondary MI2S Playback",
  6365. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6366. .platform_name = "msm-pcm-routing",
  6367. .codec_name = "msm-stub-codec.1",
  6368. .codec_dai_name = "msm-stub-rx",
  6369. .no_pcm = 1,
  6370. .dpcm_playback = 1,
  6371. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6372. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6373. .ops = &msm_mi2s_be_ops,
  6374. .ignore_suspend = 1,
  6375. .ignore_pmdown_time = 1,
  6376. },
  6377. {
  6378. .name = LPASS_BE_SEC_MI2S_TX,
  6379. .stream_name = "Secondary MI2S Capture",
  6380. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6381. .platform_name = "msm-pcm-routing",
  6382. .codec_name = "msm-stub-codec.1",
  6383. .codec_dai_name = "msm-stub-tx",
  6384. .no_pcm = 1,
  6385. .dpcm_capture = 1,
  6386. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6387. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6388. .ops = &msm_mi2s_be_ops,
  6389. .ignore_suspend = 1,
  6390. },
  6391. {
  6392. .name = LPASS_BE_TERT_MI2S_RX,
  6393. .stream_name = "Tertiary MI2S Playback",
  6394. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6395. .platform_name = "msm-pcm-routing",
  6396. .codec_name = "msm-stub-codec.1",
  6397. .codec_dai_name = "msm-stub-rx",
  6398. .no_pcm = 1,
  6399. .dpcm_playback = 1,
  6400. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6401. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6402. .ops = &msm_mi2s_be_ops,
  6403. .ignore_suspend = 1,
  6404. .ignore_pmdown_time = 1,
  6405. },
  6406. {
  6407. .name = LPASS_BE_TERT_MI2S_TX,
  6408. .stream_name = "Tertiary MI2S Capture",
  6409. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6410. .platform_name = "msm-pcm-routing",
  6411. .codec_name = "msm-stub-codec.1",
  6412. .codec_dai_name = "msm-stub-tx",
  6413. .no_pcm = 1,
  6414. .dpcm_capture = 1,
  6415. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6416. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6417. .ops = &msm_mi2s_be_ops,
  6418. .ignore_suspend = 1,
  6419. },
  6420. {
  6421. .name = LPASS_BE_QUAT_MI2S_RX,
  6422. .stream_name = "Quaternary MI2S Playback",
  6423. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6424. .platform_name = "msm-pcm-routing",
  6425. .codec_name = "msm-stub-codec.1",
  6426. .codec_dai_name = "msm-stub-rx",
  6427. .no_pcm = 1,
  6428. .dpcm_playback = 1,
  6429. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6430. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6431. .ops = &msm_mi2s_be_ops,
  6432. .ignore_suspend = 1,
  6433. .ignore_pmdown_time = 1,
  6434. },
  6435. {
  6436. .name = LPASS_BE_QUAT_MI2S_TX,
  6437. .stream_name = "Quaternary MI2S Capture",
  6438. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6439. .platform_name = "msm-pcm-routing",
  6440. .codec_name = "msm-stub-codec.1",
  6441. .codec_dai_name = "msm-stub-tx",
  6442. .no_pcm = 1,
  6443. .dpcm_capture = 1,
  6444. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6445. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6446. .ops = &msm_mi2s_be_ops,
  6447. .ignore_suspend = 1,
  6448. },
  6449. {
  6450. .name = LPASS_BE_QUIN_MI2S_RX,
  6451. .stream_name = "Quinary MI2S Playback",
  6452. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6453. .platform_name = "msm-pcm-routing",
  6454. .codec_name = "msm-stub-codec.1",
  6455. .codec_dai_name = "msm-stub-rx",
  6456. .no_pcm = 1,
  6457. .dpcm_playback = 1,
  6458. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6459. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6460. .ops = &msm_mi2s_be_ops,
  6461. .ignore_suspend = 1,
  6462. .ignore_pmdown_time = 1,
  6463. },
  6464. {
  6465. .name = LPASS_BE_QUIN_MI2S_TX,
  6466. .stream_name = "Quinary MI2S Capture",
  6467. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6468. .platform_name = "msm-pcm-routing",
  6469. .codec_name = "msm-stub-codec.1",
  6470. .codec_dai_name = "msm-stub-tx",
  6471. .no_pcm = 1,
  6472. .dpcm_capture = 1,
  6473. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6474. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6475. .ops = &msm_mi2s_be_ops,
  6476. .ignore_suspend = 1,
  6477. },
  6478. };
  6479. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6480. /* Primary AUX PCM Backend DAI Links */
  6481. {
  6482. .name = LPASS_BE_AUXPCM_RX,
  6483. .stream_name = "AUX PCM Playback",
  6484. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6485. .platform_name = "msm-pcm-routing",
  6486. .codec_name = "msm-stub-codec.1",
  6487. .codec_dai_name = "msm-stub-rx",
  6488. .no_pcm = 1,
  6489. .dpcm_playback = 1,
  6490. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6491. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6492. .ignore_pmdown_time = 1,
  6493. .ignore_suspend = 1,
  6494. },
  6495. {
  6496. .name = LPASS_BE_AUXPCM_TX,
  6497. .stream_name = "AUX PCM Capture",
  6498. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6499. .platform_name = "msm-pcm-routing",
  6500. .codec_name = "msm-stub-codec.1",
  6501. .codec_dai_name = "msm-stub-tx",
  6502. .no_pcm = 1,
  6503. .dpcm_capture = 1,
  6504. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6505. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6506. .ignore_suspend = 1,
  6507. },
  6508. /* Secondary AUX PCM Backend DAI Links */
  6509. {
  6510. .name = LPASS_BE_SEC_AUXPCM_RX,
  6511. .stream_name = "Sec AUX PCM Playback",
  6512. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6513. .platform_name = "msm-pcm-routing",
  6514. .codec_name = "msm-stub-codec.1",
  6515. .codec_dai_name = "msm-stub-rx",
  6516. .no_pcm = 1,
  6517. .dpcm_playback = 1,
  6518. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6519. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6520. .ignore_pmdown_time = 1,
  6521. .ignore_suspend = 1,
  6522. },
  6523. {
  6524. .name = LPASS_BE_SEC_AUXPCM_TX,
  6525. .stream_name = "Sec AUX PCM Capture",
  6526. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6527. .platform_name = "msm-pcm-routing",
  6528. .codec_name = "msm-stub-codec.1",
  6529. .codec_dai_name = "msm-stub-tx",
  6530. .no_pcm = 1,
  6531. .dpcm_capture = 1,
  6532. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6533. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6534. .ignore_suspend = 1,
  6535. },
  6536. /* Tertiary AUX PCM Backend DAI Links */
  6537. {
  6538. .name = LPASS_BE_TERT_AUXPCM_RX,
  6539. .stream_name = "Tert AUX PCM Playback",
  6540. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6541. .platform_name = "msm-pcm-routing",
  6542. .codec_name = "msm-stub-codec.1",
  6543. .codec_dai_name = "msm-stub-rx",
  6544. .no_pcm = 1,
  6545. .dpcm_playback = 1,
  6546. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6547. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6548. .ignore_suspend = 1,
  6549. },
  6550. {
  6551. .name = LPASS_BE_TERT_AUXPCM_TX,
  6552. .stream_name = "Tert AUX PCM Capture",
  6553. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6554. .platform_name = "msm-pcm-routing",
  6555. .codec_name = "msm-stub-codec.1",
  6556. .codec_dai_name = "msm-stub-tx",
  6557. .no_pcm = 1,
  6558. .dpcm_capture = 1,
  6559. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6560. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6561. .ignore_suspend = 1,
  6562. },
  6563. /* Quaternary AUX PCM Backend DAI Links */
  6564. {
  6565. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6566. .stream_name = "Quat AUX PCM Playback",
  6567. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6568. .platform_name = "msm-pcm-routing",
  6569. .codec_name = "msm-stub-codec.1",
  6570. .codec_dai_name = "msm-stub-rx",
  6571. .no_pcm = 1,
  6572. .dpcm_playback = 1,
  6573. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6574. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6575. .ignore_pmdown_time = 1,
  6576. .ignore_suspend = 1,
  6577. },
  6578. {
  6579. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6580. .stream_name = "Quat AUX PCM Capture",
  6581. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6582. .platform_name = "msm-pcm-routing",
  6583. .codec_name = "msm-stub-codec.1",
  6584. .codec_dai_name = "msm-stub-tx",
  6585. .no_pcm = 1,
  6586. .dpcm_capture = 1,
  6587. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6588. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6589. .ignore_suspend = 1,
  6590. },
  6591. /* Quinary AUX PCM Backend DAI Links */
  6592. {
  6593. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6594. .stream_name = "Quin AUX PCM Playback",
  6595. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6596. .platform_name = "msm-pcm-routing",
  6597. .codec_name = "msm-stub-codec.1",
  6598. .codec_dai_name = "msm-stub-rx",
  6599. .no_pcm = 1,
  6600. .dpcm_playback = 1,
  6601. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6602. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6603. .ignore_pmdown_time = 1,
  6604. .ignore_suspend = 1,
  6605. },
  6606. {
  6607. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6608. .stream_name = "Quin AUX PCM Capture",
  6609. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6610. .platform_name = "msm-pcm-routing",
  6611. .codec_name = "msm-stub-codec.1",
  6612. .codec_dai_name = "msm-stub-tx",
  6613. .no_pcm = 1,
  6614. .dpcm_capture = 1,
  6615. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6616. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6617. .ignore_suspend = 1,
  6618. },
  6619. };
  6620. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6621. /* WSA CDC DMA Backend DAI Links */
  6622. {
  6623. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6624. .stream_name = "WSA CDC DMA0 Playback",
  6625. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6626. .platform_name = "msm-pcm-routing",
  6627. .codec_name = "bolero_codec",
  6628. .codec_dai_name = "wsa_macro_rx1",
  6629. .no_pcm = 1,
  6630. .dpcm_playback = 1,
  6631. .init = &msm_wsa_cdc_dma_init,
  6632. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6633. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6634. .ignore_pmdown_time = 1,
  6635. .ignore_suspend = 1,
  6636. .ops = &msm_cdc_dma_be_ops,
  6637. },
  6638. {
  6639. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6640. .stream_name = "WSA CDC DMA1 Playback",
  6641. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6642. .platform_name = "msm-pcm-routing",
  6643. .codec_name = "bolero_codec",
  6644. .codec_dai_name = "wsa_macro_rx_mix",
  6645. .no_pcm = 1,
  6646. .dpcm_playback = 1,
  6647. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6648. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6649. .ignore_pmdown_time = 1,
  6650. .ignore_suspend = 1,
  6651. .ops = &msm_cdc_dma_be_ops,
  6652. },
  6653. {
  6654. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6655. .stream_name = "WSA CDC DMA1 Capture",
  6656. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6657. .platform_name = "msm-pcm-routing",
  6658. .codec_name = "bolero_codec",
  6659. .codec_dai_name = "wsa_macro_echo",
  6660. .no_pcm = 1,
  6661. .dpcm_capture = 1,
  6662. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6663. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6664. .ignore_suspend = 1,
  6665. .ops = &msm_cdc_dma_be_ops,
  6666. },
  6667. };
  6668. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6669. {
  6670. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6671. .stream_name = "VA CDC DMA0 Capture",
  6672. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6673. .platform_name = "msm-pcm-routing",
  6674. .codec_name = "bolero_codec",
  6675. .codec_dai_name = "va_macro_tx1",
  6676. .no_pcm = 1,
  6677. .dpcm_capture = 1,
  6678. .init = &msm_va_cdc_dma_init,
  6679. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6680. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6681. .ignore_suspend = 1,
  6682. .ops = &msm_cdc_dma_be_ops,
  6683. },
  6684. {
  6685. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6686. .stream_name = "VA CDC DMA1 Capture",
  6687. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6688. .platform_name = "msm-pcm-routing",
  6689. .codec_name = "bolero_codec",
  6690. .codec_dai_name = "va_macro_tx2",
  6691. .no_pcm = 1,
  6692. .dpcm_capture = 1,
  6693. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6694. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6695. .ignore_suspend = 1,
  6696. .ops = &msm_cdc_dma_be_ops,
  6697. },
  6698. };
  6699. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6700. {
  6701. .name = LPASS_BE_PRI_SPDIF_RX,
  6702. .stream_name = "Primary SPDIF Playback",
  6703. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6704. .platform_name = "msm-pcm-routing",
  6705. .codec_name = "msm-stub-codec.1",
  6706. .codec_dai_name = "msm-stub-rx",
  6707. .no_pcm = 1,
  6708. .dpcm_playback = 1,
  6709. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6710. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6711. .ops = &msm_spdif_be_ops,
  6712. .ignore_suspend = 1,
  6713. .ignore_pmdown_time = 1,
  6714. },
  6715. {
  6716. .name = LPASS_BE_PRI_SPDIF_TX,
  6717. .stream_name = "Primary SPDIF Capture",
  6718. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6719. .platform_name = "msm-pcm-routing",
  6720. .codec_name = "msm-stub-codec.1",
  6721. .codec_dai_name = "msm-stub-tx",
  6722. .no_pcm = 1,
  6723. .dpcm_capture = 1,
  6724. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6725. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6726. .ops = &msm_spdif_be_ops,
  6727. .ignore_suspend = 1,
  6728. },
  6729. {
  6730. .name = LPASS_BE_SEC_SPDIF_RX,
  6731. .stream_name = "Secondary SPDIF Playback",
  6732. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6733. .platform_name = "msm-pcm-routing",
  6734. .codec_name = "msm-stub-codec.1",
  6735. .codec_dai_name = "msm-stub-rx",
  6736. .no_pcm = 1,
  6737. .dpcm_playback = 1,
  6738. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6739. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6740. .ops = &msm_spdif_be_ops,
  6741. .ignore_suspend = 1,
  6742. .ignore_pmdown_time = 1,
  6743. },
  6744. {
  6745. .name = LPASS_BE_SEC_SPDIF_TX,
  6746. .stream_name = "Secondary SPDIF Capture",
  6747. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6748. .platform_name = "msm-pcm-routing",
  6749. .codec_name = "msm-stub-codec.1",
  6750. .codec_dai_name = "msm-stub-tx",
  6751. .no_pcm = 1,
  6752. .dpcm_capture = 1,
  6753. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6754. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6755. .ops = &msm_spdif_be_ops,
  6756. .ignore_suspend = 1,
  6757. },
  6758. };
  6759. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6760. ARRAY_SIZE(msm_common_dai_links) +
  6761. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6762. ARRAY_SIZE(msm_common_be_dai_links) +
  6763. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6764. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6765. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6766. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6767. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6768. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6769. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6770. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6771. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6772. {
  6773. int ret = 0;
  6774. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6775. &service_nb);
  6776. if (ret < 0)
  6777. pr_err("%s: Audio notifier register failed ret = %d\n",
  6778. __func__, ret);
  6779. return ret;
  6780. }
  6781. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6782. struct snd_ctl_elem_value *ucontrol)
  6783. {
  6784. int ret = 0;
  6785. int port_id;
  6786. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6787. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6788. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6789. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6790. (vad_enable < 0) || (vad_enable > 1) ||
  6791. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6792. pr_err("%s: Invalid arguments\n", __func__);
  6793. ret = -EINVAL;
  6794. goto done;
  6795. }
  6796. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6797. vad_enable, preroll_config, vad_intf);
  6798. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6799. if (ret) {
  6800. pr_err("%s: Invalid vad interface\n", __func__);
  6801. goto done;
  6802. }
  6803. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6804. done:
  6805. return ret;
  6806. }
  6807. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6808. {
  6809. int ret = 0;
  6810. uint32_t tasha_codec = 0;
  6811. ret = afe_cal_init_hwdep(card);
  6812. if (ret) {
  6813. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6814. ret = 0;
  6815. }
  6816. /* tasha late probe when it is present */
  6817. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6818. &tasha_codec);
  6819. if (ret) {
  6820. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6821. ret = 0;
  6822. } else {
  6823. if (tasha_codec) {
  6824. ret = msm_snd_card_tasha_late_probe(card);
  6825. if (ret)
  6826. dev_err(card->dev, "%s: tasha late probe err\n",
  6827. __func__);
  6828. }
  6829. }
  6830. return ret;
  6831. }
  6832. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6833. .name = "qcs405-snd-card",
  6834. .controls = msm_snd_controls,
  6835. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6836. .late_probe = msm_snd_card_codec_late_probe,
  6837. };
  6838. static int msm_populate_dai_link_component_of_node(
  6839. struct snd_soc_card *card)
  6840. {
  6841. int i, index, ret = 0;
  6842. struct device *cdev = card->dev;
  6843. struct snd_soc_dai_link *dai_link = card->dai_link;
  6844. struct device_node *np;
  6845. if (!cdev) {
  6846. pr_err("%s: Sound card device memory NULL\n", __func__);
  6847. return -ENODEV;
  6848. }
  6849. for (i = 0; i < card->num_links; i++) {
  6850. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6851. continue;
  6852. /* populate platform_of_node for snd card dai links */
  6853. if (dai_link[i].platform_name &&
  6854. !dai_link[i].platform_of_node) {
  6855. index = of_property_match_string(cdev->of_node,
  6856. "asoc-platform-names",
  6857. dai_link[i].platform_name);
  6858. if (index < 0) {
  6859. pr_err("%s: No match found for platform name: %s\n",
  6860. __func__, dai_link[i].platform_name);
  6861. ret = index;
  6862. goto err;
  6863. }
  6864. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6865. index);
  6866. if (!np) {
  6867. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6868. __func__, dai_link[i].platform_name,
  6869. index);
  6870. ret = -ENODEV;
  6871. goto err;
  6872. }
  6873. dai_link[i].platform_of_node = np;
  6874. dai_link[i].platform_name = NULL;
  6875. }
  6876. /* populate cpu_of_node for snd card dai links */
  6877. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6878. index = of_property_match_string(cdev->of_node,
  6879. "asoc-cpu-names",
  6880. dai_link[i].cpu_dai_name);
  6881. if (index >= 0) {
  6882. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6883. index);
  6884. if (!np) {
  6885. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6886. __func__,
  6887. dai_link[i].cpu_dai_name);
  6888. ret = -ENODEV;
  6889. goto err;
  6890. }
  6891. dai_link[i].cpu_of_node = np;
  6892. dai_link[i].cpu_dai_name = NULL;
  6893. }
  6894. }
  6895. /* populate codec_of_node for snd card dai links */
  6896. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6897. index = of_property_match_string(cdev->of_node,
  6898. "asoc-codec-names",
  6899. dai_link[i].codec_name);
  6900. if (index < 0)
  6901. continue;
  6902. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6903. index);
  6904. if (!np) {
  6905. pr_err("%s: retrieving phandle for codec %s failed\n",
  6906. __func__, dai_link[i].codec_name);
  6907. ret = -ENODEV;
  6908. goto err;
  6909. }
  6910. dai_link[i].codec_of_node = np;
  6911. dai_link[i].codec_name = NULL;
  6912. }
  6913. }
  6914. err:
  6915. return ret;
  6916. }
  6917. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6918. /* FrontEnd DAI Links */
  6919. {
  6920. .name = "MSMSTUB Media1",
  6921. .stream_name = "MultiMedia1",
  6922. .cpu_dai_name = "MultiMedia1",
  6923. .platform_name = "msm-pcm-dsp.0",
  6924. .dynamic = 1,
  6925. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6926. .dpcm_playback = 1,
  6927. .dpcm_capture = 1,
  6928. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6929. SND_SOC_DPCM_TRIGGER_POST},
  6930. .codec_dai_name = "snd-soc-dummy-dai",
  6931. .codec_name = "snd-soc-dummy",
  6932. .ignore_suspend = 1,
  6933. /* this dainlink has playback support */
  6934. .ignore_pmdown_time = 1,
  6935. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6936. },
  6937. };
  6938. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6939. /* Backend DAI Links */
  6940. {
  6941. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6942. .stream_name = "VA CDC DMA0 Capture",
  6943. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6944. .platform_name = "msm-pcm-routing",
  6945. .codec_name = "bolero_codec",
  6946. .codec_dai_name = "va_macro_tx1",
  6947. .no_pcm = 1,
  6948. .dpcm_capture = 1,
  6949. .init = &msm_va_cdc_dma_init,
  6950. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6951. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6952. .ignore_suspend = 1,
  6953. .ops = &msm_cdc_dma_be_ops,
  6954. },
  6955. {
  6956. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6957. .stream_name = "VA CDC DMA1 Capture",
  6958. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6959. .platform_name = "msm-pcm-routing",
  6960. .codec_name = "bolero_codec",
  6961. .codec_dai_name = "va_macro_tx2",
  6962. .no_pcm = 1,
  6963. .dpcm_capture = 1,
  6964. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6965. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6966. .ignore_suspend = 1,
  6967. .ops = &msm_cdc_dma_be_ops,
  6968. },
  6969. };
  6970. static struct snd_soc_dai_link msm_stub_dai_links[
  6971. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6972. ARRAY_SIZE(msm_stub_be_dai_links)];
  6973. struct snd_soc_card snd_soc_card_stub_msm = {
  6974. .name = "qcs405-stub-snd-card",
  6975. };
  6976. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6977. { .compatible = "qcom,qcs405-asoc-snd",
  6978. .data = "codec"},
  6979. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6980. .data = "stub_codec"},
  6981. {},
  6982. };
  6983. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6984. {
  6985. struct snd_soc_card *card = NULL;
  6986. struct snd_soc_dai_link *dailink;
  6987. int total_links = 0;
  6988. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6989. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6990. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  6991. const struct of_device_id *match;
  6992. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6993. int rc = 0;
  6994. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6995. if (!match) {
  6996. dev_err(dev, "%s: No DT match found for sound card\n",
  6997. __func__);
  6998. return NULL;
  6999. }
  7000. if (!strcmp(match->data, "codec")) {
  7001. card = &snd_soc_card_qcs405_msm;
  7002. memcpy(msm_qcs405_dai_links + total_links,
  7003. msm_common_dai_links,
  7004. sizeof(msm_common_dai_links));
  7005. total_links += ARRAY_SIZE(msm_common_dai_links);
  7006. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  7007. &wsa_bolero_codec);
  7008. if (rc) {
  7009. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  7010. __func__);
  7011. } else {
  7012. if (wsa_bolero_codec) {
  7013. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  7014. __func__);
  7015. memcpy(msm_qcs405_dai_links + total_links,
  7016. msm_bolero_fe_dai_links,
  7017. sizeof(msm_bolero_fe_dai_links));
  7018. total_links +=
  7019. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7020. }
  7021. }
  7022. memcpy(msm_qcs405_dai_links + total_links,
  7023. msm_common_misc_fe_dai_links,
  7024. sizeof(msm_common_misc_fe_dai_links));
  7025. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7026. memcpy(msm_qcs405_dai_links + total_links,
  7027. msm_common_be_dai_links,
  7028. sizeof(msm_common_be_dai_links));
  7029. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7030. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7031. &tasha_codec);
  7032. if (rc) {
  7033. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7034. __func__);
  7035. } else {
  7036. if (tasha_codec) {
  7037. memcpy(msm_qcs405_dai_links + total_links,
  7038. msm_tasha_be_dai_links,
  7039. sizeof(msm_tasha_be_dai_links));
  7040. total_links +=
  7041. ARRAY_SIZE(msm_tasha_be_dai_links);
  7042. }
  7043. }
  7044. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7045. &va_bolero_codec);
  7046. if (rc) {
  7047. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7048. __func__);
  7049. } else {
  7050. if (va_bolero_codec) {
  7051. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7052. __func__);
  7053. memcpy(msm_qcs405_dai_links + total_links,
  7054. msm_va_cdc_dma_be_dai_links,
  7055. sizeof(msm_va_cdc_dma_be_dai_links));
  7056. total_links +=
  7057. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7058. }
  7059. }
  7060. if (wsa_bolero_codec) {
  7061. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7062. __func__);
  7063. memcpy(msm_qcs405_dai_links + total_links,
  7064. msm_wsa_cdc_dma_be_dai_links,
  7065. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7066. total_links +=
  7067. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7068. }
  7069. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7070. &mi2s_audio_intf);
  7071. if (rc) {
  7072. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7073. __func__);
  7074. } else {
  7075. if (mi2s_audio_intf) {
  7076. memcpy(msm_qcs405_dai_links + total_links,
  7077. msm_mi2s_be_dai_links,
  7078. sizeof(msm_mi2s_be_dai_links));
  7079. total_links +=
  7080. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7081. }
  7082. }
  7083. rc = of_property_read_u32(dev->of_node,
  7084. "qcom,auxpcm-audio-intf",
  7085. &auxpcm_audio_intf);
  7086. if (rc) {
  7087. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7088. __func__);
  7089. } else {
  7090. if (auxpcm_audio_intf) {
  7091. memcpy(msm_qcs405_dai_links + total_links,
  7092. msm_auxpcm_be_dai_links,
  7093. sizeof(msm_auxpcm_be_dai_links));
  7094. total_links +=
  7095. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7096. }
  7097. }
  7098. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7099. &spdif_audio_intf);
  7100. if (rc) {
  7101. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7102. __func__);
  7103. } else {
  7104. if (spdif_audio_intf) {
  7105. memcpy(msm_qcs405_dai_links + total_links,
  7106. msm_spdif_be_dai_links,
  7107. sizeof(msm_spdif_be_dai_links));
  7108. total_links +=
  7109. ARRAY_SIZE(msm_spdif_be_dai_links);
  7110. /* enable spdif coax pins */
  7111. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7112. spdif_pin_ctl =
  7113. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7114. iowrite32(0xc0, spdif_cfg);
  7115. iowrite32(0x2220, spdif_pin_ctl);
  7116. }
  7117. }
  7118. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7119. &wcn_audio_intf);
  7120. if (rc) {
  7121. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7122. __func__);
  7123. } else {
  7124. if (wcn_audio_intf) {
  7125. memcpy(msm_qcs405_dai_links + total_links,
  7126. msm_wcn_be_dai_links,
  7127. sizeof(msm_wcn_be_dai_links));
  7128. total_links +=
  7129. ARRAY_SIZE(msm_wcn_be_dai_links);
  7130. }
  7131. }
  7132. dailink = msm_qcs405_dai_links;
  7133. } else if (!strcmp(match->data, "stub_codec")) {
  7134. card = &snd_soc_card_stub_msm;
  7135. memcpy(msm_stub_dai_links + total_links,
  7136. msm_stub_fe_dai_links,
  7137. sizeof(msm_stub_fe_dai_links));
  7138. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7139. memcpy(msm_stub_dai_links + total_links,
  7140. msm_stub_be_dai_links,
  7141. sizeof(msm_stub_be_dai_links));
  7142. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7143. dailink = msm_stub_dai_links;
  7144. }
  7145. if (card) {
  7146. card->dai_link = dailink;
  7147. card->num_links = total_links;
  7148. }
  7149. return card;
  7150. }
  7151. static int msm_wsa881x_init(struct snd_soc_component *component)
  7152. {
  7153. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7154. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7155. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7156. SPKR_L_BOOST, SPKR_L_VI};
  7157. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7158. SPKR_R_BOOST, SPKR_R_VI};
  7159. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7160. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7161. struct msm_asoc_mach_data *pdata;
  7162. struct snd_soc_dapm_context *dapm;
  7163. int ret = 0;
  7164. if (!component) {
  7165. pr_err("%s component is NULL\n", __func__);
  7166. return -EINVAL;
  7167. }
  7168. dapm = snd_soc_component_get_dapm(component);
  7169. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7170. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  7171. __func__, component->name);
  7172. wsa881x_set_channel_map(component, &spkleft_ports[0],
  7173. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7174. &ch_rate[0], &spkleft_port_types[0]);
  7175. if (dapm->component) {
  7176. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7177. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7178. }
  7179. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7180. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  7181. __func__, component->name);
  7182. wsa881x_set_channel_map(component, &spkright_ports[0],
  7183. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7184. &ch_rate[0], &spkright_port_types[0]);
  7185. if (dapm->component) {
  7186. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7187. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7188. }
  7189. } else {
  7190. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  7191. component->name);
  7192. ret = -EINVAL;
  7193. goto err;
  7194. }
  7195. pdata = snd_soc_card_get_drvdata(component->card);
  7196. if (pdata && pdata->codec_root)
  7197. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7198. component);
  7199. err:
  7200. return ret;
  7201. }
  7202. static int msm_init_wsa_dev(struct platform_device *pdev,
  7203. struct snd_soc_card *card)
  7204. {
  7205. struct device_node *wsa_of_node;
  7206. u32 wsa_max_devs;
  7207. u32 wsa_dev_cnt;
  7208. int i;
  7209. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7210. const char *wsa_auxdev_name_prefix[1];
  7211. char *dev_name_str = NULL;
  7212. int found = 0;
  7213. int ret = 0;
  7214. /* Get maximum WSA device count for this platform */
  7215. ret = of_property_read_u32(pdev->dev.of_node,
  7216. "qcom,wsa-max-devs", &wsa_max_devs);
  7217. if (ret) {
  7218. dev_info(&pdev->dev,
  7219. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7220. __func__, pdev->dev.of_node->full_name, ret);
  7221. card->num_aux_devs = 0;
  7222. return 0;
  7223. }
  7224. if (wsa_max_devs == 0) {
  7225. dev_warn(&pdev->dev,
  7226. "%s: Max WSA devices is 0 for this target?\n",
  7227. __func__);
  7228. card->num_aux_devs = 0;
  7229. return 0;
  7230. }
  7231. /* Get count of WSA device phandles for this platform */
  7232. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7233. "qcom,wsa-devs", NULL);
  7234. if (wsa_dev_cnt == -ENOENT) {
  7235. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7236. __func__);
  7237. goto err;
  7238. } else if (wsa_dev_cnt <= 0) {
  7239. dev_err(&pdev->dev,
  7240. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7241. __func__, wsa_dev_cnt);
  7242. ret = -EINVAL;
  7243. goto err;
  7244. }
  7245. /*
  7246. * Expect total phandles count to be NOT less than maximum possible
  7247. * WSA count. However, if it is less, then assign same value to
  7248. * max count as well.
  7249. */
  7250. if (wsa_dev_cnt < wsa_max_devs) {
  7251. dev_dbg(&pdev->dev,
  7252. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7253. __func__, wsa_max_devs, wsa_dev_cnt);
  7254. wsa_max_devs = wsa_dev_cnt;
  7255. }
  7256. /* Make sure prefix string passed for each WSA device */
  7257. ret = of_property_count_strings(pdev->dev.of_node,
  7258. "qcom,wsa-aux-dev-prefix");
  7259. if (ret != wsa_dev_cnt) {
  7260. dev_err(&pdev->dev,
  7261. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7262. __func__, wsa_dev_cnt, ret);
  7263. ret = -EINVAL;
  7264. goto err;
  7265. }
  7266. /*
  7267. * Alloc mem to store phandle and index info of WSA device, if already
  7268. * registered with ALSA core
  7269. */
  7270. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7271. sizeof(struct msm_wsa881x_dev_info),
  7272. GFP_KERNEL);
  7273. if (!wsa881x_dev_info) {
  7274. ret = -ENOMEM;
  7275. goto err;
  7276. }
  7277. /*
  7278. * search and check whether all WSA devices are already
  7279. * registered with ALSA core or not. If found a node, store
  7280. * the node and the index in a local array of struct for later
  7281. * use.
  7282. */
  7283. for (i = 0; i < wsa_dev_cnt; i++) {
  7284. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7285. "qcom,wsa-devs", i);
  7286. if (unlikely(!wsa_of_node)) {
  7287. /* we should not be here */
  7288. dev_err(&pdev->dev,
  7289. "%s: wsa dev node is not present\n",
  7290. __func__);
  7291. ret = -EINVAL;
  7292. goto err_free_dev_info;
  7293. }
  7294. if (soc_find_component(wsa_of_node, NULL)) {
  7295. /* WSA device registered with ALSA core */
  7296. wsa881x_dev_info[found].of_node = wsa_of_node;
  7297. wsa881x_dev_info[found].index = i;
  7298. found++;
  7299. if (found == wsa_max_devs)
  7300. break;
  7301. }
  7302. }
  7303. if (found < wsa_max_devs) {
  7304. dev_err(&pdev->dev,
  7305. "%s: failed to find %d components. Found only %d\n",
  7306. __func__, wsa_max_devs, found);
  7307. return -EPROBE_DEFER;
  7308. }
  7309. dev_info(&pdev->dev,
  7310. "%s: found %d wsa881x devices registered with ALSA core\n",
  7311. __func__, found);
  7312. card->num_aux_devs = wsa_max_devs;
  7313. card->num_configs = wsa_max_devs;
  7314. /* Alloc array of AUX devs struct */
  7315. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7316. sizeof(struct snd_soc_aux_dev),
  7317. GFP_KERNEL);
  7318. if (!msm_aux_dev) {
  7319. ret = -ENOMEM;
  7320. goto err_free_dev_info;
  7321. }
  7322. /* Alloc array of codec conf struct */
  7323. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7324. sizeof(struct snd_soc_codec_conf),
  7325. GFP_KERNEL);
  7326. if (!msm_codec_conf) {
  7327. ret = -ENOMEM;
  7328. goto err_free_aux_dev;
  7329. }
  7330. for (i = 0; i < card->num_aux_devs; i++) {
  7331. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7332. GFP_KERNEL);
  7333. if (!dev_name_str) {
  7334. ret = -ENOMEM;
  7335. goto err_free_cdc_conf;
  7336. }
  7337. ret = of_property_read_string_index(pdev->dev.of_node,
  7338. "qcom,wsa-aux-dev-prefix",
  7339. wsa881x_dev_info[i].index,
  7340. wsa_auxdev_name_prefix);
  7341. if (ret) {
  7342. dev_err(&pdev->dev,
  7343. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7344. __func__, ret);
  7345. ret = -EINVAL;
  7346. goto err_free_dev_name_str;
  7347. }
  7348. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7349. msm_aux_dev[i].name = dev_name_str;
  7350. msm_aux_dev[i].codec_name = NULL;
  7351. msm_aux_dev[i].codec_of_node =
  7352. wsa881x_dev_info[i].of_node;
  7353. msm_aux_dev[i].init = msm_wsa881x_init;
  7354. msm_codec_conf[i].dev_name = NULL;
  7355. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7356. msm_codec_conf[i].of_node =
  7357. wsa881x_dev_info[i].of_node;
  7358. }
  7359. card->codec_conf = msm_codec_conf;
  7360. card->aux_dev = msm_aux_dev;
  7361. return 0;
  7362. err_free_dev_name_str:
  7363. devm_kfree(&pdev->dev, dev_name_str);
  7364. err_free_cdc_conf:
  7365. devm_kfree(&pdev->dev, msm_codec_conf);
  7366. err_free_aux_dev:
  7367. devm_kfree(&pdev->dev, msm_aux_dev);
  7368. err_free_dev_info:
  7369. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7370. err:
  7371. return ret;
  7372. }
  7373. static int msm_csra66x0_init(struct snd_soc_component *component)
  7374. {
  7375. if (!component) {
  7376. pr_err("%s component is NULL\n", __func__);
  7377. return -EINVAL;
  7378. }
  7379. return 0;
  7380. }
  7381. static int msm_init_csra_dev(struct platform_device *pdev,
  7382. struct snd_soc_card *card)
  7383. {
  7384. struct device_node *csra_of_node;
  7385. u32 csra_max_devs;
  7386. u32 csra_dev_cnt;
  7387. char *dev_name_str = NULL;
  7388. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7389. const char *csra_auxdev_name_prefix[1];
  7390. int i;
  7391. int found = 0;
  7392. int ret = 0;
  7393. /* Get maximum CSRA device count for this platform */
  7394. ret = of_property_read_u32(pdev->dev.of_node,
  7395. "qcom,csra-max-devs", &csra_max_devs);
  7396. if (ret) {
  7397. dev_info(&pdev->dev,
  7398. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7399. __func__, pdev->dev.of_node->full_name, ret);
  7400. card->num_aux_devs = 0;
  7401. return 0;
  7402. }
  7403. if (csra_max_devs == 0) {
  7404. dev_warn(&pdev->dev,
  7405. "%s: Max CSRA devices is 0 for this target?\n",
  7406. __func__);
  7407. return 0;
  7408. }
  7409. /* Get count of CSRA device phandles for this platform */
  7410. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7411. "qcom,csra-devs", NULL);
  7412. if (csra_dev_cnt == -ENOENT) {
  7413. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7414. __func__);
  7415. goto err;
  7416. } else if (csra_dev_cnt <= 0) {
  7417. dev_err(&pdev->dev,
  7418. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7419. __func__, csra_dev_cnt);
  7420. ret = -EINVAL;
  7421. goto err;
  7422. }
  7423. /*
  7424. * Expect total phandles count to be NOT less than maximum possible
  7425. * CSRA count. However, if it is less, then assign same value to
  7426. * max count as well.
  7427. */
  7428. if (csra_dev_cnt < csra_max_devs) {
  7429. dev_dbg(&pdev->dev,
  7430. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7431. __func__, csra_max_devs, csra_dev_cnt);
  7432. csra_max_devs = csra_dev_cnt;
  7433. }
  7434. /* Make sure prefix string passed for each CSRA device */
  7435. ret = of_property_count_strings(pdev->dev.of_node,
  7436. "qcom,csra-aux-dev-prefix");
  7437. if (ret != csra_dev_cnt) {
  7438. dev_err(&pdev->dev,
  7439. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7440. __func__, csra_dev_cnt, ret);
  7441. ret = -EINVAL;
  7442. goto err;
  7443. }
  7444. /*
  7445. * Alloc mem to store phandle and index info of CSRA device, if already
  7446. * registered with ALSA core
  7447. */
  7448. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7449. sizeof(struct msm_csra66x0_dev_info),
  7450. GFP_KERNEL);
  7451. if (!csra66x0_dev_info) {
  7452. ret = -ENOMEM;
  7453. goto err;
  7454. }
  7455. /*
  7456. * search and check whether all CSRA devices are already
  7457. * registered with ALSA core or not. If found a node, store
  7458. * the node and the index in a local array of struct for later
  7459. * use.
  7460. */
  7461. for (i = 0; i < csra_dev_cnt; i++) {
  7462. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7463. "qcom,csra-devs", i);
  7464. if (unlikely(!csra_of_node)) {
  7465. /* we should not be here */
  7466. dev_err(&pdev->dev,
  7467. "%s: csra dev node is not present\n",
  7468. __func__);
  7469. ret = -EINVAL;
  7470. goto err_free_dev_info;
  7471. }
  7472. if (soc_find_component(csra_of_node, NULL)) {
  7473. /* CSRA device registered with ALSA core */
  7474. csra66x0_dev_info[found].of_node = csra_of_node;
  7475. csra66x0_dev_info[found].index = i;
  7476. found++;
  7477. if (found == csra_max_devs)
  7478. break;
  7479. }
  7480. }
  7481. if (found < csra_max_devs) {
  7482. dev_dbg(&pdev->dev,
  7483. "%s: failed to find %d components. Found only %d\n",
  7484. __func__, csra_max_devs, found);
  7485. return -EPROBE_DEFER;
  7486. }
  7487. dev_info(&pdev->dev,
  7488. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7489. __func__, found);
  7490. card->num_aux_devs = csra_max_devs;
  7491. card->num_configs = csra_max_devs;
  7492. /* Alloc array of AUX devs struct */
  7493. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7494. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7495. if (!msm_aux_dev) {
  7496. ret = -ENOMEM;
  7497. goto err_free_dev_info;
  7498. }
  7499. /* Alloc array of codec conf struct */
  7500. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7501. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7502. if (!msm_codec_conf) {
  7503. ret = -ENOMEM;
  7504. goto err_free_aux_dev;
  7505. }
  7506. for (i = 0; i < card->num_aux_devs; i++) {
  7507. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7508. GFP_KERNEL);
  7509. if (!dev_name_str) {
  7510. ret = -ENOMEM;
  7511. goto err_free_cdc_conf;
  7512. }
  7513. ret = of_property_read_string_index(pdev->dev.of_node,
  7514. "qcom,csra-aux-dev-prefix",
  7515. csra66x0_dev_info[i].index,
  7516. csra_auxdev_name_prefix);
  7517. if (ret) {
  7518. dev_err(&pdev->dev,
  7519. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7520. __func__, ret);
  7521. ret = -EINVAL;
  7522. goto err_free_dev_name_str;
  7523. }
  7524. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7525. msm_aux_dev[i].name = dev_name_str;
  7526. msm_aux_dev[i].codec_name = NULL;
  7527. msm_aux_dev[i].codec_of_node =
  7528. csra66x0_dev_info[i].of_node;
  7529. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7530. msm_codec_conf[i].dev_name = NULL;
  7531. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7532. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7533. }
  7534. card->codec_conf = msm_codec_conf;
  7535. card->aux_dev = msm_aux_dev;
  7536. return 0;
  7537. err_free_dev_name_str:
  7538. devm_kfree(&pdev->dev, dev_name_str);
  7539. err_free_cdc_conf:
  7540. devm_kfree(&pdev->dev, msm_codec_conf);
  7541. err_free_aux_dev:
  7542. devm_kfree(&pdev->dev, msm_aux_dev);
  7543. err_free_dev_info:
  7544. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7545. err:
  7546. return ret;
  7547. }
  7548. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7549. {
  7550. int count;
  7551. u32 mi2s_master_slave[MI2S_MAX];
  7552. int ret;
  7553. for (count = 0; count < MI2S_MAX; count++) {
  7554. mutex_init(&mi2s_intf_conf[count].lock);
  7555. mi2s_intf_conf[count].ref_cnt = 0;
  7556. }
  7557. ret = of_property_read_u32_array(pdev->dev.of_node,
  7558. "qcom,msm-mi2s-master",
  7559. mi2s_master_slave, MI2S_MAX);
  7560. if (ret) {
  7561. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7562. __func__);
  7563. } else {
  7564. for (count = 0; count < MI2S_MAX; count++) {
  7565. mi2s_intf_conf[count].msm_is_mi2s_master =
  7566. mi2s_master_slave[count];
  7567. }
  7568. }
  7569. }
  7570. static void msm_i2s_auxpcm_deinit(void)
  7571. {
  7572. int count;
  7573. for (count = 0; count < MI2S_MAX; count++) {
  7574. mutex_destroy(&mi2s_intf_conf[count].lock);
  7575. mi2s_intf_conf[count].ref_cnt = 0;
  7576. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7577. }
  7578. }
  7579. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7580. uint32_t busnum, uint32_t addr)
  7581. {
  7582. struct i2c_adapter *adap;
  7583. u8 rbuf;
  7584. struct i2c_msg msg;
  7585. int status = 0;
  7586. adap = i2c_get_adapter(busnum);
  7587. if (!adap) {
  7588. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7589. __func__, busnum);
  7590. return -EBUSY;
  7591. }
  7592. /* to test presence, read one byte from device */
  7593. msg.addr = addr;
  7594. msg.flags = I2C_M_RD;
  7595. msg.len = 1;
  7596. msg.buf = &rbuf;
  7597. status = i2c_transfer(adap, &msg, 1);
  7598. i2c_put_adapter(adap);
  7599. if (status != 1) {
  7600. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7601. __func__, addr);
  7602. return -ENODEV;
  7603. }
  7604. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7605. __func__, addr);
  7606. return 0;
  7607. }
  7608. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7609. struct snd_soc_card *card)
  7610. {
  7611. int i;
  7612. uint32_t ep92_busnum = 0;
  7613. uint32_t ep92_reg = 0;
  7614. const char *ep92_name = NULL;
  7615. struct snd_soc_dai_link *dai;
  7616. int rc = 0;
  7617. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7618. &ep92_busnum);
  7619. if (rc) {
  7620. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7621. return 0;
  7622. }
  7623. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7624. &ep92_reg);
  7625. if (rc) {
  7626. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7627. return 0;
  7628. }
  7629. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7630. &ep92_name);
  7631. if (rc) {
  7632. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7633. return 0;
  7634. }
  7635. /* check I2C bus for connected ep92 chip */
  7636. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7637. /* check a second time after a short delay */
  7638. msleep(20);
  7639. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7640. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7641. __func__);
  7642. /* continue with snd_card registration without ep92 */
  7643. return 0;
  7644. }
  7645. }
  7646. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7647. /* update codec info in MI2S dai link */
  7648. dai = &msm_mi2s_be_dai_links[0];
  7649. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7650. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7651. dev_dbg(&pdev->dev,
  7652. "%s: Set Sec MI2S dai to ep92 codec\n",
  7653. __func__);
  7654. dai->codec_name = ep92_name;
  7655. dai->codec_dai_name = "ep92-hdmi";
  7656. break;
  7657. }
  7658. dai++;
  7659. }
  7660. /* update codec info in SPDIF dai link */
  7661. dai = &msm_spdif_be_dai_links[0];
  7662. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7663. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7664. dev_dbg(&pdev->dev,
  7665. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7666. __func__);
  7667. dai->codec_name = ep92_name;
  7668. dai->codec_dai_name = "ep92-arc";
  7669. break;
  7670. }
  7671. dai++;
  7672. }
  7673. return 0;
  7674. }
  7675. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7676. {
  7677. struct snd_soc_card *card;
  7678. struct msm_asoc_mach_data *pdata;
  7679. int ret;
  7680. u32 val;
  7681. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7682. const char *micb_supply_str1 = "tdm-vdd-micb";
  7683. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7684. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7685. if (!pdev->dev.of_node) {
  7686. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7687. return -EINVAL;
  7688. }
  7689. pdata = devm_kzalloc(&pdev->dev,
  7690. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7691. if (!pdata)
  7692. return -ENOMEM;
  7693. /* test for ep92 HDMI bridge and update dai links accordingly */
  7694. ret = msm_detect_ep92_dev(pdev, card);
  7695. if (ret)
  7696. goto err;
  7697. card = populate_snd_card_dailinks(&pdev->dev);
  7698. if (!card) {
  7699. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7700. ret = -EINVAL;
  7701. goto err;
  7702. }
  7703. card->dev = &pdev->dev;
  7704. platform_set_drvdata(pdev, card);
  7705. snd_soc_card_set_drvdata(card, pdata);
  7706. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7707. if (ret) {
  7708. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7709. ret);
  7710. goto err;
  7711. }
  7712. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7713. if (ret) {
  7714. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7715. ret);
  7716. goto err;
  7717. }
  7718. ret = msm_populate_dai_link_component_of_node(card);
  7719. if (ret) {
  7720. ret = -EPROBE_DEFER;
  7721. goto err;
  7722. }
  7723. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7724. if (ret) {
  7725. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7726. val = 0;
  7727. }
  7728. if (val) {
  7729. pdata->codec_is_csra = true;
  7730. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  7731. ret = msm_init_csra_dev(pdev, card);
  7732. if (ret)
  7733. goto err;
  7734. } else {
  7735. pdata->codec_is_csra = false;
  7736. ret = msm_init_wsa_dev(pdev, card);
  7737. if (ret)
  7738. goto err;
  7739. }
  7740. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7741. "qcom,cdc-dmic01-gpios", 0);
  7742. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7743. "qcom,cdc-dmic23-gpios", 0);
  7744. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7745. "qcom,cdc-dmic45-gpios", 0);
  7746. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7747. "qcom,cdc-dmic67-gpios", 0);
  7748. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7749. "qcom,pri-mi2s-gpios", 0);
  7750. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7751. "qcom,sec-mi2s-gpios", 0);
  7752. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7753. "qcom,tert-mi2s-gpios", 0);
  7754. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7755. "qcom,quat-mi2s-gpios", 0);
  7756. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7757. "qcom,quin-mi2s-gpios", 0);
  7758. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7759. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7760. micb_supply_str1);
  7761. if (IS_ERR(pdata->tdm_micb_supply)) {
  7762. ret = PTR_ERR(pdata->tdm_micb_supply);
  7763. dev_err(&pdev->dev,
  7764. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7765. __func__, ret);
  7766. }
  7767. ret = of_property_read_u32(pdev->dev.of_node,
  7768. micb_voltage_str,
  7769. &pdata->tdm_micb_voltage);
  7770. if (ret) {
  7771. dev_err(&pdev->dev,
  7772. "%s:Looking up %s property in node %s failed\n",
  7773. __func__, micb_voltage_str,
  7774. pdev->dev.of_node->full_name);
  7775. }
  7776. ret = of_property_read_u32(pdev->dev.of_node,
  7777. micb_current_str,
  7778. &pdata->tdm_micb_current);
  7779. if (ret) {
  7780. dev_err(&pdev->dev,
  7781. "%s:Looking up %s property in node %s failed\n",
  7782. __func__, micb_current_str,
  7783. pdev->dev.of_node->full_name);
  7784. }
  7785. }
  7786. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7787. if (ret == -EPROBE_DEFER) {
  7788. if (codec_reg_done)
  7789. ret = -EINVAL;
  7790. goto err;
  7791. } else if (ret) {
  7792. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7793. ret);
  7794. goto err;
  7795. }
  7796. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7797. spdev = pdev;
  7798. ret = msm_mdf_mem_init();
  7799. if (ret)
  7800. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7801. ret);
  7802. msm_i2s_auxpcm_init(pdev);
  7803. is_initial_boot = true;
  7804. return 0;
  7805. err:
  7806. return ret;
  7807. }
  7808. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7809. {
  7810. audio_notifier_deregister("qcs405");
  7811. msm_i2s_auxpcm_deinit();
  7812. msm_mdf_mem_deinit();
  7813. return 0;
  7814. }
  7815. static struct platform_driver qcs405_asoc_machine_driver = {
  7816. .driver = {
  7817. .name = DRV_NAME,
  7818. .owner = THIS_MODULE,
  7819. .pm = &snd_soc_pm_ops,
  7820. .of_match_table = qcs405_asoc_machine_of_match,
  7821. },
  7822. .probe = msm_asoc_machine_probe,
  7823. .remove = msm_asoc_machine_remove,
  7824. };
  7825. module_platform_driver(qcs405_asoc_machine_driver);
  7826. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7827. MODULE_LICENSE("GPL v2");
  7828. MODULE_ALIAS("platform:" DRV_NAME);
  7829. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);