sde_rm.c 66 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s] " fmt, __func__
  6. #include "sde_kms.h"
  7. #include "sde_hw_lm.h"
  8. #include "sde_hw_ctl.h"
  9. #include "sde_hw_cdm.h"
  10. #include "sde_hw_dspp.h"
  11. #include "sde_hw_ds.h"
  12. #include "sde_hw_pingpong.h"
  13. #include "sde_hw_intf.h"
  14. #include "sde_hw_wb.h"
  15. #include "sde_encoder.h"
  16. #include "sde_connector.h"
  17. #include "sde_hw_dsc.h"
  18. #include "sde_hw_vdc.h"
  19. #include "sde_crtc.h"
  20. #include "sde_hw_qdss.h"
  21. #define RESERVED_BY_OTHER(h, r) \
  22. (((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
  23. ((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
  24. #define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
  25. #define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
  26. #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
  27. #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
  28. #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
  29. #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
  30. (t).num_comp_enc == (r).num_enc && \
  31. (t).num_intf == (r).num_intf && \
  32. (t).comp_type == (r).comp_type)
  33. #define IS_COMPATIBLE_PP_DSC(p, d) (p % 2 == d % 2)
  34. /* ~one vsync poll time for rsvp_nxt to cleared by modeset from commit thread */
  35. #define RM_NXT_CLEAR_POLL_TIMEOUT_US 16600
  36. /**
  37. * toplogy information to be used when ctl path version does not
  38. * support driving more than one interface per ctl_path
  39. */
  40. static const struct sde_rm_topology_def g_top_table[SDE_RM_TOPOLOGY_MAX] = {
  41. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  42. MSM_DISPLAY_COMPRESSION_NONE },
  43. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  44. MSM_DISPLAY_COMPRESSION_NONE },
  45. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  46. MSM_DISPLAY_COMPRESSION_DSC },
  47. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true,
  48. MSM_DISPLAY_COMPRESSION_NONE },
  49. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true,
  50. MSM_DISPLAY_COMPRESSION_DSC },
  51. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  52. MSM_DISPLAY_COMPRESSION_NONE },
  53. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  54. MSM_DISPLAY_COMPRESSION_DSC },
  55. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  56. MSM_DISPLAY_COMPRESSION_DSC },
  57. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  58. MSM_DISPLAY_COMPRESSION_NONE },
  59. };
  60. /**
  61. * topology information to be used when the ctl path version
  62. * is SDE_CTL_CFG_VERSION_1_0_0
  63. */
  64. static const struct sde_rm_topology_def g_top_table_v1[SDE_RM_TOPOLOGY_MAX] = {
  65. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  66. MSM_DISPLAY_COMPRESSION_NONE },
  67. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  68. MSM_DISPLAY_COMPRESSION_NONE },
  69. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  70. MSM_DISPLAY_COMPRESSION_DSC },
  71. { SDE_RM_TOPOLOGY_SINGLEPIPE_VDC, 1, 1, 1, 1, false,
  72. MSM_DISPLAY_COMPRESSION_VDC },
  73. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 1, false,
  74. MSM_DISPLAY_COMPRESSION_NONE },
  75. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 1, false,
  76. MSM_DISPLAY_COMPRESSION_DSC },
  77. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  78. MSM_DISPLAY_COMPRESSION_NONE },
  79. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  80. MSM_DISPLAY_COMPRESSION_DSC },
  81. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC, 2, 1, 1, 1, false,
  82. MSM_DISPLAY_COMPRESSION_VDC },
  83. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  84. MSM_DISPLAY_COMPRESSION_DSC },
  85. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, false,
  86. MSM_DISPLAY_COMPRESSION_NONE },
  87. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE, 4, 0, 2, 1, false,
  88. MSM_DISPLAY_COMPRESSION_NONE },
  89. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE_DSC, 4, 3, 2, 1, false,
  90. MSM_DISPLAY_COMPRESSION_DSC },
  91. { SDE_RM_TOPOLOGY_QUADPIPE_DSCMERGE, 4, 4, 2, 1, false,
  92. MSM_DISPLAY_COMPRESSION_DSC },
  93. { SDE_RM_TOPOLOGY_QUADPIPE_DSC4HSMERGE, 4, 4, 1, 1, false,
  94. MSM_DISPLAY_COMPRESSION_DSC },
  95. };
  96. /**
  97. * struct sde_rm_requirements - Reservation requirements parameter bundle
  98. * @top_ctrl: topology control preference from kernel client
  99. * @top: selected topology for the display
  100. * @hw_res: Hardware resources required as reported by the encoders
  101. */
  102. struct sde_rm_requirements {
  103. uint64_t top_ctrl;
  104. const struct sde_rm_topology_def *topology;
  105. struct sde_encoder_hw_resources hw_res;
  106. };
  107. /**
  108. * struct sde_rm_rsvp - Use Case Reservation tagging structure
  109. * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
  110. * By using as a tag, rather than lists of pointers to HW blocks used
  111. * we can avoid some list management since we don't know how many blocks
  112. * of each type a given use case may require.
  113. * @list: List head for list of all reservations
  114. * @seq: Global RSVP sequence number for debugging, especially for
  115. * differentiating differenct allocations for same encoder.
  116. * @enc_id: Reservations are tracked by Encoder DRM object ID.
  117. * CRTCs may be connected to multiple Encoders.
  118. * An encoder or connector id identifies the display path.
  119. * @topology DRM<->HW topology use case
  120. */
  121. struct sde_rm_rsvp {
  122. struct list_head list;
  123. uint32_t seq;
  124. uint32_t enc_id;
  125. enum sde_rm_topology_name topology;
  126. };
  127. /**
  128. * struct sde_rm_hw_blk - hardware block tracking list member
  129. * @list: List head for list of all hardware blocks tracking items
  130. * @rsvp: Pointer to use case reservation if reserved by a client
  131. * @rsvp_nxt: Temporary pointer used during reservation to the incoming
  132. * request. Will be swapped into rsvp if proposal is accepted
  133. * @type: Type of hardware block this structure tracks
  134. * @id: Hardware ID number, within it's own space, ie. LM_X
  135. * @catalog: Pointer to the hardware catalog entry for this block
  136. * @hw: Pointer to the hardware register access object for this block
  137. */
  138. struct sde_rm_hw_blk {
  139. struct list_head list;
  140. struct sde_rm_rsvp *rsvp;
  141. struct sde_rm_rsvp *rsvp_nxt;
  142. enum sde_hw_blk_type type;
  143. uint32_t id;
  144. struct sde_hw_blk *hw;
  145. };
  146. /**
  147. * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
  148. */
  149. enum sde_rm_dbg_rsvp_stage {
  150. SDE_RM_STAGE_BEGIN,
  151. SDE_RM_STAGE_AFTER_CLEAR,
  152. SDE_RM_STAGE_AFTER_RSVPNEXT,
  153. SDE_RM_STAGE_FINAL
  154. };
  155. static void _sde_rm_inc_resource_info_lm(struct sde_rm *rm,
  156. struct msm_resource_caps_info *avail_res,
  157. struct sde_rm_hw_blk *blk)
  158. {
  159. struct sde_rm_hw_blk *blk2;
  160. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  161. avail_res->num_lm++;
  162. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  163. /* Check for 3d muxes by comparing paired lms */
  164. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  165. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  166. /*
  167. * If lm2 is free, or
  168. * lm1 & lm2 reserved by same enc, check mask
  169. */
  170. if ((!blk2->rsvp || (blk->rsvp &&
  171. blk2->rsvp->enc_id == blk->rsvp->enc_id
  172. && lm_cfg->id > lm_cfg2->id)) &&
  173. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  174. avail_res->num_3dmux++;
  175. }
  176. }
  177. static void _sde_rm_dec_resource_info_lm(struct sde_rm *rm,
  178. struct msm_resource_caps_info *avail_res,
  179. struct sde_rm_hw_blk *blk)
  180. {
  181. struct sde_rm_hw_blk *blk2;
  182. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  183. avail_res->num_lm--;
  184. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  185. /* Check for 3d muxes by comparing paired lms */
  186. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  187. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  188. /* If lm2 is free and lm1 is now being reserved */
  189. if (!blk2->rsvp &&
  190. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  191. avail_res->num_3dmux--;
  192. }
  193. }
  194. static void _sde_rm_inc_resource_info(struct sde_rm *rm,
  195. struct msm_resource_caps_info *avail_res,
  196. struct sde_rm_hw_blk *blk)
  197. {
  198. enum sde_hw_blk_type type = blk->type;
  199. if (type == SDE_HW_BLK_LM)
  200. _sde_rm_inc_resource_info_lm(rm, avail_res, blk);
  201. else if (type == SDE_HW_BLK_CTL)
  202. avail_res->num_ctl++;
  203. else if (type == SDE_HW_BLK_DSC)
  204. avail_res->num_dsc++;
  205. else if (type == SDE_HW_BLK_VDC)
  206. avail_res->num_vdc++;
  207. }
  208. static void _sde_rm_dec_resource_info(struct sde_rm *rm,
  209. struct msm_resource_caps_info *avail_res,
  210. struct sde_rm_hw_blk *blk)
  211. {
  212. enum sde_hw_blk_type type = blk->type;
  213. if (type == SDE_HW_BLK_LM)
  214. _sde_rm_dec_resource_info_lm(rm, avail_res, blk);
  215. else if (type == SDE_HW_BLK_CTL)
  216. avail_res->num_ctl--;
  217. else if (type == SDE_HW_BLK_DSC)
  218. avail_res->num_dsc--;
  219. else if (type == SDE_HW_BLK_VDC)
  220. avail_res->num_vdc--;
  221. }
  222. void sde_rm_get_resource_info(struct sde_rm *rm,
  223. struct drm_encoder *drm_enc,
  224. struct msm_resource_caps_info *avail_res)
  225. {
  226. struct sde_rm_hw_blk *blk;
  227. enum sde_hw_blk_type type;
  228. struct sde_rm_rsvp rsvp;
  229. memcpy(avail_res, &rm->avail_res,
  230. sizeof(rm->avail_res));
  231. if (!drm_enc)
  232. return;
  233. rsvp.enc_id = drm_enc->base.id;
  234. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  235. list_for_each_entry(blk, &rm->hw_blks[type], list)
  236. if (blk->rsvp && blk->rsvp->enc_id == rsvp.enc_id)
  237. _sde_rm_inc_resource_info(rm, avail_res, blk);
  238. }
  239. static void _sde_rm_print_rsvps(
  240. struct sde_rm *rm,
  241. enum sde_rm_dbg_rsvp_stage stage)
  242. {
  243. struct sde_rm_rsvp *rsvp;
  244. struct sde_rm_hw_blk *blk;
  245. enum sde_hw_blk_type type;
  246. SDE_DEBUG("%d\n", stage);
  247. list_for_each_entry(rsvp, &rm->rsvps, list) {
  248. SDE_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
  249. rsvp->enc_id, rsvp->topology);
  250. SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
  251. }
  252. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  253. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  254. if (!blk->rsvp && !blk->rsvp_nxt)
  255. continue;
  256. SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
  257. (blk->rsvp) ? blk->rsvp->seq : 0,
  258. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  259. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  260. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  261. blk->type, blk->id);
  262. SDE_EVT32(stage,
  263. (blk->rsvp) ? blk->rsvp->seq : 0,
  264. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  265. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  266. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  267. blk->type, blk->id);
  268. }
  269. }
  270. }
  271. static void _sde_rm_print_rsvps_by_type(
  272. struct sde_rm *rm,
  273. enum sde_hw_blk_type type)
  274. {
  275. struct sde_rm_hw_blk *blk;
  276. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  277. if (!blk->rsvp && !blk->rsvp_nxt)
  278. continue;
  279. SDE_ERROR("rsvp[s%ue%u->s%ue%u] %d %d\n",
  280. (blk->rsvp) ? blk->rsvp->seq : 0,
  281. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  282. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  283. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  284. blk->type, blk->id);
  285. SDE_EVT32((blk->rsvp) ? blk->rsvp->seq : 0,
  286. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  287. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  288. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  289. blk->type, blk->id);
  290. }
  291. }
  292. struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
  293. {
  294. return rm->hw_mdp;
  295. }
  296. void sde_rm_init_hw_iter(
  297. struct sde_rm_hw_iter *iter,
  298. uint32_t enc_id,
  299. enum sde_hw_blk_type type)
  300. {
  301. memset(iter, 0, sizeof(*iter));
  302. iter->enc_id = enc_id;
  303. iter->type = type;
  304. }
  305. enum sde_rm_topology_name sde_rm_get_topology_name(struct sde_rm *rm,
  306. struct msm_display_topology topology)
  307. {
  308. int i;
  309. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  310. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  311. topology))
  312. return rm->topology_tbl[i].top_name;
  313. return SDE_RM_TOPOLOGY_NONE;
  314. }
  315. static bool _sde_rm_get_hw_locked(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  316. {
  317. struct list_head *blk_list;
  318. if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
  319. SDE_ERROR("invalid rm\n");
  320. return false;
  321. }
  322. i->hw = NULL;
  323. blk_list = &rm->hw_blks[i->type];
  324. if (i->blk && (&i->blk->list == blk_list)) {
  325. SDE_DEBUG("attempt resume iteration past last\n");
  326. return false;
  327. }
  328. i->blk = list_prepare_entry(i->blk, blk_list, list);
  329. list_for_each_entry_continue(i->blk, blk_list, list) {
  330. struct sde_rm_rsvp *rsvp = i->blk->rsvp;
  331. if (i->blk->type != i->type) {
  332. SDE_ERROR("found incorrect block type %d on %d list\n",
  333. i->blk->type, i->type);
  334. return false;
  335. }
  336. if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
  337. i->hw = i->blk->hw;
  338. SDE_DEBUG("found type %d id %d for enc %d\n",
  339. i->type, i->blk->id, i->enc_id);
  340. return true;
  341. }
  342. }
  343. SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
  344. return false;
  345. }
  346. static bool _sde_rm_request_hw_blk_locked(struct sde_rm *rm,
  347. struct sde_rm_hw_request *hw_blk_info)
  348. {
  349. struct list_head *blk_list;
  350. struct sde_rm_hw_blk *blk = NULL;
  351. if (!rm || !hw_blk_info || hw_blk_info->type >= SDE_HW_BLK_MAX) {
  352. SDE_ERROR("invalid rm\n");
  353. return false;
  354. }
  355. hw_blk_info->hw = NULL;
  356. blk_list = &rm->hw_blks[hw_blk_info->type];
  357. blk = list_prepare_entry(blk, blk_list, list);
  358. list_for_each_entry_continue(blk, blk_list, list) {
  359. if (blk->type != hw_blk_info->type) {
  360. SDE_ERROR("found incorrect block type %d on %d list\n",
  361. blk->type, hw_blk_info->type);
  362. return false;
  363. }
  364. if (blk->hw->id == hw_blk_info->id) {
  365. hw_blk_info->hw = blk->hw;
  366. SDE_DEBUG("found type %d id %d\n",
  367. blk->type, blk->id);
  368. return true;
  369. }
  370. }
  371. SDE_DEBUG("no match, type %d id %d\n", hw_blk_info->type,
  372. hw_blk_info->id);
  373. return false;
  374. }
  375. bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  376. {
  377. bool ret;
  378. mutex_lock(&rm->rm_lock);
  379. ret = _sde_rm_get_hw_locked(rm, i);
  380. mutex_unlock(&rm->rm_lock);
  381. return ret;
  382. }
  383. bool sde_rm_request_hw_blk(struct sde_rm *rm, struct sde_rm_hw_request *hw)
  384. {
  385. bool ret;
  386. mutex_lock(&rm->rm_lock);
  387. ret = _sde_rm_request_hw_blk_locked(rm, hw);
  388. mutex_unlock(&rm->rm_lock);
  389. return ret;
  390. }
  391. static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, void *hw)
  392. {
  393. switch (type) {
  394. case SDE_HW_BLK_LM:
  395. sde_hw_lm_destroy(hw);
  396. break;
  397. case SDE_HW_BLK_DSPP:
  398. sde_hw_dspp_destroy(hw);
  399. break;
  400. case SDE_HW_BLK_DS:
  401. sde_hw_ds_destroy(hw);
  402. break;
  403. case SDE_HW_BLK_CTL:
  404. sde_hw_ctl_destroy(hw);
  405. break;
  406. case SDE_HW_BLK_CDM:
  407. sde_hw_cdm_destroy(hw);
  408. break;
  409. case SDE_HW_BLK_PINGPONG:
  410. sde_hw_pingpong_destroy(hw);
  411. break;
  412. case SDE_HW_BLK_INTF:
  413. sde_hw_intf_destroy(hw);
  414. break;
  415. case SDE_HW_BLK_WB:
  416. sde_hw_wb_destroy(hw);
  417. break;
  418. case SDE_HW_BLK_DSC:
  419. sde_hw_dsc_destroy(hw);
  420. break;
  421. case SDE_HW_BLK_VDC:
  422. sde_hw_vdc_destroy(hw);
  423. break;
  424. case SDE_HW_BLK_QDSS:
  425. sde_hw_qdss_destroy(hw);
  426. break;
  427. case SDE_HW_BLK_SSPP:
  428. /* SSPPs are not managed by the resource manager */
  429. case SDE_HW_BLK_TOP:
  430. /* Top is a singleton, not managed in hw_blks list */
  431. case SDE_HW_BLK_MAX:
  432. default:
  433. SDE_ERROR("unsupported block type %d\n", type);
  434. break;
  435. }
  436. }
  437. int sde_rm_destroy(struct sde_rm *rm)
  438. {
  439. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  440. struct sde_rm_hw_blk *hw_cur, *hw_nxt;
  441. enum sde_hw_blk_type type;
  442. if (!rm) {
  443. SDE_ERROR("invalid rm\n");
  444. return -EINVAL;
  445. }
  446. list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
  447. list_del(&rsvp_cur->list);
  448. kfree(rsvp_cur);
  449. }
  450. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  451. list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
  452. list) {
  453. list_del(&hw_cur->list);
  454. _sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
  455. kfree(hw_cur);
  456. }
  457. }
  458. sde_hw_mdp_destroy(rm->hw_mdp);
  459. rm->hw_mdp = NULL;
  460. mutex_destroy(&rm->rm_lock);
  461. return 0;
  462. }
  463. static int _sde_rm_hw_blk_create(
  464. struct sde_rm *rm,
  465. struct sde_mdss_cfg *cat,
  466. void __iomem *mmio,
  467. enum sde_hw_blk_type type,
  468. uint32_t id,
  469. void *hw_catalog_info)
  470. {
  471. struct sde_rm_hw_blk *blk;
  472. struct sde_hw_mdp *hw_mdp;
  473. void *hw;
  474. hw_mdp = rm->hw_mdp;
  475. switch (type) {
  476. case SDE_HW_BLK_LM:
  477. hw = sde_hw_lm_init(id, mmio, cat);
  478. break;
  479. case SDE_HW_BLK_DSPP:
  480. hw = sde_hw_dspp_init(id, mmio, cat);
  481. break;
  482. case SDE_HW_BLK_DS:
  483. hw = sde_hw_ds_init(id, mmio, cat);
  484. break;
  485. case SDE_HW_BLK_CTL:
  486. hw = sde_hw_ctl_init(id, mmio, cat);
  487. break;
  488. case SDE_HW_BLK_CDM:
  489. hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
  490. break;
  491. case SDE_HW_BLK_PINGPONG:
  492. hw = sde_hw_pingpong_init(id, mmio, cat);
  493. break;
  494. case SDE_HW_BLK_INTF:
  495. hw = sde_hw_intf_init(id, mmio, cat);
  496. break;
  497. case SDE_HW_BLK_WB:
  498. hw = sde_hw_wb_init(id, mmio, cat, hw_mdp);
  499. break;
  500. case SDE_HW_BLK_DSC:
  501. hw = sde_hw_dsc_init(id, mmio, cat);
  502. break;
  503. case SDE_HW_BLK_VDC:
  504. hw = sde_hw_vdc_init(id, mmio, cat);
  505. break;
  506. case SDE_HW_BLK_QDSS:
  507. hw = sde_hw_qdss_init(id, mmio, cat);
  508. break;
  509. case SDE_HW_BLK_SSPP:
  510. /* SSPPs are not managed by the resource manager */
  511. case SDE_HW_BLK_TOP:
  512. /* Top is a singleton, not managed in hw_blks list */
  513. case SDE_HW_BLK_MAX:
  514. default:
  515. SDE_ERROR("unsupported block type %d\n", type);
  516. return -EINVAL;
  517. }
  518. if (IS_ERR_OR_NULL(hw)) {
  519. SDE_ERROR("failed hw object creation: type %d, err %ld\n",
  520. type, PTR_ERR(hw));
  521. return -EFAULT;
  522. }
  523. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  524. if (!blk) {
  525. _sde_rm_hw_destroy(type, hw);
  526. return -ENOMEM;
  527. }
  528. blk->type = type;
  529. blk->id = id;
  530. blk->hw = hw;
  531. list_add_tail(&blk->list, &rm->hw_blks[type]);
  532. _sde_rm_inc_resource_info(rm, &rm->avail_res, blk);
  533. return 0;
  534. }
  535. static int _sde_rm_hw_blk_create_new(struct sde_rm *rm,
  536. struct sde_mdss_cfg *cat,
  537. void __iomem *mmio)
  538. {
  539. int i, rc = 0;
  540. for (i = 0; i < cat->dspp_count; i++) {
  541. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
  542. cat->dspp[i].id, &cat->dspp[i]);
  543. if (rc) {
  544. SDE_ERROR("failed: dspp hw not available\n");
  545. goto fail;
  546. }
  547. }
  548. if (cat->mdp[0].has_dest_scaler) {
  549. for (i = 0; i < cat->ds_count; i++) {
  550. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DS,
  551. cat->ds[i].id, &cat->ds[i]);
  552. if (rc) {
  553. SDE_ERROR("failed: ds hw not available\n");
  554. goto fail;
  555. }
  556. }
  557. }
  558. for (i = 0; i < cat->pingpong_count; i++) {
  559. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
  560. cat->pingpong[i].id, &cat->pingpong[i]);
  561. if (rc) {
  562. SDE_ERROR("failed: pp hw not available\n");
  563. goto fail;
  564. }
  565. }
  566. for (i = 0; i < cat->dsc_count; i++) {
  567. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSC,
  568. cat->dsc[i].id, &cat->dsc[i]);
  569. if (rc) {
  570. SDE_ERROR("failed: dsc hw not available\n");
  571. goto fail;
  572. }
  573. }
  574. for (i = 0; i < cat->vdc_count; i++) {
  575. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_VDC,
  576. cat->vdc[i].id, &cat->vdc[i]);
  577. if (rc) {
  578. SDE_ERROR("failed: vdc hw not available\n");
  579. goto fail;
  580. }
  581. }
  582. for (i = 0; i < cat->intf_count; i++) {
  583. if (cat->intf[i].type == INTF_NONE) {
  584. SDE_DEBUG("skip intf %d with type none\n", i);
  585. continue;
  586. }
  587. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
  588. cat->intf[i].id, &cat->intf[i]);
  589. if (rc) {
  590. SDE_ERROR("failed: intf hw not available\n");
  591. goto fail;
  592. }
  593. }
  594. for (i = 0; i < cat->wb_count; i++) {
  595. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
  596. cat->wb[i].id, &cat->wb[i]);
  597. if (rc) {
  598. SDE_ERROR("failed: wb hw not available\n");
  599. goto fail;
  600. }
  601. }
  602. for (i = 0; i < cat->ctl_count; i++) {
  603. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
  604. cat->ctl[i].id, &cat->ctl[i]);
  605. if (rc) {
  606. SDE_ERROR("failed: ctl hw not available\n");
  607. goto fail;
  608. }
  609. }
  610. for (i = 0; i < cat->cdm_count; i++) {
  611. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
  612. cat->cdm[i].id, &cat->cdm[i]);
  613. if (rc) {
  614. SDE_ERROR("failed: cdm hw not available\n");
  615. goto fail;
  616. }
  617. }
  618. for (i = 0; i < cat->qdss_count; i++) {
  619. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_QDSS,
  620. cat->qdss[i].id, &cat->qdss[i]);
  621. if (rc) {
  622. SDE_ERROR("failed: qdss hw not available\n");
  623. goto fail;
  624. }
  625. }
  626. fail:
  627. return rc;
  628. }
  629. int sde_rm_init(struct sde_rm *rm,
  630. struct sde_mdss_cfg *cat,
  631. void __iomem *mmio,
  632. struct drm_device *dev)
  633. {
  634. int i, rc = 0;
  635. enum sde_hw_blk_type type;
  636. if (!rm || !cat || !mmio || !dev) {
  637. SDE_ERROR("invalid input params\n");
  638. return -EINVAL;
  639. }
  640. /* Clear, setup lists */
  641. memset(rm, 0, sizeof(*rm));
  642. mutex_init(&rm->rm_lock);
  643. INIT_LIST_HEAD(&rm->rsvps);
  644. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  645. INIT_LIST_HEAD(&rm->hw_blks[type]);
  646. rm->dev = dev;
  647. if (IS_SDE_CTL_REV_100(cat->ctl_rev))
  648. rm->topology_tbl = g_top_table_v1;
  649. else
  650. rm->topology_tbl = g_top_table;
  651. /* Some of the sub-blocks require an mdptop to be created */
  652. rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
  653. if (IS_ERR_OR_NULL(rm->hw_mdp)) {
  654. rc = PTR_ERR(rm->hw_mdp);
  655. rm->hw_mdp = NULL;
  656. SDE_ERROR("failed: mdp hw not available\n");
  657. goto fail;
  658. }
  659. /* Interrogate HW catalog and create tracking items for hw blocks */
  660. for (i = 0; i < cat->mixer_count; i++) {
  661. struct sde_lm_cfg *lm = &cat->mixer[i];
  662. if (lm->pingpong == PINGPONG_MAX) {
  663. SDE_ERROR("mixer %d without pingpong\n", lm->id);
  664. goto fail;
  665. }
  666. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
  667. cat->mixer[i].id, &cat->mixer[i]);
  668. if (rc) {
  669. SDE_ERROR("failed: lm hw not available\n");
  670. goto fail;
  671. }
  672. if (!rm->lm_max_width) {
  673. rm->lm_max_width = lm->sblk->maxwidth;
  674. } else if (rm->lm_max_width != lm->sblk->maxwidth) {
  675. /*
  676. * Don't expect to have hw where lm max widths differ.
  677. * If found, take the min.
  678. */
  679. SDE_ERROR("unsupported: lm maxwidth differs\n");
  680. if (rm->lm_max_width > lm->sblk->maxwidth)
  681. rm->lm_max_width = lm->sblk->maxwidth;
  682. }
  683. }
  684. rc = _sde_rm_hw_blk_create_new(rm, cat, mmio);
  685. if (!rc)
  686. return 0;
  687. fail:
  688. sde_rm_destroy(rm);
  689. return rc;
  690. }
  691. static bool _sde_rm_check_lm(
  692. struct sde_rm *rm,
  693. struct sde_rm_rsvp *rsvp,
  694. struct sde_rm_requirements *reqs,
  695. const struct sde_lm_cfg *lm_cfg,
  696. struct sde_rm_hw_blk *lm,
  697. struct sde_rm_hw_blk **dspp,
  698. struct sde_rm_hw_blk **ds,
  699. struct sde_rm_hw_blk **pp)
  700. {
  701. bool is_valid_dspp, is_valid_ds, ret = true;
  702. is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
  703. is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
  704. /**
  705. * RM_RQ_X: specification of which LMs to choose
  706. * is_valid_X: indicates whether LM is tied with block X
  707. * ret: true if given LM matches the user requirement,
  708. * false otherwise
  709. */
  710. if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
  711. ret = (is_valid_dspp && is_valid_ds);
  712. else if (RM_RQ_DSPP(reqs))
  713. ret = is_valid_dspp;
  714. else if (RM_RQ_DS(reqs))
  715. ret = is_valid_ds;
  716. if (!ret) {
  717. SDE_DEBUG(
  718. "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
  719. lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
  720. lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
  721. lm_cfg->ds);
  722. return ret;
  723. }
  724. return true;
  725. }
  726. static bool _sde_rm_reserve_dspp(
  727. struct sde_rm *rm,
  728. struct sde_rm_rsvp *rsvp,
  729. const struct sde_lm_cfg *lm_cfg,
  730. struct sde_rm_hw_blk *lm,
  731. struct sde_rm_hw_blk **dspp)
  732. {
  733. struct sde_rm_hw_iter iter;
  734. if (lm_cfg->dspp != DSPP_MAX) {
  735. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
  736. while (_sde_rm_get_hw_locked(rm, &iter)) {
  737. if (iter.blk->id == lm_cfg->dspp) {
  738. *dspp = iter.blk;
  739. break;
  740. }
  741. }
  742. if (!*dspp) {
  743. SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
  744. lm_cfg->dspp);
  745. return false;
  746. }
  747. if (RESERVED_BY_OTHER(*dspp, rsvp)) {
  748. SDE_DEBUG("lm %d dspp %d already reserved\n",
  749. lm->id, (*dspp)->id);
  750. return false;
  751. }
  752. }
  753. return true;
  754. }
  755. static bool _sde_rm_reserve_ds(
  756. struct sde_rm *rm,
  757. struct sde_rm_rsvp *rsvp,
  758. const struct sde_lm_cfg *lm_cfg,
  759. struct sde_rm_hw_blk *lm,
  760. struct sde_rm_hw_blk **ds)
  761. {
  762. struct sde_rm_hw_iter iter;
  763. if (lm_cfg->ds != DS_MAX) {
  764. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DS);
  765. while (_sde_rm_get_hw_locked(rm, &iter)) {
  766. if (iter.blk->id == lm_cfg->ds) {
  767. *ds = iter.blk;
  768. break;
  769. }
  770. }
  771. if (!*ds) {
  772. SDE_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
  773. lm_cfg->ds);
  774. return false;
  775. }
  776. if (RESERVED_BY_OTHER(*ds, rsvp)) {
  777. SDE_DEBUG("lm %d ds %d already reserved\n",
  778. lm->id, (*ds)->id);
  779. return false;
  780. }
  781. }
  782. return true;
  783. }
  784. static bool _sde_rm_reserve_pp(
  785. struct sde_rm *rm,
  786. struct sde_rm_rsvp *rsvp,
  787. struct sde_rm_requirements *reqs,
  788. const struct sde_lm_cfg *lm_cfg,
  789. const struct sde_pingpong_cfg *pp_cfg,
  790. struct sde_rm_hw_blk *lm,
  791. struct sde_rm_hw_blk **dspp,
  792. struct sde_rm_hw_blk **ds,
  793. struct sde_rm_hw_blk **pp)
  794. {
  795. struct sde_rm_hw_iter iter;
  796. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
  797. while (_sde_rm_get_hw_locked(rm, &iter)) {
  798. if (iter.blk->id == lm_cfg->pingpong) {
  799. *pp = iter.blk;
  800. break;
  801. }
  802. }
  803. if (!*pp) {
  804. SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
  805. return false;
  806. }
  807. if (RESERVED_BY_OTHER(*pp, rsvp)) {
  808. SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
  809. (*pp)->id);
  810. *dspp = NULL;
  811. *ds = NULL;
  812. return false;
  813. }
  814. pp_cfg = to_sde_hw_pingpong((*pp)->hw)->caps;
  815. if ((reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
  816. !(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
  817. SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
  818. *dspp = NULL;
  819. *ds = NULL;
  820. return false;
  821. }
  822. return true;
  823. }
  824. /**
  825. * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
  826. * proposed use case requirements, incl. hardwired dependent blocks like
  827. * pingpong, and dspp.
  828. * @rm: sde resource manager handle
  829. * @rsvp: reservation currently being created
  830. * @reqs: proposed use case requirements
  831. * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  832. * blocks connected to the lm (pp, dspp) are available and appropriate
  833. * @dspp: output parameter, dspp block attached to the layer mixer.
  834. * NULL if dspp was not available, or not matching requirements.
  835. * @pp: output parameter, pingpong block attached to the layer mixer.
  836. * NULL if dspp was not available, or not matching requirements.
  837. * @primary_lm: if non-null, this function check if lm is compatible primary_lm
  838. * as well as satisfying all other requirements
  839. * @Return: true if lm matches all requirements, false otherwise
  840. */
  841. static bool _sde_rm_check_lm_and_get_connected_blks(
  842. struct sde_rm *rm,
  843. struct sde_rm_rsvp *rsvp,
  844. struct sde_rm_requirements *reqs,
  845. struct sde_rm_hw_blk *lm,
  846. struct sde_rm_hw_blk **dspp,
  847. struct sde_rm_hw_blk **ds,
  848. struct sde_rm_hw_blk **pp,
  849. struct sde_rm_hw_blk *primary_lm)
  850. {
  851. const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
  852. const struct sde_pingpong_cfg *pp_cfg;
  853. bool ret, is_conn_primary, is_conn_secondary;
  854. u32 lm_primary_pref, lm_secondary_pref, cwb_pref;
  855. *dspp = NULL;
  856. *ds = NULL;
  857. *pp = NULL;
  858. lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
  859. lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
  860. cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
  861. is_conn_primary = (reqs->hw_res.display_type ==
  862. SDE_CONNECTOR_PRIMARY) ? true : false;
  863. is_conn_secondary = (reqs->hw_res.display_type ==
  864. SDE_CONNECTOR_SECONDARY) ? true : false;
  865. SDE_DEBUG("check lm %d: dspp %d ds %d pp %d features %d disp type %d\n",
  866. lm_cfg->id, lm_cfg->dspp, lm_cfg->ds, lm_cfg->pingpong,
  867. lm_cfg->features, (int)reqs->hw_res.display_type);
  868. /* Check if this layer mixer is a peer of the proposed primary LM */
  869. if (primary_lm) {
  870. const struct sde_lm_cfg *prim_lm_cfg =
  871. to_sde_hw_mixer(primary_lm->hw)->cap;
  872. if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
  873. SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
  874. prim_lm_cfg->id);
  875. return false;
  876. }
  877. }
  878. /* bypass rest of the checks if LM for primary display is found */
  879. if (!lm_primary_pref && !lm_secondary_pref) {
  880. /* Check lm for valid requirements */
  881. ret = _sde_rm_check_lm(rm, rsvp, reqs, lm_cfg, lm,
  882. dspp, ds, pp);
  883. if (!ret)
  884. return ret;
  885. /**
  886. * If CWB is enabled and LM is not CWB supported
  887. * then return false.
  888. */
  889. if (RM_RQ_CWB(reqs) && !cwb_pref) {
  890. SDE_DEBUG("fail: cwb supported lm not allocated\n");
  891. return false;
  892. }
  893. } else if ((!is_conn_primary && lm_primary_pref) ||
  894. (!is_conn_secondary && lm_secondary_pref)) {
  895. SDE_DEBUG(
  896. "display preference is not met. display_type: %d lm_features: %x\n",
  897. (int)reqs->hw_res.display_type, lm_cfg->features);
  898. return false;
  899. }
  900. /* Already reserved? */
  901. if (RESERVED_BY_OTHER(lm, rsvp)) {
  902. SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
  903. return false;
  904. }
  905. /* Reserve dspp */
  906. ret = _sde_rm_reserve_dspp(rm, rsvp, lm_cfg, lm, dspp);
  907. if (!ret)
  908. return ret;
  909. /* Reserve ds */
  910. ret = _sde_rm_reserve_ds(rm, rsvp, lm_cfg, lm, ds);
  911. if (!ret)
  912. return ret;
  913. /* Reserve pp */
  914. ret = _sde_rm_reserve_pp(rm, rsvp, reqs, lm_cfg, pp_cfg, lm,
  915. dspp, ds, pp);
  916. if (!ret)
  917. return ret;
  918. return true;
  919. }
  920. static int _sde_rm_reserve_lms(
  921. struct sde_rm *rm,
  922. struct sde_rm_rsvp *rsvp,
  923. struct sde_rm_requirements *reqs,
  924. u8 *_lm_ids)
  925. {
  926. struct sde_rm_hw_blk *lm[MAX_BLOCKS];
  927. struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
  928. struct sde_rm_hw_blk *ds[MAX_BLOCKS];
  929. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  930. struct sde_rm_hw_iter iter_i, iter_j;
  931. u32 lm_mask = 0;
  932. int lm_count = 0;
  933. int i, rc = 0;
  934. if (!reqs->topology->num_lm) {
  935. SDE_DEBUG("invalid number of lm: %d\n", reqs->topology->num_lm);
  936. return 0;
  937. }
  938. /* Find a primary mixer */
  939. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
  940. while (lm_count != reqs->topology->num_lm &&
  941. _sde_rm_get_hw_locked(rm, &iter_i)) {
  942. if (lm_mask & (1 << iter_i.blk->id))
  943. continue;
  944. lm[lm_count] = iter_i.blk;
  945. dspp[lm_count] = NULL;
  946. ds[lm_count] = NULL;
  947. pp[lm_count] = NULL;
  948. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  949. iter_i.blk->id,
  950. lm_count,
  951. _lm_ids ? _lm_ids[lm_count] : -1);
  952. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  953. continue;
  954. if (!_sde_rm_check_lm_and_get_connected_blks(
  955. rm, rsvp, reqs, lm[lm_count],
  956. &dspp[lm_count], &ds[lm_count],
  957. &pp[lm_count], NULL))
  958. continue;
  959. lm_mask |= (1 << iter_i.blk->id);
  960. ++lm_count;
  961. /* Return if peer is not needed */
  962. if (lm_count == reqs->topology->num_lm)
  963. break;
  964. /* Valid primary mixer found, find matching peers */
  965. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
  966. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  967. if (lm_mask & (1 << iter_j.blk->id))
  968. continue;
  969. lm[lm_count] = iter_j.blk;
  970. dspp[lm_count] = NULL;
  971. ds[lm_count] = NULL;
  972. pp[lm_count] = NULL;
  973. if (!_sde_rm_check_lm_and_get_connected_blks(
  974. rm, rsvp, reqs, iter_j.blk,
  975. &dspp[lm_count], &ds[lm_count],
  976. &pp[lm_count], iter_i.blk))
  977. continue;
  978. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  979. iter_j.blk->id,
  980. lm_count,
  981. _lm_ids ? _lm_ids[lm_count] : -1);
  982. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  983. continue;
  984. lm_mask |= (1 << iter_j.blk->id);
  985. ++lm_count;
  986. break;
  987. }
  988. /* Rollback primary LM if peer is not found */
  989. if (!iter_j.hw) {
  990. lm_mask &= ~(1 << iter_i.blk->id);
  991. --lm_count;
  992. }
  993. }
  994. if (lm_count != reqs->topology->num_lm) {
  995. SDE_DEBUG("unable to find appropriate mixers\n");
  996. return -ENAVAIL;
  997. }
  998. for (i = 0; i < lm_count; i++) {
  999. lm[i]->rsvp_nxt = rsvp;
  1000. pp[i]->rsvp_nxt = rsvp;
  1001. if (dspp[i])
  1002. dspp[i]->rsvp_nxt = rsvp;
  1003. if (ds[i])
  1004. ds[i]->rsvp_nxt = rsvp;
  1005. SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
  1006. dspp[i] ? dspp[i]->id : 0,
  1007. ds[i] ? ds[i]->id : 0);
  1008. }
  1009. if (reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
  1010. /* reserve a free PINGPONG_SLAVE block */
  1011. rc = -ENAVAIL;
  1012. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
  1013. while (_sde_rm_get_hw_locked(rm, &iter_i)) {
  1014. const struct sde_hw_pingpong *pp =
  1015. to_sde_hw_pingpong(iter_i.blk->hw);
  1016. const struct sde_pingpong_cfg *pp_cfg = pp->caps;
  1017. if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
  1018. continue;
  1019. if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
  1020. continue;
  1021. iter_i.blk->rsvp_nxt = rsvp;
  1022. rc = 0;
  1023. break;
  1024. }
  1025. }
  1026. return rc;
  1027. }
  1028. static int _sde_rm_reserve_ctls(
  1029. struct sde_rm *rm,
  1030. struct sde_rm_rsvp *rsvp,
  1031. struct sde_rm_requirements *reqs,
  1032. const struct sde_rm_topology_def *top,
  1033. u8 *_ctl_ids)
  1034. {
  1035. struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
  1036. struct sde_rm_hw_iter iter;
  1037. int i = 0;
  1038. if (!top->num_ctl) {
  1039. SDE_DEBUG("invalid number of ctl: %d\n", top->num_ctl);
  1040. return 0;
  1041. }
  1042. memset(&ctls, 0, sizeof(ctls));
  1043. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  1044. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1045. const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  1046. unsigned long features = ctl->caps->features;
  1047. bool has_split_display, has_ppsplit, primary_pref;
  1048. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1049. continue;
  1050. has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
  1051. has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
  1052. primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
  1053. SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
  1054. /*
  1055. * bypass rest feature checks on finding CTL preferred
  1056. * for primary displays.
  1057. */
  1058. if (!primary_pref && !_ctl_ids) {
  1059. if (top->needs_split_display != has_split_display)
  1060. continue;
  1061. if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
  1062. !has_ppsplit)
  1063. continue;
  1064. } else if (!(reqs->hw_res.display_type ==
  1065. SDE_CONNECTOR_PRIMARY && primary_pref) && !_ctl_ids) {
  1066. SDE_DEBUG(
  1067. "display pref not met. display_type: %d primary_pref: %d\n",
  1068. reqs->hw_res.display_type, primary_pref);
  1069. continue;
  1070. }
  1071. ctls[i] = iter.blk;
  1072. SDE_DEBUG("blk id = %d, _ctl_ids[%d] = %d\n",
  1073. iter.blk->id, i,
  1074. _ctl_ids ? _ctl_ids[i] : -1);
  1075. if (_ctl_ids && (ctls[i]->id != _ctl_ids[i]))
  1076. continue;
  1077. SDE_DEBUG("ctl %d match\n", iter.blk->id);
  1078. if (++i == top->num_ctl)
  1079. break;
  1080. }
  1081. if (i != top->num_ctl)
  1082. return -ENAVAIL;
  1083. for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
  1084. ctls[i]->rsvp_nxt = rsvp;
  1085. SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
  1086. }
  1087. return 0;
  1088. }
  1089. static bool _sde_rm_check_dsc(struct sde_rm *rm,
  1090. struct sde_rm_rsvp *rsvp,
  1091. struct sde_rm_hw_blk *dsc,
  1092. struct sde_rm_hw_blk *paired_dsc,
  1093. struct sde_rm_hw_blk *pp_blk)
  1094. {
  1095. const struct sde_dsc_cfg *dsc_cfg = to_sde_hw_dsc(dsc->hw)->caps;
  1096. /* Already reserved? */
  1097. if (RESERVED_BY_OTHER(dsc, rsvp)) {
  1098. SDE_DEBUG("dsc %d already reserved\n", dsc_cfg->id);
  1099. return false;
  1100. }
  1101. /**
  1102. * This check is required for routing even numbered DSC
  1103. * blks to any of the even numbered PP blks and odd numbered
  1104. * DSC blks to any of the odd numbered PP blks.
  1105. */
  1106. if (!pp_blk || !IS_COMPATIBLE_PP_DSC(pp_blk->id, dsc->id))
  1107. return false;
  1108. /* Check if this dsc is a peer of the proposed paired DSC */
  1109. if (paired_dsc) {
  1110. const struct sde_dsc_cfg *paired_dsc_cfg =
  1111. to_sde_hw_dsc(paired_dsc->hw)->caps;
  1112. if (!test_bit(dsc_cfg->id, paired_dsc_cfg->dsc_pair_mask)) {
  1113. SDE_DEBUG("dsc %d not peer of dsc %d\n", dsc_cfg->id,
  1114. paired_dsc_cfg->id);
  1115. return false;
  1116. }
  1117. }
  1118. return true;
  1119. }
  1120. static bool _sde_rm_check_vdc(struct sde_rm *rm,
  1121. struct sde_rm_rsvp *rsvp,
  1122. struct sde_rm_hw_blk *vdc)
  1123. {
  1124. const struct sde_vdc_cfg *vdc_cfg = to_sde_hw_vdc(vdc->hw)->caps;
  1125. /* Already reserved? */
  1126. if (RESERVED_BY_OTHER(vdc, rsvp)) {
  1127. SDE_DEBUG("vdc %d already reserved\n", vdc_cfg->id);
  1128. return false;
  1129. }
  1130. return true;
  1131. }
  1132. static void sde_rm_get_rsvp_nxt_hw_blks(
  1133. struct sde_rm *rm,
  1134. struct sde_rm_rsvp *rsvp,
  1135. int type,
  1136. struct sde_rm_hw_blk **blk_arr)
  1137. {
  1138. struct sde_rm_hw_blk *blk;
  1139. int i = 0;
  1140. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1141. if (blk->rsvp_nxt && blk->rsvp_nxt->seq ==
  1142. rsvp->seq)
  1143. blk_arr[i++] = blk;
  1144. }
  1145. }
  1146. static int _sde_rm_reserve_dsc(
  1147. struct sde_rm *rm,
  1148. struct sde_rm_rsvp *rsvp,
  1149. struct sde_rm_requirements *reqs,
  1150. u8 *_dsc_ids)
  1151. {
  1152. struct sde_rm_hw_iter iter_i, iter_j;
  1153. struct sde_rm_hw_blk *dsc[MAX_BLOCKS];
  1154. u32 reserve_mask = 0;
  1155. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1156. int alloc_count = 0;
  1157. int num_dsc_enc;
  1158. struct msm_display_dsc_info *dsc_info;
  1159. int i;
  1160. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_DSC) {
  1161. SDE_DEBUG("compression blk dsc not required\n");
  1162. return 0;
  1163. }
  1164. num_dsc_enc = reqs->topology->num_comp_enc;
  1165. dsc_info = &reqs->hw_res.comp_info->dsc_info;
  1166. if ((!num_dsc_enc) || !dsc_info) {
  1167. SDE_DEBUG("invalid topoplogy params: %d, %d\n",
  1168. num_dsc_enc, !(dsc_info == NULL));
  1169. return 0;
  1170. }
  1171. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_DSC);
  1172. sde_rm_get_rsvp_nxt_hw_blks(rm, rsvp, SDE_HW_BLK_PINGPONG, pp);
  1173. /* Find a first DSC */
  1174. while (alloc_count != num_dsc_enc &&
  1175. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1176. const struct sde_hw_dsc *hw_dsc = to_sde_hw_dsc(
  1177. iter_i.blk->hw);
  1178. unsigned long features = hw_dsc->caps->features;
  1179. bool has_422_420_support =
  1180. BIT(SDE_DSC_NATIVE_422_EN) & features;
  1181. if (reserve_mask & (1 << iter_i.blk->id))
  1182. continue;
  1183. if (_dsc_ids && (iter_i.blk->id != _dsc_ids[alloc_count]))
  1184. continue;
  1185. /* if this hw block does not support required feature */
  1186. if (!_dsc_ids && (dsc_info->config.native_422 ||
  1187. dsc_info->config.native_420) && !has_422_420_support)
  1188. continue;
  1189. if (!_sde_rm_check_dsc(rm, rsvp, iter_i.blk, NULL,
  1190. pp[alloc_count]))
  1191. continue;
  1192. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1193. iter_i.blk->id,
  1194. alloc_count,
  1195. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1196. reserve_mask |= (1 << iter_i.blk->id);
  1197. dsc[alloc_count++] = iter_i.blk;
  1198. /* Return if peer is not needed */
  1199. if (alloc_count == num_dsc_enc)
  1200. break;
  1201. /* Valid first dsc found, find matching peers */
  1202. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_DSC);
  1203. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1204. if (reserve_mask & (1 << iter_j.blk->id))
  1205. continue;
  1206. if (_dsc_ids && (iter_j.blk->id !=
  1207. _dsc_ids[alloc_count]))
  1208. continue;
  1209. if (!_sde_rm_check_dsc(rm, rsvp, iter_j.blk,
  1210. iter_i.blk, pp[alloc_count]))
  1211. continue;
  1212. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1213. iter_j.blk->id,
  1214. alloc_count,
  1215. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1216. reserve_mask |= (1 << iter_j.blk->id);
  1217. dsc[alloc_count++] = iter_j.blk;
  1218. break;
  1219. }
  1220. /* Rollback primary DSC if peer is not found */
  1221. if (!iter_j.hw) {
  1222. reserve_mask &= ~(1 << iter_i.blk->id);
  1223. --alloc_count;
  1224. }
  1225. }
  1226. if (alloc_count != num_dsc_enc) {
  1227. SDE_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
  1228. num_dsc_enc, rsvp->enc_id);
  1229. return -EINVAL;
  1230. }
  1231. for (i = 0; i < alloc_count; i++) {
  1232. if (!dsc[i])
  1233. break;
  1234. dsc[i]->rsvp_nxt = rsvp;
  1235. SDE_EVT32(dsc[i]->type, rsvp->enc_id, dsc[i]->id);
  1236. }
  1237. return 0;
  1238. }
  1239. static int _sde_rm_reserve_vdc(
  1240. struct sde_rm *rm,
  1241. struct sde_rm_rsvp *rsvp,
  1242. struct sde_rm_requirements *reqs,
  1243. const struct sde_rm_topology_def *top,
  1244. u8 *_vdc_ids)
  1245. {
  1246. struct sde_rm_hw_iter iter_i;
  1247. struct sde_rm_hw_blk *vdc[MAX_BLOCKS];
  1248. int alloc_count = 0;
  1249. int num_vdc_enc = top->num_comp_enc;
  1250. int i;
  1251. if (!top->num_comp_enc)
  1252. return 0;
  1253. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_VDC)
  1254. return 0;
  1255. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_VDC);
  1256. /* Find a VDC */
  1257. while (alloc_count != num_vdc_enc &&
  1258. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1259. memset(&vdc, 0, sizeof(vdc));
  1260. alloc_count = 0;
  1261. if (_vdc_ids && (iter_i.blk->id != _vdc_ids[alloc_count]))
  1262. continue;
  1263. if (!_sde_rm_check_vdc(rm, rsvp, iter_i.blk))
  1264. continue;
  1265. SDE_DEBUG("blk id = %d, _vdc_ids[%d] = %d\n",
  1266. iter_i.blk->id,
  1267. alloc_count,
  1268. _vdc_ids ? _vdc_ids[alloc_count] : -1);
  1269. vdc[alloc_count++] = iter_i.blk;
  1270. }
  1271. if (alloc_count != num_vdc_enc) {
  1272. SDE_ERROR("couldn't reserve %d vdc blocks for enc id %d\n",
  1273. num_vdc_enc, rsvp->enc_id);
  1274. return -EINVAL;
  1275. }
  1276. for (i = 0; i < ARRAY_SIZE(vdc); i++) {
  1277. if (!vdc[i])
  1278. break;
  1279. vdc[i]->rsvp_nxt = rsvp;
  1280. SDE_EVT32(vdc[i]->type, rsvp->enc_id, vdc[i]->id);
  1281. }
  1282. return 0;
  1283. }
  1284. static int _sde_rm_reserve_qdss(
  1285. struct sde_rm *rm,
  1286. struct sde_rm_rsvp *rsvp,
  1287. const struct sde_rm_topology_def *top,
  1288. u8 *_qdss_ids)
  1289. {
  1290. struct sde_rm_hw_iter iter;
  1291. struct msm_drm_private *priv = rm->dev->dev_private;
  1292. struct sde_kms *sde_kms;
  1293. if (!priv->kms) {
  1294. SDE_ERROR("invalid kms\n");
  1295. return -EINVAL;
  1296. }
  1297. sde_kms = to_sde_kms(priv->kms);
  1298. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_QDSS);
  1299. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1300. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1301. continue;
  1302. SDE_DEBUG("blk id = %d\n", iter.blk->id);
  1303. iter.blk->rsvp_nxt = rsvp;
  1304. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1305. return 0;
  1306. }
  1307. if (!iter.hw && sde_kms->catalog->qdss_count) {
  1308. SDE_DEBUG("couldn't reserve qdss for type %d id %d\n",
  1309. SDE_HW_BLK_QDSS, iter.blk->id);
  1310. return -ENAVAIL;
  1311. }
  1312. return 0;
  1313. }
  1314. static int _sde_rm_reserve_cdm(
  1315. struct sde_rm *rm,
  1316. struct sde_rm_rsvp *rsvp,
  1317. uint32_t id,
  1318. enum sde_hw_blk_type type)
  1319. {
  1320. struct sde_rm_hw_iter iter;
  1321. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
  1322. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1323. const struct sde_hw_cdm *cdm = to_sde_hw_cdm(iter.blk->hw);
  1324. const struct sde_cdm_cfg *caps = cdm->caps;
  1325. bool match = false;
  1326. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1327. continue;
  1328. if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
  1329. match = test_bit(id, &caps->intf_connect);
  1330. else if (type == SDE_HW_BLK_WB && id != WB_MAX)
  1331. match = test_bit(id, &caps->wb_connect);
  1332. SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
  1333. type, id, caps->intf_connect, caps->wb_connect,
  1334. match);
  1335. if (!match)
  1336. continue;
  1337. iter.blk->rsvp_nxt = rsvp;
  1338. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1339. break;
  1340. }
  1341. if (!iter.hw) {
  1342. SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
  1343. return -ENAVAIL;
  1344. }
  1345. return 0;
  1346. }
  1347. static int _sde_rm_reserve_intf_or_wb(
  1348. struct sde_rm *rm,
  1349. struct sde_rm_rsvp *rsvp,
  1350. uint32_t id,
  1351. enum sde_hw_blk_type type,
  1352. bool needs_cdm)
  1353. {
  1354. struct sde_rm_hw_iter iter;
  1355. int ret = 0;
  1356. /* Find the block entry in the rm, and note the reservation */
  1357. sde_rm_init_hw_iter(&iter, 0, type);
  1358. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1359. if (iter.blk->id != id)
  1360. continue;
  1361. if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
  1362. SDE_ERROR("type %d id %d already reserved\n", type, id);
  1363. return -ENAVAIL;
  1364. }
  1365. iter.blk->rsvp_nxt = rsvp;
  1366. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1367. break;
  1368. }
  1369. /* Shouldn't happen since wbs / intfs are fixed at probe */
  1370. if (!iter.hw) {
  1371. SDE_ERROR("couldn't find type %d id %d\n", type, id);
  1372. return -EINVAL;
  1373. }
  1374. /* Expected only one intf or wb will request cdm */
  1375. if (needs_cdm)
  1376. ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
  1377. return ret;
  1378. }
  1379. static int _sde_rm_reserve_intf_related_hw(
  1380. struct sde_rm *rm,
  1381. struct sde_rm_rsvp *rsvp,
  1382. struct sde_encoder_hw_resources *hw_res)
  1383. {
  1384. int i, ret = 0;
  1385. u32 id;
  1386. for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
  1387. if (hw_res->intfs[i] == INTF_MODE_NONE)
  1388. continue;
  1389. id = i + INTF_0;
  1390. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1391. SDE_HW_BLK_INTF, hw_res->needs_cdm);
  1392. if (ret)
  1393. return ret;
  1394. }
  1395. for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
  1396. if (hw_res->wbs[i] == INTF_MODE_NONE)
  1397. continue;
  1398. id = i + WB_0;
  1399. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1400. SDE_HW_BLK_WB, hw_res->needs_cdm);
  1401. if (ret)
  1402. return ret;
  1403. }
  1404. return ret;
  1405. }
  1406. static bool _sde_rm_is_display_in_cont_splash(struct sde_kms *sde_kms,
  1407. struct drm_encoder *enc)
  1408. {
  1409. int i;
  1410. struct sde_splash_display *splash_dpy;
  1411. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1412. splash_dpy = &sde_kms->splash_data.splash_display[i];
  1413. if (splash_dpy->encoder == enc)
  1414. return splash_dpy->cont_splash_enabled;
  1415. }
  1416. return false;
  1417. }
  1418. static int _sde_rm_make_lm_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1419. struct sde_rm_requirements *reqs,
  1420. struct sde_splash_display *splash_display)
  1421. {
  1422. int ret, i;
  1423. u8 *hw_ids = NULL;
  1424. /* Check if splash data provided lm_ids */
  1425. if (splash_display) {
  1426. hw_ids = splash_display->lm_ids;
  1427. for (i = 0; i < splash_display->lm_cnt; i++)
  1428. SDE_DEBUG("splash_display->lm_ids[%d] = %d\n",
  1429. i, splash_display->lm_ids[i]);
  1430. if (splash_display->lm_cnt != reqs->topology->num_lm)
  1431. SDE_DEBUG("Configured splash LMs != needed LM cnt\n");
  1432. }
  1433. /*
  1434. * Assign LMs and blocks whose usage is tied to them:
  1435. * DSPP & Pingpong.
  1436. */
  1437. ret = _sde_rm_reserve_lms(rm, rsvp, reqs, hw_ids);
  1438. return ret;
  1439. }
  1440. static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1441. struct sde_rm_requirements *reqs,
  1442. struct sde_splash_display *splash_display)
  1443. {
  1444. int ret, i;
  1445. u8 *hw_ids = NULL;
  1446. struct sde_rm_topology_def topology;
  1447. /* Check if splash data provided ctl_ids */
  1448. if (splash_display) {
  1449. hw_ids = splash_display->ctl_ids;
  1450. for (i = 0; i < splash_display->ctl_cnt; i++)
  1451. SDE_DEBUG("splash_display->ctl_ids[%d] = %d\n",
  1452. i, splash_display->ctl_ids[i]);
  1453. }
  1454. /*
  1455. * Do assignment preferring to give away low-resource CTLs first:
  1456. * - Check mixers without Split Display
  1457. * - Only then allow to grab from CTLs with split display capability
  1458. */
  1459. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology, hw_ids);
  1460. if (ret && !reqs->topology->needs_split_display &&
  1461. reqs->topology->num_ctl > SINGLE_CTL) {
  1462. memcpy(&topology, reqs->topology, sizeof(topology));
  1463. topology.needs_split_display = true;
  1464. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology, hw_ids);
  1465. }
  1466. return ret;
  1467. }
  1468. static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1469. struct sde_rm_requirements *reqs,
  1470. struct sde_splash_display *splash_display)
  1471. {
  1472. int i;
  1473. u8 *hw_ids = NULL;
  1474. /* Check if splash data provided dsc_ids */
  1475. if (splash_display) {
  1476. hw_ids = splash_display->dsc_ids;
  1477. if (splash_display->dsc_cnt)
  1478. reqs->hw_res.comp_info->comp_type =
  1479. MSM_DISPLAY_COMPRESSION_DSC;
  1480. for (i = 0; i < splash_display->dsc_cnt; i++)
  1481. SDE_DEBUG("splash_data.dsc_ids[%d] = %d\n",
  1482. i, splash_display->dsc_ids[i]);
  1483. }
  1484. return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
  1485. }
  1486. static int _sde_rm_make_vdc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1487. struct sde_rm_requirements *reqs,
  1488. struct sde_splash_display *splash_display)
  1489. {
  1490. int ret, i;
  1491. u8 *hw_ids = NULL;
  1492. /* Check if splash data provided vdc_ids */
  1493. if (splash_display) {
  1494. hw_ids = splash_display->vdc_ids;
  1495. for (i = 0; i < splash_display->vdc_cnt; i++)
  1496. SDE_DEBUG("splash_data.vdc_ids[%d] = %d\n",
  1497. i, splash_display->vdc_ids[i]);
  1498. }
  1499. ret = _sde_rm_reserve_vdc(rm, rsvp, reqs, reqs->topology, hw_ids);
  1500. return ret;
  1501. }
  1502. static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
  1503. struct drm_crtc_state *crtc_state,
  1504. struct drm_connector_state *conn_state,
  1505. struct sde_rm_rsvp *rsvp,
  1506. struct sde_rm_requirements *reqs)
  1507. {
  1508. struct msm_drm_private *priv;
  1509. struct sde_kms *sde_kms;
  1510. struct sde_splash_display *splash_display = NULL;
  1511. struct sde_splash_data *splash_data;
  1512. int i, ret;
  1513. priv = enc->dev->dev_private;
  1514. sde_kms = to_sde_kms(priv->kms);
  1515. splash_data = &sde_kms->splash_data;
  1516. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1517. for (i = 0; i < ARRAY_SIZE(splash_data->splash_display); i++) {
  1518. if (enc == splash_data->splash_display[i].encoder)
  1519. splash_display =
  1520. &splash_data->splash_display[i];
  1521. }
  1522. if (!splash_display) {
  1523. SDE_ERROR("rm is in cont_splash but data not found\n");
  1524. return -EINVAL;
  1525. }
  1526. }
  1527. /* Create reservation info, tag reserved blocks with it as we go */
  1528. rsvp->seq = ++rm->rsvp_next_seq;
  1529. rsvp->enc_id = enc->base.id;
  1530. rsvp->topology = reqs->topology->top_name;
  1531. list_add_tail(&rsvp->list, &rm->rsvps);
  1532. ret = _sde_rm_make_lm_rsvp(rm, rsvp, reqs, splash_display);
  1533. if (ret) {
  1534. SDE_ERROR("unable to find appropriate mixers\n");
  1535. _sde_rm_print_rsvps_by_type(rm, SDE_HW_BLK_LM);
  1536. return ret;
  1537. }
  1538. ret = _sde_rm_make_ctl_rsvp(rm, rsvp, reqs, splash_display);
  1539. if (ret) {
  1540. SDE_ERROR("unable to find appropriate CTL\n");
  1541. return ret;
  1542. }
  1543. /* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
  1544. ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
  1545. if (ret)
  1546. return ret;
  1547. ret = _sde_rm_make_dsc_rsvp(rm, rsvp, reqs, splash_display);
  1548. if (ret)
  1549. return ret;
  1550. ret = _sde_rm_make_vdc_rsvp(rm, rsvp, reqs, splash_display);
  1551. if (ret)
  1552. return ret;
  1553. ret = _sde_rm_reserve_qdss(rm, rsvp, reqs->topology, NULL);
  1554. if (ret)
  1555. return ret;
  1556. return ret;
  1557. }
  1558. /**
  1559. * _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
  1560. * and populate the connected HW blk ids in sde_splash_display
  1561. * @rm: Pointer to resource manager structure
  1562. * @ctl: Pointer to CTL hardware block
  1563. * @splash_display: Pointer to struct sde_splash_display
  1564. * return: number of active LM blocks for this CTL block
  1565. */
  1566. static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
  1567. struct sde_hw_ctl *ctl,
  1568. struct sde_splash_display *splash_display)
  1569. {
  1570. u32 lm_reg;
  1571. struct sde_rm_hw_iter iter_lm, iter_dsc;
  1572. struct sde_kms *sde_kms;
  1573. if (!rm || !ctl || !splash_display) {
  1574. SDE_ERROR("invalid input parameters\n");
  1575. return 0;
  1576. }
  1577. sde_kms = container_of(rm, struct sde_kms, rm);
  1578. sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
  1579. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1580. while (_sde_rm_get_hw_locked(rm, &iter_lm)) {
  1581. if (splash_display->lm_cnt >= MAX_DATA_PATH_PER_DSIPLAY)
  1582. break;
  1583. lm_reg = ctl->ops.read_ctl_layers(ctl, iter_lm.blk->id);
  1584. if (!lm_reg)
  1585. continue;
  1586. splash_display->lm_ids[splash_display->lm_cnt++] =
  1587. iter_lm.blk->id;
  1588. SDE_DEBUG("lm_cnt=%d lm_reg[%d]=0x%x\n", splash_display->lm_cnt,
  1589. iter_lm.blk->id - LM_0, lm_reg);
  1590. if (ctl->ops.get_staged_sspp &&
  1591. ctl->ops.get_staged_sspp(ctl, iter_lm.blk->id,
  1592. &splash_display->pipes[
  1593. splash_display->pipe_cnt], 1)) {
  1594. splash_display->pipe_cnt++;
  1595. } else if (sde_kms->splash_data.type == SDE_VM_HANDOFF) {
  1596. /* Allow VM handoff without any pipes, as it is a
  1597. * valid case to have NULL commit before the
  1598. * transition.
  1599. */
  1600. SDE_DEBUG("VM handoff with no pipes staged\n");
  1601. } else {
  1602. SDE_ERROR("no pipe detected on LM-%d\n",
  1603. iter_lm.blk->id - LM_0);
  1604. return 0;
  1605. }
  1606. }
  1607. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1608. if (ctl->ops.read_active_status &&
  1609. !(ctl->ops.read_active_status(ctl,
  1610. SDE_HW_BLK_DSC,
  1611. iter_dsc.blk->id)))
  1612. continue;
  1613. splash_display->dsc_ids[splash_display->dsc_cnt++] =
  1614. iter_dsc.blk->id;
  1615. SDE_DEBUG("CTL[%d] path, using dsc[%d]\n",
  1616. ctl->idx,
  1617. iter_dsc.blk->id - DSC_0);
  1618. }
  1619. return splash_display->lm_cnt;
  1620. }
  1621. int sde_rm_cont_splash_res_init(struct msm_drm_private *priv,
  1622. struct sde_rm *rm,
  1623. struct sde_splash_data *splash_data,
  1624. struct sde_mdss_cfg *cat)
  1625. {
  1626. struct sde_rm_hw_iter iter_c;
  1627. int index = 0, ctl_top_cnt;
  1628. struct sde_kms *sde_kms = NULL;
  1629. struct sde_hw_mdp *hw_mdp;
  1630. struct sde_splash_display *splash_display;
  1631. u8 intf_sel;
  1632. if (!priv || !rm || !cat || !splash_data) {
  1633. SDE_ERROR("invalid input parameters\n");
  1634. return -EINVAL;
  1635. }
  1636. SDE_DEBUG("mixer_count=%d, ctl_count=%d, dsc_count=%d\n",
  1637. cat->mixer_count,
  1638. cat->ctl_count,
  1639. cat->dsc_count);
  1640. ctl_top_cnt = cat->ctl_count;
  1641. if (!priv->kms) {
  1642. SDE_ERROR("invalid kms\n");
  1643. return -EINVAL;
  1644. }
  1645. sde_kms = to_sde_kms(priv->kms);
  1646. hw_mdp = sde_rm_get_mdp(rm);
  1647. sde_rm_init_hw_iter(&iter_c, 0, SDE_HW_BLK_CTL);
  1648. while (_sde_rm_get_hw_locked(rm, &iter_c)
  1649. && (index < splash_data->num_splash_displays)) {
  1650. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter_c.blk->hw);
  1651. if (!ctl->ops.get_ctl_intf) {
  1652. SDE_ERROR("get_ctl_intf not initialized\n");
  1653. return -EINVAL;
  1654. }
  1655. intf_sel = ctl->ops.get_ctl_intf(ctl);
  1656. if (intf_sel) {
  1657. splash_display = &splash_data->splash_display[index];
  1658. SDE_DEBUG("finding resources for display=%d ctl=%d\n",
  1659. index, iter_c.blk->id - CTL_0);
  1660. _sde_rm_get_hw_blk_for_cont_splash(rm,
  1661. ctl, splash_display);
  1662. splash_display->cont_splash_enabled = true;
  1663. splash_display->ctl_ids[splash_display->ctl_cnt++] =
  1664. iter_c.blk->id;
  1665. }
  1666. index++;
  1667. }
  1668. return 0;
  1669. }
  1670. static int _sde_rm_populate_requirements(
  1671. struct sde_rm *rm,
  1672. struct drm_encoder *enc,
  1673. struct drm_crtc_state *crtc_state,
  1674. struct drm_connector_state *conn_state,
  1675. struct sde_rm_requirements *reqs)
  1676. {
  1677. const struct drm_display_mode *mode = &crtc_state->mode;
  1678. int i, num_lm;
  1679. reqs->top_ctrl = sde_connector_get_property(conn_state,
  1680. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1681. sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
  1682. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++) {
  1683. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  1684. reqs->hw_res.topology)) {
  1685. reqs->topology = &rm->topology_tbl[i];
  1686. break;
  1687. }
  1688. }
  1689. if (!reqs->topology) {
  1690. SDE_ERROR("invalid topology for the display\n");
  1691. return -EINVAL;
  1692. }
  1693. /*
  1694. * select dspp HW block for all dsi displays and ds for only
  1695. * primary dsi display.
  1696. */
  1697. if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
  1698. if (!RM_RQ_DSPP(reqs))
  1699. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
  1700. if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
  1701. sde_encoder_is_primary_display(enc))
  1702. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);
  1703. }
  1704. /**
  1705. * Set the requirement for LM which has CWB support if CWB is
  1706. * found enabled.
  1707. */
  1708. if (!RM_RQ_CWB(reqs) && sde_encoder_in_clone_mode(enc)) {
  1709. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
  1710. /*
  1711. * topology selection based on conn mode is not valid for CWB
  1712. * as WB conn populates modes based on max_mixer_width check
  1713. * but primary can be using dual LMs. This topology override for
  1714. * CWB is to check number of datapath active in primary and
  1715. * allocate same number of LM/PP blocks reserved for CWB
  1716. */
  1717. reqs->topology =
  1718. &rm->topology_tbl[SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE];
  1719. num_lm = sde_crtc_get_num_datapath(crtc_state->crtc,
  1720. conn_state->connector);
  1721. if (num_lm == 1)
  1722. reqs->topology =
  1723. &rm->topology_tbl[SDE_RM_TOPOLOGY_SINGLEPIPE];
  1724. else if (num_lm == 0)
  1725. SDE_ERROR("Primary layer mixer is not set\n");
  1726. SDE_EVT32(num_lm, reqs->topology->num_lm,
  1727. reqs->topology->top_name, reqs->topology->num_ctl);
  1728. }
  1729. SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
  1730. reqs->hw_res.display_num_of_h_tiles);
  1731. SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
  1732. reqs->topology->num_lm, reqs->topology->num_ctl,
  1733. reqs->topology->top_name,
  1734. reqs->topology->needs_split_display);
  1735. SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
  1736. reqs->top_ctrl, reqs->topology->top_name,
  1737. reqs->topology->num_ctl);
  1738. return 0;
  1739. }
  1740. static struct sde_rm_rsvp *_sde_rm_get_rsvp(
  1741. struct sde_rm *rm,
  1742. struct drm_encoder *enc)
  1743. {
  1744. struct sde_rm_rsvp *i;
  1745. if (!rm || !enc) {
  1746. SDE_ERROR("invalid params\n");
  1747. return NULL;
  1748. }
  1749. if (list_empty(&rm->rsvps))
  1750. return NULL;
  1751. list_for_each_entry(i, &rm->rsvps, list)
  1752. if (i->enc_id == enc->base.id)
  1753. return i;
  1754. return NULL;
  1755. }
  1756. static struct sde_rm_rsvp *_sde_rm_get_rsvp_nxt(
  1757. struct sde_rm *rm,
  1758. struct drm_encoder *enc)
  1759. {
  1760. struct sde_rm_rsvp *i;
  1761. if (list_empty(&rm->rsvps))
  1762. return NULL;
  1763. list_for_each_entry(i, &rm->rsvps, list)
  1764. if (i->enc_id == enc->base.id)
  1765. break;
  1766. list_for_each_entry_continue(i, &rm->rsvps, list)
  1767. if (i->enc_id == enc->base.id)
  1768. return i;
  1769. return NULL;
  1770. }
  1771. static struct drm_connector *_sde_rm_get_connector(
  1772. struct drm_encoder *enc)
  1773. {
  1774. struct drm_connector *conn = NULL, *conn_search;
  1775. struct sde_connector *c_conn = NULL;
  1776. struct drm_connector_list_iter conn_iter;
  1777. drm_connector_list_iter_begin(enc->dev, &conn_iter);
  1778. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1779. c_conn = to_sde_connector(conn_search);
  1780. if (c_conn->encoder == enc) {
  1781. conn = conn_search;
  1782. break;
  1783. }
  1784. }
  1785. drm_connector_list_iter_end(&conn_iter);
  1786. return conn;
  1787. }
  1788. int sde_rm_update_topology(struct sde_rm *rm,
  1789. struct drm_connector_state *conn_state,
  1790. struct msm_display_topology *topology)
  1791. {
  1792. int i, ret = 0;
  1793. struct msm_display_topology top;
  1794. enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
  1795. if (!conn_state)
  1796. return -EINVAL;
  1797. if (topology) {
  1798. top = *topology;
  1799. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  1800. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i], top)) {
  1801. top_name = rm->topology_tbl[i].top_name;
  1802. break;
  1803. }
  1804. }
  1805. ret = msm_property_set_property(
  1806. sde_connector_get_propinfo(conn_state->connector),
  1807. sde_connector_get_property_state(conn_state),
  1808. CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
  1809. return ret;
  1810. }
  1811. bool sde_rm_topology_is_group(struct sde_rm *rm,
  1812. struct drm_crtc_state *state,
  1813. enum sde_rm_topology_group group)
  1814. {
  1815. int i, ret = 0;
  1816. struct sde_crtc_state *cstate;
  1817. struct drm_connector *conn;
  1818. struct drm_connector_state *conn_state;
  1819. struct msm_display_topology topology;
  1820. enum sde_rm_topology_name name;
  1821. if ((!rm) || (!state) || (!state->state)) {
  1822. pr_err("invalid arguments: rm:%d state:%d atomic state:%d\n",
  1823. !rm, !state, state ? (!state->state) : 0);
  1824. return false;
  1825. }
  1826. cstate = to_sde_crtc_state(state);
  1827. for (i = 0; i < cstate->num_connectors; i++) {
  1828. conn = cstate->connectors[i];
  1829. if (!conn) {
  1830. SDE_DEBUG("invalid connector\n");
  1831. continue;
  1832. }
  1833. conn_state = drm_atomic_get_new_connector_state(state->state,
  1834. conn);
  1835. if (!conn_state) {
  1836. SDE_DEBUG("%s invalid connector state\n", conn->name);
  1837. continue;
  1838. }
  1839. ret = sde_connector_state_get_topology(conn_state, &topology);
  1840. if (ret) {
  1841. SDE_DEBUG("%s invalid topology\n", conn->name);
  1842. continue;
  1843. }
  1844. name = sde_rm_get_topology_name(rm, topology);
  1845. switch (group) {
  1846. case SDE_RM_TOPOLOGY_GROUP_SINGLEPIPE:
  1847. if (TOPOLOGY_SINGLEPIPE_MODE(name))
  1848. return true;
  1849. break;
  1850. case SDE_RM_TOPOLOGY_GROUP_DUALPIPE:
  1851. if (TOPOLOGY_DUALPIPE_MODE(name))
  1852. return true;
  1853. break;
  1854. case SDE_RM_TOPOLOGY_GROUP_QUADPIPE:
  1855. if (TOPOLOGY_QUADPIPE_MODE(name))
  1856. return true;
  1857. break;
  1858. case SDE_RM_TOPOLOGY_GROUP_3DMERGE:
  1859. if (topology.num_lm > topology.num_intf &&
  1860. !topology.num_enc)
  1861. return true;
  1862. break;
  1863. case SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC:
  1864. if (topology.num_lm > topology.num_enc &&
  1865. topology.num_enc)
  1866. return true;
  1867. break;
  1868. case SDE_RM_TOPOLOGY_GROUP_DSCMERGE:
  1869. if (topology.num_lm == topology.num_enc &&
  1870. topology.num_enc)
  1871. return true;
  1872. break;
  1873. default:
  1874. SDE_ERROR("invalid topology group\n");
  1875. return false;
  1876. }
  1877. }
  1878. return false;
  1879. }
  1880. /**
  1881. * _sde_rm_release_rsvp - release resources and release a reservation
  1882. * @rm: KMS handle
  1883. * @rsvp: RSVP pointer to release and release resources for
  1884. */
  1885. static void _sde_rm_release_rsvp(
  1886. struct sde_rm *rm,
  1887. struct sde_rm_rsvp *rsvp,
  1888. struct drm_connector *conn)
  1889. {
  1890. struct sde_rm_rsvp *rsvp_c, *rsvp_n;
  1891. struct sde_rm_hw_blk *blk;
  1892. enum sde_hw_blk_type type;
  1893. if (!rsvp)
  1894. return;
  1895. SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
  1896. list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
  1897. if (rsvp == rsvp_c) {
  1898. list_del(&rsvp_c->list);
  1899. break;
  1900. }
  1901. }
  1902. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  1903. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1904. if (blk->rsvp == rsvp) {
  1905. blk->rsvp = NULL;
  1906. SDE_DEBUG("rel rsvp %d enc %d %d %d\n",
  1907. rsvp->seq, rsvp->enc_id,
  1908. blk->type, blk->id);
  1909. _sde_rm_inc_resource_info(rm,
  1910. &rm->avail_res, blk);
  1911. }
  1912. if (blk->rsvp_nxt == rsvp) {
  1913. blk->rsvp_nxt = NULL;
  1914. SDE_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
  1915. rsvp->seq, rsvp->enc_id,
  1916. blk->type, blk->id);
  1917. }
  1918. }
  1919. }
  1920. kfree(rsvp);
  1921. }
  1922. void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  1923. {
  1924. struct sde_rm_rsvp *rsvp;
  1925. struct drm_connector *conn = NULL;
  1926. struct msm_drm_private *priv;
  1927. struct sde_kms *sde_kms;
  1928. uint64_t top_ctrl = 0;
  1929. if (!rm || !enc) {
  1930. SDE_ERROR("invalid params\n");
  1931. return;
  1932. }
  1933. priv = enc->dev->dev_private;
  1934. if (!priv->kms) {
  1935. SDE_ERROR("invalid kms\n");
  1936. return;
  1937. }
  1938. sde_kms = to_sde_kms(priv->kms);
  1939. mutex_lock(&rm->rm_lock);
  1940. if (nxt)
  1941. rsvp = _sde_rm_get_rsvp_nxt(rm, enc);
  1942. else
  1943. rsvp = _sde_rm_get_rsvp(rm, enc);
  1944. if (!rsvp) {
  1945. SDE_DEBUG("failed to find rsvp for enc %d, nxt %d",
  1946. enc->base.id, nxt);
  1947. goto end;
  1948. }
  1949. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1950. _sde_rm_release_rsvp(rm, rsvp, conn);
  1951. goto end;
  1952. }
  1953. conn = _sde_rm_get_connector(enc);
  1954. if (!conn) {
  1955. SDE_EVT32(enc->base.id, 0x0, 0xffffffff);
  1956. _sde_rm_release_rsvp(rm, rsvp, conn);
  1957. SDE_DEBUG("failed to get conn for enc %d nxt %d\n",
  1958. enc->base.id, nxt);
  1959. goto end;
  1960. }
  1961. top_ctrl = sde_connector_get_property(conn->state,
  1962. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1963. SDE_EVT32(enc->base.id, conn->base.id, rsvp->seq, top_ctrl, nxt);
  1964. if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
  1965. SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
  1966. rsvp->seq, rsvp->enc_id);
  1967. } else {
  1968. SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
  1969. rsvp->enc_id);
  1970. _sde_rm_release_rsvp(rm, rsvp, conn);
  1971. }
  1972. end:
  1973. mutex_unlock(&rm->rm_lock);
  1974. }
  1975. static int _sde_rm_commit_rsvp(
  1976. struct sde_rm *rm,
  1977. struct sde_rm_rsvp *rsvp,
  1978. struct drm_connector_state *conn_state)
  1979. {
  1980. struct sde_rm_hw_blk *blk;
  1981. enum sde_hw_blk_type type;
  1982. int ret = 0;
  1983. /* Swap next rsvp to be the active */
  1984. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  1985. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1986. if (blk->rsvp_nxt && conn_state->best_encoder->base.id
  1987. == blk->rsvp_nxt->enc_id) {
  1988. blk->rsvp = blk->rsvp_nxt;
  1989. blk->rsvp_nxt = NULL;
  1990. _sde_rm_dec_resource_info(rm,
  1991. &rm->avail_res, blk);
  1992. }
  1993. }
  1994. }
  1995. if (!ret) {
  1996. SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id,
  1997. rsvp->topology);
  1998. SDE_EVT32(rsvp->enc_id, rsvp->topology);
  1999. }
  2000. return ret;
  2001. }
  2002. /* call this only after rm_mutex held */
  2003. struct sde_rm_rsvp *_sde_rm_poll_get_rsvp_nxt_locked(struct sde_rm *rm,
  2004. struct drm_encoder *enc)
  2005. {
  2006. int i;
  2007. u32 loop_count = 20;
  2008. struct sde_rm_rsvp *rsvp_nxt = NULL;
  2009. u32 sleep = RM_NXT_CLEAR_POLL_TIMEOUT_US / loop_count;
  2010. for (i = 0; i < loop_count; i++) {
  2011. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2012. if (!rsvp_nxt)
  2013. return rsvp_nxt;
  2014. mutex_unlock(&rm->rm_lock);
  2015. SDE_DEBUG("iteration i:%d sleep range:%uus to %uus\n",
  2016. i, sleep, sleep * 2);
  2017. usleep_range(sleep, sleep * 2);
  2018. mutex_lock(&rm->rm_lock);
  2019. }
  2020. /* make sure to get latest rsvp_next to avoid use after free issues */
  2021. return _sde_rm_get_rsvp_nxt(rm, enc);
  2022. }
  2023. int sde_rm_reserve(
  2024. struct sde_rm *rm,
  2025. struct drm_encoder *enc,
  2026. struct drm_crtc_state *crtc_state,
  2027. struct drm_connector_state *conn_state,
  2028. bool test_only)
  2029. {
  2030. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  2031. struct sde_rm_requirements reqs = {0,};
  2032. struct msm_drm_private *priv;
  2033. struct sde_kms *sde_kms;
  2034. struct msm_compression_info *comp_info;
  2035. int ret;
  2036. if (!rm || !enc || !crtc_state || !conn_state) {
  2037. SDE_ERROR("invalid arguments\n");
  2038. return -EINVAL;
  2039. }
  2040. if (!enc->dev || !enc->dev->dev_private) {
  2041. SDE_ERROR("drm device invalid\n");
  2042. return -EINVAL;
  2043. }
  2044. priv = enc->dev->dev_private;
  2045. if (!priv->kms) {
  2046. SDE_ERROR("invalid kms\n");
  2047. return -EINVAL;
  2048. }
  2049. sde_kms = to_sde_kms(priv->kms);
  2050. /* Check if this is just a page-flip */
  2051. if (!_sde_rm_is_display_in_cont_splash(sde_kms, enc) &&
  2052. !drm_atomic_crtc_needs_modeset(crtc_state))
  2053. return 0;
  2054. comp_info = kzalloc(sizeof(*comp_info), GFP_KERNEL);
  2055. if (!comp_info)
  2056. return -ENOMEM;
  2057. SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
  2058. conn_state->connector->base.id, enc->base.id,
  2059. crtc_state->crtc->base.id, test_only);
  2060. SDE_EVT32(enc->base.id, conn_state->connector->base.id);
  2061. mutex_lock(&rm->rm_lock);
  2062. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
  2063. rsvp_cur = _sde_rm_get_rsvp(rm, enc);
  2064. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2065. /*
  2066. * RM currently relies on rsvp_nxt assigned to the hw blocks to
  2067. * commit rsvps. This rsvp_nxt can be cleared by a back to back
  2068. * check_only commit with modeset when its predecessor atomic
  2069. * commit is delayed / not committed the reservation yet.
  2070. * Poll for rsvp_nxt clear, allow the check_only commit if rsvp_nxt
  2071. * gets cleared and bailout if it does not get cleared before timeout.
  2072. */
  2073. if (test_only && rsvp_cur && rsvp_nxt) {
  2074. rsvp_nxt = _sde_rm_poll_get_rsvp_nxt_locked(rm, enc);
  2075. if (rsvp_nxt) {
  2076. SDE_ERROR("poll timeout cur %d nxt %d enc %d\n",
  2077. rsvp_cur->seq, rsvp_nxt->seq, enc->base.id);
  2078. ret = -EINVAL;
  2079. goto end;
  2080. }
  2081. }
  2082. if (!test_only && rsvp_nxt)
  2083. goto commit_rsvp;
  2084. reqs.hw_res.comp_info = comp_info;
  2085. ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
  2086. conn_state, &reqs);
  2087. if (ret) {
  2088. SDE_ERROR("failed to populate hw requirements\n");
  2089. goto end;
  2090. }
  2091. /*
  2092. * We only support one active reservation per-hw-block. But to implement
  2093. * transactional semantics for test-only, and for allowing failure while
  2094. * modifying your existing reservation, over the course of this
  2095. * function we can have two reservations:
  2096. * Current: Existing reservation
  2097. * Next: Proposed reservation. The proposed reservation may fail, or may
  2098. * be discarded if in test-only mode.
  2099. * If reservation is successful, and we're not in test-only, then we
  2100. * replace the current with the next.
  2101. */
  2102. rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
  2103. if (!rsvp_nxt) {
  2104. ret = -ENOMEM;
  2105. goto end;
  2106. }
  2107. /*
  2108. * User can request that we clear out any reservation during the
  2109. * atomic_check phase by using this CLEAR bit
  2110. */
  2111. if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
  2112. SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
  2113. rsvp_cur->seq, rsvp_cur->enc_id);
  2114. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2115. rsvp_cur = NULL;
  2116. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
  2117. }
  2118. /* Check the proposed reservation, store it in hw's "next" field */
  2119. ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
  2120. rsvp_nxt, &reqs);
  2121. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
  2122. if (ret) {
  2123. SDE_ERROR("failed to reserve hw resources: %d, test_only %d\n",
  2124. ret, test_only);
  2125. _sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
  2126. goto end;
  2127. } else if (test_only && !RM_RQ_LOCK(&reqs)) {
  2128. /*
  2129. * Normally, if test_only, test the reservation and then undo
  2130. * However, if the user requests LOCK, then keep the reservation
  2131. * made during the atomic_check phase.
  2132. */
  2133. SDE_DEBUG("test_only: rsvp[s%de%d]\n",
  2134. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2135. goto end;
  2136. } else {
  2137. if (test_only && RM_RQ_LOCK(&reqs))
  2138. SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
  2139. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2140. }
  2141. commit_rsvp:
  2142. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2143. ret = _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
  2144. end:
  2145. kfree(comp_info);
  2146. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
  2147. mutex_unlock(&rm->rm_lock);
  2148. return ret;
  2149. }
  2150. int sde_rm_ext_blk_create_reserve(struct sde_rm *rm,
  2151. struct sde_hw_blk *hw, struct drm_encoder *enc)
  2152. {
  2153. struct sde_rm_hw_blk *blk;
  2154. struct sde_rm_rsvp *rsvp;
  2155. int ret = 0;
  2156. if (!rm || !hw || !enc) {
  2157. SDE_ERROR("invalid parameters\n");
  2158. return -EINVAL;
  2159. }
  2160. if (hw->type >= SDE_HW_BLK_MAX) {
  2161. SDE_ERROR("invalid HW type\n");
  2162. return -EINVAL;
  2163. }
  2164. mutex_lock(&rm->rm_lock);
  2165. rsvp = _sde_rm_get_rsvp(rm, enc);
  2166. if (!rsvp) {
  2167. rsvp = kzalloc(sizeof(*rsvp), GFP_KERNEL);
  2168. if (!rsvp) {
  2169. ret = -ENOMEM;
  2170. goto end;
  2171. }
  2172. rsvp->seq = ++rm->rsvp_next_seq;
  2173. rsvp->enc_id = enc->base.id;
  2174. list_add_tail(&rsvp->list, &rm->rsvps);
  2175. SDE_DEBUG("create rsvp %d for enc %d\n",
  2176. rsvp->seq, rsvp->enc_id);
  2177. }
  2178. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  2179. if (!blk) {
  2180. ret = -ENOMEM;
  2181. goto end;
  2182. }
  2183. blk->type = hw->type;
  2184. blk->id = hw->id;
  2185. blk->hw = hw;
  2186. blk->rsvp = rsvp;
  2187. list_add_tail(&blk->list, &rm->hw_blks[hw->type]);
  2188. SDE_DEBUG("create blk %d %d for rsvp %d enc %d\n", blk->type, blk->id,
  2189. rsvp->seq, rsvp->enc_id);
  2190. end:
  2191. mutex_unlock(&rm->rm_lock);
  2192. return ret;
  2193. }
  2194. int sde_rm_ext_blk_destroy(struct sde_rm *rm,
  2195. struct drm_encoder *enc)
  2196. {
  2197. struct sde_rm_hw_blk *blk = NULL, *p;
  2198. struct sde_rm_rsvp *rsvp;
  2199. enum sde_hw_blk_type type;
  2200. int ret = 0;
  2201. if (!rm || !enc) {
  2202. SDE_ERROR("invalid parameters\n");
  2203. return -EINVAL;
  2204. }
  2205. mutex_lock(&rm->rm_lock);
  2206. rsvp = _sde_rm_get_rsvp(rm, enc);
  2207. if (!rsvp) {
  2208. ret = -ENOENT;
  2209. SDE_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
  2210. goto end;
  2211. }
  2212. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2213. list_for_each_entry_safe(blk, p, &rm->hw_blks[type], list) {
  2214. if (blk->rsvp == rsvp) {
  2215. list_del(&blk->list);
  2216. SDE_DEBUG("del blk %d %d from rsvp %d enc %d\n",
  2217. blk->type, blk->id,
  2218. rsvp->seq, rsvp->enc_id);
  2219. kfree(blk);
  2220. }
  2221. }
  2222. }
  2223. SDE_DEBUG("del rsvp %d\n", rsvp->seq);
  2224. list_del(&rsvp->list);
  2225. kfree(rsvp);
  2226. end:
  2227. mutex_unlock(&rm->rm_lock);
  2228. return ret;
  2229. }